/*
** ###################################################################
**     Processors:          MIMX8UD7CVP08_dsp1
**                          MIMX8UD7DVK08_dsp1
**                          MIMX8UD7DVP08_dsp1
**
**     Compiler:            Xtensa Compiler
**     Reference manual:    IMX8ULPRM, Rev. D, December. 2022
**     Version:             rev. 5.0, 2023-04-27
**     Build:               b240228
**
**     Abstract:
**         Peripheral Access Layer for MIMX8UD7_dsp1
**
**     Copyright 1997-2016 Freescale Semiconductor, Inc.
**     Copyright 2016-2024 NXP
**     SPDX-License-Identifier: BSD-3-Clause
**
**     http:                 www.nxp.com
**     mail:                 support@nxp.com
**
**     Revisions:
**     - rev. 1.0 (2020-05-25)
**         Initial version.
**     - rev. 2.0 (2020-09-18)
**         Base on rev A RM
**     - rev. 3.0 (2021-01-20)
**         Base on rev A.1 RM
**     - rev. 4.0 (2021-07-05)
**         Base on rev B RM
**     - rev. 5.0 (2023-04-27)
**         Base on rev D RM
**
** ###################################################################
*/

/*!
 * @file MIMX8UD7_dsp1.h
 * @version 5.0
 * @date 2023-04-27
 * @brief Peripheral Access Layer for MIMX8UD7_dsp1
 *
 * Peripheral Access Layer for MIMX8UD7_dsp1
 */

#if !defined(MIMX8UD7_DSP1_H_)
#define MIMX8UD7_DSP1_H_                         /**< Symbol preventing repeated inclusion */

/** Memory map major version (memory maps with equal major version number are
 * compatible) */
#define MCU_MEM_MAP_VERSION 0x0500U
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0000U

/* ----------------------------------------------------------------------------
   --
   ---------------------------------------------------------------------------- */

/* IO definitions (access restrictions to peripheral registers) */
/**
    \defgroup CMSIS_glob_defs CMSIS Global Defines
    <strong>IO Type Qualifiers</strong> are used
    \li to specify the access to peripheral variables.
    \li for automatic generation of peripheral register debug information.
*/
#define     __I     volatile const       /*!< Defines 'read only' permissions */
#define     __O     volatile             /*!< Defines 'write only' permissions */
#define     __IO    volatile             /*!< Defines 'read / write' permissions */

/* following defines should be used for structure members */
#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */

#define __STATIC_INLINE static inline

#define __BKPT(value) do {} while(0)
#define __NOP() do {} while(0)

#include "system_MIMX8UD7_dsp1.h"     /* Device specific configuration file */



/* ----------------------------------------------------------------------------
   -- Interrupt vector numbers
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
 * @{
 */

/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 32                 /**< Number of interrupts in the Vector table */

typedef enum IRQn {
  /* Auxiliary constants */
  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */

  /* Core interrupts */
  NonMaskableInt_IRQn          = 0,                /**< SysIRQ, Non Maskable Interrupt */
  Software_IRQn                = 1,                /**< Software triggered Interrupt */
  RtosTimer0_IRQn              = 2,                /**< Internal RTOS Timer0 Interrupt */
  RtosTimer1_IRQn              = 3,                /**< Internal RTOS Timer1 Interrupt */
  Profiling_IRQn               = 4,                /**< Profiling Interrupt */

  /* Device specific interrupts */
  DMA2_0_IRQn                  = 6,                /**< DMA2 Channel 0 Error or Transfer Complete */
  DMA2_1_IRQn                  = 7,                /**< DMA2 Channel 1 Error or Transfer Complete */
  DMA2_2_IRQn                  = 8,                /**< DMA2 Channel 2 Error or Transfer Complete */
  DMA2_3_IRQn                  = 9,                /**< DMA2 Channel 3 Error or Transfer Complete */
  DMA2_4_IRQn                  = 10,               /**< DMA2 Channel 4 Error or Transfer Complete */
  DMA2_5_IRQn                  = 11,               /**< DMA2 Channel 5 Error or Transfer Complete */
  DMA2_6_IRQn                  = 12,               /**< DMA2 Channel 6 Error or Transfer Complete */
  DMA2_7_IRQn                  = 13,               /**< DMA2 Channel 7 Error or Transfer Complete */
  MU2_B_IRQn                   = 14,               /**< Messaging Unit 2 - Side B (to communicate with M33) */
  MU3_B_IRQn                   = 15,               /**< Messaging Unit 3 - Side B (to communicate with M33) */
  WDOG5_IRQn                   = 16,               /**< Watchdog 5 Interrupt */
  TPM8_IRQn                    = 17,               /**< Timer PWM module 8 */
  SAI0_IRQn                    = 18,               /**< Serial Audio Interface 0 */
  SAI1_IRQn                    = 19,               /**< Serial Audio Interface 1 */
  SAI4_IRQn                    = 22,               /**< Serial Audio Interface 4 */
  SAI5_IRQn                    = 23,               /**< Serial Audio Interface 5 */
  SAI6_IRQn                    = 24,               /**< Serial Audio Interface 6 */
  SAI7_IRQn                    = 25,               /**< Serial Audio Interface 7 */
  SPDIF_IRQn                   = 26,               /**< Sony/Phillips Digital Interface */
  GPIOA_IRQn                   = 27,               /**< General Purpose Input/Output A interrupt */
  GPIOB_IRQn                   = 28,               /**< General Purpose Input/Output B interrupt */
  GPIOD_IRQn                   = 29,               /**< General Purpose Input/Output D interrupt */
  GPIOE_IRQn                   = 30,               /**< General Purpose Input/Output E interrupt */
  GPIOF_IRQn                   = 31                /**< General Purpose Input/Output F interrupt */
} IRQn_Type;

/*!
 * @}
 */ /* end of group Interrupt_vector_numbers */


/* ----------------------------------------------------------------------------
   -- Mapping Information
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Mapping_Information Mapping Information
 * @{
 */

/** Mapping Information */
/*!
 * @addtogroup edma0_request
 * @{ */

/*******************************************************************************
 * Definitions
*******************************************************************************/

/*!
 * @brief Enumeration for the DMA0 hardware request
 *
 * Defines the enumeration for the DMA0 hardware request collections.
 */
typedef enum _dma0_request_source
{
    kDmaRequestMux0Disable          = 0|0x100U,    /**< Channel disabled */
    kDmaRequestMux0WUU0             = 1|0x100U,    /**< Wake up event */
    kDmaRequestMux0FlexSPI0Rx       = 2|0x100U,    /**< FlexSPI0 Receive request */
    kDmaRequestMux0FlexSPI0Tx       = 3|0x100U,    /**< FlexSPI0 Transmit request */
    kDmaRequestMux0FlexSPI1Rx       = 4|0x100U,    /**< FlexSPI1 Receive request */
    kDmaRequestMux0FlexSPI1Tx       = 5|0x100U,    /**< FlexSPI1 Transmit request */
    kDmaRequestMux0FlexSPI2Rx       = 6|0x100U,    /**< FlexSPI2 Receive request */
    kDmaRequestMux0FlexSPI2Tx       = 7|0x100U,    /**< FlexSPI2 Transmit request */
    kDmaRequestMux0SNT              = 8|0x100U,    /**< SNT Data request */
    kDmaRequestMux0LPTMR0           = 9|0x100U,    /**< Low Power Timer 0 */
    kDmaRequestMux0LPTMR1           = 10|0x100U,   /**< Low Power Timer 1 */
    kDmaRequestMux0TPM0Channel0     = 13|0x100U,   /**< TPM0 Channel 0 */
    kDmaRequestMux0TPM0Channel1     = 14|0x100U,   /**< TPM0 Channel 1 */
    kDmaRequestMux0TPM0Channel2     = 15|0x100U,   /**< TPM0 Channel 2 */
    kDmaRequestMux0TPM0Channel3     = 16|0x100U,   /**< TPM0 Channel 3 */
    kDmaRequestMux0TPM0Channel4     = 17|0x100U,   /**< TPM0 Channel 4 */
    kDmaRequestMux0TPM0Channel5     = 18|0x100U,   /**< TPM0 Channel 5 */
    kDmaRequestMux0TPM0Overflow     = 19|0x100U,   /**< TPM0 Overflow */
    kDmaRequestMux0TPM1Channel0     = 20|0x100U,   /**< TPM1 Channel 0 */
    kDmaRequestMux0TPM1Channel1     = 21|0x100U,   /**< TPM1 Channel 1 */
    kDmaRequestMux0TPM1Overflow     = 22|0x100U,   /**< TPM1 Overflow */
    kDmaRequestMux0TPM2Channel0     = 23|0x100U,   /**< TPM2 Channel 0 */
    kDmaRequestMux0TPM2Channel1     = 24|0x100U,   /**< TPM2 Channel 1 */
    kDmaRequestMux0TPM2Overflow     = 25|0x100U,   /**< TPM2 Overflow */
    kDmaRequestMux0TPM3Channel0     = 26|0x100U,   /**< TPM3 Channel 0 */
    kDmaRequestMux0TPM3Channel1     = 27|0x100U,   /**< TPM3 Channel 1 */
    kDmaRequestMux0TPM3Channel2     = 28|0x100U,   /**< TPM3 Channel 2 */
    kDmaRequestMux0TPM3Channel3     = 29|0x100U,   /**< TPM3 Channel 3 */
    kDmaRequestMux0TPM3Channel4     = 30|0x100U,   /**< TPM3 Channel 4 */
    kDmaRequestMux0TPM3Channel5     = 31|0x100U,   /**< TPM3 Channel 5 */
    kDmaRequestMux0TPM3Overflow     = 32|0x100U,   /**< TPM3 Overflow */
    kDmaRequestMux0CAN              = 40|0x100U,   /**< CAN DMA request */
    kDmaRequestMux0FlexIO0Shifter0  = 41|0x100U,   /**< FlexIO0 Shifter 0 */
    kDmaRequestMux0FlexIO0Shifter1  = 42|0x100U,   /**< FlexIO0 Shifter 1 */
    kDmaRequestMux0FlexIO0Shifter2  = 43|0x100U,   /**< FlexIO0 Shifter 2 */
    kDmaRequestMux0FlexIO0Shifter3  = 44|0x100U,   /**< FlexIO0 Shifter 3 */
    kDmaRequestMux0FlexIO0Shifter4  = 45|0x100U,   /**< FlexIO0 Shifter 4 */
    kDmaRequestMux0FlexIO0Shifter5  = 46|0x100U,   /**< FlexIO0 Shifter 5 */
    kDmaRequestMux0FlexIO0Shifter6  = 47|0x100U,   /**< FlexIO0 Shifter 6 */
    kDmaRequestMux0FlexIO0Shifter7  = 48|0x100U,   /**< FlexIO0 Shifter 7 */
    kDmaRequestMux0LPI2C0Rx         = 49|0x100U,   /**< LPI2C0 Master/Slave Receive */
    kDmaRequestMux0LPI2C0Tx         = 50|0x100U,   /**< LPI2C0 Master/Slave Transmit */
    kDmaRequestMux0LPI2C1Rx         = 51|0x100U,   /**< LPI2C1 Master/Slave Receive */
    kDmaRequestMux0LPI2C1Tx         = 52|0x100U,   /**< LPI2C1 Master/Slave Transmit */
    kDmaRequestMux0LPI2C2Rx         = 53|0x100U,   /**< LPI2C2 Master/Slave Receive */
    kDmaRequestMux0LPI2C2Tx         = 54|0x100U,   /**< LPI2C2 Master/Slave Transmit */
    kDmaRequestMux0LPI2C3Rx         = 55|0x100U,   /**< LPI2C3 Master/Slave Receive */
    kDmaRequestMux0LPI2C3Tx         = 56|0x100U,   /**< LPI2C3 Master/Slave Transmit */
    kDmaRequestMux0I3C0Rx           = 57|0x100U,   /**< I3C0 Master/Slave Receive */
    kDmaRequestMux0I3C0Tx           = 58|0x100U,   /**< I3C0 Master/Slave Transmit */
    kDmaRequestMux0I3C1Rx           = 59|0x100U,   /**< I3C1 Master/Slave Receive */
    kDmaRequestMux0I3C1Tx           = 60|0x100U,   /**< I3C1 Master/Slave Receive */
    kDmaRequestMux0LPSPI0Rx         = 61|0x100U,   /**< LPSPI0 Receive */
    kDmaRequestMux0LPSPI0Tx         = 62|0x100U,   /**< LPSPI0 Transmit */
    kDmaRequestMux0LPSPI1Rx         = 63|0x100U,   /**< LPSPI1 Receive */
    kDmaRequestMux0LPSPI1Tx         = 64|0x100U,   /**< LPSPI1 Transmit */
    kDmaRequestMux0LPSPI2Rx         = 65|0x100U,   /**< LPSPI2 Receive */
    kDmaRequestMux0LPSPI2Tx         = 66|0x100U,   /**< LPSPI2 Transmit */
    kDmaRequestMux0LPSPI3Rx         = 67|0x100U,   /**< LPSPI3 Receive */
    kDmaRequestMux0LPSPI3Tx         = 68|0x100U,   /**< LPSPI3 Transmit */
    kDmaRequestMux0LPUART0Rx        = 69|0x100U,   /**< LPUART0 Receive */
    kDmaRequestMux0LPUART0Tx        = 70|0x100U,   /**< LPUART0 Transmit */
    kDmaRequestMux0LPUART1Rx        = 71|0x100U,   /**< LPUART1 Receive */
    kDmaRequestMux0LPUART1Tx        = 72|0x100U,   /**< LPUART1 Transmit */
    kDmaRequestMux0LPUART2Rx        = 73|0x100U,   /**< LPUART2 Receive */
    kDmaRequestMux0LPUART2Tx        = 74|0x100U,   /**< LPUART2 Transmit */
    kDmaRequestMux0LPUART3Rx        = 75|0x100U,   /**< LPUART3 Receive */
    kDmaRequestMux0LPUART3Tx        = 76|0x100U,   /**< LPUART3 Transmit */
    kDmaRequestMux0SAI0Rx           = 77|0x100U,   /**< SAI0 Receive */
    kDmaRequestMux0SAI0Tx           = 78|0x100U,   /**< SAI0 Transmit */
    kDmaRequestMux0SAI1Rx           = 79|0x100U,   /**< SAI1 Receive */
    kDmaRequestMux0SAI1Tx           = 80|0x100U,   /**< SAI1 Transmit */
    kDmaRequestMux0SAI2Rx           = 81|0x100U,   /**< SAI2 Receive */
    kDmaRequestMux0SAI2Tx           = 82|0x100U,   /**< SAI2 Transmit */
    kDmaRequestMux0SAI3Rx           = 83|0x100U,   /**< SAI3 Receive */
    kDmaRequestMux0SAI3Tx           = 84|0x100U,   /**< SAI3 Transmit */
    kDmaRequestMux0MICFIL           = 91|0x100U,   /**< MICFIL FIFO Request */
    kDmaRequestMux0GPIOAEvent2      = 92|0x100U,   /**< GPIOA Pin event request 2 */
    kDmaRequestMux0GPIOAEvent3      = 93|0x100U,   /**< GPIOA Pin event request 3 */
    kDmaRequestMux0GPIOBEvent2      = 94|0x100U,   /**< GPIOB Pin event request 2 */
    kDmaRequestMux0GPIOBEvent3      = 95|0x100U,   /**< GPIOB Pin event request 3 */
    kDmaRequestMux0GPIOCEvent2      = 96|0x100U,   /**< GPIOC Pin event request 2 */
    kDmaRequestMux0GPIOCEvent3      = 97|0x100U,   /**< GPIOC Pin event request 3 */
    kDmaRequestMux0ADC0             = 104|0x100U,  /**< ADC0 Conversion Complete */
    kDmaRequestMux0ADC1             = 105|0x100U,  /**< ADC1 Conversion Complete */
    kDmaRequestMux0CMP0             = 106|0x100U,  /**< CMP0 Comparison Event */
    kDmaRequestMux0CMP1             = 107|0x100U,  /**< CMP1 Comparison Event */
    kDmaRequestMux0DAC0             = 108|0x100U,  /**< DAC0 Request */
    kDmaRequestMux0DAC1             = 109|0x100U,  /**< DAC1 Request */
} dma0_request_source_t;

/* @} */

/*!
 * @addtogroup edma1_request
 * @{ */

/*******************************************************************************
 * Definitions
*******************************************************************************/

/*!
 * @brief Enumeration for the DMA1 hardware request
 *
 * Defines the enumeration for the DMA1 hardware request collections.
 */
typedef enum _dma1_request_source
{
    kDmaRequestMux1Disable          = 0|0x200U,    /**< Channel disabled */
    kDmaRequestMux1WUU1             = 1|0x200U,    /**< Wake up event */
    kDmaRequestMux1FlexSPI0Rx       = 2|0x200U,    /**< FlexSPI0 Receive request */
    kDmaRequestMux1FlexSPI0Tx       = 3|0x200U,    /**< FlexSPI0 Transmit request */
    kDmaRequestMux1FlexSPI1Rx       = 4|0x200U,    /**< FlexSPI1 Receive request */
    kDmaRequestMux1FlexSPI1Tx       = 5|0x200U,    /**< FlexSPI1 Transmit request */
    kDmaRequestMux1FlexSPI2Rx       = 6|0x200U,    /**< FlexSPI2 Receive request */
    kDmaRequestMux1FlexSPI2Tx       = 7|0x200U,    /**< FlexSPI2 Transmit request */
    kDmaRequestMux1SNT              = 8|0x200U,    /**< SNT Data request */
    kDmaRequestMux1TPM4Channel0     = 9|0x200U,    /**< TPM4 Channel 0 */
    kDmaRequestMux1TPM4Channel1     = 10|0x200U,   /**< TPM4 Channel 1 */
    kDmaRequestMux1TPM4Channel2     = 11|0x200U,   /**< TPM4 Channel 2 */
    kDmaRequestMux1TPM4Channel3     = 12|0x200U,   /**< TPM4 Channel 3 */
    kDmaRequestMux1TPM4Channel4     = 13|0x200U,   /**< TPM4 Channel 4 */
    kDmaRequestMux1TPM4Channel5     = 14|0x200U,   /**< TPM4 Channel 5 */
    kDmaRequestMux1TPM4Overflow     = 15|0x200U,   /**< TPM4 Overflow */
    kDmaRequestMux1TPM5Channel0     = 16|0x200U,   /**< TPM5 Channel 0 */
    kDmaRequestMux1TPM5Channel1     = 17|0x200U,   /**< TPM5 Channel 1 */
    kDmaRequestMux1TPM5Overflow     = 18|0x200U,   /**< TPM5 Overflow */
    kDmaRequestMux1TPM6Channel0     = 19|0x200U,   /**< TPM6 Channel 0 */
    kDmaRequestMux1TPM6Channel1     = 20|0x200U,   /**< TPM6 Channel 1 */
    kDmaRequestMux1TPM6Overflow     = 21|0x200U,   /**< TPM6 Overflow */
    kDmaRequestMux1TPM7Channel0     = 22|0x200U,   /**< TPM7 Channel 0 */
    kDmaRequestMux1TPM7Channel1     = 23|0x200U,   /**< TPM7 Channel 1 */
    kDmaRequestMux1TPM7Channel2     = 24|0x200U,   /**< TPM7 Channel 2 */
    kDmaRequestMux1TPM7Channel3     = 25|0x200U,   /**< TPM7 Channel 3 */
    kDmaRequestMux1TPM7Channel4     = 26|0x200U,   /**< TPM7 Channel 4 */
    kDmaRequestMux1TPM7Channel5     = 27|0x200U,   /**< TPM7 Channel 5 */
    kDmaRequestMux1TPM7Overflow     = 28|0x200U,   /**< TPM7 Overflow */
    kDmaRequestMux1FlexIO1Shifter0  = 37|0x200U,   /**< FlexIO1 Shifter 0 */
    kDmaRequestMux1FlexIO1Shifter1  = 38|0x200U,   /**< FlexIO1 Shifter 1 */
    kDmaRequestMux1FlexIO1Shifter2  = 39|0x200U,   /**< FlexIO1 Shifter 2 */
    kDmaRequestMux1FlexIO1Shifter3  = 40|0x200U,   /**< FlexIO1 Shifter 3 */
    kDmaRequestMux1FlexIO1Shifter4  = 41|0x200U,   /**< FlexIO1 Shifter 4 */
    kDmaRequestMux1FlexIO1Shifter5  = 42|0x200U,   /**< FlexIO1 Shifter 5 */
    kDmaRequestMux1FlexIO1Shifter6  = 43|0x200U,   /**< FlexIO1 Shifter 6 */
    kDmaRequestMux1FlexIO1Shifter7  = 44|0x200U,   /**< FlexIO1 Shifter 7 */
    kDmaRequestMux1LPI2C4Rx         = 45|0x200U,   /**< LPI2C4 Master/Slave Receive */
    kDmaRequestMux1LPI2C4Tx         = 46|0x200U,   /**< LPI2C4 Master/Slave Transmit */
    kDmaRequestMux1LPI2C5Rx         = 47|0x200U,   /**< LPI2C5 Master/Slave Receive */
    kDmaRequestMux1LPI2C5Tx         = 48|0x200U,   /**< LPI2C5 Master/Slave Transmit */
    kDmaRequestMux1LPI2C6Rx         = 49|0x200U,   /**< LPI2C6 Master/Slave Receive */
    kDmaRequestMux1LPI2C6Tx         = 50|0x200U,   /**< LPI2C6 Master/Slave Transmit */
    kDmaRequestMux1LPI2C7Rx         = 51|0x200U,   /**< LPI2C7 Master/Slave Receive */
    kDmaRequestMux1LPI2C7Tx         = 52|0x200U,   /**< LPI2C7 Master/Slave Transmit */
    kDmaRequestMux1I3C2Rx           = 53|0x200U,   /**< I3C2 Master/Slave Receive */
    kDmaRequestMux1I3C2Tx           = 54|0x200U,   /**< I3C2 Master/Slave Transmit */
    kDmaRequestMux1LPUART4Rx        = 55|0x200U,   /**< LPUART4 Receive */
    kDmaRequestMux1LPUART4Tx        = 56|0x200U,   /**< LPUART4 Transmit */
    kDmaRequestMux1LPUART5Rx        = 57|0x200U,   /**< LPUART5 Receive */
    kDmaRequestMux1LPUART5Tx        = 58|0x200U,   /**< LPUART5 Transmit */
    kDmaRequestMux1LPUART6Rx        = 59|0x200U,   /**< LPUART6 Receive */
    kDmaRequestMux1LPUART6Tx        = 60|0x200U,   /**< LPUART6 Transmit */
    kDmaRequestMux1LPUART7Rx        = 61|0x200U,   /**< LPUART7 Receive */
    kDmaRequestMux1LPUART7Tx        = 62|0x200U,   /**< LPUART7 Transmit */
    kDmaRequestMux1LPSPI4Rx         = 63|0x200U,   /**< LPSPI4 Receive */
    kDmaRequestMux1LPSPI4Tx         = 64|0x200U,   /**< LPSPI4 Transmit */
    kDmaRequestMux1LPSPI5Rx         = 65|0x200U,   /**< LPSPI5 Receive */
    kDmaRequestMux1LPSPI5Tx         = 66|0x200U,   /**< LPSPI5 Transmit */
    kDmaRequestMux1SAI4Rx           = 67|0x200U,   /**< SAI4 Receive */
    kDmaRequestMux1SAI4Tx           = 68|0x200U,   /**< SAI4 Transmit */
    kDmaRequestMux1SAI5Rx           = 69|0x200U,   /**< SAI5 Receive */
    kDmaRequestMux1SAI5Tx           = 70|0x200U,   /**< SAI5 Transmit */
    kDmaRequestMux1GPIOEEvent0      = 85|0x200U,   /**< GPIOE Pin event request 0 */
    kDmaRequestMux1GPIOEEvent1      = 86|0x200U,   /**< GPIOE Pin event request 1 */
    kDmaRequestMux1GPIOFEvent0      = 87|0x200U,   /**< GPIOF Pin event request 0 */
    kDmaRequestMux1GPIOFEvent1      = 88|0x200U,   /**< GPIOF Pin event request 1 */
    kDmaRequestMux1ENETTimer0       = 89|0x200U,   /**< ENET Timer 0 */
    kDmaRequestMux1ENETTimer1       = 90|0x200U,   /**< ENET Timer 1 */
    kDmaRequestMux1ENETTimer2       = 91|0x200U,   /**< ENET Timer 2 */
    kDmaRequestMux1ENETTimer3       = 92|0x200U,   /**< ENET Timer 3 */
} dma1_request_source_t;

/* @} */

/*!
 * @addtogroup edma2_request
 * @{ */

/*******************************************************************************
 * Definitions
*******************************************************************************/

/*!
 * @brief Enumeration for the DMA2 hardware request
 *
 * Defines the enumeration for the DMA2 hardware request collections.
 */
typedef enum _dma2_request_source
{
    kDmaRequestMux2Disable          = 0|0x300U,    /**< Channel disabled */
    kDmaRequestMux2TPM8Channel0     = 1|0x300U,    /**< TPM8 Channel 0 */
    kDmaRequestMux2TPM8Channel1     = 2|0x300U,    /**< TPM8 Channel 0 */
    kDmaRequestMux2TPM8Channel2     = 3|0x300U,    /**< TPM8 Channel 0 */
    kDmaRequestMux2TPM8Channel3     = 4|0x300U,    /**< TPM8 Channel 0 */
    kDmaRequestMux2TPM8Channel4     = 5|0x300U,    /**< TPM8 Channel 0 */
    kDmaRequestMux2TPM8Channel5     = 6|0x300U,    /**< TPM8 Channel 0 */
    kDmaRequestMux2TPM8Overflow     = 7|0x300U,    /**< TPM8 Overflow */
    kDmaRequestMux2FlexSPI0Rx       = 8|0x300U,    /**< FlexSPI0 Receive request */
    kDmaRequestMux2FlexSPI0Tx       = 9|0x300U,    /**< FlexSPI0 Transmit request */
    kDmaRequestMux2FlexSPI1Rx       = 10|0x300U,   /**< FlexSPI1 Receive request */
    kDmaRequestMux2FlexSPI1Tx       = 11|0x300U,   /**< FlexSPI1 Transmit request */
    kDmaRequestMux2FlexSPI2Rx       = 12|0x300U,   /**< FlexSPI2 Receive request */
    kDmaRequestMux2FlexSPI2Tx       = 13|0x300U,   /**< FlexSPI2 Transmit request */
    kDmaRequestMux2FlexIO0Shifter0  = 15|0x300U,   /**< FlexIO0 Shifter 0 */
    kDmaRequestMux2FlexIO0Shifter1  = 16|0x300U,   /**< FlexIO0 Shifter 1 */
    kDmaRequestMux2FlexIO0Shifter2  = 17|0x300U,   /**< FlexIO0 Shifter 2 */
    kDmaRequestMux2FlexIO0Shifter3  = 18|0x300U,   /**< FlexIO0 Shifter 3 */
    kDmaRequestMux2FlexIO0Shifter4  = 19|0x300U,   /**< FlexIO0 Shifter 4 */
    kDmaRequestMux2FlexIO0Shifter5  = 20|0x300U,   /**< FlexIO0 Shifter 5 */
    kDmaRequestMux2FlexIO0Shifter6  = 21|0x300U,   /**< FlexIO0 Shifter 6 */
    kDmaRequestMux2FlexIO0Shifter7  = 22|0x300U,   /**< FlexIO0 Shifter 7 */
    kDmaRequestMux2FlexIO1Shifter0  = 23|0x300U,   /**< FlexIO1 Shifter 0 */
    kDmaRequestMux2FlexIO1Shifter1  = 24|0x300U,   /**< FlexIO1 Shifter 1 */
    kDmaRequestMux2FlexIO1Shifter2  = 25|0x300U,   /**< FlexIO1 Shifter 2 */
    kDmaRequestMux2FlexIO1Shifter3  = 26|0x300U,   /**< FlexIO1 Shifter 3 */
    kDmaRequestMux2FlexIO1Shifter4  = 27|0x300U,   /**< FlexIO1 Shifter 4 */
    kDmaRequestMux2FlexIO1Shifter5  = 28|0x300U,   /**< FlexIO1 Shifter 5 */
    kDmaRequestMux2FlexIO1Shifter6  = 29|0x300U,   /**< FlexIO1 Shifter 6 */
    kDmaRequestMux2FlexIO1Shifter7  = 30|0x300U,   /**< FlexIO1 Shifter 7 */
    kDmaRequestMux2LPI2C3Rx         = 33|0x300U,   /**< LPI2C3 Master/Slave Receive */
    kDmaRequestMux2LPI2C3Tx         = 34|0x300U,   /**< LPI2C3 Master/Slave Transmit */
    kDmaRequestMux2LPI2C5Rx         = 37|0x300U,   /**< LPI2C5 Master/Slave Receive */
    kDmaRequestMux2LPI2C5Tx         = 38|0x300U,   /**< LPI2C5 Master/Slave Transmit */
    kDmaRequestMux2I3C1Rx           = 39|0x300U,   /**< I3C1 Master/Slave Receive */
    kDmaRequestMux2I3C1Tx           = 40|0x300U,   /**< I3C1 Master/Slave Transmit */
    kDmaRequestMux2I3C2Rx           = 41|0x300U,   /**< I3C2 Master/Slave Receive */
    kDmaRequestMux2I3C2Tx           = 42|0x300U,   /**< I3C2 Master/Slave Transmit */
    kDmaRequestMux2LPSPI3Rx         = 45|0x300U,   /**< LPSPI3 Receive */
    kDmaRequestMux2LPSPI3Tx         = 46|0x300U,   /**< LPSPI3 Transmit */
    kDmaRequestMux2LPSPI5Rx         = 49|0x300U,   /**< LPSPI5 Receive */
    kDmaRequestMux2LPSPI5Tx         = 50|0x300U,   /**< LPSPI5 Transmit */
    kDmaRequestMux2LPUART3Rx        = 53|0x300U,   /**< LPUART3 Receive */
    kDmaRequestMux2LPUART3Tx        = 54|0x300U,   /**< LPUART3 Transmit */
    kDmaRequestMux2LPUART5Rx        = 57|0x300U,   /**< LPUART5 Receive */
    kDmaRequestMux2LPUART5Tx        = 58|0x300U,   /**< LPUART5 Transmit */
    kDmaRequestMux2SAI0Rx           = 59|0x300U,   /**< SAI0 Receive */
    kDmaRequestMux2SAI0Tx           = 60|0x300U,   /**< SAI0 Transmit */
    kDmaRequestMux2SAI1Rx           = 61|0x300U,   /**< SAI1 Receive */
    kDmaRequestMux2SAI1Tx           = 62|0x300U,   /**< SAI1 Transmit */
    kDmaRequestMux2SAI4Rx           = 67|0x300U,   /**< SAI4 Receive */
    kDmaRequestMux2SAI4Tx           = 68|0x300U,   /**< SAI4 Transmit */
    kDmaRequestMux2SAI5Rx           = 69|0x300U,   /**< SAI5 Receive */
    kDmaRequestMux2SAI5Tx           = 70|0x300U,   /**< SAI5 Transmit */
    kDmaRequestMux2SAI6Rx           = 71|0x300U,   /**< SAI6 Receive */
    kDmaRequestMux2SAI6Tx           = 72|0x300U,   /**< SAI6 Transmit */
    kDmaRequestMux2SAI7Rx           = 73|0x300U,   /**< SAI7 Receive */
    kDmaRequestMux2SAI7Tx           = 74|0x300U,   /**< SAI7 Transmit */
    kDmaRequestMux2SPDIFRx          = 75|0x300U,   /**< SPDIF Receive */
    kDmaRequestMux2SPDIFTx          = 76|0x300U,   /**< SPDIF Transmit */
    kDmaRequestMux2GPIODEvent0      = 83|0x300U,   /**< GPIOD Pin event request 0 */
    kDmaRequestMux2GPIODEvent1      = 84|0x300U,   /**< GPIOD Pin event request 1 */
} dma2_request_source_t;

/* @} */

/*!
 * @addtogroup trgmux0_source
 * @{ */

/*******************************************************************************
 * Definitions
*******************************************************************************/

/*!
 * @brief Enumeration for the TRGMUX0 source
 *
 * Defines the enumeration for the TRGMUX0 source collections.
 */
typedef enum _trgmux0_source
{
    kTRGMUX0_SourceDisabled         = 0U,          /**< Trigger function is disabled */
    kTRGMUX0_SourceWUU0             = 1U,          /**< WUU0 input is selected */
    kTRGMUX0_SourceRTC0Alarm        = 2U,          /**< RTC0 Alarm event input is selected */
    kTRGMUX0_SourceRTC0Seconds      = 3U,          /**< RTC0 Seconds input is selected */
    kTRGMUX0_SourceLPTMR0           = 4U,          /**< LPTMR0 input is selected */
    kTRGMUX0_SourceLPTMR1           = 5U,          /**< LPTMR1 input is selected */
    kTRGMUX0_SourceLPIT0Channel0    = 8U,          /**< LPIT0 Channel0 input is selected */
    kTRGMUX0_SourceLPIT0Channel1    = 9U,          /**< LPIT0 Channel1 input is selected */
    kTRGMUX0_SourceLPIT0Channel2    = 10U,         /**< LPIT0 Channel2 input is selected */
    kTRGMUX0_SourceLPIT0Channel3    = 11U,         /**< LPIT0 Channel3 input is selected */
    kTRGMUX0_SourceTPM0Channel0     = 12U,         /**< TPM0 Channel0 input is selected */
    kTRGMUX0_SourceTPM0Channel1     = 13U,         /**< TPM0 Channel1 input is selected */
    kTRGMUX0_SourceTPM0Channel2     = 14U,         /**< TPM0 Channel2 input is selected */
    kTRGMUX0_SourceTPM0Channel3     = 15U,         /**< TPM0 Channel3 input is selected */
    kTRGMUX0_SourceTPM0Channel4     = 16U,         /**< TPM0 Channel4 input is selected */
    kTRGMUX0_SourceTPM0Channel5     = 17U,         /**< TPM0 Channel5 input is selected */
    kTRGMUX0_SourceTPM0Overflow     = 18U,         /**< TPM0 Overflow input is selected */
    kTRGMUX0_SourceTPM1Channel0     = 19U,         /**< TPM1 Channel0 input is selected */
    kTRGMUX0_SourceTPM1Channel1     = 20U,         /**< TPM1 Channel1 input is selected */
    kTRGMUX0_SourceTPM1Overflow     = 25U,         /**< TPM1 Overflow input is selected */
    kTRGMUX0_SourceTPM2Channel0     = 26U,         /**< TPM2 Channel0 input is selected */
    kTRGMUX0_SourceTPM2Channel1     = 27U,         /**< TPM2 Channel1 input is selected */
    kTRGMUX0_SourceTPM2Overflow     = 32U,         /**< TPM2 Overflow input is selected */
    kTRGMUX0_SourceTPM3Channel0     = 33U,         /**< TPM3 Channel0 input is selected */
    kTRGMUX0_SourceTPM3Channel1     = 34U,         /**< TPM3 Channel1 input is selected */
    kTRGMUX0_SourceTPM3Channel2     = 35U,         /**< TPM3 Channel2 input is selected */
    kTRGMUX0_SourceTPM3Channel3     = 36U,         /**< TPM3 Channel3 input is selected */
    kTRGMUX0_SourceTPM3Channel4     = 37U,         /**< TPM3 Channel4 input is selected */
    kTRGMUX0_SourceTPM3Channel5     = 38U,         /**< TPM3 Channel5 input is selected */
    kTRGMUX0_SourceTPM3Overflow     = 39U,         /**< TPM3 Overflow input is selected */
    kTRGMUX0_SourceTPM8Channel0     = 40U,         /**< TPM8 Channel0 input is selected */
    kTRGMUX0_SourceTPM8Channel1     = 41U,         /**< TPM8 Channel1 input is selected */
    kTRGMUX0_SourceTPM8Channel2     = 42U,         /**< TPM8 Channel2 input is selected */
    kTRGMUX0_SourceTPM8Channel3     = 43U,         /**< TPM8 Channel3 input is selected */
    kTRGMUX0_SourceTPM8Channel4     = 44U,         /**< TPM8 Channel4 input is selected */
    kTRGMUX0_SourceTPM8Channel5     = 45U,         /**< TPM8 Channel5 input is selected */
    kTRGMUX0_SourceTPM8Overflow     = 46U,         /**< TPM8 Overflow input is selected */
    kTRGMUX0_SourceFlexIO0Channel0  = 47U,         /**< FlexIO0 Channel0 input is selected */
    kTRGMUX0_SourceFlexIO0Channel1  = 48U,         /**< FlexIO0 Channel1 input is selected */
    kTRGMUX0_SourceFlexIO0Channel2  = 49U,         /**< FlexIO0 Channel2 input is selected */
    kTRGMUX0_SourceFlexIO0Channel3  = 50U,         /**< FlexIO0 Channel3 input is selected */
    kTRGMUX0_SourceFlexIO0Channel4  = 51U,         /**< FlexIO0 Channel4 input is selected */
    kTRGMUX0_SourceFlexIO0Channel5  = 52U,         /**< FlexIO0 Channel5 input is selected */
    kTRGMUX0_SourceFlexIO0Channel6  = 53U,         /**< FlexIO0 Channel6 input is selected */
    kTRGMUX0_SourceFlexIO0Channel7  = 54U,         /**< FlexIO0 Channel7 input is selected */
    kTRGMUX0_SourceLPI2C0MasterStop = 55U,         /**< LPI2C0 Master Stop input is selected */
    kTRGMUX0_SourceLPI2C0SlaveStop  = 56U,         /**< LPI2C0 Slave Stop input is selected */
    kTRGMUX0_SourceLPI2C1MasterStop = 57U,         /**< LPI2C1 Master Stop input is selected */
    kTRGMUX0_SourceLPI2C1SlaveStop  = 58U,         /**< LPI2C1 Slave Stop input is selected */
    kTRGMUX0_SourceLPI2C2MasterStop = 59U,         /**< LPI2C2 Master Stop input is selected */
    kTRGMUX0_SourceLPI2C2SlaveStop  = 60U,         /**< LPI2C2 Slave Stop input is selected */
    kTRGMUX0_SourceLPI2C3MasterStop = 61U,         /**< LPI2C3 Master Stop input is selected */
    kTRGMUX0_SourceLPI2C3SlaveStop  = 62U,         /**< LPI2C3 Slave Stop input is selected */
    kTRGMUX0_SourceI2S0TxFrameSync  = 63U,         /**< SAI0 TX Frame Sync input is selected */
    kTRGMUX0_SourceI2S0RxFrameSync  = 64U,         /**< SAI0 RX Frame Sync input is selected */
    kTRGMUX0_SourceI2S1TxFrameSync  = 65U,         /**< SAI1 TX Frame Sync input is selected */
    kTRGMUX0_SourceI2S1RxFrameSync  = 66U,         /**< SAI1 RX Frame Sync input is selected */
    kTRGMUX0_SourceI2S2TxFrameSync  = 67U,         /**< SAI2 TX Frame Sync input is selected */
    kTRGMUX0_SourceI2S2RxFrameSync  = 68U,         /**< SAI2 RX Frame Sync input is selected */
    kTRGMUX0_SourceI2S3TxFrameSync  = 69U,         /**< SAI3 TX Frame Sync input is selected */
    kTRGMUX0_SourceI2S3RxFrameSync  = 70U,         /**< SAI3 RX Frame Sync input is selected */
    kTRGMUX0_SourceI2S6TxFrameSync  = 71U,         /**< SAI6 TX Frame Sync input is selected */
    kTRGMUX0_SourceI2S6RxFrameSync  = 72U,         /**< SAI6 RX Frame Sync input is selected */
    kTRGMUX0_SourceI2S7TxFrameSync  = 73U,         /**< SAI7 TX Frame Sync input is selected */
    kTRGMUX0_SourceI2S7RxFrameSync  = 74U,         /**< SAI7 RX Frame Sync input is selected */
    kTRGMUX0_SourceLPSPI0Frame      = 75U,         /**< LPSPI0 Frame input is selected */
    kTRGMUX0_SourceLPSPI0RxData     = 76U,         /**< LPSPI0 RX Data input is selected */
    kTRGMUX0_SourceLPSPI1Frame      = 77U,         /**< LPSPI1 Frame input is selected */
    kTRGMUX0_SourceLPSPI1RxData     = 78U,         /**< LPSPI1 RX Data input is selected */
    kTRGMUX0_SourceLPSPI2Frame      = 79U,         /**< LPSPI2 Frame input is selected */
    kTRGMUX0_SourceLPSPI2RxData     = 80U,         /**< LPSPI2 RX Data input is selected */
    kTRGMUX0_SourceLPSPI3Frame      = 81U,         /**< LPSPI3 Frame input is selected */
    kTRGMUX0_SourceLPSPI3RxData     = 82U,         /**< LPSPI3 RX Data input is selected */
    kTRGMUX0_SourceLPUART0RxData    = 83U,         /**< LPUART0 RX Data input is selected */
    kTRGMUX0_SourceLPUART0TxData    = 84U,         /**< LPUART0 TX Data input is selected */
    kTRGMUX0_SourceLPUART0RxIdle    = 85U,         /**< LPUART0 RX Idle input is selected */
    kTRGMUX0_SourceLPUART1RxData    = 86U,         /**< LPUART1 RX Data input is selected */
    kTRGMUX0_SourceLPUART1TxData    = 87U,         /**< LPUART1 TX Data input is selected */
    kTRGMUX0_SourceLPUART1RxIdle    = 88U,         /**< LPUART1 RX Idle input is selected */
    kTRGMUX0_SourceLPUART2RxData    = 89U,         /**< LPUART2 RX Data input is selected */
    kTRGMUX0_SourceLPUART2TxData    = 90U,         /**< LPUART2 TX Data input is selected */
    kTRGMUX0_SourceLPUART2RxIdle    = 91U,         /**< LPUART2 RX Idle input is selected */
    kTRGMUX0_SourceLPUART3RxData    = 92U,         /**< LPUART3 RX Data input is selected */
    kTRGMUX0_SourceLPUART3TxData    = 93U,         /**< LPUART3 TX Data input is selected */
    kTRGMUX0_SourceLPUART3RxIdle    = 94U,         /**< LPUART3 RX Idle input is selected */
    kTRGMUX0_SourceUSB0StartOfFrame = 95U,         /**< USB0 Start of Frame input is selected */
    kTRGMUX0_SourceUSB1StartOfFrame = 96U,         /**< USB1 Start of Frame input is selected */
    kTRGMUX0_SourceGPIOAPinEvent2   = 97U,         /**< GPIO A Pin event trigger 2 is selected */
    kTRGMUX0_SourceGPIOAPinEvent3   = 98U,         /**< GPIO A Pin event trigger 3 is selected */
    kTRGMUX0_SourceGPIOBPinEvent2   = 99U,         /**< GPIO B Pin event trigger 2 is selected */
    kTRGMUX0_SourceGPIOBPinEvent3   = 100U,        /**< GPIO B Pin event trigger 3 is selected */
    kTRGMUX0_SourceGPIOCPinEvent2   = 101U,        /**< GPIO C Pin event trigger 2 is selected */
    kTRGMUX0_SourceGPIOCPinEvent3   = 102U,        /**< GPIO C Pin event trigger 3 is selected */
    kTRGMUX0_SourceGPIODPinEvent2   = 103U,        /**< GPIO D Pin event trigger 2 is selected */
    kTRGMUX0_SourceGPIODPinEvent3   = 104U,        /**< GPIO D Pin event trigger 3 is selected */
    kTRGMUX0_SourceGPIOEPinEvent2   = 105U,        /**< GPIO E Pin event trigger 2 is selected */
    kTRGMUX0_SourceGPIOEPinEvent3   = 106U,        /**< GPIO E Pin event trigger 3 is selected */
    kTRGMUX0_SourceGPIOFPinEvent2   = 107U,        /**< GPIO F Pin event trigger 2 is selected */
    kTRGMUX0_SourceGPIOFPinEvent3   = 108U,        /**< GPIO F Pin event trigger 3 is selected */
    kTRGMUX0_SourceADC0Output0      = 109U,        /**< ADC0 Output0 input is selected */
    kTRGMUX0_SourceADC0Output1      = 110U,        /**< ADC0 Output1 input is selected */
    kTRGMUX0_SourceADC0Output2      = 111U,        /**< ADC0 Output2 input is selected */
    kTRGMUX0_SourceADC0Output3      = 112U,        /**< ADC0 Output3 input is selected */
    kTRGMUX0_SourceADC1Output0      = 113U,        /**< ADC1 Output0 input is selected */
    kTRGMUX0_SourceADC1Output1      = 114U,        /**< ADC1 Output1 input is selected */
    kTRGMUX0_SourceADC1Output2      = 115U,        /**< ADC1 Output2 input is selected */
    kTRGMUX0_SourceADC1Output3      = 116U,        /**< ADC1 Output3 input is selected */
    kTRGMUX0_SourceCMP0Output       = 117U,        /**< CMP0 Output input is selected */
    kTRGMUX0_SourceCMP1Output       = 118U,        /**< CMP1 Output input is selected */
} trgmux0_source_t;

/* @} */

/*!
 * @addtogroup trgmux1_source
 * @{ */

/*******************************************************************************
 * Definitions
*******************************************************************************/

/*!
 * @brief Enumeration for the TRGMUX1 source
 *
 * Defines the enumeration for the TRGMUX1 source collections.
 */
typedef enum _trgmux1_source
{
    kTRGMUX1_SourceDisabled         = 0U,          /**< Trigger function is disabled */
    kTRGMUX1_SourceWUU1             = 1U,          /**< WUU1 input is selected */
    kTRGMUX1_SourceRTC0Alarm        = 2U,          /**< RTC0 Alarm event input is selected */
    kTRGMUX1_SourceRTC0Seconds      = 3U,          /**< RTC0 Seconds input is selected */
    kTRGMUX1_SourceLPIT1Channel0    = 4U,          /**< LPIT1 Channel0 input is selected */
    kTRGMUX1_SourceLPIT1Channel1    = 5U,          /**< LPIT1 Channel1 input is selected */
    kTRGMUX1_SourceLPIT1Channel2    = 6U,          /**< LPIT1 Channel2 input is selected */
    kTRGMUX1_SourceLPIT1Channel3    = 7U,          /**< LPIT1 Channel3 input is selected */
    kTRGMUX1_SourceTPM4Channel0     = 8U,          /**< TPM4 Channel0 input is selected */
    kTRGMUX1_SourceTPM4Channel1     = 9U,          /**< TPM4 Channel1 input is selected */
    kTRGMUX1_SourceTPM4Channel2     = 10U,         /**< TPM4 Channel2 input is selected */
    kTRGMUX1_SourceTPM4Channel3     = 11U,         /**< TPM4 Channel3 input is selected */
    kTRGMUX1_SourceTPM4Channel4     = 12U,         /**< TPM4 Channel4 input is selected */
    kTRGMUX1_SourceTPM4Channel5     = 13U,         /**< TPM4 Channel5 input is selected */
    kTRGMUX1_SourceTPM4Overflow     = 14U,         /**< TPM4 Overflow input is selected */
    kTRGMUX1_SourceTPM5Channel0     = 15U,         /**< TPM5 Channel0 input is selected */
    kTRGMUX1_SourceTPM5Channel1     = 16U,         /**< TPM5 Channel1 input is selected */
    kTRGMUX1_SourceTPM5Overflow     = 21U,         /**< TPM5 Overflow input is selected */
    kTRGMUX1_SourceTPM6Channel0     = 22U,         /**< TPM6 Channel0 input is selected */
    kTRGMUX1_SourceTPM6Channel1     = 23U,         /**< TPM6 Channel1 input is selected */
    kTRGMUX1_SourceTPM6Overflow     = 28U,         /**< TPM6 Overflow input is selected */
    kTRGMUX1_SourceTPM7Channel0     = 29U,         /**< TPM7 Channel0 input is selected */
    kTRGMUX1_SourceTPM7Channel1     = 30U,         /**< TPM7 Channel1 input is selected */
    kTRGMUX1_SourceTPM7Channel2     = 31U,         /**< TPM7 Channel2 input is selected */
    kTRGMUX1_SourceTPM7Channel3     = 32U,         /**< TPM7 Channel3 input is selected */
    kTRGMUX1_SourceTPM7Channel4     = 33U,         /**< TPM7 Channel4 input is selected */
    kTRGMUX1_SourceTPM7Channel5     = 34U,         /**< TPM7 Channel5 input is selected */
    kTRGMUX1_SourceTPM7Overflow     = 35U,         /**< TPM7 Overflow input is selected */
    kTRGMUX1_SourceTPM8Channel0     = 36U,         /**< TPM8 Channel0 input is selected */
    kTRGMUX1_SourceTPM8Channel1     = 37U,         /**< TPM8 Channel1 input is selected */
    kTRGMUX1_SourceTPM8Channel2     = 38U,         /**< TPM8 Channel2 input is selected */
    kTRGMUX1_SourceTPM8Channel3     = 39U,         /**< TPM8 Channel3 input is selected */
    kTRGMUX1_SourceTPM8Channel4     = 40U,         /**< TPM8 Channel4 input is selected */
    kTRGMUX1_SourceTPM8Channel5     = 41U,         /**< TPM8 Channel5 input is selected */
    kTRGMUX1_SourceTPM8Overflow     = 42U,         /**< TPM8 Overflow input is selected */
    kTRGMUX1_SourceFlexIO1Channel0  = 43U,         /**< FlexIO1 Channel0 input is selected */
    kTRGMUX1_SourceFlexIO1Channel1  = 44U,         /**< FlexIO1 Channel1 input is selected */
    kTRGMUX1_SourceFlexIO1Channel2  = 45U,         /**< FlexIO1 Channel2 input is selected */
    kTRGMUX1_SourceFlexIO1Channel3  = 46U,         /**< FlexIO1 Channel3 input is selected */
    kTRGMUX1_SourceFlexIO1Channel4  = 47U,         /**< FlexIO1 Channel4 input is selected */
    kTRGMUX1_SourceFlexIO1Channel5  = 48U,         /**< FlexIO1 Channel5 input is selected */
    kTRGMUX1_SourceFlexIO1Channel6  = 49U,         /**< FlexIO1 Channel6 input is selected */
    kTRGMUX1_SourceFlexIO1Channel7  = 50U,         /**< FlexIO1 Channel7 input is selected */
    kTRGMUX1_SourceLPI2C4MasterStop = 51U,         /**< LPI2C4 Master Stop input is selected */
    kTRGMUX1_SourceLPI2C4SlaveStop  = 52U,         /**< LPI2C4 Slave Stop input is selected */
    kTRGMUX1_SourceLPI2C5MasterStop = 53U,         /**< LPI2C5 Master Stop input is selected */
    kTRGMUX1_SourceLPI2C5SlaveStop  = 54U,         /**< LPI2C5 Slave Stop input is selected */
    kTRGMUX1_SourceLPI2C6MasterStop = 55U,         /**< LPI2C6 Master Stop input is selected */
    kTRGMUX1_SourceLPI2C6SlaveStop  = 56U,         /**< LPI2C6 Slave Stop input is selected */
    kTRGMUX1_SourceLPI2C7MasterStop = 57U,         /**< LPI2C7 Master Stop input is selected */
    kTRGMUX1_SourceLPI2C7SlaveStop  = 58U,         /**< LPI2C7 Slave Stop input is selected */
    kTRGMUX1_SourceI2S4TxFrameSync  = 59U,         /**< SAI4 TX Frame Sync input is selected */
    kTRGMUX1_SourceI2S4RxFrameSync  = 60U,         /**< SAI4 RX Frame Sync input is selected */
    kTRGMUX1_SourceI2S5TxFrameSync  = 61U,         /**< SAI5 TX Frame Sync input is selected */
    kTRGMUX1_SourceI2S5RxFrameSync  = 62U,         /**< SAI5 RX Frame Sync input is selected */
    kTRGMUX1_SourceI2S6TxFrameSync  = 63U,         /**< SAI6 TX Frame Sync input is selected */
    kTRGMUX1_SourceI2S6RxFrameSync  = 64U,         /**< SAI6 RX Frame Sync input is selected */
    kTRGMUX1_SourceI2S7TxFrameSync  = 65U,         /**< SAI7 TX Frame Sync input is selected */
    kTRGMUX1_SourceI2S7RxFrameSync  = 66U,         /**< SAI7 RX Frame Sync input is selected */
    kTRGMUX1_SourceLPSPI4Frame      = 67U,         /**< LPSPI4 Frame input is selected */
    kTRGMUX1_SourceLPSPI4RxData     = 68U,         /**< LPSPI4 RX Data input is selected */
    kTRGMUX1_SourceLPSPI5Frame      = 69U,         /**< LPSPI5 Frame input is selected */
    kTRGMUX1_SourceLPSPI5RxData     = 70U,         /**< LPSPI5 RX Data input is selected */
    kTRGMUX1_SourceLPUART4RxData    = 71U,         /**< LPUART4 RX Data input is selected */
    kTRGMUX1_SourceLPUART4TxData    = 72U,         /**< LPUART4 TX Data input is selected */
    kTRGMUX1_SourceLPUART4RxIdle    = 73U,         /**< LPUART4 RX Idle input is selected */
    kTRGMUX1_SourceLPUART5RxData    = 74U,         /**< LPUART5 RX Data input is selected */
    kTRGMUX1_SourceLPUART5TxData    = 75U,         /**< LPUART5 TX Data input is selected */
    kTRGMUX1_SourceLPUART5RxIdle    = 76U,         /**< LPUART5 RX Idle input is selected */
    kTRGMUX1_SourceLPUART6RxData    = 77U,         /**< LPUART6 RX Data input is selected */
    kTRGMUX1_SourceLPUART6TxData    = 78U,         /**< LPUART6 TX Data input is selected */
    kTRGMUX1_SourceLPUART6RxIdle    = 79U,         /**< LPUART6 RX Idle input is selected */
    kTRGMUX1_SourceLPUART7RxData    = 80U,         /**< LPUART7 RX Data input is selected */
    kTRGMUX1_SourceLPUART7TxData    = 81U,         /**< LPUART7 TX Data input is selected */
    kTRGMUX1_SourceLPUART7RxIdle    = 82U,         /**< LPUART7 RX Idle input is selected */
    kTRGMUX1_SourceUSB0StartOfFrame = 83U,         /**< USB0 Start of Frame input is selected */
    kTRGMUX1_SourceUSB1StartOfFrame = 84U,         /**< USB1 Start of Frame input is selected */
    kTRGMUX1_SourceGPIOAPinEvent0   = 85U,         /**< GPIO A Pin event trigger 0 is selected */
    kTRGMUX1_SourceGPIOAPinEvent1   = 86U,         /**< GPIO A Pin event trigger 1 is selected */
    kTRGMUX1_SourceGPIOBPinEvent0   = 87U,         /**< GPIO B Pin event trigger 0 is selected */
    kTRGMUX1_SourceGPIOBPinEvent1   = 88U,         /**< GPIO B Pin event trigger 1 is selected */
    kTRGMUX1_SourceGPIOCPinEvent0   = 89U,         /**< GPIO C Pin event trigger 0 is selected */
    kTRGMUX1_SourceGPIOCPinEvent1   = 90U,         /**< GPIO C Pin event trigger 1 is selected */
    kTRGMUX1_SourceGPIODPinEvent0   = 91U,         /**< GPIO D Pin event trigger 0 is selected */
    kTRGMUX1_SourceGPIODPinEvent1   = 92U,         /**< GPIO D Pin event trigger 1 is selected */
    kTRGMUX1_SourceGPIOEPinEvent0   = 93U,         /**< GPIO E Pin event trigger 0 is selected */
    kTRGMUX1_SourceGPIOEPinEvent1   = 94U,         /**< GPIO E Pin event trigger 1 is selected */
    kTRGMUX1_SourceGPIOFPinEvent0   = 95U,         /**< GPIO F Pin event trigger 0 is selected */
    kTRGMUX1_SourceGPIOFPinEvent1   = 96U,         /**< GPIO F Pin event trigger 1 is selected */
} trgmux1_source_t;

/* @} */

/*!
 * @brief Enumeration for the TRGMUX0 device
 *
 * Defines the enumeration for the TRGMUX0 device collections.
 */
typedef enum _trgmux0_device
{
    kTRGMUX0_LPIT0                  = 0U,          /**< LPIT0 trigger 0-3 */
    kTRGMUX0_TPM0                   = 1U,          /**< TPM0 channel 0-1 trigger */
    kTRGMUX0_TPM1                   = 2U,          /**< TPM1 channel 0-1 trigger */
    kTRGMUX0_TPM2                   = 3U,          /**< TPM2 channel 0-1 trigger */
    kTRGMUX0_TPM3                   = 4U,          /**< TPM3 channel 0-1 trigger */
    kTRGMUX0_TPM8                   = 5U,          /**< TPM8 channel 0-1 trigger */
    kTRGMUX0_FLEXIO0                = 6U,          /**< FlexIO0 trigger 0-3 */
    kTRGMUX0_LPI2C0                 = 7U,          /**< LPI2C0 Host request */
    kTRGMUX0_LPI2C1                 = 8U,          /**< LPI2C1 Host request */
    kTRGMUX0_LPI2C2                 = 9U,          /**< LPI2C2 Host request */
    kTRGMUX0_LPI2C3                 = 10U,         /**< LPI2C3 Host request */
    kTRGMUX0_LPSPI0                 = 11U,         /**< LPSPI0 Host request */
    kTRGMUX0_LPSPI1                 = 12U,         /**< LPSPI1 Host request */
    kTRGMUX0_LPSPI2                 = 13U,         /**< LPSPI2 Host request */
    kTRGMUX0_LPSPI3                 = 14U,         /**< LPSPI3 Host request */
    kTRGMUX0_LPUART0                = 15U,         /**< LPUART0 input */
    kTRGMUX0_LPUART1                = 16U,         /**< LPUART1 input */
    kTRGMUX0_LPUART2                = 17U,         /**< LPUART2 input */
    kTRGMUX0_LPUART3                = 18U,         /**< LPUART3 input */
    kTRGMUX0_ADC0                   = 19U,         /**< ADC0 trigger */
    kTRGMUX0_ADC1                   = 20U,         /**< ADC1 trigger */
    kTRGMUX0_CMP0                   = 21U,         /**< CMP0 Window trigger */
    kTRGMUX0_CMP1                   = 22U,         /**< CMP1 Window trigger */
    kTRGMUX0_DAC0                   = 23U,         /**< DAC0 Trigger */
    kTRGMUX0_DAC1                   = 24U,         /**< DAC1 Trigger */
} trgmux0_device_t;

/*!
 * @brief Enumeration for the TRGMUX1 device
 *
 * Defines the enumeration for the TRGMUX1 device collections.
 */
typedef enum _trgmux1_device
{
    kTRGMUX1_LPIT1                  = 0U,          /**< LPIT1 trigger 0-3 */
    kTRGMUX1_TPM4                   = 1U,          /**< TPM4 channel 0-1 trigger */
    kTRGMUX1_TPM5                   = 2U,          /**< TPM5 channel 0-1 trigger */
    kTRGMUX1_TPM6                   = 3U,          /**< TPM6 channel 0-1 trigger */
    kTRGMUX1_TPM7                   = 4U,          /**< TPM7 channel 0-1 trigger */
    kTRGMUX1_TPM8                   = 5U,          /**< TPM8 channel 0-1 trigger */
    kTRGMUX1_FLEXIO1                = 6U,          /**< FlexIO1 trigger 0-3 */
    kTRGMUX1_LPI2C4                 = 7U,          /**< LPI2C4 Host request */
    kTRGMUX1_LPI2C5                 = 8U,          /**< LPI2C5 Host request */
    kTRGMUX1_LPI2C6                 = 9U,          /**< LPI2C6 Host request */
    kTRGMUX1_LPI2C7                 = 10U,         /**< LPI2C7 Host request */
    kTRGMUX1_LPSPI4                 = 11U,         /**< LPSPI4 Host request */
    kTRGMUX1_LPSPI5                 = 12U,         /**< LPSPI5 Host request */
    kTRGMUX1_LPUART4                = 13U,         /**< LPUART4 input */
    kTRGMUX1_LPUART5                = 14U,         /**< LPUART5 input */
    kTRGMUX1_LPUART6                = 15U,         /**< LPUART6 input */
    kTRGMUX1_LPUART7                = 16U,         /**< LPUART7 input */
} trgmux1_device_t;


/*!
 * @}
 */ /* end of group Mapping_Information */


/* ----------------------------------------------------------------------------
   -- Device Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
 * @{
 */


/*
** Start of section using anonymous unions
*/

#if defined(__XTENSA__)
  /* anonymous unions are enabled by default */
#else
  #error Not supported compiler type
#endif

/* ----------------------------------------------------------------------------
   -- ADC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
 * @{
 */

/** ADC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t CTRL;                              /**< ADC Control Register, offset: 0x10 */
  __IO uint32_t STAT;                              /**< ADC Status Register, offset: 0x14 */
  __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
  __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
  __IO uint32_t CFG;                               /**< ADC Configuration Register, offset: 0x20 */
  __IO uint32_t PAUSE;                             /**< ADC Pause Register, offset: 0x24 */
       uint8_t RESERVED_1[12];
  __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
  __IO uint32_t TSTAT;                             /**< Trigger Status Register, offset: 0x38 */
       uint8_t RESERVED_2[100];
  __IO uint32_t TCTRL[4];                          /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
       uint8_t RESERVED_3[48];
  __IO uint32_t FCTRL;                             /**< FIFO Control Register, offset: 0xE0 */
       uint8_t RESERVED_4[28];
  struct {                                         /* offset: 0x100, array step: 0x8 */
    __IO uint32_t CMDL;                              /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
    __IO uint32_t CMDH;                              /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
  } CMD[15];
       uint8_t RESERVED_5[136];
  __IO uint32_t CV[4];                             /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_6[240];
  __I  uint32_t RESFIFO;                           /**< ADC Data Result FIFO Register, offset: 0x300 */
} ADC_Type;

/* ----------------------------------------------------------------------------
   -- ADC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ADC_Register_Masks ADC Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define ADC_VERID_RES_MASK                       (0x1U)
#define ADC_VERID_RES_SHIFT                      (0U)
/*! RES - Resolution
 *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
 *  0b1..Up to 16-bit differential/15-bit single ended resolution supported.
 */
#define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)

#define ADC_VERID_DIFFEN_MASK                    (0x2U)
#define ADC_VERID_DIFFEN_SHIFT                   (1U)
/*! DIFFEN - Differential Supported
 *  0b0..Differential operation not supported.
 *  0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
 */
#define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)

#define ADC_VERID_MVI_MASK                       (0x8U)
#define ADC_VERID_MVI_SHIFT                      (3U)
/*! MVI - Multi Vref Implemented
 *  0b0..Single voltage reference high (VREFH) input supported.
 *  0b1..Multiple voltage reference high (VREFH) inputs supported.
 */
#define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)

#define ADC_VERID_CSW_MASK                       (0x70U)
#define ADC_VERID_CSW_SHIFT                      (4U)
/*! CSW - Channel Scale Width
 *  0b000..Channel scaling not supported.
 *  0b001..Channel scaling supported. 1-bit CSCALE control field.
 *  0b110..Channel scaling supported. 6-bit CSCALE control field.
 */
#define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)

#define ADC_VERID_VR1RNGI_MASK                   (0x100U)
#define ADC_VERID_VR1RNGI_SHIFT                  (8U)
/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
 *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
 *  0b1..Range control required. CFG[VREF1RNG] is implemented.
 */
#define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)

#define ADC_VERID_IADCKI_MASK                    (0x200U)
#define ADC_VERID_IADCKI_SHIFT                   (9U)
/*! IADCKI - Internal ADC Clock implemented
 *  0b0..Internal clock source not implemented.
 *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
 */
#define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)

#define ADC_VERID_CALOFSI_MASK                   (0x400U)
#define ADC_VERID_CALOFSI_SHIFT                  (10U)
/*! CALOFSI - Calibration Function Implemented
 *  0b0..Calibration Not Implemented.
 *  0b1..Calibration Implemented.
 */
#define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)

#define ADC_VERID_NUM_SEC_MASK                   (0x800U)
#define ADC_VERID_NUM_SEC_SHIFT                  (11U)
/*! NUM_SEC - Number of Single Ended Outputs Supported
 *  0b0..This design supports one single ended conversion at a time.
 *  0b1..This design supports two simultanious single ended conversions.
 */
#define ADC_VERID_NUM_SEC(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)

#define ADC_VERID_NUM_FIFO_MASK                  (0x7000U)
#define ADC_VERID_NUM_FIFO_SHIFT                 (12U)
/*! NUM_FIFO - Number of FIFOs
 *  0b000..N/A
 *  0b001..This design supports one result FIFO.
 *  0b010..This design supports two result FIFOs.
 *  0b011..This design supports three result FIFOs.
 *  0b100..This design supports four result FIFOs.
 */
#define ADC_VERID_NUM_FIFO(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)

#define ADC_VERID_MINOR_MASK                     (0xFF0000U)
#define ADC_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number */
#define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)

#define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
#define ADC_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number */
#define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
#define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
/*! TRIG_NUM - Trigger Number */
#define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)

#define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
#define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
/*! FIFOSIZE - Result FIFO Depth
 *  0b00000001..Result FIFO depth = 1 dataword.
 *  0b00000100..Result FIFO depth = 4 datawords.
 *  0b00001000..Result FIFO depth = 8 datawords.
 *  0b00010000..Result FIFO depth = 16 datawords.
 *  0b00100000..Result FIFO depth = 32 datawords.
 *  0b01000000..Result FIFO depth = 64 datawords.
 */
#define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)

#define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
#define ADC_PARAM_CV_NUM_SHIFT                   (16U)
/*! CV_NUM - Compare Value Number */
#define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)

#define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
#define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
/*! CMD_NUM - Command Buffer Number */
#define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
/*! @} */

/*! @name CTRL - ADC Control Register */
/*! @{ */

#define ADC_CTRL_ADCEN_MASK                      (0x1U)
#define ADC_CTRL_ADCEN_SHIFT                     (0U)
/*! ADCEN - ADC Enable
 *  0b0..ADC is disabled.
 *  0b1..ADC is enabled.
 */
#define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)

#define ADC_CTRL_RST_MASK                        (0x2U)
#define ADC_CTRL_RST_SHIFT                       (1U)
/*! RST - Software Reset
 *  0b0..ADC logic is not reset.
 *  0b1..ADC logic is reset.
 */
#define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)

#define ADC_CTRL_DOZEN_MASK                      (0x4U)
#define ADC_CTRL_DOZEN_SHIFT                     (2U)
/*! DOZEN - Doze Enable
 *  0b0..ADC is enabled in low power mode.
 *  0b1..ADC is disabled in low power mode.
 */
#define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)

#define ADC_CTRL_RSTFIFO0_MASK                   (0x100U)
#define ADC_CTRL_RSTFIFO0_SHIFT                  (8U)
/*! RSTFIFO0 - Reset FIFO 0
 *  0b0..No effect.
 *  0b1..FIFO 0 is reset.
 */
#define ADC_CTRL_RSTFIFO0(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
/*! @} */

/*! @name STAT - ADC Status Register */
/*! @{ */

#define ADC_STAT_RDY0_MASK                       (0x1U)
#define ADC_STAT_RDY0_SHIFT                      (0U)
/*! RDY0 - Result FIFO 0 Ready Flag
 *  0b0..Result FIFO 0 data level not above watermark level.
 *  0b1..Result FIFO 0 holding data above watermark level.
 */
#define ADC_STAT_RDY0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)

#define ADC_STAT_FOF0_MASK                       (0x2U)
#define ADC_STAT_FOF0_SHIFT                      (1U)
/*! FOF0 - Result FIFO 0 Overflow Flag
 *  0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
 */
#define ADC_STAT_FOF0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)

#define ADC_STAT_TEXC_INT_MASK                   (0x100U)
#define ADC_STAT_TEXC_INT_SHIFT                  (8U)
/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
 *  0b0..No trigger exceptions have occurred.
 *  0b1..A trigger exception has occurred and is pending acknowledgement.
 */
#define ADC_STAT_TEXC_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)

#define ADC_STAT_TCOMP_INT_MASK                  (0x200U)
#define ADC_STAT_TCOMP_INT_SHIFT                 (9U)
/*! TCOMP_INT - Interrupt Flag For Trigger Completion
 *  0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
 *  0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
 */
#define ADC_STAT_TCOMP_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)

#define ADC_STAT_ADC_ACTIVE_MASK                 (0x800U)
#define ADC_STAT_ADC_ACTIVE_SHIFT                (11U)
/*! ADC_ACTIVE - ADC Active
 *  0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
 *  0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
 */
#define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)

#define ADC_STAT_TRGACT_MASK                     (0x30000U)
#define ADC_STAT_TRGACT_SHIFT                    (16U)
/*! TRGACT - Trigger Active
 *  0b00..Command (sequence) associated with Trigger 0 currently being executed.
 *  0b01..Command (sequence) associated with Trigger 1 currently being executed.
 *  0b10..Command (sequence) associated with Trigger 2 currently being executed.
 *  0b11..Command (sequence) associated with Trigger 3 currently being executed.
 */
#define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)

#define ADC_STAT_CMDACT_MASK                     (0xF000000U)
#define ADC_STAT_CMDACT_SHIFT                    (24U)
/*! CMDACT - Command Active
 *  0b0000..No command is currently in progress.
 *  0b0001..Command 1 currently being executed.
 *  0b0010..Command 2 currently being executed.
 *  0b0011-0b1111..Associated command number is currently being executed.
 */
#define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
/*! @} */

/*! @name IE - Interrupt Enable Register */
/*! @{ */

#define ADC_IE_FWMIE0_MASK                       (0x1U)
#define ADC_IE_FWMIE0_SHIFT                      (0U)
/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
 *  0b0..FIFO 0 watermark interrupts are not enabled.
 *  0b1..FIFO 0 watermark interrupts are enabled.
 */
#define ADC_IE_FWMIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)

#define ADC_IE_FOFIE0_MASK                       (0x2U)
#define ADC_IE_FOFIE0_SHIFT                      (1U)
/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
 *  0b0..FIFO 0 overflow interrupts are not enabled.
 *  0b1..FIFO 0 overflow interrupts are enabled.
 */
#define ADC_IE_FOFIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)

#define ADC_IE_TEXC_IE_MASK                      (0x100U)
#define ADC_IE_TEXC_IE_SHIFT                     (8U)
/*! TEXC_IE - Trigger Exception Interrupt Enable
 *  0b0..Trigger exception interrupts are disabled.
 *  0b1..Trigger exception interrupts are enabled.
 */
#define ADC_IE_TEXC_IE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)

#define ADC_IE_TCOMP_IE_MASK                     (0xF0000U)
#define ADC_IE_TCOMP_IE_SHIFT                    (16U)
/*! TCOMP_IE - Trigger Completion Interrupt Enable
 *  0b0000..Trigger completion interrupts are disabled.
 *  0b0001..Trigger completion interrupts are enabled for trigger source 0 only.
 *  0b0010..Trigger completion interrupts are enabled for trigger source 1 only.
 *  0b0011-0b1110..Associated trigger completion interrupts are enabled.
 *  0b1111..Trigger completion interrupts are enabled for every trigger source.
 */
#define ADC_IE_TCOMP_IE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
/*! @} */

/*! @name DE - DMA Enable Register */
/*! @{ */

#define ADC_DE_FWMDE0_MASK                       (0x1U)
#define ADC_DE_FWMDE0_SHIFT                      (0U)
/*! FWMDE0 - FIFO 0 Watermark DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define ADC_DE_FWMDE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
/*! @} */

/*! @name CFG - ADC Configuration Register */
/*! @{ */

#define ADC_CFG_TPRICTRL_MASK                    (0x3U)
#define ADC_CFG_TPRICTRL_SHIFT                   (0U)
/*! TPRICTRL - ADC trigger priority control
 *  0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
 *        and the new command specified by the trigger is started.
 *  0b01..If a higher priority trigger is received during command processing, the current command is stopped after
 *        completing the current conversion. If averaging is enabled, the averaging loop will be completed.
 *        However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
 *  0b10..If a higher priority trigger is received during command processing, the current command will be
 *        completed (averaging, looping, compare) before servicing the higher priority trigger.
 *  0b11..RESERVED
 */
#define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)

#define ADC_CFG_PWRSEL_MASK                      (0x30U)
#define ADC_CFG_PWRSEL_SHIFT                     (4U)
/*! PWRSEL - Power Configuration Select
 *  0b00..Lowest power setting.
 *  0b01..Higher power setting than 0b0.
 *  0b10..Higher power setting than 0b1.
 *  0b11..Highest power setting.
 */
#define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)

#define ADC_CFG_REFSEL_MASK                      (0xC0U)
#define ADC_CFG_REFSEL_SHIFT                     (6U)
/*! REFSEL - Voltage Reference Selection
 *  0b00..(Default) Option 1 setting.
 *  0b01..Option 2 setting.
 *  0b10..Option 3 setting.
 *  0b11..Reserved
 */
#define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)

#define ADC_CFG_TRES_MASK                        (0x100U)
#define ADC_CFG_TRES_SHIFT                       (8U)
/*! TRES - Trigger Resume Enable
 *  0b0..Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted.
 *  0b1..Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted.
 */
#define ADC_CFG_TRES(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)

#define ADC_CFG_TCMDRES_MASK                     (0x200U)
#define ADC_CFG_TCMDRES_SHIFT                    (9U)
/*! TCMDRES - Trigger Command Resume
 *  0b0..Trigger sequences interrupted by a high priority trigger exception is automatically restarted.
 *  0b1..Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception.
 */
#define ADC_CFG_TCMDRES(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)

#define ADC_CFG_HPT_EXDI_MASK                    (0x400U)
#define ADC_CFG_HPT_EXDI_SHIFT                   (10U)
/*! HPT_EXDI - High Priority Trigger Exception Disable
 *  0b0..High priority trigger exceptions are enabled.
 *  0b1..High priority trigger exceptions are disabled.
 */
#define ADC_CFG_HPT_EXDI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)

#define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
#define ADC_CFG_PUDLY_SHIFT                      (16U)
/*! PUDLY - Power Up Delay */
#define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)

#define ADC_CFG_PWREN_MASK                       (0x10000000U)
#define ADC_CFG_PWREN_SHIFT                      (28U)
/*! PWREN - ADC Analog Pre-Enable
 *  0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
 *  0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
 *       of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN
 *       is set, and any detected trigger does not begin ADC operation until the power up delay time has passed.
 *       After this initial delay expires the analog will remain pre-enabled, and no additional delays will be
 *       executed.
 */
#define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
/*! @} */

/*! @name PAUSE - ADC Pause Register */
/*! @{ */

#define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
#define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
/*! PAUSEDLY - Pause Delay */
#define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)

#define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
#define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
/*! PAUSEEN - PAUSE Option Enable
 *  0b0..Pause operation disabled
 *  0b1..Pause operation enabled
 */
#define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
/*! @} */

/*! @name SWTRIG - Software Trigger Register */
/*! @{ */

#define ADC_SWTRIG_SWT0_MASK                     (0x1U)
#define ADC_SWTRIG_SWT0_SHIFT                    (0U)
/*! SWT0 - Software trigger 0 event
 *  0b0..No trigger 0 event generated.
 *  0b1..Trigger 0 event generated.
 */
#define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)

#define ADC_SWTRIG_SWT1_MASK                     (0x2U)
#define ADC_SWTRIG_SWT1_SHIFT                    (1U)
/*! SWT1 - Software trigger 1 event
 *  0b0..No trigger 1 event generated.
 *  0b1..Trigger 1 event generated.
 */
#define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)

#define ADC_SWTRIG_SWT2_MASK                     (0x4U)
#define ADC_SWTRIG_SWT2_SHIFT                    (2U)
/*! SWT2 - Software trigger 2 event
 *  0b0..No trigger 2 event generated.
 *  0b1..Trigger 2 event generated.
 */
#define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)

#define ADC_SWTRIG_SWT3_MASK                     (0x8U)
#define ADC_SWTRIG_SWT3_SHIFT                    (3U)
/*! SWT3 - Software trigger 3 event
 *  0b0..No trigger 3 event generated.
 *  0b1..Trigger 3 event generated.
 */
#define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
/*! @} */

/*! @name TSTAT - Trigger Status Register */
/*! @{ */

#define ADC_TSTAT_TEXC_NUM_MASK                  (0xFU)
#define ADC_TSTAT_TEXC_NUM_SHIFT                 (0U)
/*! TEXC_NUM - Trigger Exception Number
 *  0b0000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
 *  0b0001..Trigger 0 has been interrupted by a high priority exception.
 *  0b0010..Trigger 1 has been interrupted by a high priority exception.
 *  0b0011-0b1110..Associated trigger sequence has interrupted by a high priority exception.
 *  0b1111..Every trigger sequence has been interrupted by a high priority exception.
 */
#define ADC_TSTAT_TEXC_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)

#define ADC_TSTAT_TCOMP_FLAG_MASK                (0xF0000U)
#define ADC_TSTAT_TCOMP_FLAG_SHIFT               (16U)
/*! TCOMP_FLAG - Trigger Completion Flag
 *  0b0000..No triggers have been completed. Trigger completion interrupts are disabled.
 *  0b0001..Trigger 0 has been completed and triger 0 has enabled completion interrupts.
 *  0b0010..Trigger 1 has been completed and triger 1 has enabled completion interrupts.
 *  0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts.
 *  0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
 */
#define ADC_TSTAT_TCOMP_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
/*! @} */

/*! @name TCTRL - Trigger Control Register */
/*! @{ */

#define ADC_TCTRL_HTEN_MASK                      (0x1U)
#define ADC_TCTRL_HTEN_SHIFT                     (0U)
/*! HTEN - Trigger enable
 *  0b0..Hardware trigger source disabled
 *  0b1..Hardware trigger source enabled
 */
#define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)

#define ADC_TCTRL_TPRI_MASK                      (0x300U)
#define ADC_TCTRL_TPRI_SHIFT                     (8U)
/*! TPRI - Trigger priority setting
 *  0b00..Set to highest priority, Level 1
 *  0b01-0b10..Set to corresponding priority level
 *  0b11..Set to lowest priority, Level 4
 */
#define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)

#define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
#define ADC_TCTRL_TDLY_SHIFT                     (16U)
/*! TDLY - Trigger delay select */
#define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)

#define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
#define ADC_TCTRL_TCMD_SHIFT                     (24U)
/*! TCMD - Trigger command select
 *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
 *  0b0001..CMD1 is executed
 *  0b0010-0b1110..Corresponding CMD is executed
 *  0b1111..CMD15 is executed
 */
#define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
/*! @} */

/* The count of ADC_TCTRL */
#define ADC_TCTRL_COUNT                          (4U)

/*! @name FCTRL - FIFO Control Register */
/*! @{ */

#define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
#define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
/*! FCOUNT - Result FIFO counter */
#define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)

#define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
#define ADC_FCTRL_FWMARK_SHIFT                   (16U)
/*! FWMARK - Watermark level selection */
#define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
/*! @} */

/*! @name CMDL - ADC Command Low Buffer Register */
/*! @{ */

#define ADC_CMDL_ADCH_MASK                       (0x1FU)
#define ADC_CMDL_ADCH_SHIFT                      (0U)
/*! ADCH - Input channel select
 *  0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
 *  0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
 *  0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
 *  0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
 *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
 *  0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
 *  0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
 */
#define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)

#define ADC_CMDL_ABSEL_MASK                      (0x20U)
#define ADC_CMDL_ABSEL_SHIFT                     (5U)
/*! ABSEL - A-side vs. B-side Select
 *  0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
 *  0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
 */
#define ADC_CMDL_ABSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)

#define ADC_CMDL_DIFF_MASK                       (0x40U)
#define ADC_CMDL_DIFF_SHIFT                      (6U)
/*! DIFF - Differential Mode Enable
 *  0b0..Single-ended mode.
 *  0b1..Differential mode.
 */
#define ADC_CMDL_DIFF(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)

#define ADC_CMDL_CSCALE_MASK                     (0x2000U)
#define ADC_CMDL_CSCALE_SHIFT                    (13U)
/*! CSCALE - Channel Scale
 *  0b0..Scale selected analog channel (Factor of 30/64)
 *  0b1..(Default) Full scale (Factor of 1)
 */
#define ADC_CMDL_CSCALE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
/*! @} */

/* The count of ADC_CMDL */
#define ADC_CMDL_COUNT                           (15U)

/*! @name CMDH - ADC Command High Buffer Register */
/*! @{ */

#define ADC_CMDH_CMPEN_MASK                      (0x3U)
#define ADC_CMDH_CMPEN_SHIFT                     (0U)
/*! CMPEN - Compare Function Enable
 *  0b00..Compare disabled.
 *  0b01..Reserved
 *  0b10..Compare enabled. Store on true.
 *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
 */
#define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)

#define ADC_CMDH_WAIT_TRIG_MASK                  (0x4U)
#define ADC_CMDH_WAIT_TRIG_SHIFT                 (2U)
/*! WAIT_TRIG - Wait for trigger assertion before execution.
 *  0b0..This command will be automatically executed.
 *  0b1..The active trigger must be asserted again before executing this command.
 */
#define ADC_CMDH_WAIT_TRIG(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)

#define ADC_CMDH_LWI_MASK                        (0x80U)
#define ADC_CMDH_LWI_SHIFT                       (7U)
/*! LWI - Loop with Increment
 *  0b0..Auto channel increment disabled
 *  0b1..Auto channel increment enabled
 */
#define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)

#define ADC_CMDH_STS_MASK                        (0x700U)
#define ADC_CMDH_STS_SHIFT                       (8U)
/*! STS - Sample Time Select
 *  0b000..Minimum sample time of 3.5 ADCK cycles.
 *  0b001..3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
 *  0b010..3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
 *  0b011..3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
 *  0b100..3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
 *  0b101..3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
 *  0b110..3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
 *  0b111..3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
 */
#define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)

#define ADC_CMDH_AVGS_MASK                       (0x7000U)
#define ADC_CMDH_AVGS_SHIFT                      (12U)
/*! AVGS - Hardware Average Select
 *  0b000..Single conversion.
 *  0b001..2 conversions averaged.
 *  0b010..4 conversions averaged.
 *  0b011..8 conversions averaged.
 *  0b100..16 conversions averaged.
 *  0b101..32 conversions averaged.
 *  0b110..64 conversions averaged.
 *  0b111..128 conversions averaged.
 */
#define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)

#define ADC_CMDH_LOOP_MASK                       (0xF0000U)
#define ADC_CMDH_LOOP_SHIFT                      (16U)
/*! LOOP - Loop Count Select
 *  0b0000..Looping not enabled. Command executes 1 time.
 *  0b0001..Loop 1 time. Command executes 2 times.
 *  0b0010..Loop 2 times. Command executes 3 times.
 *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
 *  0b1111..Loop 15 times. Command executes 16 times.
 */
#define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)

#define ADC_CMDH_NEXT_MASK                       (0xF000000U)
#define ADC_CMDH_NEXT_SHIFT                      (24U)
/*! NEXT - Next Command Select
 *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
 *          trigger pending, begin command associated with lower priority trigger.
 *  0b0001..Select CMD1 command buffer register as next command.
 *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
 *  0b1111..Select CMD15 command buffer register as next command.
 */
#define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
/*! @} */

/* The count of ADC_CMDH */
#define ADC_CMDH_COUNT                           (15U)

/*! @name CV - Compare Value Register */
/*! @{ */

#define ADC_CV_CVL_MASK                          (0xFFFFU)
#define ADC_CV_CVL_SHIFT                         (0U)
/*! CVL - Compare Value Low. */
#define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)

#define ADC_CV_CVH_MASK                          (0xFFFF0000U)
#define ADC_CV_CVH_SHIFT                         (16U)
/*! CVH - Compare Value High. */
#define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
/*! @} */

/* The count of ADC_CV */
#define ADC_CV_COUNT                             (4U)

/*! @name RESFIFO - ADC Data Result FIFO Register */
/*! @{ */

#define ADC_RESFIFO_D_MASK                       (0xFFFFU)
#define ADC_RESFIFO_D_SHIFT                      (0U)
/*! D - Data result */
#define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)

#define ADC_RESFIFO_TSRC_MASK                    (0x30000U)
#define ADC_RESFIFO_TSRC_SHIFT                   (16U)
/*! TSRC - Trigger Source
 *  0b00..Trigger source 0 initiated this conversion.
 *  0b01..Trigger source 1 initiated this conversion.
 *  0b10-0b10..Corresponding trigger source initiated this conversion.
 *  0b11..Trigger source 3 initiated this conversion.
 */
#define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)

#define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
#define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
/*! LOOPCNT - Loop count value
 *  0b0000..Result is from initial conversion in command.
 *  0b0001..Result is from second conversion in command.
 *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
 *  0b1111..Result is from 16th conversion in command.
 */
#define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)

#define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
#define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
/*! CMDSRC - Command Buffer Source
 *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
 *          prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
 *  0b0001..CMD1 buffer used as control settings for this conversion.
 *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
 *  0b1111..CMD15 buffer used as control settings for this conversion.
 */
#define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)

#define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
#define ADC_RESFIFO_VALID_SHIFT                  (31U)
/*! VALID - FIFO entry is valid
 *  0b0..FIFO is empty. Discard any read from RESFIFO.
 *  0b1..FIFO record read from RESFIFO is valid.
 */
#define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ADC_Register_Masks */


/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base address */
#define ADC0_BASE                                (0x28040000u)
/** Peripheral ADC0 base pointer */
#define ADC0                                     ((ADC_Type *)ADC0_BASE)
/** Peripheral ADC1 base address */
#define ADC1_BASE                                (0x280A2000u)
/** Peripheral ADC1 base pointer */
#define ADC1                                     ((ADC_Type *)ADC1_BASE)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS                            { ADC0, ADC1 }
/* Backward compatibility */
 #define ADC_CTRL_RSTFIFO_MASK                     ADC_CTRL_RSTFIFO0_MASK
 #define ADC_CTRL_RSTFIFO_SHIFT                    ADC_CTRL_RSTFIFO0_SHIFT
 #define ADC_CTRL_RSTFIFO(x)                       ADC_CTRL_RSTFIFO0(x)
 #define ADC_STAT_RDY_MASK                         ADC_STAT_RDY0_MASK
 #define ADC_STAT_RDY_SHIFT                        ADC_STAT_RDY0_SHIFT
 #define ADC_STAT_RDY(x)                           ADC_STAT_RDY0(x)
 #define ADC_STAT_FOF_MASK                         ADC_STAT_FOF0_MASK
 #define ADC_STAT_FOF_SHIFT                        ADC_STAT_FOF0_SHIFT
 #define ADC_STAT_FOF(x)                           ADC_STAT_FOF0(x)
 #define ADC_IE_FWMIE_MASK                         ADC_IE_FWMIE0_MASK
 #define ADC_IE_FWMIE_SHIFT                        ADC_IE_FWMIE0_SHIFT
 #define ADC_IE_FWMIE(x)                           ADC_IE_FWMIE0(x)
 #define ADC_IE_FOFIE_MASK                         ADC_IE_FOFIE0_MASK
 #define ADC_IE_FOFIE_SHIFT                        ADC_IE_FOFIE0_SHIFT
 #define ADC_IE_FOFIE(x)                           ADC_IE_FOFIE0(x)
 #define ADC_DE_FWMDE_MASK                         ADC_DE_FWMDE0_MASK
 #define ADC_DE_FWMDE_SHIFT                        ADC_DE_FWMDE0_SHIFT
 #define ADC_DE_FWMDE(x)                           ADC_DE_FWMDE0(x)


/*!
 * @}
 */ /* end of group ADC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AHB_ADDR_REMAP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AHB_ADDR_REMAP_Peripheral_Access_Layer AHB_ADDR_REMAP Peripheral Access Layer
 * @{
 */

/** AHB_ADDR_REMAP - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[2048];
  __O  uint32_t CR;                                /**< Control, offset: 0x800 */
  __I  uint32_t SR;                                /**< Status tag, offset: 0x804 */
  __I  uint32_t TAG;                               /**< Virtual tag, offset: 0x808 */
  __I  uint32_t DATA;                              /**< Physical Address Data, offset: 0x80C */
} AHB_ADDR_REMAP_Type;

/* ----------------------------------------------------------------------------
   -- AHB_ADDR_REMAP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AHB_ADDR_REMAP_Register_Masks AHB_ADDR_REMAP Register Masks
 * @{
 */

/*! @name CR - Control */
/*! @{ */

#define AHB_ADDR_REMAP_CR_ENB_MASK               (0x1U)
#define AHB_ADDR_REMAP_CR_ENB_SHIFT              (0U)
/*! ENB - Enable Remap.
 *  0b0..The module is disabled and all input AHB addresses & attributes are simply routed to the output AHB address & attributes buses.
 *  0b1..All AHB addresses from the designed bus master (typically a processor core) are remapped using the
 *       constant offset defined by the CR[RADDR] field. AHB accesses from other bus masters are simply passed through
 *       the module as if it was disabled.
 */
#define AHB_ADDR_REMAP_CR_ENB(x)                 (((uint32_t)(((uint32_t)(x)) << AHB_ADDR_REMAP_CR_ENB_SHIFT)) & AHB_ADDR_REMAP_CR_ENB_MASK)

#define AHB_ADDR_REMAP_CR_INV_MASK               (0x4U)
#define AHB_ADDR_REMAP_CR_INV_SHIFT              (2U)
/*! INV - Invalidate Tag register. */
#define AHB_ADDR_REMAP_CR_INV(x)                 (((uint32_t)(((uint32_t)(x)) << AHB_ADDR_REMAP_CR_INV_SHIFT)) & AHB_ADDR_REMAP_CR_INV_MASK)

#define AHB_ADDR_REMAP_CR_LK_MASK                (0x8U)
#define AHB_ADDR_REMAP_CR_LK_SHIFT               (3U)
/*! LK - Sticky lock bit. */
#define AHB_ADDR_REMAP_CR_LK(x)                  (((uint32_t)(((uint32_t)(x)) << AHB_ADDR_REMAP_CR_LK_SHIFT)) & AHB_ADDR_REMAP_CR_LK_MASK)

#define AHB_ADDR_REMAP_CR_RADDR_MASK             (0xFFFFF80U)
#define AHB_ADDR_REMAP_CR_RADDR_SHIFT            (7U)
/*! RADDR - Remap address. */
#define AHB_ADDR_REMAP_CR_RADDR(x)               (((uint32_t)(((uint32_t)(x)) << AHB_ADDR_REMAP_CR_RADDR_SHIFT)) & AHB_ADDR_REMAP_CR_RADDR_MASK)
/*! @} */

/*! @name SR - Status tag */
/*! @{ */

#define AHB_ADDR_REMAP_SR_ENB_MASK               (0x1U)
#define AHB_ADDR_REMAP_SR_ENB_SHIFT              (0U)
/*! ENB - Enable Remap.
 *  0b0..The module is disabled and all input AHB addresses & attributes are simply routed to the output AHB address & attributes buses.
 *  0b1..All AHB addresses from the designed bus master (typically a processor core) are remapped using the
 *       constant offset defined by the CR[RADDR] field. AHB accesses from other bus masters are simply passed through
 *       the module as if it was disabled.
 */
#define AHB_ADDR_REMAP_SR_ENB(x)                 (((uint32_t)(((uint32_t)(x)) << AHB_ADDR_REMAP_SR_ENB_SHIFT)) & AHB_ADDR_REMAP_SR_ENB_MASK)

#define AHB_ADDR_REMAP_SR_INV_MASK               (0x4U)
#define AHB_ADDR_REMAP_SR_INV_SHIFT              (2U)
/*! INV - Invalidate Tag register. */
#define AHB_ADDR_REMAP_SR_INV(x)                 (((uint32_t)(((uint32_t)(x)) << AHB_ADDR_REMAP_SR_INV_SHIFT)) & AHB_ADDR_REMAP_SR_INV_MASK)

#define AHB_ADDR_REMAP_SR_LK_MASK                (0x8U)
#define AHB_ADDR_REMAP_SR_LK_SHIFT               (3U)
/*! LK - Sticky lock bit. */
#define AHB_ADDR_REMAP_SR_LK(x)                  (((uint32_t)(((uint32_t)(x)) << AHB_ADDR_REMAP_SR_LK_SHIFT)) & AHB_ADDR_REMAP_SR_LK_MASK)

#define AHB_ADDR_REMAP_SR_RADDR_MASK             (0xFFFFF80U)
#define AHB_ADDR_REMAP_SR_RADDR_SHIFT            (7U)
/*! RADDR - Remap address. */
#define AHB_ADDR_REMAP_SR_RADDR(x)               (((uint32_t)(((uint32_t)(x)) << AHB_ADDR_REMAP_SR_RADDR_SHIFT)) & AHB_ADDR_REMAP_SR_RADDR_MASK)
/*! @} */

/*! @name TAG - Virtual tag */
/*! @{ */

#define AHB_ADDR_REMAP_TAG_VLD_MASK              (0x1U)
#define AHB_ADDR_REMAP_TAG_VLD_SHIFT             (0U)
/*! VLD - This bit indicates the validity of the entry.
 *  0b0..Disabled.
 *  0b1..Enabled.
 */
#define AHB_ADDR_REMAP_TAG_VLD(x)                (((uint32_t)(((uint32_t)(x)) << AHB_ADDR_REMAP_TAG_VLD_SHIFT)) & AHB_ADDR_REMAP_TAG_VLD_MASK)

#define AHB_ADDR_REMAP_TAG_VADDR_MASK            (0xFFFFFF80U)
#define AHB_ADDR_REMAP_TAG_VADDR_SHIFT           (7U)
/*! VADDR - This bit indicates the virtual address. */
#define AHB_ADDR_REMAP_TAG_VADDR(x)              (((uint32_t)(((uint32_t)(x)) << AHB_ADDR_REMAP_TAG_VADDR_SHIFT)) & AHB_ADDR_REMAP_TAG_VADDR_MASK)
/*! @} */

/*! @name DATA - Physical Address Data */
/*! @{ */

#define AHB_ADDR_REMAP_DATA_VADDRL_MASK          (0x7FU)
#define AHB_ADDR_REMAP_DATA_VADDRL_SHIFT         (0U)
/*! VADDRL - This bit indicates the low portion of the virtual address. */
#define AHB_ADDR_REMAP_DATA_VADDRL(x)            (((uint32_t)(((uint32_t)(x)) << AHB_ADDR_REMAP_DATA_VADDRL_SHIFT)) & AHB_ADDR_REMAP_DATA_VADDRL_MASK)

#define AHB_ADDR_REMAP_DATA_PADDR_MASK           (0xFFFFF80U)
#define AHB_ADDR_REMAP_DATA_PADDR_SHIFT          (7U)
/*! PADDR - This bit indicates the physical address. */
#define AHB_ADDR_REMAP_DATA_PADDR(x)             (((uint32_t)(((uint32_t)(x)) << AHB_ADDR_REMAP_DATA_PADDR_SHIFT)) & AHB_ADDR_REMAP_DATA_PADDR_MASK)

#define AHB_ADDR_REMAP_DATA_VADDRH_MASK          (0xF0000000U)
#define AHB_ADDR_REMAP_DATA_VADDRH_SHIFT         (28U)
/*! VADDRH - This bit indicates the high portion of the virtual address. */
#define AHB_ADDR_REMAP_DATA_VADDRH(x)            (((uint32_t)(((uint32_t)(x)) << AHB_ADDR_REMAP_DATA_VADDRH_SHIFT)) & AHB_ADDR_REMAP_DATA_VADDRH_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AHB_ADDR_REMAP_Register_Masks */


/* AHB_ADDR_REMAP - Peripheral instance base addresses */
/** Peripheral ADDR_REMAP0 base address */
#define ADDR_REMAP0_BASE                         (0x28039800u)
/** Peripheral ADDR_REMAP0 base pointer */
#define ADDR_REMAP0                              ((AHB_ADDR_REMAP_Type *)ADDR_REMAP0_BASE)
/** Peripheral ADDR_REMAP1 base address */
#define ADDR_REMAP1_BASE                         (0x29810800u)
/** Peripheral ADDR_REMAP1 base pointer */
#define ADDR_REMAP1                              ((AHB_ADDR_REMAP_Type *)ADDR_REMAP1_BASE)
/** Array initializer of AHB_ADDR_REMAP peripheral base addresses */
#define AHB_ADDR_REMAP_BASE_ADDRS                { ADDR_REMAP0_BASE, ADDR_REMAP1_BASE }
/** Array initializer of AHB_ADDR_REMAP peripheral base pointers */
#define AHB_ADDR_REMAP_BASE_PTRS                 { ADDR_REMAP0, ADDR_REMAP1 }

/*!
 * @}
 */ /* end of group AHB_ADDR_REMAP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AXBS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
 * @{
 */

/** AXBS - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0x100 */
    __IO uint32_t PRS;                               /**< Priority Slave Registers, array offset: 0x0, array step: 0x100 */
         uint8_t RESERVED_0[12];
    __IO uint32_t CRS;                               /**< Control Register, array offset: 0x10, array step: 0x100 */
         uint8_t RESERVED_1[236];
  } SLAVE[8];
} AXBS_Type;

/* ----------------------------------------------------------------------------
   -- AXBS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AXBS_Register_Masks AXBS Register Masks
 * @{
 */

/*! @name PRS - Priority Slave Registers */
/*! @{ */

#define AXBS_PRS_M0_MASK                         (0x7U)
#define AXBS_PRS_M0_SHIFT                        (0U)
/*! M0 - Master 0 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)

#define AXBS_PRS_M1_MASK                         (0x70U)
#define AXBS_PRS_M1_SHIFT                        (4U)
/*! M1 - Master 1 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)

#define AXBS_PRS_M2_MASK                         (0x700U)
#define AXBS_PRS_M2_SHIFT                        (8U)
/*! M2 - Master 2 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)

#define AXBS_PRS_M3_MASK                         (0x7000U)
#define AXBS_PRS_M3_SHIFT                        (12U)
/*! M3 - Master 3 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)

#define AXBS_PRS_M4_MASK                         (0x70000U)
#define AXBS_PRS_M4_SHIFT                        (16U)
/*! M4 - Master 4 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)

#define AXBS_PRS_M5_MASK                         (0x700000U)
#define AXBS_PRS_M5_SHIFT                        (20U)
/*! M5 - Master 5 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)

#define AXBS_PRS_M6_MASK                         (0x7000000U)
#define AXBS_PRS_M6_SHIFT                        (24U)
/*! M6 - Master 6 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS_M6(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)

#define AXBS_PRS_M7_MASK                         (0x70000000U)
#define AXBS_PRS_M7_SHIFT                        (28U)
/*! M7 - Master 7 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS_M7(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M7_SHIFT)) & AXBS_PRS_M7_MASK)
/*! @} */

/* The count of AXBS_PRS */
#define AXBS_PRS_COUNT                           (8U)

/*! @name CRS - Control Register */
/*! @{ */

#define AXBS_CRS_PARK_MASK                       (0x7U)
#define AXBS_CRS_PARK_SHIFT                      (0U)
/*! PARK - Park
 *  0b000..Park on master port M0
 *  0b001..Park on master port M1
 *  0b010..Park on master port M2
 *  0b011..Park on master port M3
 *  0b100..Park on master port M4
 *  0b101..Park on master port M5
 *  0b110..Park on master port M6
 *  0b111..Park on master port M7
 */
#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)

#define AXBS_CRS_PCTL_MASK                       (0x30U)
#define AXBS_CRS_PCTL_SHIFT                      (4U)
/*! PCTL - Parking Control
 *  0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field.
 *  0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port.
 *  0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter
 *        drives all outputs to a constant safe state.
 *  0b11..Reserved
 */
#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)

#define AXBS_CRS_ARB_MASK                        (0x300U)
#define AXBS_CRS_ARB_SHIFT                       (8U)
/*! ARB - Arbitration Mode
 *  0b00..Fixed priority
 *  0b01..Round-robin (rotating) priority
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)

#define AXBS_CRS_HPE0_MASK                       (0x10000U)
#define AXBS_CRS_HPE0_SHIFT                      (16U)
/*! HPE0 - High Priority Elevation 0
 *  0b0..Master high-priority elevation for master 0. is disabled on this slave port.
 *  0b1..Master high-priority elevation for master 0. is enabled on this slave port.
 */
#define AXBS_CRS_HPE0(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE0_SHIFT)) & AXBS_CRS_HPE0_MASK)

#define AXBS_CRS_HPE1_MASK                       (0x20000U)
#define AXBS_CRS_HPE1_SHIFT                      (17U)
/*! HPE1 - High Priority Elevation 1
 *  0b0..Master high-priority elevation for master 1. is disabled on this slave port.
 *  0b1..Master high-priority elevation for master 1. is enabled on this slave port.
 */
#define AXBS_CRS_HPE1(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE1_SHIFT)) & AXBS_CRS_HPE1_MASK)

#define AXBS_CRS_HPE2_MASK                       (0x40000U)
#define AXBS_CRS_HPE2_SHIFT                      (18U)
/*! HPE2 - High Priority Elevation 2
 *  0b0..Master high-priority elevation for master 2. is disabled on this slave port.
 *  0b1..Master high-priority elevation for master 2. is enabled on this slave port.
 */
#define AXBS_CRS_HPE2(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE2_SHIFT)) & AXBS_CRS_HPE2_MASK)

#define AXBS_CRS_HPE3_MASK                       (0x80000U)
#define AXBS_CRS_HPE3_SHIFT                      (19U)
/*! HPE3 - High Priority Elevation 3
 *  0b0..Master high-priority elevation for master 3. is disabled on this slave port.
 *  0b1..Master high-priority elevation for master 3. is enabled on this slave port.
 */
#define AXBS_CRS_HPE3(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE3_SHIFT)) & AXBS_CRS_HPE3_MASK)

#define AXBS_CRS_HPE4_MASK                       (0x100000U)
#define AXBS_CRS_HPE4_SHIFT                      (20U)
/*! HPE4 - High Priority Elevation 4
 *  0b0..Master high-priority elevation for master 4. is disabled on this slave port.
 *  0b1..Master high-priority elevation for master 4. is enabled on this slave port.
 */
#define AXBS_CRS_HPE4(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE4_SHIFT)) & AXBS_CRS_HPE4_MASK)

#define AXBS_CRS_HPE5_MASK                       (0x200000U)
#define AXBS_CRS_HPE5_SHIFT                      (21U)
/*! HPE5 - High Priority Elevation 5
 *  0b0..Master high-priority elevation for master 5. is disabled on this slave port.
 *  0b1..Master high-priority elevation for master 5. is enabled on this slave port.
 */
#define AXBS_CRS_HPE5(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE5_SHIFT)) & AXBS_CRS_HPE5_MASK)

#define AXBS_CRS_HPE6_MASK                       (0x400000U)
#define AXBS_CRS_HPE6_SHIFT                      (22U)
/*! HPE6 - High Priority Elevation 6
 *  0b0..Master high-priority elevation for master 6. is disabled on this slave port.
 *  0b1..Master high-priority elevation for master 6. is enabled on this slave port.
 */
#define AXBS_CRS_HPE6(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE6_SHIFT)) & AXBS_CRS_HPE6_MASK)

#define AXBS_CRS_HPE7_MASK                       (0x800000U)
#define AXBS_CRS_HPE7_SHIFT                      (23U)
/*! HPE7 - High Priority Elevation 7
 *  0b0..Master high-priority elevation for master 7. is disabled on this slave port.
 *  0b1..Master high-priority elevation for master 7. is enabled on this slave port.
 */
#define AXBS_CRS_HPE7(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE7_SHIFT)) & AXBS_CRS_HPE7_MASK)

#define AXBS_CRS_HLP_MASK                        (0x40000000U)
#define AXBS_CRS_HLP_SHIFT                       (30U)
/*! HLP - Halt Low Priority
 *  0b0..The low-power mode request has the highest priority for arbitration on this slave port.
 *  0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port.
 */
#define AXBS_CRS_HLP(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)

#define AXBS_CRS_RO_MASK                         (0x80000000U)
#define AXBS_CRS_RO_SHIFT                        (31U)
/*! RO - Read Only
 *  0b0..The CRSn and PRSn registers are writeable
 *  0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the
 *       registers and result in a bus error response).
 */
#define AXBS_CRS_RO(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
/*! @} */

/* The count of AXBS_CRS */
#define AXBS_CRS_COUNT                           (8U)


/*!
 * @}
 */ /* end of group AXBS_Register_Masks */


/* AXBS - Peripheral instance base addresses */
/** Peripheral AXBS0 base address */
#define AXBS0_BASE                               (0x28000000u)
/** Peripheral AXBS0 base pointer */
#define AXBS0                                    ((AXBS_Type *)AXBS0_BASE)
/** Peripheral AXBS1 base address */
#define AXBS1_BASE                               (0x29000000u)
/** Peripheral AXBS1 base pointer */
#define AXBS1                                    ((AXBS_Type *)AXBS1_BASE)
/** Array initializer of AXBS peripheral base addresses */
#define AXBS_BASE_ADDRS                          { AXBS0_BASE, AXBS1_BASE }
/** Array initializer of AXBS peripheral base pointers */
#define AXBS_BASE_PTRS                           { AXBS0, AXBS1 }

/*!
 * @}
 */ /* end of group AXBS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- BBNSM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup BBNSM_Peripheral_Access_Layer BBNSM Peripheral Access Layer
 * @{
 */

/** BBNSM - Register Layout Typedef */
typedef struct {
  __I  uint32_t BBNSM_VID;                         /**< BBNSM Version ID Register, offset: 0x0 */
  __I  uint32_t BBNSM_FEATURES;                    /**< BBNSM Features Register, offset: 0x4 */
  __IO uint32_t BBNSM_CTRL;                        /**< BBNSM Control Register, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t BBNSM_INT_EN;                      /**< BBNSM Interrupt Enable Register, offset: 0x10 */
  __IO uint32_t BBNSM_EVENTS;                      /**< BBNSM Events Register, offset: 0x14 */
       uint8_t RESERVED_1[12];
  __IO uint32_t BBNSM_PAD_CTRL;                    /**< BBNSM External Pad Control Register, offset: 0x24 */
       uint8_t RESERVED_2[24];
  __IO uint32_t BBNSM_RTC_LS;                      /**< BBNSM Real-Time Counter LS Register, offset: 0x40 */
  __IO uint32_t BBNSM_RTC_MS;                      /**< BBNSM Real-Time Counter MS Register, offset: 0x44 */
       uint8_t RESERVED_3[8];
  __IO uint32_t BBNSM_TA;                          /**< BBNSM Time Alarm Register, offset: 0x50 */
       uint8_t RESERVED_4[684];
  __IO uint32_t GPR[16];                           /**< General Purpose Register Word 0..General Purpose Register Word 15, array offset: 0x300, array step: 0x4 */
} BBNSM_Type;

/* ----------------------------------------------------------------------------
   -- BBNSM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup BBNSM_Register_Masks BBNSM Register Masks
 * @{
 */

/*! @name BBNSM_VID - BBNSM Version ID Register */
/*! @{ */

#define BBNSM_BBNSM_VID_BBNSM_IPID_MASK          (0xFFU)
#define BBNSM_BBNSM_VID_BBNSM_IPID_SHIFT         (0U)
/*! BBNSM_IPID - BBNSM IP ID */
#define BBNSM_BBNSM_VID_BBNSM_IPID(x)            (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_VID_BBNSM_IPID_SHIFT)) & BBNSM_BBNSM_VID_BBNSM_IPID_MASK)

#define BBNSM_BBNSM_VID_BBNSM_REV_MASK           (0xFF00U)
#define BBNSM_BBNSM_VID_BBNSM_REV_SHIFT          (8U)
/*! BBNSM_REV - BBNSM Revision */
#define BBNSM_BBNSM_VID_BBNSM_REV(x)             (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_VID_BBNSM_REV_SHIFT)) & BBNSM_BBNSM_VID_BBNSM_REV_MASK)

#define BBNSM_BBNSM_VID_BBNSM_VID_MASK           (0xFF0000U)
#define BBNSM_BBNSM_VID_BBNSM_VID_SHIFT          (16U)
/*! BBNSM_VID - BBNSM Version ID */
#define BBNSM_BBNSM_VID_BBNSM_VID(x)             (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_VID_BBNSM_VID_SHIFT)) & BBNSM_BBNSM_VID_BBNSM_VID_MASK)
/*! @} */

/*! @name BBNSM_FEATURES - BBNSM Features Register */
/*! @{ */

#define BBNSM_BBNSM_FEATURES_GPR_SZ_MASK         (0xFCU)
#define BBNSM_BBNSM_FEATURES_GPR_SZ_SHIFT        (2U)
/*! GPR_SZ - GPR Register Array Size
 *  0b000000..This version of BBNSM does not implement a general-purpose register array.
 *  *..The number of 32-bit words implemented in the general-purpose register array.
 */
#define BBNSM_BBNSM_FEATURES_GPR_SZ(x)           (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_FEATURES_GPR_SZ_SHIFT)) & BBNSM_BBNSM_FEATURES_GPR_SZ_MASK)
/*! @} */

/*! @name BBNSM_CTRL - BBNSM Control Register */
/*! @{ */

#define BBNSM_BBNSM_CTRL_RTC_EN_MASK             (0x3U)
#define BBNSM_BBNSM_CTRL_RTC_EN_SHIFT            (0U)
/*! RTC_EN - Real-Time Counter Enable
 *  0b01..Disable the real-time counter.
 *  0b10..Enable the real-time counter.
 */
#define BBNSM_BBNSM_CTRL_RTC_EN(x)               (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_RTC_EN_SHIFT)) & BBNSM_BBNSM_CTRL_RTC_EN_MASK)

#define BBNSM_BBNSM_CTRL_TA_EN_MASK              (0xCU)
#define BBNSM_BBNSM_CTRL_TA_EN_SHIFT             (2U)
/*! TA_EN - Time Alarm Enable
 *  0b01..Disable the time alarm.
 *  0b10..Enable the time alarm. A time alarm event occurs if the value in the real-time counter register is equal
 *        to the value in the time alarm register.
 */
#define BBNSM_BBNSM_CTRL_TA_EN(x)                (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_TA_EN_SHIFT)) & BBNSM_BBNSM_CTRL_TA_EN_MASK)

#define BBNSM_BBNSM_CTRL_CAL_EN_MASK             (0x10U)
#define BBNSM_BBNSM_CTRL_CAL_EN_SHIFT            (4U)
/*! CAL_EN - Calibration Enable
 *  0b0..RTC Time calibration is disabled.
 *  0b1..RTC Time calibration is enabled.
 */
#define BBNSM_BBNSM_CTRL_CAL_EN(x)               (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_CAL_EN_SHIFT)) & BBNSM_BBNSM_CTRL_CAL_EN_MASK)

#define BBNSM_BBNSM_CTRL_CAL_VAL_MASK            (0x1F00U)
#define BBNSM_BBNSM_CTRL_CAL_VAL_SHIFT           (8U)
/*! CAL_VAL - Calibration Value
 *  0b01111..+15 counts per each 32768 ticks of the counter clock.
 *  0b00010..+2 counts per each 32768 ticks of the counter clock.
 *  0b00001..+1 counts per each 32768 ticks of the counter clock.
 *  0b00000..+0 counts per each 32768 ticks of the counter clock.
 *  0b11111..-1 counts per each 32768 ticks of the counter clock.
 *  0b11110..-2 counts per each 32768 ticks of the counter clock.
 *  0b10001..-15 counts per each 32768 ticks of the counter clock.
 *  0b10000..-16 counts per each 32768 ticks of the counter clock.
 */
#define BBNSM_BBNSM_CTRL_CAL_VAL(x)              (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_CAL_VAL_SHIFT)) & BBNSM_BBNSM_CTRL_CAL_VAL_MASK)

#define BBNSM_BBNSM_CTRL_BTN_TIMEOUT_MASK        (0x30000U)
#define BBNSM_BBNSM_CTRL_BTN_TIMEOUT_SHIFT       (16U)
/*! BTN_TIMEOUT - Button Press Timeout
 *  0b00..5 seconds.
 *  0b01..10 seconds.
 *  0b10..15 seconds.
 *  0b11..Timeout disabled. Long button presses will not request a power down.
 */
#define BBNSM_BBNSM_CTRL_BTN_TIMEOUT(x)          (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_BTN_TIMEOUT_SHIFT)) & BBNSM_BBNSM_CTRL_BTN_TIMEOUT_MASK)

#define BBNSM_BBNSM_CTRL_DEBOUNCE_MASK           (0xC0000U)
#define BBNSM_BBNSM_CTRL_DEBOUNCE_SHIFT          (18U)
/*! DEBOUNCE - Debounce Time
 *  0b00..50 milliseconds.
 *  0b01..100 milliseconds.
 *  0b10..500 milliseconds.
 *  0b11..0 milliseconds.
 */
#define BBNSM_BBNSM_CTRL_DEBOUNCE(x)             (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_DEBOUNCE_SHIFT)) & BBNSM_BBNSM_CTRL_DEBOUNCE_MASK)

#define BBNSM_BBNSM_CTRL_TURN_ON_TIME_MASK       (0x300000U)
#define BBNSM_BBNSM_CTRL_TURN_ON_TIME_SHIFT      (20U)
/*! TURN_ON_TIME - Turn-On Time
 *  0b00..500 milliseconds.
 *  0b01..50 milliseconds.
 *  0b10..100 milliseconds.
 *  0b11..0 milliseconds.
 */
#define BBNSM_BBNSM_CTRL_TURN_ON_TIME(x)         (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_TURN_ON_TIME_SHIFT)) & BBNSM_BBNSM_CTRL_TURN_ON_TIME_MASK)

#define BBNSM_BBNSM_CTRL_PK_EN_MASK              (0x400000U)
#define BBNSM_BBNSM_CTRL_PK_EN_SHIFT             (22U)
/*! PK_EN - PMIC On Request Enable
 *  0b0..PMIC On Request is disabled.
 *  0b1..PMIC On Request is enabled.
 */
#define BBNSM_BBNSM_CTRL_PK_EN(x)                (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_PK_EN_SHIFT)) & BBNSM_BBNSM_CTRL_PK_EN_MASK)

#define BBNSM_BBNSM_CTRL_PK_OVR_MASK             (0x800000U)
#define BBNSM_BBNSM_CTRL_PK_OVR_SHIFT            (23U)
/*! PK_OVR - PMIC On Request Override
 *  0b0..PMIC On Request Override is disabled.
 *  0b1..PMIC On Request Override is enabled.
 */
#define BBNSM_BBNSM_CTRL_PK_OVR(x)               (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_PK_OVR_SHIFT)) & BBNSM_BBNSM_CTRL_PK_OVR_MASK)

#define BBNSM_BBNSM_CTRL_DP_EN_MASK              (0x1000000U)
#define BBNSM_BBNSM_CTRL_DP_EN_SHIFT             (24U)
/*! DP_EN - Dumb PMIC Enable
 *  0b0..Smart PMIC is enabled.
 *  0b1..Dumb PMIC is enabled.
 */
#define BBNSM_BBNSM_CTRL_DP_EN(x)                (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_DP_EN_SHIFT)) & BBNSM_BBNSM_CTRL_DP_EN_MASK)

#define BBNSM_BBNSM_CTRL_TOSP_MASK               (0x2000000U)
#define BBNSM_BBNSM_CTRL_TOSP_SHIFT              (25U)
/*! TOSP - Turn Off System Power
 *  0b0..Leave system power on.
 *  0b1..Turn off system power when Dumb PMIC is enabled.
 */
#define BBNSM_BBNSM_CTRL_TOSP(x)                 (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_TOSP_SHIFT)) & BBNSM_BBNSM_CTRL_TOSP_MASK)

#define BBNSM_BBNSM_CTRL_BTN_CONFIG_MASK         (0x1C000000U)
#define BBNSM_BBNSM_CTRL_BTN_CONFIG_SHIFT        (26U)
/*! BTN_CONFIG - Button Configuration.
 *  0b000..Button signal is active high
 *  0b001..Button signal is active low
 *  0b010..Button signal is active on the falling edge
 *  0b011..Button signal is active on the rising edge
 *  0b100..Button signal is active on any edge
 */
#define BBNSM_BBNSM_CTRL_BTN_CONFIG(x)           (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_BTN_CONFIG_SHIFT)) & BBNSM_BBNSM_CTRL_BTN_CONFIG_MASK)
/*! @} */

/*! @name BBNSM_INT_EN - BBNSM Interrupt Enable Register */
/*! @{ */

#define BBNSM_BBNSM_INT_EN_RTC_INT_EN_MASK       (0x3U)
#define BBNSM_BBNSM_INT_EN_RTC_INT_EN_SHIFT      (0U)
/*! RTC_INT_EN - Real-Time Counter Rollover Interrupt Enable
 *  0b01..Do not issue an interrupt when RTC has rolled over. The interrupt is cleared when this value is written.
 *  0b10..Issue an interrupt when RTC has rolled over.
 */
#define BBNSM_BBNSM_INT_EN_RTC_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_INT_EN_RTC_INT_EN_SHIFT)) & BBNSM_BBNSM_INT_EN_RTC_INT_EN_MASK)

#define BBNSM_BBNSM_INT_EN_TA_INT_EN_MASK        (0xCU)
#define BBNSM_BBNSM_INT_EN_TA_INT_EN_SHIFT       (2U)
/*! TA_INT_EN - Time Alarm Interrupt Enable
 *  0b01..Do not issue an interrupt when RTC has rolled over. The interrupt is cleared when this value is written.
 *  0b10..Issue an interrupt when RTC has rolled over.
 */
#define BBNSM_BBNSM_INT_EN_TA_INT_EN(x)          (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_INT_EN_TA_INT_EN_SHIFT)) & BBNSM_BBNSM_INT_EN_TA_INT_EN_MASK)

#define BBNSM_BBNSM_INT_EN_BTN_INT_EN_MASK       (0x10U)
#define BBNSM_BBNSM_INT_EN_BTN_INT_EN_SHIFT      (4U)
/*! BTN_INT_EN - Button Interrupt Enable
 *  0b0..Interrupt Disabled
 *  0b1..Interrupt Enabled
 */
#define BBNSM_BBNSM_INT_EN_BTN_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_INT_EN_BTN_INT_EN_SHIFT)) & BBNSM_BBNSM_INT_EN_BTN_INT_EN_MASK)
/*! @} */

/*! @name BBNSM_EVENTS - BBNSM Events Register */
/*! @{ */

#define BBNSM_BBNSM_EVENTS_RTC_ROLL_MASK         (0x3U)
#define BBNSM_BBNSM_EVENTS_RTC_ROLL_SHIFT        (0U)
/*! RTC_ROLL - Real-Time Counter Rollover Event
 *  0b01..The real-time counter has not rolled over.
 *  0b10..The real-time counter has rolled over.
 */
#define BBNSM_BBNSM_EVENTS_RTC_ROLL(x)           (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_RTC_ROLL_SHIFT)) & BBNSM_BBNSM_EVENTS_RTC_ROLL_MASK)

#define BBNSM_BBNSM_EVENTS_TA_MASK               (0xCU)
#define BBNSM_BBNSM_EVENTS_TA_SHIFT              (2U)
/*! TA - Time Alarm Event
 *  0b01..The real-time counter has not reached the alarm time.
 *  0b10..The real-time counter has reached the alarm time.
 */
#define BBNSM_BBNSM_EVENTS_TA(x)                 (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_TA_SHIFT)) & BBNSM_BBNSM_EVENTS_TA_MASK)

#define BBNSM_BBNSM_EVENTS_EMG_OFF_MASK          (0x10U)
#define BBNSM_BBNSM_EVENTS_EMG_OFF_SHIFT         (4U)
/*! EMG_OFF - Emergency Off Event
 *  0b0..An emergency power off has not been requested.
 *  0b1..An emergency power off has been requested.
 */
#define BBNSM_BBNSM_EVENTS_EMG_OFF(x)            (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_EMG_OFF_SHIFT)) & BBNSM_BBNSM_EVENTS_EMG_OFF_MASK)

#define BBNSM_BBNSM_EVENTS_PWR_OFF_MASK          (0x20U)
#define BBNSM_BBNSM_EVENTS_PWR_OFF_SHIFT         (5U)
/*! PWR_OFF - Set Power Off Event
 *  0b0..The set_pwr_off_irq interrupt has not been requested.
 *  0b1..The set_pwr_off_irq interrupt has been requested.
 */
#define BBNSM_BBNSM_EVENTS_PWR_OFF(x)            (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_PWR_OFF_SHIFT)) & BBNSM_BBNSM_EVENTS_PWR_OFF_MASK)

#define BBNSM_BBNSM_EVENTS_PWR_ON_MASK           (0x40U)
#define BBNSM_BBNSM_EVENTS_PWR_ON_SHIFT          (6U)
/*! PWR_ON - Set Power On Event
 *  0b0..The set_pwr_on_irq interrupt has not been requested.
 *  0b1..The set_pwr_on_irq interrupt has been requested.
 */
#define BBNSM_BBNSM_EVENTS_PWR_ON(x)             (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_PWR_ON_SHIFT)) & BBNSM_BBNSM_EVENTS_PWR_ON_MASK)

#define BBNSM_BBNSM_EVENTS_BTN_MASK              (0x80U)
#define BBNSM_BBNSM_EVENTS_BTN_SHIFT             (7U)
/*! BTN - Button
 *  0b0..BTN not pressed
 *  0b1..BTN pressed
 */
#define BBNSM_BBNSM_EVENTS_BTN(x)                (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_BTN_SHIFT)) & BBNSM_BBNSM_EVENTS_BTN_MASK)

#define BBNSM_BBNSM_EVENTS_BI_MASK               (0x100U)
#define BBNSM_BBNSM_EVENTS_BI_SHIFT              (8U)
/*! BI - Button Interrupt */
#define BBNSM_BBNSM_EVENTS_BI(x)                 (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_BI_SHIFT)) & BBNSM_BBNSM_EVENTS_BI_MASK)
/*! @} */

/*! @name BBNSM_PAD_CTRL - BBNSM External Pad Control Register */
/*! @{ */

#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_MASK      (0x1U)
#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_SHIFT     (0U)
/*! PAD_CTRL0 - Control I/O Pads
 *  0b0..SoC specified pad control data.
 *  0b1..SoC specified pad control data.
 */
#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0(x)        (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_MASK)
/*! @} */

/*! @name BBNSM_RTC_LS - BBNSM Real-Time Counter LS Register */
/*! @{ */

#define BBNSM_BBNSM_RTC_LS_RTC_MASK              (0xFFFFFFFFU)
#define BBNSM_BBNSM_RTC_LS_RTC_SHIFT             (0U)
/*! RTC - Real-time Counter */
#define BBNSM_BBNSM_RTC_LS_RTC(x)                (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_RTC_LS_RTC_SHIFT)) & BBNSM_BBNSM_RTC_LS_RTC_MASK)
/*! @} */

/*! @name BBNSM_RTC_MS - BBNSM Real-Time Counter MS Register */
/*! @{ */

#define BBNSM_BBNSM_RTC_MS_RTC_MASK              (0x7FFFU)
#define BBNSM_BBNSM_RTC_MS_RTC_SHIFT             (0U)
/*! RTC - Real-Time Counter */
#define BBNSM_BBNSM_RTC_MS_RTC(x)                (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_RTC_MS_RTC_SHIFT)) & BBNSM_BBNSM_RTC_MS_RTC_MASK)
/*! @} */

/*! @name BBNSM_TA - BBNSM Time Alarm Register */
/*! @{ */

#define BBNSM_BBNSM_TA_TA_MASK                   (0xFFFFFFFFU)
#define BBNSM_BBNSM_TA_TA_SHIFT                  (0U)
/*! TA - Time Alarm Value */
#define BBNSM_BBNSM_TA_TA(x)                     (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_TA_TA_SHIFT)) & BBNSM_BBNSM_TA_TA_MASK)
/*! @} */

/*! @name GPR - General Purpose Register Word 0..General Purpose Register Word 15 */
/*! @{ */

#define BBNSM_GPR_GPR_MASK                       (0xFFFFFFFFU)
#define BBNSM_GPR_GPR_SHIFT                      (0U)
/*! GPR - 32 bits of the GPR. */
#define BBNSM_GPR_GPR(x)                         (((uint32_t)(((uint32_t)(x)) << BBNSM_GPR_GPR_SHIFT)) & BBNSM_GPR_GPR_MASK)
/*! @} */

/* The count of BBNSM_GPR */
#define BBNSM_GPR_COUNT                          (16U)


/*!
 * @}
 */ /* end of group BBNSM_Register_Masks */


/* BBNSM - Peripheral instance base addresses */
/** Peripheral BBNSM base address */
#define BBNSM_BASE                               (0x28038000u)
/** Peripheral BBNSM base pointer */
#define BBNSM                                    ((BBNSM_Type *)BBNSM_BASE)
/** Array initializer of BBNSM peripheral base addresses */
#define BBNSM_BASE_ADDRS                         { BBNSM_BASE }
/** Array initializer of BBNSM peripheral base pointers */
#define BBNSM_BASE_PTRS                          { BBNSM }

/*!
 * @}
 */ /* end of group BBNSM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CACHE64_CTRL Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_CTRL_Peripheral_Access_Layer CACHE64_CTRL Peripheral Access Layer
 * @{
 */

/** CACHE64_CTRL - Register Layout Typedef */
typedef struct {
  __IO uint32_t CCR;                               /**< Cache control register, offset: 0x0 */
  __IO uint32_t CLCR;                              /**< Cache line control register, offset: 0x4 */
  __IO uint32_t CSAR;                              /**< Cache search address register, offset: 0x8 */
  __IO uint32_t CCVR;                              /**< Cache read/write value register, offset: 0xC */
} CACHE64_CTRL_Type;

/* ----------------------------------------------------------------------------
   -- CACHE64_CTRL Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_CTRL_Register_Masks CACHE64_CTRL Register Masks
 * @{
 */

/*! @name CCR - Cache control register */
/*! @{ */

#define CACHE64_CTRL_CCR_ENCACHE_MASK            (0x1U)
#define CACHE64_CTRL_CCR_ENCACHE_SHIFT           (0U)
/*! ENCACHE - Cache enable
 *  0b0..Cache disabled
 *  0b1..Cache enabled
 */
#define CACHE64_CTRL_CCR_ENCACHE(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENCACHE_SHIFT)) & CACHE64_CTRL_CCR_ENCACHE_MASK)

#define CACHE64_CTRL_CCR_INVW0_MASK              (0x1000000U)
#define CACHE64_CTRL_CCR_INVW0_SHIFT             (24U)
/*! INVW0 - Invalidate Way 0
 *  0b0..No operation
 *  0b1..When setting the GO bit, invalidate all lines in way 0.
 */
#define CACHE64_CTRL_CCR_INVW0(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW0_SHIFT)) & CACHE64_CTRL_CCR_INVW0_MASK)

#define CACHE64_CTRL_CCR_PUSHW0_MASK             (0x2000000U)
#define CACHE64_CTRL_CCR_PUSHW0_SHIFT            (25U)
/*! PUSHW0 - Push Way 0
 *  0b0..No operation
 *  0b1..When setting the GO bit, push all modified lines in way 0
 */
#define CACHE64_CTRL_CCR_PUSHW0(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW0_SHIFT)) & CACHE64_CTRL_CCR_PUSHW0_MASK)

#define CACHE64_CTRL_CCR_INVW1_MASK              (0x4000000U)
#define CACHE64_CTRL_CCR_INVW1_SHIFT             (26U)
/*! INVW1 - Invalidate Way 1
 *  0b0..No operation
 *  0b1..When setting the GO bit, invalidate all lines in way 1
 */
#define CACHE64_CTRL_CCR_INVW1(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK)

#define CACHE64_CTRL_CCR_PUSHW1_MASK             (0x8000000U)
#define CACHE64_CTRL_CCR_PUSHW1_SHIFT            (27U)
/*! PUSHW1 - Push Way 1
 *  0b0..No operation
 *  0b1..When setting the GO bit, push all modified lines in way 1
 */
#define CACHE64_CTRL_CCR_PUSHW1(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW1_SHIFT)) & CACHE64_CTRL_CCR_PUSHW1_MASK)

#define CACHE64_CTRL_CCR_GO_MASK                 (0x80000000U)
#define CACHE64_CTRL_CCR_GO_SHIFT                (31U)
/*! GO - Initiate Cache Command
 *  0b0..Write: no effect. Read: no cache command active.
 *  0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
 */
#define CACHE64_CTRL_CCR_GO(x)                   (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK)
/*! @} */

/*! @name CLCR - Cache line control register */
/*! @{ */

#define CACHE64_CTRL_CLCR_LGO_MASK               (0x1U)
#define CACHE64_CTRL_CLCR_LGO_SHIFT              (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect. Read: no line command active.
 *  0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
 */
#define CACHE64_CTRL_CLCR_LGO(x)                 (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)

#define CACHE64_CTRL_CLCR_CACHEADDR_MASK         (0x3FFCU)
#define CACHE64_CTRL_CLCR_CACHEADDR_SHIFT        (2U)
/*! CACHEADDR - Cache address */
#define CACHE64_CTRL_CLCR_CACHEADDR(x)           (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_CACHEADDR_SHIFT)) & CACHE64_CTRL_CLCR_CACHEADDR_MASK)

#define CACHE64_CTRL_CLCR_WSEL_MASK              (0x4000U)
#define CACHE64_CTRL_CLCR_WSEL_SHIFT             (14U)
/*! WSEL - Way select
 *  0b0..Way 0
 *  0b1..Way 1
 */
#define CACHE64_CTRL_CLCR_WSEL(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_WSEL_SHIFT)) & CACHE64_CTRL_CLCR_WSEL_MASK)

#define CACHE64_CTRL_CLCR_TDSEL_MASK             (0x10000U)
#define CACHE64_CTRL_CLCR_TDSEL_SHIFT            (16U)
/*! TDSEL - Tag/Data Select
 *  0b0..Data
 *  0b1..Tag
 */
#define CACHE64_CTRL_CLCR_TDSEL(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_TDSEL_SHIFT)) & CACHE64_CTRL_CLCR_TDSEL_MASK)

#define CACHE64_CTRL_CLCR_LCIVB_MASK             (0x100000U)
#define CACHE64_CTRL_CLCR_LCIVB_SHIFT            (20U)
/*! LCIVB - Line Command Initial Valid Bit */
#define CACHE64_CTRL_CLCR_LCIVB(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIVB_SHIFT)) & CACHE64_CTRL_CLCR_LCIVB_MASK)

#define CACHE64_CTRL_CLCR_LCIMB_MASK             (0x200000U)
#define CACHE64_CTRL_CLCR_LCIMB_SHIFT            (21U)
/*! LCIMB - Line Command Initial Modified Bit */
#define CACHE64_CTRL_CLCR_LCIMB(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIMB_SHIFT)) & CACHE64_CTRL_CLCR_LCIMB_MASK)

#define CACHE64_CTRL_CLCR_LCWAY_MASK             (0x400000U)
#define CACHE64_CTRL_CLCR_LCWAY_SHIFT            (22U)
/*! LCWAY - Line Command Way */
#define CACHE64_CTRL_CLCR_LCWAY(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCWAY_SHIFT)) & CACHE64_CTRL_CLCR_LCWAY_MASK)

#define CACHE64_CTRL_CLCR_LCMD_MASK              (0x3000000U)
#define CACHE64_CTRL_CLCR_LCMD_SHIFT             (24U)
/*! LCMD - Line Command
 *  0b00..Search and read or write
 *  0b01..Invalidate
 *  0b10..Push
 *  0b11..Clear
 */
#define CACHE64_CTRL_CLCR_LCMD(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCMD_SHIFT)) & CACHE64_CTRL_CLCR_LCMD_MASK)

#define CACHE64_CTRL_CLCR_LADSEL_MASK            (0x4000000U)
#define CACHE64_CTRL_CLCR_LADSEL_SHIFT           (26U)
/*! LADSEL - Line Address Select
 *  0b0..Cache address
 *  0b1..Physical address
 */
#define CACHE64_CTRL_CLCR_LADSEL(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)

#define CACHE64_CTRL_CLCR_LACC_MASK              (0x8000000U)
#define CACHE64_CTRL_CLCR_LACC_SHIFT             (27U)
/*! LACC - Line access type
 *  0b0..Read
 *  0b1..Write
 */
#define CACHE64_CTRL_CLCR_LACC(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/*! @} */

/*! @name CSAR - Cache search address register */
/*! @{ */

#define CACHE64_CTRL_CSAR_LGO_MASK               (0x1U)
#define CACHE64_CTRL_CSAR_LGO_SHIFT              (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect. Read: no line command active.
 *  0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
 */
#define CACHE64_CTRL_CSAR_LGO(x)                 (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_LGO_SHIFT)) & CACHE64_CTRL_CSAR_LGO_MASK)

#define CACHE64_CTRL_CSAR_PHYADDR_MASK           (0xFFFFFFFCU)
#define CACHE64_CTRL_CSAR_PHYADDR_SHIFT          (2U)
/*! PHYADDR - Physical Address */
#define CACHE64_CTRL_CSAR_PHYADDR(x)             (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_PHYADDR_SHIFT)) & CACHE64_CTRL_CSAR_PHYADDR_MASK)
/*! @} */

/*! @name CCVR - Cache read/write value register */
/*! @{ */

#define CACHE64_CTRL_CCVR_DATA_MASK              (0xFFFFFFFFU)
#define CACHE64_CTRL_CCVR_DATA_SHIFT             (0U)
/*! DATA - Cache read/write Data */
#define CACHE64_CTRL_CCVR_DATA(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCVR_DATA_SHIFT)) & CACHE64_CTRL_CCVR_DATA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CACHE64_CTRL_Register_Masks */


/* CACHE64_CTRL - Peripheral instance base addresses */
/** Peripheral CACHE64_CTRL0 base address */
#define CACHE64_CTRL0_BASE                       (0x28046000u)
/** Peripheral CACHE64_CTRL0 base pointer */
#define CACHE64_CTRL0                            ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
/** Peripheral CACHE64_CTRL1 base address */
#define CACHE64_CTRL1_BASE                       (0x28046800u)
/** Peripheral CACHE64_CTRL1 base pointer */
#define CACHE64_CTRL1                            ((CACHE64_CTRL_Type *)CACHE64_CTRL1_BASE)
/** Array initializer of CACHE64_CTRL peripheral base addresses */
#define CACHE64_CTRL_BASE_ADDRS                  { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
/** Array initializer of CACHE64_CTRL peripheral base pointers */
#define CACHE64_CTRL_BASE_PTRS                   { CACHE64_CTRL0, CACHE64_CTRL1 }

/*!
 * @}
 */ /* end of group CACHE64_CTRL_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CAN Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
 * @{
 */

/** CAN - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
  __IO uint32_t CTRL1;                             /**< Control 1 Register, offset: 0x4 */
  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask Register, offset: 0x14 */
  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask Register, offset: 0x18 */
  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
  __IO uint32_t ESR1;                              /**< Error and Status 1 Register, offset: 0x20 */
  __IO uint32_t IMASK2;                            /**< Interrupt Masks 2 Register, offset: 0x24 */
  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 Register, offset: 0x28 */
  __IO uint32_t IFLAG2;                            /**< Interrupt Flags 2 Register, offset: 0x2C */
  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 Register, offset: 0x30 */
  __IO uint32_t CTRL2;                             /**< Control 2 Register, offset: 0x34 */
  __I  uint32_t ESR2;                              /**< Error and Status 2 Register, offset: 0x38 */
       uint8_t RESERVED_1[8];
  __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
  __IO uint32_t RXFGMASK;                          /**< Legacy Rx FIFO Global Mask Register, offset: 0x48 */
  __I  uint32_t RXFIR;                             /**< Legacy Rx FIFO Information Register, offset: 0x4C */
  __IO uint32_t CBT;                               /**< CAN Bit Timing Register, offset: 0x50 */
       uint8_t RESERVED_2[44];
  union {                                          /* offset: 0x80 */
    struct {                                         /* offset: 0x80, array step: 0x10 */
      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
      __IO uint32_t WORD[2];                           /**< Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */
    } MB_8B[64];
    struct {                                         /* offset: 0x80, array step: 0x18 */
      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 41 CS Register, array offset: 0x80, array step: 0x18 */
      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 41 ID Register, array offset: 0x84, array step: 0x18 */
      __IO uint32_t WORD[4];                           /**< Message Buffer 0 WORD_16B Register..Message Buffer 41 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */
    } MB_16B[42];
    struct {                                         /* offset: 0x80, array step: 0x28 */
      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 23 CS Register, array offset: 0x80, array step: 0x28 */
      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 23 ID Register, array offset: 0x84, array step: 0x28 */
      __IO uint32_t WORD[8];                           /**< Message Buffer 0 WORD_32B Register..Message Buffer 23 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */
    } MB_32B[24];
    struct {                                         /* offset: 0x80, array step: 0x48 */
      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 13 CS Register, array offset: 0x80, array step: 0x48 */
      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 13 ID Register, array offset: 0x84, array step: 0x48 */
      __IO uint32_t WORD[16];                          /**< Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */
    } MB_64B[14];
    struct {                                         /* offset: 0x80, array step: 0x10 */
      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
      __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
      __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
    } MB[64];
  };
       uint8_t RESERVED_3[1024];
  __IO uint32_t RXIMR[64];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
       uint8_t RESERVED_4[384];
  __IO uint32_t CTRL1_PN;                          /**< Pretended Networking Control 1 Register, offset: 0xB00 */
  __IO uint32_t CTRL2_PN;                          /**< Pretended Networking Control 2 Register, offset: 0xB04 */
  __IO uint32_t WU_MTC;                            /**< Pretended Networking Wake Up Match Register, offset: 0xB08 */
  __IO uint32_t FLT_ID1;                           /**< Pretended Networking ID Filter 1 Register, offset: 0xB0C */
  __IO uint32_t FLT_DLC;                           /**< Pretended Networking DLC Filter Register, offset: 0xB10 */
  __IO uint32_t PL1_LO;                            /**< Pretended Networking Payload Low Filter 1 Register, offset: 0xB14 */
  __IO uint32_t PL1_HI;                            /**< Pretended Networking Payload High Filter 1 Register, offset: 0xB18 */
  __IO uint32_t FLT_ID2_IDMASK;                    /**< Pretended Networking ID Filter 2 Register / ID Mask Register, offset: 0xB1C */
  __IO uint32_t PL2_PLMASK_LO;                     /**< Pretended Networking Payload Low Filter 2 Register / Payload Low Mask register, offset: 0xB20 */
  __IO uint32_t PL2_PLMASK_HI;                     /**< Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register, offset: 0xB24 */
       uint8_t RESERVED_5[24];
  struct {                                         /* offset: 0xB40, array step: 0x10 */
    __I  uint32_t CS;                                /**< Wake Up Message Buffer register for C/S, array offset: 0xB40, array step: 0x10 */
    __I  uint32_t ID;                                /**< Wake Up Message Buffer Register for ID, array offset: 0xB44, array step: 0x10 */
    __I  uint32_t D03;                               /**< Wake Up Message Buffer Register for Data 0-3, array offset: 0xB48, array step: 0x10 */
    __I  uint32_t D47;                               /**< Wake Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */
  } WMB[4];
       uint8_t RESERVED_6[112];
  __IO uint32_t EPRS;                              /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */
  __IO uint32_t ENCBT;                             /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */
  __IO uint32_t EDCBT;                             /**< Enhanced Data Phase CAN bit Timing, offset: 0xBF8 */
  __IO uint32_t ETDC;                              /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */
  __IO uint32_t FDCTRL;                            /**< CAN FD Control Register, offset: 0xC00 */
  __IO uint32_t FDCBT;                             /**< CAN FD Bit Timing Register, offset: 0xC04 */
  __I  uint32_t FDCRC;                             /**< CAN FD CRC Register, offset: 0xC08 */
  __IO uint32_t ERFCR;                             /**< Enhanced Rx FIFO Control Register, offset: 0xC0C */
  __IO uint32_t ERFIER;                            /**< Enhanced Rx FIFO Interrupt Enable Register, offset: 0xC10 */
  __IO uint32_t ERFSR;                             /**< Enhanced Rx FIFO Status Register, offset: 0xC14 */
       uint8_t RESERVED_7[24];
  __IO uint32_t HR_TIME_STAMP[64];                 /**< High Resolution Time Stamp, array offset: 0xC30, array step: 0x4 */
       uint8_t RESERVED_8[8912];
  __IO uint32_t ERFFEL[32];                        /**< Enhanced Rx FIFO Filter Element, array offset: 0x3000, array step: 0x4 */
} CAN_Type;

/* ----------------------------------------------------------------------------
   -- CAN Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CAN_Register_Masks CAN Register Masks
 * @{
 */

/*! @name MCR - Module Configuration Register */
/*! @{ */

#define CAN_MCR_MAXMB_MASK                       (0x7FU)
#define CAN_MCR_MAXMB_SHIFT                      (0U)
/*! MAXMB - Number Of The Last Message Buffer */
#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)

#define CAN_MCR_IDAM_MASK                        (0x300U)
#define CAN_MCR_IDAM_SHIFT                       (8U)
/*! IDAM - ID Acceptance Mode
 *  0b00..Format A: One full ID (standard and extended) per ID filter table element.
 *  0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
 *  0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
 *  0b11..Format D: All frames rejected.
 */
#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

#define CAN_MCR_FDEN_MASK                        (0x800U)
#define CAN_MCR_FDEN_SHIFT                       (11U)
/*! FDEN - CAN FD operation enable
 *  0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
 *  0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
 */
#define CAN_MCR_FDEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)

#define CAN_MCR_AEN_MASK                         (0x1000U)
#define CAN_MCR_AEN_SHIFT                        (12U)
/*! AEN - Abort Enable
 *  0b0..Abort disabled.
 *  0b1..Abort enabled.
 */
#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

#define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
#define CAN_MCR_LPRIOEN_SHIFT                    (13U)
/*! LPRIOEN - Local Priority Enable
 *  0b0..Local Priority disabled.
 *  0b1..Local Priority enabled.
 */
#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

#define CAN_MCR_PNET_EN_MASK                     (0x4000U)
#define CAN_MCR_PNET_EN_SHIFT                    (14U)
/*! PNET_EN - Pretended Networking Enable
 *  0b0..Pretended Networking mode is disabled.
 *  0b1..Pretended Networking mode is enabled.
 */
#define CAN_MCR_PNET_EN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK)

#define CAN_MCR_DMA_MASK                         (0x8000U)
#define CAN_MCR_DMA_SHIFT                        (15U)
/*! DMA - DMA Enable
 *  0b0..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO disabled.
 *  0b1..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO enabled.
 */
#define CAN_MCR_DMA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)

#define CAN_MCR_IRMQ_MASK                        (0x10000U)
#define CAN_MCR_IRMQ_SHIFT                       (16U)
/*! IRMQ - Individual Rx Masking And Queue Enable
 *  0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
 *       applications, the reading of C/S word locks the MB even if it is EMPTY.
 *  0b1..Individual Rx masking and queue feature are enabled.
 */
#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

#define CAN_MCR_SRXDIS_MASK                      (0x20000U)
#define CAN_MCR_SRXDIS_SHIFT                     (17U)
/*! SRXDIS - Self Reception Disable
 *  0b0..Self-reception enabled.
 *  0b1..Self-reception disabled.
 */
#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

#define CAN_MCR_DOZE_MASK                        (0x40000U)
#define CAN_MCR_DOZE_SHIFT                       (18U)
/*! DOZE - Doze Mode Enable
 *  0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
 *  0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
 */
#define CAN_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)

#define CAN_MCR_WAKSRC_MASK                      (0x80000U)
#define CAN_MCR_WAKSRC_SHIFT                     (19U)
/*! WAKSRC - Wake Up Source
 *  0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
 *  0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
 */
#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

#define CAN_MCR_LPMACK_MASK                      (0x100000U)
#define CAN_MCR_LPMACK_SHIFT                     (20U)
/*! LPMACK - Low-Power Mode Acknowledge
 *  0b0..FlexCAN is not in a low-power mode.
 *  0b1..FlexCAN is in a low-power mode.
 */
#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

#define CAN_MCR_WRNEN_MASK                       (0x200000U)
#define CAN_MCR_WRNEN_SHIFT                      (21U)
/*! WRNEN - Warning Interrupt Enable
 *  0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
 *  0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
 */
#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

#define CAN_MCR_SLFWAK_MASK                      (0x400000U)
#define CAN_MCR_SLFWAK_SHIFT                     (22U)
/*! SLFWAK - Self Wake Up
 *  0b0..FlexCAN Self Wake Up feature is disabled.
 *  0b1..FlexCAN Self Wake Up feature is enabled.
 */
#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

#define CAN_MCR_SUPV_MASK                        (0x800000U)
#define CAN_MCR_SUPV_SHIFT                       (23U)
/*! SUPV - Supervisor Mode
 *  0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses.
 *  0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access
 *       behaves as though the access was done to an unimplemented register location.
 */
#define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)

#define CAN_MCR_FRZACK_MASK                      (0x1000000U)
#define CAN_MCR_FRZACK_SHIFT                     (24U)
/*! FRZACK - Freeze Mode Acknowledge
 *  0b0..FlexCAN not in Freeze mode, prescaler running.
 *  0b1..FlexCAN in Freeze mode, prescaler stopped.
 */
#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

#define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
#define CAN_MCR_SOFTRST_SHIFT                    (25U)
/*! SOFTRST - Soft Reset
 *  0b0..No reset request.
 *  0b1..Resets the registers affected by soft reset.
 */
#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

#define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
#define CAN_MCR_WAKMSK_SHIFT                     (26U)
/*! WAKMSK - Wake Up Interrupt Mask
 *  0b0..Wake Up interrupt is disabled.
 *  0b1..Wake Up interrupt is enabled.
 */
#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

#define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
#define CAN_MCR_NOTRDY_SHIFT                     (27U)
/*! NOTRDY - FlexCAN Not Ready
 *  0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
 *  0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
 */
#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

#define CAN_MCR_HALT_MASK                        (0x10000000U)
#define CAN_MCR_HALT_SHIFT                       (28U)
/*! HALT - Halt FlexCAN
 *  0b0..No Freeze mode request.
 *  0b1..Enters Freeze mode if the FRZ bit is asserted.
 */
#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

#define CAN_MCR_RFEN_MASK                        (0x20000000U)
#define CAN_MCR_RFEN_SHIFT                       (29U)
/*! RFEN - Legacy Rx FIFO Enable
 *  0b0..Legacy Rx FIFO not enabled.
 *  0b1..Legacy Rx FIFO enabled.
 */
#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

#define CAN_MCR_FRZ_MASK                         (0x40000000U)
#define CAN_MCR_FRZ_SHIFT                        (30U)
/*! FRZ - Freeze Enable
 *  0b0..Not enabled to enter Freeze mode.
 *  0b1..Enabled to enter Freeze mode.
 */
#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

#define CAN_MCR_MDIS_MASK                        (0x80000000U)
#define CAN_MCR_MDIS_SHIFT                       (31U)
/*! MDIS - Module Disable
 *  0b0..Enable the FlexCAN module.
 *  0b1..Disable the FlexCAN module.
 */
#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
/*! @} */

/*! @name CTRL1 - Control 1 Register */
/*! @{ */

#define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
#define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
/*! PROPSEG - Propagation Segment */
#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)

#define CAN_CTRL1_LOM_MASK                       (0x8U)
#define CAN_CTRL1_LOM_SHIFT                      (3U)
/*! LOM - Listen-Only Mode
 *  0b0..Listen-Only mode is deactivated.
 *  0b1..FlexCAN module operates in Listen-Only mode.
 */
#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

#define CAN_CTRL1_LBUF_MASK                      (0x10U)
#define CAN_CTRL1_LBUF_SHIFT                     (4U)
/*! LBUF - Lowest Buffer Transmitted First
 *  0b0..Buffer with highest priority is transmitted first.
 *  0b1..Lowest number buffer is transmitted first.
 */
#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

#define CAN_CTRL1_TSYN_MASK                      (0x20U)
#define CAN_CTRL1_TSYN_SHIFT                     (5U)
/*! TSYN - Timer Sync
 *  0b0..Timer sync feature disabled
 *  0b1..Timer sync feature enabled
 */
#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

#define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
#define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
/*! BOFFREC - Bus Off Recovery
 *  0b0..Automatic recovering from Bus Off state enabled.
 *  0b1..Automatic recovering from Bus Off state disabled.
 */
#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

#define CAN_CTRL1_SMP_MASK                       (0x80U)
#define CAN_CTRL1_SMP_SHIFT                      (7U)
/*! SMP - CAN Bit Sampling
 *  0b0..Just one sample is used to determine the bit value.
 *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
 *       preceding samples; a majority rule is used.
 */
#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

#define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
#define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
/*! RWRNMSK - Rx Warning Interrupt Mask
 *  0b0..Rx Warning interrupt disabled.
 *  0b1..Rx Warning interrupt enabled.
 */
#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

#define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
#define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
/*! TWRNMSK - Tx Warning Interrupt Mask
 *  0b0..Tx Warning interrupt disabled.
 *  0b1..Tx Warning interrupt enabled.
 */
#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

#define CAN_CTRL1_LPB_MASK                       (0x1000U)
#define CAN_CTRL1_LPB_SHIFT                      (12U)
/*! LPB - Loop Back Mode
 *  0b0..Loop Back disabled.
 *  0b1..Loop Back enabled.
 */
#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

#define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
#define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
/*! ERRMSK - Error Interrupt Mask
 *  0b0..Error interrupt disabled.
 *  0b1..Error interrupt enabled.
 */
#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

#define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
#define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
/*! BOFFMSK - Bus Off Interrupt Mask
 *  0b0..Bus Off interrupt disabled.
 *  0b1..Bus Off interrupt enabled.
 */
#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

#define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
#define CAN_CTRL1_PSEG2_SHIFT                    (16U)
/*! PSEG2 - Phase Segment 2 */
#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)

#define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
#define CAN_CTRL1_PSEG1_SHIFT                    (19U)
/*! PSEG1 - Phase Segment 1 */
#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)

#define CAN_CTRL1_RJW_MASK                       (0xC00000U)
#define CAN_CTRL1_RJW_SHIFT                      (22U)
/*! RJW - Resync Jump Width */
#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)

#define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
#define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
/*! PRESDIV - Prescaler Division Factor */
#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
/*! @} */

/*! @name TIMER - Free Running Timer */
/*! @{ */

#define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
#define CAN_TIMER_TIMER_SHIFT                    (0U)
/*! TIMER - Timer Value */
#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
/*! @} */

/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
/*! @{ */

#define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
#define CAN_RXMGMASK_MG_SHIFT                    (0U)
/*! MG - Rx Mailboxes Global Mask Bits */
#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
/*! @} */

/*! @name RX14MASK - Rx 14 Mask Register */
/*! @{ */

#define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
#define CAN_RX14MASK_RX14M_SHIFT                 (0U)
/*! RX14M - Rx Buffer 14 Mask Bits */
#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
/*! @} */

/*! @name RX15MASK - Rx 15 Mask Register */
/*! @{ */

#define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
#define CAN_RX15MASK_RX15M_SHIFT                 (0U)
/*! RX15M - Rx Buffer 15 Mask Bits */
#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
/*! @} */

/*! @name ECR - Error Counter */
/*! @{ */

#define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
#define CAN_ECR_TXERRCNT_SHIFT                   (0U)
/*! TXERRCNT - Transmit Error Counter */
#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)

#define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
#define CAN_ECR_RXERRCNT_SHIFT                   (8U)
/*! RXERRCNT - Receive Error Counter */
#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)

#define CAN_ECR_TXERRCNT_FAST_MASK               (0xFF0000U)
#define CAN_ECR_TXERRCNT_FAST_SHIFT              (16U)
/*! TXERRCNT_FAST - Transmit Error Counter for fast bits */
#define CAN_ECR_TXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)

#define CAN_ECR_RXERRCNT_FAST_MASK               (0xFF000000U)
#define CAN_ECR_RXERRCNT_FAST_SHIFT              (24U)
/*! RXERRCNT_FAST - Receive Error Counter for fast bits */
#define CAN_ECR_RXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
/*! @} */

/*! @name ESR1 - Error and Status 1 Register */
/*! @{ */

#define CAN_ESR1_WAKINT_MASK                     (0x1U)
#define CAN_ESR1_WAKINT_SHIFT                    (0U)
/*! WAKINT - Wake-Up Interrupt
 *  0b0..No such occurrence.
 *  0b1..Indicates a recessive to dominant transition was received on the CAN bus.
 */
#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

#define CAN_ESR1_ERRINT_MASK                     (0x2U)
#define CAN_ESR1_ERRINT_SHIFT                    (1U)
/*! ERRINT - Error Interrupt
 *  0b0..No such occurrence.
 *  0b1..Indicates setting of any error bit in the Error and Status register.
 */
#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

#define CAN_ESR1_BOFFINT_MASK                    (0x4U)
#define CAN_ESR1_BOFFINT_SHIFT                   (2U)
/*! BOFFINT - Bus Off Interrupt
 *  0b0..No such occurrence.
 *  0b1..FlexCAN module entered Bus Off state.
 */
#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

#define CAN_ESR1_RX_MASK                         (0x8U)
#define CAN_ESR1_RX_SHIFT                        (3U)
/*! RX - FlexCAN In Reception
 *  0b0..FlexCAN is not receiving a message.
 *  0b1..FlexCAN is receiving a message.
 */
#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

#define CAN_ESR1_FLTCONF_MASK                    (0x30U)
#define CAN_ESR1_FLTCONF_SHIFT                   (4U)
/*! FLTCONF - Fault Confinement State
 *  0b00..Error Active
 *  0b01..Error Passive
 *  0b1x..Bus Off
 */
#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

#define CAN_ESR1_TX_MASK                         (0x40U)
#define CAN_ESR1_TX_SHIFT                        (6U)
/*! TX - FlexCAN In Transmission
 *  0b0..FlexCAN is not transmitting a message.
 *  0b1..FlexCAN is transmitting a message.
 */
#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

#define CAN_ESR1_IDLE_MASK                       (0x80U)
#define CAN_ESR1_IDLE_SHIFT                      (7U)
/*! IDLE - IDLE
 *  0b0..No such occurrence.
 *  0b1..CAN bus is now IDLE.
 */
#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

#define CAN_ESR1_RXWRN_MASK                      (0x100U)
#define CAN_ESR1_RXWRN_SHIFT                     (8U)
/*! RXWRN - Rx Error Warning
 *  0b0..No such occurrence.
 *  0b1..RXERRCNT is greater than or equal to 96.
 */
#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

#define CAN_ESR1_TXWRN_MASK                      (0x200U)
#define CAN_ESR1_TXWRN_SHIFT                     (9U)
/*! TXWRN - TX Error Warning
 *  0b0..No such occurrence.
 *  0b1..TXERRCNT is greater than or equal to 96.
 */
#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

#define CAN_ESR1_STFERR_MASK                     (0x400U)
#define CAN_ESR1_STFERR_SHIFT                    (10U)
/*! STFERR - Stuffing Error
 *  0b0..No such occurrence.
 *  0b1..A stuffing error occurred since last read of this register.
 */
#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

#define CAN_ESR1_FRMERR_MASK                     (0x800U)
#define CAN_ESR1_FRMERR_SHIFT                    (11U)
/*! FRMERR - Form Error
 *  0b0..No such occurrence.
 *  0b1..A Form Error occurred since last read of this register.
 */
#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

#define CAN_ESR1_CRCERR_MASK                     (0x1000U)
#define CAN_ESR1_CRCERR_SHIFT                    (12U)
/*! CRCERR - Cyclic Redundancy Check Error
 *  0b0..No such occurrence.
 *  0b1..A CRC error occurred since last read of this register.
 */
#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

#define CAN_ESR1_ACKERR_MASK                     (0x2000U)
#define CAN_ESR1_ACKERR_SHIFT                    (13U)
/*! ACKERR - Acknowledge Error
 *  0b0..No such occurrence.
 *  0b1..An ACK error occurred since last read of this register.
 */
#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

#define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
#define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
/*! BIT0ERR - Bit0 Error
 *  0b0..No such occurrence.
 *  0b1..At least one bit sent as dominant is received as recessive.
 */
#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

#define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
#define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
/*! BIT1ERR - Bit1 Error
 *  0b0..No such occurrence.
 *  0b1..At least one bit sent as recessive is received as dominant.
 */
#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

#define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
#define CAN_ESR1_RWRNINT_SHIFT                   (16U)
/*! RWRNINT - Rx Warning Interrupt Flag
 *  0b0..No such occurrence.
 *  0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
 */
#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

#define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
#define CAN_ESR1_TWRNINT_SHIFT                   (17U)
/*! TWRNINT - Tx Warning Interrupt Flag
 *  0b0..No such occurrence.
 *  0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
 */
#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

#define CAN_ESR1_SYNCH_MASK                      (0x40000U)
#define CAN_ESR1_SYNCH_SHIFT                     (18U)
/*! SYNCH - CAN Synchronization Status
 *  0b0..FlexCAN is not synchronized to the CAN bus.
 *  0b1..FlexCAN is synchronized to the CAN bus.
 */
#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

#define CAN_ESR1_BOFFDONEINT_MASK                (0x80000U)
#define CAN_ESR1_BOFFDONEINT_SHIFT               (19U)
/*! BOFFDONEINT - Bus Off Done Interrupt
 *  0b0..No such occurrence.
 *  0b1..FlexCAN module has completed Bus Off process.
 */
#define CAN_ESR1_BOFFDONEINT(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)

#define CAN_ESR1_ERRINT_FAST_MASK                (0x100000U)
#define CAN_ESR1_ERRINT_FAST_SHIFT               (20U)
/*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
 *  0b0..No such occurrence.
 *  0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
 */
#define CAN_ESR1_ERRINT_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)

#define CAN_ESR1_ERROVR_MASK                     (0x200000U)
#define CAN_ESR1_ERROVR_SHIFT                    (21U)
/*! ERROVR - Error Overrun
 *  0b0..Overrun has not occurred.
 *  0b1..Overrun has occurred.
 */
#define CAN_ESR1_ERROVR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)

#define CAN_ESR1_STFERR_FAST_MASK                (0x4000000U)
#define CAN_ESR1_STFERR_FAST_SHIFT               (26U)
/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..A stuffing error occurred since last read of this register.
 */
#define CAN_ESR1_STFERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)

#define CAN_ESR1_FRMERR_FAST_MASK                (0x8000000U)
#define CAN_ESR1_FRMERR_FAST_SHIFT               (27U)
/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..A form error occurred since last read of this register.
 */
#define CAN_ESR1_FRMERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)

#define CAN_ESR1_CRCERR_FAST_MASK                (0x10000000U)
#define CAN_ESR1_CRCERR_FAST_SHIFT               (28U)
/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..A CRC error occurred since last read of this register.
 */
#define CAN_ESR1_CRCERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)

#define CAN_ESR1_BIT0ERR_FAST_MASK               (0x40000000U)
#define CAN_ESR1_BIT0ERR_FAST_SHIFT              (30U)
/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..At least one bit sent as dominant is received as recessive.
 */
#define CAN_ESR1_BIT0ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)

#define CAN_ESR1_BIT1ERR_FAST_MASK               (0x80000000U)
#define CAN_ESR1_BIT1ERR_FAST_SHIFT              (31U)
/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..At least one bit sent as recessive is received as dominant.
 */
#define CAN_ESR1_BIT1ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
/*! @} */

/*! @name IMASK2 - Interrupt Masks 2 Register */
/*! @{ */

#define CAN_IMASK2_BUF63TO32M_MASK               (0xFFFFFFFFU)
#define CAN_IMASK2_BUF63TO32M_SHIFT              (0U)
/*! BUF63TO32M - Buffer MBi Mask */
#define CAN_IMASK2_BUF63TO32M(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
/*! @} */

/*! @name IMASK1 - Interrupt Masks 1 Register */
/*! @{ */

#define CAN_IMASK1_BUF31TO0M_MASK                (0xFFFFFFFFU)
#define CAN_IMASK1_BUF31TO0M_SHIFT               (0U)
/*! BUF31TO0M - Buffer MBi Mask */
#define CAN_IMASK1_BUF31TO0M(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
/*! @} */

/*! @name IFLAG2 - Interrupt Flags 2 Register */
/*! @{ */

#define CAN_IFLAG2_BUF63TO32I_MASK               (0xFFFFFFFFU)
#define CAN_IFLAG2_BUF63TO32I_SHIFT              (0U)
/*! BUF63TO32I - Buffer MBi Interrupt */
#define CAN_IFLAG2_BUF63TO32I(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
/*! @} */

/*! @name IFLAG1 - Interrupt Flags 1 Register */
/*! @{ */

#define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
#define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
/*! BUF0I - Buffer MB0 Interrupt Or Clear Legacy FIFO bit
 *  0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
 *  0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
 */
#define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)

#define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
#define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
/*! BUF4TO1I - Buffer MBi Interrupt Or Reserved */
#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)

#define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
#define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
/*! BUF5I - Buffer MB5 Interrupt Or Frames available in Legacy Rx FIFO
 *  0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the Legacy FIFO, when MCR[RFEN]=1
 *  0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Legacy Rx FIFO when
 *       MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
 */
#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

#define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
#define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
/*! BUF6I - Buffer MB6 Interrupt Or Legacy Rx FIFO Warning
 *  0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Legacy Rx FIFO almost full when MCR[RFEN]=1
 *  0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Legacy Rx FIFO almost full when MCR[RFEN]=1
 */
#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

#define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
#define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
/*! BUF7I - Buffer MB7 Interrupt Or Legacy Rx FIFO Overflow
 *  0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Legacy Rx FIFO overflow when MCR[RFEN]=1
 *  0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Legacy Rx FIFO overflow when MCR[RFEN]=1
 */
#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

#define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
#define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
/*! BUF31TO8I - Buffer MBi Interrupt */
#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
/*! @} */

/*! @name CTRL2 - Control 2 Register */
/*! @{ */

#define CAN_CTRL2_TSTAMPCAP_MASK                 (0xC0U)
#define CAN_CTRL2_TSTAMPCAP_SHIFT                (6U)
/*! TSTAMPCAP - Time Stamp Capture Point
 *  0b00..The high resolution time stamp capture is disabled
 *  0b01..The high resolution time stamp is captured in the end of the CAN frame
 *  0b10..The high resolution time stamp is captured in the start of the CAN frame
 *  0b11..The high resolution time stamp is captured in the start of frame for classical CAN frames and in res bit for CAN FD frames
 */
#define CAN_CTRL2_TSTAMPCAP(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TSTAMPCAP_SHIFT)) & CAN_CTRL2_TSTAMPCAP_MASK)

#define CAN_CTRL2_MBTSBASE_MASK                  (0x300U)
#define CAN_CTRL2_MBTSBASE_SHIFT                 (8U)
/*! MBTSBASE - Message Buffer Time Stamp Base
 *  0b00..Message buffer time stamp base is TIMER
 *  0b01..Message buffer time stamp base is lower 16 bits of high resolution timer
 *  0b10..Message buffer time stamp base is upper 16 bits of high resolution timer
 *  0b11..Reserved
 */
#define CAN_CTRL2_MBTSBASE(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MBTSBASE_SHIFT)) & CAN_CTRL2_MBTSBASE_MASK)

#define CAN_CTRL2_EDFLTDIS_MASK                  (0x800U)
#define CAN_CTRL2_EDFLTDIS_SHIFT                 (11U)
/*! EDFLTDIS - Edge Filter Disable
 *  0b0..Edge filter is enabled
 *  0b1..Edge filter is disabled
 */
#define CAN_CTRL2_EDFLTDIS(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)

#define CAN_CTRL2_ISOCANFDEN_MASK                (0x1000U)
#define CAN_CTRL2_ISOCANFDEN_SHIFT               (12U)
/*! ISOCANFDEN - ISO CAN FD Enable
 *  0b0..FlexCAN operates using the non-ISO CAN FD protocol.
 *  0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1:2015).
 */
#define CAN_CTRL2_ISOCANFDEN(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)

#define CAN_CTRL2_BTE_MASK                       (0x2000U)
#define CAN_CTRL2_BTE_SHIFT                      (13U)
/*! BTE - Bit Timing Expansion enable
 *  0b0..CAN Bit timing expansion is disabled.
 *  0b1..CAN bit timing expansion is enabled.
 */
#define CAN_CTRL2_BTE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK)

#define CAN_CTRL2_PREXCEN_MASK                   (0x4000U)
#define CAN_CTRL2_PREXCEN_SHIFT                  (14U)
/*! PREXCEN - Protocol Exception Enable
 *  0b0..Protocol exception is disabled.
 *  0b1..Protocol exception is enabled.
 */
#define CAN_CTRL2_PREXCEN(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)

#define CAN_CTRL2_TIMER_SRC_MASK                 (0x8000U)
#define CAN_CTRL2_TIMER_SRC_SHIFT                (15U)
/*! TIMER_SRC - Timer Source
 *  0b0..The free running timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus.
 *  0b1..The free running timer is clocked by an external time tick. The period can be either adjusted to be equal
 *       to the baud rate on the CAN bus, or a different value as required. See the device-specific section for
 *       details about the external time tick.
 */
#define CAN_CTRL2_TIMER_SRC(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)

#define CAN_CTRL2_EACEN_MASK                     (0x10000U)
#define CAN_CTRL2_EACEN_SHIFT                    (16U)
/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
 *  0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
 *  0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
 *       the incoming frame. Mask bits do apply.
 */
#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

#define CAN_CTRL2_RRS_MASK                       (0x20000U)
#define CAN_CTRL2_RRS_SHIFT                      (17U)
/*! RRS - Remote Request Storing
 *  0b0..Remote response frame is generated.
 *  0b1..Remote request frame is stored.
 */
#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

#define CAN_CTRL2_MRP_MASK                       (0x40000U)
#define CAN_CTRL2_MRP_SHIFT                      (18U)
/*! MRP - Mailboxes Reception Priority
 *  0b0..Matching starts from Legacy Rx FIFO or Enhanced Rx FIFO and continues on mailboxes.
 *  0b1..Matching starts from mailboxes and continues on Legacy Rx FIFO or Enhanced Rx FIFO.
 */
#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

#define CAN_CTRL2_TASD_MASK                      (0xF80000U)
#define CAN_CTRL2_TASD_SHIFT                     (19U)
/*! TASD - Tx Arbitration Start Delay */
#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)

#define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
#define CAN_CTRL2_RFFN_SHIFT                     (24U)
/*! RFFN - Number Of Legacy Rx FIFO Filters */
#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)

#define CAN_CTRL2_BOFFDONEMSK_MASK               (0x40000000U)
#define CAN_CTRL2_BOFFDONEMSK_SHIFT              (30U)
/*! BOFFDONEMSK - Bus Off Done Interrupt Mask
 *  0b0..Bus off done interrupt disabled.
 *  0b1..Bus off done interrupt enabled.
 */
#define CAN_CTRL2_BOFFDONEMSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)

#define CAN_CTRL2_ERRMSK_FAST_MASK               (0x80000000U)
#define CAN_CTRL2_ERRMSK_FAST_SHIFT              (31U)
/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
 *  0b0..ERRINT_FAST error interrupt disabled.
 *  0b1..ERRINT_FAST error interrupt enabled.
 */
#define CAN_CTRL2_ERRMSK_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
/*! @} */

/*! @name ESR2 - Error and Status 2 Register */
/*! @{ */

#define CAN_ESR2_IMB_MASK                        (0x2000U)
#define CAN_ESR2_IMB_SHIFT                       (13U)
/*! IMB - Inactive Mailbox
 *  0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
 *  0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
 */
#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

#define CAN_ESR2_VPS_MASK                        (0x4000U)
#define CAN_ESR2_VPS_SHIFT                       (14U)
/*! VPS - Valid Priority Status
 *  0b0..Contents of IMB and LPTM are invalid.
 *  0b1..Contents of IMB and LPTM are valid.
 */
#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

#define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
#define CAN_ESR2_LPTM_SHIFT                      (16U)
/*! LPTM - Lowest Priority Tx Mailbox */
#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
/*! @} */

/*! @name CRCR - CRC Register */
/*! @{ */

#define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
#define CAN_CRCR_TXCRC_SHIFT                     (0U)
/*! TXCRC - Transmitted CRC value */
#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)

#define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
#define CAN_CRCR_MBCRC_SHIFT                     (16U)
/*! MBCRC - CRC Mailbox */
#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
/*! @} */

/*! @name RXFGMASK - Legacy Rx FIFO Global Mask Register */
/*! @{ */

#define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
#define CAN_RXFGMASK_FGM_SHIFT                   (0U)
/*! FGM - Legacy Rx FIFO Global Mask Bits */
#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
/*! @} */

/*! @name RXFIR - Legacy Rx FIFO Information Register */
/*! @{ */

#define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
#define CAN_RXFIR_IDHIT_SHIFT                    (0U)
/*! IDHIT - Identifier Acceptance Filter Hit Indicator */
#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
/*! @} */

/*! @name CBT - CAN Bit Timing Register */
/*! @{ */

#define CAN_CBT_EPSEG2_MASK                      (0x1FU)
#define CAN_CBT_EPSEG2_SHIFT                     (0U)
/*! EPSEG2 - Extended Phase Segment 2 */
#define CAN_CBT_EPSEG2(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)

#define CAN_CBT_EPSEG1_MASK                      (0x3E0U)
#define CAN_CBT_EPSEG1_SHIFT                     (5U)
/*! EPSEG1 - Extended Phase Segment 1 */
#define CAN_CBT_EPSEG1(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)

#define CAN_CBT_EPROPSEG_MASK                    (0xFC00U)
#define CAN_CBT_EPROPSEG_SHIFT                   (10U)
/*! EPROPSEG - Extended Propagation Segment */
#define CAN_CBT_EPROPSEG(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)

#define CAN_CBT_ERJW_MASK                        (0x1F0000U)
#define CAN_CBT_ERJW_SHIFT                       (16U)
/*! ERJW - Extended Resync Jump Width */
#define CAN_CBT_ERJW(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)

#define CAN_CBT_EPRESDIV_MASK                    (0x7FE00000U)
#define CAN_CBT_EPRESDIV_SHIFT                   (21U)
/*! EPRESDIV - Extended Prescaler Division Factor */
#define CAN_CBT_EPRESDIV(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)

#define CAN_CBT_BTF_MASK                         (0x80000000U)
#define CAN_CBT_BTF_SHIFT                        (31U)
/*! BTF - Bit Timing Format Enable
 *  0b0..Extended bit time definitions disabled.
 *  0b1..Extended bit time definitions enabled.
 */
#define CAN_CBT_BTF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
/*! @} */

/* The count of CAN_CS */
#define CAN_CS_COUNT_MB8B                        (64U)

/* The count of CAN_ID */
#define CAN_ID_COUNT_MB8B                        (64U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB8B                      (64U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB8B2                     (2U)

/* The count of CAN_CS */
#define CAN_CS_COUNT_MB16B                       (42U)

/* The count of CAN_ID */
#define CAN_ID_COUNT_MB16B                       (42U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB16B                     (42U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB16B2                    (4U)

/* The count of CAN_CS */
#define CAN_CS_COUNT_MB32B                       (24U)

/* The count of CAN_ID */
#define CAN_ID_COUNT_MB32B                       (24U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB32B                     (24U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB32B2                    (8U)

/*! @name CS - Message Buffer 0 CS Register..Message Buffer 13 CS Register */
/*! @{ */

#define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
#define CAN_CS_TIME_STAMP_SHIFT                  (0U)
/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
 *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
 *    appears on the CAN bus.
 */
#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)

#define CAN_CS_DLC_MASK                          (0xF0000U)
#define CAN_CS_DLC_SHIFT                         (16U)
/*! DLC - Length of the data to be stored/transmitted. */
#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

#define CAN_CS_RTR_MASK                          (0x100000U)
#define CAN_CS_RTR_SHIFT                         (20U)
/*! RTR - Remote Transmission Request. One/zero for remote/data frame. */
#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

#define CAN_CS_IDE_MASK                          (0x200000U)
#define CAN_CS_IDE_SHIFT                         (21U)
/*! IDE - ID Extended. One/zero for extended/standard format frame. */
#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

#define CAN_CS_SRR_MASK                          (0x400000U)
#define CAN_CS_SRR_SHIFT                         (22U)
/*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */
#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)

#define CAN_CS_CODE_MASK                         (0xF000000U)
#define CAN_CS_CODE_SHIFT                        (24U)
/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
 *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
 */
#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)

#define CAN_CS_ESI_MASK                          (0x20000000U)
#define CAN_CS_ESI_SHIFT                         (29U)
/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */
#define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)

#define CAN_CS_BRS_MASK                          (0x40000000U)
#define CAN_CS_BRS_SHIFT                         (30U)
/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */
#define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)

#define CAN_CS_EDL_MASK                          (0x80000000U)
#define CAN_CS_EDL_SHIFT                         (31U)
/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
 *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
 */
#define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
/*! @} */

/* The count of CAN_CS */
#define CAN_CS_COUNT_MB64B                       (14U)

/*! @name ID - Message Buffer 0 ID Register..Message Buffer 13 ID Register */
/*! @{ */

#define CAN_ID_EXT_MASK                          (0x3FFFFU)
#define CAN_ID_EXT_SHIFT                         (0U)
/*! EXT - Contains extended (LOW word) identifier of message buffer. */
#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)

#define CAN_ID_STD_MASK                          (0x1FFC0000U)
#define CAN_ID_STD_SHIFT                         (18U)
/*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */
#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)

#define CAN_ID_PRIO_MASK                         (0xE0000000U)
#define CAN_ID_PRIO_SHIFT                        (29U)
/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
 *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
 *    ID to define the transmission priority.
 */
#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
/*! @} */

/* The count of CAN_ID */
#define CAN_ID_COUNT_MB64B                       (14U)

/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register */
/*! @{ */

#define CAN_WORD_DATA_BYTE_3_MASK                (0xFFU)
#define CAN_WORD_DATA_BYTE_3_SHIFT               (0U)
/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_3(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)

#define CAN_WORD_DATA_BYTE_7_MASK                (0xFFU)
#define CAN_WORD_DATA_BYTE_7_SHIFT               (0U)
/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_7(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)

#define CAN_WORD_DATA_BYTE_11_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_11_SHIFT              (0U)
/*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_11(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)

#define CAN_WORD_DATA_BYTE_15_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_15_SHIFT              (0U)
/*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_15(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)

#define CAN_WORD_DATA_BYTE_19_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_19_SHIFT              (0U)
/*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_19(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)

#define CAN_WORD_DATA_BYTE_23_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_23_SHIFT              (0U)
/*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_23(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)

#define CAN_WORD_DATA_BYTE_27_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_27_SHIFT              (0U)
/*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_27(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)

#define CAN_WORD_DATA_BYTE_31_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_31_SHIFT              (0U)
/*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_31(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)

#define CAN_WORD_DATA_BYTE_35_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_35_SHIFT              (0U)
/*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_35(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)

#define CAN_WORD_DATA_BYTE_39_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_39_SHIFT              (0U)
/*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_39(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)

#define CAN_WORD_DATA_BYTE_43_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_43_SHIFT              (0U)
/*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_43(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)

#define CAN_WORD_DATA_BYTE_47_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_47_SHIFT              (0U)
/*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_47(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)

#define CAN_WORD_DATA_BYTE_51_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_51_SHIFT              (0U)
/*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_51(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)

#define CAN_WORD_DATA_BYTE_55_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_55_SHIFT              (0U)
/*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_55(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)

#define CAN_WORD_DATA_BYTE_59_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_59_SHIFT              (0U)
/*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_59(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)

#define CAN_WORD_DATA_BYTE_63_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_63_SHIFT              (0U)
/*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_63(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)

#define CAN_WORD_DATA_BYTE_2_MASK                (0xFF00U)
#define CAN_WORD_DATA_BYTE_2_SHIFT               (8U)
/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_2(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)

#define CAN_WORD_DATA_BYTE_6_MASK                (0xFF00U)
#define CAN_WORD_DATA_BYTE_6_SHIFT               (8U)
/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_6(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)

#define CAN_WORD_DATA_BYTE_10_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_10_SHIFT              (8U)
/*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_10(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)

#define CAN_WORD_DATA_BYTE_14_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_14_SHIFT              (8U)
/*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_14(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)

#define CAN_WORD_DATA_BYTE_18_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_18_SHIFT              (8U)
/*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_18(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)

#define CAN_WORD_DATA_BYTE_22_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_22_SHIFT              (8U)
/*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_22(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)

#define CAN_WORD_DATA_BYTE_26_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_26_SHIFT              (8U)
/*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_26(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)

#define CAN_WORD_DATA_BYTE_30_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_30_SHIFT              (8U)
/*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_30(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)

#define CAN_WORD_DATA_BYTE_34_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_34_SHIFT              (8U)
/*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_34(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)

#define CAN_WORD_DATA_BYTE_38_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_38_SHIFT              (8U)
/*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_38(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)

#define CAN_WORD_DATA_BYTE_42_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_42_SHIFT              (8U)
/*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_42(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)

#define CAN_WORD_DATA_BYTE_46_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_46_SHIFT              (8U)
/*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_46(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)

#define CAN_WORD_DATA_BYTE_50_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_50_SHIFT              (8U)
/*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_50(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)

#define CAN_WORD_DATA_BYTE_54_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_54_SHIFT              (8U)
/*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_54(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)

#define CAN_WORD_DATA_BYTE_58_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_58_SHIFT              (8U)
/*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_58(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)

#define CAN_WORD_DATA_BYTE_62_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_62_SHIFT              (8U)
/*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_62(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)

#define CAN_WORD_DATA_BYTE_1_MASK                (0xFF0000U)
#define CAN_WORD_DATA_BYTE_1_SHIFT               (16U)
/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_1(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)

#define CAN_WORD_DATA_BYTE_5_MASK                (0xFF0000U)
#define CAN_WORD_DATA_BYTE_5_SHIFT               (16U)
/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_5(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)

#define CAN_WORD_DATA_BYTE_9_MASK                (0xFF0000U)
#define CAN_WORD_DATA_BYTE_9_SHIFT               (16U)
/*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_9(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)

#define CAN_WORD_DATA_BYTE_13_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_13_SHIFT              (16U)
/*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_13(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)

#define CAN_WORD_DATA_BYTE_17_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_17_SHIFT              (16U)
/*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_17(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)

#define CAN_WORD_DATA_BYTE_21_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_21_SHIFT              (16U)
/*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_21(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)

#define CAN_WORD_DATA_BYTE_25_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_25_SHIFT              (16U)
/*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_25(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)

#define CAN_WORD_DATA_BYTE_29_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_29_SHIFT              (16U)
/*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_29(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)

#define CAN_WORD_DATA_BYTE_33_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_33_SHIFT              (16U)
/*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_33(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)

#define CAN_WORD_DATA_BYTE_37_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_37_SHIFT              (16U)
/*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_37(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)

#define CAN_WORD_DATA_BYTE_41_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_41_SHIFT              (16U)
/*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_41(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)

#define CAN_WORD_DATA_BYTE_45_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_45_SHIFT              (16U)
/*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_45(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)

#define CAN_WORD_DATA_BYTE_49_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_49_SHIFT              (16U)
/*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_49(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)

#define CAN_WORD_DATA_BYTE_53_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_53_SHIFT              (16U)
/*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_53(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)

#define CAN_WORD_DATA_BYTE_57_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_57_SHIFT              (16U)
/*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_57(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)

#define CAN_WORD_DATA_BYTE_61_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_61_SHIFT              (16U)
/*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_61(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)

#define CAN_WORD_DATA_BYTE_0_MASK                (0xFF000000U)
#define CAN_WORD_DATA_BYTE_0_SHIFT               (24U)
/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_0(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)

#define CAN_WORD_DATA_BYTE_4_MASK                (0xFF000000U)
#define CAN_WORD_DATA_BYTE_4_SHIFT               (24U)
/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_4(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)

#define CAN_WORD_DATA_BYTE_8_MASK                (0xFF000000U)
#define CAN_WORD_DATA_BYTE_8_SHIFT               (24U)
/*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_8(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)

#define CAN_WORD_DATA_BYTE_12_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_12_SHIFT              (24U)
/*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_12(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)

#define CAN_WORD_DATA_BYTE_16_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_16_SHIFT              (24U)
/*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_16(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)

#define CAN_WORD_DATA_BYTE_20_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_20_SHIFT              (24U)
/*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_20(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)

#define CAN_WORD_DATA_BYTE_24_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_24_SHIFT              (24U)
/*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_24(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)

#define CAN_WORD_DATA_BYTE_28_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_28_SHIFT              (24U)
/*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_28(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)

#define CAN_WORD_DATA_BYTE_32_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_32_SHIFT              (24U)
/*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_32(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)

#define CAN_WORD_DATA_BYTE_36_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_36_SHIFT              (24U)
/*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_36(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)

#define CAN_WORD_DATA_BYTE_40_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_40_SHIFT              (24U)
/*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_40(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)

#define CAN_WORD_DATA_BYTE_44_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_44_SHIFT              (24U)
/*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_44(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)

#define CAN_WORD_DATA_BYTE_48_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_48_SHIFT              (24U)
/*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_48(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)

#define CAN_WORD_DATA_BYTE_52_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_52_SHIFT              (24U)
/*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_52(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)

#define CAN_WORD_DATA_BYTE_56_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_56_SHIFT              (24U)
/*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_56(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)

#define CAN_WORD_DATA_BYTE_60_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_60_SHIFT              (24U)
/*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD_DATA_BYTE_60(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
/*! @} */

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB64B                     (14U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB64B2                    (16U)

/* The count of CAN_CS */
#define CAN_CS_COUNT                             (64U)

/* The count of CAN_ID */
#define CAN_ID_COUNT                             (64U)

/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
/*! @{ */

#define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
#define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)

#define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
#define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)

#define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
#define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)

#define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
#define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
/*! @} */

/* The count of CAN_WORD0 */
#define CAN_WORD0_COUNT                          (64U)

/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
/*! @{ */

#define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
#define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)

#define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
#define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)

#define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
#define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)

#define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
#define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
/*! @} */

/* The count of CAN_WORD1 */
#define CAN_WORD1_COUNT                          (64U)

/*! @name RXIMR - Rx Individual Mask Registers */
/*! @{ */

#define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
#define CAN_RXIMR_MI_SHIFT                       (0U)
/*! MI - Individual Mask Bits */
#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
/*! @} */

/* The count of CAN_RXIMR */
#define CAN_RXIMR_COUNT                          (64U)

/*! @name CTRL1_PN - Pretended Networking Control 1 Register */
/*! @{ */

#define CAN_CTRL1_PN_FCS_MASK                    (0x3U)
#define CAN_CTRL1_PN_FCS_SHIFT                   (0U)
/*! FCS - Filtering Combination Selection
 *  0b00..Message ID filtering only
 *  0b01..Message ID filtering and payload filtering
 *  0b10..Message ID filtering occurring a specified number of times
 *  0b11..Message ID filtering and payload filtering a specified number of times
 */
#define CAN_CTRL1_PN_FCS(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_FCS_SHIFT)) & CAN_CTRL1_PN_FCS_MASK)

#define CAN_CTRL1_PN_IDFS_MASK                   (0xCU)
#define CAN_CTRL1_PN_IDFS_SHIFT                  (2U)
/*! IDFS - ID Filtering Selection
 *  0b00..Match upon ID contents against an exact target value
 *  0b01..Match upon an ID value greater than or equal to a specified target value
 *  0b10..Match upon an ID value smaller than or equal to a specified target value
 *  0b11..Match upon an ID value inside a range, greater than or equal to a specified lower limit, and smaller
 *        than or equal to a specified upper limit
 */
#define CAN_CTRL1_PN_IDFS(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK)

#define CAN_CTRL1_PN_PLFS_MASK                   (0x30U)
#define CAN_CTRL1_PN_PLFS_SHIFT                  (4U)
/*! PLFS - Payload Filtering Selection
 *  0b00..Match upon a payload contents against an exact target value
 *  0b01..Match upon a payload value greater than or equal to a specified target value
 *  0b10..Match upon a payload value smaller than or equal to a specified target value
 *  0b11..Match upon a payload value inside a range, greater than or equal to a specified lower limit, and smaller
 *        than or equal to a specified upper limit
 */
#define CAN_CTRL1_PN_PLFS(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK)

#define CAN_CTRL1_PN_NMATCH_MASK                 (0xFF00U)
#define CAN_CTRL1_PN_NMATCH_SHIFT                (8U)
/*! NMATCH - Number of Messages Matching the Same Filtering Criteria
 *  0b00000001..Received message must match the predefined filtering criteria for ID and/or PL once before generating a wakeup event.
 *  0b00000010..Received message must match the predefined filtering criteria for ID and/or PL twice before generating a wakeup event.
 *  0b11111111..Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wakeup event.
 */
#define CAN_CTRL1_PN_NMATCH(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK)

#define CAN_CTRL1_PN_WUMF_MSK_MASK               (0x10000U)
#define CAN_CTRL1_PN_WUMF_MSK_SHIFT              (16U)
/*! WUMF_MSK - Wake Up by Match Flag Mask Bit
 *  0b0..Wakeup match event is disabled
 *  0b1..Wakeup match event is enabled
 */
#define CAN_CTRL1_PN_WUMF_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK)

#define CAN_CTRL1_PN_WTOF_MSK_MASK               (0x20000U)
#define CAN_CTRL1_PN_WTOF_MSK_SHIFT              (17U)
/*! WTOF_MSK - Wake Up by Timeout Flag Mask Bit
 *  0b0..Timeout wakeup event is disabled
 *  0b1..Timeout wakeup event is enabled
 */
#define CAN_CTRL1_PN_WTOF_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK)
/*! @} */

/*! @name CTRL2_PN - Pretended Networking Control 2 Register */
/*! @{ */

#define CAN_CTRL2_PN_MATCHTO_MASK                (0xFFFFU)
#define CAN_CTRL2_PN_MATCHTO_SHIFT               (0U)
/*! MATCHTO - Timeout for No Message Matching the Filtering Criteria */
#define CAN_CTRL2_PN_MATCHTO(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK)
/*! @} */

/*! @name WU_MTC - Pretended Networking Wake Up Match Register */
/*! @{ */

#define CAN_WU_MTC_MCOUNTER_MASK                 (0xFF00U)
#define CAN_WU_MTC_MCOUNTER_SHIFT                (8U)
/*! MCOUNTER - Number of Matches when in Pretended Networking */
#define CAN_WU_MTC_MCOUNTER(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK)

#define CAN_WU_MTC_WUMF_MASK                     (0x10000U)
#define CAN_WU_MTC_WUMF_SHIFT                    (16U)
/*! WUMF - Wake Up by Match Flag Bit
 *  0b0..No wakeup by match event detected
 *  0b1..Wakeup by match event detected
 */
#define CAN_WU_MTC_WUMF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK)

#define CAN_WU_MTC_WTOF_MASK                     (0x20000U)
#define CAN_WU_MTC_WTOF_SHIFT                    (17U)
/*! WTOF - Wake Up by Timeout Flag Bit
 *  0b0..No wakeup by timeout event detected
 *  0b1..Wakeup by timeout event detected
 */
#define CAN_WU_MTC_WTOF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK)
/*! @} */

/*! @name FLT_ID1 - Pretended Networking ID Filter 1 Register */
/*! @{ */

#define CAN_FLT_ID1_FLT_ID1_MASK                 (0x1FFFFFFFU)
#define CAN_FLT_ID1_FLT_ID1_SHIFT                (0U)
/*! FLT_ID1 - ID Filter 1 for Pretended Networking filtering */
#define CAN_FLT_ID1_FLT_ID1(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_ID1_SHIFT)) & CAN_FLT_ID1_FLT_ID1_MASK)

#define CAN_FLT_ID1_FLT_RTR_MASK                 (0x20000000U)
#define CAN_FLT_ID1_FLT_RTR_SHIFT                (29U)
/*! FLT_RTR - Remote Transmission Request Filter
 *  0b0..Reject remote frame (accept data frame)
 *  0b1..Accept remote frame
 */
#define CAN_FLT_ID1_FLT_RTR(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_RTR_SHIFT)) & CAN_FLT_ID1_FLT_RTR_MASK)

#define CAN_FLT_ID1_FLT_IDE_MASK                 (0x40000000U)
#define CAN_FLT_ID1_FLT_IDE_SHIFT                (30U)
/*! FLT_IDE - ID Extended Filter
 *  0b0..Accept standard frame format
 *  0b1..Accept extended frame format
 */
#define CAN_FLT_ID1_FLT_IDE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK)
/*! @} */

/*! @name FLT_DLC - Pretended Networking DLC Filter Register */
/*! @{ */

#define CAN_FLT_DLC_FLT_DLC_HI_MASK              (0xFU)
#define CAN_FLT_DLC_FLT_DLC_HI_SHIFT             (0U)
/*! FLT_DLC_HI - Upper Limit for Length of Data Bytes Filter */
#define CAN_FLT_DLC_FLT_DLC_HI(x)                (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_HI_SHIFT)) & CAN_FLT_DLC_FLT_DLC_HI_MASK)

#define CAN_FLT_DLC_FLT_DLC_LO_MASK              (0xF0000U)
#define CAN_FLT_DLC_FLT_DLC_LO_SHIFT             (16U)
/*! FLT_DLC_LO - Lower Limit for Length of Data Bytes Filter */
#define CAN_FLT_DLC_FLT_DLC_LO(x)                (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK)
/*! @} */

/*! @name PL1_LO - Pretended Networking Payload Low Filter 1 Register */
/*! @{ */

#define CAN_PL1_LO_Data_byte_3_MASK              (0xFFU)
#define CAN_PL1_LO_Data_byte_3_SHIFT             (0U)
/*! Data_byte_3 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 3. */
#define CAN_PL1_LO_Data_byte_3(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK)

#define CAN_PL1_LO_Data_byte_2_MASK              (0xFF00U)
#define CAN_PL1_LO_Data_byte_2_SHIFT             (8U)
/*! Data_byte_2 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 2. */
#define CAN_PL1_LO_Data_byte_2(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK)

#define CAN_PL1_LO_Data_byte_1_MASK              (0xFF0000U)
#define CAN_PL1_LO_Data_byte_1_SHIFT             (16U)
/*! Data_byte_1 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 1. */
#define CAN_PL1_LO_Data_byte_1(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK)

#define CAN_PL1_LO_Data_byte_0_MASK              (0xFF000000U)
#define CAN_PL1_LO_Data_byte_0_SHIFT             (24U)
/*! Data_byte_0 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 0. */
#define CAN_PL1_LO_Data_byte_0(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK)
/*! @} */

/*! @name PL1_HI - Pretended Networking Payload High Filter 1 Register */
/*! @{ */

#define CAN_PL1_HI_Data_byte_7_MASK              (0xFFU)
#define CAN_PL1_HI_Data_byte_7_SHIFT             (0U)
/*! Data_byte_7 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 7. */
#define CAN_PL1_HI_Data_byte_7(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK)

#define CAN_PL1_HI_Data_byte_6_MASK              (0xFF00U)
#define CAN_PL1_HI_Data_byte_6_SHIFT             (8U)
/*! Data_byte_6 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 6. */
#define CAN_PL1_HI_Data_byte_6(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK)

#define CAN_PL1_HI_Data_byte_5_MASK              (0xFF0000U)
#define CAN_PL1_HI_Data_byte_5_SHIFT             (16U)
/*! Data_byte_5 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 5. */
#define CAN_PL1_HI_Data_byte_5(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK)

#define CAN_PL1_HI_Data_byte_4_MASK              (0xFF000000U)
#define CAN_PL1_HI_Data_byte_4_SHIFT             (24U)
/*! Data_byte_4 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 4. */
#define CAN_PL1_HI_Data_byte_4(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK)
/*! @} */

/*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 Register / ID Mask Register */
/*! @{ */

#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK   (0x1FFFFFFFU)
#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT  (0U)
/*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering */
#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x)     (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK)

#define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK          (0x20000000U)
#define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT         (29U)
/*! RTR_MSK - Remote Transmission Request Mask Bit
 *  0b0..The corresponding bit in the filter is "don't care"
 *  0b1..The corresponding bit in the filter is checked
 */
#define CAN_FLT_ID2_IDMASK_RTR_MSK(x)            (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK)

#define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK          (0x40000000U)
#define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT         (30U)
/*! IDE_MSK - ID Extended Mask Bit
 *  0b0..The corresponding bit in the filter is "don't care"
 *  0b1..The corresponding bit in the filter is checked
 */
#define CAN_FLT_ID2_IDMASK_IDE_MSK(x)            (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK)
/*! @} */

/*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 Register / Payload Low Mask register */
/*! @{ */

#define CAN_PL2_PLMASK_LO_Data_byte_3_MASK       (0xFFU)
#define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT      (0U)
/*! Data_byte_3 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 3.
 */
#define CAN_PL2_PLMASK_LO_Data_byte_3(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK)

#define CAN_PL2_PLMASK_LO_Data_byte_2_MASK       (0xFF00U)
#define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT      (8U)
/*! Data_byte_2 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 2.
 */
#define CAN_PL2_PLMASK_LO_Data_byte_2(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK)

#define CAN_PL2_PLMASK_LO_Data_byte_1_MASK       (0xFF0000U)
#define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT      (16U)
/*! Data_byte_1 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 1.
 */
#define CAN_PL2_PLMASK_LO_Data_byte_1(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK)

#define CAN_PL2_PLMASK_LO_Data_byte_0_MASK       (0xFF000000U)
#define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT      (24U)
/*! Data_byte_0 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 0.
 */
#define CAN_PL2_PLMASK_LO_Data_byte_0(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK)
/*! @} */

/*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register */
/*! @{ */

#define CAN_PL2_PLMASK_HI_Data_byte_7_MASK       (0xFFU)
#define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT      (0U)
/*! Data_byte_7 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 7.
 */
#define CAN_PL2_PLMASK_HI_Data_byte_7(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK)

#define CAN_PL2_PLMASK_HI_Data_byte_6_MASK       (0xFF00U)
#define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT      (8U)
/*! Data_byte_6 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 6.
 */
#define CAN_PL2_PLMASK_HI_Data_byte_6(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK)

#define CAN_PL2_PLMASK_HI_Data_byte_5_MASK       (0xFF0000U)
#define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT      (16U)
/*! Data_byte_5 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 5.
 */
#define CAN_PL2_PLMASK_HI_Data_byte_5(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK)

#define CAN_PL2_PLMASK_HI_Data_byte_4_MASK       (0xFF000000U)
#define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT      (24U)
/*! Data_byte_4 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 4.
 */
#define CAN_PL2_PLMASK_HI_Data_byte_4(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK)
/*! @} */

/*! @name CS - Wake Up Message Buffer register for C/S */
/*! @{ */

#define CAN_CS_DLC_MASK                          (0xF0000U)
#define CAN_CS_DLC_SHIFT                         (16U)
/*! DLC - Length of Data in Bytes */
#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

#define CAN_CS_RTR_MASK                          (0x100000U)
#define CAN_CS_RTR_SHIFT                         (20U)
/*! RTR - Remote Transmission Request Bit
 *  0b0..Frame is data one (not remote)
 *  0b1..Frame is a remote one
 */
#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

#define CAN_CS_IDE_MASK                          (0x200000U)
#define CAN_CS_IDE_SHIFT                         (21U)
/*! IDE - ID Extended Bit
 *  0b0..Frame format is standard
 *  0b1..Frame format is extended
 */
#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

#define CAN_CS_SRR_MASK                          (0x400000U)
#define CAN_CS_SRR_SHIFT                         (22U)
/*! SRR - Substitute Remote Request */
#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
/*! @} */

/* The count of CAN_CS */
#define CAN_WMB_CS_COUNT                         (4U)

/*! @name ID - Wake Up Message Buffer Register for ID */
/*! @{ */

#define CAN_ID_ID_MASK                           (0x1FFFFFFFU)
#define CAN_ID_ID_SHIFT                          (0U)
/*! ID - Received ID under Pretended Networking mode */
#define CAN_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_ID_ID_SHIFT)) & CAN_ID_ID_MASK)
/*! @} */

/* The count of CAN_ID */
#define CAN_WMB_ID_COUNT                         (4U)

/*! @name D03 - Wake Up Message Buffer Register for Data 0-3 */
/*! @{ */

#define CAN_D03_Data_byte_3_MASK                 (0xFFU)
#define CAN_D03_Data_byte_3_SHIFT                (0U)
/*! Data_byte_3 - Received payload corresponding to the data byte 3 under Pretended Networking mode */
#define CAN_D03_Data_byte_3(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_D03_Data_byte_3_SHIFT)) & CAN_D03_Data_byte_3_MASK)

#define CAN_D03_Data_byte_2_MASK                 (0xFF00U)
#define CAN_D03_Data_byte_2_SHIFT                (8U)
/*! Data_byte_2 - Received payload corresponding to the data byte 2 under Pretended Networking mode */
#define CAN_D03_Data_byte_2(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_D03_Data_byte_2_SHIFT)) & CAN_D03_Data_byte_2_MASK)

#define CAN_D03_Data_byte_1_MASK                 (0xFF0000U)
#define CAN_D03_Data_byte_1_SHIFT                (16U)
/*! Data_byte_1 - Received payload corresponding to the data byte 1 under Pretended Networking mode */
#define CAN_D03_Data_byte_1(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_D03_Data_byte_1_SHIFT)) & CAN_D03_Data_byte_1_MASK)

#define CAN_D03_Data_byte_0_MASK                 (0xFF000000U)
#define CAN_D03_Data_byte_0_SHIFT                (24U)
/*! Data_byte_0 - Received payload corresponding to the data byte 0 under Pretended Networking mode */
#define CAN_D03_Data_byte_0(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_D03_Data_byte_0_SHIFT)) & CAN_D03_Data_byte_0_MASK)
/*! @} */

/* The count of CAN_D03 */
#define CAN_D03_COUNT                            (4U)

/*! @name D47 - Wake Up Message Buffer Register Data 4-7 */
/*! @{ */

#define CAN_D47_Data_byte_7_MASK                 (0xFFU)
#define CAN_D47_Data_byte_7_SHIFT                (0U)
/*! Data_byte_7 - Received payload corresponding to the data byte 7 under Pretended Networking mode */
#define CAN_D47_Data_byte_7(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_D47_Data_byte_7_SHIFT)) & CAN_D47_Data_byte_7_MASK)

#define CAN_D47_Data_byte_6_MASK                 (0xFF00U)
#define CAN_D47_Data_byte_6_SHIFT                (8U)
/*! Data_byte_6 - Received payload corresponding to the data byte 6 under Pretended Networking mode */
#define CAN_D47_Data_byte_6(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_D47_Data_byte_6_SHIFT)) & CAN_D47_Data_byte_6_MASK)

#define CAN_D47_Data_byte_5_MASK                 (0xFF0000U)
#define CAN_D47_Data_byte_5_SHIFT                (16U)
/*! Data_byte_5 - Received payload corresponding to the data byte 5 under Pretended Networking mode */
#define CAN_D47_Data_byte_5(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_D47_Data_byte_5_SHIFT)) & CAN_D47_Data_byte_5_MASK)

#define CAN_D47_Data_byte_4_MASK                 (0xFF000000U)
#define CAN_D47_Data_byte_4_SHIFT                (24U)
/*! Data_byte_4 - Received payload corresponding to the data byte 4 under Pretended Networking mode */
#define CAN_D47_Data_byte_4(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_D47_Data_byte_4_SHIFT)) & CAN_D47_Data_byte_4_MASK)
/*! @} */

/* The count of CAN_D47 */
#define CAN_D47_COUNT                            (4U)

/*! @name EPRS - Enhanced CAN Bit Timing Prescalers */
/*! @{ */

#define CAN_EPRS_ENPRESDIV_MASK                  (0x3FFU)
#define CAN_EPRS_ENPRESDIV_SHIFT                 (0U)
/*! ENPRESDIV - Extended Nominal Prescaler Division Factor */
#define CAN_EPRS_ENPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK)

#define CAN_EPRS_EDPRESDIV_MASK                  (0x3FF0000U)
#define CAN_EPRS_EDPRESDIV_SHIFT                 (16U)
/*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */
#define CAN_EPRS_EDPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK)
/*! @} */

/*! @name ENCBT - Enhanced Nominal CAN Bit Timing */
/*! @{ */

#define CAN_ENCBT_NTSEG1_MASK                    (0xFFU)
#define CAN_ENCBT_NTSEG1_SHIFT                   (0U)
/*! NTSEG1 - Nominal Time Segment 1 */
#define CAN_ENCBT_NTSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK)

#define CAN_ENCBT_NTSEG2_MASK                    (0x7F000U)
#define CAN_ENCBT_NTSEG2_SHIFT                   (12U)
/*! NTSEG2 - Nominal Time Segment 2 */
#define CAN_ENCBT_NTSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK)

#define CAN_ENCBT_NRJW_MASK                      (0x1FC00000U)
#define CAN_ENCBT_NRJW_SHIFT                     (22U)
/*! NRJW - Nominal Resynchronization Jump Width */
#define CAN_ENCBT_NRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK)
/*! @} */

/*! @name EDCBT - Enhanced Data Phase CAN bit Timing */
/*! @{ */

#define CAN_EDCBT_DTSEG1_MASK                    (0x1FU)
#define CAN_EDCBT_DTSEG1_SHIFT                   (0U)
/*! DTSEG1 - Data Phase Segment 1 */
#define CAN_EDCBT_DTSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK)

#define CAN_EDCBT_DTSEG2_MASK                    (0xF000U)
#define CAN_EDCBT_DTSEG2_SHIFT                   (12U)
/*! DTSEG2 - Data Phase Time Segment 2 */
#define CAN_EDCBT_DTSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK)

#define CAN_EDCBT_DRJW_MASK                      (0x3C00000U)
#define CAN_EDCBT_DRJW_SHIFT                     (22U)
/*! DRJW - Data Phase Resynchronization Jump Width */
#define CAN_EDCBT_DRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK)
/*! @} */

/*! @name ETDC - Enhanced Transceiver Delay Compensation */
/*! @{ */

#define CAN_ETDC_ETDCVAL_MASK                    (0xFFU)
#define CAN_ETDC_ETDCVAL_SHIFT                   (0U)
/*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */
#define CAN_ETDC_ETDCVAL(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK)

#define CAN_ETDC_ETDCFAIL_MASK                   (0x8000U)
#define CAN_ETDC_ETDCFAIL_SHIFT                  (15U)
/*! ETDCFAIL - Transceiver Delay Compensation Fail
 *  0b0..Measured loop delay is in range.
 *  0b1..Measured loop delay is out of range.
 */
#define CAN_ETDC_ETDCFAIL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK)

#define CAN_ETDC_ETDCOFF_MASK                    (0x7F0000U)
#define CAN_ETDC_ETDCOFF_SHIFT                   (16U)
/*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */
#define CAN_ETDC_ETDCOFF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK)

#define CAN_ETDC_TDMDIS_MASK                     (0x40000000U)
#define CAN_ETDC_TDMDIS_SHIFT                    (30U)
/*! TDMDIS - Transceiver Delay Measurement Disable
 *  0b0..TDC measurement is enabled
 *  0b1..TDC measurement is disabled
 */
#define CAN_ETDC_TDMDIS(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK)

#define CAN_ETDC_ETDCEN_MASK                     (0x80000000U)
#define CAN_ETDC_ETDCEN_SHIFT                    (31U)
/*! ETDCEN - Transceiver Delay Compensation Enable
 *  0b0..TDC is disabled
 *  0b1..TDC is enabled
 */
#define CAN_ETDC_ETDCEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK)
/*! @} */

/*! @name FDCTRL - CAN FD Control Register */
/*! @{ */

#define CAN_FDCTRL_TDCVAL_MASK                   (0x3FU)
#define CAN_FDCTRL_TDCVAL_SHIFT                  (0U)
/*! TDCVAL - Transceiver Delay Compensation Value */
#define CAN_FDCTRL_TDCVAL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)

#define CAN_FDCTRL_TDCOFF_MASK                   (0x1F00U)
#define CAN_FDCTRL_TDCOFF_SHIFT                  (8U)
/*! TDCOFF - Transceiver Delay Compensation Offset */
#define CAN_FDCTRL_TDCOFF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)

#define CAN_FDCTRL_TDCFAIL_MASK                  (0x4000U)
#define CAN_FDCTRL_TDCFAIL_SHIFT                 (14U)
/*! TDCFAIL - Transceiver Delay Compensation Fail
 *  0b0..Measured loop delay is in range.
 *  0b1..Measured loop delay is out of range.
 */
#define CAN_FDCTRL_TDCFAIL(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)

#define CAN_FDCTRL_TDCEN_MASK                    (0x8000U)
#define CAN_FDCTRL_TDCEN_SHIFT                   (15U)
/*! TDCEN - Transceiver Delay Compensation Enable
 *  0b0..TDC is disabled
 *  0b1..TDC is enabled
 */
#define CAN_FDCTRL_TDCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)

#define CAN_FDCTRL_MBDSR0_MASK                   (0x30000U)
#define CAN_FDCTRL_MBDSR0_SHIFT                  (16U)
/*! MBDSR0 - Message Buffer Data Size for Region 0
 *  0b00..Selects 8 bytes per message buffer.
 *  0b01..Selects 16 bytes per message buffer.
 *  0b10..Selects 32 bytes per message buffer.
 *  0b11..Selects 64 bytes per message buffer.
 */
#define CAN_FDCTRL_MBDSR0(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)

#define CAN_FDCTRL_MBDSR1_MASK                   (0x180000U)
#define CAN_FDCTRL_MBDSR1_SHIFT                  (19U)
/*! MBDSR1 - Message Buffer Data Size for Region 1
 *  0b00..Selects 8 bytes per message buffer.
 *  0b01..Selects 16 bytes per message buffer.
 *  0b10..Selects 32 bytes per message buffer.
 *  0b11..Selects 64 bytes per message buffer.
 */
#define CAN_FDCTRL_MBDSR1(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)

#define CAN_FDCTRL_FDRATE_MASK                   (0x80000000U)
#define CAN_FDCTRL_FDRATE_SHIFT                  (31U)
/*! FDRATE - Bit Rate Switch Enable
 *  0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
 *  0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
 */
#define CAN_FDCTRL_FDRATE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
/*! @} */

/*! @name FDCBT - CAN FD Bit Timing Register */
/*! @{ */

#define CAN_FDCBT_FPSEG2_MASK                    (0x7U)
#define CAN_FDCBT_FPSEG2_SHIFT                   (0U)
/*! FPSEG2 - Fast Phase Segment 2 */
#define CAN_FDCBT_FPSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)

#define CAN_FDCBT_FPSEG1_MASK                    (0xE0U)
#define CAN_FDCBT_FPSEG1_SHIFT                   (5U)
/*! FPSEG1 - Fast Phase Segment 1 */
#define CAN_FDCBT_FPSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)

#define CAN_FDCBT_FPROPSEG_MASK                  (0x7C00U)
#define CAN_FDCBT_FPROPSEG_SHIFT                 (10U)
/*! FPROPSEG - Fast Propagation Segment */
#define CAN_FDCBT_FPROPSEG(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)

#define CAN_FDCBT_FRJW_MASK                      (0x70000U)
#define CAN_FDCBT_FRJW_SHIFT                     (16U)
/*! FRJW - Fast Resync Jump Width */
#define CAN_FDCBT_FRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)

#define CAN_FDCBT_FPRESDIV_MASK                  (0x3FF00000U)
#define CAN_FDCBT_FPRESDIV_SHIFT                 (20U)
/*! FPRESDIV - Fast Prescaler Division Factor */
#define CAN_FDCBT_FPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
/*! @} */

/*! @name FDCRC - CAN FD CRC Register */
/*! @{ */

#define CAN_FDCRC_FD_TXCRC_MASK                  (0x1FFFFFU)
#define CAN_FDCRC_FD_TXCRC_SHIFT                 (0U)
/*! FD_TXCRC - Extended Transmitted CRC value */
#define CAN_FDCRC_FD_TXCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)

#define CAN_FDCRC_FD_MBCRC_MASK                  (0x7F000000U)
#define CAN_FDCRC_FD_MBCRC_SHIFT                 (24U)
/*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC */
#define CAN_FDCRC_FD_MBCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
/*! @} */

/*! @name ERFCR - Enhanced Rx FIFO Control Register */
/*! @{ */

#define CAN_ERFCR_ERFWM_MASK                     (0x1FU)
#define CAN_ERFCR_ERFWM_SHIFT                    (0U)
/*! ERFWM - Enhanced Rx FIFO Watermark */
#define CAN_ERFCR_ERFWM(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK)

#define CAN_ERFCR_NFE_MASK                       (0x3F00U)
#define CAN_ERFCR_NFE_SHIFT                      (8U)
/*! NFE - Number of Enhanced Rx FIFO Filter Elements */
#define CAN_ERFCR_NFE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK)

#define CAN_ERFCR_NEXIF_MASK                     (0x7F0000U)
#define CAN_ERFCR_NEXIF_SHIFT                    (16U)
/*! NEXIF - Number of Extended ID Filter Elements */
#define CAN_ERFCR_NEXIF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK)

#define CAN_ERFCR_DMALW_MASK                     (0x7C000000U)
#define CAN_ERFCR_DMALW_SHIFT                    (26U)
/*! DMALW - DMA Last Word */
#define CAN_ERFCR_DMALW(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK)

#define CAN_ERFCR_ERFEN_MASK                     (0x80000000U)
#define CAN_ERFCR_ERFEN_SHIFT                    (31U)
/*! ERFEN - Enhanced Rx FIFO enable
 *  0b0..Enhanced Rx FIFO is disabled
 *  0b1..Enhanced Rx FIFO is enabled
 */
#define CAN_ERFCR_ERFEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/*! @} */

/*! @name ERFIER - Enhanced Rx FIFO Interrupt Enable Register */
/*! @{ */

#define CAN_ERFIER_ERFDAIE_MASK                  (0x10000000U)
#define CAN_ERFIER_ERFDAIE_SHIFT                 (28U)
/*! ERFDAIE - Enhanced Rx FIFO Data Available Interrupt Enable
 *  0b0..Enhanced Rx FIFO Data Available interrupt is disabled
 *  0b1..Enhanced Rx FIFO Data Available interrupt is enabled
 */
#define CAN_ERFIER_ERFDAIE(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK)

#define CAN_ERFIER_ERFWMIIE_MASK                 (0x20000000U)
#define CAN_ERFIER_ERFWMIIE_SHIFT                (29U)
/*! ERFWMIIE - Enhanced Rx FIFO Watermark Indication Interrupt Enable
 *  0b0..Enhanced Rx FIFO Watermark interrupt is disabled
 *  0b1..Enhanced Rx FIFO Watermark interrupt is enabled
 */
#define CAN_ERFIER_ERFWMIIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK)

#define CAN_ERFIER_ERFOVFIE_MASK                 (0x40000000U)
#define CAN_ERFIER_ERFOVFIE_SHIFT                (30U)
/*! ERFOVFIE - Enhanced Rx FIFO Overflow Interrupt Enable
 *  0b0..Enhanced Rx FIFO Overflow is disabled
 *  0b1..Enhanced Rx FIFO Overflow is enabled
 */
#define CAN_ERFIER_ERFOVFIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK)

#define CAN_ERFIER_ERFUFWIE_MASK                 (0x80000000U)
#define CAN_ERFIER_ERFUFWIE_SHIFT                (31U)
/*! ERFUFWIE - Enhanced Rx FIFO Underflow Interrupt Enable
 *  0b0..Enhanced Rx FIFO Underflow interrupt is disabled
 *  0b1..Enhanced Rx FIFO Underflow interrupt is enabled
 */
#define CAN_ERFIER_ERFUFWIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK)
/*! @} */

/*! @name ERFSR - Enhanced Rx FIFO Status Register */
/*! @{ */

#define CAN_ERFSR_ERFEL_MASK                     (0x3FU)
#define CAN_ERFSR_ERFEL_SHIFT                    (0U)
/*! ERFEL - Enhanced Rx FIFO Elements */
#define CAN_ERFSR_ERFEL(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK)

#define CAN_ERFSR_ERFF_MASK                      (0x10000U)
#define CAN_ERFSR_ERFF_SHIFT                     (16U)
/*! ERFF - Enhanced Rx FIFO full
 *  0b0..Enhanced Rx FIFO is not full
 *  0b1..Enhanced Rx FIFO is full
 */
#define CAN_ERFSR_ERFF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK)

#define CAN_ERFSR_ERFE_MASK                      (0x20000U)
#define CAN_ERFSR_ERFE_SHIFT                     (17U)
/*! ERFE - Enhanced Rx FIFO empty
 *  0b0..Enhanced Rx FIFO is not empty
 *  0b1..Enhanced Rx FIFO is empty
 */
#define CAN_ERFSR_ERFE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK)

#define CAN_ERFSR_ERFCLR_MASK                    (0x8000000U)
#define CAN_ERFSR_ERFCLR_SHIFT                   (27U)
/*! ERFCLR - Enhanced Rx FIFO Clear
 *  0b0..No effect
 *  0b1..Clear Enhanced Rx FIFO content
 */
#define CAN_ERFSR_ERFCLR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK)

#define CAN_ERFSR_ERFDA_MASK                     (0x10000000U)
#define CAN_ERFSR_ERFDA_SHIFT                    (28U)
/*! ERFDA - Enhanced Rx FIFO Data Available
 *  0b0..No such occurrence
 *  0b1..There is at least one message stored in Enhanced Rx FIFO
 */
#define CAN_ERFSR_ERFDA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK)

#define CAN_ERFSR_ERFWMI_MASK                    (0x20000000U)
#define CAN_ERFSR_ERFWMI_SHIFT                   (29U)
/*! ERFWMI - Enhanced Rx FIFO Watermark Indication
 *  0b0..No such occurrence
 *  0b1..The number of messages in FIFO is greater than the watermark
 */
#define CAN_ERFSR_ERFWMI(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)

#define CAN_ERFSR_ERFOVF_MASK                    (0x40000000U)
#define CAN_ERFSR_ERFOVF_SHIFT                   (30U)
/*! ERFOVF - Enhanced Rx FIFO Overflow
 *  0b0..No such occurrence
 *  0b1..Enhanced Rx FIFO overflow
 */
#define CAN_ERFSR_ERFOVF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK)

#define CAN_ERFSR_ERFUFW_MASK                    (0x80000000U)
#define CAN_ERFSR_ERFUFW_SHIFT                   (31U)
/*! ERFUFW - Enhanced Rx FIFO Underflow
 *  0b0..No such occurrence
 *  0b1..Enhanced Rx FIFO underflow
 */
#define CAN_ERFSR_ERFUFW(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK)
/*! @} */

/*! @name HR_TIME_STAMP - High Resolution Time Stamp */
/*! @{ */

#define CAN_HR_TIME_STAMP_TS_MASK                (0xFFFFFFFFU)
#define CAN_HR_TIME_STAMP_TS_SHIFT               (0U)
/*! TS - High Resolution Time Stamp */
#define CAN_HR_TIME_STAMP_TS(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_HR_TIME_STAMP_TS_SHIFT)) & CAN_HR_TIME_STAMP_TS_MASK)
/*! @} */

/* The count of CAN_HR_TIME_STAMP */
#define CAN_HR_TIME_STAMP_COUNT                  (64U)

/*! @name ERFFEL - Enhanced Rx FIFO Filter Element */
/*! @{ */

#define CAN_ERFFEL_FEL_MASK                      (0xFFFFFFFFU)
#define CAN_ERFFEL_FEL_SHIFT                     (0U)
/*! FEL - Filter Element Bits */
#define CAN_ERFFEL_FEL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK)
/*! @} */

/* The count of CAN_ERFFEL */
#define CAN_ERFFEL_COUNT                         (32U)


/*!
 * @}
 */ /* end of group CAN_Register_Masks */


/* CAN - Peripheral instance base addresses */
/** Peripheral CAN0 base address */
#define CAN0_BASE                                (0x280A8000u)
/** Peripheral CAN0 base pointer */
#define CAN0                                     ((CAN_Type *)CAN0_BASE)
/** Array initializer of CAN peripheral base addresses */
#define CAN_BASE_ADDRS                           { CAN0_BASE }
/** Array initializer of CAN peripheral base pointers */
#define CAN_BASE_PTRS                            { CAN0 }

/*!
 * @}
 */ /* end of group CAN_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CASPER Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer
 * @{
 */

/** CASPER - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL0;                             /**< Control 0, offset: 0x0 */
  __IO uint32_t CTRL1;                             /**< Control 1, offset: 0x4 */
       uint8_t RESERVED_0[4];
  __IO uint32_t STATUS;                            /**< Status, offset: 0xC */
  __IO uint32_t INTENSET;                          /**< Interrupt Enable Set, offset: 0x10 */
  __IO uint32_t INTENCLR;                          /**< Interrupt Enable Clear, offset: 0x14 */
  __I  uint32_t INTSTAT;                           /**< Interrupt status, offset: 0x18 */
       uint8_t RESERVED_1[4];
  __IO uint32_t AREG;                              /**< A Register, offset: 0x20 */
  __IO uint32_t BREG;                              /**< B Register, offset: 0x24 */
  __IO uint32_t CREG;                              /**< C Register, offset: 0x28 */
  __IO uint32_t DREG;                              /**< D Register, offset: 0x2C */
  __IO uint32_t RES0;                              /**< Result Register 0, offset: 0x30 */
  __IO uint32_t RES1;                              /**< Result Register 1, offset: 0x34 */
  __IO uint32_t RES2;                              /**< Result Register 2, offset: 0x38 */
  __IO uint32_t RES3;                              /**< Result Register 3, offset: 0x3C */
       uint8_t RESERVED_2[32];
  __IO uint32_t MASK;                              /**< Mask, offset: 0x60 */
  __IO uint32_t REMASK;                            /**< Remask, offset: 0x64 */
       uint8_t RESERVED_3[24];
  __IO uint32_t LOCK;                              /**< Lock, offset: 0x80 */
} CASPER_Type;

/* ----------------------------------------------------------------------------
   -- CASPER Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CASPER_Register_Masks CASPER Register Masks
 * @{
 */

/*! @name CTRL0 - Control 0 */
/*! @{ */

#define CASPER_CTRL0_ABBPAIR_MASK                (0x1U)
#define CASPER_CTRL0_ABBPAIR_SHIFT               (0U)
/*! ABBPAIR - ABOFF Bank Pair
 *  0b0..Bank-pair 0 (1st)
 *  0b1..Bank-pair 1 (2nd)
 */
#define CASPER_CTRL0_ABBPAIR(x)                  (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK)

#define CASPER_CTRL0_ABOFF_MASK                  (0x4U)
#define CASPER_CTRL0_ABOFF_SHIFT                 (2U)
/*! ABOFF - AB Offset */
#define CASPER_CTRL0_ABOFF(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK)

#define CASPER_CTRL0_CDBPAIR_MASK                (0x10000U)
#define CASPER_CTRL0_CDBPAIR_SHIFT               (16U)
/*! CDBPAIR - CDOFF Bank Pair
 *  0b0..Bank-pair 0 (1st)
 *  0b1..Bank-pair 1 (2nd)
 */
#define CASPER_CTRL0_CDBPAIR(x)                  (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK)

#define CASPER_CTRL0_CDOFF_MASK                  (0x1FFC0000U)
#define CASPER_CTRL0_CDOFF_SHIFT                 (18U)
/*! CDOFF - CD Offset */
#define CASPER_CTRL0_CDOFF(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK)
/*! @} */

/*! @name CTRL1 - Control 1 */
/*! @{ */

#define CASPER_CTRL1_ITER_MASK                   (0xFFU)
#define CASPER_CTRL1_ITER_SHIFT                  (0U)
/*! ITER - Interation Counter */
#define CASPER_CTRL1_ITER(x)                     (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK)

#define CASPER_CTRL1_MODE_MASK                   (0xFF00U)
#define CASPER_CTRL1_MODE_SHIFT                  (8U)
/*! MODE - Mode */
#define CASPER_CTRL1_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)

#define CASPER_CTRL1_RESBPAIR_MASK               (0x10000U)
#define CASPER_CTRL1_RESBPAIR_SHIFT              (16U)
/*! RESBPAIR - RESOFF Bank Pair
 *  0b0..Bank-pair 0 (1st)
 *  0b1..Bank-pair 1 (2nd)
 */
#define CASPER_CTRL1_RESBPAIR(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK)

#define CASPER_CTRL1_RESOFF_MASK                 (0x1FFC0000U)
#define CASPER_CTRL1_RESOFF_SHIFT                (18U)
/*! RESOFF - Result Offset */
#define CASPER_CTRL1_RESOFF(x)                   (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK)

#define CASPER_CTRL1_CSKIP_MASK                  (0xC0000000U)
#define CASPER_CTRL1_CSKIP_SHIFT                 (30U)
/*! CSKIP - Skip Rules on Carry
 *  0b00..No Skip
 *  0b01..Skip if Carry is 1
 *  0b10..Skip if Carry is 0
 *  0b11..Set CTRLOFF to CDOFF and Skip
 */
#define CASPER_CTRL1_CSKIP(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK)
/*! @} */

/*! @name STATUS - Status */
/*! @{ */

#define CASPER_STATUS_DONE_MASK                  (0x1U)
#define CASPER_STATUS_DONE_SHIFT                 (0U)
/*! DONE - Done
 *  0b0..Busy or just cleared
 *  0b1..Completed last operation
 */
#define CASPER_STATUS_DONE(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK)

#define CASPER_STATUS_CARRY_MASK                 (0x10U)
#define CASPER_STATUS_CARRY_SHIFT                (4U)
/*! CARRY - Carry
 *  0b0..Carry was 0 or no carry
 *  0b1..Carry was 1
 */
#define CASPER_STATUS_CARRY(x)                   (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK)

#define CASPER_STATUS_BUSY_MASK                  (0x20U)
#define CASPER_STATUS_BUSY_SHIFT                 (5U)
/*! BUSY - Busy
 *  0b0..Not busy - is idle
 *  0b1..Is busy
 */
#define CASPER_STATUS_BUSY(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK)
/*! @} */

/*! @name INTENSET - Interrupt Enable Set */
/*! @{ */

#define CASPER_INTENSET_DONE_MASK                (0x1U)
#define CASPER_INTENSET_DONE_SHIFT               (0U)
/*! DONE - Done
 *  0b0..Do not interrupt when done
 *  0b1..Interrupt when done
 */
#define CASPER_INTENSET_DONE(x)                  (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK)
/*! @} */

/*! @name INTENCLR - Interrupt Enable Clear */
/*! @{ */

#define CASPER_INTENCLR_DONE_MASK                (0x1U)
#define CASPER_INTENCLR_DONE_SHIFT               (0U)
/*! DONE - Done
 *  0b0..If written 0, ignored
 *  0b1..If written 1, do not interrupt when done.
 */
#define CASPER_INTENCLR_DONE(x)                  (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK)
/*! @} */

/*! @name INTSTAT - Interrupt status */
/*! @{ */

#define CASPER_INTSTAT_DONE_MASK                 (0x1U)
#define CASPER_INTSTAT_DONE_SHIFT                (0U)
/*! DONE - If set, interrupt is caused by accelerator being done.
 *  0b0..Not caused by accelerator being done
 *  0b1..Caused by accelerator being done
 */
#define CASPER_INTSTAT_DONE(x)                   (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK)
/*! @} */

/*! @name AREG - A Register */
/*! @{ */

#define CASPER_AREG_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_AREG_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register Value */
#define CASPER_AREG_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK)
/*! @} */

/*! @name BREG - B Register */
/*! @{ */

#define CASPER_BREG_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_BREG_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register Value */
#define CASPER_BREG_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK)
/*! @} */

/*! @name CREG - C Register */
/*! @{ */

#define CASPER_CREG_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_CREG_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register Value */
#define CASPER_CREG_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK)
/*! @} */

/*! @name DREG - D Register */
/*! @{ */

#define CASPER_DREG_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_DREG_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register Value */
#define CASPER_DREG_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK)
/*! @} */

/*! @name RES0 - Result Register 0 */
/*! @{ */

#define CASPER_RES0_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_RES0_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register Value */
#define CASPER_RES0_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK)
/*! @} */

/*! @name RES1 - Result Register 1 */
/*! @{ */

#define CASPER_RES1_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_RES1_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). */
#define CASPER_RES1_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK)
/*! @} */

/*! @name RES2 - Result Register 2 */
/*! @{ */

#define CASPER_RES2_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_RES2_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register Value */
#define CASPER_RES2_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK)
/*! @} */

/*! @name RES3 - Result Register 3 */
/*! @{ */

#define CASPER_RES3_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_RES3_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). */
#define CASPER_RES3_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK)
/*! @} */

/*! @name MASK - Mask */
/*! @{ */

#define CASPER_MASK_MASK_MASK                    (0xFFFFFFFFU)
#define CASPER_MASK_MASK_SHIFT                   (0U)
/*! MASK - Mask */
#define CASPER_MASK_MASK(x)                      (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK)
/*! @} */

/*! @name REMASK - Remask */
/*! @{ */

#define CASPER_REMASK_MASK_MASK                  (0xFFFFFFFFU)
#define CASPER_REMASK_MASK_SHIFT                 (0U)
/*! MASK - Mask */
#define CASPER_REMASK_MASK(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK)
/*! @} */

/*! @name LOCK - Lock */
/*! @{ */

#define CASPER_LOCK_LOCK_MASK                    (0x1U)
#define CASPER_LOCK_LOCK_SHIFT                   (0U)
/*! LOCK - Lock
 *  0b0..Unlock
 *  0b1..Lock to current security level
 */
#define CASPER_LOCK_LOCK(x)                      (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK)

#define CASPER_LOCK_KEY_MASK                     (0x1FFF0U)
#define CASPER_LOCK_KEY_SHIFT                    (4U)
/*! KEY - Key
 *  0b0011100111101..Key Value
 */
#define CASPER_LOCK_KEY(x)                       (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CASPER_Register_Masks */


/* CASPER - Peripheral instance base addresses */
/** Peripheral CASPER base address */
#define CASPER_BASE                              (0x28410000u)
/** Peripheral CASPER base pointer */
#define CASPER                                   ((CASPER_Type *)CASPER_BASE)
/** Array initializer of CASPER peripheral base addresses */
#define CASPER_BASE_ADDRS                        { CASPER_BASE }
/** Array initializer of CASPER peripheral base pointers */
#define CASPER_BASE_PTRS                         { CASPER }

/*!
 * @}
 */ /* end of group CASPER_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CGC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CGC_Peripheral_Access_Layer CGC Peripheral Access Layer
 * @{
 */

/** CGC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __IO uint32_t CM33CLK;                           /**< Clock Selection and Dividers for the M33 Domain, offset: 0x10 */
       uint8_t RESERVED_1[8];
  __IO uint32_t FUSIONCLK;                         /**< Clock Selection and Dividers for the Fusion DSP Domain, offset: 0x1C */
  __IO uint32_t CLKOUTCFG;                         /**< Clockout selection for Real Time Domain, offset: 0x20 */
       uint8_t RESERVED_2[108];
  __IO uint32_t CLKDIVRST;                         /**< Clk Dividers Reset, offset: 0x90 */
       uint8_t RESERVED_3[112];
  __IO uint32_t SOSCCSR;                           /**< System OSC Control Status Register, offset: 0x104 */
  __IO uint32_t SOSCDIV;                           /**< Clock Dividers for the SYS OSC Oscilator, offset: 0x108 */
  __IO uint32_t SOSCCFG;                           /**< System Oscillator Configuration Register, offset: 0x10C */
       uint8_t RESERVED_4[240];
  __IO uint32_t FROCSR;                            /**< FRO Control Status Register, offset: 0x200 */
  __IO uint32_t FROCTRL;                           /**< FRO Control Register, offset: 0x204 */
  __I  uint32_t FROCAPVAL;                         /**< FRO Cap Val Register, offset: 0x208 */
       uint8_t RESERVED_5[4];
  __IO uint32_t FRORDTRIM;                         /**< RD Trim Values for FRO, offset: 0x210 */
  __IO uint32_t FROSCTRIM;                         /**< SC TRIM value for FRO, offset: 0x214 */
       uint8_t RESERVED_6[8];
  __IO uint32_t FRODIV;                            /**< Clock Dividers for the FFRO 192 MHz Oscilator, offset: 0x220 */
       uint8_t RESERVED_7[12];
  __I  uint32_t FRORDTRIM_FUSE;                    /**< Trim values loaded from fuses, offset: 0x230 */
       uint8_t RESERVED_8[12];
  __I  uint32_t FROSCTRIM_FUSE;                    /**< SC Trim Values loaded from fuses, offset: 0x240 */
       uint8_t RESERVED_9[188];
  __IO uint32_t LPOSCCSR;                          /**< Low Power OSC Control Status Register, offset: 0x300 */
  __IO uint32_t LPOSCCTRL;                         /**< LPO Oscillator Control Register, offset: 0x304 */
       uint8_t RESERVED_10[252];
  __IO uint32_t ROSCCTRL;                          /**< ROSCCSR, offset: 0x404 */
       uint8_t RESERVED_11[248];
  __IO uint32_t PLL0CSR;                           /**< System OSC Control Status Register, offset: 0x500 */
  __IO uint32_t PLL0DIV_VCO;                       /**< Clock Dividers for the fractional PLL0, offset: 0x504 */
  __IO uint32_t PLL0DIV_PFD_0;                     /**< Clock Dividers for the fractional PLL0, offset: 0x508 */
       uint8_t RESERVED_12[4];
  __IO uint32_t PLL0CFG;                           /**< PLL0 Register Enable, offset: 0x510 */
  __IO uint32_t PLL0PFDCFG;                        /**< PLL0 Configuration Register, offset: 0x514 */
       uint8_t RESERVED_13[12];
  __IO uint32_t PLL0LOCK;                          /**< PLL LOCK Configuration Register, offset: 0x524 */
       uint8_t RESERVED_14[216];
  __IO uint32_t PLL1CSR;                           /**< PLL1 Control Status Register, offset: 0x600 */
  __IO uint32_t PLL1DIV_VCO;                       /**< Clock Dividers for the fractional PLL1, offset: 0x604 */
  __IO uint32_t PLL1DIV_PFD_0;                     /**< Clock Dividers for the fractional PLL1, offset: 0x608 */
       uint8_t RESERVED_15[4];
  __IO uint32_t PLL1CFG;                           /**< PLL1 Configuration Register, offset: 0x610 */
  __IO uint32_t PLL1PFDCFG;                        /**< PLL1 Configuration Register, offset: 0x614 */
  __IO uint32_t PLL1DENOM;                         /**< PLL Denominator Register, offset: 0x618 */
  __IO uint32_t PLL1NUM;                           /**< PLL Numerator Register, offset: 0x61C */
  __IO uint32_t PLL1SS;                            /**< PLL Spread Spectrum Register, offset: 0x620 */
  __IO uint32_t PLL1LOCK;                          /**< PLL LOCK Configuration Register, offset: 0x624 */
       uint8_t RESERVED_16[480];
  __IO uint32_t RTCDIV;                            /**< Clock Dividers for the RTC Oscilator, offset: 0x808 */
       uint8_t RESERVED_17[244];
  __IO uint32_t AUD_CLK0;                          /**< AUD_CLK0 source to SAI0-3, offset: 0x900 */
  __IO uint32_t SAI3_0_CLK;                        /**< SAI3-0 Clock Source Selection, offset: 0x904 */
  __IO uint32_t TPM3_2CLK;                         /**< Multiplexer to select the audio clock connected to the TPM clock input, offset: 0x908 */
  __IO uint32_t MQS0CLK;                           /**< Multiplexer to select the audio clock connected to the MQS clock input, offset: 0x90C */
       uint8_t RESERVED_18[4];
  __IO uint32_t EMICFIL;                           /**< Multiplexer to select the eMICFIL clock source, offset: 0x914 */
} CGC_Type;

/* ----------------------------------------------------------------------------
   -- CGC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CGC_Register_Masks CGC Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define CGC_VERID_FEATURE_MASK                   (0xFFFFU)
#define CGC_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Specification Number */
#define CGC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << CGC_VERID_FEATURE_SHIFT)) & CGC_VERID_FEATURE_MASK)

#define CGC_VERID_MINOR_MASK                     (0xFF0000U)
#define CGC_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number */
#define CGC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << CGC_VERID_MINOR_SHIFT)) & CGC_VERID_MINOR_MASK)

#define CGC_VERID_MAJOR_MASK                     (0xFF000000U)
#define CGC_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number */
#define CGC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << CGC_VERID_MAJOR_SHIFT)) & CGC_VERID_MAJOR_MASK)
/*! @} */

/*! @name CM33CLK - Clock Selection and Dividers for the M33 Domain */
/*! @{ */

#define CGC_CM33CLK_DIVSLOW_MASK                 (0x3FU)
#define CGC_CM33CLK_DIVSLOW_SHIFT                (0U)
/*! DIVSLOW - Clock Division for Slow Clock */
#define CGC_CM33CLK_DIVSLOW(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_CM33CLK_DIVSLOW_SHIFT)) & CGC_CM33CLK_DIVSLOW_MASK)

#define CGC_CM33CLK_DIVBUS_MASK                  (0x1F80U)
#define CGC_CM33CLK_DIVBUS_SHIFT                 (7U)
/*! DIVBUS - Clock Division for Bus Clk */
#define CGC_CM33CLK_DIVBUS(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_CM33CLK_DIVBUS_SHIFT)) & CGC_CM33CLK_DIVBUS_MASK)

#define CGC_CM33CLK_DIVCORE_MASK                 (0x7E00000U)
#define CGC_CM33CLK_DIVCORE_SHIFT                (21U)
/*! DIVCORE - Clock Division for Core Clock */
#define CGC_CM33CLK_DIVCORE(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_CM33CLK_DIVCORE_SHIFT)) & CGC_CM33CLK_DIVCORE_MASK)

#define CGC_CM33CLK_SCSW_MASK                    (0x8000000U)
#define CGC_CM33CLK_SCSW_SHIFT                   (27U)
/*! SCSW - Clock switched to selected clock source */
#define CGC_CM33CLK_SCSW(x)                      (((uint32_t)(((uint32_t)(x)) << CGC_CM33CLK_SCSW_SHIFT)) & CGC_CM33CLK_SCSW_MASK)

#define CGC_CM33CLK_SCS_MASK                     (0x70000000U)
#define CGC_CM33CLK_SCS_SHIFT                    (28U)
/*! SCS - Clock Selection for M33 Domain */
#define CGC_CM33CLK_SCS(x)                       (((uint32_t)(((uint32_t)(x)) << CGC_CM33CLK_SCS_SHIFT)) & CGC_CM33CLK_SCS_MASK)

#define CGC_CM33CLK_CM33LOCKED_MASK              (0x80000000U)
#define CGC_CM33CLK_CM33LOCKED_SHIFT             (31U)
/*! CM33LOCKED - CM33 CLK Register Locked */
#define CGC_CM33CLK_CM33LOCKED(x)                (((uint32_t)(((uint32_t)(x)) << CGC_CM33CLK_CM33LOCKED_SHIFT)) & CGC_CM33CLK_CM33LOCKED_MASK)
/*! @} */

/*! @name FUSIONCLK - Clock Selection and Dividers for the Fusion DSP Domain */
/*! @{ */

#define CGC_FUSIONCLK_DIVSLOW_MASK               (0x3FU)
#define CGC_FUSIONCLK_DIVSLOW_SHIFT              (0U)
/*! DIVSLOW - Clock Division for Slow Clock */
#define CGC_FUSIONCLK_DIVSLOW(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_FUSIONCLK_DIVSLOW_SHIFT)) & CGC_FUSIONCLK_DIVSLOW_MASK)

#define CGC_FUSIONCLK_DIVBUS_MASK                (0x1F80U)
#define CGC_FUSIONCLK_DIVBUS_SHIFT               (7U)
/*! DIVBUS - Clock Division for Bus Clk */
#define CGC_FUSIONCLK_DIVBUS(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_FUSIONCLK_DIVBUS_SHIFT)) & CGC_FUSIONCLK_DIVBUS_MASK)

#define CGC_FUSIONCLK_DIVCORE_MASK               (0x7E00000U)
#define CGC_FUSIONCLK_DIVCORE_SHIFT              (21U)
/*! DIVCORE - Clock Division for Core Clock */
#define CGC_FUSIONCLK_DIVCORE(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_FUSIONCLK_DIVCORE_SHIFT)) & CGC_FUSIONCLK_DIVCORE_MASK)

#define CGC_FUSIONCLK_SCSW_MASK                  (0x8000000U)
#define CGC_FUSIONCLK_SCSW_SHIFT                 (27U)
/*! SCSW - Clock switched to selected clock source */
#define CGC_FUSIONCLK_SCSW(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_FUSIONCLK_SCSW_SHIFT)) & CGC_FUSIONCLK_SCSW_MASK)

#define CGC_FUSIONCLK_SCS_MASK                   (0x70000000U)
#define CGC_FUSIONCLK_SCS_SHIFT                  (28U)
/*! SCS - Clock Selection for DSP Domain */
#define CGC_FUSIONCLK_SCS(x)                     (((uint32_t)(((uint32_t)(x)) << CGC_FUSIONCLK_SCS_SHIFT)) & CGC_FUSIONCLK_SCS_MASK)

#define CGC_FUSIONCLK_FUSIONLOCKED_MASK          (0x80000000U)
#define CGC_FUSIONCLK_FUSIONLOCKED_SHIFT         (31U)
/*! FUSIONLOCKED - FUSION CLK Register Locked */
#define CGC_FUSIONCLK_FUSIONLOCKED(x)            (((uint32_t)(((uint32_t)(x)) << CGC_FUSIONCLK_FUSIONLOCKED_SHIFT)) & CGC_FUSIONCLK_FUSIONLOCKED_MASK)
/*! @} */

/*! @name CLKOUTCFG - Clockout selection for Real Time Domain */
/*! @{ */

#define CGC_CLKOUTCFG_CLKOUT_DIV_MASK            (0x7E0000U)
#define CGC_CLKOUTCFG_CLKOUT_DIV_SHIFT           (17U)
/*! CLKOUT_DIV - Select the clock division for the CLKOUT pin */
#define CGC_CLKOUTCFG_CLKOUT_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CGC_CLKOUTCFG_CLKOUT_DIV_SHIFT)) & CGC_CLKOUTCFG_CLKOUT_DIV_MASK)

#define CGC_CLKOUTCFG_CLKOUT_SEL_MASK            (0xF800000U)
#define CGC_CLKOUTCFG_CLKOUT_SEL_SHIFT           (23U)
/*! CLKOUT_SEL - Select the clock source redirected to CLKOUT pin */
#define CGC_CLKOUTCFG_CLKOUT_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CGC_CLKOUTCFG_CLKOUT_SEL_SHIFT)) & CGC_CLKOUTCFG_CLKOUT_SEL_MASK)

#define CGC_CLKOUTCFG_CLKOUT_EN_MASK             (0x10000000U)
#define CGC_CLKOUTCFG_CLKOUT_EN_SHIFT            (28U)
/*! CLKOUT_EN - Clockout Enable */
#define CGC_CLKOUTCFG_CLKOUT_EN(x)               (((uint32_t)(((uint32_t)(x)) << CGC_CLKOUTCFG_CLKOUT_EN_SHIFT)) & CGC_CLKOUTCFG_CLKOUT_EN_MASK)
/*! @} */

/*! @name CLKDIVRST - Clk Dividers Reset */
/*! @{ */

#define CGC_CLKDIVRST_FUSION_OUT_OF_PHASE_MASK   (0x1U)
#define CGC_CLKDIVRST_FUSION_OUT_OF_PHASE_SHIFT  (0U)
/*! FUSION_OUT_OF_PHASE - Fusion system clocks dividers reset */
#define CGC_CLKDIVRST_FUSION_OUT_OF_PHASE(x)     (((uint32_t)(((uint32_t)(x)) << CGC_CLKDIVRST_FUSION_OUT_OF_PHASE_SHIFT)) & CGC_CLKDIVRST_FUSION_OUT_OF_PHASE_MASK)

#define CGC_CLKDIVRST_FUSION_RST_DIVIDERS_EN_MASK (0x2U)
#define CGC_CLKDIVRST_FUSION_RST_DIVIDERS_EN_SHIFT (1U)
/*! FUSION_RST_DIVIDERS_EN - Fusion system clocks dividers out of phase interrupt */
#define CGC_CLKDIVRST_FUSION_RST_DIVIDERS_EN(x)  (((uint32_t)(((uint32_t)(x)) << CGC_CLKDIVRST_FUSION_RST_DIVIDERS_EN_SHIFT)) & CGC_CLKDIVRST_FUSION_RST_DIVIDERS_EN_MASK)

#define CGC_CLKDIVRST_FUSION_INTERRUPT_EN_MASK   (0x4U)
#define CGC_CLKDIVRST_FUSION_INTERRUPT_EN_SHIFT  (2U)
/*! FUSION_INTERRUPT_EN - Selection between interrupt generation or clock dividers reset when fusion system clocks are out of phase */
#define CGC_CLKDIVRST_FUSION_INTERRUPT_EN(x)     (((uint32_t)(((uint32_t)(x)) << CGC_CLKDIVRST_FUSION_INTERRUPT_EN_SHIFT)) & CGC_CLKDIVRST_FUSION_INTERRUPT_EN_MASK)

#define CGC_CLKDIVRST_FUSION_RESET_EN_MASK       (0x8U)
#define CGC_CLKDIVRST_FUSION_RESET_EN_SHIFT      (3U)
/*! FUSION_RESET_EN - Enable of reset generation when fusion system clocks are out of phase */
#define CGC_CLKDIVRST_FUSION_RESET_EN(x)         (((uint32_t)(((uint32_t)(x)) << CGC_CLKDIVRST_FUSION_RESET_EN_SHIFT)) & CGC_CLKDIVRST_FUSION_RESET_EN_MASK)

#define CGC_CLKDIVRST_CM33_OUT_OF_PHASE_MASK     (0x10000U)
#define CGC_CLKDIVRST_CM33_OUT_OF_PHASE_SHIFT    (16U)
/*! CM33_OUT_OF_PHASE - CM33 system clocks dividers reset */
#define CGC_CLKDIVRST_CM33_OUT_OF_PHASE(x)       (((uint32_t)(((uint32_t)(x)) << CGC_CLKDIVRST_CM33_OUT_OF_PHASE_SHIFT)) & CGC_CLKDIVRST_CM33_OUT_OF_PHASE_MASK)

#define CGC_CLKDIVRST_CM33_RST_DIVIDERS_EN_MASK  (0x20000U)
#define CGC_CLKDIVRST_CM33_RST_DIVIDERS_EN_SHIFT (17U)
/*! CM33_RST_DIVIDERS_EN - CM33 system clocks dividers out of phase interrupt */
#define CGC_CLKDIVRST_CM33_RST_DIVIDERS_EN(x)    (((uint32_t)(((uint32_t)(x)) << CGC_CLKDIVRST_CM33_RST_DIVIDERS_EN_SHIFT)) & CGC_CLKDIVRST_CM33_RST_DIVIDERS_EN_MASK)

#define CGC_CLKDIVRST_CM33_INTERRUPT_EN_MASK     (0x40000U)
#define CGC_CLKDIVRST_CM33_INTERRUPT_EN_SHIFT    (18U)
/*! CM33_INTERRUPT_EN - Selection between interrupt generation or clock dividers reset when cm33 system clocks are out of phase */
#define CGC_CLKDIVRST_CM33_INTERRUPT_EN(x)       (((uint32_t)(((uint32_t)(x)) << CGC_CLKDIVRST_CM33_INTERRUPT_EN_SHIFT)) & CGC_CLKDIVRST_CM33_INTERRUPT_EN_MASK)

#define CGC_CLKDIVRST_CM33_RESET_EN_MASK         (0x80000U)
#define CGC_CLKDIVRST_CM33_RESET_EN_SHIFT        (19U)
/*! CM33_RESET_EN - Enable of reset generation when CM33 system clocks are out of phase */
#define CGC_CLKDIVRST_CM33_RESET_EN(x)           (((uint32_t)(((uint32_t)(x)) << CGC_CLKDIVRST_CM33_RESET_EN_SHIFT)) & CGC_CLKDIVRST_CM33_RESET_EN_MASK)
/*! @} */

/*! @name SOSCCSR - System OSC Control Status Register */
/*! @{ */

#define CGC_SOSCCSR_SOSCEN_MASK                  (0x1U)
#define CGC_SOSCCSR_SOSCEN_SHIFT                 (0U)
/*! SOSCEN - System OSC Enable */
#define CGC_SOSCCSR_SOSCEN(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_SOSCCSR_SOSCEN_SHIFT)) & CGC_SOSCCSR_SOSCEN_MASK)

#define CGC_SOSCCSR_SOSCDSEN_MASK                (0x2U)
#define CGC_SOSCCSR_SOSCDSEN_SHIFT               (1U)
/*! SOSCDSEN - System OSC Enable in Deep Sleep */
#define CGC_SOSCCSR_SOSCDSEN(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_SOSCCSR_SOSCDSEN_SHIFT)) & CGC_SOSCCSR_SOSCDSEN_MASK)

#define CGC_SOSCCSR_SOSCPDEN_MASK                (0x4U)
#define CGC_SOSCCSR_SOSCPDEN_SHIFT               (2U)
/*! SOSCPDEN - System OSC Enable in Power Down */
#define CGC_SOSCCSR_SOSCPDEN(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_SOSCCSR_SOSCPDEN_SHIFT)) & CGC_SOSCCSR_SOSCPDEN_MASK)

#define CGC_SOSCCSR_SOSCCM_MASK                  (0x10000U)
#define CGC_SOSCCSR_SOSCCM_SHIFT                 (16U)
/*! SOSCCM - System OSC Clock Monitor */
#define CGC_SOSCCSR_SOSCCM(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_SOSCCSR_SOSCCM_SHIFT)) & CGC_SOSCCSR_SOSCCM_MASK)

#define CGC_SOSCCSR_SOSCCMRE_MASK                (0x20000U)
#define CGC_SOSCCSR_SOSCCMRE_SHIFT               (17U)
/*! SOSCCMRE - System OSC Clock Monitor Reset Enable */
#define CGC_SOSCCSR_SOSCCMRE(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_SOSCCSR_SOSCCMRE_SHIFT)) & CGC_SOSCCSR_SOSCCMRE_MASK)

#define CGC_SOSCCSR_LK_MASK                      (0x800000U)
#define CGC_SOSCCSR_LK_SHIFT                     (23U)
/*! LK - Lock Register */
#define CGC_SOSCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << CGC_SOSCCSR_LK_SHIFT)) & CGC_SOSCCSR_LK_MASK)

#define CGC_SOSCCSR_SOSCVLD_MASK                 (0x1000000U)
#define CGC_SOSCCSR_SOSCVLD_SHIFT                (24U)
/*! SOSCVLD - System OSC Valid */
#define CGC_SOSCCSR_SOSCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_SOSCCSR_SOSCVLD_SHIFT)) & CGC_SOSCCSR_SOSCVLD_MASK)

#define CGC_SOSCCSR_SOSCSEL_MASK                 (0x2000000U)
#define CGC_SOSCCSR_SOSCSEL_SHIFT                (25U)
/*! SOSCSEL - System OSC Selected */
#define CGC_SOSCCSR_SOSCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_SOSCCSR_SOSCSEL_SHIFT)) & CGC_SOSCCSR_SOSCSEL_MASK)

#define CGC_SOSCCSR_SOSCERR_MASK                 (0x4000000U)
#define CGC_SOSCCSR_SOSCERR_SHIFT                (26U)
/*! SOSCERR - System OSC Clock Error */
#define CGC_SOSCCSR_SOSCERR(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_SOSCCSR_SOSCERR_SHIFT)) & CGC_SOSCCSR_SOSCERR_MASK)
/*! @} */

/*! @name SOSCDIV - Clock Dividers for the SYS OSC Oscilator */
/*! @{ */

#define CGC_SOSCDIV_DIV1_MASK                    (0x3FU)
#define CGC_SOSCDIV_DIV1_SHIFT                   (0U)
/*! DIV1 - Clock Division for Slow Clock */
#define CGC_SOSCDIV_DIV1(x)                      (((uint32_t)(((uint32_t)(x)) << CGC_SOSCDIV_DIV1_SHIFT)) & CGC_SOSCDIV_DIV1_MASK)

#define CGC_SOSCDIV_DIV1LOCKED_MASK              (0x40U)
#define CGC_SOSCDIV_DIV1LOCKED_SHIFT             (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked */
#define CGC_SOSCDIV_DIV1LOCKED(x)                (((uint32_t)(((uint32_t)(x)) << CGC_SOSCDIV_DIV1LOCKED_SHIFT)) & CGC_SOSCDIV_DIV1LOCKED_MASK)

#define CGC_SOSCDIV_DIV1HALT_MASK                (0x80U)
#define CGC_SOSCDIV_DIV1HALT_SHIFT               (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_SOSCDIV_DIV1HALT(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_SOSCDIV_DIV1HALT_SHIFT)) & CGC_SOSCDIV_DIV1HALT_MASK)

#define CGC_SOSCDIV_DIV2_MASK                    (0x3F00U)
#define CGC_SOSCDIV_DIV2_SHIFT                   (8U)
/*! DIV2 - Clock Division for Bus Clock */
#define CGC_SOSCDIV_DIV2(x)                      (((uint32_t)(((uint32_t)(x)) << CGC_SOSCDIV_DIV2_SHIFT)) & CGC_SOSCDIV_DIV2_MASK)

#define CGC_SOSCDIV_DIV2LOCKED_MASK              (0x4000U)
#define CGC_SOSCDIV_DIV2LOCKED_SHIFT             (14U)
/*! DIV2LOCKED - The value of clock division was changed and access to DIV2 is locked. */
#define CGC_SOSCDIV_DIV2LOCKED(x)                (((uint32_t)(((uint32_t)(x)) << CGC_SOSCDIV_DIV2LOCKED_SHIFT)) & CGC_SOSCDIV_DIV2LOCKED_MASK)

#define CGC_SOSCDIV_DIV2HALT_MASK                (0x8000U)
#define CGC_SOSCDIV_DIV2HALT_SHIFT               (15U)
/*! DIV2HALT - Divider 1 Halted */
#define CGC_SOSCDIV_DIV2HALT(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_SOSCDIV_DIV2HALT_SHIFT)) & CGC_SOSCDIV_DIV2HALT_MASK)

#define CGC_SOSCDIV_DIV3_MASK                    (0x3F0000U)
#define CGC_SOSCDIV_DIV3_SHIFT                   (16U)
/*! DIV3 - Clock Division for Platform Clock */
#define CGC_SOSCDIV_DIV3(x)                      (((uint32_t)(((uint32_t)(x)) << CGC_SOSCDIV_DIV3_SHIFT)) & CGC_SOSCDIV_DIV3_MASK)

#define CGC_SOSCDIV_DIV3LOCKED_MASK              (0x400000U)
#define CGC_SOSCDIV_DIV3LOCKED_SHIFT             (22U)
/*! DIV3LOCKED - The value of clock division was changed and access to DIV3 is locked. */
#define CGC_SOSCDIV_DIV3LOCKED(x)                (((uint32_t)(((uint32_t)(x)) << CGC_SOSCDIV_DIV3LOCKED_SHIFT)) & CGC_SOSCDIV_DIV3LOCKED_MASK)

#define CGC_SOSCDIV_DIV3HALT_MASK                (0x800000U)
#define CGC_SOSCDIV_DIV3HALT_SHIFT               (23U)
/*! DIV3HALT - Divider 1 Halted */
#define CGC_SOSCDIV_DIV3HALT(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_SOSCDIV_DIV3HALT_SHIFT)) & CGC_SOSCDIV_DIV3HALT_MASK)
/*! @} */

/*! @name SOSCCFG - System Oscillator Configuration Register */
/*! @{ */

#define CGC_SOSCCFG_SYSOSC_BYPASS_EN_MASK        (0x4U)
#define CGC_SOSCCFG_SYSOSC_BYPASS_EN_SHIFT       (2U)
/*! SYSOSC_BYPASS_EN - System Oscillator Bypass Enable */
#define CGC_SOSCCFG_SYSOSC_BYPASS_EN(x)          (((uint32_t)(((uint32_t)(x)) << CGC_SOSCCFG_SYSOSC_BYPASS_EN_SHIFT)) & CGC_SOSCCFG_SYSOSC_BYPASS_EN_MASK)

#define CGC_SOSCCFG_HGO_MASK                     (0x8U)
#define CGC_SOSCCFG_HGO_SHIFT                    (3U)
/*! HGO - High Gain Oscillator Select */
#define CGC_SOSCCFG_HGO(x)                       (((uint32_t)(((uint32_t)(x)) << CGC_SOSCCFG_HGO_SHIFT)) & CGC_SOSCCFG_HGO_MASK)
/*! @} */

/*! @name FROCSR - FRO Control Status Register */
/*! @{ */

#define CGC_FROCSR_FRODSEN_MASK                  (0x2U)
#define CGC_FROCSR_FRODSEN_SHIFT                 (1U)
/*! FRODSEN - FRO Enable in Sleep Mode */
#define CGC_FROCSR_FRODSEN(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_FROCSR_FRODSEN_SHIFT)) & CGC_FROCSR_FRODSEN_MASK)

#define CGC_FROCSR_LK_MASK                       (0x800000U)
#define CGC_FROCSR_LK_SHIFT                      (23U)
/*! LK - Lock Register */
#define CGC_FROCSR_LK(x)                         (((uint32_t)(((uint32_t)(x)) << CGC_FROCSR_LK_SHIFT)) & CGC_FROCSR_LK_MASK)

#define CGC_FROCSR_FROVLD_MASK                   (0x1000000U)
#define CGC_FROCSR_FROVLD_SHIFT                  (24U)
/*! FROVLD - FRO Valid */
#define CGC_FROCSR_FROVLD(x)                     (((uint32_t)(((uint32_t)(x)) << CGC_FROCSR_FROVLD_SHIFT)) & CGC_FROCSR_FROVLD_MASK)

#define CGC_FROCSR_FROSEL_MASK                   (0x2000000U)
#define CGC_FROCSR_FROSEL_SHIFT                  (25U)
/*! FROSEL - FRO Selected */
#define CGC_FROCSR_FROSEL(x)                     (((uint32_t)(((uint32_t)(x)) << CGC_FROCSR_FROSEL_SHIFT)) & CGC_FROCSR_FROSEL_MASK)
/*! @} */

/*! @name FROCTRL - FRO Control Register */
/*! @{ */

#define CGC_FROCTRL_EXP_COUNT_MASK               (0xFFFFU)
#define CGC_FROCTRL_EXP_COUNT_SHIFT              (0U)
/*! EXP_COUNT - Expected Count */
#define CGC_FROCTRL_EXP_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_FROCTRL_EXP_COUNT_SHIFT)) & CGC_FROCTRL_EXP_COUNT_MASK)

#define CGC_FROCTRL_THRESH_RANGE_UP_MASK         (0x1F0000U)
#define CGC_FROCTRL_THRESH_RANGE_UP_SHIFT        (16U)
/*! THRESH_RANGE_UP - Threshold Range Upper Limit */
#define CGC_FROCTRL_THRESH_RANGE_UP(x)           (((uint32_t)(((uint32_t)(x)) << CGC_FROCTRL_THRESH_RANGE_UP_SHIFT)) & CGC_FROCTRL_THRESH_RANGE_UP_MASK)

#define CGC_FROCTRL_THRESH_RANGE_LOW_MASK        (0x3E00000U)
#define CGC_FROCTRL_THRESH_RANGE_LOW_SHIFT       (21U)
/*! THRESH_RANGE_LOW - Threshold Range Lower Limit */
#define CGC_FROCTRL_THRESH_RANGE_LOW(x)          (((uint32_t)(((uint32_t)(x)) << CGC_FROCTRL_THRESH_RANGE_LOW_SHIFT)) & CGC_FROCTRL_THRESH_RANGE_LOW_MASK)

#define CGC_FROCTRL_ENA_TUNE_MASK                (0x80000000U)
#define CGC_FROCTRL_ENA_TUNE_SHIFT               (31U)
/*! ENA_TUNE - Enable Tuning */
#define CGC_FROCTRL_ENA_TUNE(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_FROCTRL_ENA_TUNE_SHIFT)) & CGC_FROCTRL_ENA_TUNE_MASK)
/*! @} */

/*! @name FROCAPVAL - FRO Cap Val Register */
/*! @{ */

#define CGC_FROCAPVAL_CAPVAL_MASK                (0xFFFFU)
#define CGC_FROCAPVAL_CAPVAL_SHIFT               (0U)
/*! CAPVAL - Captured Value */
#define CGC_FROCAPVAL_CAPVAL(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_FROCAPVAL_CAPVAL_SHIFT)) & CGC_FROCAPVAL_CAPVAL_MASK)

#define CGC_FROCAPVAL_DATA_VALID_MASK            (0x80000000U)
#define CGC_FROCAPVAL_DATA_VALID_SHIFT           (31U)
/*! DATA_VALID - Data Valid */
#define CGC_FROCAPVAL_DATA_VALID(x)              (((uint32_t)(((uint32_t)(x)) << CGC_FROCAPVAL_DATA_VALID_SHIFT)) & CGC_FROCAPVAL_DATA_VALID_MASK)
/*! @} */

/*! @name FRORDTRIM - RD Trim Values for FRO */
/*! @{ */

#define CGC_FRORDTRIM_TRIM_MASK                  (0x7FFU)
#define CGC_FRORDTRIM_TRIM_SHIFT                 (0U)
/*! TRIM - Trim */
#define CGC_FRORDTRIM_TRIM(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_FRORDTRIM_TRIM_SHIFT)) & CGC_FRORDTRIM_TRIM_MASK)
/*! @} */

/*! @name FROSCTRIM - SC TRIM value for FRO */
/*! @{ */

#define CGC_FROSCTRIM_TRIM_MASK                  (0x3FU)
#define CGC_FROSCTRIM_TRIM_SHIFT                 (0U)
/*! TRIM - Switched Capacitor TRIM Value for FRO */
#define CGC_FROSCTRIM_TRIM(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_FROSCTRIM_TRIM_SHIFT)) & CGC_FROSCTRIM_TRIM_MASK)
/*! @} */

/*! @name FRODIV - Clock Dividers for the FFRO 192 MHz Oscilator */
/*! @{ */

#define CGC_FRODIV_DIV1_MASK                     (0x3FU)
#define CGC_FRODIV_DIV1_SHIFT                    (0U)
/*! DIV1 - Clock Division for Slow Clock */
#define CGC_FRODIV_DIV1(x)                       (((uint32_t)(((uint32_t)(x)) << CGC_FRODIV_DIV1_SHIFT)) & CGC_FRODIV_DIV1_MASK)

#define CGC_FRODIV_DIV1LOCKED_MASK               (0x40U)
#define CGC_FRODIV_DIV1LOCKED_SHIFT              (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked. */
#define CGC_FRODIV_DIV1LOCKED(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_FRODIV_DIV1LOCKED_SHIFT)) & CGC_FRODIV_DIV1LOCKED_MASK)

#define CGC_FRODIV_DIV1HALT_MASK                 (0x80U)
#define CGC_FRODIV_DIV1HALT_SHIFT                (7U)
/*! DIV1HALT - Divider 1 Halted. */
#define CGC_FRODIV_DIV1HALT(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_FRODIV_DIV1HALT_SHIFT)) & CGC_FRODIV_DIV1HALT_MASK)

#define CGC_FRODIV_DIV2_MASK                     (0x3F00U)
#define CGC_FRODIV_DIV2_SHIFT                    (8U)
/*! DIV2 - Clock Division for Bus Clock */
#define CGC_FRODIV_DIV2(x)                       (((uint32_t)(((uint32_t)(x)) << CGC_FRODIV_DIV2_SHIFT)) & CGC_FRODIV_DIV2_MASK)

#define CGC_FRODIV_DIV2LOCKED_MASK               (0x4000U)
#define CGC_FRODIV_DIV2LOCKED_SHIFT              (14U)
/*! DIV2LOCKED - The value of clock division was changed and access to DIV2 is locked. */
#define CGC_FRODIV_DIV2LOCKED(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_FRODIV_DIV2LOCKED_SHIFT)) & CGC_FRODIV_DIV2LOCKED_MASK)

#define CGC_FRODIV_DIV2HALT_MASK                 (0x8000U)
#define CGC_FRODIV_DIV2HALT_SHIFT                (15U)
/*! DIV2HALT - Divider 2 Halted. */
#define CGC_FRODIV_DIV2HALT(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_FRODIV_DIV2HALT_SHIFT)) & CGC_FRODIV_DIV2HALT_MASK)

#define CGC_FRODIV_DIV3_MASK                     (0x3F0000U)
#define CGC_FRODIV_DIV3_SHIFT                    (16U)
/*! DIV3 - Clock Division for Platform Clock. */
#define CGC_FRODIV_DIV3(x)                       (((uint32_t)(((uint32_t)(x)) << CGC_FRODIV_DIV3_SHIFT)) & CGC_FRODIV_DIV3_MASK)

#define CGC_FRODIV_DIV3LOCKED_MASK               (0x400000U)
#define CGC_FRODIV_DIV3LOCKED_SHIFT              (22U)
/*! DIV3LOCKED - The value of clock division was changed and access to DIV3 is locked. */
#define CGC_FRODIV_DIV3LOCKED(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_FRODIV_DIV3LOCKED_SHIFT)) & CGC_FRODIV_DIV3LOCKED_MASK)

#define CGC_FRODIV_DIV3HALT_MASK                 (0x800000U)
#define CGC_FRODIV_DIV3HALT_SHIFT                (23U)
/*! DIV3HALT - Divider 3 Halted */
#define CGC_FRODIV_DIV3HALT(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_FRODIV_DIV3HALT_SHIFT)) & CGC_FRODIV_DIV3HALT_MASK)
/*! @} */

/*! @name FRORDTRIM_FUSE - Trim values loaded from fuses */
/*! @{ */

#define CGC_FRORDTRIM_FUSE_RD_TRIM_FROM_FUSES_MASK (0x7FFU)
#define CGC_FRORDTRIM_FUSE_RD_TRIM_FROM_FUSES_SHIFT (0U)
/*! RD_TRIM_FROM_FUSES - This register captures the value of FRO trim that were defined by fuses. */
#define CGC_FRORDTRIM_FUSE_RD_TRIM_FROM_FUSES(x) (((uint32_t)(((uint32_t)(x)) << CGC_FRORDTRIM_FUSE_RD_TRIM_FROM_FUSES_SHIFT)) & CGC_FRORDTRIM_FUSE_RD_TRIM_FROM_FUSES_MASK)
/*! @} */

/*! @name FROSCTRIM_FUSE - SC Trim Values loaded from fuses */
/*! @{ */

#define CGC_FROSCTRIM_FUSE_SC_TRIM_FROM_FUSES_MASK (0x3FU)
#define CGC_FROSCTRIM_FUSE_SC_TRIM_FROM_FUSES_SHIFT (0U)
/*! SC_TRIM_FROM_FUSES - SC TRIM Values loaded from fuses */
#define CGC_FROSCTRIM_FUSE_SC_TRIM_FROM_FUSES(x) (((uint32_t)(((uint32_t)(x)) << CGC_FROSCTRIM_FUSE_SC_TRIM_FROM_FUSES_SHIFT)) & CGC_FROSCTRIM_FUSE_SC_TRIM_FROM_FUSES_MASK)
/*! @} */

/*! @name LPOSCCSR - Low Power OSC Control Status Register */
/*! @{ */

#define CGC_LPOSCCSR_LPOSCEN_MASK                (0x1U)
#define CGC_LPOSCCSR_LPOSCEN_SHIFT               (0U)
/*! LPOSCEN - Low Power OSC Enable */
#define CGC_LPOSCCSR_LPOSCEN(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_LPOSCCSR_LPOSCEN_SHIFT)) & CGC_LPOSCCSR_LPOSCEN_MASK)

#define CGC_LPOSCCSR_LPOSCDSEN_MASK              (0x2U)
#define CGC_LPOSCCSR_LPOSCDSEN_SHIFT             (1U)
/*! LPOSCDSEN - Low Power OSC Enable in Deep Sleep */
#define CGC_LPOSCCSR_LPOSCDSEN(x)                (((uint32_t)(((uint32_t)(x)) << CGC_LPOSCCSR_LPOSCDSEN_SHIFT)) & CGC_LPOSCCSR_LPOSCDSEN_MASK)

#define CGC_LPOSCCSR_LPOSCPDEN_MASK              (0x4U)
#define CGC_LPOSCCSR_LPOSCPDEN_SHIFT             (2U)
/*! LPOSCPDEN - Low Power Oscilator Enable in Power Down */
#define CGC_LPOSCCSR_LPOSCPDEN(x)                (((uint32_t)(((uint32_t)(x)) << CGC_LPOSCCSR_LPOSCPDEN_SHIFT)) & CGC_LPOSCCSR_LPOSCPDEN_MASK)

#define CGC_LPOSCCSR_LK_MASK                     (0x800000U)
#define CGC_LPOSCCSR_LK_SHIFT                    (23U)
/*! LK - Lock Register */
#define CGC_LPOSCCSR_LK(x)                       (((uint32_t)(((uint32_t)(x)) << CGC_LPOSCCSR_LK_SHIFT)) & CGC_LPOSCCSR_LK_MASK)

#define CGC_LPOSCCSR_LPOSCVLD_MASK               (0x1000000U)
#define CGC_LPOSCCSR_LPOSCVLD_SHIFT              (24U)
/*! LPOSCVLD - Low Power OSC Valid */
#define CGC_LPOSCCSR_LPOSCVLD(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_LPOSCCSR_LPOSCVLD_SHIFT)) & CGC_LPOSCCSR_LPOSCVLD_MASK)
/*! @} */

/*! @name LPOSCCTRL - LPO Oscillator Control Register */
/*! @{ */

#define CGC_LPOSCCTRL_BIASCURRENT_MASK           (0xFFU)
#define CGC_LPOSCCTRL_BIASCURRENT_SHIFT          (0U)
/*! BIASCURRENT - BIASCURRENT */
#define CGC_LPOSCCTRL_BIASCURRENT(x)             (((uint32_t)(((uint32_t)(x)) << CGC_LPOSCCTRL_BIASCURRENT_SHIFT)) & CGC_LPOSCCTRL_BIASCURRENT_MASK)

#define CGC_LPOSCCTRL_PTAT_MASK                  (0x3F00U)
#define CGC_LPOSCCTRL_PTAT_SHIFT                 (8U)
/*! PTAT - PTAT */
#define CGC_LPOSCCTRL_PTAT(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_LPOSCCTRL_PTAT_SHIFT)) & CGC_LPOSCCTRL_PTAT_MASK)

#define CGC_LPOSCCTRL_ZTC_MASK                   (0x3FC000U)
#define CGC_LPOSCCTRL_ZTC_SHIFT                  (14U)
/*! ZTC - ZTC */
#define CGC_LPOSCCTRL_ZTC(x)                     (((uint32_t)(((uint32_t)(x)) << CGC_LPOSCCTRL_ZTC_SHIFT)) & CGC_LPOSCCTRL_ZTC_MASK)

#define CGC_LPOSCCTRL_DIS_ZTC_MASK               (0x400000U)
#define CGC_LPOSCCTRL_DIS_ZTC_SHIFT              (22U)
/*! DIS_ZTC - Disable ZTC */
#define CGC_LPOSCCTRL_DIS_ZTC(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_LPOSCCTRL_DIS_ZTC_SHIFT)) & CGC_LPOSCCTRL_DIS_ZTC_MASK)
/*! @} */

/*! @name ROSCCTRL - ROSCCSR */
/*! @{ */

#define CGC_ROSCCTRL_ROSCCM_MASK                 (0x10000U)
#define CGC_ROSCCTRL_ROSCCM_SHIFT                (16U)
/*! ROSCCM - RTC OSC Clock Monitor */
#define CGC_ROSCCTRL_ROSCCM(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_ROSCCTRL_ROSCCM_SHIFT)) & CGC_ROSCCTRL_ROSCCM_MASK)

#define CGC_ROSCCTRL_ROSCCMRE_MASK               (0x20000U)
#define CGC_ROSCCTRL_ROSCCMRE_SHIFT              (17U)
/*! ROSCCMRE - RTC OSC Clock Monitor Reset Enable */
#define CGC_ROSCCTRL_ROSCCMRE(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_ROSCCTRL_ROSCCMRE_SHIFT)) & CGC_ROSCCTRL_ROSCCMRE_MASK)

#define CGC_ROSCCTRL_LK_MASK                     (0x800000U)
#define CGC_ROSCCTRL_LK_SHIFT                    (23U)
/*! LK - Lock Register */
#define CGC_ROSCCTRL_LK(x)                       (((uint32_t)(((uint32_t)(x)) << CGC_ROSCCTRL_LK_SHIFT)) & CGC_ROSCCTRL_LK_MASK)

#define CGC_ROSCCTRL_ROSCVLD_MASK                (0x1000000U)
#define CGC_ROSCCTRL_ROSCVLD_SHIFT               (24U)
/*! ROSCVLD - RTC OSC Valid */
#define CGC_ROSCCTRL_ROSCVLD(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_ROSCCTRL_ROSCVLD_SHIFT)) & CGC_ROSCCTRL_ROSCVLD_MASK)

#define CGC_ROSCCTRL_ROSCSEL_MASK                (0x2000000U)
#define CGC_ROSCCTRL_ROSCSEL_SHIFT               (25U)
/*! ROSCSEL - RTC OSC Selected */
#define CGC_ROSCCTRL_ROSCSEL(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_ROSCCTRL_ROSCSEL_SHIFT)) & CGC_ROSCCTRL_ROSCSEL_MASK)

#define CGC_ROSCCTRL_ROSCERR_MASK                (0x4000000U)
#define CGC_ROSCCTRL_ROSCERR_SHIFT               (26U)
/*! ROSCERR - RTC OSC Clock Error */
#define CGC_ROSCCTRL_ROSCERR(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_ROSCCTRL_ROSCERR_SHIFT)) & CGC_ROSCCTRL_ROSCERR_MASK)
/*! @} */

/*! @name PLL0CSR - System OSC Control Status Register */
/*! @{ */

#define CGC_PLL0CSR_PLL0EN_MASK                  (0x1U)
#define CGC_PLL0CSR_PLL0EN_SHIFT                 (0U)
/*! PLL0EN - PLL0 Enable */
#define CGC_PLL0CSR_PLL0EN(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_PLL0CSR_PLL0EN_SHIFT)) & CGC_PLL0CSR_PLL0EN_MASK)

#define CGC_PLL0CSR_PLL0DSEN_MASK                (0x2U)
#define CGC_PLL0CSR_PLL0DSEN_SHIFT               (1U)
/*! PLL0DSEN - PLL0 Enable in Deep Sleep */
#define CGC_PLL0CSR_PLL0DSEN(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_PLL0CSR_PLL0DSEN_SHIFT)) & CGC_PLL0CSR_PLL0DSEN_MASK)

#define CGC_PLL0CSR_LK_MASK                      (0x800000U)
#define CGC_PLL0CSR_LK_SHIFT                     (23U)
/*! LK - Lock Register */
#define CGC_PLL0CSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << CGC_PLL0CSR_LK_SHIFT)) & CGC_PLL0CSR_LK_MASK)

#define CGC_PLL0CSR_PLLVLD_MASK                  (0x1000000U)
#define CGC_PLL0CSR_PLLVLD_SHIFT                 (24U)
/*! PLLVLD - PLL0 Valid */
#define CGC_PLL0CSR_PLLVLD(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_PLL0CSR_PLLVLD_SHIFT)) & CGC_PLL0CSR_PLLVLD_MASK)

#define CGC_PLL0CSR_PLLSEL_MASK                  (0x2000000U)
#define CGC_PLL0CSR_PLLSEL_SHIFT                 (25U)
/*! PLLSEL - PLL0 Selected */
#define CGC_PLL0CSR_PLLSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_PLL0CSR_PLLSEL_SHIFT)) & CGC_PLL0CSR_PLLSEL_MASK)
/*! @} */

/*! @name PLL0DIV_VCO - Clock Dividers for the fractional PLL0 */
/*! @{ */

#define CGC_PLL0DIV_VCO_DIV1_MASK                (0x3FU)
#define CGC_PLL0DIV_VCO_DIV1_SHIFT               (0U)
/*! DIV1 - Clock Division for PLL0 VCO Clock */
#define CGC_PLL0DIV_VCO_DIV1(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_PLL0DIV_VCO_DIV1_SHIFT)) & CGC_PLL0DIV_VCO_DIV1_MASK)

#define CGC_PLL0DIV_VCO_DIV1LOCKED_MASK          (0x40U)
#define CGC_PLL0DIV_VCO_DIV1LOCKED_SHIFT         (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked */
#define CGC_PLL0DIV_VCO_DIV1LOCKED(x)            (((uint32_t)(((uint32_t)(x)) << CGC_PLL0DIV_VCO_DIV1LOCKED_SHIFT)) & CGC_PLL0DIV_VCO_DIV1LOCKED_MASK)

#define CGC_PLL0DIV_VCO_DIV1HALT_MASK            (0x80U)
#define CGC_PLL0DIV_VCO_DIV1HALT_SHIFT           (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_PLL0DIV_VCO_DIV1HALT(x)              (((uint32_t)(((uint32_t)(x)) << CGC_PLL0DIV_VCO_DIV1HALT_SHIFT)) & CGC_PLL0DIV_VCO_DIV1HALT_MASK)
/*! @} */

/*! @name PLL0DIV_PFD_0 - Clock Dividers for the fractional PLL0 */
/*! @{ */

#define CGC_PLL0DIV_PFD_0_DIV1_MASK              (0x3FU)
#define CGC_PLL0DIV_PFD_0_DIV1_SHIFT             (0U)
/*! DIV1 - Clock Division for PLL0 PFD1 Clock */
#define CGC_PLL0DIV_PFD_0_DIV1(x)                (((uint32_t)(((uint32_t)(x)) << CGC_PLL0DIV_PFD_0_DIV1_SHIFT)) & CGC_PLL0DIV_PFD_0_DIV1_MASK)

#define CGC_PLL0DIV_PFD_0_DIV1LOCKED_MASK        (0x40U)
#define CGC_PLL0DIV_PFD_0_DIV1LOCKED_SHIFT       (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked */
#define CGC_PLL0DIV_PFD_0_DIV1LOCKED(x)          (((uint32_t)(((uint32_t)(x)) << CGC_PLL0DIV_PFD_0_DIV1LOCKED_SHIFT)) & CGC_PLL0DIV_PFD_0_DIV1LOCKED_MASK)

#define CGC_PLL0DIV_PFD_0_DIV1HALT_MASK          (0x80U)
#define CGC_PLL0DIV_PFD_0_DIV1HALT_SHIFT         (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_PLL0DIV_PFD_0_DIV1HALT(x)            (((uint32_t)(((uint32_t)(x)) << CGC_PLL0DIV_PFD_0_DIV1HALT_SHIFT)) & CGC_PLL0DIV_PFD_0_DIV1HALT_MASK)

#define CGC_PLL0DIV_PFD_0_DIV2_MASK              (0x3F00U)
#define CGC_PLL0DIV_PFD_0_DIV2_SHIFT             (8U)
/*! DIV2 - Clock Division for PLL0 PFD2 Clock */
#define CGC_PLL0DIV_PFD_0_DIV2(x)                (((uint32_t)(((uint32_t)(x)) << CGC_PLL0DIV_PFD_0_DIV2_SHIFT)) & CGC_PLL0DIV_PFD_0_DIV2_MASK)

#define CGC_PLL0DIV_PFD_0_DIV2LOCKED_MASK        (0x4000U)
#define CGC_PLL0DIV_PFD_0_DIV2LOCKED_SHIFT       (14U)
/*! DIV2LOCKED - The value of clock division was changed and access to DIV2 is locked */
#define CGC_PLL0DIV_PFD_0_DIV2LOCKED(x)          (((uint32_t)(((uint32_t)(x)) << CGC_PLL0DIV_PFD_0_DIV2LOCKED_SHIFT)) & CGC_PLL0DIV_PFD_0_DIV2LOCKED_MASK)

#define CGC_PLL0DIV_PFD_0_DIV2HALT_MASK          (0x8000U)
#define CGC_PLL0DIV_PFD_0_DIV2HALT_SHIFT         (15U)
/*! DIV2HALT - Divider 2 Halted */
#define CGC_PLL0DIV_PFD_0_DIV2HALT(x)            (((uint32_t)(((uint32_t)(x)) << CGC_PLL0DIV_PFD_0_DIV2HALT_SHIFT)) & CGC_PLL0DIV_PFD_0_DIV2HALT_MASK)
/*! @} */

/*! @name PLL0CFG - PLL0 Register Enable */
/*! @{ */

#define CGC_PLL0CFG_SOURCE_MASK                  (0x1U)
#define CGC_PLL0CFG_SOURCE_SHIFT                 (0U)
/*! SOURCE - Clock Source */
#define CGC_PLL0CFG_SOURCE(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_PLL0CFG_SOURCE_SHIFT)) & CGC_PLL0CFG_SOURCE_MASK)

#define CGC_PLL0CFG_HALF_LR_R_MASK               (0x8U)
#define CGC_PLL0CFG_HALF_LR_R_SHIFT              (3U)
/*! HALF_LR_R - Half Resistor in Low Pass Filter */
#define CGC_PLL0CFG_HALF_LR_R(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_PLL0CFG_HALF_LR_R_SHIFT)) & CGC_PLL0CFG_HALF_LR_R_MASK)

#define CGC_PLL0CFG_HALF_CP_CURRENT_MASK         (0x10U)
#define CGC_PLL0CFG_HALF_CP_CURRENT_SHIFT        (4U)
/*! HALF_CP_CURRENT - Half Charge Pump Current */
#define CGC_PLL0CFG_HALF_CP_CURRENT(x)           (((uint32_t)(((uint32_t)(x)) << CGC_PLL0CFG_HALF_CP_CURRENT_SHIFT)) & CGC_PLL0CFG_HALF_CP_CURRENT_MASK)

#define CGC_PLL0CFG_DOUBLE_LF_R_MASK             (0x20U)
#define CGC_PLL0CFG_DOUBLE_LF_R_SHIFT            (5U)
/*! DOUBLE_LF_R - Double Resistor in Low Pass Filter */
#define CGC_PLL0CFG_DOUBLE_LF_R(x)               (((uint32_t)(((uint32_t)(x)) << CGC_PLL0CFG_DOUBLE_LF_R_SHIFT)) & CGC_PLL0CFG_DOUBLE_LF_R_MASK)

#define CGC_PLL0CFG_DOUBLE_CP_CURRENT_MASK       (0x40U)
#define CGC_PLL0CFG_DOUBLE_CP_CURRENT_SHIFT      (6U)
/*! DOUBLE_CP_CURRENT - Double Charge Pumple Current */
#define CGC_PLL0CFG_DOUBLE_CP_CURRENT(x)         (((uint32_t)(((uint32_t)(x)) << CGC_PLL0CFG_DOUBLE_CP_CURRENT_SHIFT)) & CGC_PLL0CFG_DOUBLE_CP_CURRENT_MASK)

#define CGC_PLL0CFG_HOLDRING_OFF_MASK            (0x2000U)
#define CGC_PLL0CFG_HOLDRING_OFF_SHIFT           (13U)
/*! HOLDRING_OFF - HOLDRING_OFF */
#define CGC_PLL0CFG_HOLDRING_OFF(x)              (((uint32_t)(((uint32_t)(x)) << CGC_PLL0CFG_HOLDRING_OFF_SHIFT)) & CGC_PLL0CFG_HOLDRING_OFF_MASK)

#define CGC_PLL0CFG_MULT_MASK                    (0x70000U)
#define CGC_PLL0CFG_MULT_SHIFT                   (16U)
/*! MULT - System PLL Multiplier */
#define CGC_PLL0CFG_MULT(x)                      (((uint32_t)(((uint32_t)(x)) << CGC_PLL0CFG_MULT_SHIFT)) & CGC_PLL0CFG_MULT_MASK)
/*! @} */

/*! @name PLL0PFDCFG - PLL0 Configuration Register */
/*! @{ */

#define CGC_PLL0PFDCFG_PFD0_MASK                 (0x3FU)
#define CGC_PLL0PFDCFG_PFD0_SHIFT                (0U)
/*! PFD0 - PLL Fractional Divider 0 */
#define CGC_PLL0PFDCFG_PFD0(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_PLL0PFDCFG_PFD0_SHIFT)) & CGC_PLL0PFDCFG_PFD0_MASK)

#define CGC_PLL0PFDCFG_PFD0_VALID_MASK           (0x40U)
#define CGC_PLL0PFDCFG_PFD0_VALID_SHIFT          (6U)
/*! PFD0_VALID - PFD0_VALID */
#define CGC_PLL0PFDCFG_PFD0_VALID(x)             (((uint32_t)(((uint32_t)(x)) << CGC_PLL0PFDCFG_PFD0_VALID_SHIFT)) & CGC_PLL0PFDCFG_PFD0_VALID_MASK)

#define CGC_PLL0PFDCFG_PFD0_CLKGATE_MASK         (0x80U)
#define CGC_PLL0PFDCFG_PFD0_CLKGATE_SHIFT        (7U)
/*! PFD0_CLKGATE - Clock gate of PFD0 */
#define CGC_PLL0PFDCFG_PFD0_CLKGATE(x)           (((uint32_t)(((uint32_t)(x)) << CGC_PLL0PFDCFG_PFD0_CLKGATE_SHIFT)) & CGC_PLL0PFDCFG_PFD0_CLKGATE_MASK)

#define CGC_PLL0PFDCFG_PFD1_MASK                 (0x3F00U)
#define CGC_PLL0PFDCFG_PFD1_SHIFT                (8U)
/*! PFD1 - PLL Fractional Divider 1 */
#define CGC_PLL0PFDCFG_PFD1(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_PLL0PFDCFG_PFD1_SHIFT)) & CGC_PLL0PFDCFG_PFD1_MASK)

#define CGC_PLL0PFDCFG_PFD1_VALID_MASK           (0x4000U)
#define CGC_PLL0PFDCFG_PFD1_VALID_SHIFT          (14U)
/*! PFD1_VALID - PFD1_VALID */
#define CGC_PLL0PFDCFG_PFD1_VALID(x)             (((uint32_t)(((uint32_t)(x)) << CGC_PLL0PFDCFG_PFD1_VALID_SHIFT)) & CGC_PLL0PFDCFG_PFD1_VALID_MASK)

#define CGC_PLL0PFDCFG_PFD1_CLKGATE_MASK         (0x8000U)
#define CGC_PLL0PFDCFG_PFD1_CLKGATE_SHIFT        (15U)
/*! PFD1_CLKGATE - Clock gate of PFD1 */
#define CGC_PLL0PFDCFG_PFD1_CLKGATE(x)           (((uint32_t)(((uint32_t)(x)) << CGC_PLL0PFDCFG_PFD1_CLKGATE_SHIFT)) & CGC_PLL0PFDCFG_PFD1_CLKGATE_MASK)

#define CGC_PLL0PFDCFG_PFD2_MASK                 (0x3F0000U)
#define CGC_PLL0PFDCFG_PFD2_SHIFT                (16U)
/*! PFD2 - PLL Fractional Divider 2 */
#define CGC_PLL0PFDCFG_PFD2(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_PLL0PFDCFG_PFD2_SHIFT)) & CGC_PLL0PFDCFG_PFD2_MASK)

#define CGC_PLL0PFDCFG_PFD2_VALID_MASK           (0x400000U)
#define CGC_PLL0PFDCFG_PFD2_VALID_SHIFT          (22U)
/*! PFD2_VALID - PFD2_VALID */
#define CGC_PLL0PFDCFG_PFD2_VALID(x)             (((uint32_t)(((uint32_t)(x)) << CGC_PLL0PFDCFG_PFD2_VALID_SHIFT)) & CGC_PLL0PFDCFG_PFD2_VALID_MASK)

#define CGC_PLL0PFDCFG_PFD2_CLKGATE_MASK         (0x800000U)
#define CGC_PLL0PFDCFG_PFD2_CLKGATE_SHIFT        (23U)
/*! PFD2_CLKGATE - Clock gate of PFD2 */
#define CGC_PLL0PFDCFG_PFD2_CLKGATE(x)           (((uint32_t)(((uint32_t)(x)) << CGC_PLL0PFDCFG_PFD2_CLKGATE_SHIFT)) & CGC_PLL0PFDCFG_PFD2_CLKGATE_MASK)

#define CGC_PLL0PFDCFG_PFD3_MASK                 (0x3F000000U)
#define CGC_PLL0PFDCFG_PFD3_SHIFT                (24U)
/*! PFD3 - PLL Fractional Divider 3 */
#define CGC_PLL0PFDCFG_PFD3(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_PLL0PFDCFG_PFD3_SHIFT)) & CGC_PLL0PFDCFG_PFD3_MASK)

#define CGC_PLL0PFDCFG_PFD3_VALID_MASK           (0x40000000U)
#define CGC_PLL0PFDCFG_PFD3_VALID_SHIFT          (30U)
/*! PFD3_VALID - PFD3_VALID */
#define CGC_PLL0PFDCFG_PFD3_VALID(x)             (((uint32_t)(((uint32_t)(x)) << CGC_PLL0PFDCFG_PFD3_VALID_SHIFT)) & CGC_PLL0PFDCFG_PFD3_VALID_MASK)

#define CGC_PLL0PFDCFG_PFD3_CLKGATE_MASK         (0x80000000U)
#define CGC_PLL0PFDCFG_PFD3_CLKGATE_SHIFT        (31U)
/*! PFD3_CLKGATE - Clock gate of PFD3 */
#define CGC_PLL0PFDCFG_PFD3_CLKGATE(x)           (((uint32_t)(((uint32_t)(x)) << CGC_PLL0PFDCFG_PFD3_CLKGATE_SHIFT)) & CGC_PLL0PFDCFG_PFD3_CLKGATE_MASK)
/*! @} */

/*! @name PLL0LOCK - PLL LOCK Configuration Register */
/*! @{ */

#define CGC_PLL0LOCK_LOCK_TIME_MASK              (0xFFFFU)
#define CGC_PLL0LOCK_LOCK_TIME_SHIFT             (0U)
/*! LOCK_TIME - LOCK_TIME */
#define CGC_PLL0LOCK_LOCK_TIME(x)                (((uint32_t)(((uint32_t)(x)) << CGC_PLL0LOCK_LOCK_TIME_SHIFT)) & CGC_PLL0LOCK_LOCK_TIME_MASK)
/*! @} */

/*! @name PLL1CSR - PLL1 Control Status Register */
/*! @{ */

#define CGC_PLL1CSR_PLLEN_MASK                   (0x1U)
#define CGC_PLL1CSR_PLLEN_SHIFT                  (0U)
/*! PLLEN - PLL Enable */
#define CGC_PLL1CSR_PLLEN(x)                     (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CSR_PLLEN_SHIFT)) & CGC_PLL1CSR_PLLEN_MASK)

#define CGC_PLL1CSR_PLLDSEN_MASK                 (0x2U)
#define CGC_PLL1CSR_PLLDSEN_SHIFT                (1U)
/*! PLLDSEN - PLL1 Enable in Deep Sleep */
#define CGC_PLL1CSR_PLLDSEN(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CSR_PLLDSEN_SHIFT)) & CGC_PLL1CSR_PLLDSEN_MASK)

#define CGC_PLL1CSR_LK_MASK                      (0x800000U)
#define CGC_PLL1CSR_LK_SHIFT                     (23U)
/*! LK - Lock Register */
#define CGC_PLL1CSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CSR_LK_SHIFT)) & CGC_PLL1CSR_LK_MASK)

#define CGC_PLL1CSR_PLLVLD_MASK                  (0x1000000U)
#define CGC_PLL1CSR_PLLVLD_SHIFT                 (24U)
/*! PLLVLD - PLL1 Valid */
#define CGC_PLL1CSR_PLLVLD(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CSR_PLLVLD_SHIFT)) & CGC_PLL1CSR_PLLVLD_MASK)

#define CGC_PLL1CSR_PLLSEL_MASK                  (0x2000000U)
#define CGC_PLL1CSR_PLLSEL_SHIFT                 (25U)
/*! PLLSEL - PLL1 Selected */
#define CGC_PLL1CSR_PLLSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CSR_PLLSEL_SHIFT)) & CGC_PLL1CSR_PLLSEL_MASK)
/*! @} */

/*! @name PLL1DIV_VCO - Clock Dividers for the fractional PLL1 */
/*! @{ */

#define CGC_PLL1DIV_VCO_DIV1_MASK                (0x3FU)
#define CGC_PLL1DIV_VCO_DIV1_SHIFT               (0U)
/*! DIV1 - Clock Division for PLL1 VCO Clock */
#define CGC_PLL1DIV_VCO_DIV1(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_PLL1DIV_VCO_DIV1_SHIFT)) & CGC_PLL1DIV_VCO_DIV1_MASK)

#define CGC_PLL1DIV_VCO_DIV1LOCKED_MASK          (0x40U)
#define CGC_PLL1DIV_VCO_DIV1LOCKED_SHIFT         (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked */
#define CGC_PLL1DIV_VCO_DIV1LOCKED(x)            (((uint32_t)(((uint32_t)(x)) << CGC_PLL1DIV_VCO_DIV1LOCKED_SHIFT)) & CGC_PLL1DIV_VCO_DIV1LOCKED_MASK)

#define CGC_PLL1DIV_VCO_DIV1HALT_MASK            (0x80U)
#define CGC_PLL1DIV_VCO_DIV1HALT_SHIFT           (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_PLL1DIV_VCO_DIV1HALT(x)              (((uint32_t)(((uint32_t)(x)) << CGC_PLL1DIV_VCO_DIV1HALT_SHIFT)) & CGC_PLL1DIV_VCO_DIV1HALT_MASK)
/*! @} */

/*! @name PLL1DIV_PFD_0 - Clock Dividers for the fractional PLL1 */
/*! @{ */

#define CGC_PLL1DIV_PFD_0_DIV1_MASK              (0x3FU)
#define CGC_PLL1DIV_PFD_0_DIV1_SHIFT             (0U)
/*! DIV1 - Clock Division for PLL1 PFD1 Clock */
#define CGC_PLL1DIV_PFD_0_DIV1(x)                (((uint32_t)(((uint32_t)(x)) << CGC_PLL1DIV_PFD_0_DIV1_SHIFT)) & CGC_PLL1DIV_PFD_0_DIV1_MASK)

#define CGC_PLL1DIV_PFD_0_DIV1LOCKED_MASK        (0x40U)
#define CGC_PLL1DIV_PFD_0_DIV1LOCKED_SHIFT       (6U)
/*! DIV1LOCKED - Write to DIV1 Locked */
#define CGC_PLL1DIV_PFD_0_DIV1LOCKED(x)          (((uint32_t)(((uint32_t)(x)) << CGC_PLL1DIV_PFD_0_DIV1LOCKED_SHIFT)) & CGC_PLL1DIV_PFD_0_DIV1LOCKED_MASK)

#define CGC_PLL1DIV_PFD_0_DIV1HALT_MASK          (0x80U)
#define CGC_PLL1DIV_PFD_0_DIV1HALT_SHIFT         (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_PLL1DIV_PFD_0_DIV1HALT(x)            (((uint32_t)(((uint32_t)(x)) << CGC_PLL1DIV_PFD_0_DIV1HALT_SHIFT)) & CGC_PLL1DIV_PFD_0_DIV1HALT_MASK)

#define CGC_PLL1DIV_PFD_0_DIV2_MASK              (0x3F00U)
#define CGC_PLL1DIV_PFD_0_DIV2_SHIFT             (8U)
/*! DIV2 - Clock Division for PLL1 PFD2 Clock */
#define CGC_PLL1DIV_PFD_0_DIV2(x)                (((uint32_t)(((uint32_t)(x)) << CGC_PLL1DIV_PFD_0_DIV2_SHIFT)) & CGC_PLL1DIV_PFD_0_DIV2_MASK)

#define CGC_PLL1DIV_PFD_0_DIV2LOCKED_MASK        (0x4000U)
#define CGC_PLL1DIV_PFD_0_DIV2LOCKED_SHIFT       (14U)
/*! DIV2LOCKED - The value of clock division was changed and access to DIV2 is locked. */
#define CGC_PLL1DIV_PFD_0_DIV2LOCKED(x)          (((uint32_t)(((uint32_t)(x)) << CGC_PLL1DIV_PFD_0_DIV2LOCKED_SHIFT)) & CGC_PLL1DIV_PFD_0_DIV2LOCKED_MASK)

#define CGC_PLL1DIV_PFD_0_DIV2HALT_MASK          (0x8000U)
#define CGC_PLL1DIV_PFD_0_DIV2HALT_SHIFT         (15U)
/*! DIV2HALT - Divider 2 Halted */
#define CGC_PLL1DIV_PFD_0_DIV2HALT(x)            (((uint32_t)(((uint32_t)(x)) << CGC_PLL1DIV_PFD_0_DIV2HALT_SHIFT)) & CGC_PLL1DIV_PFD_0_DIV2HALT_MASK)
/*! @} */

/*! @name PLL1CFG - PLL1 Configuration Register */
/*! @{ */

#define CGC_PLL1CFG_SOURCE_MASK                  (0x1U)
#define CGC_PLL1CFG_SOURCE_SHIFT                 (0U)
/*! SOURCE - Clock Source */
#define CGC_PLL1CFG_SOURCE(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CFG_SOURCE_SHIFT)) & CGC_PLL1CFG_SOURCE_MASK)

#define CGC_PLL1CFG_HALF_LR_R_MASK               (0x8U)
#define CGC_PLL1CFG_HALF_LR_R_SHIFT              (3U)
/*! HALF_LR_R - Half Resistor in Low Pass Filter */
#define CGC_PLL1CFG_HALF_LR_R(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CFG_HALF_LR_R_SHIFT)) & CGC_PLL1CFG_HALF_LR_R_MASK)

#define CGC_PLL1CFG_HALF_CP_CURRENT_MASK         (0x10U)
#define CGC_PLL1CFG_HALF_CP_CURRENT_SHIFT        (4U)
/*! HALF_CP_CURRENT - Half Charge Pump Current */
#define CGC_PLL1CFG_HALF_CP_CURRENT(x)           (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CFG_HALF_CP_CURRENT_SHIFT)) & CGC_PLL1CFG_HALF_CP_CURRENT_MASK)

#define CGC_PLL1CFG_DOUBLE_LF_R_MASK             (0x20U)
#define CGC_PLL1CFG_DOUBLE_LF_R_SHIFT            (5U)
/*! DOUBLE_LF_R - Double Resistor in Low Pass Filter */
#define CGC_PLL1CFG_DOUBLE_LF_R(x)               (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CFG_DOUBLE_LF_R_SHIFT)) & CGC_PLL1CFG_DOUBLE_LF_R_MASK)

#define CGC_PLL1CFG_DOUBLE_CP_CURRENT_MASK       (0x40U)
#define CGC_PLL1CFG_DOUBLE_CP_CURRENT_SHIFT      (6U)
/*! DOUBLE_CP_CURRENT - Double Charge Pumple Current */
#define CGC_PLL1CFG_DOUBLE_CP_CURRENT(x)         (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CFG_DOUBLE_CP_CURRENT_SHIFT)) & CGC_PLL1CFG_DOUBLE_CP_CURRENT_MASK)

#define CGC_PLL1CFG_DITHER_EN_MASK               (0x800U)
#define CGC_PLL1CFG_DITHER_EN_SHIFT              (11U)
/*! DITHER_EN - DITHER_EN */
#define CGC_PLL1CFG_DITHER_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CFG_DITHER_EN_SHIFT)) & CGC_PLL1CFG_DITHER_EN_MASK)

#define CGC_PLL1CFG_PFD_OFFSET_EN_MASK           (0x1000U)
#define CGC_PLL1CFG_PFD_OFFSET_EN_SHIFT          (12U)
/*! PFD_OFFSET_EN - PFD_OFFSET_EN */
#define CGC_PLL1CFG_PFD_OFFSET_EN(x)             (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CFG_PFD_OFFSET_EN_SHIFT)) & CGC_PLL1CFG_PFD_OFFSET_EN_MASK)

#define CGC_PLL1CFG_HOLDRING_OFF_MASK            (0x2000U)
#define CGC_PLL1CFG_HOLDRING_OFF_SHIFT           (13U)
/*! HOLDRING_OFF - Hold Ring Off Control */
#define CGC_PLL1CFG_HOLDRING_OFF(x)              (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CFG_HOLDRING_OFF_SHIFT)) & CGC_PLL1CFG_HOLDRING_OFF_MASK)

#define CGC_PLL1CFG_MULT_MASK                    (0x7F0000U)
#define CGC_PLL1CFG_MULT_SHIFT                   (16U)
/*! MULT - System PLL Multiplier */
#define CGC_PLL1CFG_MULT(x)                      (((uint32_t)(((uint32_t)(x)) << CGC_PLL1CFG_MULT_SHIFT)) & CGC_PLL1CFG_MULT_MASK)
/*! @} */

/*! @name PLL1PFDCFG - PLL1 Configuration Register */
/*! @{ */

#define CGC_PLL1PFDCFG_PFD0_MASK                 (0x3FU)
#define CGC_PLL1PFDCFG_PFD0_SHIFT                (0U)
/*! PFD0 - PLL Fractional Divider 0 */
#define CGC_PLL1PFDCFG_PFD0(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_PLL1PFDCFG_PFD0_SHIFT)) & CGC_PLL1PFDCFG_PFD0_MASK)

#define CGC_PLL1PFDCFG_PFD0_VALID_MASK           (0x40U)
#define CGC_PLL1PFDCFG_PFD0_VALID_SHIFT          (6U)
/*! PFD0_VALID - PFD0_VALID */
#define CGC_PLL1PFDCFG_PFD0_VALID(x)             (((uint32_t)(((uint32_t)(x)) << CGC_PLL1PFDCFG_PFD0_VALID_SHIFT)) & CGC_PLL1PFDCFG_PFD0_VALID_MASK)

#define CGC_PLL1PFDCFG_PFD0_CLKGATE_MASK         (0x80U)
#define CGC_PLL1PFDCFG_PFD0_CLKGATE_SHIFT        (7U)
/*! PFD0_CLKGATE - Clock gate of PFD0 */
#define CGC_PLL1PFDCFG_PFD0_CLKGATE(x)           (((uint32_t)(((uint32_t)(x)) << CGC_PLL1PFDCFG_PFD0_CLKGATE_SHIFT)) & CGC_PLL1PFDCFG_PFD0_CLKGATE_MASK)

#define CGC_PLL1PFDCFG_PFD1_MASK                 (0x3F00U)
#define CGC_PLL1PFDCFG_PFD1_SHIFT                (8U)
/*! PFD1 - PLL Fractional Divider 0 */
#define CGC_PLL1PFDCFG_PFD1(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_PLL1PFDCFG_PFD1_SHIFT)) & CGC_PLL1PFDCFG_PFD1_MASK)

#define CGC_PLL1PFDCFG_PFD1_VALID_MASK           (0x4000U)
#define CGC_PLL1PFDCFG_PFD1_VALID_SHIFT          (14U)
/*! PFD1_VALID - PFD0_VALID */
#define CGC_PLL1PFDCFG_PFD1_VALID(x)             (((uint32_t)(((uint32_t)(x)) << CGC_PLL1PFDCFG_PFD1_VALID_SHIFT)) & CGC_PLL1PFDCFG_PFD1_VALID_MASK)

#define CGC_PLL1PFDCFG_PFD1_CLKGATE_MASK         (0x8000U)
#define CGC_PLL1PFDCFG_PFD1_CLKGATE_SHIFT        (15U)
/*! PFD1_CLKGATE - Clock gate of PFD0 */
#define CGC_PLL1PFDCFG_PFD1_CLKGATE(x)           (((uint32_t)(((uint32_t)(x)) << CGC_PLL1PFDCFG_PFD1_CLKGATE_SHIFT)) & CGC_PLL1PFDCFG_PFD1_CLKGATE_MASK)

#define CGC_PLL1PFDCFG_PFD2_MASK                 (0x3F0000U)
#define CGC_PLL1PFDCFG_PFD2_SHIFT                (16U)
/*! PFD2 - PLL Fractional Divider 0 */
#define CGC_PLL1PFDCFG_PFD2(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_PLL1PFDCFG_PFD2_SHIFT)) & CGC_PLL1PFDCFG_PFD2_MASK)

#define CGC_PLL1PFDCFG_PFD2_VALID_MASK           (0x400000U)
#define CGC_PLL1PFDCFG_PFD2_VALID_SHIFT          (22U)
/*! PFD2_VALID - PFD0_VALID */
#define CGC_PLL1PFDCFG_PFD2_VALID(x)             (((uint32_t)(((uint32_t)(x)) << CGC_PLL1PFDCFG_PFD2_VALID_SHIFT)) & CGC_PLL1PFDCFG_PFD2_VALID_MASK)

#define CGC_PLL1PFDCFG_PFD2_CLKGATE_MASK         (0x800000U)
#define CGC_PLL1PFDCFG_PFD2_CLKGATE_SHIFT        (23U)
/*! PFD2_CLKGATE - Clock gate of PFD0 */
#define CGC_PLL1PFDCFG_PFD2_CLKGATE(x)           (((uint32_t)(((uint32_t)(x)) << CGC_PLL1PFDCFG_PFD2_CLKGATE_SHIFT)) & CGC_PLL1PFDCFG_PFD2_CLKGATE_MASK)

#define CGC_PLL1PFDCFG_PFD3_MASK                 (0x3F000000U)
#define CGC_PLL1PFDCFG_PFD3_SHIFT                (24U)
/*! PFD3 - PLL Fractional Divider 3 */
#define CGC_PLL1PFDCFG_PFD3(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_PLL1PFDCFG_PFD3_SHIFT)) & CGC_PLL1PFDCFG_PFD3_MASK)

#define CGC_PLL1PFDCFG_PFD3_VALID_MASK           (0x40000000U)
#define CGC_PLL1PFDCFG_PFD3_VALID_SHIFT          (30U)
/*! PFD3_VALID - PFD3_VALID */
#define CGC_PLL1PFDCFG_PFD3_VALID(x)             (((uint32_t)(((uint32_t)(x)) << CGC_PLL1PFDCFG_PFD3_VALID_SHIFT)) & CGC_PLL1PFDCFG_PFD3_VALID_MASK)

#define CGC_PLL1PFDCFG_PFD3_CLKGATE_MASK         (0x80000000U)
#define CGC_PLL1PFDCFG_PFD3_CLKGATE_SHIFT        (31U)
/*! PFD3_CLKGATE - Clock gate of PFD3 */
#define CGC_PLL1PFDCFG_PFD3_CLKGATE(x)           (((uint32_t)(((uint32_t)(x)) << CGC_PLL1PFDCFG_PFD3_CLKGATE_SHIFT)) & CGC_PLL1PFDCFG_PFD3_CLKGATE_MASK)
/*! @} */

/*! @name PLL1DENOM - PLL Denominator Register */
/*! @{ */

#define CGC_PLL1DENOM_DENOM_MASK                 (0x3FFFFFFFU)
#define CGC_PLL1DENOM_DENOM_SHIFT                (0U)
/*! DENOM - PLL Denominator Register */
#define CGC_PLL1DENOM_DENOM(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_PLL1DENOM_DENOM_SHIFT)) & CGC_PLL1DENOM_DENOM_MASK)
/*! @} */

/*! @name PLL1NUM - PLL Numerator Register */
/*! @{ */

#define CGC_PLL1NUM_NUM_MASK                     (0x3FFFFFFFU)
#define CGC_PLL1NUM_NUM_SHIFT                    (0U)
/*! NUM - PLL Numerator Register */
#define CGC_PLL1NUM_NUM(x)                       (((uint32_t)(((uint32_t)(x)) << CGC_PLL1NUM_NUM_SHIFT)) & CGC_PLL1NUM_NUM_MASK)
/*! @} */

/*! @name PLL1SS - PLL Spread Spectrum Register */
/*! @{ */

#define CGC_PLL1SS_STEP_MASK                     (0x7FFFU)
#define CGC_PLL1SS_STEP_SHIFT                    (0U)
/*! STEP - STEP */
#define CGC_PLL1SS_STEP(x)                       (((uint32_t)(((uint32_t)(x)) << CGC_PLL1SS_STEP_SHIFT)) & CGC_PLL1SS_STEP_MASK)

#define CGC_PLL1SS_ENABLE_MASK                   (0x8000U)
#define CGC_PLL1SS_ENABLE_SHIFT                  (15U)
/*! ENABLE - ENABLE */
#define CGC_PLL1SS_ENABLE(x)                     (((uint32_t)(((uint32_t)(x)) << CGC_PLL1SS_ENABLE_SHIFT)) & CGC_PLL1SS_ENABLE_MASK)

#define CGC_PLL1SS_STOP_MASK                     (0xFFFF0000U)
#define CGC_PLL1SS_STOP_SHIFT                    (16U)
/*! STOP - STOP */
#define CGC_PLL1SS_STOP(x)                       (((uint32_t)(((uint32_t)(x)) << CGC_PLL1SS_STOP_SHIFT)) & CGC_PLL1SS_STOP_MASK)
/*! @} */

/*! @name PLL1LOCK - PLL LOCK Configuration Register */
/*! @{ */

#define CGC_PLL1LOCK_LOCK_TIME_MASK              (0xFFFFU)
#define CGC_PLL1LOCK_LOCK_TIME_SHIFT             (0U)
/*! LOCK_TIME - LOCK_TIME */
#define CGC_PLL1LOCK_LOCK_TIME(x)                (((uint32_t)(((uint32_t)(x)) << CGC_PLL1LOCK_LOCK_TIME_SHIFT)) & CGC_PLL1LOCK_LOCK_TIME_MASK)
/*! @} */

/*! @name RTCDIV - Clock Dividers for the RTC Oscilator */
/*! @{ */

#define CGC_RTCDIV_DIV1_MASK                     (0x3FFU)
#define CGC_RTCDIV_DIV1_SHIFT                    (0U)
/*! DIV1 - Clock Division for Slow Clock */
#define CGC_RTCDIV_DIV1(x)                       (((uint32_t)(((uint32_t)(x)) << CGC_RTCDIV_DIV1_SHIFT)) & CGC_RTCDIV_DIV1_MASK)

#define CGC_RTCDIV_HALTDIV_MASK                  (0x400U)
#define CGC_RTCDIV_HALTDIV_SHIFT                 (10U)
/*! HALTDIV - RTC Divider Halted */
#define CGC_RTCDIV_HALTDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_RTCDIV_HALTDIV_SHIFT)) & CGC_RTCDIV_HALTDIV_MASK)
/*! @} */

/*! @name AUD_CLK0 - AUD_CLK0 source to SAI0-3 */
/*! @{ */

#define CGC_AUD_CLK0_AUD_CLK0_MASK               (0xFU)
#define CGC_AUD_CLK0_AUD_CLK0_SHIFT              (0U)
/*! AUD_CLK0 - AUD_CLK0 Clock Source Selection */
#define CGC_AUD_CLK0_AUD_CLK0(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_AUD_CLK0_AUD_CLK0_SHIFT)) & CGC_AUD_CLK0_AUD_CLK0_MASK)
/*! @} */

/*! @name SAI3_0_CLK - SAI3-0 Clock Source Selection */
/*! @{ */

#define CGC_SAI3_0_CLK_SAI0CLK_MASK              (0x3U)
#define CGC_SAI3_0_CLK_SAI0CLK_SHIFT             (0U)
/*! SAI0CLK - Clock Source for SAI0 */
#define CGC_SAI3_0_CLK_SAI0CLK(x)                (((uint32_t)(((uint32_t)(x)) << CGC_SAI3_0_CLK_SAI0CLK_SHIFT)) & CGC_SAI3_0_CLK_SAI0CLK_MASK)

#define CGC_SAI3_0_CLK_SAI1CLK_MASK              (0x300U)
#define CGC_SAI3_0_CLK_SAI1CLK_SHIFT             (8U)
/*! SAI1CLK - Clock Source for SAI1 */
#define CGC_SAI3_0_CLK_SAI1CLK(x)                (((uint32_t)(((uint32_t)(x)) << CGC_SAI3_0_CLK_SAI1CLK_SHIFT)) & CGC_SAI3_0_CLK_SAI1CLK_MASK)

#define CGC_SAI3_0_CLK_SAI2CLK_MASK              (0x30000U)
#define CGC_SAI3_0_CLK_SAI2CLK_SHIFT             (16U)
/*! SAI2CLK - Clock Source for SAI2 */
#define CGC_SAI3_0_CLK_SAI2CLK(x)                (((uint32_t)(((uint32_t)(x)) << CGC_SAI3_0_CLK_SAI2CLK_SHIFT)) & CGC_SAI3_0_CLK_SAI2CLK_MASK)

#define CGC_SAI3_0_CLK_SAI3CLK_MASK              (0x3000000U)
#define CGC_SAI3_0_CLK_SAI3CLK_SHIFT             (24U)
/*! SAI3CLK - Clock Source for SAI3 */
#define CGC_SAI3_0_CLK_SAI3CLK(x)                (((uint32_t)(((uint32_t)(x)) << CGC_SAI3_0_CLK_SAI3CLK_SHIFT)) & CGC_SAI3_0_CLK_SAI3CLK_MASK)
/*! @} */

/*! @name TPM3_2CLK - Multiplexer to select the audio clock connected to the TPM clock input */
/*! @{ */

#define CGC_TPM3_2CLK_TPM2CLK_MASK               (0x3U)
#define CGC_TPM3_2CLK_TPM2CLK_SHIFT              (0U)
/*! TPM2CLK - Clock Selection for TPM2 */
#define CGC_TPM3_2CLK_TPM2CLK(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_TPM3_2CLK_TPM2CLK_SHIFT)) & CGC_TPM3_2CLK_TPM2CLK_MASK)

#define CGC_TPM3_2CLK_TPM3CLK_MASK               (0x300U)
#define CGC_TPM3_2CLK_TPM3CLK_SHIFT              (8U)
/*! TPM3CLK - Clock Selection for TPM3 */
#define CGC_TPM3_2CLK_TPM3CLK(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_TPM3_2CLK_TPM3CLK_SHIFT)) & CGC_TPM3_2CLK_TPM3CLK_MASK)
/*! @} */

/*! @name MQS0CLK - Multiplexer to select the audio clock connected to the MQS clock input */
/*! @{ */

#define CGC_MQS0CLK_MQS0CLK_MASK                 (0x3U)
#define CGC_MQS0CLK_MQS0CLK_SHIFT                (0U)
/*! MQS0CLK - Clock Selection for MQS0 */
#define CGC_MQS0CLK_MQS0CLK(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_MQS0CLK_MQS0CLK_SHIFT)) & CGC_MQS0CLK_MQS0CLK_MASK)
/*! @} */

/*! @name EMICFIL - Multiplexer to select the eMICFIL clock source */
/*! @{ */

#define CGC_EMICFIL_MICFILCLK_MASK               (0x7U)
#define CGC_EMICFIL_MICFILCLK_SHIFT              (0U)
/*! MICFILCLK - Clock Source for eMICFIL */
#define CGC_EMICFIL_MICFILCLK(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_EMICFIL_MICFILCLK_SHIFT)) & CGC_EMICFIL_MICFILCLK_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CGC_Register_Masks */


/* CGC - Peripheral instance base addresses */
/** Peripheral CGC_RTD base address */
#define CGC_RTD_BASE                             (0x2802F000u)
/** Peripheral CGC_RTD base pointer */
#define CGC_RTD                                  ((CGC_Type *)CGC_RTD_BASE)
/** Array initializer of CGC peripheral base addresses */
#define CGC_BASE_ADDRS                           { CGC_RTD_BASE }
/** Array initializer of CGC peripheral base pointers */
#define CGC_BASE_PTRS                            { CGC_RTD }

/*!
 * @}
 */ /* end of group CGC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CGC_AD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CGC_AD_Peripheral_Access_Layer CGC_AD Peripheral Access Layer
 * @{
 */

/** CGC_AD - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
       uint8_t RESERVED_0[16];
  __IO uint32_t CA35CLK;                           /**< Clock Selection and Dividers for the CA35 Domain, offset: 0x14 */
       uint8_t RESERVED_1[8];
  __IO uint32_t CLKOUTCFG;                         /**< Clockout selection for Application Domain, offset: 0x20 */
       uint8_t RESERVED_2[16];
  __IO uint32_t NICCLK;                            /**< Clock Selection and Dividers for the NIC/XBAR Domain, offset: 0x34 */
  __IO uint32_t XBARCLK;                           /**< Clock Selection and Dividers for the NIC/XBAR Domain, offset: 0x38 */
       uint8_t RESERVED_3[84];
  __IO uint32_t CLKDIVRST;                         /**< Clk Dividers Reset, offset: 0x90 */
       uint8_t RESERVED_4[116];
  __IO uint32_t SOSCDIV;                           /**< Clock Dividers for the SYS OSC Oscilator, offset: 0x108 */
       uint8_t RESERVED_5[252];
  __IO uint32_t FRODIV;                            /**< Clock Dividers for the FFRO 192 MHz Oscilator, offset: 0x208 */
       uint8_t RESERVED_6[756];
  __IO uint32_t PLL2CSR;                           /**< PLL2 Control Status Register, offset: 0x500 */
       uint8_t RESERVED_7[12];
  __IO uint32_t PLL2CFG;                           /**< PLL2 Configuration Register, offset: 0x510 */
       uint8_t RESERVED_8[4];
  __IO uint32_t PLL2DENOM;                         /**< Fractional PLL2 Denominator Control Register, offset: 0x518 */
  __IO uint32_t PLL2NUM;                           /**< Fractional PLL2 Numerator Control Register, offset: 0x51C */
  __IO uint32_t PLL2SS;                            /**< Fractional PLL2 Spread Spectrum Control Register, offset: 0x520 */
       uint8_t RESERVED_9[220];
  __IO uint32_t PLL3CSR;                           /**< PLL3 Control Status Register, offset: 0x600 */
  __IO uint32_t PLL3DIV_VCO;                       /**< Clock Dividers for the fractional PLL3, offset: 0x604 */
  __IO uint32_t PLL3DIV_PFD_0;                     /**< Clock Dividers for the fractional PLL3, offset: 0x608 */
  __IO uint32_t PLL3DIV_PFD_1;                     /**< Clock Dividers for the fractional PLL3, offset: 0x60C */
  __IO uint32_t PLL3CFG;                           /**< PLL3 Configuration Register, offset: 0x610 */
  __IO uint32_t PLL3PFDCFG;                        /**< PLL3 Configuration Register, offset: 0x614 */
  __IO uint32_t PLL3DENOM;                         /**< PLL3 Denominator Register, offset: 0x618 */
  __IO uint32_t PLL3NUM;                           /**< PLL3 Numerator Register, offset: 0x61C */
  __IO uint32_t PLL3SS;                            /**< PLL3 Spread Spectrum Register, offset: 0x620 */
  __IO uint32_t PLL3LOCK;                          /**< PLL3 LOCK Configuration Register, offset: 0x624 */
       uint8_t RESERVED_10[216];
  __IO uint32_t ENETSTAMP;                         /**< Clock Selection for Ethernet Time Stamp, offset: 0x700 */
       uint8_t RESERVED_11[268];
  __IO uint32_t PLLUSBCFG;                         /**< PLLUSB Register Enable, offset: 0x810 */
       uint8_t RESERVED_12[236];
  __IO uint32_t AUD_CLK1;                          /**< AUD_CLK1 source to SAI4-5, offset: 0x900 */
  __IO uint32_t SAI5_4_CLK;                        /**< SAI5-4 Clock Source Selection, offset: 0x904 */
  __IO uint32_t TPM6_7CLK;                         /**< Multiplexer to select the audio clock connected to the TPM clock input, offset: 0x908 */
  __IO uint32_t MQS1CLK;                           /**< Multiplexer to select the audio clock connected to the MQS clock input, offset: 0x90C */
} CGC_AD_Type;

/* ----------------------------------------------------------------------------
   -- CGC_AD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CGC_AD_Register_Masks CGC_AD Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define CGC_AD_VERID_FEATURE_MASK                (0xFFFFU)
#define CGC_AD_VERID_FEATURE_SHIFT               (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000010..Master only with standard feature set.
 *  0b0000000000000011..Master and slave with standard feature set.
 */
#define CGC_AD_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_AD_VERID_FEATURE_SHIFT)) & CGC_AD_VERID_FEATURE_MASK)

#define CGC_AD_VERID_MINOR_MASK                  (0xFF0000U)
#define CGC_AD_VERID_MINOR_SHIFT                 (16U)
/*! MINOR - Minor Version Number */
#define CGC_AD_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_AD_VERID_MINOR_SHIFT)) & CGC_AD_VERID_MINOR_MASK)

#define CGC_AD_VERID_MAJOR_MASK                  (0xFF000000U)
#define CGC_AD_VERID_MAJOR_SHIFT                 (24U)
/*! MAJOR - Major Version Number */
#define CGC_AD_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_AD_VERID_MAJOR_SHIFT)) & CGC_AD_VERID_MAJOR_MASK)
/*! @} */

/*! @name CA35CLK - Clock Selection and Dividers for the CA35 Domain */
/*! @{ */

#define CGC_AD_CA35CLK_DIVCORE_MASK              (0x7E00000U)
#define CGC_AD_CA35CLK_DIVCORE_SHIFT             (21U)
/*! DIVCORE - Clock Division for Core Clock */
#define CGC_AD_CA35CLK_DIVCORE(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_CA35CLK_DIVCORE_SHIFT)) & CGC_AD_CA35CLK_DIVCORE_MASK)

#define CGC_AD_CA35CLK_SCSW_MASK                 (0x8000000U)
#define CGC_AD_CA35CLK_SCSW_SHIFT                (27U)
/*! SCSW - Clock switched to selected clock source */
#define CGC_AD_CA35CLK_SCSW(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_AD_CA35CLK_SCSW_SHIFT)) & CGC_AD_CA35CLK_SCSW_MASK)

#define CGC_AD_CA35CLK_SCS_MASK                  (0x30000000U)
#define CGC_AD_CA35CLK_SCS_SHIFT                 (28U)
/*! SCS - Clock Selection for CA35 Domain */
#define CGC_AD_CA35CLK_SCS(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_AD_CA35CLK_SCS_SHIFT)) & CGC_AD_CA35CLK_SCS_MASK)

#define CGC_AD_CA35CLK_CA35LOCKED_MASK           (0x80000000U)
#define CGC_AD_CA35CLK_CA35LOCKED_SHIFT          (31U)
/*! CA35LOCKED - CA35CLK Register Locked */
#define CGC_AD_CA35CLK_CA35LOCKED(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_CA35CLK_CA35LOCKED_SHIFT)) & CGC_AD_CA35CLK_CA35LOCKED_MASK)
/*! @} */

/*! @name CLKOUTCFG - Clockout selection for Application Domain */
/*! @{ */

#define CGC_AD_CLKOUTCFG_CLKOUT_DIV_MASK         (0x7E0000U)
#define CGC_AD_CLKOUTCFG_CLKOUT_DIV_SHIFT        (17U)
/*! CLKOUT_DIV - Select the clock division for the CLKOUT pin */
#define CGC_AD_CLKOUTCFG_CLKOUT_DIV(x)           (((uint32_t)(((uint32_t)(x)) << CGC_AD_CLKOUTCFG_CLKOUT_DIV_SHIFT)) & CGC_AD_CLKOUTCFG_CLKOUT_DIV_MASK)

#define CGC_AD_CLKOUTCFG_CLKOUT_SEL_MASK         (0x7800000U)
#define CGC_AD_CLKOUTCFG_CLKOUT_SEL_SHIFT        (23U)
/*! CLKOUT_SEL - Select the clock source redirected to CLKOUT pin */
#define CGC_AD_CLKOUTCFG_CLKOUT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CGC_AD_CLKOUTCFG_CLKOUT_SEL_SHIFT)) & CGC_AD_CLKOUTCFG_CLKOUT_SEL_MASK)

#define CGC_AD_CLKOUTCFG_CLKOUT_EN_MASK          (0x10000000U)
#define CGC_AD_CLKOUTCFG_CLKOUT_EN_SHIFT         (28U)
/*! CLKOUT_EN - Clockout Enable */
#define CGC_AD_CLKOUTCFG_CLKOUT_EN(x)            (((uint32_t)(((uint32_t)(x)) << CGC_AD_CLKOUTCFG_CLKOUT_EN_SHIFT)) & CGC_AD_CLKOUTCFG_CLKOUT_EN_MASK)
/*! @} */

/*! @name NICCLK - Clock Selection and Dividers for the NIC/XBAR Domain */
/*! @{ */

#define CGC_AD_NICCLK_NIC_PER_DIVPLAT_MASK       (0xFC000U)
#define CGC_AD_NICCLK_NIC_PER_DIVPLAT_SHIFT      (14U)
/*! NIC_PER_DIVPLAT - Clock Division for Core Clock */
#define CGC_AD_NICCLK_NIC_PER_DIVPLAT(x)         (((uint32_t)(((uint32_t)(x)) << CGC_AD_NICCLK_NIC_PER_DIVPLAT_SHIFT)) & CGC_AD_NICCLK_NIC_PER_DIVPLAT_MASK)

#define CGC_AD_NICCLK_NIC_AD_DIVPLAT_MASK        (0x7E00000U)
#define CGC_AD_NICCLK_NIC_AD_DIVPLAT_SHIFT       (21U)
/*! NIC_AD_DIVPLAT - Clock Division for Platform Clock */
#define CGC_AD_NICCLK_NIC_AD_DIVPLAT(x)          (((uint32_t)(((uint32_t)(x)) << CGC_AD_NICCLK_NIC_AD_DIVPLAT_SHIFT)) & CGC_AD_NICCLK_NIC_AD_DIVPLAT_MASK)

#define CGC_AD_NICCLK_SCSW_MASK                  (0x8000000U)
#define CGC_AD_NICCLK_SCSW_SHIFT                 (27U)
/*! SCSW - Clock switched to selected clock source */
#define CGC_AD_NICCLK_SCSW(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_AD_NICCLK_SCSW_SHIFT)) & CGC_AD_NICCLK_SCSW_MASK)

#define CGC_AD_NICCLK_SCS_MASK                   (0x30000000U)
#define CGC_AD_NICCLK_SCS_SHIFT                  (28U)
/*! SCS - Clock Selection forNIC Domain */
#define CGC_AD_NICCLK_SCS(x)                     (((uint32_t)(((uint32_t)(x)) << CGC_AD_NICCLK_SCS_SHIFT)) & CGC_AD_NICCLK_SCS_MASK)

#define CGC_AD_NICCLK_NICLOCKED_MASK             (0x80000000U)
#define CGC_AD_NICCLK_NICLOCKED_SHIFT            (31U)
/*! NICLOCKED - NICCLK Register Locked */
#define CGC_AD_NICCLK_NICLOCKED(x)               (((uint32_t)(((uint32_t)(x)) << CGC_AD_NICCLK_NICLOCKED_SHIFT)) & CGC_AD_NICCLK_NICLOCKED_MASK)
/*! @} */

/*! @name XBARCLK - Clock Selection and Dividers for the NIC/XBAR Domain */
/*! @{ */

#define CGC_AD_XBARCLK_AD_SLOW_MASK              (0x3FU)
#define CGC_AD_XBARCLK_AD_SLOW_SHIFT             (0U)
/*! AD_SLOW - Clock Division for Slow Clock */
#define CGC_AD_XBARCLK_AD_SLOW(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_XBARCLK_AD_SLOW_SHIFT)) & CGC_AD_XBARCLK_AD_SLOW_MASK)

#define CGC_AD_XBARCLK_XBAR_DIVBUS_MASK          (0x1F80U)
#define CGC_AD_XBARCLK_XBAR_DIVBUS_SHIFT         (7U)
/*! XBAR_DIVBUS - Clock Division for Bus Clock */
#define CGC_AD_XBARCLK_XBAR_DIVBUS(x)            (((uint32_t)(((uint32_t)(x)) << CGC_AD_XBARCLK_XBAR_DIVBUS_SHIFT)) & CGC_AD_XBARCLK_XBAR_DIVBUS_MASK)

#define CGC_AD_XBARCLK_XBAR_AD_DIVPLAT_MASK      (0xFC000U)
#define CGC_AD_XBARCLK_XBAR_AD_DIVPLAT_SHIFT     (14U)
/*! XBAR_AD_DIVPLAT - Clock Division for Plat Clk */
#define CGC_AD_XBARCLK_XBAR_AD_DIVPLAT(x)        (((uint32_t)(((uint32_t)(x)) << CGC_AD_XBARCLK_XBAR_AD_DIVPLAT_SHIFT)) & CGC_AD_XBARCLK_XBAR_AD_DIVPLAT_MASK)

#define CGC_AD_XBARCLK_XBARLOCKED_MASK           (0x80000000U)
#define CGC_AD_XBARCLK_XBARLOCKED_SHIFT          (31U)
/*! XBARLOCKED - XBARCLK Register Locked */
#define CGC_AD_XBARCLK_XBARLOCKED(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_XBARCLK_XBARLOCKED_SHIFT)) & CGC_AD_XBARCLK_XBARLOCKED_MASK)
/*! @} */

/*! @name CLKDIVRST - Clk Dividers Reset */
/*! @{ */

#define CGC_AD_CLKDIVRST_NIC_OUT_OF_PHASE_MASK   (0x10000U)
#define CGC_AD_CLKDIVRST_NIC_OUT_OF_PHASE_SHIFT  (16U)
/*! NIC_OUT_OF_PHASE - NIC clocks dividers reset */
#define CGC_AD_CLKDIVRST_NIC_OUT_OF_PHASE(x)     (((uint32_t)(((uint32_t)(x)) << CGC_AD_CLKDIVRST_NIC_OUT_OF_PHASE_SHIFT)) & CGC_AD_CLKDIVRST_NIC_OUT_OF_PHASE_MASK)

#define CGC_AD_CLKDIVRST_NIC_RST_DIVIDERS_EN_MASK (0x20000U)
#define CGC_AD_CLKDIVRST_NIC_RST_DIVIDERS_EN_SHIFT (17U)
/*! NIC_RST_DIVIDERS_EN - NIC clocks dividers out of phase interrupt */
#define CGC_AD_CLKDIVRST_NIC_RST_DIVIDERS_EN(x)  (((uint32_t)(((uint32_t)(x)) << CGC_AD_CLKDIVRST_NIC_RST_DIVIDERS_EN_SHIFT)) & CGC_AD_CLKDIVRST_NIC_RST_DIVIDERS_EN_MASK)

#define CGC_AD_CLKDIVRST_NIC_INTERRUPT_EN_MASK   (0x40000U)
#define CGC_AD_CLKDIVRST_NIC_INTERRUPT_EN_SHIFT  (18U)
/*! NIC_INTERRUPT_EN - Selection between interrupt generation or clock dividers reset when NIC clocks are out of phase */
#define CGC_AD_CLKDIVRST_NIC_INTERRUPT_EN(x)     (((uint32_t)(((uint32_t)(x)) << CGC_AD_CLKDIVRST_NIC_INTERRUPT_EN_SHIFT)) & CGC_AD_CLKDIVRST_NIC_INTERRUPT_EN_MASK)

#define CGC_AD_CLKDIVRST_NIC_RESET_EN_MASK       (0x80000U)
#define CGC_AD_CLKDIVRST_NIC_RESET_EN_SHIFT      (19U)
#define CGC_AD_CLKDIVRST_NIC_RESET_EN(x)         (((uint32_t)(((uint32_t)(x)) << CGC_AD_CLKDIVRST_NIC_RESET_EN_SHIFT)) & CGC_AD_CLKDIVRST_NIC_RESET_EN_MASK)
/*! @} */

/*! @name SOSCDIV - Clock Dividers for the SYS OSC Oscilator */
/*! @{ */

#define CGC_AD_SOSCDIV_DIV1_MASK                 (0x3FU)
#define CGC_AD_SOSCDIV_DIV1_SHIFT                (0U)
/*! DIV1 - Clock Division for Slow Clock */
#define CGC_AD_SOSCDIV_DIV1(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_AD_SOSCDIV_DIV1_SHIFT)) & CGC_AD_SOSCDIV_DIV1_MASK)

#define CGC_AD_SOSCDIV_DIV1LOCKED_MASK           (0x40U)
#define CGC_AD_SOSCDIV_DIV1LOCKED_SHIFT          (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked */
#define CGC_AD_SOSCDIV_DIV1LOCKED(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_SOSCDIV_DIV1LOCKED_SHIFT)) & CGC_AD_SOSCDIV_DIV1LOCKED_MASK)

#define CGC_AD_SOSCDIV_DIV1HALT_MASK             (0x80U)
#define CGC_AD_SOSCDIV_DIV1HALT_SHIFT            (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_AD_SOSCDIV_DIV1HALT(x)               (((uint32_t)(((uint32_t)(x)) << CGC_AD_SOSCDIV_DIV1HALT_SHIFT)) & CGC_AD_SOSCDIV_DIV1HALT_MASK)

#define CGC_AD_SOSCDIV_DIV2_MASK                 (0x3F00U)
#define CGC_AD_SOSCDIV_DIV2_SHIFT                (8U)
/*! DIV2 - Clock Division for Bus Clock */
#define CGC_AD_SOSCDIV_DIV2(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_AD_SOSCDIV_DIV2_SHIFT)) & CGC_AD_SOSCDIV_DIV2_MASK)

#define CGC_AD_SOSCDIV_DIV2LOCKED_MASK           (0x4000U)
#define CGC_AD_SOSCDIV_DIV2LOCKED_SHIFT          (14U)
/*! DIV2LOCKED - The value of clock division was changed and access to DIV2 is locked */
#define CGC_AD_SOSCDIV_DIV2LOCKED(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_SOSCDIV_DIV2LOCKED_SHIFT)) & CGC_AD_SOSCDIV_DIV2LOCKED_MASK)

#define CGC_AD_SOSCDIV_DIV2HALT_MASK             (0x8000U)
#define CGC_AD_SOSCDIV_DIV2HALT_SHIFT            (15U)
/*! DIV2HALT - Divider 2 Halted */
#define CGC_AD_SOSCDIV_DIV2HALT(x)               (((uint32_t)(((uint32_t)(x)) << CGC_AD_SOSCDIV_DIV2HALT_SHIFT)) & CGC_AD_SOSCDIV_DIV2HALT_MASK)

#define CGC_AD_SOSCDIV_DIV3_MASK                 (0x3F0000U)
#define CGC_AD_SOSCDIV_DIV3_SHIFT                (16U)
/*! DIV3 - Clock Division for Platform Clock */
#define CGC_AD_SOSCDIV_DIV3(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_AD_SOSCDIV_DIV3_SHIFT)) & CGC_AD_SOSCDIV_DIV3_MASK)

#define CGC_AD_SOSCDIV_DIV3LOCKED_MASK           (0x400000U)
#define CGC_AD_SOSCDIV_DIV3LOCKED_SHIFT          (22U)
/*! DIV3LOCKED - The value of clock division was changed and access to DIV3 is locked */
#define CGC_AD_SOSCDIV_DIV3LOCKED(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_SOSCDIV_DIV3LOCKED_SHIFT)) & CGC_AD_SOSCDIV_DIV3LOCKED_MASK)

#define CGC_AD_SOSCDIV_DIV3HALT_MASK             (0x800000U)
#define CGC_AD_SOSCDIV_DIV3HALT_SHIFT            (23U)
/*! DIV3HALT - Divider 3 Halted */
#define CGC_AD_SOSCDIV_DIV3HALT(x)               (((uint32_t)(((uint32_t)(x)) << CGC_AD_SOSCDIV_DIV3HALT_SHIFT)) & CGC_AD_SOSCDIV_DIV3HALT_MASK)
/*! @} */

/*! @name FRODIV - Clock Dividers for the FFRO 192 MHz Oscilator */
/*! @{ */

#define CGC_AD_FRODIV_DIV1_MASK                  (0x3FU)
#define CGC_AD_FRODIV_DIV1_SHIFT                 (0U)
/*! DIV1 - Clock Division for FFRO Clock */
#define CGC_AD_FRODIV_DIV1(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_AD_FRODIV_DIV1_SHIFT)) & CGC_AD_FRODIV_DIV1_MASK)

#define CGC_AD_FRODIV_DIV1LOCKED_MASK            (0x40U)
#define CGC_AD_FRODIV_DIV1LOCKED_SHIFT           (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked */
#define CGC_AD_FRODIV_DIV1LOCKED(x)              (((uint32_t)(((uint32_t)(x)) << CGC_AD_FRODIV_DIV1LOCKED_SHIFT)) & CGC_AD_FRODIV_DIV1LOCKED_MASK)

#define CGC_AD_FRODIV_DIV1HALT_MASK              (0x80U)
#define CGC_AD_FRODIV_DIV1HALT_SHIFT             (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_AD_FRODIV_DIV1HALT(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_FRODIV_DIV1HALT_SHIFT)) & CGC_AD_FRODIV_DIV1HALT_MASK)

#define CGC_AD_FRODIV_DIV2_MASK                  (0x3F00U)
#define CGC_AD_FRODIV_DIV2_SHIFT                 (8U)
/*! DIV2 - Clock Division for FFRO Clock */
#define CGC_AD_FRODIV_DIV2(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_AD_FRODIV_DIV2_SHIFT)) & CGC_AD_FRODIV_DIV2_MASK)

#define CGC_AD_FRODIV_DIV2LOCKED_MASK            (0x4000U)
#define CGC_AD_FRODIV_DIV2LOCKED_SHIFT           (14U)
/*! DIV2LOCKED - The value of clock division was changed and access to DIV2 is locked */
#define CGC_AD_FRODIV_DIV2LOCKED(x)              (((uint32_t)(((uint32_t)(x)) << CGC_AD_FRODIV_DIV2LOCKED_SHIFT)) & CGC_AD_FRODIV_DIV2LOCKED_MASK)

#define CGC_AD_FRODIV_DIV2HALT_MASK              (0x8000U)
#define CGC_AD_FRODIV_DIV2HALT_SHIFT             (15U)
/*! DIV2HALT - Divider 2 Halted */
#define CGC_AD_FRODIV_DIV2HALT(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_FRODIV_DIV2HALT_SHIFT)) & CGC_AD_FRODIV_DIV2HALT_MASK)

#define CGC_AD_FRODIV_DIV3_MASK                  (0x3F0000U)
#define CGC_AD_FRODIV_DIV3_SHIFT                 (16U)
/*! DIV3 - Clock Division for FFRO Clock */
#define CGC_AD_FRODIV_DIV3(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_AD_FRODIV_DIV3_SHIFT)) & CGC_AD_FRODIV_DIV3_MASK)

#define CGC_AD_FRODIV_DIV3LOCKED_MASK            (0x400000U)
#define CGC_AD_FRODIV_DIV3LOCKED_SHIFT           (22U)
/*! DIV3LOCKED - The value of clock division was changed and access to DIV3 is locked */
#define CGC_AD_FRODIV_DIV3LOCKED(x)              (((uint32_t)(((uint32_t)(x)) << CGC_AD_FRODIV_DIV3LOCKED_SHIFT)) & CGC_AD_FRODIV_DIV3LOCKED_MASK)

#define CGC_AD_FRODIV_DIV3HALT_MASK              (0x800000U)
#define CGC_AD_FRODIV_DIV3HALT_SHIFT             (23U)
/*! DIV3HALT - Divider 3 Halted */
#define CGC_AD_FRODIV_DIV3HALT(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_FRODIV_DIV3HALT_SHIFT)) & CGC_AD_FRODIV_DIV3HALT_MASK)
/*! @} */

/*! @name PLL2CSR - PLL2 Control Status Register */
/*! @{ */

#define CGC_AD_PLL2CSR_PLLEN_MASK                (0x1U)
#define CGC_AD_PLL2CSR_PLLEN_SHIFT               (0U)
/*! PLLEN - PLL Enable */
#define CGC_AD_PLL2CSR_PLLEN(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL2CSR_PLLEN_SHIFT)) & CGC_AD_PLL2CSR_PLLEN_MASK)

#define CGC_AD_PLL2CSR_PLLDSEN_MASK              (0x2U)
#define CGC_AD_PLL2CSR_PLLDSEN_SHIFT             (1U)
/*! PLLDSEN - PLL2 Enable in Deep Sleep */
#define CGC_AD_PLL2CSR_PLLDSEN(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL2CSR_PLLDSEN_SHIFT)) & CGC_AD_PLL2CSR_PLLDSEN_MASK)

#define CGC_AD_PLL2CSR_LK_MASK                   (0x800000U)
#define CGC_AD_PLL2CSR_LK_SHIFT                  (23U)
/*! LK - Lock Register */
#define CGC_AD_PLL2CSR_LK(x)                     (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL2CSR_LK_SHIFT)) & CGC_AD_PLL2CSR_LK_MASK)

#define CGC_AD_PLL2CSR_PLLVLD_MASK               (0x1000000U)
#define CGC_AD_PLL2CSR_PLLVLD_SHIFT              (24U)
/*! PLLVLD - PLL Valid */
#define CGC_AD_PLL2CSR_PLLVLD(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL2CSR_PLLVLD_SHIFT)) & CGC_AD_PLL2CSR_PLLVLD_MASK)

#define CGC_AD_PLL2CSR_PLLSEL_MASK               (0x2000000U)
#define CGC_AD_PLL2CSR_PLLSEL_SHIFT              (25U)
/*! PLLSEL - PLL Selected */
#define CGC_AD_PLL2CSR_PLLSEL(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL2CSR_PLLSEL_SHIFT)) & CGC_AD_PLL2CSR_PLLSEL_MASK)
/*! @} */

/*! @name PLL2CFG - PLL2 Configuration Register */
/*! @{ */

#define CGC_AD_PLL2CFG_SOURCE_MASK               (0x1U)
#define CGC_AD_PLL2CFG_SOURCE_SHIFT              (0U)
/*! SOURCE - Clock Source */
#define CGC_AD_PLL2CFG_SOURCE(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL2CFG_SOURCE_SHIFT)) & CGC_AD_PLL2CFG_SOURCE_MASK)

#define CGC_AD_PLL2CFG_MULT_MASK                 (0x7F0000U)
#define CGC_AD_PLL2CFG_MULT_SHIFT                (16U)
/*! MULT - System PLL Multiplier */
#define CGC_AD_PLL2CFG_MULT(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL2CFG_MULT_SHIFT)) & CGC_AD_PLL2CFG_MULT_MASK)
/*! @} */

/*! @name PLL2DENOM - Fractional PLL2 Denominator Control Register */
/*! @{ */

#define CGC_AD_PLL2DENOM_DENOM_MASK              (0x3FFFFFFFU)
#define CGC_AD_PLL2DENOM_DENOM_SHIFT             (0U)
/*! DENOM - Denominator */
#define CGC_AD_PLL2DENOM_DENOM(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL2DENOM_DENOM_SHIFT)) & CGC_AD_PLL2DENOM_DENOM_MASK)
/*! @} */

/*! @name PLL2NUM - Fractional PLL2 Numerator Control Register */
/*! @{ */

#define CGC_AD_PLL2NUM_NUM_MASK                  (0x3FFFFFFFU)
#define CGC_AD_PLL2NUM_NUM_SHIFT                 (0U)
/*! NUM - Numerator */
#define CGC_AD_PLL2NUM_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL2NUM_NUM_SHIFT)) & CGC_AD_PLL2NUM_NUM_MASK)
/*! @} */

/*! @name PLL2SS - Fractional PLL2 Spread Spectrum Control Register */
/*! @{ */

#define CGC_AD_PLL2SS_STEP_MASK                  (0x7FFFU)
#define CGC_AD_PLL2SS_STEP_SHIFT                 (0U)
/*! STEP - Step */
#define CGC_AD_PLL2SS_STEP(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL2SS_STEP_SHIFT)) & CGC_AD_PLL2SS_STEP_MASK)

#define CGC_AD_PLL2SS_ENABLE_MASK                (0x8000U)
#define CGC_AD_PLL2SS_ENABLE_SHIFT               (15U)
/*! ENABLE - Enable */
#define CGC_AD_PLL2SS_ENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL2SS_ENABLE_SHIFT)) & CGC_AD_PLL2SS_ENABLE_MASK)

#define CGC_AD_PLL2SS_STOP_MASK                  (0xFFFF0000U)
#define CGC_AD_PLL2SS_STOP_SHIFT                 (16U)
/*! STOP - Stop */
#define CGC_AD_PLL2SS_STOP(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL2SS_STOP_SHIFT)) & CGC_AD_PLL2SS_STOP_MASK)
/*! @} */

/*! @name PLL3CSR - PLL3 Control Status Register */
/*! @{ */

#define CGC_AD_PLL3CSR_PLLEN_MASK                (0x1U)
#define CGC_AD_PLL3CSR_PLLEN_SHIFT               (0U)
/*! PLLEN - PLL Enable */
#define CGC_AD_PLL3CSR_PLLEN(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CSR_PLLEN_SHIFT)) & CGC_AD_PLL3CSR_PLLEN_MASK)

#define CGC_AD_PLL3CSR_PLLDSEN_MASK              (0x2U)
#define CGC_AD_PLL3CSR_PLLDSEN_SHIFT             (1U)
/*! PLLDSEN - PLL3 Enable in Deep Sleep */
#define CGC_AD_PLL3CSR_PLLDSEN(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CSR_PLLDSEN_SHIFT)) & CGC_AD_PLL3CSR_PLLDSEN_MASK)

#define CGC_AD_PLL3CSR_LK_MASK                   (0x800000U)
#define CGC_AD_PLL3CSR_LK_SHIFT                  (23U)
/*! LK - Lock Register */
#define CGC_AD_PLL3CSR_LK(x)                     (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CSR_LK_SHIFT)) & CGC_AD_PLL3CSR_LK_MASK)

#define CGC_AD_PLL3CSR_PLLVLD_MASK               (0x1000000U)
#define CGC_AD_PLL3CSR_PLLVLD_SHIFT              (24U)
/*! PLLVLD - PLL Valid */
#define CGC_AD_PLL3CSR_PLLVLD(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CSR_PLLVLD_SHIFT)) & CGC_AD_PLL3CSR_PLLVLD_MASK)

#define CGC_AD_PLL3CSR_PLLSEL_MASK               (0x2000000U)
#define CGC_AD_PLL3CSR_PLLSEL_SHIFT              (25U)
/*! PLLSEL - PLL Selected */
#define CGC_AD_PLL3CSR_PLLSEL(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CSR_PLLSEL_SHIFT)) & CGC_AD_PLL3CSR_PLLSEL_MASK)
/*! @} */

/*! @name PLL3DIV_VCO - Clock Dividers for the fractional PLL3 */
/*! @{ */

#define CGC_AD_PLL3DIV_VCO_DIV1_MASK             (0x3FU)
#define CGC_AD_PLL3DIV_VCO_DIV1_SHIFT            (0U)
/*! DIV1 - Clock Division for PLL3 VCO Clock */
#define CGC_AD_PLL3DIV_VCO_DIV1(x)               (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_VCO_DIV1_SHIFT)) & CGC_AD_PLL3DIV_VCO_DIV1_MASK)

#define CGC_AD_PLL3DIV_VCO_DIV1LOCKED_MASK       (0x40U)
#define CGC_AD_PLL3DIV_VCO_DIV1LOCKED_SHIFT      (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked */
#define CGC_AD_PLL3DIV_VCO_DIV1LOCKED(x)         (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_VCO_DIV1LOCKED_SHIFT)) & CGC_AD_PLL3DIV_VCO_DIV1LOCKED_MASK)

#define CGC_AD_PLL3DIV_VCO_DIV1HALT_MASK         (0x80U)
#define CGC_AD_PLL3DIV_VCO_DIV1HALT_SHIFT        (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_AD_PLL3DIV_VCO_DIV1HALT(x)           (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_VCO_DIV1HALT_SHIFT)) & CGC_AD_PLL3DIV_VCO_DIV1HALT_MASK)
/*! @} */

/*! @name PLL3DIV_PFD_0 - Clock Dividers for the fractional PLL3 */
/*! @{ */

#define CGC_AD_PLL3DIV_PFD_0_DIV1_MASK           (0x3FU)
#define CGC_AD_PLL3DIV_PFD_0_DIV1_SHIFT          (0U)
/*! DIV1 - Clock Division for PLL3 PFD0 Clock */
#define CGC_AD_PLL3DIV_PFD_0_DIV1(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_0_DIV1_SHIFT)) & CGC_AD_PLL3DIV_PFD_0_DIV1_MASK)

#define CGC_AD_PLL3DIV_PFD_0_DIV1LOCKED_MASK     (0x40U)
#define CGC_AD_PLL3DIV_PFD_0_DIV1LOCKED_SHIFT    (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked */
#define CGC_AD_PLL3DIV_PFD_0_DIV1LOCKED(x)       (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_0_DIV1LOCKED_SHIFT)) & CGC_AD_PLL3DIV_PFD_0_DIV1LOCKED_MASK)

#define CGC_AD_PLL3DIV_PFD_0_DIV1HALT_MASK       (0x80U)
#define CGC_AD_PLL3DIV_PFD_0_DIV1HALT_SHIFT      (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_AD_PLL3DIV_PFD_0_DIV1HALT(x)         (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_0_DIV1HALT_SHIFT)) & CGC_AD_PLL3DIV_PFD_0_DIV1HALT_MASK)

#define CGC_AD_PLL3DIV_PFD_0_DIV2_MASK           (0x3F00U)
#define CGC_AD_PLL3DIV_PFD_0_DIV2_SHIFT          (8U)
/*! DIV2 - Clock Division for PLL3 PFD0 Clock */
#define CGC_AD_PLL3DIV_PFD_0_DIV2(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_0_DIV2_SHIFT)) & CGC_AD_PLL3DIV_PFD_0_DIV2_MASK)

#define CGC_AD_PLL3DIV_PFD_0_DIV2LOCKED_MASK     (0x4000U)
#define CGC_AD_PLL3DIV_PFD_0_DIV2LOCKED_SHIFT    (14U)
/*! DIV2LOCKED - The value of clock division was changed and access to DIV2 is locked */
#define CGC_AD_PLL3DIV_PFD_0_DIV2LOCKED(x)       (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_0_DIV2LOCKED_SHIFT)) & CGC_AD_PLL3DIV_PFD_0_DIV2LOCKED_MASK)

#define CGC_AD_PLL3DIV_PFD_0_DIV2HALT_MASK       (0x8000U)
#define CGC_AD_PLL3DIV_PFD_0_DIV2HALT_SHIFT      (15U)
/*! DIV2HALT - Divider 2 Halted */
#define CGC_AD_PLL3DIV_PFD_0_DIV2HALT(x)         (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_0_DIV2HALT_SHIFT)) & CGC_AD_PLL3DIV_PFD_0_DIV2HALT_MASK)

#define CGC_AD_PLL3DIV_PFD_0_DIV3_MASK           (0x3F0000U)
#define CGC_AD_PLL3DIV_PFD_0_DIV3_SHIFT          (16U)
/*! DIV3 - Clock Division for PLL3 PFD1 Clock */
#define CGC_AD_PLL3DIV_PFD_0_DIV3(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_0_DIV3_SHIFT)) & CGC_AD_PLL3DIV_PFD_0_DIV3_MASK)

#define CGC_AD_PLL3DIV_PFD_0_DIV3LOCKED_MASK     (0x400000U)
#define CGC_AD_PLL3DIV_PFD_0_DIV3LOCKED_SHIFT    (22U)
/*! DIV3LOCKED - The value of clock division was changed and access to DIV3 is locked */
#define CGC_AD_PLL3DIV_PFD_0_DIV3LOCKED(x)       (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_0_DIV3LOCKED_SHIFT)) & CGC_AD_PLL3DIV_PFD_0_DIV3LOCKED_MASK)

#define CGC_AD_PLL3DIV_PFD_0_DIV3HALT_MASK       (0x800000U)
#define CGC_AD_PLL3DIV_PFD_0_DIV3HALT_SHIFT      (23U)
/*! DIV3HALT - Divider 3 Halted */
#define CGC_AD_PLL3DIV_PFD_0_DIV3HALT(x)         (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_0_DIV3HALT_SHIFT)) & CGC_AD_PLL3DIV_PFD_0_DIV3HALT_MASK)

#define CGC_AD_PLL3DIV_PFD_0_DIV4_MASK           (0x3F000000U)
#define CGC_AD_PLL3DIV_PFD_0_DIV4_SHIFT          (24U)
/*! DIV4 - Clock Division for PLL3 PFD1 Clock */
#define CGC_AD_PLL3DIV_PFD_0_DIV4(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_0_DIV4_SHIFT)) & CGC_AD_PLL3DIV_PFD_0_DIV4_MASK)

#define CGC_AD_PLL3DIV_PFD_0_DIV4LOCKED_MASK     (0x40000000U)
#define CGC_AD_PLL3DIV_PFD_0_DIV4LOCKED_SHIFT    (30U)
/*! DIV4LOCKED - The value of clock division was changed and access to DIV4 is locked */
#define CGC_AD_PLL3DIV_PFD_0_DIV4LOCKED(x)       (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_0_DIV4LOCKED_SHIFT)) & CGC_AD_PLL3DIV_PFD_0_DIV4LOCKED_MASK)

#define CGC_AD_PLL3DIV_PFD_0_DIV4HALT_MASK       (0x80000000U)
#define CGC_AD_PLL3DIV_PFD_0_DIV4HALT_SHIFT      (31U)
/*! DIV4HALT - Divider 4 Halted */
#define CGC_AD_PLL3DIV_PFD_0_DIV4HALT(x)         (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_0_DIV4HALT_SHIFT)) & CGC_AD_PLL3DIV_PFD_0_DIV4HALT_MASK)
/*! @} */

/*! @name PLL3DIV_PFD_1 - Clock Dividers for the fractional PLL3 */
/*! @{ */

#define CGC_AD_PLL3DIV_PFD_1_DIV1_MASK           (0x3FU)
#define CGC_AD_PLL3DIV_PFD_1_DIV1_SHIFT          (0U)
/*! DIV1 - Clock Division for PLL3 PFD2 Clock */
#define CGC_AD_PLL3DIV_PFD_1_DIV1(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_1_DIV1_SHIFT)) & CGC_AD_PLL3DIV_PFD_1_DIV1_MASK)

#define CGC_AD_PLL3DIV_PFD_1_DIV1LOCKED_MASK     (0x40U)
#define CGC_AD_PLL3DIV_PFD_1_DIV1LOCKED_SHIFT    (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked */
#define CGC_AD_PLL3DIV_PFD_1_DIV1LOCKED(x)       (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_1_DIV1LOCKED_SHIFT)) & CGC_AD_PLL3DIV_PFD_1_DIV1LOCKED_MASK)

#define CGC_AD_PLL3DIV_PFD_1_DIV1HALT_MASK       (0x80U)
#define CGC_AD_PLL3DIV_PFD_1_DIV1HALT_SHIFT      (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_AD_PLL3DIV_PFD_1_DIV1HALT(x)         (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_1_DIV1HALT_SHIFT)) & CGC_AD_PLL3DIV_PFD_1_DIV1HALT_MASK)

#define CGC_AD_PLL3DIV_PFD_1_DIV2_MASK           (0x3F00U)
#define CGC_AD_PLL3DIV_PFD_1_DIV2_SHIFT          (8U)
/*! DIV2 - Clock Division for PLL3 PFD2 Clock */
#define CGC_AD_PLL3DIV_PFD_1_DIV2(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_1_DIV2_SHIFT)) & CGC_AD_PLL3DIV_PFD_1_DIV2_MASK)

#define CGC_AD_PLL3DIV_PFD_1_DIV2LOCKED_MASK     (0x4000U)
#define CGC_AD_PLL3DIV_PFD_1_DIV2LOCKED_SHIFT    (14U)
/*! DIV2LOCKED - The value of clock division was changed and access to DIV2 is locked */
#define CGC_AD_PLL3DIV_PFD_1_DIV2LOCKED(x)       (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_1_DIV2LOCKED_SHIFT)) & CGC_AD_PLL3DIV_PFD_1_DIV2LOCKED_MASK)

#define CGC_AD_PLL3DIV_PFD_1_DIV2HALT_MASK       (0x8000U)
#define CGC_AD_PLL3DIV_PFD_1_DIV2HALT_SHIFT      (15U)
/*! DIV2HALT - Divider 2 Halted */
#define CGC_AD_PLL3DIV_PFD_1_DIV2HALT(x)         (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_1_DIV2HALT_SHIFT)) & CGC_AD_PLL3DIV_PFD_1_DIV2HALT_MASK)

#define CGC_AD_PLL3DIV_PFD_1_DIV3_MASK           (0x3F0000U)
#define CGC_AD_PLL3DIV_PFD_1_DIV3_SHIFT          (16U)
/*! DIV3 - Clock Division for PLL3 PFD3 Clock */
#define CGC_AD_PLL3DIV_PFD_1_DIV3(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_1_DIV3_SHIFT)) & CGC_AD_PLL3DIV_PFD_1_DIV3_MASK)

#define CGC_AD_PLL3DIV_PFD_1_DIV3LOCKED_MASK     (0x400000U)
#define CGC_AD_PLL3DIV_PFD_1_DIV3LOCKED_SHIFT    (22U)
/*! DIV3LOCKED - The value of clock division was changed and access to DIV3 is locked */
#define CGC_AD_PLL3DIV_PFD_1_DIV3LOCKED(x)       (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_1_DIV3LOCKED_SHIFT)) & CGC_AD_PLL3DIV_PFD_1_DIV3LOCKED_MASK)

#define CGC_AD_PLL3DIV_PFD_1_DIV3HALT_MASK       (0x800000U)
#define CGC_AD_PLL3DIV_PFD_1_DIV3HALT_SHIFT      (23U)
/*! DIV3HALT - Divider 3 Halted */
#define CGC_AD_PLL3DIV_PFD_1_DIV3HALT(x)         (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_1_DIV3HALT_SHIFT)) & CGC_AD_PLL3DIV_PFD_1_DIV3HALT_MASK)

#define CGC_AD_PLL3DIV_PFD_1_DIV4_MASK           (0x3F000000U)
#define CGC_AD_PLL3DIV_PFD_1_DIV4_SHIFT          (24U)
/*! DIV4 - Clock Division for PLL3 PFD3 Clock */
#define CGC_AD_PLL3DIV_PFD_1_DIV4(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_1_DIV4_SHIFT)) & CGC_AD_PLL3DIV_PFD_1_DIV4_MASK)

#define CGC_AD_PLL3DIV_PFD_1_DIV4LOCKED_MASK     (0x40000000U)
#define CGC_AD_PLL3DIV_PFD_1_DIV4LOCKED_SHIFT    (30U)
/*! DIV4LOCKED - The value of clock division was changed and access to DIV4 is locked */
#define CGC_AD_PLL3DIV_PFD_1_DIV4LOCKED(x)       (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_1_DIV4LOCKED_SHIFT)) & CGC_AD_PLL3DIV_PFD_1_DIV4LOCKED_MASK)

#define CGC_AD_PLL3DIV_PFD_1_DIV4HALT_MASK       (0x80000000U)
#define CGC_AD_PLL3DIV_PFD_1_DIV4HALT_SHIFT      (31U)
/*! DIV4HALT - Divider 4 Halted */
#define CGC_AD_PLL3DIV_PFD_1_DIV4HALT(x)         (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DIV_PFD_1_DIV4HALT_SHIFT)) & CGC_AD_PLL3DIV_PFD_1_DIV4HALT_MASK)
/*! @} */

/*! @name PLL3CFG - PLL3 Configuration Register */
/*! @{ */

#define CGC_AD_PLL3CFG_SOURCE_MASK               (0x1U)
#define CGC_AD_PLL3CFG_SOURCE_SHIFT              (0U)
/*! SOURCE - Clock Source */
#define CGC_AD_PLL3CFG_SOURCE(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CFG_SOURCE_SHIFT)) & CGC_AD_PLL3CFG_SOURCE_MASK)

#define CGC_AD_PLL3CFG_HALF_LR_R_MASK            (0x8U)
#define CGC_AD_PLL3CFG_HALF_LR_R_SHIFT           (3U)
/*! HALF_LR_R - HALF_LR_R */
#define CGC_AD_PLL3CFG_HALF_LR_R(x)              (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CFG_HALF_LR_R_SHIFT)) & CGC_AD_PLL3CFG_HALF_LR_R_MASK)

#define CGC_AD_PLL3CFG_HALF_CP_CURRENT_MASK      (0x10U)
#define CGC_AD_PLL3CFG_HALF_CP_CURRENT_SHIFT     (4U)
/*! HALF_CP_CURRENT - HALF_CP_CURRENT */
#define CGC_AD_PLL3CFG_HALF_CP_CURRENT(x)        (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CFG_HALF_CP_CURRENT_SHIFT)) & CGC_AD_PLL3CFG_HALF_CP_CURRENT_MASK)

#define CGC_AD_PLL3CFG_DOUBLE_LF_R_MASK          (0x20U)
#define CGC_AD_PLL3CFG_DOUBLE_LF_R_SHIFT         (5U)
/*! DOUBLE_LF_R - DOUBLE_LF_R */
#define CGC_AD_PLL3CFG_DOUBLE_LF_R(x)            (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CFG_DOUBLE_LF_R_SHIFT)) & CGC_AD_PLL3CFG_DOUBLE_LF_R_MASK)

#define CGC_AD_PLL3CFG_DOUBLE_CP_CURRENT_MASK    (0x40U)
#define CGC_AD_PLL3CFG_DOUBLE_CP_CURRENT_SHIFT   (6U)
/*! DOUBLE_CP_CURRENT - DOUBLE_CP_CURRENT */
#define CGC_AD_PLL3CFG_DOUBLE_CP_CURRENT(x)      (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CFG_DOUBLE_CP_CURRENT_SHIFT)) & CGC_AD_PLL3CFG_DOUBLE_CP_CURRENT_MASK)

#define CGC_AD_PLL3CFG_DITHER_EN_MASK            (0x800U)
#define CGC_AD_PLL3CFG_DITHER_EN_SHIFT           (11U)
/*! DITHER_EN - DITHER_EN */
#define CGC_AD_PLL3CFG_DITHER_EN(x)              (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CFG_DITHER_EN_SHIFT)) & CGC_AD_PLL3CFG_DITHER_EN_MASK)

#define CGC_AD_PLL3CFG_PFD_OFFSET_EN_MASK        (0x1000U)
#define CGC_AD_PLL3CFG_PFD_OFFSET_EN_SHIFT       (12U)
/*! PFD_OFFSET_EN - PFD_OFFSET_EN */
#define CGC_AD_PLL3CFG_PFD_OFFSET_EN(x)          (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CFG_PFD_OFFSET_EN_SHIFT)) & CGC_AD_PLL3CFG_PFD_OFFSET_EN_MASK)

#define CGC_AD_PLL3CFG_HOLDRING_OFF_MASK         (0x2000U)
#define CGC_AD_PLL3CFG_HOLDRING_OFF_SHIFT        (13U)
/*! HOLDRING_OFF - HOLDRING_OFF */
#define CGC_AD_PLL3CFG_HOLDRING_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CFG_HOLDRING_OFF_SHIFT)) & CGC_AD_PLL3CFG_HOLDRING_OFF_MASK)

#define CGC_AD_PLL3CFG_MULT_MASK                 (0x7F0000U)
#define CGC_AD_PLL3CFG_MULT_SHIFT                (16U)
/*! MULT - System PLL Multiplier */
#define CGC_AD_PLL3CFG_MULT(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3CFG_MULT_SHIFT)) & CGC_AD_PLL3CFG_MULT_MASK)
/*! @} */

/*! @name PLL3PFDCFG - PLL3 Configuration Register */
/*! @{ */

#define CGC_AD_PLL3PFDCFG_PFD0_MASK              (0x3FU)
#define CGC_AD_PLL3PFDCFG_PFD0_SHIFT             (0U)
/*! PFD0 - PLL Fractional Divider 0 */
#define CGC_AD_PLL3PFDCFG_PFD0(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3PFDCFG_PFD0_SHIFT)) & CGC_AD_PLL3PFDCFG_PFD0_MASK)

#define CGC_AD_PLL3PFDCFG_PFD0_VALID_MASK        (0x40U)
#define CGC_AD_PLL3PFDCFG_PFD0_VALID_SHIFT       (6U)
/*! PFD0_VALID - PFD0_VALID */
#define CGC_AD_PLL3PFDCFG_PFD0_VALID(x)          (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3PFDCFG_PFD0_VALID_SHIFT)) & CGC_AD_PLL3PFDCFG_PFD0_VALID_MASK)

#define CGC_AD_PLL3PFDCFG_PFD0_CLKGATE_MASK      (0x80U)
#define CGC_AD_PLL3PFDCFG_PFD0_CLKGATE_SHIFT     (7U)
/*! PFD0_CLKGATE - Clock gate of PFD0 */
#define CGC_AD_PLL3PFDCFG_PFD0_CLKGATE(x)        (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3PFDCFG_PFD0_CLKGATE_SHIFT)) & CGC_AD_PLL3PFDCFG_PFD0_CLKGATE_MASK)

#define CGC_AD_PLL3PFDCFG_PFD1_MASK              (0x3F00U)
#define CGC_AD_PLL3PFDCFG_PFD1_SHIFT             (8U)
/*! PFD1 - PLL Fractional Divider 1 */
#define CGC_AD_PLL3PFDCFG_PFD1(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3PFDCFG_PFD1_SHIFT)) & CGC_AD_PLL3PFDCFG_PFD1_MASK)

#define CGC_AD_PLL3PFDCFG_PFD1_VALID_MASK        (0x4000U)
#define CGC_AD_PLL3PFDCFG_PFD1_VALID_SHIFT       (14U)
/*! PFD1_VALID - PFD1_VALID */
#define CGC_AD_PLL3PFDCFG_PFD1_VALID(x)          (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3PFDCFG_PFD1_VALID_SHIFT)) & CGC_AD_PLL3PFDCFG_PFD1_VALID_MASK)

#define CGC_AD_PLL3PFDCFG_PFD1_CLKGATE_MASK      (0x8000U)
#define CGC_AD_PLL3PFDCFG_PFD1_CLKGATE_SHIFT     (15U)
/*! PFD1_CLKGATE - Clock gate of PFD1 */
#define CGC_AD_PLL3PFDCFG_PFD1_CLKGATE(x)        (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3PFDCFG_PFD1_CLKGATE_SHIFT)) & CGC_AD_PLL3PFDCFG_PFD1_CLKGATE_MASK)

#define CGC_AD_PLL3PFDCFG_PFD2_MASK              (0x3F0000U)
#define CGC_AD_PLL3PFDCFG_PFD2_SHIFT             (16U)
/*! PFD2 - PLL Fractional Divider 2 */
#define CGC_AD_PLL3PFDCFG_PFD2(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3PFDCFG_PFD2_SHIFT)) & CGC_AD_PLL3PFDCFG_PFD2_MASK)

#define CGC_AD_PLL3PFDCFG_PFD2_VALID_MASK        (0x400000U)
#define CGC_AD_PLL3PFDCFG_PFD2_VALID_SHIFT       (22U)
/*! PFD2_VALID - PFD2_VALID */
#define CGC_AD_PLL3PFDCFG_PFD2_VALID(x)          (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3PFDCFG_PFD2_VALID_SHIFT)) & CGC_AD_PLL3PFDCFG_PFD2_VALID_MASK)

#define CGC_AD_PLL3PFDCFG_PFD2_CLKGATE_MASK      (0x800000U)
#define CGC_AD_PLL3PFDCFG_PFD2_CLKGATE_SHIFT     (23U)
/*! PFD2_CLKGATE - Clock gate of PFD2 */
#define CGC_AD_PLL3PFDCFG_PFD2_CLKGATE(x)        (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3PFDCFG_PFD2_CLKGATE_SHIFT)) & CGC_AD_PLL3PFDCFG_PFD2_CLKGATE_MASK)

#define CGC_AD_PLL3PFDCFG_PFD3_MASK              (0x3F000000U)
#define CGC_AD_PLL3PFDCFG_PFD3_SHIFT             (24U)
/*! PFD3 - PLL Fractional Divider 3 */
#define CGC_AD_PLL3PFDCFG_PFD3(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3PFDCFG_PFD3_SHIFT)) & CGC_AD_PLL3PFDCFG_PFD3_MASK)

#define CGC_AD_PLL3PFDCFG_PFD3_VALID_MASK        (0x40000000U)
#define CGC_AD_PLL3PFDCFG_PFD3_VALID_SHIFT       (30U)
/*! PFD3_VALID - PFD3_VALID */
#define CGC_AD_PLL3PFDCFG_PFD3_VALID(x)          (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3PFDCFG_PFD3_VALID_SHIFT)) & CGC_AD_PLL3PFDCFG_PFD3_VALID_MASK)

#define CGC_AD_PLL3PFDCFG_PFD3_CLKGATE_MASK      (0x80000000U)
#define CGC_AD_PLL3PFDCFG_PFD3_CLKGATE_SHIFT     (31U)
/*! PFD3_CLKGATE - Clock gate of PFD3 */
#define CGC_AD_PLL3PFDCFG_PFD3_CLKGATE(x)        (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3PFDCFG_PFD3_CLKGATE_SHIFT)) & CGC_AD_PLL3PFDCFG_PFD3_CLKGATE_MASK)
/*! @} */

/*! @name PLL3DENOM - PLL3 Denominator Register */
/*! @{ */

#define CGC_AD_PLL3DENOM_DENOM_MASK              (0x3FFFFFFFU)
#define CGC_AD_PLL3DENOM_DENOM_SHIFT             (0U)
/*! DENOM - PLL Denominator Register */
#define CGC_AD_PLL3DENOM_DENOM(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3DENOM_DENOM_SHIFT)) & CGC_AD_PLL3DENOM_DENOM_MASK)
/*! @} */

/*! @name PLL3NUM - PLL3 Numerator Register */
/*! @{ */

#define CGC_AD_PLL3NUM_NUM_MASK                  (0x3FFFFFFFU)
#define CGC_AD_PLL3NUM_NUM_SHIFT                 (0U)
/*! NUM - PLL Numerator Register */
#define CGC_AD_PLL3NUM_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3NUM_NUM_SHIFT)) & CGC_AD_PLL3NUM_NUM_MASK)
/*! @} */

/*! @name PLL3SS - PLL3 Spread Spectrum Register */
/*! @{ */

#define CGC_AD_PLL3SS_STEP_MASK                  (0x7FFFU)
#define CGC_AD_PLL3SS_STEP_SHIFT                 (0U)
/*! STEP - STEP */
#define CGC_AD_PLL3SS_STEP(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3SS_STEP_SHIFT)) & CGC_AD_PLL3SS_STEP_MASK)

#define CGC_AD_PLL3SS_ENABLE_MASK                (0x8000U)
#define CGC_AD_PLL3SS_ENABLE_SHIFT               (15U)
/*! ENABLE - ENABLE */
#define CGC_AD_PLL3SS_ENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3SS_ENABLE_SHIFT)) & CGC_AD_PLL3SS_ENABLE_MASK)

#define CGC_AD_PLL3SS_STOP_MASK                  (0xFFFF0000U)
#define CGC_AD_PLL3SS_STOP_SHIFT                 (16U)
/*! STOP - STOP */
#define CGC_AD_PLL3SS_STOP(x)                    (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3SS_STOP_SHIFT)) & CGC_AD_PLL3SS_STOP_MASK)
/*! @} */

/*! @name PLL3LOCK - PLL3 LOCK Configuration Register */
/*! @{ */

#define CGC_AD_PLL3LOCK_LOCK_TIME_MASK           (0xFFFFU)
#define CGC_AD_PLL3LOCK_LOCK_TIME_SHIFT          (0U)
/*! LOCK_TIME - LOCK_TIME */
#define CGC_AD_PLL3LOCK_LOCK_TIME(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLL3LOCK_LOCK_TIME_SHIFT)) & CGC_AD_PLL3LOCK_LOCK_TIME_MASK)
/*! @} */

/*! @name ENETSTAMP - Clock Selection for Ethernet Time Stamp */
/*! @{ */

#define CGC_AD_ENETSTAMP_CLKOUT_SEL_MASK         (0x7000000U)
#define CGC_AD_ENETSTAMP_CLKOUT_SEL_SHIFT        (24U)
/*! CLKOUT_SEL - Selection of clock source used for Ethernet time stamp. */
#define CGC_AD_ENETSTAMP_CLKOUT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CGC_AD_ENETSTAMP_CLKOUT_SEL_SHIFT)) & CGC_AD_ENETSTAMP_CLKOUT_SEL_MASK)
/*! @} */

/*! @name PLLUSBCFG - PLLUSB Register Enable */
/*! @{ */

#define CGC_AD_PLLUSBCFG_SOURCE_MASK             (0x1U)
#define CGC_AD_PLLUSBCFG_SOURCE_SHIFT            (0U)
/*! SOURCE - Clock Source */
#define CGC_AD_PLLUSBCFG_SOURCE(x)               (((uint32_t)(((uint32_t)(x)) << CGC_AD_PLLUSBCFG_SOURCE_SHIFT)) & CGC_AD_PLLUSBCFG_SOURCE_MASK)
/*! @} */

/*! @name AUD_CLK1 - AUD_CLK1 source to SAI4-5 */
/*! @{ */

#define CGC_AD_AUD_CLK1_AUD_CLK1_MASK            (0x7U)
#define CGC_AD_AUD_CLK1_AUD_CLK1_SHIFT           (0U)
/*! AUD_CLK1 - AUD_CLK1 Clock Source Selection */
#define CGC_AD_AUD_CLK1_AUD_CLK1(x)              (((uint32_t)(((uint32_t)(x)) << CGC_AD_AUD_CLK1_AUD_CLK1_SHIFT)) & CGC_AD_AUD_CLK1_AUD_CLK1_MASK)
/*! @} */

/*! @name SAI5_4_CLK - SAI5-4 Clock Source Selection */
/*! @{ */

#define CGC_AD_SAI5_4_CLK_SAI4CLK_MASK           (0x3U)
#define CGC_AD_SAI5_4_CLK_SAI4CLK_SHIFT          (0U)
/*! SAI4CLK - Clock Source for SAI4 */
#define CGC_AD_SAI5_4_CLK_SAI4CLK(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_SAI5_4_CLK_SAI4CLK_SHIFT)) & CGC_AD_SAI5_4_CLK_SAI4CLK_MASK)

#define CGC_AD_SAI5_4_CLK_SAI5CLK_MASK           (0x300U)
#define CGC_AD_SAI5_4_CLK_SAI5CLK_SHIFT          (8U)
/*! SAI5CLK - Clock Source for SAI5 */
#define CGC_AD_SAI5_4_CLK_SAI5CLK(x)             (((uint32_t)(((uint32_t)(x)) << CGC_AD_SAI5_4_CLK_SAI5CLK_SHIFT)) & CGC_AD_SAI5_4_CLK_SAI5CLK_MASK)
/*! @} */

/*! @name TPM6_7CLK - Multiplexer to select the audio clock connected to the TPM clock input */
/*! @{ */

#define CGC_AD_TPM6_7CLK_TPM6CLK_MASK            (0x3U)
#define CGC_AD_TPM6_7CLK_TPM6CLK_SHIFT           (0U)
/*! TPM6CLK - Clock Selection for TPM6 */
#define CGC_AD_TPM6_7CLK_TPM6CLK(x)              (((uint32_t)(((uint32_t)(x)) << CGC_AD_TPM6_7CLK_TPM6CLK_SHIFT)) & CGC_AD_TPM6_7CLK_TPM6CLK_MASK)

#define CGC_AD_TPM6_7CLK_TPM7CLK_MASK            (0x300U)
#define CGC_AD_TPM6_7CLK_TPM7CLK_SHIFT           (8U)
/*! TPM7CLK - Clock Selection for TPM7 */
#define CGC_AD_TPM6_7CLK_TPM7CLK(x)              (((uint32_t)(((uint32_t)(x)) << CGC_AD_TPM6_7CLK_TPM7CLK_SHIFT)) & CGC_AD_TPM6_7CLK_TPM7CLK_MASK)
/*! @} */

/*! @name MQS1CLK - Multiplexer to select the audio clock connected to the MQS clock input */
/*! @{ */

#define CGC_AD_MQS1CLK_MQS1CLK_MASK              (0x3U)
#define CGC_AD_MQS1CLK_MQS1CLK_SHIFT             (0U)
/*! MQS1CLK - Clock Selection for MQS1 */
#define CGC_AD_MQS1CLK_MQS1CLK(x)                (((uint32_t)(((uint32_t)(x)) << CGC_AD_MQS1CLK_MQS1CLK_SHIFT)) & CGC_AD_MQS1CLK_MQS1CLK_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CGC_AD_Register_Masks */


/* CGC_AD - Peripheral instance base addresses */
/** Peripheral CGC_AD base address */
#define CGC_AD_BASE                              (0x292C0000u)
/** Peripheral CGC_AD base pointer */
#define CGC_AD                                   ((CGC_AD_Type *)CGC_AD_BASE)
/** Array initializer of CGC_AD peripheral base addresses */
#define CGC_AD_BASE_ADDRS                        { CGC_AD_BASE }
/** Array initializer of CGC_AD peripheral base pointers */
#define CGC_AD_BASE_PTRS                         { CGC_AD }

/*!
 * @}
 */ /* end of group CGC_AD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CGC_LPAV Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CGC_LPAV_Peripheral_Access_Layer CGC_LPAV Peripheral Access Layer
 * @{
 */

/** CGC_LPAV - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
       uint8_t RESERVED_0[16];
  __IO uint32_t HIFICLK;                           /**< Clock Selection and Dividers for the HIFI Domain, offset: 0x14 */
       uint8_t RESERVED_1[8];
  __IO uint32_t CLKOUTCFG;                         /**< Clockout selection for LPAV Domain, offset: 0x20 */
       uint8_t RESERVED_2[24];
  __IO uint32_t NICLPAVCLK;                        /**< Clock Selection and Dividers for the HIFI Domain, offset: 0x3C */
  __IO uint32_t DDRCLK;                            /**< Clock Selection and Dividers for the DDR Domain, offset: 0x40 */
       uint8_t RESERVED_3[76];
  __IO uint32_t CLKDIVRST;                         /**< Clk Dividers Reset, offset: 0x90 */
       uint8_t RESERVED_4[116];
  __IO uint32_t SOSCDIV;                           /**< Clock Dividers for the SOSC CLK, offset: 0x108 */
       uint8_t RESERVED_5[252];
  __IO uint32_t FRODIV;                            /**< Clock Dividers for the FRO, offset: 0x208 */
       uint8_t RESERVED_6[1012];
  __IO uint32_t PLL4CSR;                           /**< PLL Control Status Register, offset: 0x600 */
  __IO uint32_t PLL4DIV_VCO;                       /**< Clock Dividers for the fractional PLL4, offset: 0x604 */
  __IO uint32_t PLL4DIV_PFD_0;                     /**< Clock Dividers for the fractional PLL4, offset: 0x608 */
  __IO uint32_t PLL4DIV_PFD_1;                     /**< Clock Dividers for the fractional PLL4, offset: 0x60C */
  __IO uint32_t PLL4CFG;                           /**< PLL4 Configuration Register, offset: 0x610 */
  __IO uint32_t PLL4PFDCFG;                        /**< PLL4 Configuration Register, offset: 0x614 */
  __IO uint32_t PLL4DENOM;                         /**< PLL Denominator Register, offset: 0x618 */
  __IO uint32_t PLL4NUM;                           /**< PLL Numerator Register, offset: 0x61C */
  __IO uint32_t PLL4SS;                            /**< PLL Spread Spectrum Register, offset: 0x620 */
  __IO uint32_t PLL4LOCK;                          /**< PLL LOCK Configuration Register, offset: 0x624 */
       uint8_t RESERVED_7[728];
  __IO uint32_t AUD_CLK2;                          /**< AUD_CLK2 source to SAI7-6, offset: 0x900 */
  __IO uint32_t SAI7_6_CLK;                        /**< SAI7-6 Clock Source Selection, offset: 0x904 */
  __IO uint32_t TPM8CLK;                           /**< Multiplexer to select the audio clock connected to the TPM clock input, offset: 0x908 */
       uint8_t RESERVED_8[4];
  __IO uint32_t SPDIFCLK;                          /**< Multiplexer to select the audio clock connected to the SPDIF clock input, offset: 0x910 */
} CGC_LPAV_Type;

/* ----------------------------------------------------------------------------
   -- CGC_LPAV Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CGC_LPAV_Register_Masks CGC_LPAV Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define CGC_LPAV_VERID_FEATURE_MASK              (0xFFFFU)
#define CGC_LPAV_VERID_FEATURE_SHIFT             (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000010..Master only with standard feature set.
 *  0b0000000000000011..Master and slave with standard feature set.
 */
#define CGC_LPAV_VERID_FEATURE(x)                (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_VERID_FEATURE_SHIFT)) & CGC_LPAV_VERID_FEATURE_MASK)

#define CGC_LPAV_VERID_MINOR_MASK                (0xFF0000U)
#define CGC_LPAV_VERID_MINOR_SHIFT               (16U)
/*! MINOR - Minor Version Number */
#define CGC_LPAV_VERID_MINOR(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_VERID_MINOR_SHIFT)) & CGC_LPAV_VERID_MINOR_MASK)

#define CGC_LPAV_VERID_MAJOR_MASK                (0xFF000000U)
#define CGC_LPAV_VERID_MAJOR_SHIFT               (24U)
/*! MAJOR - Major Version Number */
#define CGC_LPAV_VERID_MAJOR(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_VERID_MAJOR_SHIFT)) & CGC_LPAV_VERID_MAJOR_MASK)
/*! @} */

/*! @name HIFICLK - Clock Selection and Dividers for the HIFI Domain */
/*! @{ */

#define CGC_LPAV_HIFICLK_NIC_HIFI_DIVPLAT_MASK   (0xFC000U)
#define CGC_LPAV_HIFICLK_NIC_HIFI_DIVPLAT_SHIFT  (14U)
/*! NIC_HIFI_DIVPLAT - Clock Division for Platform Clock */
#define CGC_LPAV_HIFICLK_NIC_HIFI_DIVPLAT(x)     (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_HIFICLK_NIC_HIFI_DIVPLAT_SHIFT)) & CGC_LPAV_HIFICLK_NIC_HIFI_DIVPLAT_MASK)

#define CGC_LPAV_HIFICLK_HIFI_DIVCORE_MASK       (0x7E00000U)
#define CGC_LPAV_HIFICLK_HIFI_DIVCORE_SHIFT      (21U)
/*! HIFI_DIVCORE - Clock Division for Core Clock */
#define CGC_LPAV_HIFICLK_HIFI_DIVCORE(x)         (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_HIFICLK_HIFI_DIVCORE_SHIFT)) & CGC_LPAV_HIFICLK_HIFI_DIVCORE_MASK)

#define CGC_LPAV_HIFICLK_SCSW_MASK               (0x8000000U)
#define CGC_LPAV_HIFICLK_SCSW_SHIFT              (27U)
/*! SCSW - Clock switched to selected clock source */
#define CGC_LPAV_HIFICLK_SCSW(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_HIFICLK_SCSW_SHIFT)) & CGC_LPAV_HIFICLK_SCSW_MASK)

#define CGC_LPAV_HIFICLK_SCS_MASK                (0x70000000U)
#define CGC_LPAV_HIFICLK_SCS_SHIFT               (28U)
/*! SCS - Clock Selection for HIFI Domain */
#define CGC_LPAV_HIFICLK_SCS(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_HIFICLK_SCS_SHIFT)) & CGC_LPAV_HIFICLK_SCS_MASK)

#define CGC_LPAV_HIFICLK_HIFILOCKED_MASK         (0x80000000U)
#define CGC_LPAV_HIFICLK_HIFILOCKED_SHIFT        (31U)
/*! HIFILOCKED - HIFICLK Register Locked */
#define CGC_LPAV_HIFICLK_HIFILOCKED(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_HIFICLK_HIFILOCKED_SHIFT)) & CGC_LPAV_HIFICLK_HIFILOCKED_MASK)
/*! @} */

/*! @name CLKOUTCFG - Clockout selection for LPAV Domain */
/*! @{ */

#define CGC_LPAV_CLKOUTCFG_CLKOUT_DIV_MASK       (0x7E0000U)
#define CGC_LPAV_CLKOUTCFG_CLKOUT_DIV_SHIFT      (17U)
/*! CLKOUT_DIV - Select the clock division for the CLKOUT pin */
#define CGC_LPAV_CLKOUTCFG_CLKOUT_DIV(x)         (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_CLKOUTCFG_CLKOUT_DIV_SHIFT)) & CGC_LPAV_CLKOUTCFG_CLKOUT_DIV_MASK)

#define CGC_LPAV_CLKOUTCFG_CLKOUT_SEL_MASK       (0x7800000U)
#define CGC_LPAV_CLKOUTCFG_CLKOUT_SEL_SHIFT      (23U)
/*! CLKOUT_SEL - Select the clock source redirected to CLKOUT pin */
#define CGC_LPAV_CLKOUTCFG_CLKOUT_SEL(x)         (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_CLKOUTCFG_CLKOUT_SEL_SHIFT)) & CGC_LPAV_CLKOUTCFG_CLKOUT_SEL_MASK)

#define CGC_LPAV_CLKOUTCFG_CLKOUT_EN_MASK        (0x10000000U)
#define CGC_LPAV_CLKOUTCFG_CLKOUT_EN_SHIFT       (28U)
/*! CLKOUT_EN - Clockout Enable */
#define CGC_LPAV_CLKOUTCFG_CLKOUT_EN(x)          (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_CLKOUTCFG_CLKOUT_EN_SHIFT)) & CGC_LPAV_CLKOUTCFG_CLKOUT_EN_MASK)
/*! @} */

/*! @name NICLPAVCLK - Clock Selection and Dividers for the HIFI Domain */
/*! @{ */

#define CGC_LPAV_NICLPAVCLK_LPAV_BUS_CLK_MASK    (0x780U)
#define CGC_LPAV_NICLPAVCLK_LPAV_BUS_CLK_SHIFT   (7U)
/*! LPAV_BUS_CLK - Clock Division for Bus Clk */
#define CGC_LPAV_NICLPAVCLK_LPAV_BUS_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_NICLPAVCLK_LPAV_BUS_CLK_SHIFT)) & CGC_LPAV_NICLPAVCLK_LPAV_BUS_CLK_MASK)

#define CGC_LPAV_NICLPAVCLK_LPAV_AHB_CLK_MASK    (0x3C000U)
#define CGC_LPAV_NICLPAVCLK_LPAV_AHB_CLK_SHIFT   (14U)
/*! LPAV_AHB_CLK - Clock Division for AHB Clock */
#define CGC_LPAV_NICLPAVCLK_LPAV_AHB_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_NICLPAVCLK_LPAV_AHB_CLK_SHIFT)) & CGC_LPAV_NICLPAVCLK_LPAV_AHB_CLK_MASK)

#define CGC_LPAV_NICLPAVCLK_LPAV_AXI_CLK_MASK    (0x1E00000U)
#define CGC_LPAV_NICLPAVCLK_LPAV_AXI_CLK_SHIFT   (21U)
/*! LPAV_AXI_CLK - Clock Division for AXI Clock */
#define CGC_LPAV_NICLPAVCLK_LPAV_AXI_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_NICLPAVCLK_LPAV_AXI_CLK_SHIFT)) & CGC_LPAV_NICLPAVCLK_LPAV_AXI_CLK_MASK)

#define CGC_LPAV_NICLPAVCLK_SCSW_MASK            (0x8000000U)
#define CGC_LPAV_NICLPAVCLK_SCSW_SHIFT           (27U)
/*! SCSW - Clock switched to selected clock source */
#define CGC_LPAV_NICLPAVCLK_SCSW(x)              (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_NICLPAVCLK_SCSW_SHIFT)) & CGC_LPAV_NICLPAVCLK_SCSW_MASK)

#define CGC_LPAV_NICLPAVCLK_SCS_MASK             (0x30000000U)
#define CGC_LPAV_NICLPAVCLK_SCS_SHIFT            (28U)
/*! SCS - Clock Selection for HIFI domain */
#define CGC_LPAV_NICLPAVCLK_SCS(x)               (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_NICLPAVCLK_SCS_SHIFT)) & CGC_LPAV_NICLPAVCLK_SCS_MASK)

#define CGC_LPAV_NICLPAVCLK_NICLOCKED_MASK       (0x80000000U)
#define CGC_LPAV_NICLPAVCLK_NICLOCKED_SHIFT      (31U)
/*! NICLOCKED - NIC CLK Register Locked */
#define CGC_LPAV_NICLPAVCLK_NICLOCKED(x)         (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_NICLPAVCLK_NICLOCKED_SHIFT)) & CGC_LPAV_NICLPAVCLK_NICLOCKED_MASK)
/*! @} */

/*! @name DDRCLK - Clock Selection and Dividers for the DDR Domain */
/*! @{ */

#define CGC_LPAV_DDRCLK_DDR_DIV_MASK             (0x7E00000U)
#define CGC_LPAV_DDRCLK_DDR_DIV_SHIFT            (21U)
/*! DDR_DIV - Clock Division for DDR Clock */
#define CGC_LPAV_DDRCLK_DDR_DIV(x)               (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_DDRCLK_DDR_DIV_SHIFT)) & CGC_LPAV_DDRCLK_DDR_DIV_MASK)

#define CGC_LPAV_DDRCLK_SCSW_MASK                (0x8000000U)
#define CGC_LPAV_DDRCLK_SCSW_SHIFT               (27U)
/*! SCSW - Clock switched to selected clock source */
#define CGC_LPAV_DDRCLK_SCSW(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_DDRCLK_SCSW_SHIFT)) & CGC_LPAV_DDRCLK_SCSW_MASK)

#define CGC_LPAV_DDRCLK_SCS_MASK                 (0x70000000U)
#define CGC_LPAV_DDRCLK_SCS_SHIFT                (28U)
/*! SCS - Clock Selection for DDR Clock */
#define CGC_LPAV_DDRCLK_SCS(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_DDRCLK_SCS_SHIFT)) & CGC_LPAV_DDRCLK_SCS_MASK)

#define CGC_LPAV_DDRCLK_DDRLOCKED_MASK           (0x80000000U)
#define CGC_LPAV_DDRCLK_DDRLOCKED_SHIFT          (31U)
/*! DDRLOCKED - DDR CLK Register Locked */
#define CGC_LPAV_DDRCLK_DDRLOCKED(x)             (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_DDRCLK_DDRLOCKED_SHIFT)) & CGC_LPAV_DDRCLK_DDRLOCKED_MASK)
/*! @} */

/*! @name CLKDIVRST - Clk Dividers Reset */
/*! @{ */

#define CGC_LPAV_CLKDIVRST_NICLPAV_OUT_OF_PHASE_MASK (0x1U)
#define CGC_LPAV_CLKDIVRST_NICLPAV_OUT_OF_PHASE_SHIFT (0U)
/*! NICLPAV_OUT_OF_PHASE - NIC clocks dividers reset */
#define CGC_LPAV_CLKDIVRST_NICLPAV_OUT_OF_PHASE(x) (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_CLKDIVRST_NICLPAV_OUT_OF_PHASE_SHIFT)) & CGC_LPAV_CLKDIVRST_NICLPAV_OUT_OF_PHASE_MASK)

#define CGC_LPAV_CLKDIVRST_NICLPAV_RST_DIVIDERS_EN_MASK (0x2U)
#define CGC_LPAV_CLKDIVRST_NICLPAV_RST_DIVIDERS_EN_SHIFT (1U)
/*! NICLPAV_RST_DIVIDERS_EN - NIC clocks dividers out of phase interrupt */
#define CGC_LPAV_CLKDIVRST_NICLPAV_RST_DIVIDERS_EN(x) (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_CLKDIVRST_NICLPAV_RST_DIVIDERS_EN_SHIFT)) & CGC_LPAV_CLKDIVRST_NICLPAV_RST_DIVIDERS_EN_MASK)

#define CGC_LPAV_CLKDIVRST_NICLPAV_INTERRUPT_EN_MASK (0x4U)
#define CGC_LPAV_CLKDIVRST_NICLPAV_INTERRUPT_EN_SHIFT (2U)
/*! NICLPAV_INTERRUPT_EN - Selection between interrupt generation or clock dividers reset when nic clocks are out of phase */
#define CGC_LPAV_CLKDIVRST_NICLPAV_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_CLKDIVRST_NICLPAV_INTERRUPT_EN_SHIFT)) & CGC_LPAV_CLKDIVRST_NICLPAV_INTERRUPT_EN_MASK)

#define CGC_LPAV_CLKDIVRST_NICLPAV_RESET_EN_MASK (0x8U)
#define CGC_LPAV_CLKDIVRST_NICLPAV_RESET_EN_SHIFT (3U)
#define CGC_LPAV_CLKDIVRST_NICLPAV_RESET_EN(x)   (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_CLKDIVRST_NICLPAV_RESET_EN_SHIFT)) & CGC_LPAV_CLKDIVRST_NICLPAV_RESET_EN_MASK)

#define CGC_LPAV_CLKDIVRST_HIFI_OUT_OF_PHASE_MASK (0x10000U)
#define CGC_LPAV_CLKDIVRST_HIFI_OUT_OF_PHASE_SHIFT (16U)
/*! HIFI_OUT_OF_PHASE - HIFI4 clocks dividers reset */
#define CGC_LPAV_CLKDIVRST_HIFI_OUT_OF_PHASE(x)  (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_CLKDIVRST_HIFI_OUT_OF_PHASE_SHIFT)) & CGC_LPAV_CLKDIVRST_HIFI_OUT_OF_PHASE_MASK)

#define CGC_LPAV_CLKDIVRST_HIFI_RST_DIVIDERS_EN_MASK (0x20000U)
#define CGC_LPAV_CLKDIVRST_HIFI_RST_DIVIDERS_EN_SHIFT (17U)
/*! HIFI_RST_DIVIDERS_EN - HIFI4 clocks dividers out of phase interrupt */
#define CGC_LPAV_CLKDIVRST_HIFI_RST_DIVIDERS_EN(x) (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_CLKDIVRST_HIFI_RST_DIVIDERS_EN_SHIFT)) & CGC_LPAV_CLKDIVRST_HIFI_RST_DIVIDERS_EN_MASK)

#define CGC_LPAV_CLKDIVRST_HIFI_INTERRUPT_EN_MASK (0x40000U)
#define CGC_LPAV_CLKDIVRST_HIFI_INTERRUPT_EN_SHIFT (18U)
/*! HIFI_INTERRUPT_EN - Selection between interrupt generation or clock dividers reset when hifi4 clocks are out of phase */
#define CGC_LPAV_CLKDIVRST_HIFI_INTERRUPT_EN(x)  (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_CLKDIVRST_HIFI_INTERRUPT_EN_SHIFT)) & CGC_LPAV_CLKDIVRST_HIFI_INTERRUPT_EN_MASK)

#define CGC_LPAV_CLKDIVRST_HIFI_RESET_EN_MASK    (0x80000U)
#define CGC_LPAV_CLKDIVRST_HIFI_RESET_EN_SHIFT   (19U)
#define CGC_LPAV_CLKDIVRST_HIFI_RESET_EN(x)      (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_CLKDIVRST_HIFI_RESET_EN_SHIFT)) & CGC_LPAV_CLKDIVRST_HIFI_RESET_EN_MASK)
/*! @} */

/*! @name SOSCDIV - Clock Dividers for the SOSC CLK */
/*! @{ */

#define CGC_LPAV_SOSCDIV_DIV1_MASK               (0x3FU)
#define CGC_LPAV_SOSCDIV_DIV1_SHIFT              (0U)
/*! DIV1 - Clock Division for Slow Clock */
#define CGC_LPAV_SOSCDIV_DIV1(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_SOSCDIV_DIV1_SHIFT)) & CGC_LPAV_SOSCDIV_DIV1_MASK)

#define CGC_LPAV_SOSCDIV_DIV1LOCKED_MASK         (0x40U)
#define CGC_LPAV_SOSCDIV_DIV1LOCKED_SHIFT        (6U)
/*! DIV1LOCKED - Write to DIV1 Locked */
#define CGC_LPAV_SOSCDIV_DIV1LOCKED(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_SOSCDIV_DIV1LOCKED_SHIFT)) & CGC_LPAV_SOSCDIV_DIV1LOCKED_MASK)

#define CGC_LPAV_SOSCDIV_DIV1HALT_MASK           (0x80U)
#define CGC_LPAV_SOSCDIV_DIV1HALT_SHIFT          (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_LPAV_SOSCDIV_DIV1HALT(x)             (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_SOSCDIV_DIV1HALT_SHIFT)) & CGC_LPAV_SOSCDIV_DIV1HALT_MASK)

#define CGC_LPAV_SOSCDIV_DIV2_MASK               (0x3F00U)
#define CGC_LPAV_SOSCDIV_DIV2_SHIFT              (8U)
/*! DIV2 - Clock Division for Bus Clock */
#define CGC_LPAV_SOSCDIV_DIV2(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_SOSCDIV_DIV2_SHIFT)) & CGC_LPAV_SOSCDIV_DIV2_MASK)

#define CGC_LPAV_SOSCDIV_DIV2LOCKED_MASK         (0x4000U)
#define CGC_LPAV_SOSCDIV_DIV2LOCKED_SHIFT        (14U)
/*! DIV2LOCKED - Write to DIV2 Locked */
#define CGC_LPAV_SOSCDIV_DIV2LOCKED(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_SOSCDIV_DIV2LOCKED_SHIFT)) & CGC_LPAV_SOSCDIV_DIV2LOCKED_MASK)

#define CGC_LPAV_SOSCDIV_DIV2HALT_MASK           (0x8000U)
#define CGC_LPAV_SOSCDIV_DIV2HALT_SHIFT          (15U)
/*! DIV2HALT - Divider 2 Halted */
#define CGC_LPAV_SOSCDIV_DIV2HALT(x)             (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_SOSCDIV_DIV2HALT_SHIFT)) & CGC_LPAV_SOSCDIV_DIV2HALT_MASK)

#define CGC_LPAV_SOSCDIV_DIV3_MASK               (0x3F0000U)
#define CGC_LPAV_SOSCDIV_DIV3_SHIFT              (16U)
/*! DIV3 - Clock Division for Platform Clock */
#define CGC_LPAV_SOSCDIV_DIV3(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_SOSCDIV_DIV3_SHIFT)) & CGC_LPAV_SOSCDIV_DIV3_MASK)

#define CGC_LPAV_SOSCDIV_DIV3LOCKED_MASK         (0x400000U)
#define CGC_LPAV_SOSCDIV_DIV3LOCKED_SHIFT        (22U)
/*! DIV3LOCKED - Write to DIV3 Locked */
#define CGC_LPAV_SOSCDIV_DIV3LOCKED(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_SOSCDIV_DIV3LOCKED_SHIFT)) & CGC_LPAV_SOSCDIV_DIV3LOCKED_MASK)

#define CGC_LPAV_SOSCDIV_DIV3HALT_MASK           (0x800000U)
#define CGC_LPAV_SOSCDIV_DIV3HALT_SHIFT          (23U)
/*! DIV3HALT - Divider 3 Halted */
#define CGC_LPAV_SOSCDIV_DIV3HALT(x)             (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_SOSCDIV_DIV3HALT_SHIFT)) & CGC_LPAV_SOSCDIV_DIV3HALT_MASK)
/*! @} */

/*! @name FRODIV - Clock Dividers for the FRO */
/*! @{ */

#define CGC_LPAV_FRODIV_DIV1_MASK                (0x3FU)
#define CGC_LPAV_FRODIV_DIV1_SHIFT               (0U)
/*! DIV1 - Clock Division for Slow Clock */
#define CGC_LPAV_FRODIV_DIV1(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_FRODIV_DIV1_SHIFT)) & CGC_LPAV_FRODIV_DIV1_MASK)

#define CGC_LPAV_FRODIV_DIV1LOCKED_MASK          (0x40U)
#define CGC_LPAV_FRODIV_DIV1LOCKED_SHIFT         (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked */
#define CGC_LPAV_FRODIV_DIV1LOCKED(x)            (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_FRODIV_DIV1LOCKED_SHIFT)) & CGC_LPAV_FRODIV_DIV1LOCKED_MASK)

#define CGC_LPAV_FRODIV_DIV1HALT_MASK            (0x80U)
#define CGC_LPAV_FRODIV_DIV1HALT_SHIFT           (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_LPAV_FRODIV_DIV1HALT(x)              (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_FRODIV_DIV1HALT_SHIFT)) & CGC_LPAV_FRODIV_DIV1HALT_MASK)

#define CGC_LPAV_FRODIV_DIV2_MASK                (0x3F00U)
#define CGC_LPAV_FRODIV_DIV2_SHIFT               (8U)
/*! DIV2 - Clock Division for Bus Clock */
#define CGC_LPAV_FRODIV_DIV2(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_FRODIV_DIV2_SHIFT)) & CGC_LPAV_FRODIV_DIV2_MASK)

#define CGC_LPAV_FRODIV_DIV2LOCKED_MASK          (0x4000U)
#define CGC_LPAV_FRODIV_DIV2LOCKED_SHIFT         (14U)
/*! DIV2LOCKED - The value of clock division was changed and access to DIV2 is locked */
#define CGC_LPAV_FRODIV_DIV2LOCKED(x)            (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_FRODIV_DIV2LOCKED_SHIFT)) & CGC_LPAV_FRODIV_DIV2LOCKED_MASK)

#define CGC_LPAV_FRODIV_DIV2HALT_MASK            (0x8000U)
#define CGC_LPAV_FRODIV_DIV2HALT_SHIFT           (15U)
/*! DIV2HALT - Divider 2 Halted */
#define CGC_LPAV_FRODIV_DIV2HALT(x)              (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_FRODIV_DIV2HALT_SHIFT)) & CGC_LPAV_FRODIV_DIV2HALT_MASK)

#define CGC_LPAV_FRODIV_DIV3_MASK                (0x3F0000U)
#define CGC_LPAV_FRODIV_DIV3_SHIFT               (16U)
/*! DIV3 - Clock Division for Platform Clock */
#define CGC_LPAV_FRODIV_DIV3(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_FRODIV_DIV3_SHIFT)) & CGC_LPAV_FRODIV_DIV3_MASK)

#define CGC_LPAV_FRODIV_DIV3LOCKED_MASK          (0x400000U)
#define CGC_LPAV_FRODIV_DIV3LOCKED_SHIFT         (22U)
/*! DIV3LOCKED - The value of clock division was changed and access to DIV3 is locked */
#define CGC_LPAV_FRODIV_DIV3LOCKED(x)            (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_FRODIV_DIV3LOCKED_SHIFT)) & CGC_LPAV_FRODIV_DIV3LOCKED_MASK)

#define CGC_LPAV_FRODIV_DIV3HALT_MASK            (0x800000U)
#define CGC_LPAV_FRODIV_DIV3HALT_SHIFT           (23U)
/*! DIV3HALT - Divider 3 Halted */
#define CGC_LPAV_FRODIV_DIV3HALT(x)              (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_FRODIV_DIV3HALT_SHIFT)) & CGC_LPAV_FRODIV_DIV3HALT_MASK)
/*! @} */

/*! @name PLL4CSR - PLL Control Status Register */
/*! @{ */

#define CGC_LPAV_PLL4CSR_PLLEN_MASK              (0x1U)
#define CGC_LPAV_PLL4CSR_PLLEN_SHIFT             (0U)
/*! PLLEN - PLL Enable */
#define CGC_LPAV_PLL4CSR_PLLEN(x)                (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CSR_PLLEN_SHIFT)) & CGC_LPAV_PLL4CSR_PLLEN_MASK)

#define CGC_LPAV_PLL4CSR_PLLDSEN_MASK            (0x2U)
#define CGC_LPAV_PLL4CSR_PLLDSEN_SHIFT           (1U)
/*! PLLDSEN - PLL4 Enable in Deep Sleep */
#define CGC_LPAV_PLL4CSR_PLLDSEN(x)              (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CSR_PLLDSEN_SHIFT)) & CGC_LPAV_PLL4CSR_PLLDSEN_MASK)

#define CGC_LPAV_PLL4CSR_LK_MASK                 (0x800000U)
#define CGC_LPAV_PLL4CSR_LK_SHIFT                (23U)
/*! LK - Lock Register */
#define CGC_LPAV_PLL4CSR_LK(x)                   (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CSR_LK_SHIFT)) & CGC_LPAV_PLL4CSR_LK_MASK)

#define CGC_LPAV_PLL4CSR_PLLVLD_MASK             (0x1000000U)
#define CGC_LPAV_PLL4CSR_PLLVLD_SHIFT            (24U)
/*! PLLVLD - PLL Valid */
#define CGC_LPAV_PLL4CSR_PLLVLD(x)               (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CSR_PLLVLD_SHIFT)) & CGC_LPAV_PLL4CSR_PLLVLD_MASK)

#define CGC_LPAV_PLL4CSR_PLLSEL_MASK             (0x2000000U)
#define CGC_LPAV_PLL4CSR_PLLSEL_SHIFT            (25U)
/*! PLLSEL - PLL Selected */
#define CGC_LPAV_PLL4CSR_PLLSEL(x)               (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CSR_PLLSEL_SHIFT)) & CGC_LPAV_PLL4CSR_PLLSEL_MASK)
/*! @} */

/*! @name PLL4DIV_VCO - Clock Dividers for the fractional PLL4 */
/*! @{ */

#define CGC_LPAV_PLL4DIV_VCO_DIV1_MASK           (0x3FU)
#define CGC_LPAV_PLL4DIV_VCO_DIV1_SHIFT          (0U)
/*! DIV1 - Clock Division for PLL4 VCO Clock */
#define CGC_LPAV_PLL4DIV_VCO_DIV1(x)             (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_VCO_DIV1_SHIFT)) & CGC_LPAV_PLL4DIV_VCO_DIV1_MASK)

#define CGC_LPAV_PLL4DIV_VCO_DIV1LOCKED_MASK     (0x40U)
#define CGC_LPAV_PLL4DIV_VCO_DIV1LOCKED_SHIFT    (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked */
#define CGC_LPAV_PLL4DIV_VCO_DIV1LOCKED(x)       (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_VCO_DIV1LOCKED_SHIFT)) & CGC_LPAV_PLL4DIV_VCO_DIV1LOCKED_MASK)

#define CGC_LPAV_PLL4DIV_VCO_DIV1HALT_MASK       (0x80U)
#define CGC_LPAV_PLL4DIV_VCO_DIV1HALT_SHIFT      (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_LPAV_PLL4DIV_VCO_DIV1HALT(x)         (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_VCO_DIV1HALT_SHIFT)) & CGC_LPAV_PLL4DIV_VCO_DIV1HALT_MASK)
/*! @} */

/*! @name PLL4DIV_PFD_0 - Clock Dividers for the fractional PLL4 */
/*! @{ */

#define CGC_LPAV_PLL4DIV_PFD_0_DIV1_MASK         (0x3FU)
#define CGC_LPAV_PLL4DIV_PFD_0_DIV1_SHIFT        (0U)
/*! DIV1 - Clock Division for PLL4 PFD0 Clock */
#define CGC_LPAV_PLL4DIV_PFD_0_DIV1(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_0_DIV1_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_0_DIV1_MASK)

#define CGC_LPAV_PLL4DIV_PFD_0_DIV1LOCKED_MASK   (0x40U)
#define CGC_LPAV_PLL4DIV_PFD_0_DIV1LOCKED_SHIFT  (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked */
#define CGC_LPAV_PLL4DIV_PFD_0_DIV1LOCKED(x)     (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_0_DIV1LOCKED_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_0_DIV1LOCKED_MASK)

#define CGC_LPAV_PLL4DIV_PFD_0_DIV1HALT_MASK     (0x80U)
#define CGC_LPAV_PLL4DIV_PFD_0_DIV1HALT_SHIFT    (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_LPAV_PLL4DIV_PFD_0_DIV1HALT(x)       (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_0_DIV1HALT_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_0_DIV1HALT_MASK)

#define CGC_LPAV_PLL4DIV_PFD_0_DIV2_MASK         (0x3F00U)
#define CGC_LPAV_PLL4DIV_PFD_0_DIV2_SHIFT        (8U)
/*! DIV2 - Clock Division for PLL4 PFD0 Clock */
#define CGC_LPAV_PLL4DIV_PFD_0_DIV2(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_0_DIV2_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_0_DIV2_MASK)

#define CGC_LPAV_PLL4DIV_PFD_0_DIV2LOCKED_MASK   (0x4000U)
#define CGC_LPAV_PLL4DIV_PFD_0_DIV2LOCKED_SHIFT  (14U)
/*! DIV2LOCKED - The value of clock division was changed and access to DIV2 is locked */
#define CGC_LPAV_PLL4DIV_PFD_0_DIV2LOCKED(x)     (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_0_DIV2LOCKED_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_0_DIV2LOCKED_MASK)

#define CGC_LPAV_PLL4DIV_PFD_0_DIV2HALT_MASK     (0x8000U)
#define CGC_LPAV_PLL4DIV_PFD_0_DIV2HALT_SHIFT    (15U)
/*! DIV2HALT - Divider 2 Halted */
#define CGC_LPAV_PLL4DIV_PFD_0_DIV2HALT(x)       (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_0_DIV2HALT_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_0_DIV2HALT_MASK)

#define CGC_LPAV_PLL4DIV_PFD_0_DIV3_MASK         (0x3F0000U)
#define CGC_LPAV_PLL4DIV_PFD_0_DIV3_SHIFT        (16U)
/*! DIV3 - Clock Division for PLL4 PFD1 Clock */
#define CGC_LPAV_PLL4DIV_PFD_0_DIV3(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_0_DIV3_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_0_DIV3_MASK)

#define CGC_LPAV_PLL4DIV_PFD_0_DIV3LOCKED_MASK   (0x400000U)
#define CGC_LPAV_PLL4DIV_PFD_0_DIV3LOCKED_SHIFT  (22U)
/*! DIV3LOCKED - The value of clock division was changed and access to DIV3 is locked */
#define CGC_LPAV_PLL4DIV_PFD_0_DIV3LOCKED(x)     (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_0_DIV3LOCKED_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_0_DIV3LOCKED_MASK)

#define CGC_LPAV_PLL4DIV_PFD_0_DIV3HALT_MASK     (0x800000U)
#define CGC_LPAV_PLL4DIV_PFD_0_DIV3HALT_SHIFT    (23U)
/*! DIV3HALT - Divider 3 Halted */
#define CGC_LPAV_PLL4DIV_PFD_0_DIV3HALT(x)       (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_0_DIV3HALT_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_0_DIV3HALT_MASK)

#define CGC_LPAV_PLL4DIV_PFD_0_DIV4_MASK         (0x3F000000U)
#define CGC_LPAV_PLL4DIV_PFD_0_DIV4_SHIFT        (24U)
/*! DIV4 - Clock Division for PLL4 PFD1 Clock */
#define CGC_LPAV_PLL4DIV_PFD_0_DIV4(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_0_DIV4_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_0_DIV4_MASK)

#define CGC_LPAV_PLL4DIV_PFD_0_DIV4LOCKED_MASK   (0x40000000U)
#define CGC_LPAV_PLL4DIV_PFD_0_DIV4LOCKED_SHIFT  (30U)
/*! DIV4LOCKED - The value of clock division was changed and access to DIV4 is locked */
#define CGC_LPAV_PLL4DIV_PFD_0_DIV4LOCKED(x)     (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_0_DIV4LOCKED_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_0_DIV4LOCKED_MASK)

#define CGC_LPAV_PLL4DIV_PFD_0_DIV4HALT_MASK     (0x80000000U)
#define CGC_LPAV_PLL4DIV_PFD_0_DIV4HALT_SHIFT    (31U)
/*! DIV4HALT - Divider 4 Halted */
#define CGC_LPAV_PLL4DIV_PFD_0_DIV4HALT(x)       (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_0_DIV4HALT_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_0_DIV4HALT_MASK)
/*! @} */

/*! @name PLL4DIV_PFD_1 - Clock Dividers for the fractional PLL4 */
/*! @{ */

#define CGC_LPAV_PLL4DIV_PFD_1_DIV1_MASK         (0x3FU)
#define CGC_LPAV_PLL4DIV_PFD_1_DIV1_SHIFT        (0U)
/*! DIV1 - Clock Division for PLL4 PFD2 Clock */
#define CGC_LPAV_PLL4DIV_PFD_1_DIV1(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_1_DIV1_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_1_DIV1_MASK)

#define CGC_LPAV_PLL4DIV_PFD_1_DIV1LOCKED_MASK   (0x40U)
#define CGC_LPAV_PLL4DIV_PFD_1_DIV1LOCKED_SHIFT  (6U)
/*! DIV1LOCKED - The value of clock division was changed and access to DIV1 is locked */
#define CGC_LPAV_PLL4DIV_PFD_1_DIV1LOCKED(x)     (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_1_DIV1LOCKED_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_1_DIV1LOCKED_MASK)

#define CGC_LPAV_PLL4DIV_PFD_1_DIV1HALT_MASK     (0x80U)
#define CGC_LPAV_PLL4DIV_PFD_1_DIV1HALT_SHIFT    (7U)
/*! DIV1HALT - Divider 1 Halted */
#define CGC_LPAV_PLL4DIV_PFD_1_DIV1HALT(x)       (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_1_DIV1HALT_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_1_DIV1HALT_MASK)

#define CGC_LPAV_PLL4DIV_PFD_1_DIV2_MASK         (0x3F00U)
#define CGC_LPAV_PLL4DIV_PFD_1_DIV2_SHIFT        (8U)
/*! DIV2 - Clock Division for PLL4 PFD2 Clock */
#define CGC_LPAV_PLL4DIV_PFD_1_DIV2(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_1_DIV2_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_1_DIV2_MASK)

#define CGC_LPAV_PLL4DIV_PFD_1_DIV2LOCKED_MASK   (0x4000U)
#define CGC_LPAV_PLL4DIV_PFD_1_DIV2LOCKED_SHIFT  (14U)
/*! DIV2LOCKED - The value of clock division was changed and access to DIV2 is locked */
#define CGC_LPAV_PLL4DIV_PFD_1_DIV2LOCKED(x)     (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_1_DIV2LOCKED_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_1_DIV2LOCKED_MASK)

#define CGC_LPAV_PLL4DIV_PFD_1_DIV2HALT_MASK     (0x8000U)
#define CGC_LPAV_PLL4DIV_PFD_1_DIV2HALT_SHIFT    (15U)
/*! DIV2HALT - Divider 2 Halted */
#define CGC_LPAV_PLL4DIV_PFD_1_DIV2HALT(x)       (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_1_DIV2HALT_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_1_DIV2HALT_MASK)

#define CGC_LPAV_PLL4DIV_PFD_1_DIV3_MASK         (0x3F0000U)
#define CGC_LPAV_PLL4DIV_PFD_1_DIV3_SHIFT        (16U)
/*! DIV3 - Clock Division for PLL4 PFD3 Clock */
#define CGC_LPAV_PLL4DIV_PFD_1_DIV3(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_1_DIV3_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_1_DIV3_MASK)

#define CGC_LPAV_PLL4DIV_PFD_1_DIV3LOCKED_MASK   (0x400000U)
#define CGC_LPAV_PLL4DIV_PFD_1_DIV3LOCKED_SHIFT  (22U)
/*! DIV3LOCKED - The value of clock division was changed and access to DIV3 is locked */
#define CGC_LPAV_PLL4DIV_PFD_1_DIV3LOCKED(x)     (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_1_DIV3LOCKED_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_1_DIV3LOCKED_MASK)

#define CGC_LPAV_PLL4DIV_PFD_1_DIV3HALT_MASK     (0x800000U)
#define CGC_LPAV_PLL4DIV_PFD_1_DIV3HALT_SHIFT    (23U)
/*! DIV3HALT - Divider 3 Halted */
#define CGC_LPAV_PLL4DIV_PFD_1_DIV3HALT(x)       (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_1_DIV3HALT_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_1_DIV3HALT_MASK)

#define CGC_LPAV_PLL4DIV_PFD_1_DIV4_MASK         (0x3F000000U)
#define CGC_LPAV_PLL4DIV_PFD_1_DIV4_SHIFT        (24U)
/*! DIV4 - Clock Division for PLL4 PFD3 Clock */
#define CGC_LPAV_PLL4DIV_PFD_1_DIV4(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_1_DIV4_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_1_DIV4_MASK)

#define CGC_LPAV_PLL4DIV_PFD_1_DIV4LOCKED_MASK   (0x40000000U)
#define CGC_LPAV_PLL4DIV_PFD_1_DIV4LOCKED_SHIFT  (30U)
/*! DIV4LOCKED - The value of clock division was changed and access to DIV4 is locked */
#define CGC_LPAV_PLL4DIV_PFD_1_DIV4LOCKED(x)     (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_1_DIV4LOCKED_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_1_DIV4LOCKED_MASK)

#define CGC_LPAV_PLL4DIV_PFD_1_DIV4HALT_MASK     (0x80000000U)
#define CGC_LPAV_PLL4DIV_PFD_1_DIV4HALT_SHIFT    (31U)
/*! DIV4HALT - Divider 4 Halted */
#define CGC_LPAV_PLL4DIV_PFD_1_DIV4HALT(x)       (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DIV_PFD_1_DIV4HALT_SHIFT)) & CGC_LPAV_PLL4DIV_PFD_1_DIV4HALT_MASK)
/*! @} */

/*! @name PLL4CFG - PLL4 Configuration Register */
/*! @{ */

#define CGC_LPAV_PLL4CFG_SOURCE_MASK             (0x1U)
#define CGC_LPAV_PLL4CFG_SOURCE_SHIFT            (0U)
/*! SOURCE - Clock Source */
#define CGC_LPAV_PLL4CFG_SOURCE(x)               (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CFG_SOURCE_SHIFT)) & CGC_LPAV_PLL4CFG_SOURCE_MASK)

#define CGC_LPAV_PLL4CFG_HALF_LR_R_MASK          (0x8U)
#define CGC_LPAV_PLL4CFG_HALF_LR_R_SHIFT         (3U)
/*! HALF_LR_R - HALF_LR_R */
#define CGC_LPAV_PLL4CFG_HALF_LR_R(x)            (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CFG_HALF_LR_R_SHIFT)) & CGC_LPAV_PLL4CFG_HALF_LR_R_MASK)

#define CGC_LPAV_PLL4CFG_HALF_CP_CURRENT_MASK    (0x10U)
#define CGC_LPAV_PLL4CFG_HALF_CP_CURRENT_SHIFT   (4U)
/*! HALF_CP_CURRENT - HALF_CP_CURRENT */
#define CGC_LPAV_PLL4CFG_HALF_CP_CURRENT(x)      (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CFG_HALF_CP_CURRENT_SHIFT)) & CGC_LPAV_PLL4CFG_HALF_CP_CURRENT_MASK)

#define CGC_LPAV_PLL4CFG_DOUBLE_LF_R_MASK        (0x20U)
#define CGC_LPAV_PLL4CFG_DOUBLE_LF_R_SHIFT       (5U)
/*! DOUBLE_LF_R - DOUBLE_LF_R */
#define CGC_LPAV_PLL4CFG_DOUBLE_LF_R(x)          (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CFG_DOUBLE_LF_R_SHIFT)) & CGC_LPAV_PLL4CFG_DOUBLE_LF_R_MASK)

#define CGC_LPAV_PLL4CFG_DOUBLE_CP_CURRENT_MASK  (0x40U)
#define CGC_LPAV_PLL4CFG_DOUBLE_CP_CURRENT_SHIFT (6U)
/*! DOUBLE_CP_CURRENT - DOUBLE_CP_CURRENT */
#define CGC_LPAV_PLL4CFG_DOUBLE_CP_CURRENT(x)    (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CFG_DOUBLE_CP_CURRENT_SHIFT)) & CGC_LPAV_PLL4CFG_DOUBLE_CP_CURRENT_MASK)

#define CGC_LPAV_PLL4CFG_DITHER_EN_MASK          (0x800U)
#define CGC_LPAV_PLL4CFG_DITHER_EN_SHIFT         (11U)
/*! DITHER_EN - DITHER_EN */
#define CGC_LPAV_PLL4CFG_DITHER_EN(x)            (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CFG_DITHER_EN_SHIFT)) & CGC_LPAV_PLL4CFG_DITHER_EN_MASK)

#define CGC_LPAV_PLL4CFG_PFD_OFFSET_EN_MASK      (0x1000U)
#define CGC_LPAV_PLL4CFG_PFD_OFFSET_EN_SHIFT     (12U)
/*! PFD_OFFSET_EN - PFD_OFFSET_EN */
#define CGC_LPAV_PLL4CFG_PFD_OFFSET_EN(x)        (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CFG_PFD_OFFSET_EN_SHIFT)) & CGC_LPAV_PLL4CFG_PFD_OFFSET_EN_MASK)

#define CGC_LPAV_PLL4CFG_HOLDRING_OFF_MASK       (0x2000U)
#define CGC_LPAV_PLL4CFG_HOLDRING_OFF_SHIFT      (13U)
/*! HOLDRING_OFF - HOLDRING_OFF */
#define CGC_LPAV_PLL4CFG_HOLDRING_OFF(x)         (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CFG_HOLDRING_OFF_SHIFT)) & CGC_LPAV_PLL4CFG_HOLDRING_OFF_MASK)

#define CGC_LPAV_PLL4CFG_MULT_MASK               (0x7F0000U)
#define CGC_LPAV_PLL4CFG_MULT_SHIFT              (16U)
/*! MULT - System PLL Multiplier */
#define CGC_LPAV_PLL4CFG_MULT(x)                 (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4CFG_MULT_SHIFT)) & CGC_LPAV_PLL4CFG_MULT_MASK)
/*! @} */

/*! @name PLL4PFDCFG - PLL4 Configuration Register */
/*! @{ */

#define CGC_LPAV_PLL4PFDCFG_PFD0_MASK            (0x3FU)
#define CGC_LPAV_PLL4PFDCFG_PFD0_SHIFT           (0U)
/*! PFD0 - PLL Fractional Divider 0 */
#define CGC_LPAV_PLL4PFDCFG_PFD0(x)              (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4PFDCFG_PFD0_SHIFT)) & CGC_LPAV_PLL4PFDCFG_PFD0_MASK)

#define CGC_LPAV_PLL4PFDCFG_PFD0_VALID_MASK      (0x40U)
#define CGC_LPAV_PLL4PFDCFG_PFD0_VALID_SHIFT     (6U)
/*! PFD0_VALID - PFD0_VALID */
#define CGC_LPAV_PLL4PFDCFG_PFD0_VALID(x)        (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4PFDCFG_PFD0_VALID_SHIFT)) & CGC_LPAV_PLL4PFDCFG_PFD0_VALID_MASK)

#define CGC_LPAV_PLL4PFDCFG_PFD0_CLKGATE_MASK    (0x80U)
#define CGC_LPAV_PLL4PFDCFG_PFD0_CLKGATE_SHIFT   (7U)
/*! PFD0_CLKGATE - Clock gate of PFD0 */
#define CGC_LPAV_PLL4PFDCFG_PFD0_CLKGATE(x)      (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4PFDCFG_PFD0_CLKGATE_SHIFT)) & CGC_LPAV_PLL4PFDCFG_PFD0_CLKGATE_MASK)

#define CGC_LPAV_PLL4PFDCFG_PFD1_MASK            (0x3F00U)
#define CGC_LPAV_PLL4PFDCFG_PFD1_SHIFT           (8U)
/*! PFD1 - PLL Fractional Divider 1 */
#define CGC_LPAV_PLL4PFDCFG_PFD1(x)              (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4PFDCFG_PFD1_SHIFT)) & CGC_LPAV_PLL4PFDCFG_PFD1_MASK)

#define CGC_LPAV_PLL4PFDCFG_PFD1_VALID_MASK      (0x4000U)
#define CGC_LPAV_PLL4PFDCFG_PFD1_VALID_SHIFT     (14U)
/*! PFD1_VALID - PFD1_VALID */
#define CGC_LPAV_PLL4PFDCFG_PFD1_VALID(x)        (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4PFDCFG_PFD1_VALID_SHIFT)) & CGC_LPAV_PLL4PFDCFG_PFD1_VALID_MASK)

#define CGC_LPAV_PLL4PFDCFG_PFD1_CLKGATE_MASK    (0x8000U)
#define CGC_LPAV_PLL4PFDCFG_PFD1_CLKGATE_SHIFT   (15U)
/*! PFD1_CLKGATE - Clock gate of PFD1 */
#define CGC_LPAV_PLL4PFDCFG_PFD1_CLKGATE(x)      (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4PFDCFG_PFD1_CLKGATE_SHIFT)) & CGC_LPAV_PLL4PFDCFG_PFD1_CLKGATE_MASK)

#define CGC_LPAV_PLL4PFDCFG_PFD2_MASK            (0x3F0000U)
#define CGC_LPAV_PLL4PFDCFG_PFD2_SHIFT           (16U)
/*! PFD2 - PLL Fractional Divider 2 */
#define CGC_LPAV_PLL4PFDCFG_PFD2(x)              (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4PFDCFG_PFD2_SHIFT)) & CGC_LPAV_PLL4PFDCFG_PFD2_MASK)

#define CGC_LPAV_PLL4PFDCFG_PFD2_VALID_MASK      (0x400000U)
#define CGC_LPAV_PLL4PFDCFG_PFD2_VALID_SHIFT     (22U)
/*! PFD2_VALID - PFD2_VALID */
#define CGC_LPAV_PLL4PFDCFG_PFD2_VALID(x)        (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4PFDCFG_PFD2_VALID_SHIFT)) & CGC_LPAV_PLL4PFDCFG_PFD2_VALID_MASK)

#define CGC_LPAV_PLL4PFDCFG_PFD2_CLKGATE_MASK    (0x800000U)
#define CGC_LPAV_PLL4PFDCFG_PFD2_CLKGATE_SHIFT   (23U)
/*! PFD2_CLKGATE - Clock gate of PFD2 */
#define CGC_LPAV_PLL4PFDCFG_PFD2_CLKGATE(x)      (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4PFDCFG_PFD2_CLKGATE_SHIFT)) & CGC_LPAV_PLL4PFDCFG_PFD2_CLKGATE_MASK)

#define CGC_LPAV_PLL4PFDCFG_PFD3_MASK            (0x3F000000U)
#define CGC_LPAV_PLL4PFDCFG_PFD3_SHIFT           (24U)
/*! PFD3 - PLL Fractional Divider 3 */
#define CGC_LPAV_PLL4PFDCFG_PFD3(x)              (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4PFDCFG_PFD3_SHIFT)) & CGC_LPAV_PLL4PFDCFG_PFD3_MASK)

#define CGC_LPAV_PLL4PFDCFG_PFD3_VALID_MASK      (0x40000000U)
#define CGC_LPAV_PLL4PFDCFG_PFD3_VALID_SHIFT     (30U)
/*! PFD3_VALID - PFD3_VALID */
#define CGC_LPAV_PLL4PFDCFG_PFD3_VALID(x)        (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4PFDCFG_PFD3_VALID_SHIFT)) & CGC_LPAV_PLL4PFDCFG_PFD3_VALID_MASK)

#define CGC_LPAV_PLL4PFDCFG_PFD3_CLKGATE_MASK    (0x80000000U)
#define CGC_LPAV_PLL4PFDCFG_PFD3_CLKGATE_SHIFT   (31U)
/*! PFD3_CLKGATE - Clock gate of PFD3 */
#define CGC_LPAV_PLL4PFDCFG_PFD3_CLKGATE(x)      (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4PFDCFG_PFD3_CLKGATE_SHIFT)) & CGC_LPAV_PLL4PFDCFG_PFD3_CLKGATE_MASK)
/*! @} */

/*! @name PLL4DENOM - PLL Denominator Register */
/*! @{ */

#define CGC_LPAV_PLL4DENOM_DENOM_MASK            (0x3FFFFFFFU)
#define CGC_LPAV_PLL4DENOM_DENOM_SHIFT           (0U)
/*! DENOM - PLL Denominator Register */
#define CGC_LPAV_PLL4DENOM_DENOM(x)              (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4DENOM_DENOM_SHIFT)) & CGC_LPAV_PLL4DENOM_DENOM_MASK)
/*! @} */

/*! @name PLL4NUM - PLL Numerator Register */
/*! @{ */

#define CGC_LPAV_PLL4NUM_NUM_MASK                (0x3FFFFFFFU)
#define CGC_LPAV_PLL4NUM_NUM_SHIFT               (0U)
/*! NUM - PLL Numerator Register */
#define CGC_LPAV_PLL4NUM_NUM(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4NUM_NUM_SHIFT)) & CGC_LPAV_PLL4NUM_NUM_MASK)
/*! @} */

/*! @name PLL4SS - PLL Spread Spectrum Register */
/*! @{ */

#define CGC_LPAV_PLL4SS_STEP_MASK                (0x7FFFU)
#define CGC_LPAV_PLL4SS_STEP_SHIFT               (0U)
/*! STEP - STEP */
#define CGC_LPAV_PLL4SS_STEP(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4SS_STEP_SHIFT)) & CGC_LPAV_PLL4SS_STEP_MASK)

#define CGC_LPAV_PLL4SS_ENABLE_MASK              (0x8000U)
#define CGC_LPAV_PLL4SS_ENABLE_SHIFT             (15U)
/*! ENABLE - ENABLE */
#define CGC_LPAV_PLL4SS_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4SS_ENABLE_SHIFT)) & CGC_LPAV_PLL4SS_ENABLE_MASK)

#define CGC_LPAV_PLL4SS_STOP_MASK                (0xFFFF0000U)
#define CGC_LPAV_PLL4SS_STOP_SHIFT               (16U)
/*! STOP - STOP */
#define CGC_LPAV_PLL4SS_STOP(x)                  (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4SS_STOP_SHIFT)) & CGC_LPAV_PLL4SS_STOP_MASK)
/*! @} */

/*! @name PLL4LOCK - PLL LOCK Configuration Register */
/*! @{ */

#define CGC_LPAV_PLL4LOCK_LOCK_TIME_MASK         (0xFFFFU)
#define CGC_LPAV_PLL4LOCK_LOCK_TIME_SHIFT        (0U)
/*! LOCK_TIME - LOCK_TIME */
#define CGC_LPAV_PLL4LOCK_LOCK_TIME(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_PLL4LOCK_LOCK_TIME_SHIFT)) & CGC_LPAV_PLL4LOCK_LOCK_TIME_MASK)
/*! @} */

/*! @name AUD_CLK2 - AUD_CLK2 source to SAI7-6 */
/*! @{ */

#define CGC_LPAV_AUD_CLK2_AUD_CLK2_MASK          (0x7U)
#define CGC_LPAV_AUD_CLK2_AUD_CLK2_SHIFT         (0U)
/*! AUD_CLK2 - AUD_CLK2 Clock Source Selection */
#define CGC_LPAV_AUD_CLK2_AUD_CLK2(x)            (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_AUD_CLK2_AUD_CLK2_SHIFT)) & CGC_LPAV_AUD_CLK2_AUD_CLK2_MASK)
/*! @} */

/*! @name SAI7_6_CLK - SAI7-6 Clock Source Selection */
/*! @{ */

#define CGC_LPAV_SAI7_6_CLK_SAI6CLK_MASK         (0x7U)
#define CGC_LPAV_SAI7_6_CLK_SAI6CLK_SHIFT        (0U)
/*! SAI6CLK - Clock Source for SAI6 */
#define CGC_LPAV_SAI7_6_CLK_SAI6CLK(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_SAI7_6_CLK_SAI6CLK_SHIFT)) & CGC_LPAV_SAI7_6_CLK_SAI6CLK_MASK)

#define CGC_LPAV_SAI7_6_CLK_SAI7CLK_MASK         (0x700U)
#define CGC_LPAV_SAI7_6_CLK_SAI7CLK_SHIFT        (8U)
/*! SAI7CLK - Clock Source for SAI7 */
#define CGC_LPAV_SAI7_6_CLK_SAI7CLK(x)           (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_SAI7_6_CLK_SAI7CLK_SHIFT)) & CGC_LPAV_SAI7_6_CLK_SAI7CLK_MASK)
/*! @} */

/*! @name TPM8CLK - Multiplexer to select the audio clock connected to the TPM clock input */
/*! @{ */

#define CGC_LPAV_TPM8CLK_TPM8CLK_MASK            (0x7U)
#define CGC_LPAV_TPM8CLK_TPM8CLK_SHIFT           (0U)
/*! TPM8CLK - Clock Selection for TPM8 */
#define CGC_LPAV_TPM8CLK_TPM8CLK(x)              (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_TPM8CLK_TPM8CLK_SHIFT)) & CGC_LPAV_TPM8CLK_TPM8CLK_MASK)
/*! @} */

/*! @name SPDIFCLK - Multiplexer to select the audio clock connected to the SPDIF clock input */
/*! @{ */

#define CGC_LPAV_SPDIFCLK_SPDIFCLK_MASK          (0x7U)
#define CGC_LPAV_SPDIFCLK_SPDIFCLK_SHIFT         (0U)
/*! SPDIFCLK - Clock Selection for SPDIF */
#define CGC_LPAV_SPDIFCLK_SPDIFCLK(x)            (((uint32_t)(((uint32_t)(x)) << CGC_LPAV_SPDIFCLK_SPDIFCLK_SHIFT)) & CGC_LPAV_SPDIFCLK_SPDIFCLK_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CGC_LPAV_Register_Masks */


/* CGC_LPAV - Peripheral instance base addresses */
/** Peripheral CGC_LPAV base address */
#define CGC_LPAV_BASE                            (0x2DA60000u)
/** Peripheral CGC_LPAV base pointer */
#define CGC_LPAV                                 ((CGC_LPAV_Type *)CGC_LPAV_BASE)
/** Array initializer of CGC_LPAV peripheral base addresses */
#define CGC_LPAV_BASE_ADDRS                      { CGC_LPAV_BASE }
/** Array initializer of CGC_LPAV peripheral base pointers */
#define CGC_LPAV_BASE_PTRS                       { CGC_LPAV }

/*!
 * @}
 */ /* end of group CGC_LPAV_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CMC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CMC_Peripheral_Access_Layer CMC Peripheral Access Layer
 * @{
 */

/** CMC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __IO uint32_t CKCTRL;                            /**< Clock Control Register, offset: 0x10 */
  __IO uint32_t CKSTAT;                            /**< Clock Status Register, offset: 0x14 */
  __IO uint32_t RTD_PMPROT;                        /**< Power Mode Protection Register, offset: 0x18 */
       uint8_t RESERVED_1[4];
  __IO uint32_t RTD_PMCTRL;                        /**< Real Time Domain Power Mode Control Register, offset: 0x20 */
       uint8_t RESERVED_2[76];
  __IO uint32_t RTD_PSDORF;                        /**< Real Time Domain Power Switch Domain Out of Reset Interrupt Flag, offset: 0x70 */
  __IO uint32_t RTD_PSDORIE;                       /**< Real Time Domain Power Switch Domain Out of Reset Interrupt Enable, offset: 0x74 */
  __I  uint32_t RTD_PSDS;                          /**< Real Time Domain Power Switch Domain Status, offset: 0x78 */
       uint8_t RESERVED_3[4];
  __I  uint32_t SRS;                               /**< System Reset Status, offset: 0x80 */
       uint8_t RESERVED_4[4];
  __IO uint32_t SSRS;                              /**< Sticky System Reset Status, offset: 0x88 */
  __IO uint32_t SRIE;                              /**< System Reset Interrupt Enable, offset: 0x8C */
  __IO uint32_t SRIF;                              /**< System Reset Interrupt Flag, offset: 0x90 */
       uint8_t RESERVED_5[12];
  __IO uint32_t MR[1];                             /**< Mode Register, array offset: 0xA0, array step: 0x4 */
       uint8_t RESERVED_6[12];
  __IO uint32_t FM[1];                             /**< Force Mode Register, array offset: 0xB0, array step: 0x4 */
       uint8_t RESERVED_7[92];
  __IO uint32_t CORECTL;                           /**< Core Control Register, offset: 0x110 */
       uint8_t RESERVED_8[12];
  __IO uint32_t DBGCTL;                            /**< Debug Control Register, offset: 0x120 */
} CMC_Type;

/* ----------------------------------------------------------------------------
   -- CMC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CMC_Register_Masks CMC Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define CMC_VERID_FEATURE_MASK                   (0xFFFFU)
#define CMC_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Specification Number */
#define CMC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_VERID_FEATURE_SHIFT)) & CMC_VERID_FEATURE_MASK)

#define CMC_VERID_MINOR_MASK                     (0xFF0000U)
#define CMC_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number */
#define CMC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MINOR_SHIFT)) & CMC_VERID_MINOR_MASK)

#define CMC_VERID_MAJOR_MASK                     (0xFF000000U)
#define CMC_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number */
#define CMC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MAJOR_SHIFT)) & CMC_VERID_MAJOR_MASK)
/*! @} */

/*! @name CKCTRL - Clock Control Register */
/*! @{ */

#define CMC_CKCTRL_CKMODE_MASK                   (0x7U)
#define CMC_CKCTRL_CKMODE_SHIFT                  (0U)
/*! CKMODE - Clocking Mode
 *  0b000..No clock gating.
 *  0b001..Core clock is gated.
 *  0b011..Core and platform clocks are gated.
 *  0b111..Core, platform, bus and slow clocks are gated.
 */
#define CMC_CKCTRL_CKMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK)

#define CMC_CKCTRL_LOCK_MASK                     (0x80000000U)
#define CMC_CKCTRL_LOCK_SHIFT                    (31U)
/*! LOCK - Lock Register
 *  0b0..Register writes are allowed.
 *  0b1..Register writes are blocked.
 */
#define CMC_CKCTRL_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_LOCK_SHIFT)) & CMC_CKCTRL_LOCK_MASK)
/*! @} */

/*! @name CKSTAT - Clock Status Register */
/*! @{ */

#define CMC_CKSTAT_CKMODE_MASK                   (0x7U)
#define CMC_CKSTAT_CKMODE_SHIFT                  (0U)
/*! CKMODE - Low Power Status
 *  0b000..Core clock not gated.
 *  0b001..Core clock was gated
 *  0b011..Core and platform clocks were gated
 *  0b111..Core, platform, bus and slow clocks were gated
 */
#define CMC_CKSTAT_CKMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_CKMODE_SHIFT)) & CMC_CKSTAT_CKMODE_MASK)

#define CMC_CKSTAT_WAKEUP_MASK                   (0x1F00U)
#define CMC_CKSTAT_WAKEUP_SHIFT                  (8U)
/*! WAKEUP - Wakeup Source */
#define CMC_CKSTAT_WAKEUP(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_WAKEUP_SHIFT)) & CMC_CKSTAT_WAKEUP_MASK)

#define CMC_CKSTAT_VALID_MASK                    (0x80000000U)
#define CMC_CKSTAT_VALID_SHIFT                   (31U)
/*! VALID - Clock Status Valid
 *  0b0..Core clock not gated.
 *  0b1..Core clock was gated due to low power mode entry.
 */
#define CMC_CKSTAT_VALID(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_VALID_SHIFT)) & CMC_CKSTAT_VALID_MASK)
/*! @} */

/*! @name RTD_PMPROT - Power Mode Protection Register */
/*! @{ */

#define CMC_RTD_PMPROT_AS_MASK                   (0x1U)
#define CMC_RTD_PMPROT_AS_SHIFT                  (0U)
/*! AS - Allow Sleep
 *  0b0..Sleep is not allowed
 *  0b1..Sleep is allowed
 */
#define CMC_RTD_PMPROT_AS(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PMPROT_AS_SHIFT)) & CMC_RTD_PMPROT_AS_MASK)

#define CMC_RTD_PMPROT_ADS_MASK                  (0x2U)
#define CMC_RTD_PMPROT_ADS_SHIFT                 (1U)
/*! ADS - Allow Deep Sleep
 *  0b0..Deep Sleep is not allowed
 *  0b1..Deep Sleep is allowed
 */
#define CMC_RTD_PMPROT_ADS(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PMPROT_ADS_SHIFT)) & CMC_RTD_PMPROT_ADS_MASK)

#define CMC_RTD_PMPROT_APD_MASK                  (0x4U)
#define CMC_RTD_PMPROT_APD_SHIFT                 (2U)
/*! APD - Allow Power Down
 *  0b0..Power Down is not allowed
 *  0b1..Power Down is allowed
 */
#define CMC_RTD_PMPROT_APD(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PMPROT_APD_SHIFT)) & CMC_RTD_PMPROT_APD_MASK)

#define CMC_RTD_PMPROT_ADPD_MASK                 (0x8U)
#define CMC_RTD_PMPROT_ADPD_SHIFT                (3U)
/*! ADPD - Allow Deep Power Down
 *  0b0..Deep Power Down is not allowed
 *  0b1..Deep Power Down is allowed
 */
#define CMC_RTD_PMPROT_ADPD(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PMPROT_ADPD_SHIFT)) & CMC_RTD_PMPROT_ADPD_MASK)

#define CMC_RTD_PMPROT_AHLD_MASK                 (0x10U)
#define CMC_RTD_PMPROT_AHLD_SHIFT                (4U)
/*! AHLD - Allow Hold
 *  0b0..Hold is not allowed
 *  0b1..Hold is allowed
 */
#define CMC_RTD_PMPROT_AHLD(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PMPROT_AHLD_SHIFT)) & CMC_RTD_PMPROT_AHLD_MASK)

#define CMC_RTD_PMPROT_LOCK_MASK                 (0x80000000U)
#define CMC_RTD_PMPROT_LOCK_SHIFT                (31U)
/*! LOCK - Lock Register
 *  0b0..Register writes are allowed.
 *  0b1..Register writes are blocked.
 */
#define CMC_RTD_PMPROT_LOCK(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PMPROT_LOCK_SHIFT)) & CMC_RTD_PMPROT_LOCK_MASK)
/*! @} */

/*! @name RTD_PMCTRL - Real Time Domain Power Mode Control Register */
/*! @{ */

#define CMC_RTD_PMCTRL_RTD_LPMODE_MASK           (0x1FU)
#define CMC_RTD_PMCTRL_RTD_LPMODE_SHIFT          (0U)
/*! RTD_LPMODE - Low Power Mode
 *  0b00000..Active
 *  0b00001..Sleep
 *  0b00011..Deep Sleep
 *  0b00111..Power Down
 *  0b01111..Deep Power Down
 *  0b11111..Hold
 */
#define CMC_RTD_PMCTRL_RTD_LPMODE(x)             (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PMCTRL_RTD_LPMODE_SHIFT)) & CMC_RTD_PMCTRL_RTD_LPMODE_MASK)
/*! @} */

/*! @name RTD_PSDORF - Real Time Domain Power Switch Domain Out of Reset Interrupt Flag */
/*! @{ */

#define CMC_RTD_PSDORF_FUSION_MASK               (0x2U)
#define CMC_RTD_PSDORF_FUSION_SHIFT              (1U)
/*! Fusion - Fusion Power Switch Domain Out of Reset Interrupt Flag
 *  0b0..Fusion Power Switch Domain in reset or user has cleared it by writing 1 to clear
 *  0b1..Fusion Power switch domain out of reset interrupt flag. This bit is asserted only once after the power switch domain exits the reset.
 */
#define CMC_RTD_PSDORF_FUSION(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PSDORF_FUSION_SHIFT)) & CMC_RTD_PSDORF_FUSION_MASK)

#define CMC_RTD_PSDORF_FUSION_AO_MASK            (0x4U)
#define CMC_RTD_PSDORF_FUSION_AO_SHIFT           (2U)
/*! Fusion_AO - Fusion Always ON Power Switch Domain Out of Reset Interrupt Flag
 *  0b0..Fusion Always ON Power Switch Domain in reset or user has cleared it by writing 1 to clear
 *  0b1..Fusion Always ON Power switch domain out of reset interrupt flag. This bit is asserted only once after
 *       the power switch domain exits the reset.
 */
#define CMC_RTD_PSDORF_FUSION_AO(x)              (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PSDORF_FUSION_AO_SHIFT)) & CMC_RTD_PSDORF_FUSION_AO_MASK)
/*! @} */

/*! @name RTD_PSDORIE - Real Time Domain Power Switch Domain Out of Reset Interrupt Enable */
/*! @{ */

#define CMC_RTD_PSDORIE_FUSION_MASK              (0x2U)
#define CMC_RTD_PSDORIE_FUSION_SHIFT             (1U)
/*! Fusion - Fusion Power Switch Domain Out of Reset Interrupt Enable
 *  0b0..Fusion Power Switch does not generate interrupt when domain gets out of reset.
 *  0b1..Fusion Power Switch generates interrupt when domain gets out of reset.
 */
#define CMC_RTD_PSDORIE_FUSION(x)                (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PSDORIE_FUSION_SHIFT)) & CMC_RTD_PSDORIE_FUSION_MASK)

#define CMC_RTD_PSDORIE_FUSION_AO_MASK           (0x4U)
#define CMC_RTD_PSDORIE_FUSION_AO_SHIFT          (2U)
/*! Fusion_AO - Fusion Always ON Power Switch Domain Out of Reset Interrupt Enable
 *  0b0..Fusion Always ON Power Switch does not generate interrupt when domain gets out of reset.
 *  0b1..Fusion Always ON Power Switch generates interrupt when domain gets out of reset.
 */
#define CMC_RTD_PSDORIE_FUSION_AO(x)             (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PSDORIE_FUSION_AO_SHIFT)) & CMC_RTD_PSDORIE_FUSION_AO_MASK)
/*! @} */

/*! @name RTD_PSDS - Real Time Domain Power Switch Domain Status */
/*! @{ */

#define CMC_RTD_PSDS_RTD_MASK                    (0x1U)
#define CMC_RTD_PSDS_RTD_SHIFT                   (0U)
/*! RTD - Realtime Power Switch Domain Status
 *  0b0..Realtime Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..Realtime Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_RTD_PSDS_RTD(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PSDS_RTD_SHIFT)) & CMC_RTD_PSDS_RTD_MASK)

#define CMC_RTD_PSDS_FUSION_MASK                 (0x2U)
#define CMC_RTD_PSDS_FUSION_SHIFT                (1U)
/*! Fusion - Fusion Power Switch Domain Status
 *  0b0..Fusion Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..Fusion Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_RTD_PSDS_FUSION(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PSDS_FUSION_SHIFT)) & CMC_RTD_PSDS_FUSION_MASK)

#define CMC_RTD_PSDS_FUSION_AO_MASK              (0x4U)
#define CMC_RTD_PSDS_FUSION_AO_SHIFT             (2U)
/*! Fusion_AO - Fusion Always ON Power Switch Domain Status
 *  0b0..Fusion Always ON Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..Fusion Always ON Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_RTD_PSDS_FUSION_AO(x)                (((uint32_t)(((uint32_t)(x)) << CMC_RTD_PSDS_FUSION_AO_SHIFT)) & CMC_RTD_PSDS_FUSION_AO_MASK)
/*! @} */

/*! @name SRS - System Reset Status */
/*! @{ */

#define CMC_SRS_WAKEUP_MASK                      (0x1U)
#define CMC_SRS_WAKEUP_SHIFT                     (0U)
/*! WAKEUP - Wakeup Reset
 *  0b0..Reset not generated by wakeup from Power Down or Deep Power Down mode.
 *  0b1..Reset generated by wakeup from Power Down or Deep Power Down mode.
 */
#define CMC_SRS_WAKEUP(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WAKEUP_SHIFT)) & CMC_SRS_WAKEUP_MASK)

#define CMC_SRS_POR_MASK                         (0x2U)
#define CMC_SRS_POR_SHIFT                        (1U)
/*! POR - Power-On Reset
 *  0b0..Reset not generated by POR.
 *  0b1..Reset generated by POR.
 */
#define CMC_SRS_POR(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_POR_SHIFT)) & CMC_SRS_POR_MASK)

#define CMC_SRS_HLVD_MASK                        (0x4U)
#define CMC_SRS_HLVD_SHIFT                       (2U)
/*! HLVD - High or Low Voltage Detect Reset
 *  0b0..Reset not generated by HLVD.
 *  0b1..Reset generated by HLVD.
 */
#define CMC_SRS_HLVD(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRS_HLVD_SHIFT)) & CMC_SRS_HLVD_MASK)

#define CMC_SRS_WARM_MASK                        (0x10U)
#define CMC_SRS_WARM_SHIFT                       (4U)
/*! WARM - Warm Reset
 *  0b0..Reset not generated by Warm Reset source.
 *  0b1..Reset generated by Warm Reset source.
 */
#define CMC_SRS_WARM(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WARM_SHIFT)) & CMC_SRS_WARM_MASK)

#define CMC_SRS_FATAL_MASK                       (0x20U)
#define CMC_SRS_FATAL_SHIFT                      (5U)
/*! FATAL - Fatal Reset
 *  0b0..Reset was not generated by a fatal reset source.
 *  0b1..Reset was generated by a fatal reset source.
 */
#define CMC_SRS_FATAL(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_FATAL_SHIFT)) & CMC_SRS_FATAL_MASK)

#define CMC_SRS_PIN_MASK                         (0x100U)
#define CMC_SRS_PIN_SHIFT                        (8U)
/*! PIN - Pin Reset
 *  0b0..Reset was not generated from the assertion of RESET0_b pin.
 *  0b1..Reset was generated from the assertion of RESET0_b pin.
 */
#define CMC_SRS_PIN(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_PIN_SHIFT)) & CMC_SRS_PIN_MASK)

#define CMC_SRS_ISP_AP_MASK                      (0x200U)
#define CMC_SRS_ISP_AP_SHIFT                     (9U)
/*! ISP_AP - In-System Programming Access Port Reset
 *  0b0..Reset was not generated from a ISP_AP reset request.
 *  0b1..Reset was generated from a ISP_AP reset request.
 */
#define CMC_SRS_ISP_AP(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_ISP_AP_SHIFT)) & CMC_SRS_ISP_AP_MASK)

#define CMC_SRS_RSTACK_MASK                      (0x400U)
#define CMC_SRS_RSTACK_SHIFT                     (10U)
/*! RSTACK - Reset Timeout
 *  0b0..Reset not generated from Reset Controller Timeout.
 *  0b1..Reset generated from Reset Controller Timeout.
 */
#define CMC_SRS_RSTACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RSTACK_SHIFT)) & CMC_SRS_RSTACK_MASK)

#define CMC_SRS_LPACK_MASK                       (0x800U)
#define CMC_SRS_LPACK_SHIFT                      (11U)
/*! LPACK - Low Power Acknowledge Timeout Reset
 *  0b0..Reset not generated by Low Power Acknowledge Timeout.
 *  0b1..Reset generated by Low Power Acknowledge Timeout.
 */
#define CMC_SRS_LPACK(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LPACK_SHIFT)) & CMC_SRS_LPACK_MASK)

#define CMC_SRS_RTD_CGC_LOC_MASK                 (0x1000U)
#define CMC_SRS_RTD_CGC_LOC_SHIFT                (12U)
/*! RTD_CGC_LOC - Real Time Domain Clock Generation and Control Loss-of-Clock Reset
 *  0b0..Reset is not generated from an RTD_CGC loss of clock.
 *  0b1..Reset is generated from an RTD_CGC loss of clock.
 */
#define CMC_SRS_RTD_CGC_LOC(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RTD_CGC_LOC_SHIFT)) & CMC_SRS_RTD_CGC_LOC_MASK)

#define CMC_SRS_WDOG0_MASK                       (0x2000U)
#define CMC_SRS_WDOG0_SHIFT                      (13U)
/*! WDOG0 - Watchdog 0 Reset
 *  0b0..Reset is not generated from the WatchDog 0 timeout.
 *  0b1..Reset is generated from the WatchDog 0 timeout.
 */
#define CMC_SRS_WDOG0(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WDOG0_SHIFT)) & CMC_SRS_WDOG0_MASK)

#define CMC_SRS_SW_MASK                          (0x4000U)
#define CMC_SRS_SW_SHIFT                         (14U)
/*! SW - Software Reset
 *  0b0..Reset not generated by software request from core.
 *  0b1..Reset generated by software request from core.
 */
#define CMC_SRS_SW(x)                            (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SW_SHIFT)) & CMC_SRS_SW_MASK)

#define CMC_SRS_LOCKUP_MASK                      (0x8000U)
#define CMC_SRS_LOCKUP_SHIFT                     (15U)
/*! LOCKUP - Lockup Reset
 *  0b0..Reset not generated by core lockup or exception.
 *  0b1..Reset generated by core lockup or exception.
 */
#define CMC_SRS_LOCKUP(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LOCKUP_SHIFT)) & CMC_SRS_LOCKUP_MASK)

#define CMC_SRS_AD_MU_MASK                       (0x10000U)
#define CMC_SRS_AD_MU_SHIFT                      (16U)
/*! AD_MU - Application Domain MU System Reset
 *  0b0..Reset not generated from AD_MU reset source.
 *  0b1..Reset generated from AD_MU reset source.
 */
#define CMC_SRS_AD_MU(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_AD_MU_SHIFT)) & CMC_SRS_AD_MU_MASK)

#define CMC_SRS_RTD_CGC_LOS_MASK                 (0x80000U)
#define CMC_SRS_RTD_CGC_LOS_SHIFT                (19U)
/*! RTD_CGC_LOS - RTD Clock Generation and Control Loss Of Sync
 *  0b0..Reset not generated from RTD_CGC_LOS system reset source.
 *  0b1..Reset generated from RTD_CGC_LOS system reset source.
 */
#define CMC_SRS_RTD_CGC_LOS(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RTD_CGC_LOS_SHIFT)) & CMC_SRS_RTD_CGC_LOS_MASK)

#define CMC_SRS_LPAV_CGC_LOS_MASK                (0x400000U)
#define CMC_SRS_LPAV_CGC_LOS_SHIFT               (22U)
/*! LPAV_CGC_LOS - LPAV Clock Generation and Control Loss Of Sync
 *  0b0..Reset not generated from LPAV_CGC_LOS system reset source.
 *  0b1..Reset generated from LPAV_CGC_LOS system reset source.
 */
#define CMC_SRS_LPAV_CGC_LOS(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LPAV_CGC_LOS_SHIFT)) & CMC_SRS_LPAV_CGC_LOS_MASK)

#define CMC_SRS_UPOWER_MASK                      (0x800000U)
#define CMC_SRS_UPOWER_SHIFT                     (23U)
/*! uPOWER - uPOWER WDOG System Reset
 *  0b0..Reset not generated by uPOWER WDOG timeout.
 *  0b1..Reset generated by uPOWER WDOG timeout.
 */
#define CMC_SRS_UPOWER(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_UPOWER_SHIFT)) & CMC_SRS_UPOWER_MASK)

#define CMC_SRS_VBAT_MASK                        (0x1000000U)
#define CMC_SRS_VBAT_SHIFT                       (24U)
/*! VBAT - VBAT System Reset
 *  0b0..Reset not generated by VBAT system reset.
 *  0b1..Reset generated by VBAT system reset.
 */
#define CMC_SRS_VBAT(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VBAT_SHIFT)) & CMC_SRS_VBAT_MASK)

#define CMC_SRS_WDOG_S_RTD_MASK                  (0x2000000U)
#define CMC_SRS_WDOG_S_RTD_SHIFT                 (25U)
/*! WDOG_S_RTD - Watchdog 1 Reset
 *  0b0..Reset is not generated from the WDOG_S_RTD timeout.
 *  0b1..Reset is generated from the WDOG_S_RTD timeout.
 */
#define CMC_SRS_WDOG_S_RTD(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WDOG_S_RTD_SHIFT)) & CMC_SRS_WDOG_S_RTD_MASK)

#define CMC_SRS_WDOG5_MASK                       (0x4000000U)
#define CMC_SRS_WDOG5_SHIFT                      (26U)
/*! WDOG5 - Watchdog 5 Reset
 *  0b0..Reset is not generated from the WDOG5 timeout.
 *  0b1..Reset is generated from the WDOG5 timeout.
 */
#define CMC_SRS_WDOG5(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WDOG5_SHIFT)) & CMC_SRS_WDOG5_MASK)

#define CMC_SRS_WDOG_FUSION_MASK                 (0x8000000U)
#define CMC_SRS_WDOG_FUSION_SHIFT                (27U)
/*! WDOG_FUSION - Watchdog 2 Reset
 *  0b0..Reset is not generated from the WDOG_FUSION timeout.
 *  0b1..Reset is generated from the WDOG_FUSION timeout.
 */
#define CMC_SRS_WDOG_FUSION(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WDOG_FUSION_SHIFT)) & CMC_SRS_WDOG_FUSION_MASK)

#define CMC_SRS_JTAG_MASK                        (0x10000000U)
#define CMC_SRS_JTAG_SHIFT                       (28U)
/*! JTAG - JTAG System Reset
 *  0b0..Reset not generated by JTAG system reset.
 *  0b1..Reset generated by JTAG system reset.
 */
#define CMC_SRS_JTAG(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRS_JTAG_SHIFT)) & CMC_SRS_JTAG_MASK)

#define CMC_SRS_SLB_MASK                         (0x20000000U)
#define CMC_SRS_SLB_SHIFT                        (29U)
/*! SLB - Secure enclave Lifecycle Bricked Reset
 *  0b0..Reset not generated by Secure enclave Lifecycle check.
 *  0b1..Reset generated by Secure enclave Lifecycle check.
 */
#define CMC_SRS_SLB(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SLB_SHIFT)) & CMC_SRS_SLB_MASK)

#define CMC_SRS_SRR_MASK                         (0x40000000U)
#define CMC_SRS_SRR_SHIFT                        (30U)
/*! SRR - Secure enclave Reset Request
 *  0b0..Reset not generated by SRR.
 *  0b1..Reset generated by SRR.
 */
#define CMC_SRS_SRR(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SRR_SHIFT)) & CMC_SRS_SRR_MASK)

#define CMC_SRS_SSF_MASK                         (0x80000000U)
#define CMC_SRS_SSF_SHIFT                        (31U)
/*! SSF - Secure enclave System Fail Reset
 *  0b0..Reset not generated by SSF.
 *  0b1..Reset generated by SSF.
 */
#define CMC_SRS_SSF(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SSF_SHIFT)) & CMC_SRS_SSF_MASK)
/*! @} */

/*! @name SSRS - Sticky System Reset Status */
/*! @{ */

#define CMC_SSRS_WAKEUP_MASK                     (0x1U)
#define CMC_SSRS_WAKEUP_SHIFT                    (0U)
/*! WAKEUP - Wakeup Reset
 *  0b0..Reset not generated by wakeup from DPD mode.
 *  0b1..Reset generated by wakeup from DPD mode.
 */
#define CMC_SSRS_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WAKEUP_SHIFT)) & CMC_SSRS_WAKEUP_MASK)

#define CMC_SSRS_POR_MASK                        (0x2U)
#define CMC_SSRS_POR_SHIFT                       (1U)
/*! POR - Power-On Reset
 *  0b0..Reset not generated by POR.
 *  0b1..Reset generated by POR.
 */
#define CMC_SSRS_POR(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_POR_SHIFT)) & CMC_SSRS_POR_MASK)

#define CMC_SSRS_HLVD_MASK                       (0x4U)
#define CMC_SSRS_HLVD_SHIFT                      (2U)
/*! HLVD - High or Low Voltage Detect Reset
 *  0b0..Reset not generated by HLVD.
 *  0b1..Reset generated by HLVD.
 */
#define CMC_SSRS_HLVD(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_HLVD_SHIFT)) & CMC_SSRS_HLVD_MASK)

#define CMC_SSRS_WARM_MASK                       (0x10U)
#define CMC_SSRS_WARM_SHIFT                      (4U)
/*! WARM - Warm Reset
 *  0b0..Reset not generated by warm reset source.
 *  0b1..Reset generated by warm reset source.
 */
#define CMC_SSRS_WARM(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WARM_SHIFT)) & CMC_SSRS_WARM_MASK)

#define CMC_SSRS_FATAL_MASK                      (0x20U)
#define CMC_SSRS_FATAL_SHIFT                     (5U)
/*! FATAL - Fatal Reset
 *  0b0..Reset was not generated by a fatal reset source.
 *  0b1..Reset was generated by a fatal reset source.
 */
#define CMC_SSRS_FATAL(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_FATAL_SHIFT)) & CMC_SSRS_FATAL_MASK)

#define CMC_SSRS_PIN_MASK                        (0x100U)
#define CMC_SSRS_PIN_SHIFT                       (8U)
/*! PIN - Pin Reset
 *  0b0..Reset was not generated from the RESET_B pin.
 *  0b1..Reset was generated from the RESET_B pin.
 */
#define CMC_SSRS_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_PIN_SHIFT)) & CMC_SSRS_PIN_MASK)

#define CMC_SSRS_ISP_AP_MASK                     (0x200U)
#define CMC_SSRS_ISP_AP_SHIFT                    (9U)
/*! ISP_AP - In-System Programming Access Port Reset
 *  0b0..Reset was not generated from a Debug Access Port reset request.
 *  0b1..Reset was generated from a Debug Access Port reset request.
 */
#define CMC_SSRS_ISP_AP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_ISP_AP_SHIFT)) & CMC_SSRS_ISP_AP_MASK)

#define CMC_SSRS_RSTACK_MASK                     (0x400U)
#define CMC_SSRS_RSTACK_SHIFT                    (10U)
/*! RSTACK - Reset Timeout
 *  0b0..Reset not generated from Reset Controller Timeout.
 *  0b1..Reset generated from Reset Controller Timeout.
 */
#define CMC_SSRS_RSTACK(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RSTACK_SHIFT)) & CMC_SSRS_RSTACK_MASK)

#define CMC_SSRS_LPACK_MASK                      (0x800U)
#define CMC_SSRS_LPACK_SHIFT                     (11U)
/*! LPACK - Low Power Acknowledge Timeout Reset
 *  0b0..Reset not generated by Low Power Acknowledge Timeout.
 *  0b1..Reset generated by Low Power Acknowledge Timeout.
 */
#define CMC_SSRS_LPACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LPACK_SHIFT)) & CMC_SSRS_LPACK_MASK)

#define CMC_SSRS_RTD_CGC_LOC_MASK                (0x1000U)
#define CMC_SSRS_RTD_CGC_LOC_SHIFT               (12U)
/*! RTD_CGC_LOC - RTD Clock Generation and Control Loss-of-Clock Reset
 *  0b0..Reset is not generated from an RTD CGC loss of clock.
 *  0b1..Reset is generated from an RTDF CGC loss of clock.
 */
#define CMC_SSRS_RTD_CGC_LOC(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RTD_CGC_LOC_SHIFT)) & CMC_SSRS_RTD_CGC_LOC_MASK)

#define CMC_SSRS_WDOG0_MASK                      (0x2000U)
#define CMC_SSRS_WDOG0_SHIFT                     (13U)
/*! WDOG0 - Watchdog 0 Reset
 *  0b0..Reset is not generated from the WatchDog 0 timeout.
 *  0b1..Reset is generated from the WatchDog 0 timeout.
 */
#define CMC_SSRS_WDOG0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WDOG0_SHIFT)) & CMC_SSRS_WDOG0_MASK)

#define CMC_SSRS_SW_MASK                         (0x4000U)
#define CMC_SSRS_SW_SHIFT                        (14U)
/*! SW - Software Reset
 *  0b0..Reset not generated by software request from core.
 *  0b1..Reset generated by software request from core.
 */
#define CMC_SSRS_SW(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SW_SHIFT)) & CMC_SSRS_SW_MASK)

#define CMC_SSRS_LOCKUP_MASK                     (0x8000U)
#define CMC_SSRS_LOCKUP_SHIFT                    (15U)
/*! LOCKUP - Lockup Reset
 *  0b0..Reset not generated by core lockup.
 *  0b1..Reset generated by core lockup.
 */
#define CMC_SSRS_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LOCKUP_SHIFT)) & CMC_SSRS_LOCKUP_MASK)

#define CMC_SSRS_AD_MU_MASK                      (0x10000U)
#define CMC_SSRS_AD_MU_SHIFT                     (16U)
/*! AD_MU - Application Domain MU System Reset
 *  0b0..Reset not generated from AD_MU reset source.
 *  0b1..Reset generated from AD_MU reset source.
 */
#define CMC_SSRS_AD_MU(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_AD_MU_SHIFT)) & CMC_SSRS_AD_MU_MASK)

#define CMC_SSRS_RTD_CGC_LOS_MASK                (0x80000U)
#define CMC_SSRS_RTD_CGC_LOS_SHIFT               (19U)
/*! RTD_CGC_LOS - RTD Clock Generation and Control Loss Of Sync
 *  0b0..Reset not generated from RTD_CGC_LOS system reset source.
 *  0b1..Reset generated from RTD_CGC_LOS system reset source.
 */
#define CMC_SSRS_RTD_CGC_LOS(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RTD_CGC_LOS_SHIFT)) & CMC_SSRS_RTD_CGC_LOS_MASK)

#define CMC_SSRS_LPAV_CGC_LOS_MASK               (0x400000U)
#define CMC_SSRS_LPAV_CGC_LOS_SHIFT              (22U)
/*! LPAV_CGC_LOS - LPAV Clock Generation and Control Loss Of Sync
 *  0b0..Reset not generated from LPAV_CGC_LOS system reset source.
 *  0b1..Reset generated from LPAV_CGC_LOS system reset source.
 */
#define CMC_SSRS_LPAV_CGC_LOS(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LPAV_CGC_LOS_SHIFT)) & CMC_SSRS_LPAV_CGC_LOS_MASK)

#define CMC_SSRS_UPOWER_MASK                     (0x800000U)
#define CMC_SSRS_UPOWER_SHIFT                    (23U)
/*! uPOWER - uPOWER WDOG System Reset
 *  0b0..Reset not generated by uPOWER WDOG timeout.
 *  0b1..Reset generated by uPOWER WDOG timeout.
 */
#define CMC_SSRS_UPOWER(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_UPOWER_SHIFT)) & CMC_SSRS_UPOWER_MASK)

#define CMC_SSRS_VBAT_MASK                       (0x1000000U)
#define CMC_SSRS_VBAT_SHIFT                      (24U)
/*! VBAT - VBAT System Reset
 *  0b0..Reset not generated by VBAT system reset.
 *  0b1..Reset generated by VBAT system reset.
 */
#define CMC_SSRS_VBAT(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VBAT_SHIFT)) & CMC_SSRS_VBAT_MASK)

#define CMC_SSRS_WDOG_S_RTD_MASK                 (0x2000000U)
#define CMC_SSRS_WDOG_S_RTD_SHIFT                (25U)
/*! WDOG_S_RTD - Watchdog 1 Reset
 *  0b0..Reset is not generated from the WDOG_S_RTD timeout.
 *  0b1..Reset is generated from the WDOG_S_RTD timeout.
 */
#define CMC_SSRS_WDOG_S_RTD(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WDOG_S_RTD_SHIFT)) & CMC_SSRS_WDOG_S_RTD_MASK)

#define CMC_SSRS_WDOG5_MASK                      (0x4000000U)
#define CMC_SSRS_WDOG5_SHIFT                     (26U)
/*! WDOG5 - Watchdog 5 Reset
 *  0b0..Reset is not generated from the WDOG5 timeout.
 *  0b1..Reset is generated from the WDOG5 timeout.
 */
#define CMC_SSRS_WDOG5(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WDOG5_SHIFT)) & CMC_SSRS_WDOG5_MASK)

#define CMC_SSRS_WDOG_FUSION_MASK                (0x8000000U)
#define CMC_SSRS_WDOG_FUSION_SHIFT               (27U)
/*! WDOG_FUSION - Watchdog 2 Reset
 *  0b0..Reset is not generated from the WDOG_FUSION timeout.
 *  0b1..Reset is generated from the WDOG_FUSION timeout.
 */
#define CMC_SSRS_WDOG_FUSION(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WDOG_FUSION_SHIFT)) & CMC_SSRS_WDOG_FUSION_MASK)

#define CMC_SSRS_JTAG_MASK                       (0x10000000U)
#define CMC_SSRS_JTAG_SHIFT                      (28U)
/*! JTAG - JTAG System Reset
 *  0b0..Reset not generated by JTAG system reset.
 *  0b1..Reset generated by JTAG system reset.
 */
#define CMC_SSRS_JTAG(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_JTAG_SHIFT)) & CMC_SSRS_JTAG_MASK)

#define CMC_SSRS_SLB_MASK                        (0x20000000U)
#define CMC_SSRS_SLB_SHIFT                       (29U)
/*! SLB - Secure enclave Lifecycle Bricked Reset
 *  0b0..Reset not generated by Secure enclave Lifecycle check.
 *  0b1..Reset generated by Secure enclave Lifecycle check.
 */
#define CMC_SSRS_SLB(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SLB_SHIFT)) & CMC_SSRS_SLB_MASK)

#define CMC_SSRS_SRR_MASK                        (0x40000000U)
#define CMC_SSRS_SRR_SHIFT                       (30U)
/*! SRR - Secure enclave Reset Request
 *  0b0..Reset not generated by SRR.
 *  0b1..Reset generated by SRR.
 */
#define CMC_SSRS_SRR(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SRR_SHIFT)) & CMC_SSRS_SRR_MASK)

#define CMC_SSRS_SFF_MASK                        (0x80000000U)
#define CMC_SSRS_SFF_SHIFT                       (31U)
/*! SFF - Secure enclave System Fail Reset
 *  0b0..Reset not generated by SFF.
 *  0b1..Reset generated by SFF.
 */
#define CMC_SSRS_SFF(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SFF_SHIFT)) & CMC_SSRS_SFF_MASK)
/*! @} */

/*! @name SRIE - System Reset Interrupt Enable */
/*! @{ */

#define CMC_SRIE_ISP_AP_MASK                     (0x200U)
#define CMC_SRIE_ISP_AP_SHIFT                    (9U)
/*! ISP_AP - In-System Programming Access Port Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_ISP_AP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_ISP_AP_SHIFT)) & CMC_SRIE_ISP_AP_MASK)

#define CMC_SRIE_LPACK_MASK                      (0x800U)
#define CMC_SRIE_LPACK_SHIFT                     (11U)
/*! LPACK - Low Power Acknowledge Timeout Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_LPACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LPACK_SHIFT)) & CMC_SRIE_LPACK_MASK)

#define CMC_SRIE_WDOG0_MASK                      (0x2000U)
#define CMC_SRIE_WDOG0_SHIFT                     (13U)
/*! WDOG0 - Watchdog 0 Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_WDOG0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WDOG0_SHIFT)) & CMC_SRIE_WDOG0_MASK)

#define CMC_SRIE_SW_MASK                         (0x4000U)
#define CMC_SRIE_SW_SHIFT                        (14U)
/*! SW - Software Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_SW(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SW_SHIFT)) & CMC_SRIE_SW_MASK)

#define CMC_SRIE_LOCKUP_MASK                     (0x8000U)
#define CMC_SRIE_LOCKUP_SHIFT                    (15U)
/*! LOCKUP - Lockup Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LOCKUP_SHIFT)) & CMC_SRIE_LOCKUP_MASK)

#define CMC_SRIE_AD_MU_MASK                      (0x10000U)
#define CMC_SRIE_AD_MU_SHIFT                     (16U)
/*! AD_MU - Application Domain MU System Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_AD_MU(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_AD_MU_SHIFT)) & CMC_SRIE_AD_MU_MASK)

#define CMC_SRIE_WDOG_S_RTD_MASK                 (0x2000000U)
#define CMC_SRIE_WDOG_S_RTD_SHIFT                (25U)
/*! WDOG_S_RTD - Watchdog 1 Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_WDOG_S_RTD(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WDOG_S_RTD_SHIFT)) & CMC_SRIE_WDOG_S_RTD_MASK)

#define CMC_SRIE_WDOG5_MASK                      (0x4000000U)
#define CMC_SRIE_WDOG5_SHIFT                     (26U)
/*! WDOG5 - Watchdog 5 Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_WDOG5(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WDOG5_SHIFT)) & CMC_SRIE_WDOG5_MASK)

#define CMC_SRIE_WDOG_FUSION_MASK                (0x8000000U)
#define CMC_SRIE_WDOG_FUSION_SHIFT               (27U)
/*! WDOG_FUSION - Watchdog 2 Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_WDOG_FUSION(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WDOG_FUSION_SHIFT)) & CMC_SRIE_WDOG_FUSION_MASK)
/*! @} */

/*! @name SRIF - System Reset Interrupt Flag */
/*! @{ */

#define CMC_SRIF_ISP_AP_MASK                     (0x200U)
#define CMC_SRIF_ISP_AP_SHIFT                    (9U)
/*! ISP_AP - In-System Programming Access Port Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_ISP_AP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_ISP_AP_SHIFT)) & CMC_SRIF_ISP_AP_MASK)

#define CMC_SRIF_LPACK_MASK                      (0x800U)
#define CMC_SRIF_LPACK_SHIFT                     (11U)
/*! LPACK - Low Power Acknowledge Timeout Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_LPACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LPACK_SHIFT)) & CMC_SRIF_LPACK_MASK)

#define CMC_SRIF_WDOG0_MASK                      (0x2000U)
#define CMC_SRIF_WDOG0_SHIFT                     (13U)
/*! WDOG0 - Watchdog 0 Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_WDOG0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WDOG0_SHIFT)) & CMC_SRIF_WDOG0_MASK)

#define CMC_SRIF_SW_MASK                         (0x4000U)
#define CMC_SRIF_SW_SHIFT                        (14U)
/*! SW - Software Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_SW(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_SW_SHIFT)) & CMC_SRIF_SW_MASK)

#define CMC_SRIF_LOCKUP_MASK                     (0x8000U)
#define CMC_SRIF_LOCKUP_SHIFT                    (15U)
/*! LOCKUP - Lockup Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LOCKUP_SHIFT)) & CMC_SRIF_LOCKUP_MASK)

#define CMC_SRIF_AD_MU_MASK                      (0x10000U)
#define CMC_SRIF_AD_MU_SHIFT                     (16U)
/*! AD_MU - Application Domain MU System Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_AD_MU(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_AD_MU_SHIFT)) & CMC_SRIF_AD_MU_MASK)

#define CMC_SRIF_WDOG_S_RTD_MASK                 (0x2000000U)
#define CMC_SRIF_WDOG_S_RTD_SHIFT                (25U)
/*! WDOG_S_RTD - Watchdog 1 Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_WDOG_S_RTD(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WDOG_S_RTD_SHIFT)) & CMC_SRIF_WDOG_S_RTD_MASK)

#define CMC_SRIF_WDOG5_MASK                      (0x4000000U)
#define CMC_SRIF_WDOG5_SHIFT                     (26U)
/*! WDOG5 - Watchdog 5 Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_WDOG5(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WDOG5_SHIFT)) & CMC_SRIF_WDOG5_MASK)

#define CMC_SRIF_WDOG_FUSION_MASK                (0x8000000U)
#define CMC_SRIF_WDOG_FUSION_SHIFT               (27U)
/*! WDOG_FUSION - Watchdog 2 Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_WDOG_FUSION(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WDOG_FUSION_SHIFT)) & CMC_SRIF_WDOG_FUSION_MASK)
/*! @} */

/*! @name MR - Mode Register */
/*! @{ */

#define CMC_MR_BOOTCFG_MASK                      (0xFFFFFFFFU)
#define CMC_MR_BOOTCFG_SHIFT                     (0U)
/*! BOOTCFG - Boot Configuration */
#define CMC_MR_BOOTCFG(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_MR_BOOTCFG_SHIFT)) & CMC_MR_BOOTCFG_MASK)
/*! @} */

/* The count of CMC_MR */
#define CMC_MR_COUNT                             (1U)

/*! @name FM - Force Mode Register */
/*! @{ */

#define CMC_FM_FORCECFG_MASK                     (0xFFFFFFFFU)
#define CMC_FM_FORCECFG_SHIFT                    (0U)
/*! FORCECFG - Boot Configuration
 *  0b00000000000000000000000000000000..No effect.
 *  0b00000000000000000000000000000001..Assert corresponding bit in Mode Register on next system reset.
 */
#define CMC_FM_FORCECFG(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_FM_FORCECFG_SHIFT)) & CMC_FM_FORCECFG_MASK)
/*! @} */

/* The count of CMC_FM */
#define CMC_FM_COUNT                             (1U)

/*! @name CORECTL - Core Control Register */
/*! @{ */

#define CMC_CORECTL_NPIE_MASK                    (0x1U)
#define CMC_CORECTL_NPIE_SHIFT                   (0U)
/*! NPIE - Non maskable Pin Interrupt Enable
 *  0b0..Pin interrupt disabled
 *  0b1..Pin interrupt enabled
 */
#define CMC_CORECTL_NPIE(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_CORECTL_NPIE_SHIFT)) & CMC_CORECTL_NPIE_MASK)
/*! @} */

/*! @name DBGCTL - Debug Control Register */
/*! @{ */

#define CMC_DBGCTL_SOD_MASK                      (0x1U)
#define CMC_DBGCTL_SOD_SHIFT                     (0U)
/*! SOD - Sleep Or Debug
 *  0b0..Debug remains enabled when Core is sleeping.
 *  0b1..Debug is disabled when Core is sleeping.
 */
#define CMC_DBGCTL_SOD(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_DBGCTL_SOD_SHIFT)) & CMC_DBGCTL_SOD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CMC_Register_Masks */


/* CMC - Peripheral instance base addresses */
/** Peripheral CMC_RTD base address */
#define CMC_RTD_BASE                             (0x28025000u)
/** Peripheral CMC_RTD base pointer */
#define CMC_RTD                                  ((CMC_Type *)CMC_RTD_BASE)
/** Array initializer of CMC peripheral base addresses */
#define CMC_BASE_ADDRS                           { CMC_RTD_BASE }
/** Array initializer of CMC peripheral base pointers */
#define CMC_BASE_PTRS                            { CMC_RTD }
/* Backward compatibility */
 #define CMC_SRS_WDOG_HIFI4_MASK                 CMC_SRS_WDOG5_MASK
 #define CMC_SRS_WDOG_HIFI4_SHIFT                CMC_SRS_WDOG5_SHIFT
 #define CMC_SRS_WDOG_HIFI4(x)                   CMC_SRS_WDOG5(x)
 #define CMC_SSRS_WDOG_HIFI4_MASK                CMC_SSRS_WDOG5_MASK
 #define CMC_SSRS_WDOG_HIFI4_SHIFT               CMC_SSRS_WDOG5_SHIFT
 #define CMC_SSRS_WDOG_HIFI4(x)                  CMC_SSRS_WDOG5(x)
 #define CMC_SRIE_WDOG_HIFI4_MASK                CMC_SRIE_WDOG5_MASK
 #define CMC_SRIE_WDOG_HIFI4_SHIFT               CMC_SRIE_WDOG5_SHIFT
 #define CMC_SRIE_WDOG_HIFI4(x)                  CMC_SRIE_WDOG5(x)
 #define CMC_SRIF_WDOG_HIFI4_MASK                CMC_SRIF_WDOG5_MASK
 #define CMC_SRIF_WDOG_HIFI4_SHIFT               CMC_SRIF_WDOG5_SHIFT
 #define CMC_SRIF_WDOG_HIFI4(x)                  CMC_SRIF_WDOG5(x)


/*!
 * @}
 */ /* end of group CMC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CMC_AD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CMC_AD_Peripheral_Access_Layer CMC_AD Peripheral Access Layer
 * @{
 */

/** CMC_AD - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __IO uint32_t CKCTRL;                            /**< Clock Control Register, offset: 0x10 */
  __IO uint32_t CKSTAT;                            /**< Clock Status Register, offset: 0x14 */
  __IO uint32_t AD_PMPROT;                         /**< Power Mode Protection Register, offset: 0x18 */
       uint8_t RESERVED_1[4];
  __IO uint32_t AD_PMCTRL;                         /**< AD Power Mode Control Register, offset: 0x20 */
       uint8_t RESERVED_2[44];
  __IO uint32_t AD_A35CORE0_LPMODE;                /**< AD A35 CORE0 Low Power Mode Control Register, offset: 0x50 */
  __IO uint32_t AD_A35CORE1_LPMODE;                /**< AD A35 CORE1 Low Power Mode Control Register, offset: 0x54 */
       uint8_t RESERVED_3[24];
  __IO uint32_t AD_PSDORF;                         /**< Application Domain Power Switch Domain Out of Reset Interrupt Flag Register, offset: 0x70 */
  __IO uint32_t AD_PSDORIE;                        /**< Application Domain Power Switch Domain Out of Reset Interrupt Enable Register, offset: 0x74 */
  __I  uint32_t AD_PSDS;                           /**< Application Domain Power Switch Domain Status Register, offset: 0x78 */
       uint8_t RESERVED_4[4];
  __I  uint32_t SRS;                               /**< System Reset Status Register, offset: 0x80 */
       uint8_t RESERVED_5[4];
  __IO uint32_t SSRS;                              /**< Sticky System Reset Status Register, offset: 0x88 */
  __IO uint32_t SRIE;                              /**< System Reset Interrupt Enable Register, offset: 0x8C */
  __IO uint32_t SRIF;                              /**< System Reset Interrupt Flag Register, offset: 0x90 */
       uint8_t RESERVED_6[12];
  __IO uint32_t MR[1];                             /**< Mode Register, array offset: 0xA0, array step: 0x4 */
       uint8_t RESERVED_7[12];
  __IO uint32_t FM[1];                             /**< Force Mode Register, array offset: 0xB0, array step: 0x4 */
       uint8_t RESERVED_8[92];
  __IO uint32_t CORECTL;                           /**< Core Control Register, offset: 0x110 */
       uint8_t RESERVED_9[12];
  __IO uint32_t DBGCTL;                            /**< Debug Control Register, offset: 0x120 */
} CMC_AD_Type;

/* ----------------------------------------------------------------------------
   -- CMC_AD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CMC_AD_Register_Masks CMC_AD Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define CMC_AD_VERID_FEATURE_MASK                (0xFFFFU)
#define CMC_AD_VERID_FEATURE_SHIFT               (0U)
/*! FEATURE - Feature Specification Number */
#define CMC_AD_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_AD_VERID_FEATURE_SHIFT)) & CMC_AD_VERID_FEATURE_MASK)

#define CMC_AD_VERID_MINOR_MASK                  (0xFF0000U)
#define CMC_AD_VERID_MINOR_SHIFT                 (16U)
/*! MINOR - Minor Version Number */
#define CMC_AD_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_AD_VERID_MINOR_SHIFT)) & CMC_AD_VERID_MINOR_MASK)

#define CMC_AD_VERID_MAJOR_MASK                  (0xFF000000U)
#define CMC_AD_VERID_MAJOR_SHIFT                 (24U)
/*! MAJOR - Major Version Number */
#define CMC_AD_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_AD_VERID_MAJOR_SHIFT)) & CMC_AD_VERID_MAJOR_MASK)
/*! @} */

/*! @name CKCTRL - Clock Control Register */
/*! @{ */

#define CMC_AD_CKCTRL_CKMODE_MASK                (0x7U)
#define CMC_AD_CKCTRL_CKMODE_SHIFT               (0U)
/*! CKMODE - Clocking Mode
 *  0b000..No clock gating.
 *  0b001..Core clock is gated.
 *  0b011..Core and platform clocks are gated.
 *  0b111..Core, platform, bus and slow clocks are gated.
 */
#define CMC_AD_CKCTRL_CKMODE(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_AD_CKCTRL_CKMODE_SHIFT)) & CMC_AD_CKCTRL_CKMODE_MASK)

#define CMC_AD_CKCTRL_LOCK_MASK                  (0x80000000U)
#define CMC_AD_CKCTRL_LOCK_SHIFT                 (31U)
/*! LOCK - Lock Register
 *  0b0..Register writes are allowed.
 *  0b1..Register writes are blocked.
 */
#define CMC_AD_CKCTRL_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_AD_CKCTRL_LOCK_SHIFT)) & CMC_AD_CKCTRL_LOCK_MASK)
/*! @} */

/*! @name CKSTAT - Clock Status Register */
/*! @{ */

#define CMC_AD_CKSTAT_CKMODE_MASK                (0x7U)
#define CMC_AD_CKSTAT_CKMODE_SHIFT               (0U)
/*! CKMODE - Low Power Status
 *  0b000..Core clock not gated.
 *  0b001..Core clock was gated
 *  0b011..Core and platform clocks were gated
 *  0b111..Core, platform, bus and slow clocks were gated
 */
#define CMC_AD_CKSTAT_CKMODE(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_AD_CKSTAT_CKMODE_SHIFT)) & CMC_AD_CKSTAT_CKMODE_MASK)

#define CMC_AD_CKSTAT_WAKEUP_MASK                (0x3F00U)
#define CMC_AD_CKSTAT_WAKEUP_SHIFT               (8U)
/*! WAKEUP - Wakeup Source */
#define CMC_AD_CKSTAT_WAKEUP(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_AD_CKSTAT_WAKEUP_SHIFT)) & CMC_AD_CKSTAT_WAKEUP_MASK)

#define CMC_AD_CKSTAT_VALID_MASK                 (0x80000000U)
#define CMC_AD_CKSTAT_VALID_SHIFT                (31U)
/*! VALID - Clock Status Valid
 *  0b0..Core clock not gated.
 *  0b1..Core clock was gated due to low power mode entry.
 */
#define CMC_AD_CKSTAT_VALID(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_AD_CKSTAT_VALID_SHIFT)) & CMC_AD_CKSTAT_VALID_MASK)
/*! @} */

/*! @name AD_PMPROT - Power Mode Protection Register */
/*! @{ */

#define CMC_AD_AD_PMPROT_AS_MASK                 (0x1U)
#define CMC_AD_AD_PMPROT_AS_SHIFT                (0U)
/*! AS - Allow Sleep
 *  0b0..Sleep is not allowed
 *  0b1..Sleep is allowed
 */
#define CMC_AD_AD_PMPROT_AS(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PMPROT_AS_SHIFT)) & CMC_AD_AD_PMPROT_AS_MASK)

#define CMC_AD_AD_PMPROT_ADS_MASK                (0x2U)
#define CMC_AD_AD_PMPROT_ADS_SHIFT               (1U)
/*! ADS - Allow Deep Sleep
 *  0b0..Deep Sleep is not allowed
 *  0b1..Deep Sleep is allowed
 */
#define CMC_AD_AD_PMPROT_ADS(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PMPROT_ADS_SHIFT)) & CMC_AD_AD_PMPROT_ADS_MASK)

#define CMC_AD_AD_PMPROT_APA_MASK                (0x4U)
#define CMC_AD_AD_PMPROT_APA_SHIFT               (2U)
/*! APA - Allow Partial Active
 *  0b0..Partial Active is not allowed
 *  0b1..Partial Active is allowed
 */
#define CMC_AD_AD_PMPROT_APA(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PMPROT_APA_SHIFT)) & CMC_AD_AD_PMPROT_APA_MASK)

#define CMC_AD_AD_PMPROT_APD_MASK                (0x8U)
#define CMC_AD_AD_PMPROT_APD_SHIFT               (3U)
/*! APD - Allow Power Down
 *  0b0..Power Down is not allowed
 *  0b1..Power Down is allowed
 */
#define CMC_AD_AD_PMPROT_APD(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PMPROT_APD_SHIFT)) & CMC_AD_AD_PMPROT_APD_MASK)

#define CMC_AD_AD_PMPROT_ADPD_MASK               (0x10U)
#define CMC_AD_AD_PMPROT_ADPD_SHIFT              (4U)
/*! ADPD - Allow Deep Power Down
 *  0b0..Deep Power Down is not allowed
 *  0b1..Deep Power Down is allowed
 */
#define CMC_AD_AD_PMPROT_ADPD(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PMPROT_ADPD_SHIFT)) & CMC_AD_AD_PMPROT_ADPD_MASK)

#define CMC_AD_AD_PMPROT_AHLD_MASK               (0x20U)
#define CMC_AD_AD_PMPROT_AHLD_SHIFT              (5U)
/*! AHLD - Allow Hold
 *  0b0..Hold is not allowed
 *  0b1..Hold is allowed
 */
#define CMC_AD_AD_PMPROT_AHLD(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PMPROT_AHLD_SHIFT)) & CMC_AD_AD_PMPROT_AHLD_MASK)

#define CMC_AD_AD_PMPROT_LOCK_MASK               (0x80000000U)
#define CMC_AD_AD_PMPROT_LOCK_SHIFT              (31U)
/*! LOCK - Lock Register
 *  0b0..Register writes are allowed.
 *  0b1..Register writes are blocked.
 */
#define CMC_AD_AD_PMPROT_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PMPROT_LOCK_SHIFT)) & CMC_AD_AD_PMPROT_LOCK_MASK)
/*! @} */

/*! @name AD_PMCTRL - AD Power Mode Control Register */
/*! @{ */

#define CMC_AD_AD_PMCTRL_AD_LPMODE_MASK          (0x3FU)
#define CMC_AD_AD_PMCTRL_AD_LPMODE_SHIFT         (0U)
/*! AD_LPMODE - Low Power Mode
 *  0b000000..Active
 *  0b000001..Sleep
 *  0b000011..Deep Sleep
 *  0b000111..Partial Active
 *  0b001111..Power Down
 *  0b011111..Deep Power Down
 *  0b111111..Hold
 */
#define CMC_AD_AD_PMCTRL_AD_LPMODE(x)            (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PMCTRL_AD_LPMODE_SHIFT)) & CMC_AD_AD_PMCTRL_AD_LPMODE_MASK)
/*! @} */

/*! @name AD_A35CORE0_LPMODE - AD A35 CORE0 Low Power Mode Control Register */
/*! @{ */

#define CMC_AD_AD_A35CORE0_LPMODE_A35CORE0_LPMODE_MASK (0x3U)
#define CMC_AD_AD_A35CORE0_LPMODE_A35CORE0_LPMODE_SHIFT (0U)
/*! A35CORE0_LPMODE - Low Power Mode
 *  0b00..A35 CORE0 Active(ACT)
 *  0b01..A35 CORE0 Standby(STDB)
 *  0b11..A35 CORE0 PowerDown(PD)
 */
#define CMC_AD_AD_A35CORE0_LPMODE_A35CORE0_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_A35CORE0_LPMODE_A35CORE0_LPMODE_SHIFT)) & CMC_AD_AD_A35CORE0_LPMODE_A35CORE0_LPMODE_MASK)
/*! @} */

/*! @name AD_A35CORE1_LPMODE - AD A35 CORE1 Low Power Mode Control Register */
/*! @{ */

#define CMC_AD_AD_A35CORE1_LPMODE_A35CORE1_LPMODE_MASK (0x3U)
#define CMC_AD_AD_A35CORE1_LPMODE_A35CORE1_LPMODE_SHIFT (0U)
/*! A35CORE1_LPMODE - Low Power Mode
 *  0b00..A35 CORE1 Active(ACT)
 *  0b01..A35 CORE1 Standby(STDB)
 *  0b11..A35 CORE1 PowerDown(PD)
 */
#define CMC_AD_AD_A35CORE1_LPMODE_A35CORE1_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_A35CORE1_LPMODE_A35CORE1_LPMODE_SHIFT)) & CMC_AD_AD_A35CORE1_LPMODE_A35CORE1_LPMODE_MASK)
/*! @} */

/*! @name AD_PSDORF - Application Domain Power Switch Domain Out of Reset Interrupt Flag Register */
/*! @{ */

#define CMC_AD_AD_PSDORF_A35_0_MASK              (0x1U)
#define CMC_AD_AD_PSDORF_A35_0_SHIFT             (0U)
/*! A35_0 - A35_Core0 Power switch domain out of reset interrupt flag
 *  0b0..A35_Core0 Power Switch Domain in reset or user has cleared it by writing 1 to clear.
 *  0b1..A35_Core0 Power switch domain out of reset interrupt flag. This bit is asserted only once after the power switch domain exits the reset.
 */
#define CMC_AD_AD_PSDORF_A35_0(x)                (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PSDORF_A35_0_SHIFT)) & CMC_AD_AD_PSDORF_A35_0_MASK)

#define CMC_AD_AD_PSDORF_A35_1_MASK              (0x2U)
#define CMC_AD_AD_PSDORF_A35_1_SHIFT             (1U)
/*! A35_1 - A35_Core1 Power switch domain out of reset interrupt flag
 *  0b0..A35_Core1 Power Switch Domain in reset or user has cleared it by writing 1 to clear.
 *  0b1..A35_Core1 Power switch domain out of reset interrupt flag. This bit is asserted only once after the power switch domain exits the reset.
 */
#define CMC_AD_AD_PSDORF_A35_1(x)                (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PSDORF_A35_1_SHIFT)) & CMC_AD_AD_PSDORF_A35_1_MASK)

#define CMC_AD_AD_PSDORF_AD_PERIPH_MASK          (0x10U)
#define CMC_AD_AD_PSDORF_AD_PERIPH_SHIFT         (4U)
/*! AD_PERIPH - AD_PERIPH Power switch domain out of reset interrupt flag
 *  0b0..AD_PERIPH Power Switch Domain in reset or user has cleared it by writing 1 to clear.
 *  0b1..AD_PERIPH Power switch domain out of reset interrupt flag. This bit is asserted only once after the power switch domain exits the reset.
 */
#define CMC_AD_AD_PSDORF_AD_PERIPH(x)            (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PSDORF_AD_PERIPH_SHIFT)) & CMC_AD_AD_PSDORF_AD_PERIPH_MASK)
/*! @} */

/*! @name AD_PSDORIE - Application Domain Power Switch Domain Out of Reset Interrupt Enable Register */
/*! @{ */

#define CMC_AD_AD_PSDORIE_A35_0_MASK             (0x1U)
#define CMC_AD_AD_PSDORIE_A35_0_SHIFT            (0U)
/*! A35_0 - A35_Core0 Power Switch Domain Out of Reset Interrupt Enable
 *  0b0..A35_Core0 Power Switch does not generate interrupt when domain gets out of reset.
 *  0b1..A35_Core0 Power Switch generates interrupt when domain gets out of reset.
 */
#define CMC_AD_AD_PSDORIE_A35_0(x)               (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PSDORIE_A35_0_SHIFT)) & CMC_AD_AD_PSDORIE_A35_0_MASK)

#define CMC_AD_AD_PSDORIE_A35_1_MASK             (0x2U)
#define CMC_AD_AD_PSDORIE_A35_1_SHIFT            (1U)
/*! A35_1 - A35_Core1 Power Switch Domain Out of Reset Interrupt Enable
 *  0b0..A35_Core1 Power Switch does not generate interrupt when domain gets out of reset.
 *  0b1..A35_Core1 Power Switch generates interrupt when domain gets out of reset.
 */
#define CMC_AD_AD_PSDORIE_A35_1(x)               (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PSDORIE_A35_1_SHIFT)) & CMC_AD_AD_PSDORIE_A35_1_MASK)

#define CMC_AD_AD_PSDORIE_AD_PERIPH_MASK         (0x10U)
#define CMC_AD_AD_PSDORIE_AD_PERIPH_SHIFT        (4U)
/*! AD_PERIPH - AD_PERIPH Power Switch Domain Out of Reset Interrupt Enable
 *  0b0..AD_PERIPH Power Switch does not generate interrupt when domain gets out of reset.
 *  0b1..AD_PERIPH Power Switch generates interrupt when domain gets out of reset.
 */
#define CMC_AD_AD_PSDORIE_AD_PERIPH(x)           (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PSDORIE_AD_PERIPH_SHIFT)) & CMC_AD_AD_PSDORIE_AD_PERIPH_MASK)
/*! @} */

/*! @name AD_PSDS - Application Domain Power Switch Domain Status Register */
/*! @{ */

#define CMC_AD_AD_PSDS_A35_0_MASK                (0x1U)
#define CMC_AD_AD_PSDS_A35_0_SHIFT               (0U)
/*! A35_0 - A35_Core0 Power Switch Domain Status
 *  0b0..A35_Core0 Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..A35_Core0 Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_AD_AD_PSDS_A35_0(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PSDS_A35_0_SHIFT)) & CMC_AD_AD_PSDS_A35_0_MASK)

#define CMC_AD_AD_PSDS_A35_1_MASK                (0x2U)
#define CMC_AD_AD_PSDS_A35_1_SHIFT               (1U)
/*! A35_1 - A35_Core1 Power Switch Domain Status
 *  0b0..A35_Core1 Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..A35_Core1 Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_AD_AD_PSDS_A35_1(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PSDS_A35_1_SHIFT)) & CMC_AD_AD_PSDS_A35_1_MASK)

#define CMC_AD_AD_PSDS_L2_CACHE_MASK             (0x4U)
#define CMC_AD_AD_PSDS_L2_CACHE_SHIFT            (2U)
/*! L2_CACHE - L2 Cache Power Switch Domain Status
 *  0b0..L2 Cache Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..L2 Cache Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_AD_AD_PSDS_L2_CACHE(x)               (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PSDS_L2_CACHE_SHIFT)) & CMC_AD_AD_PSDS_L2_CACHE_MASK)

#define CMC_AD_AD_PSDS_FAST_NIC_MASK             (0x8U)
#define CMC_AD_AD_PSDS_FAST_NIC_SHIFT            (3U)
/*! FAST_NIC - Fast NIC Power Switch Domain Status
 *  0b0..Fast NIC Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..Fast NIC Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_AD_AD_PSDS_FAST_NIC(x)               (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PSDS_FAST_NIC_SHIFT)) & CMC_AD_AD_PSDS_FAST_NIC_MASK)

#define CMC_AD_AD_PSDS_AD_PERIPH_MASK            (0x10U)
#define CMC_AD_AD_PSDS_AD_PERIPH_SHIFT           (4U)
/*! AD_PERIPH - Application Power Switch Domain Status
 *  0b0..Application Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..Application Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_AD_AD_PSDS_AD_PERIPH(x)              (((uint32_t)(((uint32_t)(x)) << CMC_AD_AD_PSDS_AD_PERIPH_SHIFT)) & CMC_AD_AD_PSDS_AD_PERIPH_MASK)
/*! @} */

/*! @name SRS - System Reset Status Register */
/*! @{ */

#define CMC_AD_SRS_WAKEUP_MASK                   (0x1U)
#define CMC_AD_SRS_WAKEUP_SHIFT                  (0U)
/*! WAKEUP - Wakeup Reset
 *  0b0..Reset not generated by wakeup from Power Down or Deep Power Down mode.
 *  0b1..Reset generated by wakeup from Power Down or Deep Power Down mode.
 */
#define CMC_AD_SRS_WAKEUP(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_WAKEUP_SHIFT)) & CMC_AD_SRS_WAKEUP_MASK)

#define CMC_AD_SRS_POR_MASK                      (0x2U)
#define CMC_AD_SRS_POR_SHIFT                     (1U)
/*! POR - Power On Reset
 *  0b0..Reset not generated by POR.
 *  0b1..Reset generated by POR.
 */
#define CMC_AD_SRS_POR(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_POR_SHIFT)) & CMC_AD_SRS_POR_MASK)

#define CMC_AD_SRS_HLVD_MASK                     (0x4U)
#define CMC_AD_SRS_HLVD_SHIFT                    (2U)
/*! HLVD - High or Low Voltage Detect Reset
 *  0b0..Reset not generated by HLVD.
 *  0b1..Reset generated by HLVD.
 */
#define CMC_AD_SRS_HLVD(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_HLVD_SHIFT)) & CMC_AD_SRS_HLVD_MASK)

#define CMC_AD_SRS_WARM_MASK                     (0x10U)
#define CMC_AD_SRS_WARM_SHIFT                    (4U)
/*! WARM - Warm Reset
 *  0b0..Reset not generated by Warm Reset source.
 *  0b1..Reset generated by Warm Reset source.
 */
#define CMC_AD_SRS_WARM(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_WARM_SHIFT)) & CMC_AD_SRS_WARM_MASK)

#define CMC_AD_SRS_FATAL_MASK                    (0x20U)
#define CMC_AD_SRS_FATAL_SHIFT                   (5U)
/*! FATAL - Fatal Reset
 *  0b0..Reset was not generated by a fatal reset source.
 *  0b1..Reset was generated by a fatal reset source.
 */
#define CMC_AD_SRS_FATAL(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_FATAL_SHIFT)) & CMC_AD_SRS_FATAL_MASK)

#define CMC_AD_SRS_PIN_MASK                      (0x100U)
#define CMC_AD_SRS_PIN_SHIFT                     (8U)
/*! PIN - Pin Reset
 *  0b0..Reset was not generated from the assertion of RESET_b pin.
 *  0b1..Reset was generated from the assertion of RESET_b pin.
 */
#define CMC_AD_SRS_PIN(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_PIN_SHIFT)) & CMC_AD_SRS_PIN_MASK)

#define CMC_AD_SRS_RSTACK_MASK                   (0x400U)
#define CMC_AD_SRS_RSTACK_SHIFT                  (10U)
/*! RSTACK - Reset Timeout
 *  0b0..Reset not generated from Reset Controller Timeout.
 *  0b1..Reset generated from Reset Controller Timeout.
 */
#define CMC_AD_SRS_RSTACK(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_RSTACK_SHIFT)) & CMC_AD_SRS_RSTACK_MASK)

#define CMC_AD_SRS_LPACK_MASK                    (0x800U)
#define CMC_AD_SRS_LPACK_SHIFT                   (11U)
/*! LPACK - Low Power Acknowledge Timeout Reset
 *  0b0..Reset not generated by Low Power Acknowledge Timeout.
 *  0b1..Reset generated by Low Power Acknowledge Timeout.
 */
#define CMC_AD_SRS_LPACK(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_LPACK_SHIFT)) & CMC_AD_SRS_LPACK_MASK)

#define CMC_AD_SRS_WDOG_AD_MASK                  (0x2000U)
#define CMC_AD_SRS_WDOG_AD_SHIFT                 (13U)
/*! WDOG_AD - Watchdog 3 Reset
 *  0b0..Reset is not generated from the WatchDog 0 timeout.
 *  0b1..Reset is generated from the WatchDog 0 timeout.
 */
#define CMC_AD_SRS_WDOG_AD(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_WDOG_AD_SHIFT)) & CMC_AD_SRS_WDOG_AD_MASK)

#define CMC_AD_SRS_SW_MASK                       (0x4000U)
#define CMC_AD_SRS_SW_SHIFT                      (14U)
/*! SW - Software Reset (SIM)
 *  0b0..Reset not generated by software request from core.
 *  0b1..Reset generated by software request from core.
 */
#define CMC_AD_SRS_SW(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_SW_SHIFT)) & CMC_AD_SRS_SW_MASK)

#define CMC_AD_SRS_GIC_ECC_MASK                  (0x8000U)
#define CMC_AD_SRS_GIC_ECC_SHIFT                 (15U)
/*! GIC_ECC - Interrupt SRAM Controller ECC Error
 *  0b0..Reset not generated by GIC SRAM ECC error.
 *  0b1..Reset generated by GIC SRAM ECC error.
 */
#define CMC_AD_SRS_GIC_ECC(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_GIC_ECC_SHIFT)) & CMC_AD_SRS_GIC_ECC_MASK)

#define CMC_AD_SRS_RTD_MU_MASK                   (0x10000U)
#define CMC_AD_SRS_RTD_MU_SHIFT                  (16U)
/*! RTD_MU - Real Time Domain MU System Reset
 *  0b0..Reset not generated from RTD_MU reset source.
 *  0b1..Reset generated from RTD_MU reset source.
 */
#define CMC_AD_SRS_RTD_MU(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_RTD_MU_SHIFT)) & CMC_AD_SRS_RTD_MU_MASK)

#define CMC_AD_SRS_AD_CGC_LOS_MASK               (0x80000U)
#define CMC_AD_SRS_AD_CGC_LOS_SHIFT              (19U)
/*! AD_CGC_LOS - AD CGC Loss Of Sync
 *  0b0..Reset not generated from CGC_LOS system reset source.
 *  0b1..Reset generated from CGC_LOS system reset source.
 */
#define CMC_AD_SRS_AD_CGC_LOS(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_AD_CGC_LOS_SHIFT)) & CMC_AD_SRS_AD_CGC_LOS_MASK)

#define CMC_AD_SRS_LPAV_CGC_LOS_MASK             (0x400000U)
#define CMC_AD_SRS_LPAV_CGC_LOS_SHIFT            (22U)
/*! LPAV_CGC_LOS - LPAV CGC Loss Of Sync
 *  0b0..Reset not generated from LPAV_CGC_LOS system reset source.
 *  0b1..Reset generated from LPAV_CGC_LOS system reset source.
 */
#define CMC_AD_SRS_LPAV_CGC_LOS(x)               (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_LPAV_CGC_LOS_SHIFT)) & CMC_AD_SRS_LPAV_CGC_LOS_MASK)

#define CMC_AD_SRS_UPOWER_MASK                   (0x800000U)
#define CMC_AD_SRS_UPOWER_SHIFT                  (23U)
/*! uPOWER - uPOWER WDOG System Reset
 *  0b0..Reset not generated by uPOWER WDOG timeout.
 *  0b1..Reset generated by uPOWER WDOG timeout.
 */
#define CMC_AD_SRS_UPOWER(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_UPOWER_SHIFT)) & CMC_AD_SRS_UPOWER_MASK)

#define CMC_AD_SRS_WDOG_S_AD_MASK                (0x2000000U)
#define CMC_AD_SRS_WDOG_S_AD_SHIFT               (25U)
/*! WDOG_S_AD - Watchdog 4 Reset
 *  0b0..Reset is not generated from the WDOG_S_AD timeout.
 *  0b1..Reset is generated from the WDOG_S_AD timeout.
 */
#define CMC_AD_SRS_WDOG_S_AD(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_WDOG_S_AD_SHIFT)) & CMC_AD_SRS_WDOG_S_AD_MASK)

#define CMC_AD_SRS_WDOG5_MASK                    (0x4000000U)
#define CMC_AD_SRS_WDOG5_SHIFT                   (26U)
/*! WDOG5 - Watchdog 5 Reset
 *  0b0..Reset is not generated from the WDOG5 timeout.
 *  0b1..Reset is generated from the WDOG5 timeout.
 */
#define CMC_AD_SRS_WDOG5(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRS_WDOG5_SHIFT)) & CMC_AD_SRS_WDOG5_MASK)
/*! @} */

/*! @name SSRS - Sticky System Reset Status Register */
/*! @{ */

#define CMC_AD_SSRS_WAKEUP_MASK                  (0x1U)
#define CMC_AD_SSRS_WAKEUP_SHIFT                 (0U)
/*! WAKEUP - Wakeup Reset
 *  0b0..Reset not generated by wakeup from DPD mode.
 *  0b1..Reset generated by wakeup from DPD mode.
 */
#define CMC_AD_SSRS_WAKEUP(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_WAKEUP_SHIFT)) & CMC_AD_SSRS_WAKEUP_MASK)

#define CMC_AD_SSRS_POR_MASK                     (0x2U)
#define CMC_AD_SSRS_POR_SHIFT                    (1U)
/*! POR - Power On Reset
 *  0b0..Reset not generated by POR.
 *  0b1..Reset generated by POR.
 */
#define CMC_AD_SSRS_POR(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_POR_SHIFT)) & CMC_AD_SSRS_POR_MASK)

#define CMC_AD_SSRS_HLVD_MASK                    (0x4U)
#define CMC_AD_SSRS_HLVD_SHIFT                   (2U)
/*! HLVD - High or Low Voltage Detect Reset
 *  0b0..Reset not generated by HLVD.
 *  0b1..Reset generated by HLVD.
 */
#define CMC_AD_SSRS_HLVD(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_HLVD_SHIFT)) & CMC_AD_SSRS_HLVD_MASK)

#define CMC_AD_SSRS_WARM_MASK                    (0x10U)
#define CMC_AD_SSRS_WARM_SHIFT                   (4U)
/*! WARM - Warm Reset
 *  0b0..Reset not generated by warm reset source.
 *  0b1..Reset generated by warm reset source.
 */
#define CMC_AD_SSRS_WARM(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_WARM_SHIFT)) & CMC_AD_SSRS_WARM_MASK)

#define CMC_AD_SSRS_FATAL_MASK                   (0x20U)
#define CMC_AD_SSRS_FATAL_SHIFT                  (5U)
/*! FATAL - Fatal Reset
 *  0b0..Reset was not generated by a fatal reset source.
 *  0b1..Reset was generated by a fatal reset source.
 */
#define CMC_AD_SSRS_FATAL(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_FATAL_SHIFT)) & CMC_AD_SSRS_FATAL_MASK)

#define CMC_AD_SSRS_PIN_MASK                     (0x100U)
#define CMC_AD_SSRS_PIN_SHIFT                    (8U)
/*! PIN - Pin Reset
 *  0b0..Reset was not generated from the RESET_B pin.
 *  0b1..Reset was generated from the RESET_B pin.
 */
#define CMC_AD_SSRS_PIN(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_PIN_SHIFT)) & CMC_AD_SSRS_PIN_MASK)

#define CMC_AD_SSRS_RSTACK_MASK                  (0x400U)
#define CMC_AD_SSRS_RSTACK_SHIFT                 (10U)
/*! RSTACK - Reset Timeout
 *  0b0..Reset not generated from Reset Controller Timeout.
 *  0b1..Reset generated from Reset Controller Timeout.
 */
#define CMC_AD_SSRS_RSTACK(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_RSTACK_SHIFT)) & CMC_AD_SSRS_RSTACK_MASK)

#define CMC_AD_SSRS_LPACK_MASK                   (0x800U)
#define CMC_AD_SSRS_LPACK_SHIFT                  (11U)
/*! LPACK - Low Power Acknowledge Timeout Reset
 *  0b0..Reset not generated by Low Power Acknowledge Timeout.
 *  0b1..Reset generated by Low Power Acknowledge Timeout.
 */
#define CMC_AD_SSRS_LPACK(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_LPACK_SHIFT)) & CMC_AD_SSRS_LPACK_MASK)

#define CMC_AD_SSRS_WDOG_AD_MASK                 (0x2000U)
#define CMC_AD_SSRS_WDOG_AD_SHIFT                (13U)
/*! WDOG_AD - Watchdog 3 Reset
 *  0b0..Reset is not generated from the WatchDog 0 timeout.
 *  0b1..Reset is generated from the WatchDog 0 timeout.
 */
#define CMC_AD_SSRS_WDOG_AD(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_WDOG_AD_SHIFT)) & CMC_AD_SSRS_WDOG_AD_MASK)

#define CMC_AD_SSRS_SW_MASK                      (0x4000U)
#define CMC_AD_SSRS_SW_SHIFT                     (14U)
/*! SW - Software Reset
 *  0b0..Reset not generated by software request from core.
 *  0b1..Reset generated by software request from core.
 */
#define CMC_AD_SSRS_SW(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_SW_SHIFT)) & CMC_AD_SSRS_SW_MASK)

#define CMC_AD_SSRS_GIC_ECC_MASK                 (0x8000U)
#define CMC_AD_SSRS_GIC_ECC_SHIFT                (15U)
/*! GIC_ECC - Interrupt SRAM Controller ECC Error
 *  0b0..Reset not generated by GIC SRAM ECC error.
 *  0b1..Reset generated by GIC SRAM ECC error.
 */
#define CMC_AD_SSRS_GIC_ECC(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_GIC_ECC_SHIFT)) & CMC_AD_SSRS_GIC_ECC_MASK)

#define CMC_AD_SSRS_RTD_MU_MASK                  (0x10000U)
#define CMC_AD_SSRS_RTD_MU_SHIFT                 (16U)
/*! RTD_MU - Real Time Domain MU Reset
 *  0b0..Reset not generated from Core0 reset source.
 *  0b1..Reset generated from Core0 reset source.
 */
#define CMC_AD_SSRS_RTD_MU(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_RTD_MU_SHIFT)) & CMC_AD_SSRS_RTD_MU_MASK)

#define CMC_AD_SSRS_AD_CGC_LOS_MASK              (0x80000U)
#define CMC_AD_SSRS_AD_CGC_LOS_SHIFT             (19U)
/*! AD_CGC_LOS - AD CGC Loss Of Sync
 *  0b0..Reset not generated from CGC_LOS system reset source.
 *  0b1..Reset generated from CGC_LOS system reset source.
 */
#define CMC_AD_SSRS_AD_CGC_LOS(x)                (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_AD_CGC_LOS_SHIFT)) & CMC_AD_SSRS_AD_CGC_LOS_MASK)

#define CMC_AD_SSRS_LPAV_CGC_LOS_MASK            (0x400000U)
#define CMC_AD_SSRS_LPAV_CGC_LOS_SHIFT           (22U)
/*! LPAV_CGC_LOS - LPAV CGC Loss Of Sync
 *  0b0..Reset not generated from LPAV_CGC_LOS system reset source.
 *  0b1..Reset generated from LPAV_CGC_LOS system reset source.
 */
#define CMC_AD_SSRS_LPAV_CGC_LOS(x)              (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_LPAV_CGC_LOS_SHIFT)) & CMC_AD_SSRS_LPAV_CGC_LOS_MASK)

#define CMC_AD_SSRS_UPOWER_MASK                  (0x800000U)
#define CMC_AD_SSRS_UPOWER_SHIFT                 (23U)
/*! uPOWER - uPOWER WDOG System Reset
 *  0b0..Reset not generated by uPOWER WDOG timeout.
 *  0b1..Reset generated by uPOWER WDOG timeout.
 */
#define CMC_AD_SSRS_UPOWER(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_UPOWER_SHIFT)) & CMC_AD_SSRS_UPOWER_MASK)

#define CMC_AD_SSRS_WDOG_S_AD_MASK               (0x2000000U)
#define CMC_AD_SSRS_WDOG_S_AD_SHIFT              (25U)
/*! WDOG_S_AD - Watchdog 4 Reset
 *  0b0..Reset is not generated from the WatchDog 1 timeout.
 *  0b1..Reset is generated from the WatchDog 1 timeout.
 */
#define CMC_AD_SSRS_WDOG_S_AD(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_WDOG_S_AD_SHIFT)) & CMC_AD_SSRS_WDOG_S_AD_MASK)

#define CMC_AD_SSRS_WDOG5_MASK                   (0x4000000U)
#define CMC_AD_SSRS_WDOG5_SHIFT                  (26U)
/*! WDOG5 - Watchdog 5 Reset
 *  0b0..Reset is not generated from the WDOG5 timeout.
 *  0b1..Reset is generated from the WDOG5 timeout.
 */
#define CMC_AD_SSRS_WDOG5(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_AD_SSRS_WDOG5_SHIFT)) & CMC_AD_SSRS_WDOG5_MASK)
/*! @} */

/*! @name SRIE - System Reset Interrupt Enable Register */
/*! @{ */

#define CMC_AD_SRIE_LPACK_MASK                   (0x800U)
#define CMC_AD_SRIE_LPACK_SHIFT                  (11U)
/*! LPACK - Low Power Acknowledge Timeout Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_AD_SRIE_LPACK(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIE_LPACK_SHIFT)) & CMC_AD_SRIE_LPACK_MASK)

#define CMC_AD_SRIE_WDOG_AD_MASK                 (0x2000U)
#define CMC_AD_SRIE_WDOG_AD_SHIFT                (13U)
/*! WDOG_AD - Watchdog_AD Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_AD_SRIE_WDOG_AD(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIE_WDOG_AD_SHIFT)) & CMC_AD_SRIE_WDOG_AD_MASK)

#define CMC_AD_SRIE_SW_MASK                      (0x4000U)
#define CMC_AD_SRIE_SW_SHIFT                     (14U)
/*! SW - Software Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_AD_SRIE_SW(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIE_SW_SHIFT)) & CMC_AD_SRIE_SW_MASK)

#define CMC_AD_SRIE_GIC_ECC_MASK                 (0x8000U)
#define CMC_AD_SRIE_GIC_ECC_SHIFT                (15U)
/*! GIC_ECC - Application domain Interrupt Controller ECC Error Event
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_AD_SRIE_GIC_ECC(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIE_GIC_ECC_SHIFT)) & CMC_AD_SRIE_GIC_ECC_MASK)

#define CMC_AD_SRIE_RTD_MU_MASK                  (0x10000U)
#define CMC_AD_SRIE_RTD_MU_SHIFT                 (16U)
/*! RTD_MU - Real Time Domain MU Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_AD_SRIE_RTD_MU(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIE_RTD_MU_SHIFT)) & CMC_AD_SRIE_RTD_MU_MASK)

#define CMC_AD_SRIE_WDOG_S_AD_MASK               (0x2000000U)
#define CMC_AD_SRIE_WDOG_S_AD_SHIFT              (25U)
/*! WDOG_S_AD - Watchdog 4 Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_AD_SRIE_WDOG_S_AD(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIE_WDOG_S_AD_SHIFT)) & CMC_AD_SRIE_WDOG_S_AD_MASK)

#define CMC_AD_SRIE_WDOG5_MASK                   (0x4000000U)
#define CMC_AD_SRIE_WDOG5_SHIFT                  (26U)
/*! WDOG5 - Watchdog 5 Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_AD_SRIE_WDOG5(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIE_WDOG5_SHIFT)) & CMC_AD_SRIE_WDOG5_MASK)
/*! @} */

/*! @name SRIF - System Reset Interrupt Flag Register */
/*! @{ */

#define CMC_AD_SRIF_LPACK_MASK                   (0x800U)
#define CMC_AD_SRIF_LPACK_SHIFT                  (11U)
/*! LPACK - Low Power Acknowledge Timeout Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_AD_SRIF_LPACK(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIF_LPACK_SHIFT)) & CMC_AD_SRIF_LPACK_MASK)

#define CMC_AD_SRIF_WDOG_AD_MASK                 (0x2000U)
#define CMC_AD_SRIF_WDOG_AD_SHIFT                (13U)
/*! WDOG_AD - Watchdog_AD Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_AD_SRIF_WDOG_AD(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIF_WDOG_AD_SHIFT)) & CMC_AD_SRIF_WDOG_AD_MASK)

#define CMC_AD_SRIF_SW_MASK                      (0x4000U)
#define CMC_AD_SRIF_SW_SHIFT                     (14U)
/*! SW - Software Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_AD_SRIF_SW(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIF_SW_SHIFT)) & CMC_AD_SRIF_SW_MASK)

#define CMC_AD_SRIF_GIC_ECC_MASK                 (0x8000U)
#define CMC_AD_SRIF_GIC_ECC_SHIFT                (15U)
/*! GIC_ECC - Application domain Interrupt Controller ECC Error Event
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_AD_SRIF_GIC_ECC(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIF_GIC_ECC_SHIFT)) & CMC_AD_SRIF_GIC_ECC_MASK)

#define CMC_AD_SRIF_RTD_MU_MASK                  (0x10000U)
#define CMC_AD_SRIF_RTD_MU_SHIFT                 (16U)
/*! RTD_MU - Real Time Domain MU Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_AD_SRIF_RTD_MU(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIF_RTD_MU_SHIFT)) & CMC_AD_SRIF_RTD_MU_MASK)

#define CMC_AD_SRIF_WDOG_S_AD_MASK               (0x2000000U)
#define CMC_AD_SRIF_WDOG_S_AD_SHIFT              (25U)
/*! WDOG_S_AD - Watchdog 4 Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_AD_SRIF_WDOG_S_AD(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIF_WDOG_S_AD_SHIFT)) & CMC_AD_SRIF_WDOG_S_AD_MASK)

#define CMC_AD_SRIF_WDOG5_MASK                   (0x4000000U)
#define CMC_AD_SRIF_WDOG5_SHIFT                  (26U)
/*! WDOG5 - Watchdog 5 Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_AD_SRIF_WDOG5(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_AD_SRIF_WDOG5_SHIFT)) & CMC_AD_SRIF_WDOG5_MASK)
/*! @} */

/*! @name MR - Mode Register */
/*! @{ */

#define CMC_AD_MR_BOOTCFG_MASK                   (0xFFFFFFFFU)
#define CMC_AD_MR_BOOTCFG_SHIFT                  (0U)
/*! BOOTCFG - Boot Configuration */
#define CMC_AD_MR_BOOTCFG(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_AD_MR_BOOTCFG_SHIFT)) & CMC_AD_MR_BOOTCFG_MASK)
/*! @} */

/* The count of CMC_AD_MR */
#define CMC_AD_MR_COUNT                          (1U)

/*! @name FM - Force Mode Register */
/*! @{ */

#define CMC_AD_FM_FORCECFG_MASK                  (0xFFFFFFFFU)
#define CMC_AD_FM_FORCECFG_SHIFT                 (0U)
/*! FORCECFG - Boot Configuration
 *  0b00000000000000000000000000000000..No effect.
 *  0b00000000000000000000000000000001..Assert corresponding bit in Mode Register on next system reset.
 */
#define CMC_AD_FM_FORCECFG(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_AD_FM_FORCECFG_SHIFT)) & CMC_AD_FM_FORCECFG_MASK)
/*! @} */

/* The count of CMC_AD_FM */
#define CMC_AD_FM_COUNT                          (1U)

/*! @name CORECTL - Core Control Register */
/*! @{ */

#define CMC_AD_CORECTL_NPIE_MASK                 (0x1U)
#define CMC_AD_CORECTL_NPIE_SHIFT                (0U)
/*! NPIE - Non maskable Pin Interrupt Enable
 *  0b0..Pin interrupt disabled
 *  0b1..Pin interrupt enabled
 */
#define CMC_AD_CORECTL_NPIE(x)                   (((uint32_t)(((uint32_t)(x)) << CMC_AD_CORECTL_NPIE_SHIFT)) & CMC_AD_CORECTL_NPIE_MASK)
/*! @} */

/*! @name DBGCTL - Debug Control Register */
/*! @{ */

#define CMC_AD_DBGCTL_SOD_MASK                   (0x1U)
#define CMC_AD_DBGCTL_SOD_SHIFT                  (0U)
/*! SOD - Sleep Or Debug
 *  0b0..Debug remains enabled when Core is sleeping.
 *  0b1..Debug is disabled when Core is sleeping.
 */
#define CMC_AD_DBGCTL_SOD(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_AD_DBGCTL_SOD_SHIFT)) & CMC_AD_DBGCTL_SOD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CMC_AD_Register_Masks */


/* CMC_AD - Peripheral instance base addresses */
/** Peripheral CMC_AD base address */
#define CMC_AD_BASE                              (0x29240000u)
/** Peripheral CMC_AD base pointer */
#define CMC_AD                                   ((CMC_AD_Type *)CMC_AD_BASE)
/** Array initializer of CMC_AD peripheral base addresses */
#define CMC_AD_BASE_ADDRS                        { CMC_AD_BASE }
/** Array initializer of CMC_AD peripheral base pointers */
#define CMC_AD_BASE_PTRS                         { CMC_AD }
/* Backward compatibility */
 #define CMC_AD_SRS_WDOG_HIFI4_MASK              CMC_AD_SRS_WDOG5_MASK
 #define CMC_AD_SRS_WDOG_HIFI4_SHIFT             CMC_AD_SRS_WDOG5_SHIFT
 #define CMC_AD_SRS_WDOG_HIFI4(x)                CMC_AD_SRS_WDOG5(x)
 #define CMC_AD_SSRS_WDOG_HIFI4_MASK             CMC_AD_SSRS_WDOG5_MASK
 #define CMC_AD_SSRS_WDOG_HIFI4_SHIFT            CMC_AD_SSRS_WDOG5_SHIFT
 #define CMC_AD_SSRS_WDOG_HIFI4(x)               CMC_AD_SSRS_WDOG5(x)
 #define CMC_AD_SRIE_WDOG_HIFI4_MASK             CMC_AD_SRIE_WDOG5_MASK
 #define CMC_AD_SRIE_WDOG_HIFI4_SHIFT            CMC_AD_SRIE_WDOG5_SHIFT
 #define CMC_AD_SRIE_WDOG_HIFI4(x)               CMC_AD_SRIE_WDOG5(x)
 #define CMC_AD_SRIF_WDOG_HIFI4_MASK             CMC_AD_SRIF_WDOG5_MASK
 #define CMC_AD_SRIF_WDOG_HIFI4_SHIFT            CMC_AD_SRIF_WDOG5_SHIFT
 #define CMC_AD_SRIF_WDOG_HIFI4(x)               CMC_AD_SRIF_WDOG5(x)


/*!
 * @}
 */ /* end of group CMC_AD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CMC_LPAC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CMC_LPAC_Peripheral_Access_Layer CMC_LPAC Peripheral Access Layer
 * @{
 */

/** CMC_LPAC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
       uint8_t RESERVED_0[108];
  __IO uint32_t LPAV_PSDORF;                       /**< Audio Video Domain Power Switch Domain Out of Reset Interrupt Flag Register, offset: 0x70 */
  __IO uint32_t LPAV_PSDORIE;                      /**< Audio Video Domain Power Switch Domain Out of Reset Interrupt Enable Register, offset: 0x74 */
  __I  uint32_t LPAV_PSDS;                         /**< Audio Video Domain Power Switch Domain Status Register, offset: 0x78 */
} CMC_LPAC_Type;

/* ----------------------------------------------------------------------------
   -- CMC_LPAC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CMC_LPAC_Register_Masks CMC_LPAC Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define CMC_LPAC_VERID_FEATURE_MASK              (0xFFFFU)
#define CMC_LPAC_VERID_FEATURE_SHIFT             (0U)
/*! FEATURE - Feature Specification Number */
#define CMC_LPAC_VERID_FEATURE(x)                (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_VERID_FEATURE_SHIFT)) & CMC_LPAC_VERID_FEATURE_MASK)

#define CMC_LPAC_VERID_MINOR_MASK                (0xFF0000U)
#define CMC_LPAC_VERID_MINOR_SHIFT               (16U)
/*! MINOR - Minor Version Number */
#define CMC_LPAC_VERID_MINOR(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_VERID_MINOR_SHIFT)) & CMC_LPAC_VERID_MINOR_MASK)

#define CMC_LPAC_VERID_MAJOR_MASK                (0xFF000000U)
#define CMC_LPAC_VERID_MAJOR_SHIFT               (24U)
/*! MAJOR - Major Version Number */
#define CMC_LPAC_VERID_MAJOR(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_VERID_MAJOR_SHIFT)) & CMC_LPAC_VERID_MAJOR_MASK)
/*! @} */

/*! @name LPAV_PSDORF - Audio Video Domain Power Switch Domain Out of Reset Interrupt Flag Register */
/*! @{ */

#define CMC_LPAC_LPAV_PSDORF_GPU3D_MASK          (0x1U)
#define CMC_LPAC_LPAV_PSDORF_GPU3D_SHIFT         (0U)
/*! GPU3D - GPU3D Power Switch Domain Out of Reset Interrupt Flag
 *  0b0..GPU3D Power Switch Domain in reset or user has cleared it by writing 1 to clear.
 *  0b1..GPU3D Power switch domain out of reset interrupt flag. This bit is asserted only once after the power switch domain exits the reset.
 */
#define CMC_LPAC_LPAV_PSDORF_GPU3D(x)            (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORF_GPU3D_SHIFT)) & CMC_LPAC_LPAV_PSDORF_GPU3D_MASK)

#define CMC_LPAC_LPAV_PSDORF_HIFI4_MASK          (0x2U)
#define CMC_LPAC_LPAV_PSDORF_HIFI4_SHIFT         (1U)
/*! HIFI4 - HIFI4 Power Switch Domain Out of Reset Interrupt Flag
 *  0b0..HIFI4 Power Switch Domain in reset or user has cleared it by writing 1 to clear.
 *  0b1..HIFI4 Power switch domain out of reset interrupt flag. This bit is asserted only once after the power switch domain exits the reset.
 */
#define CMC_LPAC_LPAV_PSDORF_HIFI4(x)            (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORF_HIFI4_SHIFT)) & CMC_LPAC_LPAV_PSDORF_HIFI4_MASK)

#define CMC_LPAC_LPAV_PSDORF_DDR_MASK            (0x4U)
#define CMC_LPAC_LPAV_PSDORF_DDR_SHIFT           (2U)
/*! DDR - DDR Power Switch Domain Out of Reset Interrupt Flag
 *  0b0..DDR Power Switch Domain in reset or user has cleared it by writing 1 to clear.
 *  0b1..DDR Power switch domain out of reset interrupt flag. This bit is asserted only once after the power switch domain exits the reset.
 */
#define CMC_LPAC_LPAV_PSDORF_DDR(x)              (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORF_DDR_SHIFT)) & CMC_LPAC_LPAV_PSDORF_DDR_MASK)

#define CMC_LPAC_LPAV_PSDORF_PXP_EPDC_MASK       (0x8U)
#define CMC_LPAC_LPAV_PSDORF_PXP_EPDC_SHIFT      (3U)
/*! PXP_EPDC - PXP/EPDC Power Switch Domain Out of Reset Interrupt Flag
 *  0b0..PXP/EPDC Power Switch Domain in reset or user has cleared it by writing 1 to clear.
 *  0b1..PXP/EPDC Power switch domain out of reset interrupt flag. This bit is asserted only once after the power switch domain exits the reset.
 */
#define CMC_LPAC_LPAV_PSDORF_PXP_EPDC(x)         (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORF_PXP_EPDC_SHIFT)) & CMC_LPAC_LPAV_PSDORF_PXP_EPDC_MASK)

#define CMC_LPAC_LPAV_PSDORF_MIPI_DSI_MASK       (0x10U)
#define CMC_LPAC_LPAV_PSDORF_MIPI_DSI_SHIFT      (4U)
/*! MIPI_DSI - MIPI-DSI Power Switch Domain Out of Reset Interrupt Flag
 *  0b0..MIPI-DSI Power Switch Domain in reset or user has cleared it by writing 1 to clear.
 *  0b1..MIPI-DSI Power switch domain out of reset interrupt flag. This bit is asserted only once after the power switch domain exits the reset.
 */
#define CMC_LPAC_LPAV_PSDORF_MIPI_DSI(x)         (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORF_MIPI_DSI_SHIFT)) & CMC_LPAC_LPAV_PSDORF_MIPI_DSI_MASK)

#define CMC_LPAC_LPAV_PSDORF_MIPI_CSI_MASK       (0x20U)
#define CMC_LPAC_LPAV_PSDORF_MIPI_CSI_SHIFT      (5U)
/*! MIPI_CSI - MIPI-CSI Power Switch Domain Out of Reset Interrupt Flag
 *  0b0..MIPI-CSI Power Switch Domain in reset or user has cleared it by writing 1 to clear.
 *  0b1..MIPI-CSI Power switch domain out of reset interrupt flag. This bit is asserted only once after the power switch domain exits the reset.
 */
#define CMC_LPAC_LPAV_PSDORF_MIPI_CSI(x)         (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORF_MIPI_CSI_SHIFT)) & CMC_LPAC_LPAV_PSDORF_MIPI_CSI_MASK)

#define CMC_LPAC_LPAV_PSDORF_NIC_AV_MASK         (0x40U)
#define CMC_LPAC_LPAV_PSDORF_NIC_AV_SHIFT        (6U)
/*! NIC_AV - NIC_AV/Periph Power Switch Domain Out of Reset Interrupt Flag
 *  0b0..NIC_AV/Periph Power Switch Domain in reset or user has cleared it by writing 1 to clear.
 *  0b1..NIC_AV/Periph Power switch domain out of reset interrupt flag. This bit is asserted only once after the power switch domain exits the reset.
 */
#define CMC_LPAC_LPAV_PSDORF_NIC_AV(x)           (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORF_NIC_AV_SHIFT)) & CMC_LPAC_LPAV_PSDORF_NIC_AV_MASK)
/*! @} */

/*! @name LPAV_PSDORIE - Audio Video Domain Power Switch Domain Out of Reset Interrupt Enable Register */
/*! @{ */

#define CMC_LPAC_LPAV_PSDORIE_GPU3D_MASK         (0x1U)
#define CMC_LPAC_LPAV_PSDORIE_GPU3D_SHIFT        (0U)
/*! GPU3D - GPU3D Power Switch Domain Out of Reset Interrupt Enable
 *  0b0..GPU3D Power Switch does not generate interrupt when domain gets out of reset.
 *  0b1..GPU3D Power Switch generates interrupt when domain gets out of reset.
 */
#define CMC_LPAC_LPAV_PSDORIE_GPU3D(x)           (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORIE_GPU3D_SHIFT)) & CMC_LPAC_LPAV_PSDORIE_GPU3D_MASK)

#define CMC_LPAC_LPAV_PSDORIE_HIFI4_MASK         (0x2U)
#define CMC_LPAC_LPAV_PSDORIE_HIFI4_SHIFT        (1U)
/*! HIFI4 - HIFI4 Power Switch Domain Out of Reset Interrupt Enable
 *  0b0..HIFI4 Power Switch does not generate interrupt when domain gets out of reset.
 *  0b1..HIFI4 Power Switch generates interrupt when domain gets out of reset.
 */
#define CMC_LPAC_LPAV_PSDORIE_HIFI4(x)           (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORIE_HIFI4_SHIFT)) & CMC_LPAC_LPAV_PSDORIE_HIFI4_MASK)

#define CMC_LPAC_LPAV_PSDORIE_DDR_MASK           (0x4U)
#define CMC_LPAC_LPAV_PSDORIE_DDR_SHIFT          (2U)
/*! DDR - DDR Power Switch Domain Out of Reset Interrupt Enable
 *  0b0..DDR Power Switch does not generate interrupt when domain gets out of reset.
 *  0b1..DDR Power Switch generates interrupt when domain gets out of reset.
 */
#define CMC_LPAC_LPAV_PSDORIE_DDR(x)             (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORIE_DDR_SHIFT)) & CMC_LPAC_LPAV_PSDORIE_DDR_MASK)

#define CMC_LPAC_LPAV_PSDORIE_PXP_EPDC_MASK      (0x8U)
#define CMC_LPAC_LPAV_PSDORIE_PXP_EPDC_SHIFT     (3U)
/*! PXP_EPDC - PXP/EPDC Power Switch Domain Out of Reset Interrupt Enable
 *  0b0..PXP/EPDC Power Switch does not generate interrupt when domain gets out of reset.
 *  0b1..PXP/EPDC Power Switch generates interrupt when domain gets out of reset.
 */
#define CMC_LPAC_LPAV_PSDORIE_PXP_EPDC(x)        (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORIE_PXP_EPDC_SHIFT)) & CMC_LPAC_LPAV_PSDORIE_PXP_EPDC_MASK)

#define CMC_LPAC_LPAV_PSDORIE_MIPI_DSI_MASK      (0x10U)
#define CMC_LPAC_LPAV_PSDORIE_MIPI_DSI_SHIFT     (4U)
/*! MIPI_DSI - MIPI-DSI Power Switch Domain Out of Reset Interrupt Enable
 *  0b0..MIPI-DSI Power Switch does not generate interrupt when domain gets out of reset.
 *  0b1..MIPI-DSI Power Switch generates interrupt when domain gets out of reset.
 */
#define CMC_LPAC_LPAV_PSDORIE_MIPI_DSI(x)        (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORIE_MIPI_DSI_SHIFT)) & CMC_LPAC_LPAV_PSDORIE_MIPI_DSI_MASK)

#define CMC_LPAC_LPAV_PSDORIE_MIPI_CSI_MASK      (0x20U)
#define CMC_LPAC_LPAV_PSDORIE_MIPI_CSI_SHIFT     (5U)
/*! MIPI_CSI - MIPI-CSI Power Switch Domain Out of Reset Interrupt Enable
 *  0b0..MIPI-CSI Power Switch does not generate interrupt when domain gets out of reset.
 *  0b1..MIPI-CSI Power Switch generates interrupt when domain gets out of reset.
 */
#define CMC_LPAC_LPAV_PSDORIE_MIPI_CSI(x)        (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORIE_MIPI_CSI_SHIFT)) & CMC_LPAC_LPAV_PSDORIE_MIPI_CSI_MASK)

#define CMC_LPAC_LPAV_PSDORIE_NIC_AV_MASK        (0x40U)
#define CMC_LPAC_LPAV_PSDORIE_NIC_AV_SHIFT       (6U)
/*! NIC_AV - NIC_AV/Periph Power Switch Domain Out of Reset Interrupt Enable
 *  0b0..NIC_AV/Periph Power Switch does not generate interrupt when domain gets out of reset.
 *  0b1..NIC_AV/Periph Power Switch generates interrupt when domain gets out of reset.
 */
#define CMC_LPAC_LPAV_PSDORIE_NIC_AV(x)          (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDORIE_NIC_AV_SHIFT)) & CMC_LPAC_LPAV_PSDORIE_NIC_AV_MASK)
/*! @} */

/*! @name LPAV_PSDS - Audio Video Domain Power Switch Domain Status Register */
/*! @{ */

#define CMC_LPAC_LPAV_PSDS_GPU3D_MASK            (0x1U)
#define CMC_LPAC_LPAV_PSDS_GPU3D_SHIFT           (0U)
/*! GPU3D - GPU3D Power Switch Domain Status
 *  0b0..GPU3D Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..GPU3D Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_LPAC_LPAV_PSDS_GPU3D(x)              (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDS_GPU3D_SHIFT)) & CMC_LPAC_LPAV_PSDS_GPU3D_MASK)

#define CMC_LPAC_LPAV_PSDS_HIFI4_MASK            (0x2U)
#define CMC_LPAC_LPAV_PSDS_HIFI4_SHIFT           (1U)
/*! HIFI4 - HIFI4 Power Switch Domain Status
 *  0b0..HIFI4 Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..HIFI4 Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_LPAC_LPAV_PSDS_HIFI4(x)              (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDS_HIFI4_SHIFT)) & CMC_LPAC_LPAV_PSDS_HIFI4_MASK)

#define CMC_LPAC_LPAV_PSDS_DDR_MASK              (0x4U)
#define CMC_LPAC_LPAV_PSDS_DDR_SHIFT             (2U)
/*! DDR - DDR Power Switch Domain Status
 *  0b0..DDR Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..DDR Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_LPAC_LPAV_PSDS_DDR(x)                (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDS_DDR_SHIFT)) & CMC_LPAC_LPAV_PSDS_DDR_MASK)

#define CMC_LPAC_LPAV_PSDS_PXP_EPDC_MASK         (0x8U)
#define CMC_LPAC_LPAV_PSDS_PXP_EPDC_SHIFT        (3U)
/*! PXP_EPDC - PXP/EPDC Power Switch Domain Status
 *  0b0..PXP/EPDC Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..PXP/EPDC Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_LPAC_LPAV_PSDS_PXP_EPDC(x)           (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDS_PXP_EPDC_SHIFT)) & CMC_LPAC_LPAV_PSDS_PXP_EPDC_MASK)

#define CMC_LPAC_LPAV_PSDS_MIPI_DSI_MASK         (0x10U)
#define CMC_LPAC_LPAV_PSDS_MIPI_DSI_SHIFT        (4U)
/*! MIPI_DSI - MIPI-DSI Power Switch Domain Status
 *  0b0..MIPI-DSI Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..MIPI-DSI Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_LPAC_LPAV_PSDS_MIPI_DSI(x)           (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDS_MIPI_DSI_SHIFT)) & CMC_LPAC_LPAV_PSDS_MIPI_DSI_MASK)

#define CMC_LPAC_LPAV_PSDS_MIPI_CSI_MASK         (0x20U)
#define CMC_LPAC_LPAV_PSDS_MIPI_CSI_SHIFT        (5U)
/*! MIPI_CSI - MIPI-CSI Power Switch Domain Status
 *  0b0..MIPI-CSI Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..MIPI-CSI Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_LPAC_LPAV_PSDS_MIPI_CSI(x)           (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDS_MIPI_CSI_SHIFT)) & CMC_LPAC_LPAV_PSDS_MIPI_CSI_MASK)

#define CMC_LPAC_LPAV_PSDS_NIC_AV_MASK           (0x40U)
#define CMC_LPAC_LPAV_PSDS_NIC_AV_SHIFT          (6U)
/*! NIC_AV - NIC_AV/Periph Power Switch Domain Status
 *  0b0..NIC_AV/Periph Power switch is open and not ready for read/write. Power switch domain is in reset.
 *  0b1..NIC_AV/Periph Power switch is closed and in normal operation. Power switch domain is out of reset.
 */
#define CMC_LPAC_LPAV_PSDS_NIC_AV(x)             (((uint32_t)(((uint32_t)(x)) << CMC_LPAC_LPAV_PSDS_NIC_AV_SHIFT)) & CMC_LPAC_LPAV_PSDS_NIC_AV_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CMC_LPAC_Register_Masks */


/* CMC_LPAC - Peripheral instance base addresses */
/** Peripheral CMC_LPAC base address */
#define CMC_LPAC_BASE                            (0x2DA40000u)
/** Peripheral CMC_LPAC base pointer */
#define CMC_LPAC                                 ((CMC_LPAC_Type *)CMC_LPAC_BASE)
/** Array initializer of CMC_LPAC peripheral base addresses */
#define CMC_LPAC_BASE_ADDRS                      { CMC_LPAC_BASE }
/** Array initializer of CMC_LPAC peripheral base pointers */
#define CMC_LPAC_BASE_PTRS                       { CMC_LPAC }

/*!
 * @}
 */ /* end of group CMC_LPAC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CMP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
 * @{
 */

/** CMP - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __IO uint32_t C0;                                /**< CMP Control Register 0, offset: 0x8 */
  __IO uint32_t C1;                                /**< CMP Control Register 1, offset: 0xC */
  __IO uint32_t C2;                                /**< CMP Control Register 2, offset: 0x10 */
  __IO uint32_t C3;                                /**< CMP Control Register 3, offset: 0x14 */
} CMP_Type;

/* ----------------------------------------------------------------------------
   -- CMP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CMP_Register_Masks CMP Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define CMP_VERID_FEATURE_MASK                   (0xFFFFU)
#define CMP_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Specification Number. This read only filed returns the feature set number. */
#define CMP_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)

#define CMP_VERID_MINOR_MASK                     (0xFF0000U)
#define CMP_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number. This read only field returns the minor version number for the module specification. */
#define CMP_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)

#define CMP_VERID_MAJOR_MASK                     (0xFF000000U)
#define CMP_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number. This read only field returns the major version number for the module specification. */
#define CMP_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define CMP_PARAM_PARAM_MASK                     (0xFFFFFFFFU)
#define CMP_PARAM_PARAM_SHIFT                    (0U)
/*! PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register. */
#define CMP_PARAM_PARAM(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)
/*! @} */

/*! @name C0 - CMP Control Register 0 */
/*! @{ */

#define CMP_C0_HYSTCTR_MASK                      (0x3U)
#define CMP_C0_HYSTCTR_SHIFT                     (0U)
/*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level
 *  0b00..The hard block output has level 0 hysteresis internally.
 *  0b01..The hard block output has level 1 hysteresis internally.
 *  0b10..The hard block output has level 2 hysteresis internally.
 *  0b11..The hard block output has level 3 hysteresis internally.
 */
#define CMP_C0_HYSTCTR(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK)

#define CMP_C0_FILTER_CNT_MASK                   (0x70U)
#define CMP_C0_FILTER_CNT_SHIFT                  (4U)
/*! FILTER_CNT - Filter Sample Count
 *  0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.
 *  0b001..1 consecutive sample must agree (comparator output is simply sampled).
 *  0b010..2 consecutive samples must agree.
 *  0b011..3 consecutive samples must agree.
 *  0b100..4 consecutive samples must agree.
 *  0b101..5 consecutive samples must agree.
 *  0b110..6 consecutive samples must agree.
 *  0b111..7 consecutive samples must agree.
 */
#define CMP_C0_FILTER_CNT(x)                     (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)

#define CMP_C0_EN_MASK                           (0x100U)
#define CMP_C0_EN_SHIFT                          (8U)
/*! EN - Comparator Module Enable
 *  0b0..Analog Comparator is disabled.
 *  0b1..Analog Comparator is enabled.
 */
#define CMP_C0_EN(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)

#define CMP_C0_OPE_MASK                          (0x200U)
#define CMP_C0_OPE_SHIFT                         (9U)
/*! OPE - Comparator Output Pin Enable
 *  0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin.
 *  0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin.
 */
#define CMP_C0_OPE(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)

#define CMP_C0_COS_MASK                          (0x400U)
#define CMP_C0_COS_SHIFT                         (10U)
/*! COS - Comparator Output Select
 *  0b0..Set CMPO to equal COUT (filtered comparator output).
 *  0b1..Set CMPO to equal COUTA (unfiltered comparator output).
 */
#define CMP_C0_COS(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)

#define CMP_C0_INVT_MASK                         (0x800U)
#define CMP_C0_INVT_SHIFT                        (11U)
/*! INVT - Comparator invert
 *  0b0..Does not invert the comparator output.
 *  0b1..Inverts the comparator output.
 */
#define CMP_C0_INVT(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)

#define CMP_C0_PMODE_MASK                        (0x1000U)
#define CMP_C0_PMODE_SHIFT                       (12U)
/*! PMODE - Power Mode Select
 *  0b0..Low Speed (LS) comparison mode is selected.
 *  0b1..High Speed (HS) comparison mode is selected.
 */
#define CMP_C0_PMODE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)

#define CMP_C0_WE_MASK                           (0x4000U)
#define CMP_C0_WE_SHIFT                          (14U)
/*! WE - Windowing Enable
 *  0b0..Windowing mode is not selected.
 *  0b1..Windowing mode is selected.
 */
#define CMP_C0_WE(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK)

#define CMP_C0_SE_MASK                           (0x8000U)
#define CMP_C0_SE_SHIFT                          (15U)
/*! SE - Sample Enable
 *  0b0..Sampling mode is not selected.
 *  0b1..Sampling mode is selected.
 */
#define CMP_C0_SE(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK)

#define CMP_C0_FPR_MASK                          (0xFF0000U)
#define CMP_C0_FPR_SHIFT                         (16U)
/*! FPR - Filter Sample Period */
#define CMP_C0_FPR(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)

#define CMP_C0_COUT_MASK                         (0x1000000U)
#define CMP_C0_COUT_SHIFT                        (24U)
/*! COUT - Analog Comparator Output */
#define CMP_C0_COUT(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)

#define CMP_C0_CFF_MASK                          (0x2000000U)
#define CMP_C0_CFF_SHIFT                         (25U)
/*! CFF - Analog Comparator Flag Falling
 *  0b0..A falling edge has not been detected on COUT.
 *  0b1..A falling edge on COUT has occurred.
 */
#define CMP_C0_CFF(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)

#define CMP_C0_CFR_MASK                          (0x4000000U)
#define CMP_C0_CFR_SHIFT                         (26U)
/*! CFR - Analog Comparator Flag Rising
 *  0b0..A rising edge has not been detected on COUT.
 *  0b1..A rising edge on COUT has occurred.
 */
#define CMP_C0_CFR(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)

#define CMP_C0_IEF_MASK                          (0x8000000U)
#define CMP_C0_IEF_SHIFT                         (27U)
/*! IEF - Comparator Interrupt Enable Falling
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define CMP_C0_IEF(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)

#define CMP_C0_IER_MASK                          (0x10000000U)
#define CMP_C0_IER_SHIFT                         (28U)
/*! IER - Comparator Interrupt Enable Rising
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define CMP_C0_IER(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)

#define CMP_C0_DMAEN_MASK                        (0x40000000U)
#define CMP_C0_DMAEN_SHIFT                       (30U)
/*! DMAEN - DMA Enable
 *  0b0..DMA is disabled.
 *  0b1..DMA is enabled.
 */
#define CMP_C0_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)

#define CMP_C0_LINKEN_MASK                       (0x80000000U)
#define CMP_C0_LINKEN_SHIFT                      (31U)
/*! LINKEN - CMP to DAC link enable.
 *  0b0..CMP to DAC link is disabled
 *  0b1..CMP to DAC link is enabled.
 */
#define CMP_C0_LINKEN(x)                         (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)
/*! @} */

/*! @name C1 - CMP Control Register 1 */
/*! @{ */

#define CMP_C1_VOSEL_MASK                        (0xFFU)
#define CMP_C1_VOSEL_SHIFT                       (0U)
/*! VOSEL - DAC Output Voltage Select */
#define CMP_C1_VOSEL(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)

#define CMP_C1_DMODE_MASK                        (0x100U)
#define CMP_C1_DMODE_SHIFT                       (8U)
/*! DMODE - DAC Mode Selection
 *  0b0..DAC is selected to work in low speed and low power mode.
 *  0b1..DAC is selected to work in high speed high power mode.
 */
#define CMP_C1_DMODE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)

#define CMP_C1_VRSEL_MASK                        (0x200U)
#define CMP_C1_VRSEL_SHIFT                       (9U)
/*! VRSEL - Supply Voltage Reference Source Select
 *  0b0..Vin1 is selected as resistor ladder network supply reference Vin. Vin1 is from internal PMC.
 *  0b1..Vin2 is selected as resistor ladder network supply reference Vin. Vin2 is from PAD.
 */
#define CMP_C1_VRSEL(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)

#define CMP_C1_DACEN_MASK                        (0x400U)
#define CMP_C1_DACEN_SHIFT                       (10U)
/*! DACEN - DAC Enable
 *  0b0..DAC is disabled.
 *  0b1..DAC is enabled.
 */
#define CMP_C1_DACEN(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)

#define CMP_C1_CHN0_MASK                         (0x10000U)
#define CMP_C1_CHN0_SHIFT                        (16U)
/*! CHN0 - Channel 0 input enable */
#define CMP_C1_CHN0(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK)

#define CMP_C1_CHN1_MASK                         (0x20000U)
#define CMP_C1_CHN1_SHIFT                        (17U)
/*! CHN1 - Channel 1 input enable */
#define CMP_C1_CHN1(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK)

#define CMP_C1_CHN2_MASK                         (0x40000U)
#define CMP_C1_CHN2_SHIFT                        (18U)
/*! CHN2 - Channel 2 input enable */
#define CMP_C1_CHN2(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK)

#define CMP_C1_CHN3_MASK                         (0x80000U)
#define CMP_C1_CHN3_SHIFT                        (19U)
/*! CHN3 - Channel 3 input enable */
#define CMP_C1_CHN3(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK)

#define CMP_C1_CHN4_MASK                         (0x100000U)
#define CMP_C1_CHN4_SHIFT                        (20U)
/*! CHN4 - Channel 4 input enable */
#define CMP_C1_CHN4(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK)

#define CMP_C1_CHN5_MASK                         (0x200000U)
#define CMP_C1_CHN5_SHIFT                        (21U)
/*! CHN5 - Channel 5 input enable */
#define CMP_C1_CHN5(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK)

#define CMP_C1_MSEL_MASK                         (0x7000000U)
#define CMP_C1_MSEL_SHIFT                        (24U)
/*! MSEL - Minus Input MUX Control
 *  0b000..Internal Negative Input 0 for Minus Channel -- Internal Minus Input
 *  0b001..External Input 1 for Minus Channel -- Reference Input 0
 *  0b010..External Input 2 for Minus Channel -- Reference Input 1
 *  0b011..External Input 3 for Minus Channel -- Reference Input 2
 *  0b100..External Input 4 for Minus Channel -- Reference Input 3
 *  0b101..External Input 5 for Minus Channel -- Reference Input 4
 *  0b110..External Input 6 for Minus Channel -- Reference Input 5
 *  0b111..Internal 8b DAC output
 */
#define CMP_C1_MSEL(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)

#define CMP_C1_PSEL_MASK                         (0x70000000U)
#define CMP_C1_PSEL_SHIFT                        (28U)
/*! PSEL - Plus Input MUX Control
 *  0b000..Internal Positive Input 0 for Plus Channel -- Internal Plus Input
 *  0b001..External Input 1 for Plus Channel -- Reference Input 0
 *  0b010..External Input 2 for Plus Channel -- Reference Input 1
 *  0b011..External Input 3 for Plus Channel -- Reference Input 2
 *  0b100..External Input 4 for Plus Channel -- Reference Input 3
 *  0b101..External Input 5 for Plus Channel -- Reference Input 4
 *  0b110..External Input 6 for Plus Channel -- Reference Input 5
 *  0b111..Internal 8b DAC output
 */
#define CMP_C1_PSEL(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)
/*! @} */

/*! @name C2 - CMP Control Register 2 */
/*! @{ */

#define CMP_C2_ACOn_MASK                         (0x3FU)
#define CMP_C2_ACOn_SHIFT                        (0U)
/*! ACOn - ACOn */
#define CMP_C2_ACOn(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK)

#define CMP_C2_INITMOD_MASK                      (0x3F00U)
#define CMP_C2_INITMOD_SHIFT                     (8U)
/*! INITMOD - Comparator and DAC initialization delay modulus. */
#define CMP_C2_INITMOD(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK)

#define CMP_C2_NSAM_MASK                         (0xC000U)
#define CMP_C2_NSAM_SHIFT                        (14U)
/*! NSAM - Number of sample clocks
 *  0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock.
 *  0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock.
 *  0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock.
 *  0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.
 */
#define CMP_C2_NSAM(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK)

#define CMP_C2_CH0F_MASK                         (0x10000U)
#define CMP_C2_CH0F_SHIFT                        (16U)
/*! CH0F - CH0F */
#define CMP_C2_CH0F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK)

#define CMP_C2_CH1F_MASK                         (0x20000U)
#define CMP_C2_CH1F_SHIFT                        (17U)
/*! CH1F - CH1F */
#define CMP_C2_CH1F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK)

#define CMP_C2_CH2F_MASK                         (0x40000U)
#define CMP_C2_CH2F_SHIFT                        (18U)
/*! CH2F - CH2F */
#define CMP_C2_CH2F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK)

#define CMP_C2_CH3F_MASK                         (0x80000U)
#define CMP_C2_CH3F_SHIFT                        (19U)
/*! CH3F - CH3F */
#define CMP_C2_CH3F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK)

#define CMP_C2_CH4F_MASK                         (0x100000U)
#define CMP_C2_CH4F_SHIFT                        (20U)
/*! CH4F - CH4F */
#define CMP_C2_CH4F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK)

#define CMP_C2_CH5F_MASK                         (0x200000U)
#define CMP_C2_CH5F_SHIFT                        (21U)
/*! CH5F - CH5F */
#define CMP_C2_CH5F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK)

#define CMP_C2_FXMXCH_MASK                       (0xE000000U)
#define CMP_C2_FXMXCH_SHIFT                      (25U)
/*! FXMXCH - Fixed channel selection
 *  0b000..External Reference Input 0 is selected as the fixed reference input for the fixed mux port.
 *  0b001..External Reference Input 1 is selected as the fixed reference input for the fixed mux port.
 *  0b010..External Reference Input 2 is selected as the fixed reference input for the fixed mux port.
 *  0b011..External Reference Input 3 is selected as the fixed reference input for the fixed mux port.
 *  0b100..External Reference Input 4 is selected as the fixed reference input for the fixed mux port.
 *  0b101..External Reference Input 5 is selected as the fixed reference input for the fixed mux port.
 *  0b110..Reserved.
 *  0b111..The 8bit DAC is selected as the fixed reference input for the fixed mux port.
 */
#define CMP_C2_FXMXCH(x)                         (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK)

#define CMP_C2_FXMP_MASK                         (0x20000000U)
#define CMP_C2_FXMP_SHIFT                        (29U)
/*! FXMP - Fixed MUX Port
 *  0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round.
 *  0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round.
 */
#define CMP_C2_FXMP(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK)

#define CMP_C2_RRIE_MASK                         (0x40000000U)
#define CMP_C2_RRIE_SHIFT                        (30U)
/*! RRIE - Round-Robin interrupt enable
 *  0b0..The round-robin interrupt is disabled.
 *  0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample.
 */
#define CMP_C2_RRIE(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK)
/*! @} */

/*! @name C3 - CMP Control Register 3 */
/*! @{ */

#define CMP_C3_ACPH2TC_MASK                      (0x70U)
#define CMP_C3_ACPH2TC_SHIFT                     (4U)
/*! ACPH2TC - Analog Comparator Phase2 Timing Control.
 *  0b000..Phase2 active time in one sampling period equals to T
 *  0b001..Phase2 active time in one sampling period equals to 2*T
 *  0b010..Phase2 active time in one sampling period equals to 4*T
 *  0b011..Phase2 active time in one sampling period equals to 8*T
 *  0b100..Phase2 active time in one sampling period equals to 16*T
 *  0b101..Phase2 active time in one sampling period equals to 32*T
 *  0b110..Phase2 active time in one sampling period equals to 64*T
 *  0b111..Phase2 active time in one sampling period equals to 16*T
 */
#define CMP_C3_ACPH2TC(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK)

#define CMP_C3_ACPH1TC_MASK                      (0x700U)
#define CMP_C3_ACPH1TC_SHIFT                     (8U)
/*! ACPH1TC - Analog Comparator Phase1 Timing Control.
 *  0b000..Phase1 active time in one sampling period equals to T
 *  0b001..Phase1 active time in one sampling period equals to 2*T
 *  0b010..Phase1 active time in one sampling period equals to 4*T
 *  0b011..Phase1 active time in one sampling period equals to 8*T
 *  0b100..Phase1 active time in one sampling period equals to T
 *  0b101..Phase1 active time in one sampling period equals to T
 *  0b110..Phase1 active time in one sampling period equals to T
 *  0b111..Phase1 active time in one sampling period equals to 0
 */
#define CMP_C3_ACPH1TC(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK)

#define CMP_C3_ACSAT_MASK                        (0x7000U)
#define CMP_C3_ACSAT_SHIFT                       (12U)
/*! ACSAT - Analog Comparator Sampling Time control.
 *  0b000..The sampling time equals to T
 *  0b001..The sampling time equasl to 2*T
 *  0b010..The sampling time equasl to 4*T
 *  0b011..The sampling time equasl to 8*T
 *  0b100..The sampling time equasl to 16*T
 *  0b101..The sampling time equasl to 32*T
 *  0b110..The sampling time equasl to 64*T
 *  0b111..The sampling time equasl to 256*T
 */
#define CMP_C3_ACSAT(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK)

#define CMP_C3_DMCS_MASK                         (0x10000U)
#define CMP_C3_DMCS_SHIFT                        (16U)
/*! DMCS - Discrete Mode Clock Selection
 *  0b0..Slow clock is selected for the timing generation.
 *  0b1..Fast clock is selected for the timing generation.
 */
#define CMP_C3_DMCS(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK)

#define CMP_C3_RDIVE_MASK                        (0x100000U)
#define CMP_C3_RDIVE_SHIFT                       (20U)
/*! RDIVE - Resistor Divider Enable
 *  0b0..The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 - 1.8v.
 *  0b1..The resistor is enabled because the inputs are above 1.8v.
 */
#define CMP_C3_RDIVE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK)

#define CMP_C3_NCHCTEN_MASK                      (0x1000000U)
#define CMP_C3_NCHCTEN_SHIFT                     (24U)
/*! NCHCTEN - Negative Channel Continuous Mode Enable.
 *  0b0..Negative channel is in Discrete Mode and special timing needs to be configured.
 *  0b1..Negative channel is in Continuous Mode and no special timing is requried.
 */
#define CMP_C3_NCHCTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)

#define CMP_C3_PCHCTEN_MASK                      (0x10000000U)
#define CMP_C3_PCHCTEN_SHIFT                     (28U)
/*! PCHCTEN - Positive Channel Continuous Mode Enable.
 *  0b0..Positive channel is in Discrete Mode and special timing needs to be configured.
 *  0b1..Positive channel is in Continuous Mode and no special timing is requried.
 */
#define CMP_C3_PCHCTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CMP_Register_Masks */


/* CMP - Peripheral instance base addresses */
/** Peripheral CMP0 base address */
#define CMP0_BASE                                (0x28041000u)
/** Peripheral CMP0 base pointer */
#define CMP0                                     ((CMP_Type *)CMP0_BASE)
/** Peripheral CMP1 base address */
#define CMP1_BASE                                (0x28042000u)
/** Peripheral CMP1 base pointer */
#define CMP1                                     ((CMP_Type *)CMP1_BASE)
/** Array initializer of CMP peripheral base addresses */
#define CMP_BASE_ADDRS                           { CMP0_BASE, CMP1_BASE }
/** Array initializer of CMP peripheral base pointers */
#define CMP_BASE_PTRS                            { CMP0, CMP1 }

/*!
 * @}
 */ /* end of group CMP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DAC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
 * @{
 */

/** DAC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version Identifier Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __O  uint32_t DATA;                              /**< DAC Data Register, offset: 0x8 */
  __IO uint32_t CR;                                /**< DAC Status and Control Register, offset: 0xC */
  __I  uint32_t PTR;                               /**< DAC FIFO Pointer Register, offset: 0x10 */
  __IO uint32_t CR2;                               /**< DAC Status and Control Register 2, offset: 0x14 */
} DAC_Type;

/* ----------------------------------------------------------------------------
   -- DAC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DAC_Register_Masks DAC Register Masks
 * @{
 */

/*! @name VERID - Version Identifier Register */
/*! @{ */

#define DAC_VERID_FEATURE_MASK                   (0xFFFFU)
#define DAC_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Identification Number
 *  0b0000000000000000..Standard feature set
 *  0b0000000000000001..C40 feature set
 *  0b0000000000000010..5V DAC feature set
 *  0b0000000000000100..ADC BIST feature set
 */
#define DAC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK)

#define DAC_VERID_MINOR_MASK                     (0xFF0000U)
#define DAC_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor version number */
#define DAC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK)

#define DAC_VERID_MAJOR_MASK                     (0xFF000000U)
#define DAC_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major version number */
#define DAC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define DAC_PARAM_FIFOSZ_MASK                    (0x7U)
#define DAC_PARAM_FIFOSZ_SHIFT                   (0U)
/*! FIFOSZ - FIFO size
 *  0b000..FIFO depth is 2
 *  0b001..FIFO depth is 4
 *  0b010..FIFO depth is 8
 *  0b011..FIFO depth is 16
 *  0b100..FIFO depth is 32
 *  0b101..FIFO depth is 64
 *  0b110..FIFO depth is 128
 *  0b111..FIFO depth is 256
 */
#define DAC_PARAM_FIFOSZ(x)                      (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)
/*! @} */

/*! @name DATA - DAC Data Register */
/*! @{ */

#define DAC_DATA_DATA0_MASK                      (0xFFFU)
#define DAC_DATA_DATA0_SHIFT                     (0U)
/*! DATA0 - FIFO DATA0 */
#define DAC_DATA_DATA0(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK)
/*! @} */

/*! @name CR - DAC Status and Control Register */
/*! @{ */

#define DAC_CR_FULLF_MASK                        (0x1U)
#define DAC_CR_FULLF_SHIFT                       (0U)
/*! FULLF - Full Flag
 *  0b0..FIFO is not full.
 *  0b1..FIFO is full.
 */
#define DAC_CR_FULLF(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK)

#define DAC_CR_NEMPTF_MASK                       (0x2U)
#define DAC_CR_NEMPTF_SHIFT                      (1U)
/*! NEMPTF - Nearly Empty Flag
 *  0b0..More than one data is available in the FIFO.
 *  0b1..One data is available in the FIFO.
 */
#define DAC_CR_NEMPTF(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK)

#define DAC_CR_WMF_MASK                          (0x4U)
#define DAC_CR_WMF_SHIFT                         (2U)
/*! WMF - FIFO Watermark Status Flag
 *  0b0..The DAC buffer read pointer has not reached the watermark level.
 *  0b1..The DAC buffer read pointer has reached the watermark level.
 */
#define DAC_CR_WMF(x)                            (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK)

#define DAC_CR_UDFF_MASK                         (0x8U)
#define DAC_CR_UDFF_SHIFT                        (3U)
/*! UDFF - Underflow Flag
 *  0b0..No underflow has occurred since the last time the flag was cleared.
 *  0b1..At least one trigger underflow has occurred since the last time the flag was cleared.
 */
#define DAC_CR_UDFF(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK)

#define DAC_CR_OVFF_MASK                         (0x10U)
#define DAC_CR_OVFF_SHIFT                        (4U)
/*! OVFF - Overflow Flag
 *  0b0..No overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one FIFO overflow has occurred since the last time the flag was cleared.
 */
#define DAC_CR_OVFF(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK)

#define DAC_CR_FULLIE_MASK                       (0x100U)
#define DAC_CR_FULLIE_SHIFT                      (8U)
/*! FULLIE - Full Interrupt Enable
 *  0b0..FIFO Full interrupt is disabled.
 *  0b1..FIFO Full interrupt is enabled.
 */
#define DAC_CR_FULLIE(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK)

#define DAC_CR_EMPTIE_MASK                       (0x200U)
#define DAC_CR_EMPTIE_SHIFT                      (9U)
/*! EMPTIE - Nearly Empty Interrupt Enable
 *  0b0..FIFO Nearly Empty interrupt is disabled.
 *  0b1..FIFO Nearly Empty interrupt is enabled.
 */
#define DAC_CR_EMPTIE(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK)

#define DAC_CR_WTMIE_MASK                        (0x400U)
#define DAC_CR_WTMIE_SHIFT                       (10U)
/*! WTMIE - Watermark Interrupt Enable
 *  0b0..Watermark interrupt is disabled.
 *  0b1..Watermark interrupt is enabled.
 */
#define DAC_CR_WTMIE(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK)

#define DAC_CR_SWTRG_MASK                        (0x1000U)
#define DAC_CR_SWTRG_SHIFT                       (12U)
/*! SWTRG - DAC Software Trigger
 *  0b0..The DAC soft trigger is not valid.
 *  0b1..The DAC soft trigger is valid.
 */
#define DAC_CR_SWTRG(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK)

#define DAC_CR_TRGSEL_MASK                       (0x2000U)
#define DAC_CR_TRGSEL_SHIFT                      (13U)
/*! TRGSEL - DAC Trigger Select
 *  0b0..The DAC hardware trigger is selected.
 *  0b1..The DAC software trigger is selected.
 */
#define DAC_CR_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK)

#define DAC_CR_DACRFS_MASK                       (0x4000U)
#define DAC_CR_DACRFS_SHIFT                      (14U)
/*! DACRFS - DAC Reference Select
 *  0b0..The DAC selects DACREF_1 as the reference voltage.
 *  0b1..The DAC selects DACREF_2 as the reference voltage.
 */
#define DAC_CR_DACRFS(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK)

#define DAC_CR_DACEN_MASK                        (0x8000U)
#define DAC_CR_DACEN_SHIFT                       (15U)
/*! DACEN - DAC Enable
 *  0b0..The DAC system is disabled.
 *  0b1..The DAC system is enabled.
 */
#define DAC_CR_DACEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK)

#define DAC_CR_FIFOEN_MASK                       (0x10000U)
#define DAC_CR_FIFOEN_SHIFT                      (16U)
/*! FIFOEN - FIFO Enable
 *  0b0..FIFO is disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion.
 *  0b1..FIFO is enabled. Data will first read from FIFO to buffer then go to conversion.
 */
#define DAC_CR_FIFOEN(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK)

#define DAC_CR_SWMD_MASK                         (0x20000U)
#define DAC_CR_SWMD_SHIFT                        (17U)
/*! SWMD - DAC FIFO Mode Select
 *  0b0..Normal mode
 *  0b1..Swing back mode
 */
#define DAC_CR_SWMD(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK)

#define DAC_CR_UVIE_MASK                         (0x40000U)
#define DAC_CR_UVIE_SHIFT                        (18U)
/*! UVIE - Underflow and overflow interrupt enable
 *  0b0..Underflow and overflow interrupt is disabled.
 *  0b1..Underflow and overflow interrupt is enabled.
 */
#define DAC_CR_UVIE(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK)

#define DAC_CR_FIFORST_MASK                      (0x200000U)
#define DAC_CR_FIFORST_SHIFT                     (21U)
/*! FIFORST - FIFO Reset
 *  0b0..No effect
 *  0b1..FIFO reset
 */
#define DAC_CR_FIFORST(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK)

#define DAC_CR_SWRST_MASK                        (0x400000U)
#define DAC_CR_SWRST_SHIFT                       (22U)
/*! SWRST - Software reset */
#define DAC_CR_SWRST(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK)

#define DAC_CR_DMAEN_MASK                        (0x800000U)
#define DAC_CR_DMAEN_SHIFT                       (23U)
/*! DMAEN - DMA Enable Select
 *  0b0..DMA is disabled.
 *  0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The
 *       interrupts will not be presented on this module at the same time.
 */
#define DAC_CR_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK)

#define DAC_CR_WML_MASK                          (0xFF000000U)
#define DAC_CR_WML_SHIFT                         (24U)
/*! WML - Watermark Level Select */
#define DAC_CR_WML(x)                            (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK)
/*! @} */

/*! @name PTR - DAC FIFO Pointer Register */
/*! @{ */

#define DAC_PTR_DACWFP_MASK                      (0xFFU)
#define DAC_PTR_DACWFP_SHIFT                     (0U)
/*! DACWFP - DACWFP */
#define DAC_PTR_DACWFP(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK)

#define DAC_PTR_DACRFP_MASK                      (0xFF0000U)
#define DAC_PTR_DACRFP_SHIFT                     (16U)
/*! DACRFP - DACRFP */
#define DAC_PTR_DACRFP(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK)
/*! @} */

/*! @name CR2 - DAC Status and Control Register 2 */
/*! @{ */

#define DAC_CR2_BFEN_MASK                        (0x1U)
#define DAC_CR2_BFEN_SHIFT                       (0U)
/*! BFEN - Buffer Enable
 *  0b0..Opamp is not used as buffer
 *  0b1..Opamp is used as buffer
 */
#define DAC_CR2_BFEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK)

#define DAC_CR2_OEN_MASK                         (0x2U)
#define DAC_CR2_OEN_SHIFT                        (1U)
/*! OEN - Optional Enable
 *  0b0..Output buffer is not bypassed
 *  0b1..Output buffer is bypassed
 */
#define DAC_CR2_OEN(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK)

#define DAC_CR2_BFMS_MASK                        (0x4U)
#define DAC_CR2_BFMS_SHIFT                       (2U)
/*! BFMS - Buffer Middle Speed Select
 *  0b0..Buffer middle speed not selected
 *  0b1..Buffer middle speed selected
 */
#define DAC_CR2_BFMS(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK)

#define DAC_CR2_BFHS_MASK                        (0x8U)
#define DAC_CR2_BFHS_SHIFT                       (3U)
/*! BFHS - Buffer High Speed Select
 *  0b0..Buffer high speed not selected
 *  0b1..Buffer high speed selected
 */
#define DAC_CR2_BFHS(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK)

#define DAC_CR2_IREF2_MASK                       (0x10U)
#define DAC_CR2_IREF2_SHIFT                      (4U)
/*! IREF2 - Internal PTAT (Proportional To Absolute Temperature) Current Reference Select
 *  0b0..Internal PTAT Current Reference not selected
 *  0b1..Internal PTAT Current Reference selected
 */
#define DAC_CR2_IREF2(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK)

#define DAC_CR2_IREF1_MASK                       (0x20U)
#define DAC_CR2_IREF1_SHIFT                      (5U)
/*! IREF1 - Internal ZTC (Zero Temperature Coefficient) Current Reference Select
 *  0b0..Internal ZTC Current Reference not selected
 *  0b1..Internal ZTC Current Reference selected
 */
#define DAC_CR2_IREF1(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK)

#define DAC_CR2_IREF_MASK                        (0x40U)
#define DAC_CR2_IREF_SHIFT                       (6U)
/*! IREF - Internal Current Reference Select
 *  0b0..Internal Current Reference not selected
 *  0b1..Internal Current Reference selected
 */
#define DAC_CR2_IREF(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DAC_Register_Masks */


/* DAC - Peripheral instance base addresses */
/** Peripheral DAC0 base address */
#define DAC0_BASE                                (0x28043000u)
/** Peripheral DAC0 base pointer */
#define DAC0                                     ((DAC_Type *)DAC0_BASE)
/** Peripheral DAC1 base address */
#define DAC1_BASE                                (0x28044000u)
/** Peripheral DAC1 base pointer */
#define DAC1                                     ((DAC_Type *)DAC1_BASE)
/** Array initializer of DAC peripheral base addresses */
#define DAC_BASE_ADDRS                           { DAC0_BASE, DAC1_BASE }
/** Array initializer of DAC peripheral base pointers */
#define DAC_BASE_PTRS                            { DAC0, DAC1 }

/*!
 * @}
 */ /* end of group DAC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
 * @{
 */

/** DMA - Register Layout Typedef */
typedef struct {
  __IO uint32_t MP_CSR;                            /**< Management Page Control, offset: 0x0 */
  __I  uint32_t MP_ES;                             /**< Management Page Error Status, offset: 0x4 */
  __I  uint32_t MP_INT;                            /**< Management Page Interrupt Request Status, offset: 0x8 */
  __I  uint32_t MP_HRS;                            /**< Management Page Hardware Request Status, offset: 0xC */
       uint8_t RESERVED_0[240];
  __IO uint32_t CH_GRPRI[32];                      /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_1[3712];
  struct {                                         /* offset: 0x1000, array step: 0x1000 */
    __IO uint32_t CH_CSR;                            /**< Channel Control and Status, array offset: 0x1000, array step: 0x1000 */
    __IO uint32_t CH_ES;                             /**< Channel Error Status, array offset: 0x1004, array step: 0x1000 */
    __IO uint32_t CH_INT;                            /**< Channel Interrupt Status, array offset: 0x1008, array step: 0x1000 */
    __IO uint32_t CH_SBR;                            /**< Channel System Bus, array offset: 0x100C, array step: 0x1000 */
    __IO uint32_t CH_PRI;                            /**< Channel Priority, array offset: 0x1010, array step: 0x1000 */
    __IO uint32_t CH_MUX;                            /**< Channel Multiplexor Configuration, array offset: 0x1014, array step: 0x1000 */
         uint8_t RESERVED_0[8];
    __IO uint32_t TCD_SADDR;                         /**< TCD Source Address, array offset: 0x1020, array step: 0x1000 */
    __IO uint16_t TCD_SOFF;                          /**< TCD Signed Source Address Offset, array offset: 0x1024, array step: 0x1000 */
    __IO uint16_t TCD_ATTR;                          /**< TCD Transfer Attributes, array offset: 0x1026, array step: 0x1000 */
    union {                                          /* offset: 0x1028, array step: 0x1000 */
      __IO uint32_t TCD_NBYTES_MLOFFNO;                /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */
      __IO uint32_t TCD_NBYTES_MLOFFYES;               /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */
    };
    __IO uint32_t TCD_SLAST_SDA;                     /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x102C, array step: 0x1000 */
    __IO uint32_t TCD_DADDR;                         /**< TCD Destination Address, array offset: 0x1030, array step: 0x1000 */
    __IO uint16_t TCD_DOFF;                          /**< TCD Signed Destination Address Offset, array offset: 0x1034, array step: 0x1000 */
    union {                                          /* offset: 0x1036, array step: 0x1000 */
      __IO uint16_t TCD_CITER_ELINKNO;                 /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000 */
      __IO uint16_t TCD_CITER_ELINKYES;                /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000 */
    };
    __IO uint32_t TCD_DLAST_SGA;                     /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x1038, array step: 0x1000 */
    __IO uint16_t TCD_CSR;                           /**< TCD Control and Status, array offset: 0x103C, array step: 0x1000 */
    union {                                          /* offset: 0x103E, array step: 0x1000 */
      __IO uint16_t TCD_BITER_ELINKNO;                 /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000 */
      __IO uint16_t TCD_BITER_ELINKYES;                /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000 */
    };
         uint8_t RESERVED_1[4032];
  } CH[32];
} DMA_Type;

/* ----------------------------------------------------------------------------
   -- DMA Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_Register_Masks DMA Register Masks
 * @{
 */

/*! @name MP_CSR - Management Page Control */
/*! @{ */

#define DMA_MP_CSR_EDBG_MASK                     (0x2U)
#define DMA_MP_CSR_EDBG_SHIFT                    (1U)
/*! EDBG - Enable Debug
 *  0b0..Debug mode disabled
 *  0b1..Debug mode is enabled.
 */
#define DMA_MP_CSR_EDBG(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK)

#define DMA_MP_CSR_ERCA_MASK                     (0x4U)
#define DMA_MP_CSR_ERCA_SHIFT                    (2U)
/*! ERCA - Enable Round Robin Channel Arbitration
 *  0b0..Round-robin channel arbitration disabled
 *  0b1..Round-robin channel arbitration enabled
 */
#define DMA_MP_CSR_ERCA(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK)

#define DMA_MP_CSR_HAE_MASK                      (0x10U)
#define DMA_MP_CSR_HAE_SHIFT                     (4U)
/*! HAE - Halt After Error
 *  0b0..Normal operation
 *  0b1..Any error causes the HALT field to be set to 1
 */
#define DMA_MP_CSR_HAE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK)

#define DMA_MP_CSR_HALT_MASK                     (0x20U)
#define DMA_MP_CSR_HALT_SHIFT                    (5U)
/*! HALT - Halt DMA Operations
 *  0b0..Normal operation
 *  0b1..Stall the start of any new channels
 */
#define DMA_MP_CSR_HALT(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK)

#define DMA_MP_CSR_GCLC_MASK                     (0x40U)
#define DMA_MP_CSR_GCLC_SHIFT                    (6U)
/*! GCLC - Global Channel Linking Control
 *  0b0..Channel linking disabled for all channels
 *  0b1..Channel linking available and controlled by each channel's link settings
 */
#define DMA_MP_CSR_GCLC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK)

#define DMA_MP_CSR_GMRC_MASK                     (0x80U)
#define DMA_MP_CSR_GMRC_SHIFT                    (7U)
/*! GMRC - Global Master ID Replication Control
 *  0b0..Master ID replication disabled for all channels
 *  0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting
 */
#define DMA_MP_CSR_GMRC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK)

#define DMA_MP_CSR_ECX_MASK                      (0x100U)
#define DMA_MP_CSR_ECX_SHIFT                     (8U)
/*! ECX - Cancel Transfer With Error
 *  0b0..Normal operation
 *  0b1..Cancel the remaining data transfer
 */
#define DMA_MP_CSR_ECX(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK)

#define DMA_MP_CSR_CX_MASK                       (0x200U)
#define DMA_MP_CSR_CX_SHIFT                      (9U)
/*! CX - Cancel Transfer
 *  0b0..Normal operation
 *  0b1..Cancel the remaining data transfer
 */
#define DMA_MP_CSR_CX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK)

#define DMA_MP_CSR_ACTIVE_ID_MASK                (0x1F000000U)
#define DMA_MP_CSR_ACTIVE_ID_SHIFT               (24U)
/*! ACTIVE_ID - Active Channel ID */
#define DMA_MP_CSR_ACTIVE_ID(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK)

#define DMA_MP_CSR_ACTIVE_MASK                   (0x80000000U)
#define DMA_MP_CSR_ACTIVE_SHIFT                  (31U)
/*! ACTIVE - DMA Active Status
 *  0b0..eDMA is idle
 *  0b1..eDMA is executing a channel
 */
#define DMA_MP_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK)
/*! @} */

/*! @name MP_ES - Management Page Error Status */
/*! @{ */

#define DMA_MP_ES_DBE_MASK                       (0x1U)
#define DMA_MP_ES_DBE_SHIFT                      (0U)
/*! DBE - Destination Bus Error
 *  0b0..No destination bus error
 *  0b1..Last recorded error was a bus error on a destination write
 */
#define DMA_MP_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK)

#define DMA_MP_ES_SBE_MASK                       (0x2U)
#define DMA_MP_ES_SBE_SHIFT                      (1U)
/*! SBE - Source Bus Error
 *  0b0..No source bus error
 *  0b1..Last recorded error was a bus error on a source read
 */
#define DMA_MP_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK)

#define DMA_MP_ES_SGE_MASK                       (0x4U)
#define DMA_MP_ES_SGE_SHIFT                      (2U)
/*! SGE - Scatter/Gather Configuration Error
 *  0b0..No scatter/gather configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
 */
#define DMA_MP_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK)

#define DMA_MP_ES_NCE_MASK                       (0x8U)
#define DMA_MP_ES_NCE_SHIFT                      (3U)
/*! NCE - NBYTES/CITER Configuration Error
 *  0b0..No NBYTES/CITER configuration error
 *  0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
 */
#define DMA_MP_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK)

#define DMA_MP_ES_DOE_MASK                       (0x10U)
#define DMA_MP_ES_DOE_SHIFT                      (4U)
/*! DOE - Destination Offset Error
 *  0b0..No destination offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
 */
#define DMA_MP_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK)

#define DMA_MP_ES_DAE_MASK                       (0x20U)
#define DMA_MP_ES_DAE_SHIFT                      (5U)
/*! DAE - Destination Address Error
 *  0b0..No destination address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
 */
#define DMA_MP_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK)

#define DMA_MP_ES_SOE_MASK                       (0x40U)
#define DMA_MP_ES_SOE_SHIFT                      (6U)
/*! SOE - Source Offset Error
 *  0b0..No source offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
 */
#define DMA_MP_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK)

#define DMA_MP_ES_SAE_MASK                       (0x80U)
#define DMA_MP_ES_SAE_SHIFT                      (7U)
/*! SAE - Source Address Error
 *  0b0..No source address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
 */
#define DMA_MP_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK)

#define DMA_MP_ES_ECX_MASK                       (0x100U)
#define DMA_MP_ES_ECX_SHIFT                      (8U)
/*! ECX - Transfer Canceled
 *  0b0..No canceled transfers
 *  0b1..Last recorded entry was a canceled transfer by the error cancel transfer input
 */
#define DMA_MP_ES_ECX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK)

#define DMA_MP_ES_ERRCHN_MASK                    (0x1F000000U)
#define DMA_MP_ES_ERRCHN_SHIFT                   (24U)
/*! ERRCHN - Error Channel Number or Canceled Channel Number */
#define DMA_MP_ES_ERRCHN(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK)

#define DMA_MP_ES_VLD_MASK                       (0x80000000U)
#define DMA_MP_ES_VLD_SHIFT                      (31U)
/*! VLD - Valid
 *  0b0..No ERR fields are set to 1
 *  0b1..At least one ERR field is set to 1, indicating a valid error exists that software has not cleared
 */
#define DMA_MP_ES_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK)
/*! @} */

/*! @name MP_INT - Management Page Interrupt Request Status */
/*! @{ */

#define DMA_MP_INT_INT_MASK                      (0xFFFFFFFFU)
#define DMA_MP_INT_INT_SHIFT                     (0U)
/*! INT - Interrupt Request Status */
#define DMA_MP_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK)
/*! @} */

/*! @name MP_HRS - Management Page Hardware Request Status */
/*! @{ */

#define DMA_MP_HRS_HRS_MASK                      (0xFFFFFFFFU)
#define DMA_MP_HRS_HRS_SHIFT                     (0U)
/*! HRS - Hardware Request Status */
#define DMA_MP_HRS_HRS(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK)
/*! @} */

/*! @name CH_GRPRI - Channel Arbitration Group */
/*! @{ */

#define DMA_CH_GRPRI_GRPRI_MASK                  (0x1FU)
#define DMA_CH_GRPRI_GRPRI_SHIFT                 (0U)
/*! GRPRI - Arbitration Group For Channel n */
#define DMA_CH_GRPRI_GRPRI(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK)
/*! @} */

/* The count of DMA_CH_GRPRI */
#define DMA_CH_GRPRI_COUNT                       (32U)

/*! @name CH_CSR - Channel Control and Status */
/*! @{ */

#define DMA_CH_CSR_ERQ_MASK                      (0x1U)
#define DMA_CH_CSR_ERQ_SHIFT                     (0U)
/*! ERQ - Enable DMA Request
 *  0b0..DMA hardware request signal for corresponding channel disabled
 *  0b1..DMA hardware request signal for corresponding channel enabled
 */
#define DMA_CH_CSR_ERQ(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)

#define DMA_CH_CSR_EARQ_MASK                     (0x2U)
#define DMA_CH_CSR_EARQ_SHIFT                    (1U)
/*! EARQ - Enable Asynchronous DMA Request
 *  0b0..Disable asynchronous DMA request for the channel
 *  0b1..Enable asynchronous DMA request for the channel
 */
#define DMA_CH_CSR_EARQ(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK)

#define DMA_CH_CSR_EEI_MASK                      (0x4U)
#define DMA_CH_CSR_EEI_SHIFT                     (2U)
/*! EEI - Enable Error Interrupt
 *  0b0..Error signal for corresponding channel does not generate error interrupt
 *  0b1..Assertion of error signal for corresponding channel generates error interrupt request
 */
#define DMA_CH_CSR_EEI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK)

#define DMA_CH_CSR_EBW_MASK                      (0x8U)
#define DMA_CH_CSR_EBW_SHIFT                     (3U)
/*! EBW - Enable Buffered Writes
 *  0b0..Buffered writes on system bus disabled
 *  0b1..Buffered writes on system bus enabled
 */
#define DMA_CH_CSR_EBW(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK)

#define DMA_CH_CSR_DONE_MASK                     (0x40000000U)
#define DMA_CH_CSR_DONE_SHIFT                    (30U)
/*! DONE - Channel Done */
#define DMA_CH_CSR_DONE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK)

#define DMA_CH_CSR_ACTIVE_MASK                   (0x80000000U)
#define DMA_CH_CSR_ACTIVE_SHIFT                  (31U)
/*! ACTIVE - Channel Active */
#define DMA_CH_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK)
/*! @} */

/* The count of DMA_CH_CSR */
#define DMA_CH_CSR_COUNT                         (32U)

/*! @name CH_ES - Channel Error Status */
/*! @{ */

#define DMA_CH_ES_DBE_MASK                       (0x1U)
#define DMA_CH_ES_DBE_SHIFT                      (0U)
/*! DBE - Destination Bus Error
 *  0b0..No destination bus error
 *  0b1..Last recorded error was bus error on destination write
 */
#define DMA_CH_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK)

#define DMA_CH_ES_SBE_MASK                       (0x2U)
#define DMA_CH_ES_SBE_SHIFT                      (1U)
/*! SBE - Source Bus Error
 *  0b0..No source bus error
 *  0b1..Last recorded error was bus error on source read
 */
#define DMA_CH_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK)

#define DMA_CH_ES_SGE_MASK                       (0x4U)
#define DMA_CH_ES_SGE_SHIFT                      (2U)
/*! SGE - Scatter/Gather Configuration Error
 *  0b0..No scatter/gather configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
 */
#define DMA_CH_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK)

#define DMA_CH_ES_NCE_MASK                       (0x8U)
#define DMA_CH_ES_NCE_SHIFT                      (3U)
/*! NCE - NBYTES/CITER Configuration Error
 *  0b0..No NBYTES/CITER configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields
 */
#define DMA_CH_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK)

#define DMA_CH_ES_DOE_MASK                       (0x10U)
#define DMA_CH_ES_DOE_SHIFT                      (4U)
/*! DOE - Destination Offset Error
 *  0b0..No destination offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
 */
#define DMA_CH_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK)

#define DMA_CH_ES_DAE_MASK                       (0x20U)
#define DMA_CH_ES_DAE_SHIFT                      (5U)
/*! DAE - Destination Address Error
 *  0b0..No destination address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
 */
#define DMA_CH_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK)

#define DMA_CH_ES_SOE_MASK                       (0x40U)
#define DMA_CH_ES_SOE_SHIFT                      (6U)
/*! SOE - Source Offset Error
 *  0b0..No source offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
 */
#define DMA_CH_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK)

#define DMA_CH_ES_SAE_MASK                       (0x80U)
#define DMA_CH_ES_SAE_SHIFT                      (7U)
/*! SAE - Source Address Error
 *  0b0..No source address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
 */
#define DMA_CH_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK)

#define DMA_CH_ES_ERR_MASK                       (0x80000000U)
#define DMA_CH_ES_ERR_SHIFT                      (31U)
/*! ERR - Error In Channel
 *  0b0..An error in this channel has not occurred
 *  0b1..An error in this channel has occurred
 */
#define DMA_CH_ES_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK)
/*! @} */

/* The count of DMA_CH_ES */
#define DMA_CH_ES_COUNT                          (32U)

/*! @name CH_INT - Channel Interrupt Status */
/*! @{ */

#define DMA_CH_INT_INT_MASK                      (0x1U)
#define DMA_CH_INT_INT_SHIFT                     (0U)
/*! INT - Interrupt Request
 *  0b0..Interrupt request for corresponding channel cleared
 *  0b1..Interrupt request for corresponding channel active
 */
#define DMA_CH_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/*! @} */

/* The count of DMA_CH_INT */
#define DMA_CH_INT_COUNT                         (32U)

/*! @name CH_SBR - Channel System Bus */
/*! @{ */

#define DMA_CH_SBR_MID_MASK                      (0x3FU)
#define DMA_CH_SBR_MID_SHIFT                     (0U)
/*! MID - Master ID */
#define DMA_CH_SBR_MID(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK)

#define DMA_CH_SBR_SEC_MASK                      (0x4000U)
#define DMA_CH_SBR_SEC_SHIFT                     (14U)
/*! SEC - Security Level
 *  0b0..Nonsecure protection level for DMA transfers
 *  0b1..Secure protection level for DMA transfers
 */
#define DMA_CH_SBR_SEC(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_SEC_SHIFT)) & DMA_CH_SBR_SEC_MASK)

#define DMA_CH_SBR_PAL_MASK                      (0x8000U)
#define DMA_CH_SBR_PAL_SHIFT                     (15U)
/*! PAL - Privileged Access Level
 *  0b0..User protection level for DMA transfers
 *  0b1..Privileged protection level for DMA transfers
 */
#define DMA_CH_SBR_PAL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK)

#define DMA_CH_SBR_EMI_MASK                      (0x10000U)
#define DMA_CH_SBR_EMI_SHIFT                     (16U)
/*! EMI - Enable Master ID Replication
 *  0b0..Master ID replication is disabled
 *  0b1..Master ID replication is enabled
 */
#define DMA_CH_SBR_EMI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK)

#define DMA_CH_SBR_ATTR_MASK                     (0x1E0000U)
#define DMA_CH_SBR_ATTR_SHIFT                    (17U)
/*! ATTR - Attribute Output */
#define DMA_CH_SBR_ATTR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_ATTR_SHIFT)) & DMA_CH_SBR_ATTR_MASK)
/*! @} */

/* The count of DMA_CH_SBR */
#define DMA_CH_SBR_COUNT                         (32U)

/*! @name CH_PRI - Channel Priority */
/*! @{ */

#define DMA_CH_PRI_APL_MASK                      (0x7U)
#define DMA_CH_PRI_APL_SHIFT                     (0U)
/*! APL - Arbitration Priority Level */
#define DMA_CH_PRI_APL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK)

#define DMA_CH_PRI_DPA_MASK                      (0x40000000U)
#define DMA_CH_PRI_DPA_SHIFT                     (30U)
/*! DPA - Disable Preempt Ability
 *  0b0..Channel can suspend a lower-priority channel
 *  0b1..Channel cannot suspend any other channel, regardless of channel priority
 */
#define DMA_CH_PRI_DPA(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK)

#define DMA_CH_PRI_ECP_MASK                      (0x80000000U)
#define DMA_CH_PRI_ECP_SHIFT                     (31U)
/*! ECP - Enable Channel Preemption
 *  0b0..Channel cannot be suspended by a higher-priority channel's service request
 *  0b1..Channel can be temporarily suspended by a higher-priority channel's service request
 */
#define DMA_CH_PRI_ECP(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK)
/*! @} */

/* The count of DMA_CH_PRI */
#define DMA_CH_PRI_COUNT                         (32U)

/*! @name CH_MUX - Channel Multiplexor Configuration */
/*! @{ */

#define DMA_CH_MUX_SRC_MASK                      (0x7FU)
#define DMA_CH_MUX_SRC_SHIFT                     (0U)
/*! SRC - Service Request Source */
#define DMA_CH_MUX_SRC(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK)
/*! @} */

/* The count of DMA_CH_MUX */
#define DMA_CH_MUX_COUNT                         (32U)

/*! @name TCD_SADDR - TCD Source Address */
/*! @{ */

#define DMA_TCD_SADDR_SADDR_MASK                 (0xFFFFFFFFU)
#define DMA_TCD_SADDR_SADDR_SHIFT                (0U)
/*! SADDR - Source Address */
#define DMA_TCD_SADDR_SADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK)
/*! @} */

/* The count of DMA_TCD_SADDR */
#define DMA_TCD_SADDR_COUNT                      (32U)

/*! @name TCD_SOFF - TCD Signed Source Address Offset */
/*! @{ */

#define DMA_TCD_SOFF_SOFF_MASK                   (0xFFFFU)
#define DMA_TCD_SOFF_SOFF_SHIFT                  (0U)
/*! SOFF - Source Address Signed Offset */
#define DMA_TCD_SOFF_SOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK)
/*! @} */

/* The count of DMA_TCD_SOFF */
#define DMA_TCD_SOFF_COUNT                       (32U)

/*! @name TCD_ATTR - TCD Transfer Attributes */
/*! @{ */

#define DMA_TCD_ATTR_DSIZE_MASK                  (0x7U)
#define DMA_TCD_ATTR_DSIZE_SHIFT                 (0U)
/*! DSIZE - Destination Data Transfer Size */
#define DMA_TCD_ATTR_DSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK)

#define DMA_TCD_ATTR_DMOD_MASK                   (0xF8U)
#define DMA_TCD_ATTR_DMOD_SHIFT                  (3U)
/*! DMOD - Destination Address Modulo */
#define DMA_TCD_ATTR_DMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK)

#define DMA_TCD_ATTR_SSIZE_MASK                  (0x700U)
#define DMA_TCD_ATTR_SSIZE_SHIFT                 (8U)
/*! SSIZE - Source Data Transfer Size
 *  0b000..8-bit
 *  0b001..16-bit
 *  0b010..32-bit
 *  0b011..64-bit
 *  0b100..16-byte
 *  0b101..32-byte
 *  0b110..64-byte
 *  0b111..
 */
#define DMA_TCD_ATTR_SSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK)

#define DMA_TCD_ATTR_SMOD_MASK                   (0xF800U)
#define DMA_TCD_ATTR_SMOD_SHIFT                  (11U)
/*! SMOD - Source Address Modulo
 *  0b00000..Source address modulo feature disabled
 *  0b00001..Source address modulo feature enabled for any non-zero value [1-31]
 */
#define DMA_TCD_ATTR_SMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK)
/*! @} */

/* The count of DMA_TCD_ATTR */
#define DMA_TCD_ATTR_COUNT                       (32U)

/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */
/*! @{ */

#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK       (0x3FFFFFFFU)
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT      (0U)
/*! NBYTES - Number of Bytes To Transfer Per Service Request */
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)

#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK        (0x40000000U)
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT       (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to DADDR
 *  0b1..Minor loop offset applied to DADDR
 */
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)

#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK        (0x80000000U)
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT       (31U)
/*! SMLOE - Source Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to SADDR
 *  0b1..Minor loop offset applied to SADDR
 */
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
/*! @} */

/* The count of DMA_TCD_NBYTES_MLOFFNO */
#define DMA_TCD_NBYTES_MLOFFNO_COUNT             (32U)

/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */
/*! @{ */

#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK      (0x3FFU)
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT     (0U)
/*! NBYTES - Number of Bytes To Transfer Per Service Request */
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)        (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)

#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK       (0x3FFFFC00U)
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT      (10U)
/*! MLOFF - Minor Loop Offset */
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)

#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK       (0x40000000U)
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT      (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to DADDR
 *  0b1..Minor loop offset applied to DADDR
 */
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)

#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK       (0x80000000U)
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT      (31U)
/*! SMLOE - Source Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to SADDR
 *  0b1..Minor loop offset applied to SADDR
 */
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
/*! @} */

/* The count of DMA_TCD_NBYTES_MLOFFYES */
#define DMA_TCD_NBYTES_MLOFFYES_COUNT            (32U)

/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */
/*! @{ */

#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK         (0xFFFFFFFFU)
#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT        (0U)
/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */
#define DMA_TCD_SLAST_SDA_SLAST_SDA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK)
/*! @} */

/* The count of DMA_TCD_SLAST_SDA */
#define DMA_TCD_SLAST_SDA_COUNT                  (32U)

/*! @name TCD_DADDR - TCD Destination Address */
/*! @{ */

#define DMA_TCD_DADDR_DADDR_MASK                 (0xFFFFFFFFU)
#define DMA_TCD_DADDR_DADDR_SHIFT                (0U)
/*! DADDR - Destination Address */
#define DMA_TCD_DADDR_DADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK)
/*! @} */

/* The count of DMA_TCD_DADDR */
#define DMA_TCD_DADDR_COUNT                      (32U)

/*! @name TCD_DOFF - TCD Signed Destination Address Offset */
/*! @{ */

#define DMA_TCD_DOFF_DOFF_MASK                   (0xFFFFU)
#define DMA_TCD_DOFF_DOFF_SHIFT                  (0U)
/*! DOFF - Destination Address Signed Offset */
#define DMA_TCD_DOFF_DOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK)
/*! @} */

/* The count of DMA_TCD_DOFF */
#define DMA_TCD_DOFF_COUNT                       (32U)

/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */
/*! @{ */

#define DMA_TCD_CITER_ELINKNO_CITER_MASK         (0x7FFFU)
#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT        (0U)
/*! CITER - Current Major Iteration Count */
#define DMA_TCD_CITER_ELINKNO_CITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK)

#define DMA_TCD_CITER_ELINKNO_ELINK_MASK         (0x8000U)
#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT        (15U)
/*! ELINK - Enable Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_CITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_CITER_ELINKNO */
#define DMA_TCD_CITER_ELINKNO_COUNT              (32U)

/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */
/*! @{ */

#define DMA_TCD_CITER_ELINKYES_CITER_MASK        (0x1FFU)
#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT       (0U)
/*! CITER - Current Major Iteration Count */
#define DMA_TCD_CITER_ELINKYES_CITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK)

#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK       (0x3E00U)
#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT      (9U)
/*! LINKCH - Minor Loop Link Channel Number */
#define DMA_TCD_CITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK)

#define DMA_TCD_CITER_ELINKYES_ELINK_MASK        (0x8000U)
#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT       (15U)
/*! ELINK - Enable Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_CITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_CITER_ELINKYES */
#define DMA_TCD_CITER_ELINKYES_COUNT             (32U)

/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */
/*! @{ */

#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK         (0xFFFFFFFFU)
#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT        (0U)
/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */
#define DMA_TCD_DLAST_SGA_DLAST_SGA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK)
/*! @} */

/* The count of DMA_TCD_DLAST_SGA */
#define DMA_TCD_DLAST_SGA_COUNT                  (32U)

/*! @name TCD_CSR - TCD Control and Status */
/*! @{ */

#define DMA_TCD_CSR_START_MASK                   (0x1U)
#define DMA_TCD_CSR_START_SHIFT                  (0U)
/*! START - Channel Start
 *  0b0..Channel not explicitly started
 *  0b1..Channel explicitly started via a software-initiated service request
 */
#define DMA_TCD_CSR_START(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK)

#define DMA_TCD_CSR_INTMAJOR_MASK                (0x2U)
#define DMA_TCD_CSR_INTMAJOR_SHIFT               (1U)
/*! INTMAJOR - Enable Interrupt If Major count complete
 *  0b0..End-of-major loop interrupt disabled
 *  0b1..End-of-major loop interrupt enabled
 */
#define DMA_TCD_CSR_INTMAJOR(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK)

#define DMA_TCD_CSR_INTHALF_MASK                 (0x4U)
#define DMA_TCD_CSR_INTHALF_SHIFT                (2U)
/*! INTHALF - Enable Interrupt If Major Counter Half-complete
 *  0b0..Halfway point interrupt disabled
 *  0b1..Halfway point interrupt enabled
 */
#define DMA_TCD_CSR_INTHALF(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK)

#define DMA_TCD_CSR_DREQ_MASK                    (0x8U)
#define DMA_TCD_CSR_DREQ_SHIFT                   (3U)
/*! DREQ - Disable Request
 *  0b0..No operation
 *  0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests
 */
#define DMA_TCD_CSR_DREQ(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)

#define DMA_TCD_CSR_ESG_MASK                     (0x10U)
#define DMA_TCD_CSR_ESG_SHIFT                    (4U)
/*! ESG - Enable Scatter/Gather Processing
 *  0b0..Current channel's TCD is normal format
 *  0b1..Current channel's TCD specifies scatter/gather format.
 */
#define DMA_TCD_CSR_ESG(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK)

#define DMA_TCD_CSR_MAJORELINK_MASK              (0x20U)
#define DMA_TCD_CSR_MAJORELINK_SHIFT             (5U)
/*! MAJORELINK - Enable Link When Major Loop Complete
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_CSR_MAJORELINK(x)                (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK)

#define DMA_TCD_CSR_EEOP_MASK                    (0x40U)
#define DMA_TCD_CSR_EEOP_SHIFT                   (6U)
/*! EEOP - Enable End-Of-Packet Processing
 *  0b0..End-of-packet operation disabled
 *  0b1..End-of-packet hardware input signal enabled
 */
#define DMA_TCD_CSR_EEOP(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK)

#define DMA_TCD_CSR_ESDA_MASK                    (0x80U)
#define DMA_TCD_CSR_ESDA_SHIFT                   (7U)
/*! ESDA - Enable Store Destination Address
 *  0b0..Ability to store destination address to system memory disabled
 *  0b1..Ability to store destination address to system memory enabled
 */
#define DMA_TCD_CSR_ESDA(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK)

#define DMA_TCD_CSR_MAJORLINKCH_MASK             (0x1F00U)
#define DMA_TCD_CSR_MAJORLINKCH_SHIFT            (8U)
/*! MAJORLINKCH - Major Loop Link Channel Number */
#define DMA_TCD_CSR_MAJORLINKCH(x)               (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK)

#define DMA_TCD_CSR_BWC_MASK                     (0xC000U)
#define DMA_TCD_CSR_BWC_SHIFT                    (14U)
/*! BWC - Bandwidth Control
 *  0b00..No eDMA engine stalls
 *  0b01..Enable eDMA master high-priority elevation (HPE) mode. No eDMA engine stalls.
 *  0b10..eDMA engine stalls for 4 cycles after each R/W
 *  0b11..eDMA engine stalls for 8 cycles after each R/W
 */
#define DMA_TCD_CSR_BWC(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK)
/*! @} */

/* The count of DMA_TCD_CSR */
#define DMA_TCD_CSR_COUNT                        (32U)

/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */
/*! @{ */

#define DMA_TCD_BITER_ELINKNO_BITER_MASK         (0x7FFFU)
#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT        (0U)
/*! BITER - Starting Major Iteration Count */
#define DMA_TCD_BITER_ELINKNO_BITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK)

#define DMA_TCD_BITER_ELINKNO_ELINK_MASK         (0x8000U)
#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT        (15U)
/*! ELINK - Enables Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_BITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_BITER_ELINKNO */
#define DMA_TCD_BITER_ELINKNO_COUNT              (32U)

/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */
/*! @{ */

#define DMA_TCD_BITER_ELINKYES_BITER_MASK        (0x1FFU)
#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT       (0U)
/*! BITER - Starting Major Iteration Count */
#define DMA_TCD_BITER_ELINKYES_BITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK)

#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK       (0x3E00U)
#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT      (9U)
/*! LINKCH - Link Channel Number */
#define DMA_TCD_BITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK)

#define DMA_TCD_BITER_ELINKYES_ELINK_MASK        (0x8000U)
#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT       (15U)
/*! ELINK - Enable Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_BITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_BITER_ELINKYES */
#define DMA_TCD_BITER_ELINKYES_COUNT             (32U)


/*!
 * @}
 */ /* end of group DMA_Register_Masks */


/* DMA - Peripheral instance base addresses */
/** Peripheral DMA0 base address */
#define DMA0_BASE                                (0x28001000u)
/** Peripheral DMA0 base pointer */
#define DMA0                                     ((DMA_Type *)DMA0_BASE)
/** Array initializer of DMA peripheral base addresses */
#define DMA_BASE_ADDRS                           { DMA0_BASE }
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASE_PTRS                            { DMA0 }

/*!
 * @}
 */ /* end of group DMA_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_AD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_AD_Peripheral_Access_Layer DMA_AD Peripheral Access Layer
 * @{
 */

/** DMA_AD - Register Layout Typedef */
typedef struct {
  __IO uint32_t MP_CSR;                            /**< Management Page Control, offset: 0x0 */
  __I  uint32_t MP_ES;                             /**< Management Page Error Status, offset: 0x4 */
  __I  uint32_t MP_INT;                            /**< Management Page Interrupt Request Status, offset: 0x8 */
  __I  uint32_t MP_HRS;                            /**< Management Page Hardware Request Status, offset: 0xC */
       uint8_t RESERVED_0[240];
  __IO uint32_t CH_GRPRI[32];                      /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_1[65152];
  struct {                                         /* offset: 0x10000, array step: 0x10000 */
    __IO uint32_t CH_CSR;                            /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
    __IO uint32_t CH_ES;                             /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
    __IO uint32_t CH_INT;                            /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */
    __IO uint32_t CH_SBR;                            /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */
    __IO uint32_t CH_PRI;                            /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */
    __IO uint32_t CH_MUX;                            /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */
         uint8_t RESERVED_0[8];
    __IO uint32_t TCD_SADDR;                         /**< TCD Source Address, array offset: 0x10020, array step: 0x10000 */
    __IO uint16_t TCD_SOFF;                          /**< TCD Signed Source Address Offset, array offset: 0x10024, array step: 0x10000 */
    __IO uint16_t TCD_ATTR;                          /**< TCD Transfer Attributes, array offset: 0x10026, array step: 0x10000 */
    union {                                          /* offset: 0x10028, array step: 0x10000 */
      __IO uint32_t TCD_NBYTES_MLOFFNO;                /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x10028, array step: 0x10000 */
      __IO uint32_t TCD_NBYTES_MLOFFYES;               /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x10028, array step: 0x10000 */
    };
    __IO uint32_t TCD_SLAST_SDA;                     /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x1002C, array step: 0x10000 */
    __IO uint32_t TCD_DADDR;                         /**< TCD Destination Address, array offset: 0x10030, array step: 0x10000 */
    __IO uint16_t TCD_DOFF;                          /**< TCD Signed Destination Address Offset, array offset: 0x10034, array step: 0x10000 */
    union {                                          /* offset: 0x10036, array step: 0x10000 */
      __IO uint16_t TCD_CITER_ELINKNO;                 /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x10036, array step: 0x10000 */
      __IO uint16_t TCD_CITER_ELINKYES;                /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x10036, array step: 0x10000 */
    };
    __IO uint32_t TCD_DLAST_SGA;                     /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x10038, array step: 0x10000 */
    __IO uint16_t TCD_CSR;                           /**< TCD Control and Status, array offset: 0x1003C, array step: 0x10000 */
    union {                                          /* offset: 0x1003E, array step: 0x10000 */
      __IO uint16_t TCD_BITER_ELINKNO;                 /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1003E, array step: 0x10000 */
      __IO uint16_t TCD_BITER_ELINKYES;                /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1003E, array step: 0x10000 */
    };
         uint8_t RESERVED_1[65472];
  } CH[32];
} DMA_AD_Type;

/* ----------------------------------------------------------------------------
   -- DMA_AD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_AD_Register_Masks DMA_AD Register Masks
 * @{
 */

/*! @name MP_CSR - Management Page Control */
/*! @{ */

#define DMA_AD_MP_CSR_EDBG_MASK                  (0x2U)
#define DMA_AD_MP_CSR_EDBG_SHIFT                 (1U)
/*! EDBG - Enable Debug
 *  0b0..Debug mode disabled
 *  0b1..Debug mode is enabled.
 */
#define DMA_AD_MP_CSR_EDBG(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_CSR_EDBG_SHIFT)) & DMA_AD_MP_CSR_EDBG_MASK)

#define DMA_AD_MP_CSR_ERCA_MASK                  (0x4U)
#define DMA_AD_MP_CSR_ERCA_SHIFT                 (2U)
/*! ERCA - Enable Round Robin Channel Arbitration
 *  0b0..Round-robin channel arbitration disabled
 *  0b1..Round-robin channel arbitration enabled
 */
#define DMA_AD_MP_CSR_ERCA(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_CSR_ERCA_SHIFT)) & DMA_AD_MP_CSR_ERCA_MASK)

#define DMA_AD_MP_CSR_HAE_MASK                   (0x10U)
#define DMA_AD_MP_CSR_HAE_SHIFT                  (4U)
/*! HAE - Halt After Error
 *  0b0..Normal operation
 *  0b1..Any error causes the HALT field to be set to 1
 */
#define DMA_AD_MP_CSR_HAE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_CSR_HAE_SHIFT)) & DMA_AD_MP_CSR_HAE_MASK)

#define DMA_AD_MP_CSR_HALT_MASK                  (0x20U)
#define DMA_AD_MP_CSR_HALT_SHIFT                 (5U)
/*! HALT - Halt DMA Operations
 *  0b0..Normal operation
 *  0b1..Stall the start of any new channels
 */
#define DMA_AD_MP_CSR_HALT(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_CSR_HALT_SHIFT)) & DMA_AD_MP_CSR_HALT_MASK)

#define DMA_AD_MP_CSR_GCLC_MASK                  (0x40U)
#define DMA_AD_MP_CSR_GCLC_SHIFT                 (6U)
/*! GCLC - Global Channel Linking Control
 *  0b0..Channel linking disabled for all channels
 *  0b1..Channel linking available and controlled by each channel's link settings
 */
#define DMA_AD_MP_CSR_GCLC(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_CSR_GCLC_SHIFT)) & DMA_AD_MP_CSR_GCLC_MASK)

#define DMA_AD_MP_CSR_GMRC_MASK                  (0x80U)
#define DMA_AD_MP_CSR_GMRC_SHIFT                 (7U)
/*! GMRC - Global Master ID Replication Control
 *  0b0..Master ID replication disabled for all channels
 *  0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting
 */
#define DMA_AD_MP_CSR_GMRC(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_CSR_GMRC_SHIFT)) & DMA_AD_MP_CSR_GMRC_MASK)

#define DMA_AD_MP_CSR_ECX_MASK                   (0x100U)
#define DMA_AD_MP_CSR_ECX_SHIFT                  (8U)
/*! ECX - Cancel Transfer With Error
 *  0b0..Normal operation
 *  0b1..Cancel the remaining data transfer
 */
#define DMA_AD_MP_CSR_ECX(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_CSR_ECX_SHIFT)) & DMA_AD_MP_CSR_ECX_MASK)

#define DMA_AD_MP_CSR_CX_MASK                    (0x200U)
#define DMA_AD_MP_CSR_CX_SHIFT                   (9U)
/*! CX - Cancel Transfer
 *  0b0..Normal operation
 *  0b1..Cancel the remaining data transfer
 */
#define DMA_AD_MP_CSR_CX(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_CSR_CX_SHIFT)) & DMA_AD_MP_CSR_CX_MASK)

#define DMA_AD_MP_CSR_ACTIVE_ID_MASK             (0x1F000000U)
#define DMA_AD_MP_CSR_ACTIVE_ID_SHIFT            (24U)
/*! ACTIVE_ID - Active Channel ID */
#define DMA_AD_MP_CSR_ACTIVE_ID(x)               (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_AD_MP_CSR_ACTIVE_ID_MASK)

#define DMA_AD_MP_CSR_ACTIVE_MASK                (0x80000000U)
#define DMA_AD_MP_CSR_ACTIVE_SHIFT               (31U)
/*! ACTIVE - DMA Active Status
 *  0b0..eDMA is idle
 *  0b1..eDMA is executing a channel
 */
#define DMA_AD_MP_CSR_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_CSR_ACTIVE_SHIFT)) & DMA_AD_MP_CSR_ACTIVE_MASK)
/*! @} */

/*! @name MP_ES - Management Page Error Status */
/*! @{ */

#define DMA_AD_MP_ES_DBE_MASK                    (0x1U)
#define DMA_AD_MP_ES_DBE_SHIFT                   (0U)
/*! DBE - Destination Bus Error
 *  0b0..No destination bus error
 *  0b1..Last recorded error was a bus error on a destination write
 */
#define DMA_AD_MP_ES_DBE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_ES_DBE_SHIFT)) & DMA_AD_MP_ES_DBE_MASK)

#define DMA_AD_MP_ES_SBE_MASK                    (0x2U)
#define DMA_AD_MP_ES_SBE_SHIFT                   (1U)
/*! SBE - Source Bus Error
 *  0b0..No source bus error
 *  0b1..Last recorded error was a bus error on a source read
 */
#define DMA_AD_MP_ES_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_ES_SBE_SHIFT)) & DMA_AD_MP_ES_SBE_MASK)

#define DMA_AD_MP_ES_SGE_MASK                    (0x4U)
#define DMA_AD_MP_ES_SGE_SHIFT                   (2U)
/*! SGE - Scatter/Gather Configuration Error
 *  0b0..No scatter/gather configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
 */
#define DMA_AD_MP_ES_SGE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_ES_SGE_SHIFT)) & DMA_AD_MP_ES_SGE_MASK)

#define DMA_AD_MP_ES_NCE_MASK                    (0x8U)
#define DMA_AD_MP_ES_NCE_SHIFT                   (3U)
/*! NCE - NBYTES/CITER Configuration Error
 *  0b0..No NBYTES/CITER configuration error
 *  0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
 */
#define DMA_AD_MP_ES_NCE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_ES_NCE_SHIFT)) & DMA_AD_MP_ES_NCE_MASK)

#define DMA_AD_MP_ES_DOE_MASK                    (0x10U)
#define DMA_AD_MP_ES_DOE_SHIFT                   (4U)
/*! DOE - Destination Offset Error
 *  0b0..No destination offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
 */
#define DMA_AD_MP_ES_DOE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_ES_DOE_SHIFT)) & DMA_AD_MP_ES_DOE_MASK)

#define DMA_AD_MP_ES_DAE_MASK                    (0x20U)
#define DMA_AD_MP_ES_DAE_SHIFT                   (5U)
/*! DAE - Destination Address Error
 *  0b0..No destination address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
 */
#define DMA_AD_MP_ES_DAE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_ES_DAE_SHIFT)) & DMA_AD_MP_ES_DAE_MASK)

#define DMA_AD_MP_ES_SOE_MASK                    (0x40U)
#define DMA_AD_MP_ES_SOE_SHIFT                   (6U)
/*! SOE - Source Offset Error
 *  0b0..No source offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
 */
#define DMA_AD_MP_ES_SOE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_ES_SOE_SHIFT)) & DMA_AD_MP_ES_SOE_MASK)

#define DMA_AD_MP_ES_SAE_MASK                    (0x80U)
#define DMA_AD_MP_ES_SAE_SHIFT                   (7U)
/*! SAE - Source Address Error
 *  0b0..No source address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
 */
#define DMA_AD_MP_ES_SAE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_ES_SAE_SHIFT)) & DMA_AD_MP_ES_SAE_MASK)

#define DMA_AD_MP_ES_ECX_MASK                    (0x100U)
#define DMA_AD_MP_ES_ECX_SHIFT                   (8U)
/*! ECX - Transfer Canceled
 *  0b0..No canceled transfers
 *  0b1..Last recorded entry was a canceled transfer by the error cancel transfer input
 */
#define DMA_AD_MP_ES_ECX(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_ES_ECX_SHIFT)) & DMA_AD_MP_ES_ECX_MASK)

#define DMA_AD_MP_ES_ERRCHN_MASK                 (0x1F000000U)
#define DMA_AD_MP_ES_ERRCHN_SHIFT                (24U)
/*! ERRCHN - Error Channel Number or Canceled Channel Number */
#define DMA_AD_MP_ES_ERRCHN(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_ES_ERRCHN_SHIFT)) & DMA_AD_MP_ES_ERRCHN_MASK)

#define DMA_AD_MP_ES_VLD_MASK                    (0x80000000U)
#define DMA_AD_MP_ES_VLD_SHIFT                   (31U)
/*! VLD - Valid
 *  0b0..No ERR fields are set to 1
 *  0b1..At least one ERR field is set to 1, indicating a valid error exists that software has not cleared
 */
#define DMA_AD_MP_ES_VLD(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_ES_VLD_SHIFT)) & DMA_AD_MP_ES_VLD_MASK)
/*! @} */

/*! @name MP_INT - Management Page Interrupt Request Status */
/*! @{ */

#define DMA_AD_MP_INT_INT_MASK                   (0xFFFFFFFFU)
#define DMA_AD_MP_INT_INT_SHIFT                  (0U)
/*! INT - Interrupt Request Status */
#define DMA_AD_MP_INT_INT(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_INT_INT_SHIFT)) & DMA_AD_MP_INT_INT_MASK)
/*! @} */

/*! @name MP_HRS - Management Page Hardware Request Status */
/*! @{ */

#define DMA_AD_MP_HRS_HRS_MASK                   (0xFFFFFFFFU)
#define DMA_AD_MP_HRS_HRS_SHIFT                  (0U)
/*! HRS - Hardware Request Status */
#define DMA_AD_MP_HRS_HRS(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_MP_HRS_HRS_SHIFT)) & DMA_AD_MP_HRS_HRS_MASK)
/*! @} */

/*! @name CH_GRPRI - Channel Arbitration Group */
/*! @{ */

#define DMA_AD_CH_GRPRI_GRPRI_MASK               (0x1FU)
#define DMA_AD_CH_GRPRI_GRPRI_SHIFT              (0U)
/*! GRPRI - Arbitration Group For Channel n */
#define DMA_AD_CH_GRPRI_GRPRI(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_GRPRI_GRPRI_SHIFT)) & DMA_AD_CH_GRPRI_GRPRI_MASK)
/*! @} */

/* The count of DMA_AD_CH_GRPRI */
#define DMA_AD_CH_GRPRI_COUNT                    (32U)

/*! @name CH_CSR - Channel Control and Status */
/*! @{ */

#define DMA_AD_CH_CSR_ERQ_MASK                   (0x1U)
#define DMA_AD_CH_CSR_ERQ_SHIFT                  (0U)
/*! ERQ - Enable DMA Request
 *  0b0..DMA hardware request signal for corresponding channel disabled
 *  0b1..DMA hardware request signal for corresponding channel enabled
 */
#define DMA_AD_CH_CSR_ERQ(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_CSR_ERQ_SHIFT)) & DMA_AD_CH_CSR_ERQ_MASK)

#define DMA_AD_CH_CSR_EARQ_MASK                  (0x2U)
#define DMA_AD_CH_CSR_EARQ_SHIFT                 (1U)
/*! EARQ - Enable Asynchronous DMA Request
 *  0b0..Disable asynchronous DMA request for the channel
 *  0b1..Enable asynchronous DMA request for the channel
 */
#define DMA_AD_CH_CSR_EARQ(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_CSR_EARQ_SHIFT)) & DMA_AD_CH_CSR_EARQ_MASK)

#define DMA_AD_CH_CSR_EEI_MASK                   (0x4U)
#define DMA_AD_CH_CSR_EEI_SHIFT                  (2U)
/*! EEI - Enable Error Interrupt
 *  0b0..Error signal for corresponding channel does not generate error interrupt
 *  0b1..Assertion of error signal for corresponding channel generates error interrupt request
 */
#define DMA_AD_CH_CSR_EEI(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_CSR_EEI_SHIFT)) & DMA_AD_CH_CSR_EEI_MASK)

#define DMA_AD_CH_CSR_EBW_MASK                   (0x8U)
#define DMA_AD_CH_CSR_EBW_SHIFT                  (3U)
/*! EBW - Enable Buffered Writes
 *  0b0..Buffered writes on system bus disabled
 *  0b1..Buffered writes on system bus enabled
 */
#define DMA_AD_CH_CSR_EBW(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_CSR_EBW_SHIFT)) & DMA_AD_CH_CSR_EBW_MASK)

#define DMA_AD_CH_CSR_DONE_MASK                  (0x40000000U)
#define DMA_AD_CH_CSR_DONE_SHIFT                 (30U)
/*! DONE - Channel Done */
#define DMA_AD_CH_CSR_DONE(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_CSR_DONE_SHIFT)) & DMA_AD_CH_CSR_DONE_MASK)

#define DMA_AD_CH_CSR_ACTIVE_MASK                (0x80000000U)
#define DMA_AD_CH_CSR_ACTIVE_SHIFT               (31U)
/*! ACTIVE - Channel Active */
#define DMA_AD_CH_CSR_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_CSR_ACTIVE_SHIFT)) & DMA_AD_CH_CSR_ACTIVE_MASK)
/*! @} */

/* The count of DMA_AD_CH_CSR */
#define DMA_AD_CH_CSR_COUNT                      (32U)

/*! @name CH_ES - Channel Error Status */
/*! @{ */

#define DMA_AD_CH_ES_DBE_MASK                    (0x1U)
#define DMA_AD_CH_ES_DBE_SHIFT                   (0U)
/*! DBE - Destination Bus Error
 *  0b0..No destination bus error
 *  0b1..Last recorded error was bus error on destination write
 */
#define DMA_AD_CH_ES_DBE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_ES_DBE_SHIFT)) & DMA_AD_CH_ES_DBE_MASK)

#define DMA_AD_CH_ES_SBE_MASK                    (0x2U)
#define DMA_AD_CH_ES_SBE_SHIFT                   (1U)
/*! SBE - Source Bus Error
 *  0b0..No source bus error
 *  0b1..Last recorded error was bus error on source read
 */
#define DMA_AD_CH_ES_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_ES_SBE_SHIFT)) & DMA_AD_CH_ES_SBE_MASK)

#define DMA_AD_CH_ES_SGE_MASK                    (0x4U)
#define DMA_AD_CH_ES_SGE_SHIFT                   (2U)
/*! SGE - Scatter/Gather Configuration Error
 *  0b0..No scatter/gather configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
 */
#define DMA_AD_CH_ES_SGE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_ES_SGE_SHIFT)) & DMA_AD_CH_ES_SGE_MASK)

#define DMA_AD_CH_ES_NCE_MASK                    (0x8U)
#define DMA_AD_CH_ES_NCE_SHIFT                   (3U)
/*! NCE - NBYTES/CITER Configuration Error
 *  0b0..No NBYTES/CITER configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields
 */
#define DMA_AD_CH_ES_NCE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_ES_NCE_SHIFT)) & DMA_AD_CH_ES_NCE_MASK)

#define DMA_AD_CH_ES_DOE_MASK                    (0x10U)
#define DMA_AD_CH_ES_DOE_SHIFT                   (4U)
/*! DOE - Destination Offset Error
 *  0b0..No destination offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
 */
#define DMA_AD_CH_ES_DOE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_ES_DOE_SHIFT)) & DMA_AD_CH_ES_DOE_MASK)

#define DMA_AD_CH_ES_DAE_MASK                    (0x20U)
#define DMA_AD_CH_ES_DAE_SHIFT                   (5U)
/*! DAE - Destination Address Error
 *  0b0..No destination address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
 */
#define DMA_AD_CH_ES_DAE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_ES_DAE_SHIFT)) & DMA_AD_CH_ES_DAE_MASK)

#define DMA_AD_CH_ES_SOE_MASK                    (0x40U)
#define DMA_AD_CH_ES_SOE_SHIFT                   (6U)
/*! SOE - Source Offset Error
 *  0b0..No source offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
 */
#define DMA_AD_CH_ES_SOE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_ES_SOE_SHIFT)) & DMA_AD_CH_ES_SOE_MASK)

#define DMA_AD_CH_ES_SAE_MASK                    (0x80U)
#define DMA_AD_CH_ES_SAE_SHIFT                   (7U)
/*! SAE - Source Address Error
 *  0b0..No source address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
 */
#define DMA_AD_CH_ES_SAE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_ES_SAE_SHIFT)) & DMA_AD_CH_ES_SAE_MASK)

#define DMA_AD_CH_ES_ERR_MASK                    (0x80000000U)
#define DMA_AD_CH_ES_ERR_SHIFT                   (31U)
/*! ERR - Error In Channel
 *  0b0..An error in this channel has not occurred
 *  0b1..An error in this channel has occurred
 */
#define DMA_AD_CH_ES_ERR(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_ES_ERR_SHIFT)) & DMA_AD_CH_ES_ERR_MASK)
/*! @} */

/* The count of DMA_AD_CH_ES */
#define DMA_AD_CH_ES_COUNT                       (32U)

/*! @name CH_INT - Channel Interrupt Status */
/*! @{ */

#define DMA_AD_CH_INT_INT_MASK                   (0x1U)
#define DMA_AD_CH_INT_INT_SHIFT                  (0U)
/*! INT - Interrupt Request
 *  0b0..Interrupt request for corresponding channel cleared
 *  0b1..Interrupt request for corresponding channel active
 */
#define DMA_AD_CH_INT_INT(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_INT_INT_SHIFT)) & DMA_AD_CH_INT_INT_MASK)
/*! @} */

/* The count of DMA_AD_CH_INT */
#define DMA_AD_CH_INT_COUNT                      (32U)

/*! @name CH_SBR - Channel System Bus */
/*! @{ */

#define DMA_AD_CH_SBR_MID_MASK                   (0x3FU)
#define DMA_AD_CH_SBR_MID_SHIFT                  (0U)
/*! MID - Master ID */
#define DMA_AD_CH_SBR_MID(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_SBR_MID_SHIFT)) & DMA_AD_CH_SBR_MID_MASK)

#define DMA_AD_CH_SBR_SEC_MASK                   (0x4000U)
#define DMA_AD_CH_SBR_SEC_SHIFT                  (14U)
/*! SEC - Security Level
 *  0b0..Nonsecure protection level for DMA transfers
 *  0b1..Secure protection level for DMA transfers
 */
#define DMA_AD_CH_SBR_SEC(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_SBR_SEC_SHIFT)) & DMA_AD_CH_SBR_SEC_MASK)

#define DMA_AD_CH_SBR_PAL_MASK                   (0x8000U)
#define DMA_AD_CH_SBR_PAL_SHIFT                  (15U)
/*! PAL - Privileged Access Level
 *  0b0..User protection level for DMA transfers
 *  0b1..Privileged protection level for DMA transfers
 */
#define DMA_AD_CH_SBR_PAL(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_SBR_PAL_SHIFT)) & DMA_AD_CH_SBR_PAL_MASK)

#define DMA_AD_CH_SBR_EMI_MASK                   (0x10000U)
#define DMA_AD_CH_SBR_EMI_SHIFT                  (16U)
/*! EMI - Enable Master ID Replication
 *  0b0..Master ID replication is disabled
 *  0b1..Master ID replication is enabled
 */
#define DMA_AD_CH_SBR_EMI(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_SBR_EMI_SHIFT)) & DMA_AD_CH_SBR_EMI_MASK)

#define DMA_AD_CH_SBR_ATTR_MASK                  (0x1E0000U)
#define DMA_AD_CH_SBR_ATTR_SHIFT                 (17U)
/*! ATTR - Attribute Output */
#define DMA_AD_CH_SBR_ATTR(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_SBR_ATTR_SHIFT)) & DMA_AD_CH_SBR_ATTR_MASK)
/*! @} */

/* The count of DMA_AD_CH_SBR */
#define DMA_AD_CH_SBR_COUNT                      (32U)

/*! @name CH_PRI - Channel Priority */
/*! @{ */

#define DMA_AD_CH_PRI_APL_MASK                   (0x7U)
#define DMA_AD_CH_PRI_APL_SHIFT                  (0U)
/*! APL - Arbitration Priority Level */
#define DMA_AD_CH_PRI_APL(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_PRI_APL_SHIFT)) & DMA_AD_CH_PRI_APL_MASK)

#define DMA_AD_CH_PRI_DPA_MASK                   (0x40000000U)
#define DMA_AD_CH_PRI_DPA_SHIFT                  (30U)
/*! DPA - Disable Preempt Ability
 *  0b0..Channel can suspend a lower-priority channel
 *  0b1..Channel cannot suspend any other channel, regardless of channel priority
 */
#define DMA_AD_CH_PRI_DPA(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_PRI_DPA_SHIFT)) & DMA_AD_CH_PRI_DPA_MASK)

#define DMA_AD_CH_PRI_ECP_MASK                   (0x80000000U)
#define DMA_AD_CH_PRI_ECP_SHIFT                  (31U)
/*! ECP - Enable Channel Preemption
 *  0b0..Channel cannot be suspended by a higher-priority channel's service request
 *  0b1..Channel can be temporarily suspended by a higher-priority channel's service request
 */
#define DMA_AD_CH_PRI_ECP(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_PRI_ECP_SHIFT)) & DMA_AD_CH_PRI_ECP_MASK)
/*! @} */

/* The count of DMA_AD_CH_PRI */
#define DMA_AD_CH_PRI_COUNT                      (32U)

/*! @name CH_MUX - Channel Multiplexor Configuration */
/*! @{ */

#define DMA_AD_CH_MUX_SRC_MASK                   (0x7FU)
#define DMA_AD_CH_MUX_SRC_SHIFT                  (0U)
/*! SRC - Service Request Source */
#define DMA_AD_CH_MUX_SRC(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_AD_CH_MUX_SRC_SHIFT)) & DMA_AD_CH_MUX_SRC_MASK)
/*! @} */

/* The count of DMA_AD_CH_MUX */
#define DMA_AD_CH_MUX_COUNT                      (32U)

/*! @name TCD_SADDR - TCD Source Address */
/*! @{ */

#define DMA_AD_TCD_SADDR_SADDR_MASK              (0xFFFFFFFFU)
#define DMA_AD_TCD_SADDR_SADDR_SHIFT             (0U)
/*! SADDR - Source Address */
#define DMA_AD_TCD_SADDR_SADDR(x)                (((uint32_t)(((uint32_t)(x)) << DMA_AD_TCD_SADDR_SADDR_SHIFT)) & DMA_AD_TCD_SADDR_SADDR_MASK)
/*! @} */

/* The count of DMA_AD_TCD_SADDR */
#define DMA_AD_TCD_SADDR_COUNT                   (32U)

/*! @name TCD_SOFF - TCD Signed Source Address Offset */
/*! @{ */

#define DMA_AD_TCD_SOFF_SOFF_MASK                (0xFFFFU)
#define DMA_AD_TCD_SOFF_SOFF_SHIFT               (0U)
/*! SOFF - Source Address Signed Offset */
#define DMA_AD_TCD_SOFF_SOFF(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_SOFF_SOFF_SHIFT)) & DMA_AD_TCD_SOFF_SOFF_MASK)
/*! @} */

/* The count of DMA_AD_TCD_SOFF */
#define DMA_AD_TCD_SOFF_COUNT                    (32U)

/*! @name TCD_ATTR - TCD Transfer Attributes */
/*! @{ */

#define DMA_AD_TCD_ATTR_DSIZE_MASK               (0x7U)
#define DMA_AD_TCD_ATTR_DSIZE_SHIFT              (0U)
/*! DSIZE - Destination Data Transfer Size */
#define DMA_AD_TCD_ATTR_DSIZE(x)                 (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_ATTR_DSIZE_SHIFT)) & DMA_AD_TCD_ATTR_DSIZE_MASK)

#define DMA_AD_TCD_ATTR_DMOD_MASK                (0xF8U)
#define DMA_AD_TCD_ATTR_DMOD_SHIFT               (3U)
/*! DMOD - Destination Address Modulo */
#define DMA_AD_TCD_ATTR_DMOD(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_ATTR_DMOD_SHIFT)) & DMA_AD_TCD_ATTR_DMOD_MASK)

#define DMA_AD_TCD_ATTR_SSIZE_MASK               (0x700U)
#define DMA_AD_TCD_ATTR_SSIZE_SHIFT              (8U)
/*! SSIZE - Source Data Transfer Size
 *  0b000..8-bit
 *  0b001..16-bit
 *  0b010..32-bit
 *  0b011..64-bit
 *  0b100..16-byte
 *  0b101..32-byte
 *  0b110..64-byte
 *  0b111..
 */
#define DMA_AD_TCD_ATTR_SSIZE(x)                 (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_ATTR_SSIZE_SHIFT)) & DMA_AD_TCD_ATTR_SSIZE_MASK)

#define DMA_AD_TCD_ATTR_SMOD_MASK                (0xF800U)
#define DMA_AD_TCD_ATTR_SMOD_SHIFT               (11U)
/*! SMOD - Source Address Modulo
 *  0b00000..Source address modulo feature disabled
 *  0b00001..Source address modulo feature enabled for any non-zero value [1-31]
 */
#define DMA_AD_TCD_ATTR_SMOD(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_ATTR_SMOD_SHIFT)) & DMA_AD_TCD_ATTR_SMOD_MASK)
/*! @} */

/* The count of DMA_AD_TCD_ATTR */
#define DMA_AD_TCD_ATTR_COUNT                    (32U)

/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */
/*! @{ */

#define DMA_AD_TCD_NBYTES_MLOFFNO_NBYTES_MASK    (0x3FFFFFFFU)
#define DMA_AD_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT   (0U)
/*! NBYTES - Number of Bytes To Transfer Per Service Request */
#define DMA_AD_TCD_NBYTES_MLOFFNO_NBYTES(x)      (((uint32_t)(((uint32_t)(x)) << DMA_AD_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_AD_TCD_NBYTES_MLOFFNO_NBYTES_MASK)

#define DMA_AD_TCD_NBYTES_MLOFFNO_DMLOE_MASK     (0x40000000U)
#define DMA_AD_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT    (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to DADDR
 *  0b1..Minor loop offset applied to DADDR
 */
#define DMA_AD_TCD_NBYTES_MLOFFNO_DMLOE(x)       (((uint32_t)(((uint32_t)(x)) << DMA_AD_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_AD_TCD_NBYTES_MLOFFNO_DMLOE_MASK)

#define DMA_AD_TCD_NBYTES_MLOFFNO_SMLOE_MASK     (0x80000000U)
#define DMA_AD_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT    (31U)
/*! SMLOE - Source Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to SADDR
 *  0b1..Minor loop offset applied to SADDR
 */
#define DMA_AD_TCD_NBYTES_MLOFFNO_SMLOE(x)       (((uint32_t)(((uint32_t)(x)) << DMA_AD_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_AD_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
/*! @} */

/* The count of DMA_AD_TCD_NBYTES_MLOFFNO */
#define DMA_AD_TCD_NBYTES_MLOFFNO_COUNT          (32U)

/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */
/*! @{ */

#define DMA_AD_TCD_NBYTES_MLOFFYES_NBYTES_MASK   (0x3FFU)
#define DMA_AD_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT  (0U)
/*! NBYTES - Number of Bytes To Transfer Per Service Request */
#define DMA_AD_TCD_NBYTES_MLOFFYES_NBYTES(x)     (((uint32_t)(((uint32_t)(x)) << DMA_AD_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_AD_TCD_NBYTES_MLOFFYES_NBYTES_MASK)

#define DMA_AD_TCD_NBYTES_MLOFFYES_MLOFF_MASK    (0x3FFFFC00U)
#define DMA_AD_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT   (10U)
/*! MLOFF - Minor Loop Offset */
#define DMA_AD_TCD_NBYTES_MLOFFYES_MLOFF(x)      (((uint32_t)(((uint32_t)(x)) << DMA_AD_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_AD_TCD_NBYTES_MLOFFYES_MLOFF_MASK)

#define DMA_AD_TCD_NBYTES_MLOFFYES_DMLOE_MASK    (0x40000000U)
#define DMA_AD_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT   (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to DADDR
 *  0b1..Minor loop offset applied to DADDR
 */
#define DMA_AD_TCD_NBYTES_MLOFFYES_DMLOE(x)      (((uint32_t)(((uint32_t)(x)) << DMA_AD_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_AD_TCD_NBYTES_MLOFFYES_DMLOE_MASK)

#define DMA_AD_TCD_NBYTES_MLOFFYES_SMLOE_MASK    (0x80000000U)
#define DMA_AD_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT   (31U)
/*! SMLOE - Source Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to SADDR
 *  0b1..Minor loop offset applied to SADDR
 */
#define DMA_AD_TCD_NBYTES_MLOFFYES_SMLOE(x)      (((uint32_t)(((uint32_t)(x)) << DMA_AD_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_AD_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
/*! @} */

/* The count of DMA_AD_TCD_NBYTES_MLOFFYES */
#define DMA_AD_TCD_NBYTES_MLOFFYES_COUNT         (32U)

/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */
/*! @{ */

#define DMA_AD_TCD_SLAST_SDA_SLAST_SDA_MASK      (0xFFFFFFFFU)
#define DMA_AD_TCD_SLAST_SDA_SLAST_SDA_SHIFT     (0U)
/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */
#define DMA_AD_TCD_SLAST_SDA_SLAST_SDA(x)        (((uint32_t)(((uint32_t)(x)) << DMA_AD_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_AD_TCD_SLAST_SDA_SLAST_SDA_MASK)
/*! @} */

/* The count of DMA_AD_TCD_SLAST_SDA */
#define DMA_AD_TCD_SLAST_SDA_COUNT               (32U)

/*! @name TCD_DADDR - TCD Destination Address */
/*! @{ */

#define DMA_AD_TCD_DADDR_DADDR_MASK              (0xFFFFFFFFU)
#define DMA_AD_TCD_DADDR_DADDR_SHIFT             (0U)
/*! DADDR - Destination Address */
#define DMA_AD_TCD_DADDR_DADDR(x)                (((uint32_t)(((uint32_t)(x)) << DMA_AD_TCD_DADDR_DADDR_SHIFT)) & DMA_AD_TCD_DADDR_DADDR_MASK)
/*! @} */

/* The count of DMA_AD_TCD_DADDR */
#define DMA_AD_TCD_DADDR_COUNT                   (32U)

/*! @name TCD_DOFF - TCD Signed Destination Address Offset */
/*! @{ */

#define DMA_AD_TCD_DOFF_DOFF_MASK                (0xFFFFU)
#define DMA_AD_TCD_DOFF_DOFF_SHIFT               (0U)
/*! DOFF - Destination Address Signed Offset */
#define DMA_AD_TCD_DOFF_DOFF(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_DOFF_DOFF_SHIFT)) & DMA_AD_TCD_DOFF_DOFF_MASK)
/*! @} */

/* The count of DMA_AD_TCD_DOFF */
#define DMA_AD_TCD_DOFF_COUNT                    (32U)

/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */
/*! @{ */

#define DMA_AD_TCD_CITER_ELINKNO_CITER_MASK      (0x7FFFU)
#define DMA_AD_TCD_CITER_ELINKNO_CITER_SHIFT     (0U)
/*! CITER - Current Major Iteration Count */
#define DMA_AD_TCD_CITER_ELINKNO_CITER(x)        (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_AD_TCD_CITER_ELINKNO_CITER_MASK)

#define DMA_AD_TCD_CITER_ELINKNO_ELINK_MASK      (0x8000U)
#define DMA_AD_TCD_CITER_ELINKNO_ELINK_SHIFT     (15U)
/*! ELINK - Enable Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_AD_TCD_CITER_ELINKNO_ELINK(x)        (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_AD_TCD_CITER_ELINKNO_ELINK_MASK)
/*! @} */

/* The count of DMA_AD_TCD_CITER_ELINKNO */
#define DMA_AD_TCD_CITER_ELINKNO_COUNT           (32U)

/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */
/*! @{ */

#define DMA_AD_TCD_CITER_ELINKYES_CITER_MASK     (0x1FFU)
#define DMA_AD_TCD_CITER_ELINKYES_CITER_SHIFT    (0U)
/*! CITER - Current Major Iteration Count */
#define DMA_AD_TCD_CITER_ELINKYES_CITER(x)       (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_AD_TCD_CITER_ELINKYES_CITER_MASK)

#define DMA_AD_TCD_CITER_ELINKYES_LINKCH_MASK    (0x3E00U)
#define DMA_AD_TCD_CITER_ELINKYES_LINKCH_SHIFT   (9U)
/*! LINKCH - Minor Loop Link Channel Number */
#define DMA_AD_TCD_CITER_ELINKYES_LINKCH(x)      (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_AD_TCD_CITER_ELINKYES_LINKCH_MASK)

#define DMA_AD_TCD_CITER_ELINKYES_ELINK_MASK     (0x8000U)
#define DMA_AD_TCD_CITER_ELINKYES_ELINK_SHIFT    (15U)
/*! ELINK - Enable Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_AD_TCD_CITER_ELINKYES_ELINK(x)       (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_AD_TCD_CITER_ELINKYES_ELINK_MASK)
/*! @} */

/* The count of DMA_AD_TCD_CITER_ELINKYES */
#define DMA_AD_TCD_CITER_ELINKYES_COUNT          (32U)

/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */
/*! @{ */

#define DMA_AD_TCD_DLAST_SGA_DLAST_SGA_MASK      (0xFFFFFFFFU)
#define DMA_AD_TCD_DLAST_SGA_DLAST_SGA_SHIFT     (0U)
/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */
#define DMA_AD_TCD_DLAST_SGA_DLAST_SGA(x)        (((uint32_t)(((uint32_t)(x)) << DMA_AD_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_AD_TCD_DLAST_SGA_DLAST_SGA_MASK)
/*! @} */

/* The count of DMA_AD_TCD_DLAST_SGA */
#define DMA_AD_TCD_DLAST_SGA_COUNT               (32U)

/*! @name TCD_CSR - TCD Control and Status */
/*! @{ */

#define DMA_AD_TCD_CSR_START_MASK                (0x1U)
#define DMA_AD_TCD_CSR_START_SHIFT               (0U)
/*! START - Channel Start
 *  0b0..Channel not explicitly started
 *  0b1..Channel explicitly started via a software-initiated service request
 */
#define DMA_AD_TCD_CSR_START(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CSR_START_SHIFT)) & DMA_AD_TCD_CSR_START_MASK)

#define DMA_AD_TCD_CSR_INTMAJOR_MASK             (0x2U)
#define DMA_AD_TCD_CSR_INTMAJOR_SHIFT            (1U)
/*! INTMAJOR - Enable Interrupt If Major count complete
 *  0b0..End-of-major loop interrupt disabled
 *  0b1..End-of-major loop interrupt enabled
 */
#define DMA_AD_TCD_CSR_INTMAJOR(x)               (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CSR_INTMAJOR_SHIFT)) & DMA_AD_TCD_CSR_INTMAJOR_MASK)

#define DMA_AD_TCD_CSR_INTHALF_MASK              (0x4U)
#define DMA_AD_TCD_CSR_INTHALF_SHIFT             (2U)
/*! INTHALF - Enable Interrupt If Major Counter Half-complete
 *  0b0..Halfway point interrupt disabled
 *  0b1..Halfway point interrupt enabled
 */
#define DMA_AD_TCD_CSR_INTHALF(x)                (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CSR_INTHALF_SHIFT)) & DMA_AD_TCD_CSR_INTHALF_MASK)

#define DMA_AD_TCD_CSR_DREQ_MASK                 (0x8U)
#define DMA_AD_TCD_CSR_DREQ_SHIFT                (3U)
/*! DREQ - Disable Request
 *  0b0..No operation
 *  0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests
 */
#define DMA_AD_TCD_CSR_DREQ(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CSR_DREQ_SHIFT)) & DMA_AD_TCD_CSR_DREQ_MASK)

#define DMA_AD_TCD_CSR_ESG_MASK                  (0x10U)
#define DMA_AD_TCD_CSR_ESG_SHIFT                 (4U)
/*! ESG - Enable Scatter/Gather Processing
 *  0b0..Current channel's TCD is normal format
 *  0b1..Current channel's TCD specifies scatter/gather format.
 */
#define DMA_AD_TCD_CSR_ESG(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CSR_ESG_SHIFT)) & DMA_AD_TCD_CSR_ESG_MASK)

#define DMA_AD_TCD_CSR_MAJORELINK_MASK           (0x20U)
#define DMA_AD_TCD_CSR_MAJORELINK_SHIFT          (5U)
/*! MAJORELINK - Enable Link When Major Loop Complete
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_AD_TCD_CSR_MAJORELINK(x)             (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CSR_MAJORELINK_SHIFT)) & DMA_AD_TCD_CSR_MAJORELINK_MASK)

#define DMA_AD_TCD_CSR_EEOP_MASK                 (0x40U)
#define DMA_AD_TCD_CSR_EEOP_SHIFT                (6U)
/*! EEOP - Enable End-Of-Packet Processing
 *  0b0..End-of-packet operation disabled
 *  0b1..End-of-packet hardware input signal enabled
 */
#define DMA_AD_TCD_CSR_EEOP(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CSR_EEOP_SHIFT)) & DMA_AD_TCD_CSR_EEOP_MASK)

#define DMA_AD_TCD_CSR_ESDA_MASK                 (0x80U)
#define DMA_AD_TCD_CSR_ESDA_SHIFT                (7U)
/*! ESDA - Enable Store Destination Address
 *  0b0..Ability to store destination address to system memory disabled
 *  0b1..Ability to store destination address to system memory enabled
 */
#define DMA_AD_TCD_CSR_ESDA(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CSR_ESDA_SHIFT)) & DMA_AD_TCD_CSR_ESDA_MASK)

#define DMA_AD_TCD_CSR_MAJORLINKCH_MASK          (0x1F00U)
#define DMA_AD_TCD_CSR_MAJORLINKCH_SHIFT         (8U)
/*! MAJORLINKCH - Major Loop Link Channel Number */
#define DMA_AD_TCD_CSR_MAJORLINKCH(x)            (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_AD_TCD_CSR_MAJORLINKCH_MASK)

#define DMA_AD_TCD_CSR_BWC_MASK                  (0xC000U)
#define DMA_AD_TCD_CSR_BWC_SHIFT                 (14U)
/*! BWC - Bandwidth Control
 *  0b00..No eDMA engine stalls
 *  0b01..Enable eDMA master high-priority elevation (HPE) mode. No eDMA engine stalls.
 *  0b10..eDMA engine stalls for 4 cycles after each R/W
 *  0b11..eDMA engine stalls for 8 cycles after each R/W
 */
#define DMA_AD_TCD_CSR_BWC(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_CSR_BWC_SHIFT)) & DMA_AD_TCD_CSR_BWC_MASK)
/*! @} */

/* The count of DMA_AD_TCD_CSR */
#define DMA_AD_TCD_CSR_COUNT                     (32U)

/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */
/*! @{ */

#define DMA_AD_TCD_BITER_ELINKNO_BITER_MASK      (0x7FFFU)
#define DMA_AD_TCD_BITER_ELINKNO_BITER_SHIFT     (0U)
/*! BITER - Starting Major Iteration Count */
#define DMA_AD_TCD_BITER_ELINKNO_BITER(x)        (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_AD_TCD_BITER_ELINKNO_BITER_MASK)

#define DMA_AD_TCD_BITER_ELINKNO_ELINK_MASK      (0x8000U)
#define DMA_AD_TCD_BITER_ELINKNO_ELINK_SHIFT     (15U)
/*! ELINK - Enables Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_AD_TCD_BITER_ELINKNO_ELINK(x)        (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_AD_TCD_BITER_ELINKNO_ELINK_MASK)
/*! @} */

/* The count of DMA_AD_TCD_BITER_ELINKNO */
#define DMA_AD_TCD_BITER_ELINKNO_COUNT           (32U)

/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */
/*! @{ */

#define DMA_AD_TCD_BITER_ELINKYES_BITER_MASK     (0x1FFU)
#define DMA_AD_TCD_BITER_ELINKYES_BITER_SHIFT    (0U)
/*! BITER - Starting Major Iteration Count */
#define DMA_AD_TCD_BITER_ELINKYES_BITER(x)       (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_AD_TCD_BITER_ELINKYES_BITER_MASK)

#define DMA_AD_TCD_BITER_ELINKYES_LINKCH_MASK    (0x3E00U)
#define DMA_AD_TCD_BITER_ELINKYES_LINKCH_SHIFT   (9U)
/*! LINKCH - Link Channel Number */
#define DMA_AD_TCD_BITER_ELINKYES_LINKCH(x)      (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_AD_TCD_BITER_ELINKYES_LINKCH_MASK)

#define DMA_AD_TCD_BITER_ELINKYES_ELINK_MASK     (0x8000U)
#define DMA_AD_TCD_BITER_ELINKYES_ELINK_SHIFT    (15U)
/*! ELINK - Enable Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_AD_TCD_BITER_ELINKYES_ELINK(x)       (((uint16_t)(((uint16_t)(x)) << DMA_AD_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_AD_TCD_BITER_ELINKYES_ELINK_MASK)
/*! @} */

/* The count of DMA_AD_TCD_BITER_ELINKYES */
#define DMA_AD_TCD_BITER_ELINKYES_COUNT          (32U)


/*!
 * @}
 */ /* end of group DMA_AD_Register_Masks */


/* DMA_AD - Peripheral instance base addresses */
/** Peripheral DMA1 base address */
#define DMA1_BASE                                (0x29010000u)
/** Peripheral DMA1 base pointer */
#define DMA1                                     ((DMA_AD_Type *)DMA1_BASE)
/** Peripheral DMA2 base address */
#define DMA2_BASE                                (0x2D800000u)
/** Peripheral DMA2 base pointer */
#define DMA2                                     ((DMA_AD_Type *)DMA2_BASE)
/** Array initializer of DMA_AD peripheral base addresses */
#define DMA_AD_BASE_ADDRS                        { DMA1_BASE, DMA2_BASE }
/** Array initializer of DMA_AD peripheral base pointers */
#define DMA_AD_BASE_PTRS                         { DMA1, DMA2 }
/** Interrupt vectors for the DMA_AD peripheral type */
#define DMA_AD_IRQS                              { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { DMA2_0_IRQn, DMA2_1_IRQn, DMA2_2_IRQn, DMA2_3_IRQn, DMA2_4_IRQn, DMA2_5_IRQn, DMA2_6_IRQn, DMA2_7_IRQn } }
#define DMA_AD_ERROR_IRQS                        { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { DMA2_0_IRQn, DMA2_1_IRQn, DMA2_2_IRQn, DMA2_3_IRQn, DMA2_4_IRQn, DMA2_5_IRQn, DMA2_6_IRQn, DMA2_7_IRQn } }

/*!
 * @}
 */ /* end of group DMA_AD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ENET Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
 * @{
 */

/** ENET - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[4];
  __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
  __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
       uint8_t RESERVED_1[4];
  __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
  __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
       uint8_t RESERVED_2[12];
  __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
       uint8_t RESERVED_3[24];
  __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
  __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
       uint8_t RESERVED_4[28];
  __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
       uint8_t RESERVED_5[28];
  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
       uint8_t RESERVED_6[60];
  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
       uint8_t RESERVED_7[28];
  __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
  __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
  __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
  __IO uint32_t TXIC[1];                           /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
       uint8_t RESERVED_8[12];
  __IO uint32_t RXIC[1];                           /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_9[20];
  __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
  __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
  __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
  __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
       uint8_t RESERVED_10[28];
  __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
       uint8_t RESERVED_11[56];
  __IO uint32_t RDSR;                              /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
  __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
  __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
       uint8_t RESERVED_12[4];
  __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
  __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
  __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
  __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
  __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
  __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
  __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
  __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
  __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
       uint8_t RESERVED_13[12];
  __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
  __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
       uint8_t RESERVED_14[60];
  __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
  __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
  __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
  __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
  __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
  __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
  __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
  __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
  __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
  __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
  __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
  __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
  __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
  __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
  __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
  __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
  __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
       uint8_t RESERVED_15[4];
  __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
  __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
  __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
  __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
  __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
  __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
  __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
  __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
  __I  uint32_t IEEE_T_SQE;                        /**< Reserved Statistic Register, offset: 0x26C */
  __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
  __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
       uint8_t RESERVED_16[12];
  __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
  __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
  __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
  __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
  __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
  __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
  __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
  __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
       uint8_t RESERVED_17[4];
  __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
  __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
  __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
  __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
  __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
  __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
  __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
  __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
  __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
  __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
  __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
  __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
  __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
  __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
  __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
       uint8_t RESERVED_18[284];
  __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
  __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
  __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
  __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
  __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
  __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
  __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
       uint8_t RESERVED_19[488];
  __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
  struct {                                         /* offset: 0x608, array step: 0x8 */
    __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
    __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
  } CHANNEL[4];
} ENET_Type;

/* ----------------------------------------------------------------------------
   -- ENET Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ENET_Register_Masks ENET Register Masks
 * @{
 */

/*! @name EIR - Interrupt Event Register */
/*! @{ */

#define ENET_EIR_TS_TIMER_MASK                   (0x8000U)
#define ENET_EIR_TS_TIMER_SHIFT                  (15U)
/*! TS_TIMER - Timestamp Timer */
#define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)

#define ENET_EIR_TS_AVAIL_MASK                   (0x10000U)
#define ENET_EIR_TS_AVAIL_SHIFT                  (16U)
/*! TS_AVAIL - Transmit Timestamp Available */
#define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)

#define ENET_EIR_WAKEUP_MASK                     (0x20000U)
#define ENET_EIR_WAKEUP_SHIFT                    (17U)
/*! WAKEUP - Node Wakeup Request Indication */
#define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)

#define ENET_EIR_PLR_MASK                        (0x40000U)
#define ENET_EIR_PLR_SHIFT                       (18U)
/*! PLR - Payload Receive Error */
#define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)

#define ENET_EIR_UN_MASK                         (0x80000U)
#define ENET_EIR_UN_SHIFT                        (19U)
/*! UN - Transmit FIFO Underrun */
#define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)

#define ENET_EIR_RL_MASK                         (0x100000U)
#define ENET_EIR_RL_SHIFT                        (20U)
/*! RL - Collision Retry Limit */
#define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)

#define ENET_EIR_LC_MASK                         (0x200000U)
#define ENET_EIR_LC_SHIFT                        (21U)
/*! LC - Late Collision */
#define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)

#define ENET_EIR_EBERR_MASK                      (0x400000U)
#define ENET_EIR_EBERR_SHIFT                     (22U)
/*! EBERR - Ethernet Bus Error */
#define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)

#define ENET_EIR_MII_MASK                        (0x800000U)
#define ENET_EIR_MII_SHIFT                       (23U)
/*! MII - MII Interrupt. */
#define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)

#define ENET_EIR_RXB_MASK                        (0x1000000U)
#define ENET_EIR_RXB_SHIFT                       (24U)
/*! RXB - Receive Buffer Interrupt */
#define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)

#define ENET_EIR_RXF_MASK                        (0x2000000U)
#define ENET_EIR_RXF_SHIFT                       (25U)
/*! RXF - Receive Frame Interrupt */
#define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)

#define ENET_EIR_TXB_MASK                        (0x4000000U)
#define ENET_EIR_TXB_SHIFT                       (26U)
/*! TXB - Transmit Buffer Interrupt */
#define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)

#define ENET_EIR_TXF_MASK                        (0x8000000U)
#define ENET_EIR_TXF_SHIFT                       (27U)
/*! TXF - Transmit Frame Interrupt */
#define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)

#define ENET_EIR_GRA_MASK                        (0x10000000U)
#define ENET_EIR_GRA_SHIFT                       (28U)
/*! GRA - Graceful Stop Complete */
#define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)

#define ENET_EIR_BABT_MASK                       (0x20000000U)
#define ENET_EIR_BABT_SHIFT                      (29U)
/*! BABT - Babbling Transmit Error */
#define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)

#define ENET_EIR_BABR_MASK                       (0x40000000U)
#define ENET_EIR_BABR_SHIFT                      (30U)
/*! BABR - Babbling Receive Error */
#define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
/*! @} */

/*! @name EIMR - Interrupt Mask Register */
/*! @{ */

#define ENET_EIMR_TS_TIMER_MASK                  (0x8000U)
#define ENET_EIMR_TS_TIMER_SHIFT                 (15U)
/*! TS_TIMER - TS_TIMER Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)

#define ENET_EIMR_TS_AVAIL_MASK                  (0x10000U)
#define ENET_EIMR_TS_AVAIL_SHIFT                 (16U)
/*! TS_AVAIL - TS_AVAIL Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)

#define ENET_EIMR_WAKEUP_MASK                    (0x20000U)
#define ENET_EIMR_WAKEUP_SHIFT                   (17U)
/*! WAKEUP - WAKEUP Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)

#define ENET_EIMR_PLR_MASK                       (0x40000U)
#define ENET_EIMR_PLR_SHIFT                      (18U)
/*! PLR - PLR Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)

#define ENET_EIMR_UN_MASK                        (0x80000U)
#define ENET_EIMR_UN_SHIFT                       (19U)
/*! UN - UN Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)

#define ENET_EIMR_RL_MASK                        (0x100000U)
#define ENET_EIMR_RL_SHIFT                       (20U)
/*! RL - RL Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)

#define ENET_EIMR_LC_MASK                        (0x200000U)
#define ENET_EIMR_LC_SHIFT                       (21U)
/*! LC - LC Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)

#define ENET_EIMR_EBERR_MASK                     (0x400000U)
#define ENET_EIMR_EBERR_SHIFT                    (22U)
/*! EBERR - EBERR Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)

#define ENET_EIMR_MII_MASK                       (0x800000U)
#define ENET_EIMR_MII_SHIFT                      (23U)
/*! MII - MII Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)

#define ENET_EIMR_RXB_MASK                       (0x1000000U)
#define ENET_EIMR_RXB_SHIFT                      (24U)
/*! RXB - RXB Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)

#define ENET_EIMR_RXF_MASK                       (0x2000000U)
#define ENET_EIMR_RXF_SHIFT                      (25U)
/*! RXF - RXF Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)

#define ENET_EIMR_TXB_MASK                       (0x4000000U)
#define ENET_EIMR_TXB_SHIFT                      (26U)
/*! TXB - TXB Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)

#define ENET_EIMR_TXF_MASK                       (0x8000000U)
#define ENET_EIMR_TXF_SHIFT                      (27U)
/*! TXF - TXF Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)

#define ENET_EIMR_GRA_MASK                       (0x10000000U)
#define ENET_EIMR_GRA_SHIFT                      (28U)
/*! GRA - GRA Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)

#define ENET_EIMR_BABT_MASK                      (0x20000000U)
#define ENET_EIMR_BABT_SHIFT                     (29U)
/*! BABT - BABT Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)

#define ENET_EIMR_BABR_MASK                      (0x40000000U)
#define ENET_EIMR_BABR_SHIFT                     (30U)
/*! BABR - BABR Interrupt Mask
 *  0b0..The corresponding interrupt source is masked.
 *  0b1..The corresponding interrupt source is not masked.
 */
#define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
/*! @} */

/*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
/*! @{ */

#define ENET_RDAR_RDAR_MASK                      (0x1000000U)
#define ENET_RDAR_RDAR_SHIFT                     (24U)
/*! RDAR - Receive Descriptor Active */
#define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
/*! @} */

/*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
/*! @{ */

#define ENET_TDAR_TDAR_MASK                      (0x1000000U)
#define ENET_TDAR_TDAR_SHIFT                     (24U)
/*! TDAR - Transmit Descriptor Active */
#define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
/*! @} */

/*! @name ECR - Ethernet Control Register */
/*! @{ */

#define ENET_ECR_RESET_MASK                      (0x1U)
#define ENET_ECR_RESET_SHIFT                     (0U)
/*! RESET - Ethernet MAC Reset */
#define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)

#define ENET_ECR_ETHEREN_MASK                    (0x2U)
#define ENET_ECR_ETHEREN_SHIFT                   (1U)
/*! ETHEREN - Ethernet Enable
 *  0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
 *  0b1..MAC is enabled, and reception and transmission are possible.
 */
#define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)

#define ENET_ECR_MAGICEN_MASK                    (0x4U)
#define ENET_ECR_MAGICEN_SHIFT                   (2U)
/*! MAGICEN - Magic Packet Detection Enable
 *  0b0..Magic detection logic disabled.
 *  0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
 */
#define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)

#define ENET_ECR_SLEEP_MASK                      (0x8U)
#define ENET_ECR_SLEEP_SHIFT                     (3U)
/*! SLEEP - Sleep Mode Enable
 *  0b0..Normal operating mode.
 *  0b1..Sleep mode.
 */
#define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)

#define ENET_ECR_EN1588_MASK                     (0x10U)
#define ENET_ECR_EN1588_SHIFT                    (4U)
/*! EN1588 - EN1588 Enable
 *  0b0..Legacy FEC buffer descriptors and functions enabled.
 *  0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588.
 */
#define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)

#define ENET_ECR_DBGEN_MASK                      (0x40U)
#define ENET_ECR_DBGEN_SHIFT                     (6U)
/*! DBGEN - Debug Enable
 *  0b0..MAC continues operation in debug mode.
 *  0b1..MAC enters hardware freeze mode when the processor is in debug mode.
 */
#define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)

#define ENET_ECR_STOPEN_MASK                     (0x80U)
#define ENET_ECR_STOPEN_SHIFT                    (7U)
/*! STOPEN - STOPEN Signal Control */
#define ENET_ECR_STOPEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)

#define ENET_ECR_DBSWP_MASK                      (0x100U)
#define ENET_ECR_DBSWP_SHIFT                     (8U)
/*! DBSWP - Descriptor Byte Swapping Enable
 *  0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
 *  0b1..The buffer descriptor bytes are swapped to support little-endian devices.
 */
#define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
/*! @} */

/*! @name MMFR - MII Management Frame Register */
/*! @{ */

#define ENET_MMFR_DATA_MASK                      (0xFFFFU)
#define ENET_MMFR_DATA_SHIFT                     (0U)
/*! DATA - Management Frame Data */
#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)

#define ENET_MMFR_TA_MASK                        (0x30000U)
#define ENET_MMFR_TA_SHIFT                       (16U)
/*! TA - Turn Around */
#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)

#define ENET_MMFR_RA_MASK                        (0x7C0000U)
#define ENET_MMFR_RA_SHIFT                       (18U)
/*! RA - Register Address */
#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)

#define ENET_MMFR_PA_MASK                        (0xF800000U)
#define ENET_MMFR_PA_SHIFT                       (23U)
/*! PA - PHY Address */
#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)

#define ENET_MMFR_OP_MASK                        (0x30000000U)
#define ENET_MMFR_OP_SHIFT                       (28U)
/*! OP - Operation Code */
#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)

#define ENET_MMFR_ST_MASK                        (0xC0000000U)
#define ENET_MMFR_ST_SHIFT                       (30U)
/*! ST - Start Of Frame Delimiter */
#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
/*! @} */

/*! @name MSCR - MII Speed Control Register */
/*! @{ */

#define ENET_MSCR_MII_SPEED_MASK                 (0x7EU)
#define ENET_MSCR_MII_SPEED_SHIFT                (1U)
/*! MII_SPEED - MII Speed */
#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)

#define ENET_MSCR_DIS_PRE_MASK                   (0x80U)
#define ENET_MSCR_DIS_PRE_SHIFT                  (7U)
/*! DIS_PRE - Disable Preamble
 *  0b0..Preamble enabled.
 *  0b1..Preamble (32 ones) is not prepended to the MII management frame.
 */
#define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)

#define ENET_MSCR_HOLDTIME_MASK                  (0x700U)
#define ENET_MSCR_HOLDTIME_SHIFT                 (8U)
/*! HOLDTIME - Hold time On MDIO Output
 *  0b000..1 internal module clock cycle
 *  0b001..2 internal module clock cycles
 *  0b010..3 internal module clock cycles
 *  0b111..8 internal module clock cycles
 */
#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
/*! @} */

/*! @name MIBC - MIB Control Register */
/*! @{ */

#define ENET_MIBC_MIB_CLEAR_MASK                 (0x20000000U)
#define ENET_MIBC_MIB_CLEAR_SHIFT                (29U)
/*! MIB_CLEAR - MIB Clear
 *  0b0..See note above.
 *  0b1..All statistics counters are reset to 0.
 */
#define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)

#define ENET_MIBC_MIB_IDLE_MASK                  (0x40000000U)
#define ENET_MIBC_MIB_IDLE_SHIFT                 (30U)
/*! MIB_IDLE - MIB Idle
 *  0b0..The MIB block is updating MIB counters.
 *  0b1..The MIB block is not currently updating any MIB counters.
 */
#define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)

#define ENET_MIBC_MIB_DIS_MASK                   (0x80000000U)
#define ENET_MIBC_MIB_DIS_SHIFT                  (31U)
/*! MIB_DIS - Disable MIB Logic
 *  0b0..MIB logic is enabled.
 *  0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
 */
#define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
/*! @} */

/*! @name RCR - Receive Control Register */
/*! @{ */

#define ENET_RCR_LOOP_MASK                       (0x1U)
#define ENET_RCR_LOOP_SHIFT                      (0U)
/*! LOOP - Internal Loopback
 *  0b0..Loopback disabled.
 *  0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
 */
#define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)

#define ENET_RCR_DRT_MASK                        (0x2U)
#define ENET_RCR_DRT_SHIFT                       (1U)
/*! DRT - Disable Receive On Transmit
 *  0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
 *  0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
 */
#define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)

#define ENET_RCR_MII_MODE_MASK                   (0x4U)
#define ENET_RCR_MII_MODE_SHIFT                  (2U)
/*! MII_MODE - Media Independent Interface Mode
 *  0b0..Reserved.
 *  0b1..MII or RMII mode, as indicated by the RMII_MODE field.
 */
#define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)

#define ENET_RCR_PROM_MASK                       (0x8U)
#define ENET_RCR_PROM_SHIFT                      (3U)
/*! PROM - Promiscuous Mode
 *  0b0..Disabled.
 *  0b1..Enabled.
 */
#define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)

#define ENET_RCR_BC_REJ_MASK                     (0x10U)
#define ENET_RCR_BC_REJ_SHIFT                    (4U)
/*! BC_REJ - Broadcast Frame Reject
 *  0b0..Will not reject frames as described above
 *  0b1..Will reject frames as described above
 */
#define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)

#define ENET_RCR_FCE_MASK                        (0x20U)
#define ENET_RCR_FCE_SHIFT                       (5U)
/*! FCE - Flow Control Enable
 *  0b0..Disable flow control
 *  0b1..Enable flow control
 */
#define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)

#define ENET_RCR_RMII_MODE_MASK                  (0x100U)
#define ENET_RCR_RMII_MODE_SHIFT                 (8U)
/*! RMII_MODE - RMII Mode Enable
 *  0b0..MAC configured for MII mode.
 *  0b1..MAC configured for RMII operation.
 */
#define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)

#define ENET_RCR_RMII_10T_MASK                   (0x200U)
#define ENET_RCR_RMII_10T_SHIFT                  (9U)
/*! RMII_10T
 *  0b0..100-Mbit/s operation.
 *  0b1..10-Mbit/s operation.
 */
#define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)

#define ENET_RCR_PADEN_MASK                      (0x1000U)
#define ENET_RCR_PADEN_SHIFT                     (12U)
/*! PADEN - Enable Frame Padding Remove On Receive
 *  0b0..No padding is removed on receive by the MAC.
 *  0b1..Padding is removed from received frames.
 */
#define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)

#define ENET_RCR_PAUFWD_MASK                     (0x2000U)
#define ENET_RCR_PAUFWD_SHIFT                    (13U)
/*! PAUFWD - Terminate/Forward Pause Frames
 *  0b0..Pause frames are terminated and discarded in the MAC.
 *  0b1..Pause frames are forwarded to the user application.
 */
#define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)

#define ENET_RCR_CRCFWD_MASK                     (0x4000U)
#define ENET_RCR_CRCFWD_SHIFT                    (14U)
/*! CRCFWD - Terminate/Forward Received CRC
 *  0b0..The CRC field of received frames is transmitted to the user application.
 *  0b1..The CRC field is stripped from the frame.
 */
#define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)

#define ENET_RCR_CFEN_MASK                       (0x8000U)
#define ENET_RCR_CFEN_SHIFT                      (15U)
/*! CFEN - MAC Control Frame Enable
 *  0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
 *  0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
 */
#define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)

#define ENET_RCR_MAX_FL_MASK                     (0x3FFF0000U)
#define ENET_RCR_MAX_FL_SHIFT                    (16U)
/*! MAX_FL - Maximum Frame Length */
#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)

#define ENET_RCR_NLC_MASK                        (0x40000000U)
#define ENET_RCR_NLC_SHIFT                       (30U)
/*! NLC - Payload Length Check Disable
 *  0b0..The payload length check is disabled.
 *  0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
 */
#define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)

#define ENET_RCR_GRS_MASK                        (0x80000000U)
#define ENET_RCR_GRS_SHIFT                       (31U)
/*! GRS - Graceful Receive Stopped
 *  0b0..Receive not stopped
 *  0b1..Receive stopped
 */
#define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
/*! @} */

/*! @name TCR - Transmit Control Register */
/*! @{ */

#define ENET_TCR_GTS_MASK                        (0x1U)
#define ENET_TCR_GTS_SHIFT                       (0U)
/*! GTS - Graceful Transmit Stop
 *  0b0..Disable graceful transmit stop
 *  0b1..Enable graceful transmit stop
 */
#define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)

#define ENET_TCR_FDEN_MASK                       (0x4U)
#define ENET_TCR_FDEN_SHIFT                      (2U)
/*! FDEN - Full-Duplex Enable
 *  0b0..Disable full-duplex
 *  0b1..Enable full-duplex
 */
#define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)

#define ENET_TCR_TFC_PAUSE_MASK                  (0x8U)
#define ENET_TCR_TFC_PAUSE_SHIFT                 (3U)
/*! TFC_PAUSE - Transmit Frame Control Pause
 *  0b0..No PAUSE frame transmitted.
 *  0b1..The MAC stops transmission of data frames after the current transmission is complete.
 */
#define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)

#define ENET_TCR_RFC_PAUSE_MASK                  (0x10U)
#define ENET_TCR_RFC_PAUSE_SHIFT                 (4U)
/*! RFC_PAUSE - Receive Frame Control Pause */
#define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)

#define ENET_TCR_ADDSEL_MASK                     (0xE0U)
#define ENET_TCR_ADDSEL_SHIFT                    (5U)
/*! ADDSEL - Source MAC Address Select On Transmit
 *  0b000..Node MAC address programmed on PADDR1/2 registers.
 *  0b100..Reserved.
 *  0b101..Reserved.
 *  0b110..Reserved.
 */
#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)

#define ENET_TCR_ADDINS_MASK                     (0x100U)
#define ENET_TCR_ADDINS_SHIFT                    (8U)
/*! ADDINS - Set MAC Address On Transmit
 *  0b0..The source MAC address is not modified by the MAC.
 *  0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
 */
#define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)

#define ENET_TCR_CRCFWD_MASK                     (0x200U)
#define ENET_TCR_CRCFWD_SHIFT                    (9U)
/*! CRCFWD - Forward Frame From Application With CRC
 *  0b0..TxBD[TC] controls whether the frame has a CRC from the application.
 *  0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
 */
#define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
/*! @} */

/*! @name PALR - Physical Address Lower Register */
/*! @{ */

#define ENET_PALR_PADDR1_MASK                    (0xFFFFFFFFU)
#define ENET_PALR_PADDR1_SHIFT                   (0U)
/*! PADDR1 - Pause Address */
#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
/*! @} */

/*! @name PAUR - Physical Address Upper Register */
/*! @{ */

#define ENET_PAUR_TYPE_MASK                      (0xFFFFU)
#define ENET_PAUR_TYPE_SHIFT                     (0U)
/*! TYPE - Type Field In PAUSE Frames */
#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)

#define ENET_PAUR_PADDR2_MASK                    (0xFFFF0000U)
#define ENET_PAUR_PADDR2_SHIFT                   (16U)
#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
/*! @} */

/*! @name OPD - Opcode/Pause Duration Register */
/*! @{ */

#define ENET_OPD_PAUSE_DUR_MASK                  (0xFFFFU)
#define ENET_OPD_PAUSE_DUR_SHIFT                 (0U)
/*! PAUSE_DUR - Pause Duration */
#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)

#define ENET_OPD_OPCODE_MASK                     (0xFFFF0000U)
#define ENET_OPD_OPCODE_SHIFT                    (16U)
/*! OPCODE - Opcode Field In PAUSE Frames */
#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
/*! @} */

/*! @name TXIC - Transmit Interrupt Coalescing Register */
/*! @{ */

#define ENET_TXIC_ICTT_MASK                      (0xFFFFU)
#define ENET_TXIC_ICTT_SHIFT                     (0U)
/*! ICTT - Interrupt coalescing timer threshold */
#define ENET_TXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)

#define ENET_TXIC_ICFT_MASK                      (0xFF00000U)
#define ENET_TXIC_ICFT_SHIFT                     (20U)
/*! ICFT - Interrupt coalescing frame count threshold */
#define ENET_TXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)

#define ENET_TXIC_ICCS_MASK                      (0x40000000U)
#define ENET_TXIC_ICCS_SHIFT                     (30U)
/*! ICCS - Interrupt Coalescing Timer Clock Source Select
 *  0b0..Use MII/GMII TX clocks.
 *  0b1..Use ENET system clock.
 */
#define ENET_TXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)

#define ENET_TXIC_ICEN_MASK                      (0x80000000U)
#define ENET_TXIC_ICEN_SHIFT                     (31U)
/*! ICEN - Interrupt Coalescing Enable
 *  0b0..Disable Interrupt coalescing.
 *  0b1..Enable Interrupt coalescing.
 */
#define ENET_TXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
/*! @} */

/* The count of ENET_TXIC */
#define ENET_TXIC_COUNT                          (1U)

/*! @name RXIC - Receive Interrupt Coalescing Register */
/*! @{ */

#define ENET_RXIC_ICTT_MASK                      (0xFFFFU)
#define ENET_RXIC_ICTT_SHIFT                     (0U)
/*! ICTT - Interrupt coalescing timer threshold */
#define ENET_RXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)

#define ENET_RXIC_ICFT_MASK                      (0xFF00000U)
#define ENET_RXIC_ICFT_SHIFT                     (20U)
/*! ICFT - Interrupt coalescing frame count threshold */
#define ENET_RXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)

#define ENET_RXIC_ICCS_MASK                      (0x40000000U)
#define ENET_RXIC_ICCS_SHIFT                     (30U)
/*! ICCS - Interrupt Coalescing Timer Clock Source Select
 *  0b0..Use MII/GMII TX clocks.
 *  0b1..Use ENET system clock.
 */
#define ENET_RXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)

#define ENET_RXIC_ICEN_MASK                      (0x80000000U)
#define ENET_RXIC_ICEN_SHIFT                     (31U)
/*! ICEN - Interrupt Coalescing Enable
 *  0b0..Disable Interrupt coalescing.
 *  0b1..Enable Interrupt coalescing.
 */
#define ENET_RXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
/*! @} */

/* The count of ENET_RXIC */
#define ENET_RXIC_COUNT                          (1U)

/*! @name IAUR - Descriptor Individual Upper Address Register */
/*! @{ */

#define ENET_IAUR_IADDR1_MASK                    (0xFFFFFFFFU)
#define ENET_IAUR_IADDR1_SHIFT                   (0U)
#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
/*! @} */

/*! @name IALR - Descriptor Individual Lower Address Register */
/*! @{ */

#define ENET_IALR_IADDR2_MASK                    (0xFFFFFFFFU)
#define ENET_IALR_IADDR2_SHIFT                   (0U)
#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
/*! @} */

/*! @name GAUR - Descriptor Group Upper Address Register */
/*! @{ */

#define ENET_GAUR_GADDR1_MASK                    (0xFFFFFFFFU)
#define ENET_GAUR_GADDR1_SHIFT                   (0U)
#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
/*! @} */

/*! @name GALR - Descriptor Group Lower Address Register */
/*! @{ */

#define ENET_GALR_GADDR2_MASK                    (0xFFFFFFFFU)
#define ENET_GALR_GADDR2_SHIFT                   (0U)
#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
/*! @} */

/*! @name TFWR - Transmit FIFO Watermark Register */
/*! @{ */

#define ENET_TFWR_TFWR_MASK                      (0x3FU)
#define ENET_TFWR_TFWR_SHIFT                     (0U)
/*! TFWR - Transmit FIFO Write
 *  0b000000..64 bytes written.
 *  0b000001..64 bytes written.
 *  0b000010..128 bytes written.
 *  0b000011..192 bytes written.
 *  0b011111..1984 bytes written.
 */
#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)

#define ENET_TFWR_STRFWD_MASK                    (0x100U)
#define ENET_TFWR_STRFWD_SHIFT                   (8U)
/*! STRFWD - Store And Forward Enable
 *  0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
 *  0b1..Enabled.
 */
#define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
/*! @} */

/*! @name RDSR - Receive Descriptor Ring 0 Start Register */
/*! @{ */

#define ENET_RDSR_R_DES_START_MASK               (0xFFFFFFF8U)
#define ENET_RDSR_R_DES_START_SHIFT              (3U)
#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
/*! @} */

/*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
/*! @{ */

#define ENET_TDSR_X_DES_START_MASK               (0xFFFFFFF8U)
#define ENET_TDSR_X_DES_START_SHIFT              (3U)
#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
/*! @} */

/*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
/*! @{ */

#define ENET_MRBR_R_BUF_SIZE_MASK                (0x3FF0U)
#define ENET_MRBR_R_BUF_SIZE_SHIFT               (4U)
#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
/*! @} */

/*! @name RSFL - Receive FIFO Section Full Threshold */
/*! @{ */

#define ENET_RSFL_RX_SECTION_FULL_MASK           (0xFFU)
#define ENET_RSFL_RX_SECTION_FULL_SHIFT          (0U)
/*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold */
#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
/*! @} */

/*! @name RSEM - Receive FIFO Section Empty Threshold */
/*! @{ */

#define ENET_RSEM_RX_SECTION_EMPTY_MASK          (0xFFU)
#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         (0U)
/*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold */
#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)

#define ENET_RSEM_STAT_SECTION_EMPTY_MASK        (0x1F0000U)
#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       (16U)
/*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold */
#define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
/*! @} */

/*! @name RAEM - Receive FIFO Almost Empty Threshold */
/*! @{ */

#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           (0xFFU)
#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          (0U)
/*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold */
#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
/*! @} */

/*! @name RAFL - Receive FIFO Almost Full Threshold */
/*! @{ */

#define ENET_RAFL_RX_ALMOST_FULL_MASK            (0xFFU)
#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           (0U)
/*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold */
#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
/*! @} */

/*! @name TSEM - Transmit FIFO Section Empty Threshold */
/*! @{ */

#define ENET_TSEM_TX_SECTION_EMPTY_MASK          (0xFFU)
#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         (0U)
/*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold */
#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
/*! @} */

/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
/*! @{ */

#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           (0xFFU)
#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          (0U)
/*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold */
#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
/*! @} */

/*! @name TAFL - Transmit FIFO Almost Full Threshold */
/*! @{ */

#define ENET_TAFL_TX_ALMOST_FULL_MASK            (0xFFU)
#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           (0U)
/*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold */
#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
/*! @} */

/*! @name TIPG - Transmit Inter-Packet Gap */
/*! @{ */

#define ENET_TIPG_IPG_MASK                       (0x1FU)
#define ENET_TIPG_IPG_SHIFT                      (0U)
/*! IPG - Transmit Inter-Packet Gap */
#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
/*! @} */

/*! @name FTRL - Frame Truncation Length */
/*! @{ */

#define ENET_FTRL_TRUNC_FL_MASK                  (0x3FFFU)
#define ENET_FTRL_TRUNC_FL_SHIFT                 (0U)
/*! TRUNC_FL - Frame Truncation Length */
#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
/*! @} */

/*! @name TACC - Transmit Accelerator Function Configuration */
/*! @{ */

#define ENET_TACC_SHIFT16_MASK                   (0x1U)
#define ENET_TACC_SHIFT16_SHIFT                  (0U)
/*! SHIFT16 - TX FIFO Shift-16
 *  0b0..Disabled.
 *  0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
 *       frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
 *       function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
 *       extended to a 16-byte header.
 */
#define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)

#define ENET_TACC_IPCHK_MASK                     (0x8U)
#define ENET_TACC_IPCHK_SHIFT                    (3U)
/*! IPCHK
 *  0b0..Checksum is not inserted.
 *  0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
 *       be cleared. If a non-IP frame is transmitted the frame is not modified.
 */
#define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)

#define ENET_TACC_PROCHK_MASK                    (0x10U)
#define ENET_TACC_PROCHK_SHIFT                   (4U)
/*! PROCHK
 *  0b0..Checksum not inserted.
 *  0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
 *       frame. The checksum field must be cleared. The other frames are not modified.
 */
#define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
/*! @} */

/*! @name RACC - Receive Accelerator Function Configuration */
/*! @{ */

#define ENET_RACC_PADREM_MASK                    (0x1U)
#define ENET_RACC_PADREM_SHIFT                   (0U)
/*! PADREM - Enable Padding Removal For Short IP Frames
 *  0b0..Padding not removed.
 *  0b1..Any bytes following the IP payload section of the frame are removed from the frame.
 */
#define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)

#define ENET_RACC_IPDIS_MASK                     (0x2U)
#define ENET_RACC_IPDIS_SHIFT                    (1U)
/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
 *  0b0..Frames with wrong IPv4 header checksum are not discarded.
 *  0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
 *       header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
 *       store and forward mode (RSFL cleared).
 */
#define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)

#define ENET_RACC_PRODIS_MASK                    (0x4U)
#define ENET_RACC_PRODIS_SHIFT                   (2U)
/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
 *  0b0..Frames with wrong checksum are not discarded.
 *  0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
 *       is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
 *       cleared).
 */
#define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)

#define ENET_RACC_LINEDIS_MASK                   (0x40U)
#define ENET_RACC_LINEDIS_SHIFT                  (6U)
/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
 *  0b0..Frames with errors are not discarded.
 *  0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
 */
#define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)

#define ENET_RACC_SHIFT16_MASK                   (0x80U)
#define ENET_RACC_SHIFT16_SHIFT                  (7U)
/*! SHIFT16 - RX FIFO Shift-16
 *  0b0..Disabled.
 *  0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
 */
#define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
/*! @} */

/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
/*! @{ */

#define ENET_RMON_T_PACKETS_TXPKTS_MASK          (0xFFFFU)
#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         (0U)
/*! TXPKTS - Packet count */
#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
/*! @{ */

#define ENET_RMON_T_BC_PKT_TXPKTS_MASK           (0xFFFFU)
#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          (0U)
/*! TXPKTS - Number of broadcast packets */
#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
/*! @{ */

#define ENET_RMON_T_MC_PKT_TXPKTS_MASK           (0xFFFFU)
#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          (0U)
/*! TXPKTS - Number of multicast packets */
#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
/*! @{ */

#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        (0xFFFFU)
#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       (0U)
/*! TXPKTS - Number of packets with CRC/align error */
#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
/*! @{ */

#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        (0xFFFFU)
#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       (0U)
/*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC */
#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
/*! @{ */

#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         (0xFFFFU)
#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        (0U)
/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC */
#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
/*! @{ */

#define ENET_RMON_T_FRAG_TXPKTS_MASK             (0xFFFFU)
#define ENET_RMON_T_FRAG_TXPKTS_SHIFT            (0U)
/*! TXPKTS - Number of packets less than 64 bytes with bad CRC */
#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
/*! @{ */

#define ENET_RMON_T_JAB_TXPKTS_MASK              (0xFFFFU)
#define ENET_RMON_T_JAB_TXPKTS_SHIFT             (0U)
/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC */
#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_COL - Tx Collision Count Statistic Register */
/*! @{ */

#define ENET_RMON_T_COL_TXPKTS_MASK              (0xFFFFU)
#define ENET_RMON_T_COL_TXPKTS_SHIFT             (0U)
/*! TXPKTS - Number of transmit collisions */
#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
/*! @{ */

#define ENET_RMON_T_P64_TXPKTS_MASK              (0xFFFFU)
#define ENET_RMON_T_P64_TXPKTS_SHIFT             (0U)
/*! TXPKTS - Number of 64-byte transmit packets */
#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
/*! @{ */

#define ENET_RMON_T_P65TO127_TXPKTS_MASK         (0xFFFFU)
#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        (0U)
/*! TXPKTS - Number of 65- to 127-byte transmit packets */
#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
/*! @{ */

#define ENET_RMON_T_P128TO255_TXPKTS_MASK        (0xFFFFU)
#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       (0U)
/*! TXPKTS - Number of 128- to 255-byte transmit packets */
#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
/*! @{ */

#define ENET_RMON_T_P256TO511_TXPKTS_MASK        (0xFFFFU)
#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       (0U)
/*! TXPKTS - Number of 256- to 511-byte transmit packets */
#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
/*! @{ */

#define ENET_RMON_T_P512TO1023_TXPKTS_MASK       (0xFFFFU)
#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      (0U)
/*! TXPKTS - Number of 512- to 1023-byte transmit packets */
#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
/*! @{ */

#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      (0xFFFFU)
#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     (0U)
/*! TXPKTS - Number of 1024- to 2047-byte transmit packets */
#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
/*! @{ */

#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        (0xFFFFU)
#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       (0U)
/*! TXPKTS - Number of transmit packets greater than 2048 bytes */
#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
/*! @} */

/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
/*! @{ */

#define ENET_RMON_T_OCTETS_TXOCTS_MASK           (0xFFFFFFFFU)
#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          (0U)
/*! TXOCTS - Number of transmit octets */
#define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
/*! @} */

/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
/*! @{ */

#define ENET_IEEE_T_FRAME_OK_COUNT_MASK          (0xFFFFU)
#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         (0U)
/*! COUNT - Number of frames transmitted OK */
#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
/*! @} */

/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
/*! @{ */

#define ENET_IEEE_T_1COL_COUNT_MASK              (0xFFFFU)
#define ENET_IEEE_T_1COL_COUNT_SHIFT             (0U)
/*! COUNT - Number of frames transmitted with one collision */
#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
/*! @} */

/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
/*! @{ */

#define ENET_IEEE_T_MCOL_COUNT_MASK              (0xFFFFU)
#define ENET_IEEE_T_MCOL_COUNT_SHIFT             (0U)
/*! COUNT - Number of frames transmitted with multiple collisions */
#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
/*! @} */

/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
/*! @{ */

#define ENET_IEEE_T_DEF_COUNT_MASK               (0xFFFFU)
#define ENET_IEEE_T_DEF_COUNT_SHIFT              (0U)
/*! COUNT - Number of frames transmitted with deferral delay */
#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
/*! @} */

/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
/*! @{ */

#define ENET_IEEE_T_LCOL_COUNT_MASK              (0xFFFFU)
#define ENET_IEEE_T_LCOL_COUNT_SHIFT             (0U)
/*! COUNT - Number of frames transmitted with late collision */
#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
/*! @} */

/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
/*! @{ */

#define ENET_IEEE_T_EXCOL_COUNT_MASK             (0xFFFFU)
#define ENET_IEEE_T_EXCOL_COUNT_SHIFT            (0U)
/*! COUNT - Number of frames transmitted with excessive collisions */
#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
/*! @} */

/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
/*! @{ */

#define ENET_IEEE_T_MACERR_COUNT_MASK            (0xFFFFU)
#define ENET_IEEE_T_MACERR_COUNT_SHIFT           (0U)
/*! COUNT - Number of frames transmitted with transmit FIFO underrun */
#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
/*! @} */

/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
/*! @{ */

#define ENET_IEEE_T_CSERR_COUNT_MASK             (0xFFFFU)
#define ENET_IEEE_T_CSERR_COUNT_SHIFT            (0U)
/*! COUNT - Number of frames transmitted with carrier sense error */
#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
/*! @} */

/*! @name IEEE_T_SQE - Reserved Statistic Register */
/*! @{ */

#define ENET_IEEE_T_SQE_COUNT_MASK               (0xFFFFU)
#define ENET_IEEE_T_SQE_COUNT_SHIFT              (0U)
/*! COUNT - This read-only field is reserved and always has the value 0 */
#define ENET_IEEE_T_SQE_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
/*! @} */

/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
/*! @{ */

#define ENET_IEEE_T_FDXFC_COUNT_MASK             (0xFFFFU)
#define ENET_IEEE_T_FDXFC_COUNT_SHIFT            (0U)
/*! COUNT - Number of flow-control pause frames transmitted */
#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
/*! @} */

/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
/*! @{ */

#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        (0U)
/*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). */
#define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
/*! @} */

/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
/*! @{ */

#define ENET_RMON_R_PACKETS_COUNT_MASK           (0xFFFFU)
#define ENET_RMON_R_PACKETS_COUNT_SHIFT          (0U)
/*! COUNT - Number of packets received */
#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
/*! @} */

/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
/*! @{ */

#define ENET_RMON_R_BC_PKT_COUNT_MASK            (0xFFFFU)
#define ENET_RMON_R_BC_PKT_COUNT_SHIFT           (0U)
/*! COUNT - Number of receive broadcast packets */
#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
/*! @} */

/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
/*! @{ */

#define ENET_RMON_R_MC_PKT_COUNT_MASK            (0xFFFFU)
#define ENET_RMON_R_MC_PKT_COUNT_SHIFT           (0U)
/*! COUNT - Number of receive multicast packets */
#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
/*! @} */

/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
/*! @{ */

#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         (0xFFFFU)
#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        (0U)
/*! COUNT - Number of receive packets with CRC or align error */
#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
/*! @} */

/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
/*! @{ */

#define ENET_RMON_R_UNDERSIZE_COUNT_MASK         (0xFFFFU)
#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        (0U)
/*! COUNT - Number of receive packets with less than 64 bytes and good CRC */
#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
/*! @} */

/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
/*! @{ */

#define ENET_RMON_R_OVERSIZE_COUNT_MASK          (0xFFFFU)
#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         (0U)
/*! COUNT - Number of receive packets greater than MAX_FL and good CRC */
#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
/*! @} */

/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
/*! @{ */

#define ENET_RMON_R_FRAG_COUNT_MASK              (0xFFFFU)
#define ENET_RMON_R_FRAG_COUNT_SHIFT             (0U)
/*! COUNT - Number of receive packets with less than 64 bytes and bad CRC */
#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
/*! @} */

/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
/*! @{ */

#define ENET_RMON_R_JAB_COUNT_MASK               (0xFFFFU)
#define ENET_RMON_R_JAB_COUNT_SHIFT              (0U)
/*! COUNT - Number of receive packets greater than MAX_FL and bad CRC */
#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
/*! @} */

/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
/*! @{ */

#define ENET_RMON_R_P64_COUNT_MASK               (0xFFFFU)
#define ENET_RMON_R_P64_COUNT_SHIFT              (0U)
/*! COUNT - Number of 64-byte receive packets */
#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
/*! @} */

/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
/*! @{ */

#define ENET_RMON_R_P65TO127_COUNT_MASK          (0xFFFFU)
#define ENET_RMON_R_P65TO127_COUNT_SHIFT         (0U)
/*! COUNT - Number of 65- to 127-byte recieve packets */
#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
/*! @} */

/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
/*! @{ */

#define ENET_RMON_R_P128TO255_COUNT_MASK         (0xFFFFU)
#define ENET_RMON_R_P128TO255_COUNT_SHIFT        (0U)
/*! COUNT - Number of 128- to 255-byte recieve packets */
#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
/*! @} */

/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
/*! @{ */

#define ENET_RMON_R_P256TO511_COUNT_MASK         (0xFFFFU)
#define ENET_RMON_R_P256TO511_COUNT_SHIFT        (0U)
/*! COUNT - Number of 256- to 511-byte recieve packets */
#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
/*! @} */

/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
/*! @{ */

#define ENET_RMON_R_P512TO1023_COUNT_MASK        (0xFFFFU)
#define ENET_RMON_R_P512TO1023_COUNT_SHIFT       (0U)
/*! COUNT - Number of 512- to 1023-byte recieve packets */
#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
/*! @} */

/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
/*! @{ */

#define ENET_RMON_R_P1024TO2047_COUNT_MASK       (0xFFFFU)
#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      (0U)
/*! COUNT - Number of 1024- to 2047-byte recieve packets */
#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
/*! @} */

/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
/*! @{ */

#define ENET_RMON_R_P_GTE2048_COUNT_MASK         (0xFFFFU)
#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        (0U)
/*! COUNT - Number of greater-than-2048-byte recieve packets */
#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
/*! @} */

/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
/*! @{ */

#define ENET_RMON_R_OCTETS_COUNT_MASK            (0xFFFFFFFFU)
#define ENET_RMON_R_OCTETS_COUNT_SHIFT           (0U)
/*! COUNT - Number of receive octets */
#define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
/*! @} */

/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
/*! @{ */

#define ENET_IEEE_R_DROP_COUNT_MASK              (0xFFFFU)
#define ENET_IEEE_R_DROP_COUNT_SHIFT             (0U)
/*! COUNT - Frame count */
#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
/*! @} */

/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
/*! @{ */

#define ENET_IEEE_R_FRAME_OK_COUNT_MASK          (0xFFFFU)
#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         (0U)
/*! COUNT - Number of frames received OK */
#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
/*! @} */

/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
/*! @{ */

#define ENET_IEEE_R_CRC_COUNT_MASK               (0xFFFFU)
#define ENET_IEEE_R_CRC_COUNT_SHIFT              (0U)
/*! COUNT - Number of frames received with CRC error */
#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
/*! @} */

/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
/*! @{ */

#define ENET_IEEE_R_ALIGN_COUNT_MASK             (0xFFFFU)
#define ENET_IEEE_R_ALIGN_COUNT_SHIFT            (0U)
/*! COUNT - Number of frames received with alignment error */
#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
/*! @} */

/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
/*! @{ */

#define ENET_IEEE_R_MACERR_COUNT_MASK            (0xFFFFU)
#define ENET_IEEE_R_MACERR_COUNT_SHIFT           (0U)
/*! COUNT - Receive FIFO overflow count */
#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
/*! @} */

/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
/*! @{ */

#define ENET_IEEE_R_FDXFC_COUNT_MASK             (0xFFFFU)
#define ENET_IEEE_R_FDXFC_COUNT_SHIFT            (0U)
/*! COUNT - Number of flow-control pause frames received */
#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
/*! @} */

/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
/*! @{ */

#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        (0U)
/*! COUNT - Number of octets for frames received without error */
#define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
/*! @} */

/*! @name ATCR - Adjustable Timer Control Register */
/*! @{ */

#define ENET_ATCR_EN_MASK                        (0x1U)
#define ENET_ATCR_EN_SHIFT                       (0U)
/*! EN - Enable Timer
 *  0b0..The timer stops at the current value.
 *  0b1..The timer starts incrementing.
 */
#define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)

#define ENET_ATCR_OFFEN_MASK                     (0x4U)
#define ENET_ATCR_OFFEN_SHIFT                    (2U)
/*! OFFEN - Enable One-Shot Offset Event
 *  0b0..Disable.
 *  0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
 *       when the offset event is reached, so no further event occurs until the field is set again. The timer
 *       offset value must be set before setting this field.
 */
#define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)

#define ENET_ATCR_OFFRST_MASK                    (0x8U)
#define ENET_ATCR_OFFRST_SHIFT                   (3U)
/*! OFFRST - Reset Timer On Offset Event
 *  0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
 *  0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
 */
#define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)

#define ENET_ATCR_PEREN_MASK                     (0x10U)
#define ENET_ATCR_PEREN_SHIFT                    (4U)
/*! PEREN - Enable Periodical Event
 *  0b0..Disable.
 *  0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
 *       the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
 *       setting this bit. Not all devices contain the event signal output. See the chip configuration details.
 */
#define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)

#define ENET_ATCR_PINPER_MASK                    (0x80U)
#define ENET_ATCR_PINPER_SHIFT                   (7U)
/*! PINPER - Enables event signal output external pin frc_evt_period assertion on period event
 *  0b0..Disable.
 *  0b1..Enable.
 */
#define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)

#define ENET_ATCR_RESTART_MASK                   (0x200U)
#define ENET_ATCR_RESTART_SHIFT                  (9U)
/*! RESTART - Reset Timer */
#define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)

#define ENET_ATCR_CAPTURE_MASK                   (0x800U)
#define ENET_ATCR_CAPTURE_SHIFT                  (11U)
/*! CAPTURE - Capture Timer Value
 *  0b0..No effect.
 *  0b1..The current time is captured and can be read from the ATVR register.
 */
#define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)

#define ENET_ATCR_SLAVE_MASK                     (0x2000U)
#define ENET_ATCR_SLAVE_SHIFT                    (13U)
/*! SLAVE - Enable Timer Slave Mode
 *  0b0..The timer is active and all configuration fields in this register are relevant.
 *  0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
 *       CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
 */
#define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
/*! @} */

/*! @name ATVR - Timer Value Register */
/*! @{ */

#define ENET_ATVR_ATIME_MASK                     (0xFFFFFFFFU)
#define ENET_ATVR_ATIME_SHIFT                    (0U)
#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
/*! @} */

/*! @name ATOFF - Timer Offset Register */
/*! @{ */

#define ENET_ATOFF_OFFSET_MASK                   (0xFFFFFFFFU)
#define ENET_ATOFF_OFFSET_SHIFT                  (0U)
#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
/*! @} */

/*! @name ATPER - Timer Period Register */
/*! @{ */

#define ENET_ATPER_PERIOD_MASK                   (0xFFFFFFFFU)
#define ENET_ATPER_PERIOD_SHIFT                  (0U)
/*! PERIOD - Value for generating periodic events */
#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
/*! @} */

/*! @name ATCOR - Timer Correction Register */
/*! @{ */

#define ENET_ATCOR_COR_MASK                      (0x7FFFFFFFU)
#define ENET_ATCOR_COR_SHIFT                     (0U)
/*! COR - Correction Counter Wrap-Around Value */
#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
/*! @} */

/*! @name ATINC - Time-Stamping Clock Period Register */
/*! @{ */

#define ENET_ATINC_INC_MASK                      (0x7FU)
#define ENET_ATINC_INC_SHIFT                     (0U)
/*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds */
#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)

#define ENET_ATINC_INC_CORR_MASK                 (0x7F00U)
#define ENET_ATINC_INC_CORR_SHIFT                (8U)
/*! INC_CORR - Correction Increment Value */
#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
/*! @} */

/*! @name ATSTMP - Timestamp of Last Transmitted Frame */
/*! @{ */

#define ENET_ATSTMP_TIMESTAMP_MASK               (0xFFFFFFFFU)
#define ENET_ATSTMP_TIMESTAMP_SHIFT              (0U)
/*! TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the
 *    ff_tx_ts_frm signal asserted from the user application
 */
#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
/*! @} */

/*! @name TGSR - Timer Global Status Register */
/*! @{ */

#define ENET_TGSR_TF0_MASK                       (0x1U)
#define ENET_TGSR_TF0_SHIFT                      (0U)
/*! TF0 - Copy Of Timer Flag For Channel 0
 *  0b0..Timer Flag for Channel 0 is clear
 *  0b1..Timer Flag for Channel 0 is set
 */
#define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)

#define ENET_TGSR_TF1_MASK                       (0x2U)
#define ENET_TGSR_TF1_SHIFT                      (1U)
/*! TF1 - Copy Of Timer Flag For Channel 1
 *  0b0..Timer Flag for Channel 1 is clear
 *  0b1..Timer Flag for Channel 1 is set
 */
#define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)

#define ENET_TGSR_TF2_MASK                       (0x4U)
#define ENET_TGSR_TF2_SHIFT                      (2U)
/*! TF2 - Copy Of Timer Flag For Channel 2
 *  0b0..Timer Flag for Channel 2 is clear
 *  0b1..Timer Flag for Channel 2 is set
 */
#define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)

#define ENET_TGSR_TF3_MASK                       (0x8U)
#define ENET_TGSR_TF3_SHIFT                      (3U)
/*! TF3 - Copy Of Timer Flag For Channel 3
 *  0b0..Timer Flag for Channel 3 is clear
 *  0b1..Timer Flag for Channel 3 is set
 */
#define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
/*! @} */

/*! @name TCSR - Timer Control Status Register */
/*! @{ */

#define ENET_TCSR_TDRE_MASK                      (0x1U)
#define ENET_TCSR_TDRE_SHIFT                     (0U)
/*! TDRE - Timer DMA Request Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)

#define ENET_TCSR_TMODE_MASK                     (0x3CU)
#define ENET_TCSR_TMODE_SHIFT                    (2U)
/*! TMODE - Timer Mode
 *  0b0000..Timer Channel is disabled.
 *  0b0001..Timer Channel is configured for Input Capture on rising edge.
 *  0b0010..Timer Channel is configured for Input Capture on falling edge.
 *  0b0011..Timer Channel is configured for Input Capture on both edges.
 *  0b0100..Timer Channel is configured for Output Compare - software only.
 *  0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
 *  0b0110..Timer Channel is configured for Output Compare - clear output on compare.
 *  0b0111..Timer Channel is configured for Output Compare - set output on compare.
 *  0b1000..Reserved
 *  0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
 *  0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
 *  0b110x..Reserved
 *  0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
 *  0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
 */
#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)

#define ENET_TCSR_TIE_MASK                       (0x40U)
#define ENET_TCSR_TIE_SHIFT                      (6U)
/*! TIE - Timer Interrupt Enable
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)

#define ENET_TCSR_TF_MASK                        (0x80U)
#define ENET_TCSR_TF_SHIFT                       (7U)
/*! TF - Timer Flag
 *  0b0..Input Capture or Output Compare has not occurred.
 *  0b1..Input Capture or Output Compare has occurred.
 */
#define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

#define ENET_TCSR_TPWC_MASK                      (0xF800U)
#define ENET_TCSR_TPWC_SHIFT                     (11U)
/*! TPWC - Timer PulseWidth Control
 *  0b00000..Pulse width is one 1588-clock cycle.
 *  0b00001..Pulse width is two 1588-clock cycles.
 *  0b00010..Pulse width is three 1588-clock cycles.
 *  0b00011..Pulse width is four 1588-clock cycles.
 *  0b11111..Pulse width is 32 1588-clock cycles.
 */
#define ENET_TCSR_TPWC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
/*! @} */

/* The count of ENET_TCSR */
#define ENET_TCSR_COUNT                          (4U)

/*! @name TCCR - Timer Compare Capture Register */
/*! @{ */

#define ENET_TCCR_TCC_MASK                       (0xFFFFFFFFU)
#define ENET_TCCR_TCC_SHIFT                      (0U)
/*! TCC - Timer Capture Compare */
#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
/*! @} */

/* The count of ENET_TCCR */
#define ENET_TCCR_COUNT                          (4U)


/*!
 * @}
 */ /* end of group ENET_Register_Masks */


/* ENET - Peripheral instance base addresses */
/** Peripheral ENET base address */
#define ENET_BASE                                (0x29950000u)
/** Peripheral ENET base pointer */
#define ENET                                     ((ENET_Type *)ENET_BASE)
/** Array initializer of ENET peripheral base addresses */
#define ENET_BASE_ADDRS                          { ENET_BASE }
/** Array initializer of ENET peripheral base pointers */
#define ENET_BASE_PTRS                           { ENET }
/* ENET Buffer Descriptor and Buffer Address Alignment. */
#define ENET_BUFF_ALIGNMENT                      (64U)


/*!
 * @}
 */ /* end of group ENET_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- EPDC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup EPDC_Peripheral_Access_Layer EPDC Peripheral Access Layer
 * @{
 */

/** EPDC - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0 */
    __IO uint32_t RW;                                /**< Control Register, offset: 0x0 */
    __IO uint32_t SET;                               /**< Control Register, offset: 0x4 */
    __IO uint32_t CLR;                               /**< Control Register, offset: 0x8 */
    __IO uint32_t TOG;                               /**< Control Register, offset: 0xC */
  } CTRL;
  __IO uint32_t WB_ADDR_TCE;                       /**< Working Buffer Address for TCE, offset: 0x10 */
       uint8_t RESERVED_0[12];
  __IO uint32_t WVADDR;                            /**< Waveform Address Pointer, offset: 0x20 */
       uint8_t RESERVED_1[12];
  __IO uint32_t WB_ADDR;                           /**< Working Buffer Address, offset: 0x30 */
       uint8_t RESERVED_2[12];
  __IO uint32_t RES;                               /**< Screen Resolution, offset: 0x40 */
       uint8_t RESERVED_3[12];
  struct {                                         /* offset: 0x50 */
    __IO uint32_t RW;                                /**< Format Control Register, offset: 0x50 */
    __IO uint32_t SET;                               /**< Format Control Register, offset: 0x54 */
    __IO uint32_t CLR;                               /**< Format Control Register, offset: 0x58 */
    __IO uint32_t TOG;                               /**< Format Control Register, offset: 0x5C */
  } FORMAT;
  struct {                                         /* offset: 0x60 */
    __IO uint32_t RW;                                /**< Working Buffer Field Setting, offset: 0x60 */
    __IO uint32_t SET;                               /**< Working Buffer Field Setting, offset: 0x64 */
    __IO uint32_t CLR;                               /**< Working Buffer Field Setting, offset: 0x68 */
    __IO uint32_t TOG;                               /**< Working Buffer Field Setting, offset: 0x6C */
  } WB_FIELD0;
  struct {                                         /* offset: 0x70 */
    __IO uint32_t RW;                                /**< Working Buffer Field Setting, offset: 0x70 */
    __IO uint32_t SET;                               /**< Working Buffer Field Setting, offset: 0x74 */
    __IO uint32_t CLR;                               /**< Working Buffer Field Setting, offset: 0x78 */
    __IO uint32_t TOG;                               /**< Working Buffer Field Setting, offset: 0x7C */
  } WB_FIELD1;
  struct {                                         /* offset: 0x80 */
    __IO uint32_t RW;                                /**< Working Buffer Field Setting, offset: 0x80 */
    __IO uint32_t SET;                               /**< Working Buffer Field Setting, offset: 0x84 */
    __IO uint32_t CLR;                               /**< Working Buffer Field Setting, offset: 0x88 */
    __IO uint32_t TOG;                               /**< Working Buffer Field Setting, offset: 0x8C */
  } WB_FIELD2;
  struct {                                         /* offset: 0x90 */
    __IO uint32_t RW;                                /**< Working Buffer Field Setting, offset: 0x90 */
    __IO uint32_t SET;                               /**< Working Buffer Field Setting, offset: 0x94 */
    __IO uint32_t CLR;                               /**< Working Buffer Field Setting, offset: 0x98 */
    __IO uint32_t TOG;                               /**< Working Buffer Field Setting, offset: 0x9C */
  } WB_FIELD3;
  struct {                                         /* offset: 0xA0 */
    __IO uint32_t RW;                                /**< FIFO control register, offset: 0xA0 */
    __IO uint32_t SET;                               /**< FIFO control register, offset: 0xA4 */
    __IO uint32_t CLR;                               /**< FIFO control register, offset: 0xA8 */
    __IO uint32_t TOG;                               /**< FIFO control register, offset: 0xAC */
  } FIFOCTRL;
       uint8_t RESERVED_4[80];
  __IO uint32_t UPD_ADDR;                          /**< Update Region Address, offset: 0x100 */
       uint8_t RESERVED_5[12];
  __IO uint32_t UPD_STRIDE;                        /**< Update Region Stride, offset: 0x110 */
       uint8_t RESERVED_6[12];
  __IO uint32_t UPD_CORD;                          /**< Update Command Co-ordinate, offset: 0x120 */
       uint8_t RESERVED_7[28];
  __IO uint32_t UPD_SIZE;                          /**< Update Command Size, offset: 0x140 */
       uint8_t RESERVED_8[28];
  struct {                                         /* offset: 0x160 */
    __IO uint32_t RW;                                /**< Update Command Control, offset: 0x160 */
    __IO uint32_t SET;                               /**< Update Command Control, offset: 0x164 */
    __IO uint32_t CLR;                               /**< Update Command Control, offset: 0x168 */
    __IO uint32_t TOG;                               /**< Update Command Control, offset: 0x16C */
  } UPD_CTRL;
       uint8_t RESERVED_9[16];
  struct {                                         /* offset: 0x180 */
    __IO uint32_t RW;                                /**< Update Fixed Pixel Control, offset: 0x180 */
    __IO uint32_t SET;                               /**< Update Fixed Pixel Control, offset: 0x184 */
    __IO uint32_t CLR;                               /**< Update Fixed Pixel Control, offset: 0x188 */
    __IO uint32_t TOG;                               /**< Update Fixed Pixel Control, offset: 0x18C */
  } UPD_FIXED;
       uint8_t RESERVED_10[16];
  __IO uint32_t TEMP;                              /**< Temperature Register, offset: 0x1A0 */
       uint8_t RESERVED_11[28];
  __IO uint32_t AUTOWV_LUT;                        /**< Waveform Mode Lookup Table Control Register., offset: 0x1C0 */
       uint8_t RESERVED_12[28];
  struct {                                         /* offset: 0x1E0 */
    __IO uint32_t RW;                                /**< LUT Standby Register for LUT 31~0, offset: 0x1E0 */
    __IO uint32_t SET;                               /**< LUT Standby Register for LUT 31~0, offset: 0x1E4 */
    __IO uint32_t CLR;                               /**< LUT Standby Register for LUT 31~0, offset: 0x1E8 */
    __IO uint32_t TOG;                               /**< LUT Standby Register for LUT 31~0, offset: 0x1EC */
  } LUT_STANDBY1;
  struct {                                         /* offset: 0x1F0 */
    __IO uint32_t RW;                                /**< LUT Standby Registerr for LUT 63~32, offset: 0x1F0 */
    __IO uint32_t SET;                               /**< LUT Standby Registerr for LUT 63~32, offset: 0x1F4 */
    __IO uint32_t CLR;                               /**< LUT Standby Registerr for LUT 63~32, offset: 0x1F8 */
    __IO uint32_t TOG;                               /**< LUT Standby Registerr for LUT 63~32, offset: 0x1FC */
  } LUT_STANDBY2;
  struct {                                         /* offset: 0x200 */
    __IO uint32_t RW;                                /**< Timing Control Engine Control Register, offset: 0x200 */
    __IO uint32_t SET;                               /**< Timing Control Engine Control Register, offset: 0x204 */
    __IO uint32_t CLR;                               /**< Timing Control Engine Control Register, offset: 0x208 */
    __IO uint32_t TOG;                               /**< Timing Control Engine Control Register, offset: 0x20C */
  } TCE_CTRL;
       uint8_t RESERVED_13[16];
  struct {                                         /* offset: 0x220 */
    __IO uint32_t RW;                                /**< Timing Control Engine Source-Driver Config Register, offset: 0x220 */
    __IO uint32_t SET;                               /**< Timing Control Engine Source-Driver Config Register, offset: 0x224 */
    __IO uint32_t CLR;                               /**< Timing Control Engine Source-Driver Config Register, offset: 0x228 */
    __IO uint32_t TOG;                               /**< Timing Control Engine Source-Driver Config Register, offset: 0x22C */
  } TCE_SDCFG;
       uint8_t RESERVED_14[16];
  struct {                                         /* offset: 0x240 */
    __IO uint32_t RW;                                /**< Timing Control Engine Gate-Driver Config Register, offset: 0x240 */
    __IO uint32_t SET;                               /**< Timing Control Engine Gate-Driver Config Register, offset: 0x244 */
    __IO uint32_t CLR;                               /**< Timing Control Engine Gate-Driver Config Register, offset: 0x248 */
    __IO uint32_t TOG;                               /**< Timing Control Engine Gate-Driver Config Register, offset: 0x24C */
  } TCE_GDCFG;
       uint8_t RESERVED_15[16];
  struct {                                         /* offset: 0x260 */
    __IO uint32_t RW;                                /**< Timing Control Engine Horizontal Timing Register 1, offset: 0x260 */
    __IO uint32_t SET;                               /**< Timing Control Engine Horizontal Timing Register 1, offset: 0x264 */
    __IO uint32_t CLR;                               /**< Timing Control Engine Horizontal Timing Register 1, offset: 0x268 */
    __IO uint32_t TOG;                               /**< Timing Control Engine Horizontal Timing Register 1, offset: 0x26C */
  } TCE_HSCAN1;
       uint8_t RESERVED_16[16];
  struct {                                         /* offset: 0x280 */
    __IO uint32_t RW;                                /**< Timing Control Engine Horizontal Timing Register 2, offset: 0x280 */
    __IO uint32_t SET;                               /**< Timing Control Engine Horizontal Timing Register 2, offset: 0x284 */
    __IO uint32_t CLR;                               /**< Timing Control Engine Horizontal Timing Register 2, offset: 0x288 */
    __IO uint32_t TOG;                               /**< Timing Control Engine Horizontal Timing Register 2, offset: 0x28C */
  } TCE_HSCAN2;
       uint8_t RESERVED_17[16];
  struct {                                         /* offset: 0x2A0 */
    __IO uint32_t RW;                                /**< Timing Control Engine Vertical Timing Register, offset: 0x2A0 */
    __IO uint32_t SET;                               /**< Timing Control Engine Vertical Timing Register, offset: 0x2A4 */
    __IO uint32_t CLR;                               /**< Timing Control Engine Vertical Timing Register, offset: 0x2A8 */
    __IO uint32_t TOG;                               /**< Timing Control Engine Vertical Timing Register, offset: 0x2AC */
  } TCE_VSCAN;
       uint8_t RESERVED_18[16];
  struct {                                         /* offset: 0x2C0 */
    __IO uint32_t RW;                                /**< Timing Control Engine OE timing control Register, offset: 0x2C0 */
    __IO uint32_t SET;                               /**< Timing Control Engine OE timing control Register, offset: 0x2C4 */
    __IO uint32_t CLR;                               /**< Timing Control Engine OE timing control Register, offset: 0x2C8 */
    __IO uint32_t TOG;                               /**< Timing Control Engine OE timing control Register, offset: 0x2CC */
  } TCE_OE;
       uint8_t RESERVED_19[16];
  struct {                                         /* offset: 0x2E0 */
    __IO uint32_t RW;                                /**< Timing Control Engine Driver Polarity Register, offset: 0x2E0 */
    __IO uint32_t SET;                               /**< Timing Control Engine Driver Polarity Register, offset: 0x2E4 */
    __IO uint32_t CLR;                               /**< Timing Control Engine Driver Polarity Register, offset: 0x2E8 */
    __IO uint32_t TOG;                               /**< Timing Control Engine Driver Polarity Register, offset: 0x2EC */
  } TCE_POLARITY;
       uint8_t RESERVED_20[16];
  struct {                                         /* offset: 0x300 */
    __IO uint32_t RW;                                /**< Timing Control Engine Timing Register 1, offset: 0x300 */
    __IO uint32_t SET;                               /**< Timing Control Engine Timing Register 1, offset: 0x304 */
    __IO uint32_t CLR;                               /**< Timing Control Engine Timing Register 1, offset: 0x308 */
    __IO uint32_t TOG;                               /**< Timing Control Engine Timing Register 1, offset: 0x30C */
  } TCE_TIMING1;
  struct {                                         /* offset: 0x310 */
    __IO uint32_t RW;                                /**< Timing Control Engine Timing Register 2, offset: 0x310 */
    __IO uint32_t SET;                               /**< Timing Control Engine Timing Register 2, offset: 0x314 */
    __IO uint32_t CLR;                               /**< Timing Control Engine Timing Register 2, offset: 0x318 */
    __IO uint32_t TOG;                               /**< Timing Control Engine Timing Register 2, offset: 0x31C */
  } TCE_TIMING2;
  struct {                                         /* offset: 0x320 */
    __IO uint32_t RW;                                /**< Timing Control Engine Timing Register 3, offset: 0x320 */
    __IO uint32_t SET;                               /**< Timing Control Engine Timing Register 3, offset: 0x324 */
    __IO uint32_t CLR;                               /**< Timing Control Engine Timing Register 3, offset: 0x328 */
    __IO uint32_t TOG;                               /**< Timing Control Engine Timing Register 3, offset: 0x32C */
  } TCE_TIMING3;
       uint8_t RESERVED_21[80];
  struct {                                         /* offset: 0x380 */
    __IO uint32_t RW;                                /**< Pigeon Mode Control Register 0, offset: 0x380 */
    __IO uint32_t SET;                               /**< Pigeon Mode Control Register 0, offset: 0x384 */
    __IO uint32_t CLR;                               /**< Pigeon Mode Control Register 0, offset: 0x388 */
    __IO uint32_t TOG;                               /**< Pigeon Mode Control Register 0, offset: 0x38C */
  } PIGEON_CTRL0;
  struct {                                         /* offset: 0x390 */
    __IO uint32_t RW;                                /**< Pigeon Mode Control Register 1, offset: 0x390 */
    __IO uint32_t SET;                               /**< Pigeon Mode Control Register 1, offset: 0x394 */
    __IO uint32_t CLR;                               /**< Pigeon Mode Control Register 1, offset: 0x398 */
    __IO uint32_t TOG;                               /**< Pigeon Mode Control Register 1, offset: 0x39C */
  } PIGEON_CTRL1;
       uint8_t RESERVED_22[32];
  struct {                                         /* offset: 0x3C0 */
    __IO uint32_t RW;                                /**< IRQ Mask Register for LUT 0~31, offset: 0x3C0 */
    __IO uint32_t SET;                               /**< IRQ Mask Register for LUT 0~31, offset: 0x3C4 */
    __IO uint32_t CLR;                               /**< IRQ Mask Register for LUT 0~31, offset: 0x3C8 */
    __IO uint32_t TOG;                               /**< IRQ Mask Register for LUT 0~31, offset: 0x3CC */
  } IRQ_MASK1;
  struct {                                         /* offset: 0x3D0 */
    __IO uint32_t RW;                                /**< IRQ Mask Register for LUT 32~63, offset: 0x3D0 */
    __IO uint32_t SET;                               /**< IRQ Mask Register for LUT 32~63, offset: 0x3D4 */
    __IO uint32_t CLR;                               /**< IRQ Mask Register for LUT 32~63, offset: 0x3D8 */
    __IO uint32_t TOG;                               /**< IRQ Mask Register for LUT 32~63, offset: 0x3DC */
  } IRQ_MASK2;
  struct {                                         /* offset: 0x3E0 */
    __IO uint32_t RW;                                /**< Interrupt Register for LUT 0~31, offset: 0x3E0 */
    __IO uint32_t SET;                               /**< Interrupt Register for LUT 0~31, offset: 0x3E4 */
    __IO uint32_t CLR;                               /**< Interrupt Register for LUT 0~31, offset: 0x3E8 */
    __IO uint32_t TOG;                               /**< Interrupt Register for LUT 0~31, offset: 0x3EC */
  } IRQ1;
  struct {                                         /* offset: 0x3F0 */
    __IO uint32_t RW;                                /**< Interrupt Registerr for LUT 32~63, offset: 0x3F0 */
    __IO uint32_t SET;                               /**< Interrupt Registerr for LUT 32~63, offset: 0x3F4 */
    __IO uint32_t CLR;                               /**< Interrupt Registerr for LUT 32~63, offset: 0x3F8 */
    __IO uint32_t TOG;                               /**< Interrupt Registerr for LUT 32~63, offset: 0x3FC */
  } IRQ2;
  struct {                                         /* offset: 0x400 */
    __IO uint32_t RW;                                /**< IRQ Mask Register, offset: 0x400 */
    __IO uint32_t SET;                               /**< IRQ Mask Register, offset: 0x404 */
    __IO uint32_t CLR;                               /**< IRQ Mask Register, offset: 0x408 */
    __IO uint32_t TOG;                               /**< IRQ Mask Register, offset: 0x40C */
  } IRQ_MASK;
       uint8_t RESERVED_23[16];
  struct {                                         /* offset: 0x420 */
    __IO uint32_t RW;                                /**< Interrupt Register, offset: 0x420 */
    __IO uint32_t SET;                               /**< Interrupt Register, offset: 0x424 */
    __IO uint32_t CLR;                               /**< Interrupt Register, offset: 0x428 */
    __IO uint32_t TOG;                               /**< Interrupt Register, offset: 0x42C */
  } IRQ;
       uint8_t RESERVED_24[16];
  struct {                                         /* offset: 0x440 */
    __I  uint32_t RW;                                /**< Status Register - LUTs, offset: 0x440 */
    __I  uint32_t SET;                               /**< Status Register - LUTs, offset: 0x444 */
    __I  uint32_t CLR;                               /**< Status Register - LUTs, offset: 0x448 */
    __I  uint32_t TOG;                               /**< Status Register - LUTs, offset: 0x44C */
  } STATUS_LUTS1;
  struct {                                         /* offset: 0x450 */
    __I  uint32_t RW;                                /**< Status Register - LUTs, offset: 0x450 */
    __I  uint32_t SET;                               /**< Status Register - LUTs, offset: 0x454 */
    __I  uint32_t CLR;                               /**< Status Register - LUTs, offset: 0x458 */
    __I  uint32_t TOG;                               /**< Status Register - LUTs, offset: 0x45C */
  } STATUS_LUTS2;
  __I  uint32_t STATUS_NEXTLUT;                    /**< Status Register - Next Available LUT, offset: 0x460 */
       uint8_t RESERVED_25[28];
  struct {                                         /* offset: 0x480 */
    __I  uint32_t RW;                                /**< LUT Collision Status, offset: 0x480 */
    __I  uint32_t SET;                               /**< LUT Collision Status, offset: 0x484 */
    __I  uint32_t CLR;                               /**< LUT Collision Status, offset: 0x488 */
    __I  uint32_t TOG;                               /**< LUT Collision Status, offset: 0x48C */
  } STATUS_COL1;
  struct {                                         /* offset: 0x490 */
    __I  uint32_t RW;                                /**< LUT Collision Status, offset: 0x490 */
    __I  uint32_t SET;                               /**< LUT Collision Status, offset: 0x494 */
    __I  uint32_t CLR;                               /**< LUT Collision Status, offset: 0x498 */
    __I  uint32_t TOG;                               /**< LUT Collision Status, offset: 0x49C */
  } STATUS_COL2;
  struct {                                         /* offset: 0x4A0 */
    __IO uint32_t RW;                                /**< General Status Register, offset: 0x4A0 */
    __IO uint32_t SET;                               /**< General Status Register, offset: 0x4A4 */
    __IO uint32_t CLR;                               /**< General Status Register, offset: 0x4A8 */
    __IO uint32_t TOG;                               /**< General Status Register, offset: 0x4AC */
  } STATUS;
       uint8_t RESERVED_26[16];
  __I  uint32_t UPD_COL_CORD;                      /**< Collision Region Co-ordinate, offset: 0x4C0 */
       uint8_t RESERVED_27[28];
  __I  uint32_t UPD_COL_SIZE;                      /**< Collision Region Size, offset: 0x4E0 */
       uint8_t RESERVED_28[284];
  __IO uint32_t HIST1_PARAM;                       /**< 1-level Histogram Parameter Register., offset: 0x600 */
       uint8_t RESERVED_29[12];
  __IO uint32_t HIST2_PARAM;                       /**< 2-level Histogram Parameter Register., offset: 0x610 */
       uint8_t RESERVED_30[12];
  __IO uint32_t HIST4_PARAM;                       /**< 4-level Histogram Parameter Register., offset: 0x620 */
       uint8_t RESERVED_31[12];
  __IO uint32_t HIST8_PARAM0;                      /**< 8-level Histogram Parameter 0 Register., offset: 0x630 */
       uint8_t RESERVED_32[12];
  __IO uint32_t HIST8_PARAM1;                      /**< 8-level Histogram Parameter 1 Register., offset: 0x640 */
       uint8_t RESERVED_33[12];
  __IO uint32_t HIST16_PARAM0;                     /**< 16-level Histogram Parameter 0 Register., offset: 0x650 */
       uint8_t RESERVED_34[12];
  __IO uint32_t HIST16_PARAM1;                     /**< 16-level Histogram Parameter Register., offset: 0x660 */
       uint8_t RESERVED_35[12];
  __IO uint32_t HIST16_PARAM2;                     /**< 16-level Histogram Parameter Register., offset: 0x670 */
       uint8_t RESERVED_36[12];
  __IO uint32_t HIST16_PARAM3;                     /**< 16-level Histogram Parameter Register., offset: 0x680 */
       uint8_t RESERVED_37[124];
  struct {                                         /* offset: 0x700 */
    __IO uint32_t RW;                                /**< General Purpose I/O Debug register, offset: 0x700 */
    __IO uint32_t SET;                               /**< General Purpose I/O Debug register, offset: 0x704 */
    __IO uint32_t CLR;                               /**< General Purpose I/O Debug register, offset: 0x708 */
    __IO uint32_t TOG;                               /**< General Purpose I/O Debug register, offset: 0x70C */
  } GPIO;
       uint8_t RESERVED_38[224];
  __I  uint32_t VERSION;                           /**< Version Register, offset: 0x7F0 */
       uint8_t RESERVED_39[12];
  struct {                                         /* offset: 0x800, array step: 0x40 */
    __IO uint32_t PIGEON_0;                          /**< Panel Interface Signal Generator Register 0_0..Panel Interface Signal Generator Register 16_0, array offset: 0x800, array step: 0x40 */
         uint8_t RESERVED_0[12];
    __IO uint32_t PIGEON_1;                          /**< Panel Interface Signal Generator Register 0_1..Panel Interface Signal Generator Register 16_1, array offset: 0x810, array step: 0x40 */
         uint8_t RESERVED_1[12];
    __IO uint32_t PIGEON_2;                          /**< Panel Interface Signal Generator Register 0_2..Panel Interface Signal Generator Register 16_2, array offset: 0x820, array step: 0x40 */
         uint8_t RESERVED_2[28];
  } PIGEON_X[17];
} EPDC_Type;

/* ----------------------------------------------------------------------------
   -- EPDC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup EPDC_Register_Masks EPDC Register Masks
 * @{
 */

/*! @name CTRL - Control Register */
/*! @{ */

#define EPDC_CTRL_LUT_DATA_SWIZZLE_MASK          (0x30U)
#define EPDC_CTRL_LUT_DATA_SWIZZLE_SHIFT         (4U)
/*! LUT_DATA_SWIZZLE
 *  0b00..No byte swapping.(Little endian)
 *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
 *  0b10..Swap half-words.
 *  0b11..Swap bytes within each half-word.
 */
#define EPDC_CTRL_LUT_DATA_SWIZZLE(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_CTRL_LUT_DATA_SWIZZLE_SHIFT)) & EPDC_CTRL_LUT_DATA_SWIZZLE_MASK)

#define EPDC_CTRL_UPD_DATA_SWIZZLE_MASK          (0xC0U)
#define EPDC_CTRL_UPD_DATA_SWIZZLE_SHIFT         (6U)
/*! UPD_DATA_SWIZZLE
 *  0b00..No byte swapping.(Little endian)
 *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
 *  0b10..Swap half-words.
 *  0b11..Swap bytes within each half-word.
 */
#define EPDC_CTRL_UPD_DATA_SWIZZLE(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_CTRL_UPD_DATA_SWIZZLE_SHIFT)) & EPDC_CTRL_UPD_DATA_SWIZZLE_MASK)

#define EPDC_CTRL_LUT_STATE_SW_RESET_EN_MASK     (0x10000000U)
#define EPDC_CTRL_LUT_STATE_SW_RESET_EN_SHIFT    (28U)
#define EPDC_CTRL_LUT_STATE_SW_RESET_EN(x)       (((uint32_t)(((uint32_t)(x)) << EPDC_CTRL_LUT_STATE_SW_RESET_EN_SHIFT)) & EPDC_CTRL_LUT_STATE_SW_RESET_EN_MASK)

#define EPDC_CTRL_FRAME_CLEAR_EN_MASK            (0x20000000U)
#define EPDC_CTRL_FRAME_CLEAR_EN_SHIFT           (29U)
#define EPDC_CTRL_FRAME_CLEAR_EN(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_CTRL_FRAME_CLEAR_EN_SHIFT)) & EPDC_CTRL_FRAME_CLEAR_EN_MASK)

#define EPDC_CTRL_CLKGATE_MASK                   (0x40000000U)
#define EPDC_CTRL_CLKGATE_SHIFT                  (30U)
#define EPDC_CTRL_CLKGATE(x)                     (((uint32_t)(((uint32_t)(x)) << EPDC_CTRL_CLKGATE_SHIFT)) & EPDC_CTRL_CLKGATE_MASK)

#define EPDC_CTRL_SFTRST_MASK                    (0x80000000U)
#define EPDC_CTRL_SFTRST_SHIFT                   (31U)
#define EPDC_CTRL_SFTRST(x)                      (((uint32_t)(((uint32_t)(x)) << EPDC_CTRL_SFTRST_SHIFT)) & EPDC_CTRL_SFTRST_MASK)
/*! @} */

/*! @name WB_ADDR_TCE - Working Buffer Address for TCE */
/*! @{ */

#define EPDC_WB_ADDR_TCE_ADDR_MASK               (0xFFFFFFFFU)
#define EPDC_WB_ADDR_TCE_ADDR_SHIFT              (0U)
#define EPDC_WB_ADDR_TCE_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_WB_ADDR_TCE_ADDR_SHIFT)) & EPDC_WB_ADDR_TCE_ADDR_MASK)
/*! @} */

/*! @name WVADDR - Waveform Address Pointer */
/*! @{ */

#define EPDC_WVADDR_ADDR_MASK                    (0xFFFFFFFFU)
#define EPDC_WVADDR_ADDR_SHIFT                   (0U)
#define EPDC_WVADDR_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << EPDC_WVADDR_ADDR_SHIFT)) & EPDC_WVADDR_ADDR_MASK)
/*! @} */

/*! @name WB_ADDR - Working Buffer Address */
/*! @{ */

#define EPDC_WB_ADDR_ADDR_MASK                   (0xFFFFFFFFU)
#define EPDC_WB_ADDR_ADDR_SHIFT                  (0U)
#define EPDC_WB_ADDR_ADDR(x)                     (((uint32_t)(((uint32_t)(x)) << EPDC_WB_ADDR_ADDR_SHIFT)) & EPDC_WB_ADDR_ADDR_MASK)
/*! @} */

/*! @name RES - Screen Resolution */
/*! @{ */

#define EPDC_RES_HORIZONTAL_MASK                 (0x1FFFU)
#define EPDC_RES_HORIZONTAL_SHIFT                (0U)
#define EPDC_RES_HORIZONTAL(x)                   (((uint32_t)(((uint32_t)(x)) << EPDC_RES_HORIZONTAL_SHIFT)) & EPDC_RES_HORIZONTAL_MASK)

#define EPDC_RES_VERTICAL_MASK                   (0x1FFF0000U)
#define EPDC_RES_VERTICAL_SHIFT                  (16U)
#define EPDC_RES_VERTICAL(x)                     (((uint32_t)(((uint32_t)(x)) << EPDC_RES_VERTICAL_SHIFT)) & EPDC_RES_VERTICAL_MASK)
/*! @} */

/*! @name FORMAT - Format Control Register */
/*! @{ */

#define EPDC_FORMAT_TFT_PIXEL_FORMAT_MASK        (0x3U)
#define EPDC_FORMAT_TFT_PIXEL_FORMAT_SHIFT       (0U)
/*! TFT_PIXEL_FORMAT
 *  0b00..2-bit
 *  0b01..2-bit and VCOM
 *  0b10..4-bit
 *  0b11..4-bit and VCOM
 */
#define EPDC_FORMAT_TFT_PIXEL_FORMAT(x)          (((uint32_t)(((uint32_t)(x)) << EPDC_FORMAT_TFT_PIXEL_FORMAT_SHIFT)) & EPDC_FORMAT_TFT_PIXEL_FORMAT_MASK)

#define EPDC_FORMAT_WB_COMPRESS_MASK             (0x800U)
#define EPDC_FORMAT_WB_COMPRESS_SHIFT            (11U)
#define EPDC_FORMAT_WB_COMPRESS(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_FORMAT_WB_COMPRESS_SHIFT)) & EPDC_FORMAT_WB_COMPRESS_MASK)

#define EPDC_FORMAT_WB_TYPE_MASK                 (0x3000U)
#define EPDC_FORMAT_WB_TYPE_SHIFT                (12U)
/*! WB_TYPE
 *  0b00..internal Working Buffer written by EPDC itself
 *  0b01..working buffer is actually holding waveform
 *  0b10..16bit working buffer written by PXP or CPU
 *  0b11..32bit working buffer written by PXP or CPU
 */
#define EPDC_FORMAT_WB_TYPE(x)                   (((uint32_t)(((uint32_t)(x)) << EPDC_FORMAT_WB_TYPE_SHIFT)) & EPDC_FORMAT_WB_TYPE_MASK)

#define EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK       (0xFF0000U)
#define EPDC_FORMAT_DEFAULT_TFT_PIXEL_SHIFT      (16U)
#define EPDC_FORMAT_DEFAULT_TFT_PIXEL(x)         (((uint32_t)(((uint32_t)(x)) << EPDC_FORMAT_DEFAULT_TFT_PIXEL_SHIFT)) & EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK)

#define EPDC_FORMAT_BUF_PIXEL_SCALE_MASK         (0x1000000U)
#define EPDC_FORMAT_BUF_PIXEL_SCALE_SHIFT        (24U)
/*! BUF_PIXEL_SCALE
 *  0b0..Use Truncate method (LSB)
 *  0b1..Use rounding method (with saturation)
 */
#define EPDC_FORMAT_BUF_PIXEL_SCALE(x)           (((uint32_t)(((uint32_t)(x)) << EPDC_FORMAT_BUF_PIXEL_SCALE_SHIFT)) & EPDC_FORMAT_BUF_PIXEL_SCALE_MASK)
/*! @} */

/*! @name WB_FIELD0 - Working Buffer Field Setting */
/*! @{ */

#define EPDC_WB_FIELD0_LEN_MASK                  (0xFU)
#define EPDC_WB_FIELD0_LEN_SHIFT                 (0U)
#define EPDC_WB_FIELD0_LEN(x)                    (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD0_LEN_SHIFT)) & EPDC_WB_FIELD0_LEN_MASK)

#define EPDC_WB_FIELD0_TO_MASK                   (0xF0U)
#define EPDC_WB_FIELD0_TO_SHIFT                  (4U)
#define EPDC_WB_FIELD0_TO(x)                     (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD0_TO_SHIFT)) & EPDC_WB_FIELD0_TO_MASK)

#define EPDC_WB_FIELD0_FROM_MASK                 (0x1F00U)
#define EPDC_WB_FIELD0_FROM_SHIFT                (8U)
#define EPDC_WB_FIELD0_FROM(x)                   (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD0_FROM_SHIFT)) & EPDC_WB_FIELD0_FROM_MASK)

#define EPDC_WB_FIELD0_USAGE_MASK                (0xE000U)
#define EPDC_WB_FIELD0_USAGE_SHIFT               (13U)
/*! USAGE
 *  0b000..NOT USED
 *  0b011..PARTIAL (won't contribute to lut lookup index)
 *  0b100..LUT
 *  0b101..CP
 *  0b110..NP
 *  0b111..PTS
 */
#define EPDC_WB_FIELD0_USAGE(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD0_USAGE_SHIFT)) & EPDC_WB_FIELD0_USAGE_MASK)

#define EPDC_WB_FIELD0_USE_FIXED_MASK            (0x30000U)
#define EPDC_WB_FIELD0_USE_FIXED_SHIFT           (16U)
/*! USE_FIXED
 *  0b00..not using FIXED field
 *  0b01..set this field to a FIXED value which specified by FIXED[31:24]
 *  0b10..mask off this pixel if this field is non equal to FIXED[31:24]
 *  0b11..mask off this pixel if this field is equal to FIXED[31:24]
 */
#define EPDC_WB_FIELD0_USE_FIXED(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD0_USE_FIXED_SHIFT)) & EPDC_WB_FIELD0_USE_FIXED_MASK)

#define EPDC_WB_FIELD0_FIXED_MASK                (0xFF000000U)
#define EPDC_WB_FIELD0_FIXED_SHIFT               (24U)
#define EPDC_WB_FIELD0_FIXED(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD0_FIXED_SHIFT)) & EPDC_WB_FIELD0_FIXED_MASK)
/*! @} */

/*! @name WB_FIELD1 - Working Buffer Field Setting */
/*! @{ */

#define EPDC_WB_FIELD1_LEN_MASK                  (0xFU)
#define EPDC_WB_FIELD1_LEN_SHIFT                 (0U)
#define EPDC_WB_FIELD1_LEN(x)                    (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD1_LEN_SHIFT)) & EPDC_WB_FIELD1_LEN_MASK)

#define EPDC_WB_FIELD1_TO_MASK                   (0xF0U)
#define EPDC_WB_FIELD1_TO_SHIFT                  (4U)
#define EPDC_WB_FIELD1_TO(x)                     (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD1_TO_SHIFT)) & EPDC_WB_FIELD1_TO_MASK)

#define EPDC_WB_FIELD1_FROM_MASK                 (0x1F00U)
#define EPDC_WB_FIELD1_FROM_SHIFT                (8U)
#define EPDC_WB_FIELD1_FROM(x)                   (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD1_FROM_SHIFT)) & EPDC_WB_FIELD1_FROM_MASK)

#define EPDC_WB_FIELD1_USAGE_MASK                (0xE000U)
#define EPDC_WB_FIELD1_USAGE_SHIFT               (13U)
/*! USAGE
 *  0b000..NOT USED
 *  0b011..PARTIAL
 *  0b100..LUT
 *  0b101..CP
 *  0b110..NP
 *  0b111..PTS
 */
#define EPDC_WB_FIELD1_USAGE(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD1_USAGE_SHIFT)) & EPDC_WB_FIELD1_USAGE_MASK)

#define EPDC_WB_FIELD1_USE_FIXED_MASK            (0x30000U)
#define EPDC_WB_FIELD1_USE_FIXED_SHIFT           (16U)
/*! USE_FIXED
 *  0b00..not using FIXED field
 *  0b01..set this field to a FIXED value which specified by FIXED[31:24]
 *  0b10..mask off this pixel if this field is non equal to FIXED[31:24]
 *  0b11..mask off this pixel if this field is equal to FIXED[31:24]
 */
#define EPDC_WB_FIELD1_USE_FIXED(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD1_USE_FIXED_SHIFT)) & EPDC_WB_FIELD1_USE_FIXED_MASK)

#define EPDC_WB_FIELD1_FIXED_MASK                (0xFF000000U)
#define EPDC_WB_FIELD1_FIXED_SHIFT               (24U)
#define EPDC_WB_FIELD1_FIXED(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD1_FIXED_SHIFT)) & EPDC_WB_FIELD1_FIXED_MASK)
/*! @} */

/*! @name WB_FIELD2 - Working Buffer Field Setting */
/*! @{ */

#define EPDC_WB_FIELD2_LEN_MASK                  (0xFU)
#define EPDC_WB_FIELD2_LEN_SHIFT                 (0U)
#define EPDC_WB_FIELD2_LEN(x)                    (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD2_LEN_SHIFT)) & EPDC_WB_FIELD2_LEN_MASK)

#define EPDC_WB_FIELD2_TO_MASK                   (0xF0U)
#define EPDC_WB_FIELD2_TO_SHIFT                  (4U)
#define EPDC_WB_FIELD2_TO(x)                     (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD2_TO_SHIFT)) & EPDC_WB_FIELD2_TO_MASK)

#define EPDC_WB_FIELD2_FROM_MASK                 (0x1F00U)
#define EPDC_WB_FIELD2_FROM_SHIFT                (8U)
#define EPDC_WB_FIELD2_FROM(x)                   (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD2_FROM_SHIFT)) & EPDC_WB_FIELD2_FROM_MASK)

#define EPDC_WB_FIELD2_USAGE_MASK                (0xE000U)
#define EPDC_WB_FIELD2_USAGE_SHIFT               (13U)
/*! USAGE
 *  0b000..NOT USED
 *  0b011..PARTIAL
 *  0b100..LUT
 *  0b101..CP
 *  0b110..NP
 *  0b111..PTS
 */
#define EPDC_WB_FIELD2_USAGE(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD2_USAGE_SHIFT)) & EPDC_WB_FIELD2_USAGE_MASK)

#define EPDC_WB_FIELD2_USE_FIXED_MASK            (0x30000U)
#define EPDC_WB_FIELD2_USE_FIXED_SHIFT           (16U)
/*! USE_FIXED
 *  0b00..not using FIXED field
 *  0b01..set this field to a FIXED value which specified by FIXED[31:24]
 *  0b10..mask off this pixel if this field is non equal to FIXED[31:24]
 *  0b11..mask off this pixel if this field is equal to FIXED[31:24]
 */
#define EPDC_WB_FIELD2_USE_FIXED(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD2_USE_FIXED_SHIFT)) & EPDC_WB_FIELD2_USE_FIXED_MASK)

#define EPDC_WB_FIELD2_FIXED_MASK                (0xFF000000U)
#define EPDC_WB_FIELD2_FIXED_SHIFT               (24U)
#define EPDC_WB_FIELD2_FIXED(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD2_FIXED_SHIFT)) & EPDC_WB_FIELD2_FIXED_MASK)
/*! @} */

/*! @name WB_FIELD3 - Working Buffer Field Setting */
/*! @{ */

#define EPDC_WB_FIELD3_LEN_MASK                  (0xFU)
#define EPDC_WB_FIELD3_LEN_SHIFT                 (0U)
#define EPDC_WB_FIELD3_LEN(x)                    (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD3_LEN_SHIFT)) & EPDC_WB_FIELD3_LEN_MASK)

#define EPDC_WB_FIELD3_TO_MASK                   (0xF0U)
#define EPDC_WB_FIELD3_TO_SHIFT                  (4U)
#define EPDC_WB_FIELD3_TO(x)                     (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD3_TO_SHIFT)) & EPDC_WB_FIELD3_TO_MASK)

#define EPDC_WB_FIELD3_FROM_MASK                 (0x1F00U)
#define EPDC_WB_FIELD3_FROM_SHIFT                (8U)
#define EPDC_WB_FIELD3_FROM(x)                   (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD3_FROM_SHIFT)) & EPDC_WB_FIELD3_FROM_MASK)

#define EPDC_WB_FIELD3_USAGE_MASK                (0xE000U)
#define EPDC_WB_FIELD3_USAGE_SHIFT               (13U)
/*! USAGE
 *  0b000..NOT USED
 *  0b011..PARTIAL
 *  0b100..LUT
 *  0b101..CP
 *  0b110..NP
 *  0b111..PTS
 */
#define EPDC_WB_FIELD3_USAGE(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD3_USAGE_SHIFT)) & EPDC_WB_FIELD3_USAGE_MASK)

#define EPDC_WB_FIELD3_USE_FIXED_MASK            (0x30000U)
#define EPDC_WB_FIELD3_USE_FIXED_SHIFT           (16U)
/*! USE_FIXED
 *  0b00..not using FIXED field
 *  0b01..set this field to a FIXED value which specified by FIXED[31:24]
 *  0b10..mask off this pixel if this field is non equal to FIXED[31:24]
 *  0b11..mask off this pixel if this field is equal to FIXED[31:24]
 */
#define EPDC_WB_FIELD3_USE_FIXED(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD3_USE_FIXED_SHIFT)) & EPDC_WB_FIELD3_USE_FIXED_MASK)

#define EPDC_WB_FIELD3_FIXED_MASK                (0xFF000000U)
#define EPDC_WB_FIELD3_FIXED_SHIFT               (24U)
#define EPDC_WB_FIELD3_FIXED(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_WB_FIELD3_FIXED_SHIFT)) & EPDC_WB_FIELD3_FIXED_MASK)
/*! @} */

/*! @name FIFOCTRL - FIFO control register */
/*! @{ */

#define EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK          (0x3FFU)
#define EPDC_FIFOCTRL_FIFO_L_LEVEL_SHIFT         (0U)
#define EPDC_FIFOCTRL_FIFO_L_LEVEL(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_FIFOCTRL_FIFO_L_LEVEL_SHIFT)) & EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK)

#define EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK          (0xFFC00U)
#define EPDC_FIFOCTRL_FIFO_H_LEVEL_SHIFT         (10U)
#define EPDC_FIFOCTRL_FIFO_H_LEVEL(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_FIFOCTRL_FIFO_H_LEVEL_SHIFT)) & EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK)

#define EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK       (0x3FF00000U)
#define EPDC_FIFOCTRL_FIFO_INIT_LEVEL_SHIFT      (20U)
#define EPDC_FIFOCTRL_FIFO_INIT_LEVEL(x)         (((uint32_t)(((uint32_t)(x)) << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_SHIFT)) & EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK)

#define EPDC_FIFOCTRL_ENABLE_PRIORITY_MASK       (0x80000000U)
#define EPDC_FIFOCTRL_ENABLE_PRIORITY_SHIFT      (31U)
#define EPDC_FIFOCTRL_ENABLE_PRIORITY(x)         (((uint32_t)(((uint32_t)(x)) << EPDC_FIFOCTRL_ENABLE_PRIORITY_SHIFT)) & EPDC_FIFOCTRL_ENABLE_PRIORITY_MASK)
/*! @} */

/*! @name UPD_ADDR - Update Region Address */
/*! @{ */

#define EPDC_UPD_ADDR_ADDR_MASK                  (0xFFFFFFFFU)
#define EPDC_UPD_ADDR_ADDR_SHIFT                 (0U)
#define EPDC_UPD_ADDR_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_ADDR_ADDR_SHIFT)) & EPDC_UPD_ADDR_ADDR_MASK)
/*! @} */

/*! @name UPD_STRIDE - Update Region Stride */
/*! @{ */

#define EPDC_UPD_STRIDE_STRIDE_MASK              (0xFFFFFFFFU)
#define EPDC_UPD_STRIDE_STRIDE_SHIFT             (0U)
#define EPDC_UPD_STRIDE_STRIDE(x)                (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_STRIDE_STRIDE_SHIFT)) & EPDC_UPD_STRIDE_STRIDE_MASK)
/*! @} */

/*! @name UPD_CORD - Update Command Co-ordinate */
/*! @{ */

#define EPDC_UPD_CORD_XCORD_MASK                 (0x1FFFU)
#define EPDC_UPD_CORD_XCORD_SHIFT                (0U)
#define EPDC_UPD_CORD_XCORD(x)                   (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_CORD_XCORD_SHIFT)) & EPDC_UPD_CORD_XCORD_MASK)

#define EPDC_UPD_CORD_YCORD_MASK                 (0x1FFF0000U)
#define EPDC_UPD_CORD_YCORD_SHIFT                (16U)
#define EPDC_UPD_CORD_YCORD(x)                   (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_CORD_YCORD_SHIFT)) & EPDC_UPD_CORD_YCORD_MASK)
/*! @} */

/*! @name UPD_SIZE - Update Command Size */
/*! @{ */

#define EPDC_UPD_SIZE_WIDTH_MASK                 (0x1FFFU)
#define EPDC_UPD_SIZE_WIDTH_SHIFT                (0U)
#define EPDC_UPD_SIZE_WIDTH(x)                   (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_SIZE_WIDTH_SHIFT)) & EPDC_UPD_SIZE_WIDTH_MASK)

#define EPDC_UPD_SIZE_HEIGHT_MASK                (0x1FFF0000U)
#define EPDC_UPD_SIZE_HEIGHT_SHIFT               (16U)
#define EPDC_UPD_SIZE_HEIGHT(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_SIZE_HEIGHT_SHIFT)) & EPDC_UPD_SIZE_HEIGHT_MASK)
/*! @} */

/*! @name UPD_CTRL - Update Command Control */
/*! @{ */

#define EPDC_UPD_CTRL_UPDATE_MODE_MASK           (0x1U)
#define EPDC_UPD_CTRL_UPDATE_MODE_SHIFT          (0U)
/*! UPDATE_MODE
 *  0b0..Partial Update : only process changed pixels in region
 *  0b1..Full Update : process all pixels in region
 */
#define EPDC_UPD_CTRL_UPDATE_MODE(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_CTRL_UPDATE_MODE_SHIFT)) & EPDC_UPD_CTRL_UPDATE_MODE_MASK)

#define EPDC_UPD_CTRL_DRY_RUN_MASK               (0x2U)
#define EPDC_UPD_CTRL_DRY_RUN_SHIFT              (1U)
#define EPDC_UPD_CTRL_DRY_RUN(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_CTRL_DRY_RUN_SHIFT)) & EPDC_UPD_CTRL_DRY_RUN_MASK)

#define EPDC_UPD_CTRL_AUTOWV_MASK                (0x4U)
#define EPDC_UPD_CTRL_AUTOWV_SHIFT               (2U)
#define EPDC_UPD_CTRL_AUTOWV(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_CTRL_AUTOWV_SHIFT)) & EPDC_UPD_CTRL_AUTOWV_MASK)

#define EPDC_UPD_CTRL_PAUSE_MASK                 (0x8U)
#define EPDC_UPD_CTRL_PAUSE_SHIFT                (3U)
/*! PAUSE
 *  0b0..will analyze update buffer, report histogram, then update waveform mode using the programmed mode mapping
 *       in AUTOWV_LUT and start LUT loading
 *  0b1..EPDC analyzes and updates buffer, reports histogram, then pauses and waits for the software to write
 *       again with selected waveform mode to start lut loading
 */
#define EPDC_UPD_CTRL_PAUSE(x)                   (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_CTRL_PAUSE_SHIFT)) & EPDC_UPD_CTRL_PAUSE_MASK)

#define EPDC_UPD_CTRL_NO_LUT_CANCEL_MASK         (0x10U)
#define EPDC_UPD_CTRL_NO_LUT_CANCEL_SHIFT        (4U)
#define EPDC_UPD_CTRL_NO_LUT_CANCEL(x)           (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_CTRL_NO_LUT_CANCEL_SHIFT)) & EPDC_UPD_CTRL_NO_LUT_CANCEL_MASK)

#define EPDC_UPD_CTRL_STANDBY_MASK               (0x20U)
#define EPDC_UPD_CTRL_STANDBY_SHIFT              (5U)
#define EPDC_UPD_CTRL_STANDBY(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_CTRL_STANDBY_SHIFT)) & EPDC_UPD_CTRL_STANDBY_MASK)

#define EPDC_UPD_CTRL_WAVEFORM_MODE_MASK         (0xFF00U)
#define EPDC_UPD_CTRL_WAVEFORM_MODE_SHIFT        (8U)
#define EPDC_UPD_CTRL_WAVEFORM_MODE(x)           (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_CTRL_WAVEFORM_MODE_SHIFT)) & EPDC_UPD_CTRL_WAVEFORM_MODE_MASK)

#define EPDC_UPD_CTRL_LUT_SEL_MASK               (0x3F0000U)
#define EPDC_UPD_CTRL_LUT_SEL_SHIFT              (16U)
#define EPDC_UPD_CTRL_LUT_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_CTRL_LUT_SEL_SHIFT)) & EPDC_UPD_CTRL_LUT_SEL_MASK)

#define EPDC_UPD_CTRL_USE_FIXED_MASK             (0x80000000U)
#define EPDC_UPD_CTRL_USE_FIXED_SHIFT            (31U)
#define EPDC_UPD_CTRL_USE_FIXED(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_CTRL_USE_FIXED_SHIFT)) & EPDC_UPD_CTRL_USE_FIXED_MASK)
/*! @} */

/*! @name UPD_FIXED - Update Fixed Pixel Control */
/*! @{ */

#define EPDC_UPD_FIXED_FIXCP_MASK                (0xFFU)
#define EPDC_UPD_FIXED_FIXCP_SHIFT               (0U)
#define EPDC_UPD_FIXED_FIXCP(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_FIXED_FIXCP_SHIFT)) & EPDC_UPD_FIXED_FIXCP_MASK)

#define EPDC_UPD_FIXED_FIXNP_MASK                (0xFF00U)
#define EPDC_UPD_FIXED_FIXNP_SHIFT               (8U)
#define EPDC_UPD_FIXED_FIXNP(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_FIXED_FIXNP_SHIFT)) & EPDC_UPD_FIXED_FIXNP_MASK)

#define EPDC_UPD_FIXED_FIXCP_EN_MASK             (0x40000000U)
#define EPDC_UPD_FIXED_FIXCP_EN_SHIFT            (30U)
#define EPDC_UPD_FIXED_FIXCP_EN(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_FIXED_FIXCP_EN_SHIFT)) & EPDC_UPD_FIXED_FIXCP_EN_MASK)

#define EPDC_UPD_FIXED_FIXNP_EN_MASK             (0x80000000U)
#define EPDC_UPD_FIXED_FIXNP_EN_SHIFT            (31U)
#define EPDC_UPD_FIXED_FIXNP_EN(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_FIXED_FIXNP_EN_SHIFT)) & EPDC_UPD_FIXED_FIXNP_EN_MASK)
/*! @} */

/*! @name TEMP - Temperature Register */
/*! @{ */

#define EPDC_TEMP_TEMPERATURE_MASK               (0xFFFFFFFFU)
#define EPDC_TEMP_TEMPERATURE_SHIFT              (0U)
#define EPDC_TEMP_TEMPERATURE(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_TEMP_TEMPERATURE_SHIFT)) & EPDC_TEMP_TEMPERATURE_MASK)
/*! @} */

/*! @name AUTOWV_LUT - Waveform Mode Lookup Table Control Register. */
/*! @{ */

#define EPDC_AUTOWV_LUT_ADDR_MASK                (0x7U)
#define EPDC_AUTOWV_LUT_ADDR_SHIFT               (0U)
#define EPDC_AUTOWV_LUT_ADDR(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_AUTOWV_LUT_ADDR_SHIFT)) & EPDC_AUTOWV_LUT_ADDR_MASK)

#define EPDC_AUTOWV_LUT_DATA_MASK                (0xFF0000U)
#define EPDC_AUTOWV_LUT_DATA_SHIFT               (16U)
#define EPDC_AUTOWV_LUT_DATA(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_AUTOWV_LUT_DATA_SHIFT)) & EPDC_AUTOWV_LUT_DATA_MASK)
/*! @} */

/*! @name LUT_STANDBY1 - LUT Standby Register for LUT 31~0 */
/*! @{ */

#define EPDC_LUT_STANDBY1_LUTN_MASK              (0xFFFFFFFFU)
#define EPDC_LUT_STANDBY1_LUTN_SHIFT             (0U)
#define EPDC_LUT_STANDBY1_LUTN(x)                (((uint32_t)(((uint32_t)(x)) << EPDC_LUT_STANDBY1_LUTN_SHIFT)) & EPDC_LUT_STANDBY1_LUTN_MASK)
/*! @} */

/*! @name LUT_STANDBY2 - LUT Standby Registerr for LUT 63~32 */
/*! @{ */

#define EPDC_LUT_STANDBY2_LUTN_MASK              (0xFFFFFFFFU)
#define EPDC_LUT_STANDBY2_LUTN_SHIFT             (0U)
#define EPDC_LUT_STANDBY2_LUTN(x)                (((uint32_t)(((uint32_t)(x)) << EPDC_LUT_STANDBY2_LUTN_SHIFT)) & EPDC_LUT_STANDBY2_LUTN_MASK)
/*! @} */

/*! @name TCE_CTRL - Timing Control Engine Control Register */
/*! @{ */

#define EPDC_TCE_CTRL_PIXELS_PER_SDCLK_MASK      (0x3U)
#define EPDC_TCE_CTRL_PIXELS_PER_SDCLK_SHIFT     (0U)
/*! PIXELS_PER_SDCLK
 *  0b00..Reserved
 *  0b01..Two TFT-pixels per SDCLK
 *  0b10..Four TFT-pixels per SDCLK
 *  0b11..Eight TFT-pixels per SDCLK
 */
#define EPDC_TCE_CTRL_PIXELS_PER_SDCLK(x)        (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_CTRL_PIXELS_PER_SDCLK_SHIFT)) & EPDC_TCE_CTRL_PIXELS_PER_SDCLK_MASK)

#define EPDC_TCE_CTRL_SDDO_WIDTH_MASK            (0x4U)
#define EPDC_TCE_CTRL_SDDO_WIDTH_SHIFT           (2U)
/*! SDDO_WIDTH
 *  0b0..Connect to 8-bit source driver
 *  0b1..Connct to 16-bit source driver
 */
#define EPDC_TCE_CTRL_SDDO_WIDTH(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_CTRL_SDDO_WIDTH_SHIFT)) & EPDC_TCE_CTRL_SDDO_WIDTH_MASK)

#define EPDC_TCE_CTRL_DUAL_SCAN_MASK             (0x8U)
#define EPDC_TCE_CTRL_DUAL_SCAN_SHIFT            (3U)
#define EPDC_TCE_CTRL_DUAL_SCAN(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_CTRL_DUAL_SCAN_SHIFT)) & EPDC_TCE_CTRL_DUAL_SCAN_MASK)

#define EPDC_TCE_CTRL_SCAN_DIR_0_MASK            (0x10U)
#define EPDC_TCE_CTRL_SCAN_DIR_0_SHIFT           (4U)
/*! SCAN_DIR_0
 *  0b1..Scan this region from bottom to top
 *  0b0..Scan this region from top to bottom
 */
#define EPDC_TCE_CTRL_SCAN_DIR_0(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_CTRL_SCAN_DIR_0_SHIFT)) & EPDC_TCE_CTRL_SCAN_DIR_0_MASK)

#define EPDC_TCE_CTRL_SCAN_DIR_1_MASK            (0x20U)
#define EPDC_TCE_CTRL_SCAN_DIR_1_SHIFT           (5U)
/*! SCAN_DIR_1
 *  0b1..Scan this region from bottom to top
 *  0b0..Scan this region from top to bottom
 */
#define EPDC_TCE_CTRL_SCAN_DIR_1(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_CTRL_SCAN_DIR_1_SHIFT)) & EPDC_TCE_CTRL_SCAN_DIR_1_MASK)

#define EPDC_TCE_CTRL_LVDS_MODE_MASK             (0x40U)
#define EPDC_TCE_CTRL_LVDS_MODE_SHIFT            (6U)
#define EPDC_TCE_CTRL_LVDS_MODE(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_CTRL_LVDS_MODE_SHIFT)) & EPDC_TCE_CTRL_LVDS_MODE_MASK)

#define EPDC_TCE_CTRL_LVDS_MODE_CE_MASK          (0x80U)
#define EPDC_TCE_CTRL_LVDS_MODE_CE_SHIFT         (7U)
#define EPDC_TCE_CTRL_LVDS_MODE_CE(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_CTRL_LVDS_MODE_CE_SHIFT)) & EPDC_TCE_CTRL_LVDS_MODE_CE_MASK)

#define EPDC_TCE_CTRL_DDR_MODE_MASK              (0x100U)
#define EPDC_TCE_CTRL_DDR_MODE_SHIFT             (8U)
#define EPDC_TCE_CTRL_DDR_MODE(x)                (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_CTRL_DDR_MODE_SHIFT)) & EPDC_TCE_CTRL_DDR_MODE_MASK)

#define EPDC_TCE_CTRL_VCOM_MODE_MASK             (0x200U)
#define EPDC_TCE_CTRL_VCOM_MODE_SHIFT            (9U)
/*! VCOM_MODE
 *  0b0..VCOM Value is set manually using VCOM_VAL field
 *  0b1..VCOM Value is used from waveform
 */
#define EPDC_TCE_CTRL_VCOM_MODE(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_CTRL_VCOM_MODE_SHIFT)) & EPDC_TCE_CTRL_VCOM_MODE_MASK)

#define EPDC_TCE_CTRL_VCOM_VAL_MASK              (0xC00U)
#define EPDC_TCE_CTRL_VCOM_VAL_SHIFT             (10U)
#define EPDC_TCE_CTRL_VCOM_VAL(x)                (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_CTRL_VCOM_VAL_SHIFT)) & EPDC_TCE_CTRL_VCOM_VAL_MASK)

#define EPDC_TCE_CTRL_WB_EXTERNAL_RANGE_EN_MASK  (0x1000U)
#define EPDC_TCE_CTRL_WB_EXTERNAL_RANGE_EN_SHIFT (12U)
#define EPDC_TCE_CTRL_WB_EXTERNAL_RANGE_EN(x)    (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_CTRL_WB_EXTERNAL_RANGE_EN_SHIFT)) & EPDC_TCE_CTRL_WB_EXTERNAL_RANGE_EN_MASK)

#define EPDC_TCE_CTRL_UNDERRUN_LOOKUP_MASK_EN_MASK (0x2000U)
#define EPDC_TCE_CTRL_UNDERRUN_LOOKUP_MASK_EN_SHIFT (13U)
#define EPDC_TCE_CTRL_UNDERRUN_LOOKUP_MASK_EN(x) (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_CTRL_UNDERRUN_LOOKUP_MASK_EN_SHIFT)) & EPDC_TCE_CTRL_UNDERRUN_LOOKUP_MASK_EN_MASK)

#define EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK         (0x1FF0000U)
#define EPDC_TCE_CTRL_VSCAN_HOLDOFF_SHIFT        (16U)
#define EPDC_TCE_CTRL_VSCAN_HOLDOFF(x)           (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_CTRL_VSCAN_HOLDOFF_SHIFT)) & EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK)
/*! @} */

/*! @name TCE_SDCFG - Timing Control Engine Source-Driver Config Register */
/*! @{ */

#define EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK        (0x1FFFU)
#define EPDC_TCE_SDCFG_PIXELS_PER_CE_SHIFT       (0U)
#define EPDC_TCE_SDCFG_PIXELS_PER_CE(x)          (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_SDCFG_PIXELS_PER_CE_SHIFT)) & EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK)

#define EPDC_TCE_SDCFG_SDDO_INVERT_MASK          (0x2000U)
#define EPDC_TCE_SDCFG_SDDO_INVERT_SHIFT         (13U)
#define EPDC_TCE_SDCFG_SDDO_INVERT(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_SDCFG_SDDO_INVERT_SHIFT)) & EPDC_TCE_SDCFG_SDDO_INVERT_MASK)

#define EPDC_TCE_SDCFG_SDDO_REFORMAT_MASK        (0xC000U)
#define EPDC_TCE_SDCFG_SDDO_REFORMAT_SHIFT       (14U)
/*! SDDO_REFORMAT
 *  0b00..No change.
 *  0b01..Reverses the order of the pixels on SDDO. This register setting is sensitive to the TFT pixel width
 *        (TFT_PIXEL_FORMAT), e.g. for TFT_PIXEL_FORMAT=2B on an 8-bit bus P3,P2,P1,P0 becomes P0,P1,P2,P3, whereas
 *        with TFT_PIXEL_FORMAT=4B, on an 8-bit bus, P1,P0 becomes P0,P1
 */
#define EPDC_TCE_SDCFG_SDDO_REFORMAT(x)          (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_SDCFG_SDDO_REFORMAT_SHIFT)) & EPDC_TCE_SDCFG_SDDO_REFORMAT_MASK)

#define EPDC_TCE_SDCFG_NUM_CE_MASK               (0xF0000U)
#define EPDC_TCE_SDCFG_NUM_CE_SHIFT              (16U)
#define EPDC_TCE_SDCFG_NUM_CE(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_SDCFG_NUM_CE_SHIFT)) & EPDC_TCE_SDCFG_NUM_CE_MASK)

#define EPDC_TCE_SDCFG_SDSHR_MASK                (0x100000U)
#define EPDC_TCE_SDCFG_SDSHR_SHIFT               (20U)
#define EPDC_TCE_SDCFG_SDSHR(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_SDCFG_SDSHR_SHIFT)) & EPDC_TCE_SDCFG_SDSHR_MASK)

#define EPDC_TCE_SDCFG_SDCLK_HOLD_MASK           (0x200000U)
#define EPDC_TCE_SDCFG_SDCLK_HOLD_SHIFT          (21U)
#define EPDC_TCE_SDCFG_SDCLK_HOLD(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_SDCFG_SDCLK_HOLD_SHIFT)) & EPDC_TCE_SDCFG_SDCLK_HOLD_MASK)
/*! @} */

/*! @name TCE_GDCFG - Timing Control Engine Gate-Driver Config Register */
/*! @{ */

#define EPDC_TCE_GDCFG_GDSP_MODE_MASK            (0x1U)
#define EPDC_TCE_GDCFG_GDSP_MODE_SHIFT           (0U)
#define EPDC_TCE_GDCFG_GDSP_MODE(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_GDCFG_GDSP_MODE_SHIFT)) & EPDC_TCE_GDCFG_GDSP_MODE_MASK)

#define EPDC_TCE_GDCFG_GDOE_MODE_MASK            (0x2U)
#define EPDC_TCE_GDCFG_GDOE_MODE_SHIFT           (1U)
#define EPDC_TCE_GDCFG_GDOE_MODE(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_GDCFG_GDOE_MODE_SHIFT)) & EPDC_TCE_GDCFG_GDOE_MODE_MASK)

#define EPDC_TCE_GDCFG_GDRL_MASK                 (0x10U)
#define EPDC_TCE_GDCFG_GDRL_SHIFT                (4U)
#define EPDC_TCE_GDCFG_GDRL(x)                   (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_GDCFG_GDRL_SHIFT)) & EPDC_TCE_GDCFG_GDRL_MASK)

#define EPDC_TCE_GDCFG_PERIOD_VSCAN_MASK         (0xFFFF0000U)
#define EPDC_TCE_GDCFG_PERIOD_VSCAN_SHIFT        (16U)
#define EPDC_TCE_GDCFG_PERIOD_VSCAN(x)           (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_GDCFG_PERIOD_VSCAN_SHIFT)) & EPDC_TCE_GDCFG_PERIOD_VSCAN_MASK)
/*! @} */

/*! @name TCE_HSCAN1 - Timing Control Engine Horizontal Timing Register 1 */
/*! @{ */

#define EPDC_TCE_HSCAN1_LINE_SYNC_MASK           (0xFFFU)
#define EPDC_TCE_HSCAN1_LINE_SYNC_SHIFT          (0U)
#define EPDC_TCE_HSCAN1_LINE_SYNC(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_HSCAN1_LINE_SYNC_SHIFT)) & EPDC_TCE_HSCAN1_LINE_SYNC_MASK)

#define EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK     (0xFFF0000U)
#define EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_SHIFT    (16U)
#define EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_SHIFT)) & EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK)
/*! @} */

/*! @name TCE_HSCAN2 - Timing Control Engine Horizontal Timing Register 2 */
/*! @{ */

#define EPDC_TCE_HSCAN2_LINE_BEGIN_MASK          (0xFFFU)
#define EPDC_TCE_HSCAN2_LINE_BEGIN_SHIFT         (0U)
#define EPDC_TCE_HSCAN2_LINE_BEGIN(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_HSCAN2_LINE_BEGIN_SHIFT)) & EPDC_TCE_HSCAN2_LINE_BEGIN_MASK)

#define EPDC_TCE_HSCAN2_LINE_END_MASK            (0xFFF0000U)
#define EPDC_TCE_HSCAN2_LINE_END_SHIFT           (16U)
#define EPDC_TCE_HSCAN2_LINE_END(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_HSCAN2_LINE_END_SHIFT)) & EPDC_TCE_HSCAN2_LINE_END_MASK)
/*! @} */

/*! @name TCE_VSCAN - Timing Control Engine Vertical Timing Register */
/*! @{ */

#define EPDC_TCE_VSCAN_FRAME_SYNC_MASK           (0xFFU)
#define EPDC_TCE_VSCAN_FRAME_SYNC_SHIFT          (0U)
#define EPDC_TCE_VSCAN_FRAME_SYNC(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_VSCAN_FRAME_SYNC_SHIFT)) & EPDC_TCE_VSCAN_FRAME_SYNC_MASK)

#define EPDC_TCE_VSCAN_FRAME_BEGIN_MASK          (0xFF00U)
#define EPDC_TCE_VSCAN_FRAME_BEGIN_SHIFT         (8U)
#define EPDC_TCE_VSCAN_FRAME_BEGIN(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_VSCAN_FRAME_BEGIN_SHIFT)) & EPDC_TCE_VSCAN_FRAME_BEGIN_MASK)

#define EPDC_TCE_VSCAN_FRAME_END_MASK            (0xFF0000U)
#define EPDC_TCE_VSCAN_FRAME_END_SHIFT           (16U)
#define EPDC_TCE_VSCAN_FRAME_END(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_VSCAN_FRAME_END_SHIFT)) & EPDC_TCE_VSCAN_FRAME_END_MASK)
/*! @} */

/*! @name TCE_OE - Timing Control Engine OE timing control Register */
/*! @{ */

#define EPDC_TCE_OE_SDOEZ_DLY_MASK               (0xFFU)
#define EPDC_TCE_OE_SDOEZ_DLY_SHIFT              (0U)
#define EPDC_TCE_OE_SDOEZ_DLY(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_OE_SDOEZ_DLY_SHIFT)) & EPDC_TCE_OE_SDOEZ_DLY_MASK)

#define EPDC_TCE_OE_SDOEZ_WIDTH_MASK             (0xFF00U)
#define EPDC_TCE_OE_SDOEZ_WIDTH_SHIFT            (8U)
#define EPDC_TCE_OE_SDOEZ_WIDTH(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_OE_SDOEZ_WIDTH_SHIFT)) & EPDC_TCE_OE_SDOEZ_WIDTH_MASK)

#define EPDC_TCE_OE_SDOED_DLY_MASK               (0xFF0000U)
#define EPDC_TCE_OE_SDOED_DLY_SHIFT              (16U)
#define EPDC_TCE_OE_SDOED_DLY(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_OE_SDOED_DLY_SHIFT)) & EPDC_TCE_OE_SDOED_DLY_MASK)

#define EPDC_TCE_OE_SDOED_WIDTH_MASK             (0xFF000000U)
#define EPDC_TCE_OE_SDOED_WIDTH_SHIFT            (24U)
#define EPDC_TCE_OE_SDOED_WIDTH(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_OE_SDOED_WIDTH_SHIFT)) & EPDC_TCE_OE_SDOED_WIDTH_MASK)
/*! @} */

/*! @name TCE_POLARITY - Timing Control Engine Driver Polarity Register */
/*! @{ */

#define EPDC_TCE_POLARITY_SDCE_POL_MASK          (0x1U)
#define EPDC_TCE_POLARITY_SDCE_POL_SHIFT         (0U)
#define EPDC_TCE_POLARITY_SDCE_POL(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_POLARITY_SDCE_POL_SHIFT)) & EPDC_TCE_POLARITY_SDCE_POL_MASK)

#define EPDC_TCE_POLARITY_SDLE_POL_MASK          (0x2U)
#define EPDC_TCE_POLARITY_SDLE_POL_SHIFT         (1U)
#define EPDC_TCE_POLARITY_SDLE_POL(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_POLARITY_SDLE_POL_SHIFT)) & EPDC_TCE_POLARITY_SDLE_POL_MASK)

#define EPDC_TCE_POLARITY_SDOE_POL_MASK          (0x4U)
#define EPDC_TCE_POLARITY_SDOE_POL_SHIFT         (2U)
#define EPDC_TCE_POLARITY_SDOE_POL(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_POLARITY_SDOE_POL_SHIFT)) & EPDC_TCE_POLARITY_SDOE_POL_MASK)

#define EPDC_TCE_POLARITY_GDOE_POL_MASK          (0x8U)
#define EPDC_TCE_POLARITY_GDOE_POL_SHIFT         (3U)
#define EPDC_TCE_POLARITY_GDOE_POL(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_POLARITY_GDOE_POL_SHIFT)) & EPDC_TCE_POLARITY_GDOE_POL_MASK)

#define EPDC_TCE_POLARITY_GDSP_POL_MASK          (0x10U)
#define EPDC_TCE_POLARITY_GDSP_POL_SHIFT         (4U)
#define EPDC_TCE_POLARITY_GDSP_POL(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_POLARITY_GDSP_POL_SHIFT)) & EPDC_TCE_POLARITY_GDSP_POL_MASK)
/*! @} */

/*! @name TCE_TIMING1 - Timing Control Engine Timing Register 1 */
/*! @{ */

#define EPDC_TCE_TIMING1_SDCLK_SHIFT_MASK        (0x3U)
#define EPDC_TCE_TIMING1_SDCLK_SHIFT_SHIFT       (0U)
/*! SDCLK_SHIFT
 *  0b00..No shift of SDCLK
 *  0b01..Shift SDCLK 1 pixclk cycle
 *  0b10..Shift SDCLK 2 pixclk cycles
 *  0b11..Shift SDCLK 3 pixclk cycles
 */
#define EPDC_TCE_TIMING1_SDCLK_SHIFT(x)          (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_TIMING1_SDCLK_SHIFT_SHIFT)) & EPDC_TCE_TIMING1_SDCLK_SHIFT_MASK)

#define EPDC_TCE_TIMING1_SDCLK_INVERT_MASK       (0x8U)
#define EPDC_TCE_TIMING1_SDCLK_INVERT_SHIFT      (3U)
#define EPDC_TCE_TIMING1_SDCLK_INVERT(x)         (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_TIMING1_SDCLK_INVERT_SHIFT)) & EPDC_TCE_TIMING1_SDCLK_INVERT_MASK)

#define EPDC_TCE_TIMING1_SDLE_SHIFT_MASK         (0x30U)
#define EPDC_TCE_TIMING1_SDLE_SHIFT_SHIFT        (4U)
/*! SDLE_SHIFT
 *  0b00..No shift of SDLE
 *  0b01..Shift SDLE 1 pixclk cycle
 *  0b10..Shift SDLE 2 pixclk cycles
 *  0b11..Shift SDLE 3 pixclk cycles
 */
#define EPDC_TCE_TIMING1_SDLE_SHIFT(x)           (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_TIMING1_SDLE_SHIFT_SHIFT)) & EPDC_TCE_TIMING1_SDLE_SHIFT_MASK)
/*! @} */

/*! @name TCE_TIMING2 - Timing Control Engine Timing Register 2 */
/*! @{ */

#define EPDC_TCE_TIMING2_GDSP_OFFSET_MASK        (0xFFFFU)
#define EPDC_TCE_TIMING2_GDSP_OFFSET_SHIFT       (0U)
#define EPDC_TCE_TIMING2_GDSP_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_TIMING2_GDSP_OFFSET_SHIFT)) & EPDC_TCE_TIMING2_GDSP_OFFSET_MASK)

#define EPDC_TCE_TIMING2_GDCLK_HP_MASK           (0xFFFF0000U)
#define EPDC_TCE_TIMING2_GDCLK_HP_SHIFT          (16U)
#define EPDC_TCE_TIMING2_GDCLK_HP(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_TIMING2_GDCLK_HP_SHIFT)) & EPDC_TCE_TIMING2_GDCLK_HP_MASK)
/*! @} */

/*! @name TCE_TIMING3 - Timing Control Engine Timing Register 3 */
/*! @{ */

#define EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK       (0xFFFFU)
#define EPDC_TCE_TIMING3_GDCLK_OFFSET_SHIFT      (0U)
#define EPDC_TCE_TIMING3_GDCLK_OFFSET(x)         (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_TIMING3_GDCLK_OFFSET_SHIFT)) & EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK)

#define EPDC_TCE_TIMING3_GDOE_OFFSET_MASK        (0xFFFF0000U)
#define EPDC_TCE_TIMING3_GDOE_OFFSET_SHIFT       (16U)
#define EPDC_TCE_TIMING3_GDOE_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << EPDC_TCE_TIMING3_GDOE_OFFSET_SHIFT)) & EPDC_TCE_TIMING3_GDOE_OFFSET_MASK)
/*! @} */

/*! @name PIGEON_CTRL0 - Pigeon Mode Control Register 0 */
/*! @{ */

#define EPDC_PIGEON_CTRL0_FD_PERIOD_MASK         (0xFFFU)
#define EPDC_PIGEON_CTRL0_FD_PERIOD_SHIFT        (0U)
#define EPDC_PIGEON_CTRL0_FD_PERIOD(x)           (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_CTRL0_FD_PERIOD_SHIFT)) & EPDC_PIGEON_CTRL0_FD_PERIOD_MASK)

#define EPDC_PIGEON_CTRL0_LD_PERIOD_MASK         (0xFFF0000U)
#define EPDC_PIGEON_CTRL0_LD_PERIOD_SHIFT        (16U)
#define EPDC_PIGEON_CTRL0_LD_PERIOD(x)           (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_CTRL0_LD_PERIOD_SHIFT)) & EPDC_PIGEON_CTRL0_LD_PERIOD_MASK)
/*! @} */

/*! @name PIGEON_CTRL1 - Pigeon Mode Control Register 1 */
/*! @{ */

#define EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD_MASK  (0xFFFU)
#define EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
#define EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD(x)    (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD_SHIFT)) & EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD_MASK)

#define EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES_MASK  (0xFFF0000U)
#define EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
#define EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES(x)    (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES_SHIFT)) & EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES_MASK)
/*! @} */

/*! @name IRQ_MASK1 - IRQ Mask Register for LUT 0~31 */
/*! @{ */

#define EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN_MASK    (0xFFFFFFFFU)
#define EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN_SHIFT   (0U)
#define EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN_SHIFT)) & EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN_MASK)
/*! @} */

/*! @name IRQ_MASK2 - IRQ Mask Register for LUT 32~63 */
/*! @{ */

#define EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN_MASK    (0xFFFFFFFFU)
#define EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN_SHIFT   (0U)
#define EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN_SHIFT)) & EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN_MASK)
/*! @} */

/*! @name IRQ1 - Interrupt Register for LUT 0~31 */
/*! @{ */

#define EPDC_IRQ1_LUTN_CMPLT_IRQ_MASK            (0xFFFFFFFFU)
#define EPDC_IRQ1_LUTN_CMPLT_IRQ_SHIFT           (0U)
#define EPDC_IRQ1_LUTN_CMPLT_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ1_LUTN_CMPLT_IRQ_SHIFT)) & EPDC_IRQ1_LUTN_CMPLT_IRQ_MASK)
/*! @} */

/*! @name IRQ2 - Interrupt Registerr for LUT 32~63 */
/*! @{ */

#define EPDC_IRQ2_LUTN_CMPLT_IRQ_MASK            (0xFFFFFFFFU)
#define EPDC_IRQ2_LUTN_CMPLT_IRQ_SHIFT           (0U)
#define EPDC_IRQ2_LUTN_CMPLT_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ2_LUTN_CMPLT_IRQ_SHIFT)) & EPDC_IRQ2_LUTN_CMPLT_IRQ_MASK)
/*! @} */

/*! @name IRQ_MASK - IRQ Mask Register */
/*! @{ */

#define EPDC_IRQ_MASK_WB_CMPLT_IRQ_EN_MASK       (0x10000U)
#define EPDC_IRQ_MASK_WB_CMPLT_IRQ_EN_SHIFT      (16U)
#define EPDC_IRQ_MASK_WB_CMPLT_IRQ_EN(x)         (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_MASK_WB_CMPLT_IRQ_EN_SHIFT)) & EPDC_IRQ_MASK_WB_CMPLT_IRQ_EN_MASK)

#define EPDC_IRQ_MASK_COL_IRQ_EN_MASK            (0x20000U)
#define EPDC_IRQ_MASK_COL_IRQ_EN_SHIFT           (17U)
#define EPDC_IRQ_MASK_COL_IRQ_EN(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_MASK_COL_IRQ_EN_SHIFT)) & EPDC_IRQ_MASK_COL_IRQ_EN_MASK)

#define EPDC_IRQ_MASK_TCE_UNDERRUN_IRQ_EN_MASK   (0x40000U)
#define EPDC_IRQ_MASK_TCE_UNDERRUN_IRQ_EN_SHIFT  (18U)
#define EPDC_IRQ_MASK_TCE_UNDERRUN_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_MASK_TCE_UNDERRUN_IRQ_EN_SHIFT)) & EPDC_IRQ_MASK_TCE_UNDERRUN_IRQ_EN_MASK)

#define EPDC_IRQ_MASK_FRAME_END_IRQ_EN_MASK      (0x80000U)
#define EPDC_IRQ_MASK_FRAME_END_IRQ_EN_SHIFT     (19U)
#define EPDC_IRQ_MASK_FRAME_END_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_MASK_FRAME_END_IRQ_EN_SHIFT)) & EPDC_IRQ_MASK_FRAME_END_IRQ_EN_MASK)

#define EPDC_IRQ_MASK_BUS_ERROR_IRQ_EN_MASK      (0x100000U)
#define EPDC_IRQ_MASK_BUS_ERROR_IRQ_EN_SHIFT     (20U)
#define EPDC_IRQ_MASK_BUS_ERROR_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_MASK_BUS_ERROR_IRQ_EN_SHIFT)) & EPDC_IRQ_MASK_BUS_ERROR_IRQ_EN_MASK)

#define EPDC_IRQ_MASK_TCE_IDLE_IRQ_EN_MASK       (0x200000U)
#define EPDC_IRQ_MASK_TCE_IDLE_IRQ_EN_SHIFT      (21U)
#define EPDC_IRQ_MASK_TCE_IDLE_IRQ_EN(x)         (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_MASK_TCE_IDLE_IRQ_EN_SHIFT)) & EPDC_IRQ_MASK_TCE_IDLE_IRQ_EN_MASK)

#define EPDC_IRQ_MASK_UPD_DONE_IRQ_EN_MASK       (0x400000U)
#define EPDC_IRQ_MASK_UPD_DONE_IRQ_EN_SHIFT      (22U)
#define EPDC_IRQ_MASK_UPD_DONE_IRQ_EN(x)         (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_MASK_UPD_DONE_IRQ_EN_SHIFT)) & EPDC_IRQ_MASK_UPD_DONE_IRQ_EN_MASK)

#define EPDC_IRQ_MASK_PWR_IRQ_EN_MASK            (0x800000U)
#define EPDC_IRQ_MASK_PWR_IRQ_EN_SHIFT           (23U)
#define EPDC_IRQ_MASK_PWR_IRQ_EN(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_MASK_PWR_IRQ_EN_SHIFT)) & EPDC_IRQ_MASK_PWR_IRQ_EN_MASK)
/*! @} */

/*! @name IRQ - Interrupt Register */
/*! @{ */

#define EPDC_IRQ_WB_CMPLT_IRQ_MASK               (0x10000U)
#define EPDC_IRQ_WB_CMPLT_IRQ_SHIFT              (16U)
#define EPDC_IRQ_WB_CMPLT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_WB_CMPLT_IRQ_SHIFT)) & EPDC_IRQ_WB_CMPLT_IRQ_MASK)

#define EPDC_IRQ_LUT_COL_IRQ_MASK                (0x20000U)
#define EPDC_IRQ_LUT_COL_IRQ_SHIFT               (17U)
#define EPDC_IRQ_LUT_COL_IRQ(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_LUT_COL_IRQ_SHIFT)) & EPDC_IRQ_LUT_COL_IRQ_MASK)

#define EPDC_IRQ_TCE_UNDERRUN_IRQ_MASK           (0x40000U)
#define EPDC_IRQ_TCE_UNDERRUN_IRQ_SHIFT          (18U)
#define EPDC_IRQ_TCE_UNDERRUN_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_TCE_UNDERRUN_IRQ_SHIFT)) & EPDC_IRQ_TCE_UNDERRUN_IRQ_MASK)

#define EPDC_IRQ_FRAME_END_IRQ_MASK              (0x80000U)
#define EPDC_IRQ_FRAME_END_IRQ_SHIFT             (19U)
#define EPDC_IRQ_FRAME_END_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_FRAME_END_IRQ_SHIFT)) & EPDC_IRQ_FRAME_END_IRQ_MASK)

#define EPDC_IRQ_BUS_ERROR_IRQ_MASK              (0x100000U)
#define EPDC_IRQ_BUS_ERROR_IRQ_SHIFT             (20U)
#define EPDC_IRQ_BUS_ERROR_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_BUS_ERROR_IRQ_SHIFT)) & EPDC_IRQ_BUS_ERROR_IRQ_MASK)

#define EPDC_IRQ_TCE_IDLE_IRQ_MASK               (0x200000U)
#define EPDC_IRQ_TCE_IDLE_IRQ_SHIFT              (21U)
#define EPDC_IRQ_TCE_IDLE_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_TCE_IDLE_IRQ_SHIFT)) & EPDC_IRQ_TCE_IDLE_IRQ_MASK)

#define EPDC_IRQ_UPD_DONE_IRQ_MASK               (0x400000U)
#define EPDC_IRQ_UPD_DONE_IRQ_SHIFT              (22U)
#define EPDC_IRQ_UPD_DONE_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_UPD_DONE_IRQ_SHIFT)) & EPDC_IRQ_UPD_DONE_IRQ_MASK)

#define EPDC_IRQ_PWR_IRQ_MASK                    (0x800000U)
#define EPDC_IRQ_PWR_IRQ_SHIFT                   (23U)
#define EPDC_IRQ_PWR_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << EPDC_IRQ_PWR_IRQ_SHIFT)) & EPDC_IRQ_PWR_IRQ_MASK)
/*! @} */

/*! @name STATUS_LUTS1 - Status Register - LUTs */
/*! @{ */

#define EPDC_STATUS_LUTS1_LUTN_STS_MASK          (0xFFFFFFFFU)
#define EPDC_STATUS_LUTS1_LUTN_STS_SHIFT         (0U)
#define EPDC_STATUS_LUTS1_LUTN_STS(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_STATUS_LUTS1_LUTN_STS_SHIFT)) & EPDC_STATUS_LUTS1_LUTN_STS_MASK)
/*! @} */

/*! @name STATUS_LUTS2 - Status Register - LUTs */
/*! @{ */

#define EPDC_STATUS_LUTS2_LUTN_STS_MASK          (0xFFFFFFFFU)
#define EPDC_STATUS_LUTS2_LUTN_STS_SHIFT         (0U)
#define EPDC_STATUS_LUTS2_LUTN_STS(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_STATUS_LUTS2_LUTN_STS_SHIFT)) & EPDC_STATUS_LUTS2_LUTN_STS_MASK)
/*! @} */

/*! @name STATUS_NEXTLUT - Status Register - Next Available LUT */
/*! @{ */

#define EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK        (0x3FU)
#define EPDC_STATUS_NEXTLUT_NEXT_LUT_SHIFT       (0U)
#define EPDC_STATUS_NEXTLUT_NEXT_LUT(x)          (((uint32_t)(((uint32_t)(x)) << EPDC_STATUS_NEXTLUT_NEXT_LUT_SHIFT)) & EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK)

#define EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID_MASK  (0x100U)
#define EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID_SHIFT (8U)
#define EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID(x)    (((uint32_t)(((uint32_t)(x)) << EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID_SHIFT)) & EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID_MASK)
/*! @} */

/*! @name STATUS_COL1 - LUT Collision Status */
/*! @{ */

#define EPDC_STATUS_COL1_LUTN_COL_STS_MASK       (0xFFFFFFFFU)
#define EPDC_STATUS_COL1_LUTN_COL_STS_SHIFT      (0U)
#define EPDC_STATUS_COL1_LUTN_COL_STS(x)         (((uint32_t)(((uint32_t)(x)) << EPDC_STATUS_COL1_LUTN_COL_STS_SHIFT)) & EPDC_STATUS_COL1_LUTN_COL_STS_MASK)
/*! @} */

/*! @name STATUS_COL2 - LUT Collision Status */
/*! @{ */

#define EPDC_STATUS_COL2_LUTN_COL_STS_MASK       (0xFFFFFFFFU)
#define EPDC_STATUS_COL2_LUTN_COL_STS_SHIFT      (0U)
#define EPDC_STATUS_COL2_LUTN_COL_STS(x)         (((uint32_t)(((uint32_t)(x)) << EPDC_STATUS_COL2_LUTN_COL_STS_SHIFT)) & EPDC_STATUS_COL2_LUTN_COL_STS_MASK)
/*! @} */

/*! @name STATUS - General Status Register */
/*! @{ */

#define EPDC_STATUS_WB_BUSY_MASK                 (0x1U)
#define EPDC_STATUS_WB_BUSY_SHIFT                (0U)
#define EPDC_STATUS_WB_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << EPDC_STATUS_WB_BUSY_SHIFT)) & EPDC_STATUS_WB_BUSY_MASK)

#define EPDC_STATUS_LUTS_BUSY_MASK               (0x2U)
#define EPDC_STATUS_LUTS_BUSY_SHIFT              (1U)
#define EPDC_STATUS_LUTS_BUSY(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_STATUS_LUTS_BUSY_SHIFT)) & EPDC_STATUS_LUTS_BUSY_MASK)

#define EPDC_STATUS_LUTS_UNDERRUN_MASK           (0x4U)
#define EPDC_STATUS_LUTS_UNDERRUN_SHIFT          (2U)
#define EPDC_STATUS_LUTS_UNDERRUN(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_STATUS_LUTS_UNDERRUN_SHIFT)) & EPDC_STATUS_LUTS_UNDERRUN_MASK)

#define EPDC_STATUS_UPD_VOID_MASK                (0x8U)
#define EPDC_STATUS_UPD_VOID_SHIFT               (3U)
#define EPDC_STATUS_UPD_VOID(x)                  (((uint32_t)(((uint32_t)(x)) << EPDC_STATUS_UPD_VOID_SHIFT)) & EPDC_STATUS_UPD_VOID_MASK)

#define EPDC_STATUS_HISTOGRAM_NP_MASK            (0x1F00U)
#define EPDC_STATUS_HISTOGRAM_NP_SHIFT           (8U)
#define EPDC_STATUS_HISTOGRAM_NP(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_STATUS_HISTOGRAM_NP_SHIFT)) & EPDC_STATUS_HISTOGRAM_NP_MASK)

#define EPDC_STATUS_HISTOGRAM_CP_MASK            (0x1F0000U)
#define EPDC_STATUS_HISTOGRAM_CP_SHIFT           (16U)
#define EPDC_STATUS_HISTOGRAM_CP(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_STATUS_HISTOGRAM_CP_SHIFT)) & EPDC_STATUS_HISTOGRAM_CP_MASK)
/*! @} */

/*! @name UPD_COL_CORD - Collision Region Co-ordinate */
/*! @{ */

#define EPDC_UPD_COL_CORD_XCORD_MASK             (0x1FFFU)
#define EPDC_UPD_COL_CORD_XCORD_SHIFT            (0U)
#define EPDC_UPD_COL_CORD_XCORD(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_COL_CORD_XCORD_SHIFT)) & EPDC_UPD_COL_CORD_XCORD_MASK)

#define EPDC_UPD_COL_CORD_YCORD_MASK             (0x1FFF0000U)
#define EPDC_UPD_COL_CORD_YCORD_SHIFT            (16U)
#define EPDC_UPD_COL_CORD_YCORD(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_COL_CORD_YCORD_SHIFT)) & EPDC_UPD_COL_CORD_YCORD_MASK)
/*! @} */

/*! @name UPD_COL_SIZE - Collision Region Size */
/*! @{ */

#define EPDC_UPD_COL_SIZE_WIDTH_MASK             (0x1FFFU)
#define EPDC_UPD_COL_SIZE_WIDTH_SHIFT            (0U)
#define EPDC_UPD_COL_SIZE_WIDTH(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_COL_SIZE_WIDTH_SHIFT)) & EPDC_UPD_COL_SIZE_WIDTH_MASK)

#define EPDC_UPD_COL_SIZE_HEIGHT_MASK            (0x1FFF0000U)
#define EPDC_UPD_COL_SIZE_HEIGHT_SHIFT           (16U)
#define EPDC_UPD_COL_SIZE_HEIGHT(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_UPD_COL_SIZE_HEIGHT_SHIFT)) & EPDC_UPD_COL_SIZE_HEIGHT_MASK)
/*! @} */

/*! @name HIST1_PARAM - 1-level Histogram Parameter Register. */
/*! @{ */

#define EPDC_HIST1_PARAM_VALUE0_MASK             (0x1FU)
#define EPDC_HIST1_PARAM_VALUE0_SHIFT            (0U)
#define EPDC_HIST1_PARAM_VALUE0(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_HIST1_PARAM_VALUE0_SHIFT)) & EPDC_HIST1_PARAM_VALUE0_MASK)

#define EPDC_HIST1_PARAM_RSVD_MASK               (0xFFFFFFE0U)
#define EPDC_HIST1_PARAM_RSVD_SHIFT              (5U)
#define EPDC_HIST1_PARAM_RSVD(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_HIST1_PARAM_RSVD_SHIFT)) & EPDC_HIST1_PARAM_RSVD_MASK)
/*! @} */

/*! @name HIST2_PARAM - 2-level Histogram Parameter Register. */
/*! @{ */

#define EPDC_HIST2_PARAM_VALUE0_MASK             (0x1FU)
#define EPDC_HIST2_PARAM_VALUE0_SHIFT            (0U)
#define EPDC_HIST2_PARAM_VALUE0(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_HIST2_PARAM_VALUE0_SHIFT)) & EPDC_HIST2_PARAM_VALUE0_MASK)

#define EPDC_HIST2_PARAM_VALUE1_MASK             (0x1F00U)
#define EPDC_HIST2_PARAM_VALUE1_SHIFT            (8U)
#define EPDC_HIST2_PARAM_VALUE1(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_HIST2_PARAM_VALUE1_SHIFT)) & EPDC_HIST2_PARAM_VALUE1_MASK)

#define EPDC_HIST2_PARAM_RSVD_MASK               (0xFFFF0000U)
#define EPDC_HIST2_PARAM_RSVD_SHIFT              (16U)
#define EPDC_HIST2_PARAM_RSVD(x)                 (((uint32_t)(((uint32_t)(x)) << EPDC_HIST2_PARAM_RSVD_SHIFT)) & EPDC_HIST2_PARAM_RSVD_MASK)
/*! @} */

/*! @name HIST4_PARAM - 4-level Histogram Parameter Register. */
/*! @{ */

#define EPDC_HIST4_PARAM_VALUE0_MASK             (0x1FU)
#define EPDC_HIST4_PARAM_VALUE0_SHIFT            (0U)
#define EPDC_HIST4_PARAM_VALUE0(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_HIST4_PARAM_VALUE0_SHIFT)) & EPDC_HIST4_PARAM_VALUE0_MASK)

#define EPDC_HIST4_PARAM_VALUE1_MASK             (0x1F00U)
#define EPDC_HIST4_PARAM_VALUE1_SHIFT            (8U)
#define EPDC_HIST4_PARAM_VALUE1(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_HIST4_PARAM_VALUE1_SHIFT)) & EPDC_HIST4_PARAM_VALUE1_MASK)

#define EPDC_HIST4_PARAM_VALUE2_MASK             (0x1F0000U)
#define EPDC_HIST4_PARAM_VALUE2_SHIFT            (16U)
#define EPDC_HIST4_PARAM_VALUE2(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_HIST4_PARAM_VALUE2_SHIFT)) & EPDC_HIST4_PARAM_VALUE2_MASK)

#define EPDC_HIST4_PARAM_VALUE3_MASK             (0x1F000000U)
#define EPDC_HIST4_PARAM_VALUE3_SHIFT            (24U)
#define EPDC_HIST4_PARAM_VALUE3(x)               (((uint32_t)(((uint32_t)(x)) << EPDC_HIST4_PARAM_VALUE3_SHIFT)) & EPDC_HIST4_PARAM_VALUE3_MASK)
/*! @} */

/*! @name HIST8_PARAM0 - 8-level Histogram Parameter 0 Register. */
/*! @{ */

#define EPDC_HIST8_PARAM0_VALUE0_MASK            (0x1FU)
#define EPDC_HIST8_PARAM0_VALUE0_SHIFT           (0U)
#define EPDC_HIST8_PARAM0_VALUE0(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_HIST8_PARAM0_VALUE0_SHIFT)) & EPDC_HIST8_PARAM0_VALUE0_MASK)

#define EPDC_HIST8_PARAM0_VALUE1_MASK            (0x1F00U)
#define EPDC_HIST8_PARAM0_VALUE1_SHIFT           (8U)
#define EPDC_HIST8_PARAM0_VALUE1(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_HIST8_PARAM0_VALUE1_SHIFT)) & EPDC_HIST8_PARAM0_VALUE1_MASK)

#define EPDC_HIST8_PARAM0_VALUE2_MASK            (0x1F0000U)
#define EPDC_HIST8_PARAM0_VALUE2_SHIFT           (16U)
#define EPDC_HIST8_PARAM0_VALUE2(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_HIST8_PARAM0_VALUE2_SHIFT)) & EPDC_HIST8_PARAM0_VALUE2_MASK)

#define EPDC_HIST8_PARAM0_VALUE3_MASK            (0x1F000000U)
#define EPDC_HIST8_PARAM0_VALUE3_SHIFT           (24U)
#define EPDC_HIST8_PARAM0_VALUE3(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_HIST8_PARAM0_VALUE3_SHIFT)) & EPDC_HIST8_PARAM0_VALUE3_MASK)
/*! @} */

/*! @name HIST8_PARAM1 - 8-level Histogram Parameter 1 Register. */
/*! @{ */

#define EPDC_HIST8_PARAM1_VALUE4_MASK            (0x1FU)
#define EPDC_HIST8_PARAM1_VALUE4_SHIFT           (0U)
#define EPDC_HIST8_PARAM1_VALUE4(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_HIST8_PARAM1_VALUE4_SHIFT)) & EPDC_HIST8_PARAM1_VALUE4_MASK)

#define EPDC_HIST8_PARAM1_VALUE5_MASK            (0x1F00U)
#define EPDC_HIST8_PARAM1_VALUE5_SHIFT           (8U)
#define EPDC_HIST8_PARAM1_VALUE5(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_HIST8_PARAM1_VALUE5_SHIFT)) & EPDC_HIST8_PARAM1_VALUE5_MASK)

#define EPDC_HIST8_PARAM1_VALUE6_MASK            (0x1F0000U)
#define EPDC_HIST8_PARAM1_VALUE6_SHIFT           (16U)
#define EPDC_HIST8_PARAM1_VALUE6(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_HIST8_PARAM1_VALUE6_SHIFT)) & EPDC_HIST8_PARAM1_VALUE6_MASK)

#define EPDC_HIST8_PARAM1_VALUE7_MASK            (0x1F000000U)
#define EPDC_HIST8_PARAM1_VALUE7_SHIFT           (24U)
#define EPDC_HIST8_PARAM1_VALUE7(x)              (((uint32_t)(((uint32_t)(x)) << EPDC_HIST8_PARAM1_VALUE7_SHIFT)) & EPDC_HIST8_PARAM1_VALUE7_MASK)
/*! @} */

/*! @name HIST16_PARAM0 - 16-level Histogram Parameter 0 Register. */
/*! @{ */

#define EPDC_HIST16_PARAM0_VALUE0_MASK           (0x1FU)
#define EPDC_HIST16_PARAM0_VALUE0_SHIFT          (0U)
#define EPDC_HIST16_PARAM0_VALUE0(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM0_VALUE0_SHIFT)) & EPDC_HIST16_PARAM0_VALUE0_MASK)

#define EPDC_HIST16_PARAM0_VALUE1_MASK           (0x1F00U)
#define EPDC_HIST16_PARAM0_VALUE1_SHIFT          (8U)
#define EPDC_HIST16_PARAM0_VALUE1(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM0_VALUE1_SHIFT)) & EPDC_HIST16_PARAM0_VALUE1_MASK)

#define EPDC_HIST16_PARAM0_VALUE2_MASK           (0x1F0000U)
#define EPDC_HIST16_PARAM0_VALUE2_SHIFT          (16U)
#define EPDC_HIST16_PARAM0_VALUE2(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM0_VALUE2_SHIFT)) & EPDC_HIST16_PARAM0_VALUE2_MASK)

#define EPDC_HIST16_PARAM0_VALUE3_MASK           (0x1F000000U)
#define EPDC_HIST16_PARAM0_VALUE3_SHIFT          (24U)
#define EPDC_HIST16_PARAM0_VALUE3(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM0_VALUE3_SHIFT)) & EPDC_HIST16_PARAM0_VALUE3_MASK)
/*! @} */

/*! @name HIST16_PARAM1 - 16-level Histogram Parameter Register. */
/*! @{ */

#define EPDC_HIST16_PARAM1_VALUE4_MASK           (0x1FU)
#define EPDC_HIST16_PARAM1_VALUE4_SHIFT          (0U)
#define EPDC_HIST16_PARAM1_VALUE4(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM1_VALUE4_SHIFT)) & EPDC_HIST16_PARAM1_VALUE4_MASK)

#define EPDC_HIST16_PARAM1_VALUE5_MASK           (0x1F00U)
#define EPDC_HIST16_PARAM1_VALUE5_SHIFT          (8U)
#define EPDC_HIST16_PARAM1_VALUE5(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM1_VALUE5_SHIFT)) & EPDC_HIST16_PARAM1_VALUE5_MASK)

#define EPDC_HIST16_PARAM1_VALUE6_MASK           (0x1F0000U)
#define EPDC_HIST16_PARAM1_VALUE6_SHIFT          (16U)
#define EPDC_HIST16_PARAM1_VALUE6(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM1_VALUE6_SHIFT)) & EPDC_HIST16_PARAM1_VALUE6_MASK)

#define EPDC_HIST16_PARAM1_VALUE7_MASK           (0x1F000000U)
#define EPDC_HIST16_PARAM1_VALUE7_SHIFT          (24U)
#define EPDC_HIST16_PARAM1_VALUE7(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM1_VALUE7_SHIFT)) & EPDC_HIST16_PARAM1_VALUE7_MASK)
/*! @} */

/*! @name HIST16_PARAM2 - 16-level Histogram Parameter Register. */
/*! @{ */

#define EPDC_HIST16_PARAM2_VALUE8_MASK           (0x1FU)
#define EPDC_HIST16_PARAM2_VALUE8_SHIFT          (0U)
#define EPDC_HIST16_PARAM2_VALUE8(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM2_VALUE8_SHIFT)) & EPDC_HIST16_PARAM2_VALUE8_MASK)

#define EPDC_HIST16_PARAM2_VALUE9_MASK           (0x1F00U)
#define EPDC_HIST16_PARAM2_VALUE9_SHIFT          (8U)
#define EPDC_HIST16_PARAM2_VALUE9(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM2_VALUE9_SHIFT)) & EPDC_HIST16_PARAM2_VALUE9_MASK)

#define EPDC_HIST16_PARAM2_VALUE10_MASK          (0x1F0000U)
#define EPDC_HIST16_PARAM2_VALUE10_SHIFT         (16U)
#define EPDC_HIST16_PARAM2_VALUE10(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM2_VALUE10_SHIFT)) & EPDC_HIST16_PARAM2_VALUE10_MASK)

#define EPDC_HIST16_PARAM2_VALUE11_MASK          (0x1F000000U)
#define EPDC_HIST16_PARAM2_VALUE11_SHIFT         (24U)
#define EPDC_HIST16_PARAM2_VALUE11(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM2_VALUE11_SHIFT)) & EPDC_HIST16_PARAM2_VALUE11_MASK)
/*! @} */

/*! @name HIST16_PARAM3 - 16-level Histogram Parameter Register. */
/*! @{ */

#define EPDC_HIST16_PARAM3_VALUE12_MASK          (0x1FU)
#define EPDC_HIST16_PARAM3_VALUE12_SHIFT         (0U)
#define EPDC_HIST16_PARAM3_VALUE12(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM3_VALUE12_SHIFT)) & EPDC_HIST16_PARAM3_VALUE12_MASK)

#define EPDC_HIST16_PARAM3_VALUE13_MASK          (0x1F00U)
#define EPDC_HIST16_PARAM3_VALUE13_SHIFT         (8U)
#define EPDC_HIST16_PARAM3_VALUE13(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM3_VALUE13_SHIFT)) & EPDC_HIST16_PARAM3_VALUE13_MASK)

#define EPDC_HIST16_PARAM3_VALUE14_MASK          (0x1F0000U)
#define EPDC_HIST16_PARAM3_VALUE14_SHIFT         (16U)
#define EPDC_HIST16_PARAM3_VALUE14(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM3_VALUE14_SHIFT)) & EPDC_HIST16_PARAM3_VALUE14_MASK)

#define EPDC_HIST16_PARAM3_VALUE15_MASK          (0x1F000000U)
#define EPDC_HIST16_PARAM3_VALUE15_SHIFT         (24U)
#define EPDC_HIST16_PARAM3_VALUE15(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_HIST16_PARAM3_VALUE15_SHIFT)) & EPDC_HIST16_PARAM3_VALUE15_MASK)
/*! @} */

/*! @name GPIO - General Purpose I/O Debug register */
/*! @{ */

#define EPDC_GPIO_BDR_MASK                       (0x3U)
#define EPDC_GPIO_BDR_SHIFT                      (0U)
#define EPDC_GPIO_BDR(x)                         (((uint32_t)(((uint32_t)(x)) << EPDC_GPIO_BDR_SHIFT)) & EPDC_GPIO_BDR_MASK)

#define EPDC_GPIO_PWRCTRL_MASK                   (0x3CU)
#define EPDC_GPIO_PWRCTRL_SHIFT                  (2U)
#define EPDC_GPIO_PWRCTRL(x)                     (((uint32_t)(((uint32_t)(x)) << EPDC_GPIO_PWRCTRL_SHIFT)) & EPDC_GPIO_PWRCTRL_MASK)

#define EPDC_GPIO_PWRCOM_MASK                    (0x40U)
#define EPDC_GPIO_PWRCOM_SHIFT                   (6U)
#define EPDC_GPIO_PWRCOM(x)                      (((uint32_t)(((uint32_t)(x)) << EPDC_GPIO_PWRCOM_SHIFT)) & EPDC_GPIO_PWRCOM_MASK)

#define EPDC_GPIO_PWRWAKE_MASK                   (0x80U)
#define EPDC_GPIO_PWRWAKE_SHIFT                  (7U)
#define EPDC_GPIO_PWRWAKE(x)                     (((uint32_t)(((uint32_t)(x)) << EPDC_GPIO_PWRWAKE_SHIFT)) & EPDC_GPIO_PWRWAKE_MASK)

#define EPDC_GPIO_PWRSTAT_MASK                   (0x100U)
#define EPDC_GPIO_PWRSTAT_SHIFT                  (8U)
#define EPDC_GPIO_PWRSTAT(x)                     (((uint32_t)(((uint32_t)(x)) << EPDC_GPIO_PWRSTAT_SHIFT)) & EPDC_GPIO_PWRSTAT_MASK)
/*! @} */

/*! @name VERSION - Version Register */
/*! @{ */

#define EPDC_VERSION_STEP_MASK                   (0xFFFFU)
#define EPDC_VERSION_STEP_SHIFT                  (0U)
#define EPDC_VERSION_STEP(x)                     (((uint32_t)(((uint32_t)(x)) << EPDC_VERSION_STEP_SHIFT)) & EPDC_VERSION_STEP_MASK)

#define EPDC_VERSION_MINOR_MASK                  (0xFF0000U)
#define EPDC_VERSION_MINOR_SHIFT                 (16U)
#define EPDC_VERSION_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << EPDC_VERSION_MINOR_SHIFT)) & EPDC_VERSION_MINOR_MASK)

#define EPDC_VERSION_MAJOR_MASK                  (0xFF000000U)
#define EPDC_VERSION_MAJOR_SHIFT                 (24U)
#define EPDC_VERSION_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << EPDC_VERSION_MAJOR_SHIFT)) & EPDC_VERSION_MAJOR_MASK)
/*! @} */

/*! @name PIGEON_X_PIGEON_0 - Panel Interface Signal Generator Register 0_0..Panel Interface Signal Generator Register 16_0 */
/*! @{ */

#define EPDC_PIGEON_X_PIGEON_0_EN_MASK           (0x1U)
#define EPDC_PIGEON_X_PIGEON_0_EN_SHIFT          (0U)
#define EPDC_PIGEON_X_PIGEON_0_EN(x)             (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_X_PIGEON_0_EN_SHIFT)) & EPDC_PIGEON_X_PIGEON_0_EN_MASK)

#define EPDC_PIGEON_X_PIGEON_0_POL_MASK          (0x2U)
#define EPDC_PIGEON_X_PIGEON_0_POL_SHIFT         (1U)
/*! POL
 *  0b0..normal signal (active high)
 *  0b1..inverted signal (active low)
 */
#define EPDC_PIGEON_X_PIGEON_0_POL(x)            (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_X_PIGEON_0_POL_SHIFT)) & EPDC_PIGEON_X_PIGEON_0_POL_MASK)

#define EPDC_PIGEON_X_PIGEON_0_INC_SEL_MASK      (0xCU)
#define EPDC_PIGEON_X_PIGEON_0_INC_SEL_SHIFT     (2U)
/*! INC_SEL
 *  0b00..pclk
 *  0b01..line start pulse
 *  0b10..frame start pulse
 *  0b11..use another signal as tick event
 */
#define EPDC_PIGEON_X_PIGEON_0_INC_SEL(x)        (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_X_PIGEON_0_INC_SEL_SHIFT)) & EPDC_PIGEON_X_PIGEON_0_INC_SEL_MASK)

#define EPDC_PIGEON_X_PIGEON_0_OFFSET_MASK       (0xF0U)
#define EPDC_PIGEON_X_PIGEON_0_OFFSET_SHIFT      (4U)
#define EPDC_PIGEON_X_PIGEON_0_OFFSET(x)         (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_X_PIGEON_0_OFFSET_SHIFT)) & EPDC_PIGEON_X_PIGEON_0_OFFSET_MASK)

#define EPDC_PIGEON_X_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)
#define EPDC_PIGEON_X_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)
/*! MASK_CNT_SEL
 *  0b0000..pclk counter within one hscan state
 *  0b0001..pclk cycle within one hscan state
 *  0b0010..line counter within one vscan state
 *  0b0011..line cycle within one vscan state
 *  0b0100..frame counter
 *  0b0101..frame cycle
 *  0b0110..horizontal counter (pclk counter within one line )
 *  0b0111..vertical counter (line counter within one frame)
 */
#define EPDC_PIGEON_X_PIGEON_0_MASK_CNT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_X_PIGEON_0_MASK_CNT_SEL_SHIFT)) & EPDC_PIGEON_X_PIGEON_0_MASK_CNT_SEL_MASK)

#define EPDC_PIGEON_X_PIGEON_0_MASK_CNT_MASK     (0xFFF000U)
#define EPDC_PIGEON_X_PIGEON_0_MASK_CNT_SHIFT    (12U)
#define EPDC_PIGEON_X_PIGEON_0_MASK_CNT(x)       (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_X_PIGEON_0_MASK_CNT_SHIFT)) & EPDC_PIGEON_X_PIGEON_0_MASK_CNT_MASK)

#define EPDC_PIGEON_X_PIGEON_0_STATE_MASK_MASK   (0xFF000000U)
#define EPDC_PIGEON_X_PIGEON_0_STATE_MASK_SHIFT  (24U)
/*! STATE_MASK
 *  0b00000001..FRAME SYNC
 *  0b00000010..FRAME BEGIN
 *  0b00000100..FRAME DATA
 *  0b00001000..FRAME END
 *  0b00010000..LINE SYNC
 *  0b00100000..LINE BEGIN
 *  0b01000000..LINE DATA
 *  0b10000000..LINE END
 */
#define EPDC_PIGEON_X_PIGEON_0_STATE_MASK(x)     (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_X_PIGEON_0_STATE_MASK_SHIFT)) & EPDC_PIGEON_X_PIGEON_0_STATE_MASK_MASK)
/*! @} */

/* The count of EPDC_PIGEON_X_PIGEON_0 */
#define EPDC_PIGEON_X_PIGEON_0_COUNT             (17U)

/*! @name PIGEON_X_PIGEON_1 - Panel Interface Signal Generator Register 0_1..Panel Interface Signal Generator Register 16_1 */
/*! @{ */

#define EPDC_PIGEON_X_PIGEON_1_SET_CNT_MASK      (0xFFFFU)
#define EPDC_PIGEON_X_PIGEON_1_SET_CNT_SHIFT     (0U)
/*! SET_CNT
 *  0b0000000000000000..start as active
 */
#define EPDC_PIGEON_X_PIGEON_1_SET_CNT(x)        (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_X_PIGEON_1_SET_CNT_SHIFT)) & EPDC_PIGEON_X_PIGEON_1_SET_CNT_MASK)

#define EPDC_PIGEON_X_PIGEON_1_CLR_CNT_MASK      (0xFFFF0000U)
#define EPDC_PIGEON_X_PIGEON_1_CLR_CNT_SHIFT     (16U)
/*! CLR_CNT
 *  0b0000000000000000..keep active until mask off
 */
#define EPDC_PIGEON_X_PIGEON_1_CLR_CNT(x)        (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_X_PIGEON_1_CLR_CNT_SHIFT)) & EPDC_PIGEON_X_PIGEON_1_CLR_CNT_MASK)
/*! @} */

/* The count of EPDC_PIGEON_X_PIGEON_1 */
#define EPDC_PIGEON_X_PIGEON_1_COUNT             (17U)

/*! @name PIGEON_X_PIGEON_2 - Panel Interface Signal Generator Register 0_2..Panel Interface Signal Generator Register 16_2 */
/*! @{ */

#define EPDC_PIGEON_X_PIGEON_2_SIG_LOGIC_MASK    (0xFU)
#define EPDC_PIGEON_X_PIGEON_2_SIG_LOGIC_SHIFT   (0U)
/*! SIG_LOGIC
 *  0b0000..no logic operation
 *  0b0001..sigout = sig_another AND this_sig
 *  0b0010..sigout = sig_another OR this_sig
 *  0b0011..mask = sig_another AND other_masks
 */
#define EPDC_PIGEON_X_PIGEON_2_SIG_LOGIC(x)      (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_X_PIGEON_2_SIG_LOGIC_SHIFT)) & EPDC_PIGEON_X_PIGEON_2_SIG_LOGIC_MASK)

#define EPDC_PIGEON_X_PIGEON_2_SIG_ANOTHER_MASK  (0x1F0U)
#define EPDC_PIGEON_X_PIGEON_2_SIG_ANOTHER_SHIFT (4U)
#define EPDC_PIGEON_X_PIGEON_2_SIG_ANOTHER(x)    (((uint32_t)(((uint32_t)(x)) << EPDC_PIGEON_X_PIGEON_2_SIG_ANOTHER_SHIFT)) & EPDC_PIGEON_X_PIGEON_2_SIG_ANOTHER_MASK)
/*! @} */

/* The count of EPDC_PIGEON_X_PIGEON_2 */
#define EPDC_PIGEON_X_PIGEON_2_COUNT             (17U)


/*!
 * @}
 */ /* end of group EPDC_Register_Masks */


/* EPDC - Peripheral instance base addresses */
/** Peripheral EPDC base address */
#define EPDC_BASE                                (0x3DB30000u)
/** Peripheral EPDC base pointer */
#define EPDC                                     ((EPDC_Type *)EPDC_BASE)
/** Array initializer of EPDC peripheral base addresses */
#define EPDC_BASE_ADDRS                          { EPDC_BASE }
/** Array initializer of EPDC peripheral base pointers */
#define EPDC_BASE_PTRS                           { EPDC }

/*!
 * @}
 */ /* end of group EPDC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- EWM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
 * @{
 */

/** EWM - Register Layout Typedef */
typedef struct {
  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
       uint8_t RESERVED_0[1];
  __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler Register, offset: 0x5 */
} EWM_Type;

/* ----------------------------------------------------------------------------
   -- EWM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup EWM_Register_Masks EWM Register Masks
 * @{
 */

/*! @name CTRL - Control Register */
/*! @{ */

#define EWM_CTRL_EWMEN_MASK                      (0x1U)
#define EWM_CTRL_EWMEN_SHIFT                     (0U)
/*! EWMEN - EWM enable.
 *  0b0..EWM module is disabled.
 *  0b1..EWM module is enabled.
 */
#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)

#define EWM_CTRL_ASSIN_MASK                      (0x2U)
#define EWM_CTRL_ASSIN_SHIFT                     (1U)
/*! ASSIN - EWM_in's Assertion State Select.
 *  0b0..Default assert state of the EWM_in signal.
 *  0b1..Inverts the assert state of EWM_in signal.
 */
#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)

#define EWM_CTRL_INEN_MASK                       (0x4U)
#define EWM_CTRL_INEN_SHIFT                      (2U)
/*! INEN - Input Enable.
 *  0b0..EWM_in port is disabled.
 *  0b1..EWM_in port is enabled.
 */
#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)

#define EWM_CTRL_INTEN_MASK                      (0x8U)
#define EWM_CTRL_INTEN_SHIFT                     (3U)
/*! INTEN - Interrupt Enable.
 *  0b1..Generates an interrupt request, when EWM_OUT_b is asserted.
 *  0b0..Deasserts the interrupt request.
 */
#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
/*! @} */

/*! @name SERV - Service Register */
/*! @{ */

#define EWM_SERV_SERVICE_MASK                    (0xFFU)
#define EWM_SERV_SERVICE_SHIFT                   (0U)
/*! SERVICE - SERVICE */
#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
/*! @} */

/*! @name CMPL - Compare Low Register */
/*! @{ */

#define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
#define EWM_CMPL_COMPAREL_SHIFT                  (0U)
/*! COMPAREL - COMPAREL */
#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
/*! @} */

/*! @name CMPH - Compare High Register */
/*! @{ */

#define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
#define EWM_CMPH_COMPAREH_SHIFT                  (0U)
/*! COMPAREH - COMPAREH */
#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
/*! @} */

/*! @name CLKPRESCALER - Clock Prescaler Register */
/*! @{ */

#define EWM_CLKPRESCALER_CLK_DIV_MASK            (0xFFU)
#define EWM_CLKPRESCALER_CLK_DIV_SHIFT           (0U)
/*! CLK_DIV - CLK_DIV */
#define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group EWM_Register_Masks */


/* EWM - Peripheral instance base addresses */
/** Peripheral EWM0 base address */
#define EWM0_BASE                                (0x2802E000u)
/** Peripheral EWM0 base pointer */
#define EWM0                                     ((EWM_Type *)EWM0_BASE)
/** Array initializer of EWM peripheral base addresses */
#define EWM_BASE_ADDRS                           { EWM0_BASE }
/** Array initializer of EWM peripheral base pointers */
#define EWM_BASE_PTRS                            { EWM0 }

/*!
 * @}
 */ /* end of group EWM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FLEXIO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
 * @{
 */

/** FLEXIO - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __IO uint32_t CTRL;                              /**< FlexIO Control Register, offset: 0x8 */
  __I  uint32_t PIN;                               /**< Pin State Register, offset: 0xC */
  __IO uint32_t SHIFTSTAT;                         /**< Shifter Status Register, offset: 0x10 */
  __IO uint32_t SHIFTERR;                          /**< Shifter Error Register, offset: 0x14 */
  __IO uint32_t TIMSTAT;                           /**< Timer Status Register, offset: 0x18 */
       uint8_t RESERVED_0[4];
  __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
  __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
  __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable Register, offset: 0x28 */
       uint8_t RESERVED_1[4];
  __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
       uint8_t RESERVED_2[4];
  __IO uint32_t TIMERSDEN;                         /**< Timer Status DMA Enable, offset: 0x38 */
       uint8_t RESERVED_3[4];
  __IO uint32_t SHIFTSTATE;                        /**< Shifter State Register, offset: 0x40 */
       uint8_t RESERVED_4[4];
  __IO uint32_t TRGSTAT;                           /**< Trigger Status Register, offset: 0x48 */
  __IO uint32_t TRIGIEN;                           /**< External Trigger Interrupt Enable Register, offset: 0x4C */
  __IO uint32_t PINSTAT;                           /**< Pin Status Register, offset: 0x50 */
  __IO uint32_t PINIEN;                            /**< Pin Interrupt Enable Register, offset: 0x54 */
  __IO uint32_t PINREN;                            /**< Pin Rising Edge Enable Register, offset: 0x58 */
  __IO uint32_t PINFEN;                            /**< Pin Falling Edge Enable Register, offset: 0x5C */
  __IO uint32_t PINOUTD;                           /**< Pin Output Data Register, offset: 0x60 */
  __IO uint32_t PINOUTE;                           /**< Pin Output Enable Register, offset: 0x64 */
  __O  uint32_t PINOUTDIS;                         /**< Pin Output Disable Register, offset: 0x68 */
  __O  uint32_t PINOUTCLR;                         /**< Pin Output Clear Register, offset: 0x6C */
  __O  uint32_t PINOUTSET;                         /**< Pin Output Set Register, offset: 0x70 */
  __O  uint32_t PINOUTTOG;                         /**< Pin Output Toggle Register, offset: 0x74 */
       uint8_t RESERVED_5[8];
  __IO uint32_t SHIFTCTL[8];                       /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
       uint8_t RESERVED_6[96];
  __IO uint32_t SHIFTCFG[8];                       /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_7[224];
  __IO uint32_t SHIFTBUF[8];                       /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_8[96];
  __IO uint32_t SHIFTBUFBIS[8];                    /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
       uint8_t RESERVED_9[96];
  __IO uint32_t SHIFTBUFBYS[8];                    /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
       uint8_t RESERVED_10[96];
  __IO uint32_t SHIFTBUFBBS[8];                    /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
       uint8_t RESERVED_11[96];
  __IO uint32_t TIMCTL[8];                         /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
       uint8_t RESERVED_12[96];
  __IO uint32_t TIMCFG[8];                         /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
       uint8_t RESERVED_13[96];
  __IO uint32_t TIMCMP[8];                         /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
       uint8_t RESERVED_14[352];
  __IO uint32_t SHIFTBUFNBS[8];                    /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
       uint8_t RESERVED_15[96];
  __IO uint32_t SHIFTBUFHWS[8];                    /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
       uint8_t RESERVED_16[96];
  __IO uint32_t SHIFTBUFNIS[8];                    /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
       uint8_t RESERVED_17[96];
  __IO uint32_t SHIFTBUFOES[8];                    /**< Shifter Buffer N Odd Even Swapped Register, array offset: 0x800, array step: 0x4 */
       uint8_t RESERVED_18[96];
  __IO uint32_t SHIFTBUFEOS[8];                    /**< Shifter Buffer N Even Odd Swapped Register, array offset: 0x880, array step: 0x4 */
       uint8_t RESERVED_19[96];
  __IO uint32_t SHIFTBUFHBS[8];                    /**< Shifter Buffer N Halfword Byte Swapped Register, array offset: 0x900, array step: 0x4 */
} FLEXIO_Type;

/* ----------------------------------------------------------------------------
   -- FLEXIO Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
#define FLEXIO_VERID_FEATURE_SHIFT               (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000000..Standard features implemented.
 *  0b0000000000000001..Supports state, logic and parallel modes.
 *  0b0000000000000010..Supports pin control registers.
 *  0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.
 */
#define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)

#define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
#define FLEXIO_VERID_MINOR_SHIFT                 (16U)
/*! MINOR - Minor Version Number */
#define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)

#define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
#define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
/*! MAJOR - Major Version Number */
#define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
#define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
/*! SHIFTER - Shifter Number */
#define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)

#define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
#define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
/*! TIMER - Timer Number */
#define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)

#define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
#define FLEXIO_PARAM_PIN_SHIFT                   (16U)
/*! PIN - Pin Number */
#define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)

#define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
#define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
/*! TRIGGER - Trigger Number */
#define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
/*! @} */

/*! @name CTRL - FlexIO Control Register */
/*! @{ */

#define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
#define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
/*! FLEXEN - FlexIO Enable
 *  0b0..FlexIO module is disabled.
 *  0b1..FlexIO module is enabled.
 */
#define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)

#define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
#define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
/*! SWRST - Software Reset
 *  0b0..Software reset is disabled
 *  0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
 */
#define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)

#define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
#define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
/*! FASTACC - Fast Access
 *  0b0..Configures for normal register accesses to FlexIO
 *  0b1..Configures for fast register accesses to FlexIO
 */
#define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)

#define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
#define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
/*! DBGE - Debug Enable
 *  0b0..FlexIO is disabled in debug modes.
 *  0b1..FlexIO is enabled in debug modes
 */
#define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)

#define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
#define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
/*! DOZEN - Doze Enable
 *  0b0..FlexIO enabled in Doze modes.
 *  0b1..FlexIO disabled in Doze modes.
 */
#define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
/*! @} */

/*! @name PIN - Pin State Register */
/*! @{ */

#define FLEXIO_PIN_PDI_MASK                      (0xFFFFFFFFU)
#define FLEXIO_PIN_PDI_SHIFT                     (0U)
/*! PDI - Pin Data Input */
#define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
/*! @} */

/*! @name SHIFTSTAT - Shifter Status Register */
/*! @{ */

#define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFFU)
#define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
/*! SSF - Shifter Status Flag */
#define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
/*! @} */

/*! @name SHIFTERR - Shifter Error Register */
/*! @{ */

#define FLEXIO_SHIFTERR_SEF_MASK                 (0xFFU)
#define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
/*! SEF - Shifter Error Flags */
#define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
/*! @} */

/*! @name TIMSTAT - Timer Status Register */
/*! @{ */

#define FLEXIO_TIMSTAT_TSF_MASK                  (0xFFU)
#define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
/*! TSF - Timer Status Flags */
#define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
/*! @} */

/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
/*! @{ */

#define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFFU)
#define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
/*! SSIE - Shifter Status Interrupt Enable */
#define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
/*! @} */

/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
/*! @{ */

#define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFFU)
#define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
/*! SEIE - Shifter Error Interrupt Enable */
#define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
/*! @} */

/*! @name TIMIEN - Timer Interrupt Enable Register */
/*! @{ */

#define FLEXIO_TIMIEN_TEIE_MASK                  (0xFFU)
#define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
/*! TEIE - Timer Status Interrupt Enable */
#define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
/*! @} */

/*! @name SHIFTSDEN - Shifter Status DMA Enable */
/*! @{ */

#define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFFU)
#define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
/*! SSDE - Shifter Status DMA Enable */
#define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
/*! @} */

/*! @name TIMERSDEN - Timer Status DMA Enable */
/*! @{ */

#define FLEXIO_TIMERSDEN_TSDE_MASK               (0xFFU)
#define FLEXIO_TIMERSDEN_TSDE_SHIFT              (0U)
/*! TSDE - Timer Status DMA Enable */
#define FLEXIO_TIMERSDEN_TSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)
/*! @} */

/*! @name SHIFTSTATE - Shifter State Register */
/*! @{ */

#define FLEXIO_SHIFTSTATE_STATE_MASK             (0x7U)
#define FLEXIO_SHIFTSTATE_STATE_SHIFT            (0U)
/*! STATE - Current State Pointer */
#define FLEXIO_SHIFTSTATE_STATE(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
/*! @} */

/*! @name TRGSTAT - Trigger Status Register */
/*! @{ */

#define FLEXIO_TRGSTAT_ETSF_MASK                 (0xFU)
#define FLEXIO_TRGSTAT_ETSF_SHIFT                (0U)
/*! ETSF - External Trigger Status Flags */
#define FLEXIO_TRGSTAT_ETSF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK)
/*! @} */

/*! @name TRIGIEN - External Trigger Interrupt Enable Register */
/*! @{ */

#define FLEXIO_TRIGIEN_TRIE_MASK                 (0xFU)
#define FLEXIO_TRIGIEN_TRIE_SHIFT                (0U)
/*! TRIE - External Trigger Interrupt Enable */
#define FLEXIO_TRIGIEN_TRIE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK)
/*! @} */

/*! @name PINSTAT - Pin Status Register */
/*! @{ */

#define FLEXIO_PINSTAT_PSF_MASK                  (0xFFFFFFFFU)
#define FLEXIO_PINSTAT_PSF_SHIFT                 (0U)
/*! PSF - Pin Status Flags */
#define FLEXIO_PINSTAT_PSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK)
/*! @} */

/*! @name PINIEN - Pin Interrupt Enable Register */
/*! @{ */

#define FLEXIO_PINIEN_PSIE_MASK                  (0xFFFFFFFFU)
#define FLEXIO_PINIEN_PSIE_SHIFT                 (0U)
/*! PSIE - Pin Status Interrupt Enable */
#define FLEXIO_PINIEN_PSIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK)
/*! @} */

/*! @name PINREN - Pin Rising Edge Enable Register */
/*! @{ */

#define FLEXIO_PINREN_PRE_MASK                   (0xFFFFFFFFU)
#define FLEXIO_PINREN_PRE_SHIFT                  (0U)
/*! PRE - Pin Rising Edge */
#define FLEXIO_PINREN_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK)
/*! @} */

/*! @name PINFEN - Pin Falling Edge Enable Register */
/*! @{ */

#define FLEXIO_PINFEN_PFE_MASK                   (0xFFFFFFFFU)
#define FLEXIO_PINFEN_PFE_SHIFT                  (0U)
/*! PFE - Pin Falling Edge */
#define FLEXIO_PINFEN_PFE(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK)
/*! @} */

/*! @name PINOUTD - Pin Output Data Register */
/*! @{ */

#define FLEXIO_PINOUTD_OUTD_MASK                 (0xFFFFFFFFU)
#define FLEXIO_PINOUTD_OUTD_SHIFT                (0U)
/*! OUTD - Output Data */
#define FLEXIO_PINOUTD_OUTD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK)
/*! @} */

/*! @name PINOUTE - Pin Output Enable Register */
/*! @{ */

#define FLEXIO_PINOUTE_OUTE_MASK                 (0xFFFFFFFFU)
#define FLEXIO_PINOUTE_OUTE_SHIFT                (0U)
/*! OUTE - Output Enable */
#define FLEXIO_PINOUTE_OUTE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK)
/*! @} */

/*! @name PINOUTDIS - Pin Output Disable Register */
/*! @{ */

#define FLEXIO_PINOUTDIS_OUTDIS_MASK             (0xFFFFFFFFU)
#define FLEXIO_PINOUTDIS_OUTDIS_SHIFT            (0U)
/*! OUTDIS - Output Disable */
#define FLEXIO_PINOUTDIS_OUTDIS(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK)
/*! @} */

/*! @name PINOUTCLR - Pin Output Clear Register */
/*! @{ */

#define FLEXIO_PINOUTCLR_OUTCLR_MASK             (0xFFFFFFFFU)
#define FLEXIO_PINOUTCLR_OUTCLR_SHIFT            (0U)
/*! OUTCLR - Output Clear */
#define FLEXIO_PINOUTCLR_OUTCLR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK)
/*! @} */

/*! @name PINOUTSET - Pin Output Set Register */
/*! @{ */

#define FLEXIO_PINOUTSET_OUTSET_MASK             (0xFFFFFFFFU)
#define FLEXIO_PINOUTSET_OUTSET_SHIFT            (0U)
/*! OUTSET - Output Set */
#define FLEXIO_PINOUTSET_OUTSET(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK)
/*! @} */

/*! @name PINOUTTOG - Pin Output Toggle Register */
/*! @{ */

#define FLEXIO_PINOUTTOG_OUTTOG_MASK             (0xFFFFFFFFU)
#define FLEXIO_PINOUTTOG_OUTTOG_SHIFT            (0U)
/*! OUTTOG - Output Toggle */
#define FLEXIO_PINOUTTOG_OUTTOG(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK)
/*! @} */

/*! @name SHIFTCTL - Shifter Control N Register */
/*! @{ */

#define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
#define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
/*! SMOD - Shifter Mode
 *  0b000..Disabled.
 *  0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
 *  0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
 *  0b011..Reserved.
 *  0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
 *  0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
 *  0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
 *  0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
 */
#define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)

#define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
#define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
/*! PINPOL - Shifter Pin Polarity
 *  0b0..Pin is active high
 *  0b1..Pin is active low
 */
#define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)

#define FLEXIO_SHIFTCTL_PINSEL_MASK              (0x1F00U)
#define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
/*! PINSEL - Shifter Pin Select */
#define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)

#define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
#define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
/*! PINCFG - Shifter Pin Configuration
 *  0b00..Shifter pin output disabled
 *  0b01..Shifter pin open drain or bidirectional output enable
 *  0b10..Shifter pin bidirectional output data
 *  0b11..Shifter pin output
 */
#define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)

#define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
/*! TIMPOL - Timer Polarity
 *  0b0..Shift on posedge of Shift clock
 *  0b1..Shift on negedge of Shift clock
 */
#define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)

#define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x7000000U)
#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
/*! TIMSEL - Timer Select */
#define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTCTL */
#define FLEXIO_SHIFTCTL_COUNT                    (8U)

/*! @name SHIFTCFG - Shifter Configuration N Register */
/*! @{ */

#define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
#define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
/*! SSTART - Shifter Start bit
 *  0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
 *  0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
 *  0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
 *  0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
 */
#define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)

#define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
#define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
/*! SSTOP - Shifter Stop bit
 *  0b00..Stop bit disabled for transmitter/receiver/match store
 *  0b01..Stop bit disabled for transmitter/receiver/match store, receiver/match store will store receive data on
 *        the configured shift edge when timer in stop condition
 *  0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not
 *        0, receiver/match store will also store receive data on the configured shift edge when timer in stop
 *        condition
 *  0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not
 *        1, receiver/match store will also store receive data on the configured shift edge when timer in stop
 *        condition
 */
#define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)

#define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
#define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
/*! INSRC - Input Source
 *  0b0..Pin
 *  0b1..Shifter N+1 Output
 */
#define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)

#define FLEXIO_SHIFTCFG_LATST_MASK               (0x200U)
#define FLEXIO_SHIFTCFG_LATST_SHIFT              (9U)
/*! LATST - Late Store
 *  0b0..Shift register stores the pre-shift register state.
 *  0b1..Shift register stores the post-shift register state.
 */
#define FLEXIO_SHIFTCFG_LATST(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)

#define FLEXIO_SHIFTCFG_SSIZE_MASK               (0x1000U)
#define FLEXIO_SHIFTCFG_SSIZE_SHIFT              (12U)
/*! SSIZE - Shifter Size
 *  0b0..Shift register is 32-bit.
 *  0b1..Shift register is 24-bit.
 */
#define FLEXIO_SHIFTCFG_SSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK)

#define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0x1F0000U)
#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
/*! PWIDTH - Parallel Width */
#define FLEXIO_SHIFTCFG_PWIDTH(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTCFG */
#define FLEXIO_SHIFTCFG_COUNT                    (8U)

/*! @name SHIFTBUF - Shifter Buffer N Register */
/*! @{ */

#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
/*! SHIFTBUF - Shift Buffer */
#define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUF */
#define FLEXIO_SHIFTBUF_COUNT                    (8U)

/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
/*! SHIFTBUFBIS - Shift Buffer */
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFBIS */
#define FLEXIO_SHIFTBUFBIS_COUNT                 (8U)

/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
/*! SHIFTBUFBYS - Shift Buffer */
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFBYS */
#define FLEXIO_SHIFTBUFBYS_COUNT                 (8U)

/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
/*! SHIFTBUFBBS - Shift Buffer */
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFBBS */
#define FLEXIO_SHIFTBUFBBS_COUNT                 (8U)

/*! @name TIMCTL - Timer Control N Register */
/*! @{ */

#define FLEXIO_TIMCTL_TIMOD_MASK                 (0x7U)
#define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
/*! TIMOD - Timer Mode
 *  0b000..Timer Disabled.
 *  0b001..Dual 8-bit counters baud mode.
 *  0b010..Dual 8-bit counters PWM high mode.
 *  0b011..Single 16-bit counter mode.
 *  0b100..Single 16-bit counter disable mode.
 *  0b101..Dual 8-bit counters word mode.
 *  0b110..Dual 8-bit counters PWM low mode.
 *  0b111..Single 16-bit input capture mode.
 */
#define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)

#define FLEXIO_TIMCTL_ONETIM_MASK                (0x20U)
#define FLEXIO_TIMCTL_ONETIM_SHIFT               (5U)
/*! ONETIM - Timer One Time Operation
 *  0b0..The timer enable event is generated as normal.
 *  0b1..The timer enable event is blocked unless timer status flag is clear.
 */
#define FLEXIO_TIMCTL_ONETIM(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)

#define FLEXIO_TIMCTL_PININS_MASK                (0x40U)
#define FLEXIO_TIMCTL_PININS_SHIFT               (6U)
/*! PININS - Timer Pin Input Select
 *  0b0..Timer pin input and output are selected by PINSEL.
 *  0b1..Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL.
 */
#define FLEXIO_TIMCTL_PININS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)

#define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
#define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
/*! PINPOL - Timer Pin Polarity
 *  0b0..Pin is active high
 *  0b1..Pin is active low
 */
#define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)

#define FLEXIO_TIMCTL_PINSEL_MASK                (0x1F00U)
#define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
/*! PINSEL - Timer Pin Select */
#define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)

#define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
#define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
/*! PINCFG - Timer Pin Configuration
 *  0b00..Timer pin output disabled
 *  0b01..Timer pin open drain or bidirectional output enable
 *  0b10..Timer pin bidirectional output data
 *  0b11..Timer pin output
 */
#define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)

#define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
#define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
/*! TRGSRC - Trigger Source
 *  0b0..External trigger selected
 *  0b1..Internal trigger selected
 */
#define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)

#define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
#define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
/*! TRGPOL - Trigger Polarity
 *  0b0..Trigger active high
 *  0b1..Trigger active low
 */
#define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)

#define FLEXIO_TIMCTL_TRGSEL_MASK                (0x3F000000U)
#define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
/*! TRGSEL - Trigger Select */
#define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
/*! @} */

/* The count of FLEXIO_TIMCTL */
#define FLEXIO_TIMCTL_COUNT                      (8U)

/*! @name TIMCFG - Timer Configuration N Register */
/*! @{ */

#define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
#define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
/*! TSTART - Timer Start Bit
 *  0b0..Start bit disabled
 *  0b1..Start bit enabled
 */
#define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)

#define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
#define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
/*! TSTOP - Timer Stop Bit
 *  0b00..Stop bit disabled
 *  0b01..Stop bit is enabled on timer compare
 *  0b10..Stop bit is enabled on timer disable
 *  0b11..Stop bit is enabled on timer compare and timer disable
 */
#define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)

#define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
#define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
/*! TIMENA - Timer Enable
 *  0b000..Timer always enabled
 *  0b001..Timer enabled on Timer N-1 enable
 *  0b010..Timer enabled on Trigger high
 *  0b011..Timer enabled on Trigger high and Pin high
 *  0b100..Timer enabled on Pin rising edge
 *  0b101..Timer enabled on Pin rising edge and Trigger high
 *  0b110..Timer enabled on Trigger rising edge
 *  0b111..Timer enabled on Trigger rising or falling edge
 */
#define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)

#define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
#define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
/*! TIMDIS - Timer Disable
 *  0b000..Timer never disabled
 *  0b001..Timer disabled on Timer N-1 disable
 *  0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
 *  0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
 *  0b100..Timer disabled on Pin rising or falling edge
 *  0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
 *  0b110..Timer disabled on Trigger falling edge
 *  0b111..Reserved
 */
#define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)

#define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
#define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
/*! TIMRST - Timer Reset
 *  0b000..Timer never reset
 *  0b001..Timer reset on Timer Output high.
 *  0b010..Timer reset on Timer Pin equal to Timer Output
 *  0b011..Timer reset on Timer Trigger equal to Timer Output
 *  0b100..Timer reset on Timer Pin rising edge
 *  0b101..Reserved
 *  0b110..Timer reset on Trigger rising edge
 *  0b111..Timer reset on Trigger rising or falling edge
 */
#define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)

#define FLEXIO_TIMCFG_TIMDEC_MASK                (0x700000U)
#define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
/*! TIMDEC - Timer Decrement
 *  0b000..Decrement counter on FlexIO clock, Shift clock equals Timer output.
 *  0b001..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
 *  0b010..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
 *  0b011..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
 *  0b100..Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output.
 *  0b101..Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output.
 *  0b110..Decrement counter on Pin input (rising edge), Shift clock equals Pin input.
 *  0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input.
 */
#define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)

#define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
#define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
/*! TIMOUT - Timer Output
 *  0b00..Timer output is logic one when enabled and is not affected by timer reset
 *  0b01..Timer output is logic zero when enabled and is not affected by timer reset
 *  0b10..Timer output is logic one when enabled and on timer reset
 *  0b11..Timer output is logic zero when enabled and on timer reset
 */
#define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
/*! @} */

/* The count of FLEXIO_TIMCFG */
#define FLEXIO_TIMCFG_COUNT                      (8U)

/*! @name TIMCMP - Timer Compare N Register */
/*! @{ */

#define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
#define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
/*! CMP - Timer Compare Value */
#define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
/*! @} */

/* The count of FLEXIO_TIMCMP */
#define FLEXIO_TIMCMP_COUNT                      (8U)

/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT     (0U)
/*! SHIFTBUFNBS - Shift Buffer */
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFNBS */
#define FLEXIO_SHIFTBUFNBS_COUNT                 (8U)

/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT     (0U)
/*! SHIFTBUFHWS - Shift Buffer */
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFHWS */
#define FLEXIO_SHIFTBUFHWS_COUNT                 (8U)

/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT     (0U)
/*! SHIFTBUFNIS - Shift Buffer */
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFNIS */
#define FLEXIO_SHIFTBUFNIS_COUNT                 (8U)

/*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT     (0U)
/*! SHIFTBUFOES - Shift Buffer */
#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFOES */
#define FLEXIO_SHIFTBUFOES_COUNT                 (8U)

/*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT     (0U)
/*! SHIFTBUFEOS - Shift Buffer */
#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFEOS */
#define FLEXIO_SHIFTBUFEOS_COUNT                 (8U)

/*! @name SHIFTBUFHBS - Shifter Buffer N Halfword Byte Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT     (0U)
/*! SHIFTBUFHBS - Shift Buffer */
#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFHBS */
#define FLEXIO_SHIFTBUFHBS_COUNT                 (8U)


/*!
 * @}
 */ /* end of group FLEXIO_Register_Masks */


/* FLEXIO - Peripheral instance base addresses */
/** Peripheral FLEXIO0 base address */
#define FLEXIO0_BASE                             (0x2803C000u)
/** Peripheral FLEXIO0 base pointer */
#define FLEXIO0                                  ((FLEXIO_Type *)FLEXIO0_BASE)
/** Peripheral FLEXIO1 base address */
#define FLEXIO1_BASE                             (0x29350000u)
/** Peripheral FLEXIO1 base pointer */
#define FLEXIO1                                  ((FLEXIO_Type *)FLEXIO1_BASE)
/** Array initializer of FLEXIO peripheral base addresses */
#define FLEXIO_BASE_ADDRS                        { FLEXIO0_BASE, FLEXIO1_BASE }
/** Array initializer of FLEXIO peripheral base pointers */
#define FLEXIO_BASE_PTRS                         { FLEXIO0, FLEXIO1 }

/*!
 * @}
 */ /* end of group FLEXIO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FLEXSPI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
 * @{
 */

/** FLEXSPI - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCR0;                              /**< Module Control Register 0, offset: 0x0 */
  __IO uint32_t MCR1;                              /**< Module Control Register 1, offset: 0x4 */
  __IO uint32_t MCR2;                              /**< Module Control Register 2, offset: 0x8 */
  __IO uint32_t AHBCR;                             /**< AHB Bus Control Register, offset: 0xC */
  __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x10 */
  __IO uint32_t INTR;                              /**< Interrupt Register, offset: 0x14 */
  __IO uint32_t LUTKEY;                            /**< LUT Key Register, offset: 0x18 */
  __IO uint32_t LUTCR;                             /**< LUT Control Register, offset: 0x1C */
  __IO uint32_t AHBRXBUFCR0[8];                    /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
       uint8_t RESERVED_0[32];
  __IO uint32_t FLSHCR0[4];                        /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
  __IO uint32_t FLSHCR1[4];                        /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
  __IO uint32_t FLSHCR2[4];                        /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
       uint8_t RESERVED_1[4];
  __IO uint32_t FLSHCR4;                           /**< Flash Control Register 4, offset: 0x94 */
       uint8_t RESERVED_2[8];
  __IO uint32_t IPCR0;                             /**< IP Control Register 0, offset: 0xA0 */
  __IO uint32_t IPCR1;                             /**< IP Control Register 1, offset: 0xA4 */
       uint8_t RESERVED_3[8];
  __IO uint32_t IPCMD;                             /**< IP Command Register, offset: 0xB0 */
  __IO uint32_t DLPR;                              /**< Data Learn Pattern Register, offset: 0xB4 */
  __IO uint32_t IPRXFCR;                           /**< IP RX FIFO Control Register, offset: 0xB8 */
  __IO uint32_t IPTXFCR;                           /**< IP TX FIFO Control Register, offset: 0xBC */
  __IO uint32_t DLLCR[2];                          /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
       uint8_t RESERVED_4[24];
  __I  uint32_t STS0;                              /**< Status Register 0, offset: 0xE0 */
  __I  uint32_t STS1;                              /**< Status Register 1, offset: 0xE4 */
  __I  uint32_t STS2;                              /**< Status Register 2, offset: 0xE8 */
  __I  uint32_t AHBSPNDSTS;                        /**< AHB Suspend Status Register, offset: 0xEC */
  __I  uint32_t IPRXFSTS;                          /**< IP RX FIFO Status Register, offset: 0xF0 */
  __I  uint32_t IPTXFSTS;                          /**< IP TX FIFO Status Register, offset: 0xF4 */
       uint8_t RESERVED_5[8];
  __I  uint32_t RFDR[32];                          /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
  __O  uint32_t TFDR[32];                          /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
  __IO uint32_t LUT[64];                           /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */
} FLEXSPI_Type;

/* ----------------------------------------------------------------------------
   -- FLEXSPI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
 * @{
 */

/*! @name MCR0 - Module Control Register 0 */
/*! @{ */

#define FLEXSPI_MCR0_SWRESET_MASK                (0x1U)
#define FLEXSPI_MCR0_SWRESET_SHIFT               (0U)
/*! SWRESET - Software Reset */
#define FLEXSPI_MCR0_SWRESET(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)

#define FLEXSPI_MCR0_MDIS_MASK                   (0x2U)
#define FLEXSPI_MCR0_MDIS_SHIFT                  (1U)
/*! MDIS - Module Disable */
#define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)

#define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
#define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
/*! RXCLKSRC - Sample Clock source selection for Flash Reading
 *  0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
 *  0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
 *  0b10..Reserved
 *  0b11..Flash provided Read strobe and input from DQS pad
 */
#define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)

#define FLEXSPI_MCR0_ARDFEN_MASK                 (0x40U)
#define FLEXSPI_MCR0_ARDFEN_SHIFT                (6U)
/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
 *  0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
 *  0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
 */
#define FLEXSPI_MCR0_ARDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)

#define FLEXSPI_MCR0_ATDFEN_MASK                 (0x80U)
#define FLEXSPI_MCR0_ATDFEN_SHIFT                (7U)
/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
 *  0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
 *  0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
 */
#define FLEXSPI_MCR0_ATDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)

#define FLEXSPI_MCR0_SERCLKDIV_MASK              (0x700U)
#define FLEXSPI_MCR0_SERCLKDIV_SHIFT             (8U)
/*! SERCLKDIV - Serial root clock
 *  0b000..Divided by 1
 *  0b001..Divided by 2
 *  0b010..Divided by 3
 *  0b011..Divided by 4
 *  0b100..Divided by 5
 *  0b101..Divided by 6
 *  0b110..Divided by 7
 *  0b111..Divided by 8
 */
#define FLEXSPI_MCR0_SERCLKDIV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)

#define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
#define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
/*! HSEN - Half Speed Serial Flash Access Enable.
 *  0b0..Disable divide by 2 of serial flash clock for half speed commands.
 *  0b1..Enable divide by 2 of serial flash clock for half speed commands.
 */
#define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)

#define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
#define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
/*! DOZEEN - Doze mode enable bit
 *  0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
 *  0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
 */
#define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)

#define FLEXSPI_MCR0_COMBINATIONEN_MASK          (0x2000U)
#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT         (13U)
/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data
 *    pins (A_DATA[3:0] and B_DATA[3:0]), when Port A and Port B are of 4 bit data width.
 *  0b0..Disable.
 *  0b1..Enable.
 */
#define FLEXSPI_MCR0_COMBINATIONEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)

#define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
/*! SCKFREERUNEN - This bit is used to enable SCLK output free-running. For FPGA applications, the
 *    external device may use SCLK as reference clock to its internal PLL.
 *  0b0..Disable.
 *  0b1..Enable.
 */
#define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)

#define FLEXSPI_MCR0_LEARNEN_MASK                (0x8000U)
#define FLEXSPI_MCR0_LEARNEN_SHIFT               (15U)
/*! LEARNEN - This bit is used to enable/disable the data learning feature.
 *  0b0..Disable.
 *  0b1..Enable.
 */
#define FLEXSPI_MCR0_LEARNEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK)

#define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
/*! IPGRANTWAIT - Timeout wait cycle for IP command grant. */
#define FLEXSPI_MCR0_IPGRANTWAIT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)

#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK           (0xFF000000U)
#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT          (24U)
/*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant. */
#define FLEXSPI_MCR0_AHBGRANTWAIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
/*! @} */

/*! @name MCR1 - Module Control Register 1 */
/*! @{ */

#define FLEXSPI_MCR1_AHBBUSWAIT_MASK             (0xFFFFU)
#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT            (0U)
/*! AHBBUSWAIT - AHB Bus wait */
#define FLEXSPI_MCR1_AHBBUSWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)

#define FLEXSPI_MCR1_SEQWAIT_MASK                (0xFFFF0000U)
#define FLEXSPI_MCR1_SEQWAIT_SHIFT               (16U)
/*! SEQWAIT - Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root
 *    Clock cycles. When sequence execution timeout occurs, there will be an interrupt generated
 *    (INTR[SEQTIMEOUT]) if this interrupt is enabled (INTEN[SEQTIMEOUTEN] is set 0x1) and AHB command is
 *    ignored by arbitrator.
 */
#define FLEXSPI_MCR1_SEQWAIT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
/*! @} */

/*! @name MCR2 - Module Control Register 2 */
/*! @{ */

#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
/*! CLRAHBBUFOPT - Clear AHB buffer
 *  0b0..AHB RX/TX Buffer will not be cleared automatically when FlexSPI returns Stop mode ACK.
 *  0b1..AHB RX/TX Buffer will be cleared automatically when FlexSPI returns Stop mode ACK.
 */
#define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)

#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK          (0x4000U)
#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT         (14U)
/*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is
 *    written with 0x1. This bit will be auto-cleared immediately.
 */
#define FLEXSPI_MCR2_CLRLEARNPHASE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)

#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
/*! SAMEDEVICEEN - All external devices are same devices (both in type and size) for A1/A2/B1/B2.
 *  0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
 *       A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
 *       FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register setting will be
 *       ignored.
 *  0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register setting will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
 */
#define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)

#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK            (0x80000U)
#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT           (19U)
/*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to
 *    A_SCLK). In this case, port B flash access is not available. After changing the value of this
 *    field, MCR0[SWRESET] should be set.
 *  0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.
 *  0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
 */
#define FLEXSPI_MCR2_SCKBDIFFOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)

#define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
/*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. */
#define FLEXSPI_MCR2_RESUMEWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
/*! @} */

/*! @name AHBCR - AHB Bus Control Register */
/*! @{ */

#define FLEXSPI_AHBCR_APAREN_MASK                (0x1U)
#define FLEXSPI_AHBCR_APAREN_SHIFT               (0U)
/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write).
 *  0b0..Flash will be accessed in Individual mode.
 *  0b1..Flash will be accessed in Parallel mode.
 */
#define FLEXSPI_AHBCR_APAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)

#define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK           (0x4U)
#define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT          (2U)
/*! CLRAHBTXBUF - Clear the status/pointers of AHB TX Buffer. Auto-cleared. */
#define FLEXSPI_AHBCR_CLRAHBTXBUF(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK)

#define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
/*! CACHABLEEN - Enable AHB bus cachable read access support.
 *  0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
 *  0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
 */
#define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)

#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
/*! BUFFERABLEEN - Enable AHB bus bufferable write access support.
 *  0b0..Disabled. For all AHB write accesses (bufferable or non-bufferable), FlexSPI will return AHB Bus ready
 *       after all data is transmitted to external device and AHB command finished.
 *  0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
 *       granted by arbitrator and will not wait for AHB command finished.
 */
#define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)

#define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
/*! PREFETCHEN - AHB Read Prefetch Enable. */
#define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)

#define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
#define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
/*! READADDROPT - AHB Read Address option bit. This option bit is intended to remove AHB burst start address alignment limitation.
 *  0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is word-addressable.
 *  0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB
 *       burst required to meet the alignment requirement.
 */
#define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)

#define FLEXSPI_AHBCR_RESUMEDISABLE_MASK         (0x80U)
#define FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT        (7U)
/*! RESUMEDISABLE - AHB Read Resume Disable
 *  0b0..Suspended AHB read prefetch will start to resume when AHB is IDLE
 *  0b1..Suspended AHB read prefetch will not resume once it is aborted
 */
#define FLEXSPI_AHBCR_RESUMEDISABLE(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT)) & FLEXSPI_AHBCR_RESUMEDISABLE_MASK)

#define FLEXSPI_AHBCR_READSZALIGN_MASK           (0x400U)
#define FLEXSPI_AHBCR_READSZALIGN_SHIFT          (10U)
/*! READSZALIGN - AHB Read Size Alignment
 *  0b0..AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN...
 *  0b1..AHB read size to up size to 8 bytes aligned, no prefetching
 */
#define FLEXSPI_AHBCR_READSZALIGN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK)
/*! @} */

/*! @name INTEN - Interrupt Enable Register */
/*! @{ */

#define FLEXSPI_INTEN_IPCMDDONEEN_MASK           (0x1U)
#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT          (0U)
/*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable. */
#define FLEXSPI_INTEN_IPCMDDONEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)

#define FLEXSPI_INTEN_IPCMDGEEN_MASK             (0x2U)
#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT            (1U)
/*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable. */
#define FLEXSPI_INTEN_IPCMDGEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)

#define FLEXSPI_INTEN_AHBCMDGEEN_MASK            (0x4U)
#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT           (2U)
/*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable. */
#define FLEXSPI_INTEN_AHBCMDGEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)

#define FLEXSPI_INTEN_IPCMDERREN_MASK            (0x8U)
#define FLEXSPI_INTEN_IPCMDERREN_SHIFT           (3U)
/*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable. */
#define FLEXSPI_INTEN_IPCMDERREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)

#define FLEXSPI_INTEN_AHBCMDERREN_MASK           (0x10U)
#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT          (4U)
/*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable. */
#define FLEXSPI_INTEN_AHBCMDERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)

#define FLEXSPI_INTEN_IPRXWAEN_MASK              (0x20U)
#define FLEXSPI_INTEN_IPRXWAEN_SHIFT             (5U)
/*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable. */
#define FLEXSPI_INTEN_IPRXWAEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)

#define FLEXSPI_INTEN_IPTXWEEN_MASK              (0x40U)
#define FLEXSPI_INTEN_IPTXWEEN_SHIFT             (6U)
/*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable. */
#define FLEXSPI_INTEN_IPTXWEEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)

#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK       (0x80U)
#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT      (7U)
/*! DATALEARNFAILEN - Data Learning failed interrupt enable. */
#define FLEXSPI_INTEN_DATALEARNFAILEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK)

#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK         (0x100U)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT        (8U)
/*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable. */
#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)

#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK         (0x200U)
#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT        (9U)
/*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable. */
#define FLEXSPI_INTEN_SCKSTOPBYWREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)

#define FLEXSPI_INTEN_AHBBUSERROREN_MASK         (0x400U)
#define FLEXSPI_INTEN_AHBBUSERROREN_SHIFT        (10U)
/*! AHBBUSERROREN - AHB Bus error interrupt enable. */
#define FLEXSPI_INTEN_AHBBUSERROREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK)

#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK       (0x400U)
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT      (10U)
/*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt. */
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)

#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK          (0x800U)
#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT         (11U)
/*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable. */
#define FLEXSPI_INTEN_SEQTIMEOUTEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)

#define FLEXSPI_INTEN_KEYDONEEN_MASK             (0x1000U)
#define FLEXSPI_INTEN_KEYDONEEN_SHIFT            (12U)
/*! KEYDONEEN - OTFAD key blob processing done interrupt enable. */
#define FLEXSPI_INTEN_KEYDONEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK)

#define FLEXSPI_INTEN_KEYERROREN_MASK            (0x2000U)
#define FLEXSPI_INTEN_KEYERROREN_SHIFT           (13U)
/*! KEYERROREN - OTFAD key blob processing error interrupt enable. */
#define FLEXSPI_INTEN_KEYERROREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK)
/*! @} */

/*! @name INTR - Interrupt Register */
/*! @{ */

#define FLEXSPI_INTR_IPCMDDONE_MASK              (0x1U)
#define FLEXSPI_INTR_IPCMDDONE_SHIFT             (0U)
/*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also
 *    generated when there is IPCMDGE or IPCMDERR interrupt generated.
 */
#define FLEXSPI_INTR_IPCMDDONE(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)

#define FLEXSPI_INTR_IPCMDGE_MASK                (0x2U)
#define FLEXSPI_INTR_IPCMDGE_SHIFT               (1U)
/*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt. */
#define FLEXSPI_INTR_IPCMDGE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)

#define FLEXSPI_INTR_AHBCMDGE_MASK               (0x4U)
#define FLEXSPI_INTR_AHBCMDGE_SHIFT              (2U)
/*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt. */
#define FLEXSPI_INTR_AHBCMDGE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)

#define FLEXSPI_INTR_IPCMDERR_MASK               (0x8U)
#define FLEXSPI_INTR_IPCMDERR_SHIFT              (3U)
/*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for
 *    IP command, this command will be ignored and not executed at all.
 */
#define FLEXSPI_INTR_IPCMDERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)

#define FLEXSPI_INTR_AHBCMDERR_MASK              (0x10U)
#define FLEXSPI_INTR_AHBCMDERR_SHIFT             (4U)
/*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for
 *    AHB command, this command will be ignored and not executed at all.
 */
#define FLEXSPI_INTR_AHBCMDERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)

#define FLEXSPI_INTR_IPRXWA_MASK                 (0x20U)
#define FLEXSPI_INTR_IPRXWA_SHIFT                (5U)
/*! IPRXWA - IP RX FIFO watermark available interrupt. */
#define FLEXSPI_INTR_IPRXWA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)

#define FLEXSPI_INTR_IPTXWE_MASK                 (0x40U)
#define FLEXSPI_INTR_IPTXWE_SHIFT                (6U)
/*! IPTXWE - IP TX FIFO watermark empty interrupt. */
#define FLEXSPI_INTR_IPTXWE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)

#define FLEXSPI_INTR_DATALEARNFAIL_MASK          (0x80U)
#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT         (7U)
/*! DATALEARNFAIL - Data Learning failed interrupt. */
#define FLEXSPI_INTR_DATALEARNFAIL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK)

#define FLEXSPI_INTR_SCKSTOPBYRD_MASK            (0x100U)
#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT           (8U)
/*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt. */
#define FLEXSPI_INTR_SCKSTOPBYRD(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)

#define FLEXSPI_INTR_SCKSTOPBYWR_MASK            (0x200U)
#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT           (9U)
/*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt. */
#define FLEXSPI_INTR_SCKSTOPBYWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)

#define FLEXSPI_INTR_AHBBUSERROR_MASK            (0x400U)
#define FLEXSPI_INTR_AHBBUSERROR_SHIFT           (10U)
/*! AHBBUSERROR - AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt. */
#define FLEXSPI_INTR_AHBBUSERROR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK)

#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK          (0x400U)
#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT         (10U)
/*! AHBBUSTIMEOUT - AHB Bus timeout interrupt. */
#define FLEXSPI_INTR_AHBBUSTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)

#define FLEXSPI_INTR_SEQTIMEOUT_MASK             (0x800U)
#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT            (11U)
/*! SEQTIMEOUT - Sequence execution timeout interrupt. */
#define FLEXSPI_INTR_SEQTIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)

#define FLEXSPI_INTR_KEYDONE_MASK                (0x1000U)
#define FLEXSPI_INTR_KEYDONE_SHIFT               (12U)
/*! KEYDONE - OTFAD key blob processing done interrupt. */
#define FLEXSPI_INTR_KEYDONE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK)

#define FLEXSPI_INTR_KEYERROR_MASK               (0x2000U)
#define FLEXSPI_INTR_KEYERROR_SHIFT              (13U)
/*! KEYERROR - OTFAD key blob processing error interrupt. */
#define FLEXSPI_INTR_KEYERROR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK)
/*! @} */

/*! @name LUTKEY - LUT Key Register */
/*! @{ */

#define FLEXSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
#define FLEXSPI_LUTKEY_KEY_SHIFT                 (0U)
/*! KEY - The Key to lock or unlock LUT. */
#define FLEXSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
/*! @} */

/*! @name LUTCR - LUT Control Register */
/*! @{ */

#define FLEXSPI_LUTCR_LOCK_MASK                  (0x1U)
#define FLEXSPI_LUTCR_LOCK_SHIFT                 (0U)
/*! LOCK - Lock LUT */
#define FLEXSPI_LUTCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)

#define FLEXSPI_LUTCR_UNLOCK_MASK                (0x2U)
#define FLEXSPI_LUTCR_UNLOCK_SHIFT               (1U)
/*! UNLOCK - Unlock LUT */
#define FLEXSPI_LUTCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
/*! @} */

/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
/*! @{ */

#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK           (0x1FFU)  /* Merged from fields with different position or width, of widths (8, 9), largest definition used */
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT          (0U)
/*! BUFSZ - AHB RX Buffer Size in 64 bits. */
#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)  /* Merged from fields with different position or width, of widths (8, 9), largest definition used */

#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK          (0xF0000U)
#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT         (16U)
/*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). */
#define FLEXSPI_AHBRXBUFCR0_MSTRID(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)

#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK        (0x7000000U)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT       (24U)
/*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. */
#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)

#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK      (0x80000000U)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT     (31U)
/*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. */
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
/*! @} */

/* The count of FLEXSPI_AHBRXBUFCR0 */
#define FLEXSPI_AHBRXBUFCR0_COUNT                (8U)

/*! @name FLSHCR0 - Flash Control Register 0 */
/*! @{ */

#define FLEXSPI_FLSHCR0_FLSHSZ_MASK              (0x7FFFFFU)
#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT             (0U)
/*! FLSHSZ - Flash Size in KByte. */
#define FLEXSPI_FLSHCR0_FLSHSZ(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
/*! @} */

/* The count of FLEXSPI_FLSHCR0 */
#define FLEXSPI_FLSHCR0_COUNT                    (4U)

/*! @name FLSHCR1 - Flash Control Register 1 */
/*! @{ */

#define FLEXSPI_FLSHCR1_TCSS_MASK                (0x1FU)
#define FLEXSPI_FLSHCR1_TCSS_SHIFT               (0U)
/*! TCSS - Serial Flash CS setup time. */
#define FLEXSPI_FLSHCR1_TCSS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)

#define FLEXSPI_FLSHCR1_TCSH_MASK                (0x3E0U)
#define FLEXSPI_FLSHCR1_TCSH_SHIFT               (5U)
/*! TCSH - Serial Flash CS Hold time. */
#define FLEXSPI_FLSHCR1_TCSH(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)

#define FLEXSPI_FLSHCR1_WA_MASK                  (0x400U)
#define FLEXSPI_FLSHCR1_WA_SHIFT                 (10U)
/*! WA - Word Addressable. */
#define FLEXSPI_FLSHCR1_WA(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)

#define FLEXSPI_FLSHCR1_CAS_MASK                 (0x7800U)
#define FLEXSPI_FLSHCR1_CAS_SHIFT                (11U)
/*! CAS - Column Address Size. */
#define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)

#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
/*! CSINTERVALUNIT - CS interval unit
 *  0b0..The CS interval unit is 1 serial clock cycle
 *  0b1..The CS interval unit is 256 serial clock cycle
 */
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)

#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
/*! CSINTERVAL - This field is used to set the minimum interval between flash device chip select
 *    deassertion and flash device chip select assertion. If external flash has a limitation on the
 *    interval between command sequences, this field should be set accordingly. If there is no
 *    limitation, set this field with value 0x0.
 */
#define FLEXSPI_FLSHCR1_CSINTERVAL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
/*! @} */

/* The count of FLEXSPI_FLSHCR1 */
#define FLEXSPI_FLSHCR1_COUNT                    (4U)

/*! @name FLSHCR2 - Flash Control Register 2 */
/*! @{ */

#define FLEXSPI_FLSHCR2_ARDSEQID_MASK            (0xFU)
#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT           (0U)
/*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT. */
#define FLEXSPI_FLSHCR2_ARDSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)

#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK           (0xE0U)
#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT          (5U)
/*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT. */
#define FLEXSPI_FLSHCR2_ARDSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)

#define FLEXSPI_FLSHCR2_AWRSEQID_MASK            (0xF00U)
#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT           (8U)
/*! AWRSEQID - Sequence Index for AHB Write triggered Command. */
#define FLEXSPI_FLSHCR2_AWRSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)

#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK           (0xE000U)
#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT          (13U)
/*! AWRSEQNUM - Sequence Number for AHB Write triggered Command. */
#define FLEXSPI_FLSHCR2_AWRSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)

#define FLEXSPI_FLSHCR2_AWRWAIT_MASK             (0xFFF0000U)
#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT            (16U)
/*! AWRWAIT - For certain devices (such as FPGA), it need some time to write data into internal
 *    memory after the command sequences finished on FlexSPI interface. If another Read command sequence
 *    comes before previous programming finished internally, the read data may be wrong. This field
 *    is used to hold AHB Bus ready for AHB write access to wait the programming finished in
 *    external device. Then there will be no AHB read command triggered before the programming finished in
 *    external device. The Wait cycle between AHB triggered command sequences finished on FlexSPI
 *    interface and AHB return Bus ready: AWRWAIT * AWRWAITUNIT
 */
#define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)

#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
/*! AWRWAITUNIT - AWRWAIT unit
 *  0b000..The AWRWAIT unit is 2 AHB clock cycle
 *  0b001..The AWRWAIT unit is 8 AHB clock cycle
 *  0b010..The AWRWAIT unit is 32 AHB clock cycle
 *  0b011..The AWRWAIT unit is 128 AHB clock cycle
 *  0b100..The AWRWAIT unit is 512 AHB clock cycle
 *  0b101..The AWRWAIT unit is 2048 AHB clock cycle
 *  0b110..The AWRWAIT unit is 8192 AHB clock cycle
 *  0b111..The AWRWAIT unit is 32768 AHB clock cycle
 */
#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)

#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
/*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. */
#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
/*! @} */

/* The count of FLEXSPI_FLSHCR2 */
#define FLEXSPI_FLSHCR2_COUNT                    (4U)

/*! @name FLSHCR4 - Flash Control Register 4 */
/*! @{ */

#define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB and IP write burst
 *    start address alignment limitation.
 *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB/IP
 *       write burst start address alignment when flash is accessed in individual mode.
 *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB/IP
 *       write burst start address alignment when flash is accessed in individual mode.
 */
#define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)

#define FLEXSPI_FLSHCR4_WMOPT2_MASK              (0x2U)
#define FLEXSPI_FLSHCR4_WMOPT2_SHIFT             (1U)
/*! WMOPT2 - Write mask option bit 2. When using AP memory, this option bit could be used to remove
 *    AHB and IP write burst minimum length limitation. When using this bit, WMOPT1 should also be
 *    set.
 *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB/IP
 *       write burst length when flash is accessed in individual mode.
 *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB/IP
 *       write burst length when flash is accessed in individual mode, the minimum write burst length should be 4.
 */
#define FLEXSPI_FLSHCR4_WMOPT2(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK)

#define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
#define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
 *    memory device on port A, this bit must be set.
 *  0b0..Write mask is disabled, DQS(RWDS) pin will not be driven when writing to external device.
 *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
 */
#define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)

#define FLEXSPI_FLSHCR4_WMENB_MASK               (0x8U)
#define FLEXSPI_FLSHCR4_WMENB_SHIFT              (3U)
/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
 *    memory device on port B, this bit must be set.
 *  0b0..Write mask is disabled, DQS(RWDS) pin will not be driven when writing to external device.
 *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
 */
#define FLEXSPI_FLSHCR4_WMENB(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
/*! @} */

/*! @name IPCR0 - IP Control Register 0 */
/*! @{ */

#define FLEXSPI_IPCR0_SFAR_MASK                  (0xFFFFFFFFU)
#define FLEXSPI_IPCR0_SFAR_SHIFT                 (0U)
/*! SFAR - Serial Flash Address for IP command. */
#define FLEXSPI_IPCR0_SFAR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
/*! @} */

/*! @name IPCR1 - IP Control Register 1 */
/*! @{ */

#define FLEXSPI_IPCR1_IDATSZ_MASK                (0xFFFFU)
#define FLEXSPI_IPCR1_IDATSZ_SHIFT               (0U)
/*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command. */
#define FLEXSPI_IPCR1_IDATSZ(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)

#define FLEXSPI_IPCR1_ISEQID_MASK                (0xF0000U)
#define FLEXSPI_IPCR1_ISEQID_SHIFT               (16U)
/*! ISEQID - Sequence Index in LUT for IP command. */
#define FLEXSPI_IPCR1_ISEQID(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)

#define FLEXSPI_IPCR1_ISEQNUM_MASK               (0x7000000U)
#define FLEXSPI_IPCR1_ISEQNUM_SHIFT              (24U)
/*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */
#define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)

#define FLEXSPI_IPCR1_IPAREN_MASK                (0x80000000U)
#define FLEXSPI_IPCR1_IPAREN_SHIFT               (31U)
/*! IPAREN - Parallel mode Enabled for IP command.
 *  0b0..Flash will be accessed in Individual mode.
 *  0b1..Flash will be accessed in Parallel mode.
 */
#define FLEXSPI_IPCR1_IPAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
/*! @} */

/*! @name IPCMD - IP Command Register */
/*! @{ */

#define FLEXSPI_IPCMD_TRG_MASK                   (0x1U)
#define FLEXSPI_IPCMD_TRG_SHIFT                  (0U)
/*! TRG - Setting this bit will trigger an IP Command. */
#define FLEXSPI_IPCMD_TRG(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
/*! @} */

/*! @name DLPR - Data Learn Pattern Register */
/*! @{ */

#define FLEXSPI_DLPR_DLP_MASK                    (0xFFFFFFFFU)
#define FLEXSPI_DLPR_DLP_SHIFT                   (0U)
/*! DLP - Data Learning Pattern. */
#define FLEXSPI_DLPR_DLP(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK)
/*! @} */

/*! @name IPRXFCR - IP RX FIFO Control Register */
/*! @{ */

#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK            (0x1U)
#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT           (0U)
/*! CLRIPRXF - Clear all valid data entries in IP RX FIFO. */
#define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)

#define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
/*! RXDMAEN - IP RX FIFO reading by DMA enabled.
 *  0b0..IP RX FIFO would be read by processor.
 *  0b1..IP RX FIFO would be read by DMA.
 */
#define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)

#define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0x1FCU)
#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
/*! RXWMRK - Watermark level is (RXWMRK+1)*64 bits. */
#define FLEXSPI_IPRXFCR_RXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
/*! @} */

/*! @name IPTXFCR - IP TX FIFO Control Register */
/*! @{ */

#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK            (0x1U)
#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT           (0U)
/*! CLRIPTXF - Clear all valid data entries in IP TX FIFO. */
#define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)

#define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
/*! TXDMAEN - IP TX FIFO filling by DMA enabled.
 *  0b0..IP TX FIFO would be filled by processor.
 *  0b1..IP TX FIFO would be filled by DMA.
 */
#define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)

#define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x1FCU)
#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
/*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits. */
#define FLEXSPI_IPTXFCR_TXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
/*! @} */

/*! @name DLLCR - DLL Control Register 0 */
/*! @{ */

#define FLEXSPI_DLLCR_DLLEN_MASK                 (0x1U)
#define FLEXSPI_DLLCR_DLLEN_SHIFT                (0U)
/*! DLLEN - DLL calibration enable. */
#define FLEXSPI_DLLCR_DLLEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)

#define FLEXSPI_DLLCR_DLLRESET_MASK              (0x2U)
#define FLEXSPI_DLLCR_DLLRESET_SHIFT             (1U)
/*! DLLRESET - DLL reset */
#define FLEXSPI_DLLCR_DLLRESET(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)

#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK          (0x78U)
#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT         (3U)
/*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle
 *    of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1,
 *    OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended.
 */
#define FLEXSPI_DLLCR_SLVDLYTARGET(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)

#define FLEXSPI_DLLCR_OVRDEN_MASK                (0x100U)
#define FLEXSPI_DLLCR_OVRDEN_SHIFT               (8U)
/*! OVRDEN - Slave clock delay line delay cell number selection override enable. */
#define FLEXSPI_DLLCR_OVRDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)

#define FLEXSPI_DLLCR_OVRDVAL_MASK               (0x7E00U)
#define FLEXSPI_DLLCR_OVRDVAL_SHIFT              (9U)
/*! OVRDVAL - Slave clock delay line delay cell number selection override value. */
#define FLEXSPI_DLLCR_OVRDVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
/*! @} */

/* The count of FLEXSPI_DLLCR */
#define FLEXSPI_DLLCR_COUNT                      (2U)

/*! @name STS0 - Status Register 0 */
/*! @{ */

#define FLEXSPI_STS0_SEQIDLE_MASK                (0x1U)
#define FLEXSPI_STS0_SEQIDLE_SHIFT               (0U)
/*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command
 *    sequence executing on FlexSPI interface.
 */
#define FLEXSPI_STS0_SEQIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)

#define FLEXSPI_STS0_ARBIDLE_MASK                (0x2U)
#define FLEXSPI_STS0_ARBIDLE_SHIFT               (1U)
/*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command
 *    sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state
 *    (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So
 *    this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
 */
#define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)

#define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
#define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
 *    by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
 *  0b00..Triggered by AHB read command.
 *  0b01..Triggered by AHB write command.
 *  0b10..Triggered by IP command (triggered by setting register bit IPCMD[TRG]).
 *  0b11..Triggered by suspended command (resumed).
 */
#define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)

#define FLEXSPI_STS0_DATALEARNPHASEA_MASK        (0xF0U)
#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT       (4U)
/*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning. */
#define FLEXSPI_STS0_DATALEARNPHASEA(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK)

#define FLEXSPI_STS0_DATALEARNPHASEB_MASK        (0xF00U)
#define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT       (8U)
/*! DATALEARNPHASEB - Indicate the sampling clock phase selection on Port B after Data Learning. */
#define FLEXSPI_STS0_DATALEARNPHASEB(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK)
/*! @} */

/*! @name STS1 - Status Register 1 */
/*! @{ */

#define FLEXSPI_STS1_AHBCMDERRID_MASK            (0xFU)
#define FLEXSPI_STS1_AHBCMDERRID_SHIFT           (0U)
/*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field
 *    will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
 */
#define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)

#define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
 *    cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
 *  0b0000..No error.
 *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
 *  0b0011..There is unknown instruction opcode in the sequence.
 *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
 *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
 *  0b1110..Sequence execution timeout.
 */
#define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)

#define FLEXSPI_STS1_IPCMDERRID_MASK             (0xF0000U)
#define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
/*! IPCMDERRID - Indicates the sequence Index when IP command error detected. */
#define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)

#define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
 *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
 *  0b0000..No error.
 *  0b0010..IP command with JMP_ON_CS instruction used in the sequence.
 *  0b0011..There is unknown instruction opcode in the sequence.
 *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
 *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
 *  0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
 *  0b1110..Sequence execution timeout.
 *  0b1111..Flash boundary crossed.
 */
#define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
/*! @} */

/*! @name STS2 - Status Register 2 */
/*! @{ */

#define FLEXSPI_STS2_ASLVLOCK_MASK               (0x1U)
#define FLEXSPI_STS2_ASLVLOCK_SHIFT              (0U)
/*! ASLVLOCK - Flash A sample clock slave delay line locked. */
#define FLEXSPI_STS2_ASLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)

#define FLEXSPI_STS2_AREFLOCK_MASK               (0x2U)
#define FLEXSPI_STS2_AREFLOCK_SHIFT              (1U)
/*! AREFLOCK - Flash A sample clock reference delay line locked. */
#define FLEXSPI_STS2_AREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)

#define FLEXSPI_STS2_ASLVSEL_MASK                (0xFCU)
#define FLEXSPI_STS2_ASLVSEL_SHIFT               (2U)
/*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection . */
#define FLEXSPI_STS2_ASLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)

#define FLEXSPI_STS2_AREFSEL_MASK                (0x3F00U)
#define FLEXSPI_STS2_AREFSEL_SHIFT               (8U)
/*! AREFSEL - Flash A sample clock reference delay line delay cell number selection. */
#define FLEXSPI_STS2_AREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)

#define FLEXSPI_STS2_BSLVLOCK_MASK               (0x10000U)
#define FLEXSPI_STS2_BSLVLOCK_SHIFT              (16U)
/*! BSLVLOCK - Flash B sample clock slave delay line locked. */
#define FLEXSPI_STS2_BSLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)

#define FLEXSPI_STS2_BREFLOCK_MASK               (0x20000U)
#define FLEXSPI_STS2_BREFLOCK_SHIFT              (17U)
/*! BREFLOCK - Flash B sample clock reference delay line locked. */
#define FLEXSPI_STS2_BREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)

#define FLEXSPI_STS2_BSLVSEL_MASK                (0xFC0000U)
#define FLEXSPI_STS2_BSLVSEL_SHIFT               (18U)
/*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection. */
#define FLEXSPI_STS2_BSLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)

#define FLEXSPI_STS2_BREFSEL_MASK                (0x3F000000U)
#define FLEXSPI_STS2_BREFSEL_SHIFT               (24U)
/*! BREFSEL - Flash B sample clock reference delay line delay cell number selection. */
#define FLEXSPI_STS2_BREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
/*! @} */

/*! @name AHBSPNDSTS - AHB Suspend Status Register */
/*! @{ */

#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK           (0x1U)
#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT          (0U)
/*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended. */
#define FLEXSPI_AHBSPNDSTS_ACTIVE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)

#define FLEXSPI_AHBSPNDSTS_BUFID_MASK            (0xEU)
#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT           (1U)
/*! BUFID - AHB RX BUF ID for suspended command sequence. */
#define FLEXSPI_AHBSPNDSTS_BUFID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)

#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK           (0xFFFF0000U)
#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT          (16U)
/*! DATLFT - Left Data size for suspended command sequence (in byte). */
#define FLEXSPI_AHBSPNDSTS_DATLFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
/*! @} */

/*! @name IPRXFSTS - IP RX FIFO Status Register */
/*! @{ */

#define FLEXSPI_IPRXFSTS_FILL_MASK               (0xFFU)
#define FLEXSPI_IPRXFSTS_FILL_SHIFT              (0U)
/*! FILL - Fill level of IP RX FIFO. */
#define FLEXSPI_IPRXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)

#define FLEXSPI_IPRXFSTS_RDCNTR_MASK             (0xFFFF0000U)
#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT            (16U)
/*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits. */
#define FLEXSPI_IPRXFSTS_RDCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
/*! @} */

/*! @name IPTXFSTS - IP TX FIFO Status Register */
/*! @{ */

#define FLEXSPI_IPTXFSTS_FILL_MASK               (0xFFU)
#define FLEXSPI_IPTXFSTS_FILL_SHIFT              (0U)
/*! FILL - Fill level of IP TX FIFO. */
#define FLEXSPI_IPTXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)

#define FLEXSPI_IPTXFSTS_WRCNTR_MASK             (0xFFFF0000U)
#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT            (16U)
/*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits. */
#define FLEXSPI_IPTXFSTS_WRCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
/*! @} */

/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
/*! @{ */

#define FLEXSPI_RFDR_RXDATA_MASK                 (0xFFFFFFFFU)
#define FLEXSPI_RFDR_RXDATA_SHIFT                (0U)
/*! RXDATA - RX Data */
#define FLEXSPI_RFDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
/*! @} */

/* The count of FLEXSPI_RFDR */
#define FLEXSPI_RFDR_COUNT                       (32U)

/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
/*! @{ */

#define FLEXSPI_TFDR_TXDATA_MASK                 (0xFFFFFFFFU)
#define FLEXSPI_TFDR_TXDATA_SHIFT                (0U)
/*! TXDATA - TX Data */
#define FLEXSPI_TFDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
/*! @} */

/* The count of FLEXSPI_TFDR */
#define FLEXSPI_TFDR_COUNT                       (32U)

/*! @name LUT - LUT 0..LUT 63 */
/*! @{ */

#define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
#define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
/*! OPERAND0 - OPERAND0 */
#define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)

#define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
#define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
/*! NUM_PADS0 - NUM_PADS0 */
#define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)

#define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
#define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
/*! OPCODE0 - OPCODE */
#define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)

#define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
#define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
/*! OPERAND1 - OPERAND1 */
#define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)

#define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
#define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
/*! NUM_PADS1 - NUM_PADS1 */
#define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)

#define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
#define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
/*! OPCODE1 - OPCODE1 */
#define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
/*! @} */

/* The count of FLEXSPI_LUT */
#define FLEXSPI_LUT_COUNT                        (64U)


/*!
 * @}
 */ /* end of group FLEXSPI_Register_Masks */


/* FLEXSPI - Peripheral instance base addresses */
/** Peripheral FLEXSPI0 base address */
#define FLEXSPI0_BASE                            (0x28039000u)
/** Peripheral FLEXSPI0 base pointer */
#define FLEXSPI0                                 ((FLEXSPI_Type *)FLEXSPI0_BASE)
/** Peripheral FLEXSPI1 base address */
#define FLEXSPI1_BASE                            (0x28092000u)
/** Peripheral FLEXSPI1 base pointer */
#define FLEXSPI1                                 ((FLEXSPI_Type *)FLEXSPI1_BASE)
/** Peripheral FLEXSPI2 base address */
#define FLEXSPI2_BASE                            (0x29810000u)
/** Peripheral FLEXSPI2 base pointer */
#define FLEXSPI2                                 ((FLEXSPI_Type *)FLEXSPI2_BASE)
/** Array initializer of FLEXSPI peripheral base addresses */
#define FLEXSPI_BASE_ADDRS                       { FLEXSPI0_BASE, FLEXSPI1_BASE, FLEXSPI2_BASE }
/** Array initializer of FLEXSPI peripheral base pointers */
#define FLEXSPI_BASE_PTRS                        { FLEXSPI0, FLEXSPI1, FLEXSPI2 }
/* FlexSPI0 AMBA address. */
#define FlexSPI0_AMBA_BASE                       (0x04000000U)
/* FlexSPI1 AMBA address. */
#define FlexSPI1_AMBA_BASE                       (0x40000000U)
/* FlexSPI2 AMBA address. */
#define FlexSPI2_AMBA_BASE                       (0x60000000U)


/*!
 * @}
 */ /* end of group FLEXSPI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I2S Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
 * @{
 */

/** I2S - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
  __IO uint32_t TCSR;                              /**< Transmit Control, offset: 0x8 */
  __IO uint32_t TCR1;                              /**< Transmit Configuration 1, offset: 0xC */
  __IO uint32_t TCR2;                              /**< Transmit Configuration 2, offset: 0x10 */
  __IO uint32_t TCR3;                              /**< Transmit Configuration 3, offset: 0x14 */
  __IO uint32_t TCR4;                              /**< Transmit Configuration 4, offset: 0x18 */
  __IO uint32_t TCR5;                              /**< Transmit Configuration 5, offset: 0x1C */
  __O  uint32_t TDR[4];                            /**< Transmit Data, array offset: 0x20, array step: 0x4, irregular array, not all indices are valid */
       uint8_t RESERVED_0[16];
  __I  uint32_t TFR[4];                            /**< Transmit FIFO, array offset: 0x40, array step: 0x4, irregular array, not all indices are valid */
       uint8_t RESERVED_1[16];
  __IO uint32_t TMR;                               /**< Transmit Mask, offset: 0x60 */
       uint8_t RESERVED_2[12];
  __IO uint32_t TTCR;                              /**< Transmit Timestamp Control, offset: 0x70 */
  __I  uint32_t TTSR;                              /**< Transmit Timestamp, offset: 0x74 */
  __I  uint32_t TBCR;                              /**< Transmit Bit Count, offset: 0x78 */
  __I  uint32_t TBCTR;                             /**< Transmit Bit Count Timestamp, offset: 0x7C */
       uint8_t RESERVED_3[8];
  __IO uint32_t RCSR;                              /**< Receive Control, offset: 0x88 */
  __IO uint32_t RCR1;                              /**< Receive Configuration 1, offset: 0x8C */
  __IO uint32_t RCR2;                              /**< Receive Configuration 2, offset: 0x90 */
  __IO uint32_t RCR3;                              /**< Receive Configuration 3, offset: 0x94 */
  __IO uint32_t RCR4;                              /**< Receive Configuration 4, offset: 0x98 */
  __IO uint32_t RCR5;                              /**< Receive Configuration 5, offset: 0x9C */
  __I  uint32_t RDR[4];                            /**< Receive Data, array offset: 0xA0, array step: 0x4, irregular array, not all indices are valid */
       uint8_t RESERVED_4[16];
  __I  uint32_t RFR[4];                            /**< Receive FIFO, array offset: 0xC0, array step: 0x4, irregular array, not all indices are valid */
       uint8_t RESERVED_5[16];
  __IO uint32_t RMR;                               /**< Receive Mask, offset: 0xE0 */
       uint8_t RESERVED_6[12];
  __IO uint32_t RTCR;                              /**< Receive Timestamp Control, offset: 0xF0 */
  __I  uint32_t RTSR;                              /**< Receive Timestamp, offset: 0xF4 */
  __I  uint32_t RBCR;                              /**< Receive Bit Count, offset: 0xF8 */
  __I  uint32_t RBCTR;                             /**< Receive Bit Count Timestamp, offset: 0xFC */
} I2S_Type;

/* ----------------------------------------------------------------------------
   -- I2S Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2S_Register_Masks I2S Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define I2S_VERID_FEATURE_MASK                   (0xFFFFU)
#define I2S_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000000..Standard feature set.
 *  0b0000000000000010..Standard feature set with Timestamp Registers.
 */
#define I2S_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)

#define I2S_VERID_MINOR_MASK                     (0xFF0000U)
#define I2S_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number */
#define I2S_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)

#define I2S_VERID_MAJOR_MASK                     (0xFF000000U)
#define I2S_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number */
#define I2S_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define I2S_PARAM_DATALINE_MASK                  (0xFU)
#define I2S_PARAM_DATALINE_SHIFT                 (0U)
/*! DATALINE - Number of Datalines */
#define I2S_PARAM_DATALINE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)

#define I2S_PARAM_FIFO_MASK                      (0xF00U)
#define I2S_PARAM_FIFO_SHIFT                     (8U)
/*! FIFO - FIFO Size */
#define I2S_PARAM_FIFO(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)

#define I2S_PARAM_FRAME_MASK                     (0xF0000U)
#define I2S_PARAM_FRAME_SHIFT                    (16U)
/*! FRAME - Frame Size */
#define I2S_PARAM_FRAME(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
/*! @} */

/*! @name TCSR - Transmit Control */
/*! @{ */

#define I2S_TCSR_FRDE_MASK                       (0x1U)
#define I2S_TCSR_FRDE_SHIFT                      (0U)
/*! FRDE - FIFO Request DMA Enable
 *  0b0..Disables the DMA request.
 *  0b1..Enables the DMA request.
 */
#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)

#define I2S_TCSR_FWDE_MASK                       (0x2U)
#define I2S_TCSR_FWDE_SHIFT                      (1U)
/*! FWDE - FIFO Warning DMA Enable
 *  0b0..Disables the DMA request.
 *  0b1..Enables the DMA request.
 */
#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)

#define I2S_TCSR_FRIE_MASK                       (0x100U)
#define I2S_TCSR_FRIE_SHIFT                      (8U)
/*! FRIE - FIFO Request Interrupt Enable
 *  0b0..Disables the interrupt.
 *  0b1..Enables the interrupt.
 */
#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)

#define I2S_TCSR_FWIE_MASK                       (0x200U)
#define I2S_TCSR_FWIE_SHIFT                      (9U)
/*! FWIE - FIFO Warning Interrupt Enable
 *  0b0..Disables the interrupt.
 *  0b1..Enables the interrupt.
 */
#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)

#define I2S_TCSR_FEIE_MASK                       (0x400U)
#define I2S_TCSR_FEIE_SHIFT                      (10U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Disables the interrupt.
 *  0b1..Enables the interrupt.
 */
#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)

#define I2S_TCSR_SEIE_MASK                       (0x800U)
#define I2S_TCSR_SEIE_SHIFT                      (11U)
/*! SEIE - Sync Error Interrupt Enable
 *  0b0..Disables interrupt.
 *  0b1..Enables interrupt.
 */
#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)

#define I2S_TCSR_WSIE_MASK                       (0x1000U)
#define I2S_TCSR_WSIE_SHIFT                      (12U)
/*! WSIE - Word Start Interrupt Enable
 *  0b0..Disables interrupt.
 *  0b1..Enables interrupt.
 */
#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)

#define I2S_TCSR_FRF_MASK                        (0x10000U)
#define I2S_TCSR_FRF_SHIFT                       (16U)
/*! FRF - FIFO Request Flag
 *  0b0..Transmit FIFO watermark has not been reached.
 *  0b1..Transmit FIFO watermark has been reached.
 */
#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)

#define I2S_TCSR_FWF_MASK                        (0x20000U)
#define I2S_TCSR_FWF_SHIFT                       (17U)
/*! FWF - FIFO Warning Flag
 *  0b0..No enabled transmit FIFO is empty.
 *  0b1..Enabled transmit FIFO is empty.
 */
#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)

#define I2S_TCSR_FEF_MASK                        (0x40000U)
#define I2S_TCSR_FEF_SHIFT                       (18U)
/*! FEF - FIFO Error Flag
 *  0b0..Transmit underrun not detected.
 *  0b1..Transmit underrun detected.
 */
#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)

#define I2S_TCSR_SEF_MASK                        (0x80000U)
#define I2S_TCSR_SEF_SHIFT                       (19U)
/*! SEF - Sync Error Flag
 *  0b0..Sync error not detected.
 *  0b1..Frame sync error detected.
 */
#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)

#define I2S_TCSR_WSF_MASK                        (0x100000U)
#define I2S_TCSR_WSF_SHIFT                       (20U)
/*! WSF - Word Start Flag
 *  0b0..Start of word not detected.
 *  0b1..Start of word detected.
 */
#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)

#define I2S_TCSR_SR_MASK                         (0x1000000U)
#define I2S_TCSR_SR_SHIFT                        (24U)
/*! SR - Software Reset
 *  0b0..No effect.
 *  0b1..Software reset.
 */
#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)

#define I2S_TCSR_FR_MASK                         (0x2000000U)
#define I2S_TCSR_FR_SHIFT                        (25U)
/*! FR - FIFO Reset
 *  0b0..No effect.
 *  0b1..FIFO reset.
 */
#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)

#define I2S_TCSR_BCE_MASK                        (0x10000000U)
#define I2S_TCSR_BCE_SHIFT                       (28U)
/*! BCE - Bit Clock Enable
 *  0b0..Transmit bit clock is disabled.
 *  0b1..Transmit bit clock is enabled.
 */
#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)

#define I2S_TCSR_DBGE_MASK                       (0x20000000U)
#define I2S_TCSR_DBGE_SHIFT                      (29U)
/*! DBGE - Debug Enable
 *  0b0..Transmitter is disabled in Debug mode, after completing the current frame.
 *  0b1..Transmitter is enabled in Debug mode.
 */
#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)

#define I2S_TCSR_STOPE_MASK                      (0x40000000U)
#define I2S_TCSR_STOPE_SHIFT                     (30U)
/*! STOPE - Stop Enable
 *  0b0..Transmitter disabled in Stop mode.
 *  0b1..Transmitter enabled in Stop mode.
 */
#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)

#define I2S_TCSR_TE_MASK                         (0x80000000U)
#define I2S_TCSR_TE_SHIFT                        (31U)
/*! TE - Transmitter Enable
 *  0b0..Transmitter is disabled.
 *  0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
 */
#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
/*! @} */

/*! @name TCR1 - Transmit Configuration 1 */
/*! @{ */

#define I2S_TCR1_TFW_MASK                        (0xFU)
#define I2S_TCR1_TFW_SHIFT                       (0U)
/*! TFW - Transmit FIFO Watermark */
#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
/*! @} */

/*! @name TCR2 - Transmit Configuration 2 */
/*! @{ */

#define I2S_TCR2_DIV_MASK                        (0xFFU)
#define I2S_TCR2_DIV_SHIFT                       (0U)
/*! DIV - Bit Clock Divide */
#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)

#define I2S_TCR2_BYP_MASK                        (0x800000U)
#define I2S_TCR2_BYP_SHIFT                       (23U)
/*! BYP - Bit Clock Bypass
 *  0b0..Internal bit clock is generated from bit clock divider.
 *  0b1..Internal bit clock is divide by one of the audio master clock.
 */
#define I2S_TCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)

#define I2S_TCR2_BCD_MASK                        (0x1000000U)
#define I2S_TCR2_BCD_SHIFT                       (24U)
/*! BCD - Bit Clock Direction
 *  0b0..Bit clock is generated externally in Slave mode.
 *  0b1..Bit clock is generated internally in Master mode.
 */
#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)

#define I2S_TCR2_BCP_MASK                        (0x2000000U)
#define I2S_TCR2_BCP_SHIFT                       (25U)
/*! BCP - Bit Clock Polarity
 *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
 *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
 */
#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)

#define I2S_TCR2_MSEL_MASK                       (0xC000000U)
#define I2S_TCR2_MSEL_SHIFT                      (26U)
/*! MSEL - MCLK Select
 *  0b00..Bus Clock selected.
 *  0b01..Master Clock (MCLK) 1 option selected.
 *  0b10..Master Clock (MCLK) 2 option selected.
 *  0b11..Master Clock (MCLK) 3 option selected.
 */
#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)

#define I2S_TCR2_BCI_MASK                        (0x10000000U)
#define I2S_TCR2_BCI_SHIFT                       (28U)
/*! BCI - Bit Clock Input
 *  0b0..No effect.
 *  0b1..Internal logic is clocked as if bit clock was externally generated.
 */
#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)

#define I2S_TCR2_BCS_MASK                        (0x20000000U)
#define I2S_TCR2_BCS_SHIFT                       (29U)
/*! BCS - Bit Clock Swap
 *  0b0..Use the normal bit clock source.
 *  0b1..Swap the bit clock source.
 */
#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)

#define I2S_TCR2_SYNC_MASK                       (0xC0000000U)
#define I2S_TCR2_SYNC_SHIFT                      (30U)
/*! SYNC - Synchronous Mode
 *  0b00..Asynchronous mode.
 *  0b01..Synchronous with receiver.
 *  0b10..Synchronous with another SAI transmitter
 *  0b11..Synchronous with another SAI receiver
 */
#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
/*! @} */

/*! @name TCR3 - Transmit Configuration 3 */
/*! @{ */

#define I2S_TCR3_WDFL_MASK                       (0x1FU)
#define I2S_TCR3_WDFL_SHIFT                      (0U)
/*! WDFL - Word Flag Configuration */
#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)

#define I2S_TCR3_TCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
#define I2S_TCR3_TCE_SHIFT                       (16U)
/*! TCE - Transmit Channel Enable */
#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */

#define I2S_TCR3_CFR_MASK                        (0xF000000U)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
#define I2S_TCR3_CFR_SHIFT                       (24U)
/*! CFR - Channel FIFO Reset */
#define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
/*! @} */

/*! @name TCR4 - Transmit Configuration 4 */
/*! @{ */

#define I2S_TCR4_FSD_MASK                        (0x1U)
#define I2S_TCR4_FSD_SHIFT                       (0U)
/*! FSD - Frame Sync Direction
 *  0b0..Frame sync is generated externally in Slave mode.
 *  0b1..Frame sync is generated internally in Master mode.
 */
#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)

#define I2S_TCR4_FSP_MASK                        (0x2U)
#define I2S_TCR4_FSP_SHIFT                       (1U)
/*! FSP - Frame Sync Polarity
 *  0b0..Frame sync is active high.
 *  0b1..Frame sync is active low.
 */
#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)

#define I2S_TCR4_ONDEM_MASK                      (0x4U)
#define I2S_TCR4_ONDEM_SHIFT                     (2U)
/*! ONDEM - On Demand Mode
 *  0b0..Internal frame sync is generated continuously.
 *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
 */
#define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)

#define I2S_TCR4_FSE_MASK                        (0x8U)
#define I2S_TCR4_FSE_SHIFT                       (3U)
/*! FSE - Frame Sync Early
 *  0b0..Frame sync asserts with the first bit of the frame.
 *  0b1..Frame sync asserts one bit before the first bit of the frame.
 */
#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)

#define I2S_TCR4_MF_MASK                         (0x10U)
#define I2S_TCR4_MF_SHIFT                        (4U)
/*! MF - MSB First
 *  0b0..LSB is transmitted first.
 *  0b1..MSB is transmitted first.
 */
#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)

#define I2S_TCR4_CHMOD_MASK                      (0x20U)
#define I2S_TCR4_CHMOD_SHIFT                     (5U)
/*! CHMOD - Channel Mode
 *  0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
 *  0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
 */
#define I2S_TCR4_CHMOD(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)

#define I2S_TCR4_SYWD_MASK                       (0x1F00U)
#define I2S_TCR4_SYWD_SHIFT                      (8U)
/*! SYWD - Sync Width */
#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)

#define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
#define I2S_TCR4_FRSZ_SHIFT                      (16U)
/*! FRSZ - Frame size */
#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)

#define I2S_TCR4_FPACK_MASK                      (0x3000000U)
#define I2S_TCR4_FPACK_SHIFT                     (24U)
/*! FPACK - FIFO Packing Mode
 *  0b00..FIFO packing is disabled.
 *  0b01..Reserved
 *  0b10..8-bit FIFO packing is enabled.
 *  0b11..16-bit FIFO packing is enabled.
 */
#define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)

#define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
#define I2S_TCR4_FCOMB_SHIFT                     (26U)
/*! FCOMB - FIFO Combine Mode
 *  0b00..FIFO combine mode disabled.
 *  0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
 *  0b10..FIFO combine mode enabled on FIFO writes (by software).
 *  0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
 */
#define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)

#define I2S_TCR4_FCONT_MASK                      (0x10000000U)
#define I2S_TCR4_FCONT_SHIFT                     (28U)
/*! FCONT - FIFO Continue on Error
 *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
 *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
 */
#define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
/*! @} */

/*! @name TCR5 - Transmit Configuration 5 */
/*! @{ */

#define I2S_TCR5_FBT_MASK                        (0x1F00U)
#define I2S_TCR5_FBT_SHIFT                       (8U)
/*! FBT - First Bit Shifted */
#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)

#define I2S_TCR5_W0W_MASK                        (0x1F0000U)
#define I2S_TCR5_W0W_SHIFT                       (16U)
/*! W0W - Word 0 Width */
#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)

#define I2S_TCR5_WNW_MASK                        (0x1F000000U)
#define I2S_TCR5_WNW_SHIFT                       (24U)
/*! WNW - Word N Width */
#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
/*! @} */

/*! @name TDR - Transmit Data */
/*! @{ */

#define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
#define I2S_TDR_TDR_SHIFT                        (0U)
/*! TDR - Transmit Data Register */
#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
/*! @} */

/* The count of I2S_TDR */
#define I2S_TDR_COUNT                            (4U)

/*! @name TFR - Transmit FIFO */
/*! @{ */

#define I2S_TFR_RFP_MASK                         (0x1FU)
#define I2S_TFR_RFP_SHIFT                        (0U)
/*! RFP - Read FIFO Pointer */
#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)

#define I2S_TFR_WFP_MASK                         (0x1F0000U)
#define I2S_TFR_WFP_SHIFT                        (16U)
/*! WFP - Write FIFO Pointer */
#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)

#define I2S_TFR_WCP_MASK                         (0x80000000U)
#define I2S_TFR_WCP_SHIFT                        (31U)
/*! WCP - Write Channel Pointer
 *  0b0..No effect.
 *  0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
 */
#define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
/*! @} */

/* The count of I2S_TFR */
#define I2S_TFR_COUNT                            (4U)

/*! @name TMR - Transmit Mask */
/*! @{ */

#define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
#define I2S_TMR_TWM_SHIFT                        (0U)
/*! TWM - Transmit Word Mask
 *  0b00000000000000000000000000000000..Word N is enabled.
 *  0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
 */
#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
/*! @} */

/*! @name TTCR - Transmit Timestamp Control */
/*! @{ */

#define I2S_TTCR_TSEN_MASK                       (0x1U)
#define I2S_TTCR_TSEN_SHIFT                      (0U)
/*! TSEN - Timestamp Enable
 *  0b0..Timestamp counter is disabled.
 *  0b1..Timestamp counter is enabled.
 */
#define I2S_TTCR_TSEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSEN_SHIFT)) & I2S_TTCR_TSEN_MASK)

#define I2S_TTCR_TSINC_MASK                      (0x2U)
#define I2S_TTCR_TSINC_SHIFT                     (1U)
/*! TSINC - Timestamp Increment
 *  0b0..Timestamp counter starts to increment when enabled and the bit counter has incremented.
 *  0b1..Timestamp counter starts to increment when enabled.
 */
#define I2S_TTCR_TSINC(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSINC_SHIFT)) & I2S_TTCR_TSINC_MASK)

#define I2S_TTCR_RTSC_MASK                       (0x100U)
#define I2S_TTCR_RTSC_SHIFT                      (8U)
/*! RTSC - Reset Timestamp Counter
 *  0b0..Timestamp counter is not reset.
 *  0b1..Timestamp counter is reset.
 */
#define I2S_TTCR_RTSC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RTSC_SHIFT)) & I2S_TTCR_RTSC_MASK)

#define I2S_TTCR_RBC_MASK                        (0x200U)
#define I2S_TTCR_RBC_SHIFT                       (9U)
/*! RBC - Reset Bit Counter
 *  0b0..Bit counter is not reset.
 *  0b1..Bit counter is reset.
 */
#define I2S_TTCR_RBC(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RBC_SHIFT)) & I2S_TTCR_RBC_MASK)
/*! @} */

/*! @name TTSR - Transmit Timestamp */
/*! @{ */

#define I2S_TTSR_TSC_MASK                        (0xFFFFFFFFU)
#define I2S_TTSR_TSC_SHIFT                       (0U)
/*! TSC - Timestamp Counter */
#define I2S_TTSR_TSC(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TTSR_TSC_SHIFT)) & I2S_TTSR_TSC_MASK)
/*! @} */

/*! @name TBCR - Transmit Bit Count */
/*! @{ */

#define I2S_TBCR_BCNT_MASK                       (0xFFFFFFFFU)
#define I2S_TBCR_BCNT_SHIFT                      (0U)
/*! BCNT - Bit Counter */
#define I2S_TBCR_BCNT(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TBCR_BCNT_SHIFT)) & I2S_TBCR_BCNT_MASK)
/*! @} */

/*! @name TBCTR - Transmit Bit Count Timestamp */
/*! @{ */

#define I2S_TBCTR_BCTS_MASK                      (0xFFFFFFFFU)
#define I2S_TBCTR_BCTS_SHIFT                     (0U)
/*! BCTS - Bit Timestamp */
#define I2S_TBCTR_BCTS(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TBCTR_BCTS_SHIFT)) & I2S_TBCTR_BCTS_MASK)
/*! @} */

/*! @name RCSR - Receive Control */
/*! @{ */

#define I2S_RCSR_FRDE_MASK                       (0x1U)
#define I2S_RCSR_FRDE_SHIFT                      (0U)
/*! FRDE - FIFO Request DMA Enable
 *  0b0..Disables the DMA request.
 *  0b1..Enables the DMA request.
 */
#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)

#define I2S_RCSR_FWDE_MASK                       (0x2U)
#define I2S_RCSR_FWDE_SHIFT                      (1U)
/*! FWDE - FIFO Warning DMA Enable
 *  0b0..Disables the DMA request.
 *  0b1..Enables the DMA request.
 */
#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)

#define I2S_RCSR_FRIE_MASK                       (0x100U)
#define I2S_RCSR_FRIE_SHIFT                      (8U)
/*! FRIE - FIFO Request Interrupt Enable
 *  0b0..Disables the interrupt.
 *  0b1..Enables the interrupt.
 */
#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)

#define I2S_RCSR_FWIE_MASK                       (0x200U)
#define I2S_RCSR_FWIE_SHIFT                      (9U)
/*! FWIE - FIFO Warning Interrupt Enable
 *  0b0..Disables the interrupt.
 *  0b1..Enables the interrupt.
 */
#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)

#define I2S_RCSR_FEIE_MASK                       (0x400U)
#define I2S_RCSR_FEIE_SHIFT                      (10U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Disables the interrupt.
 *  0b1..Enables the interrupt.
 */
#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)

#define I2S_RCSR_SEIE_MASK                       (0x800U)
#define I2S_RCSR_SEIE_SHIFT                      (11U)
/*! SEIE - Sync Error Interrupt Enable
 *  0b0..Disables interrupt.
 *  0b1..Enables interrupt.
 */
#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)

#define I2S_RCSR_WSIE_MASK                       (0x1000U)
#define I2S_RCSR_WSIE_SHIFT                      (12U)
/*! WSIE - Word Start Interrupt Enable
 *  0b0..Disables interrupt.
 *  0b1..Enables interrupt.
 */
#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)

#define I2S_RCSR_FRF_MASK                        (0x10000U)
#define I2S_RCSR_FRF_SHIFT                       (16U)
/*! FRF - FIFO Request Flag
 *  0b0..Receive FIFO watermark not reached.
 *  0b1..Receive FIFO watermark has been reached.
 */
#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)

#define I2S_RCSR_FWF_MASK                        (0x20000U)
#define I2S_RCSR_FWF_SHIFT                       (17U)
/*! FWF - FIFO Warning Flag
 *  0b0..No enabled receive FIFO is full.
 *  0b1..Enabled receive FIFO is full.
 */
#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)

#define I2S_RCSR_FEF_MASK                        (0x40000U)
#define I2S_RCSR_FEF_SHIFT                       (18U)
/*! FEF - FIFO Error Flag
 *  0b0..Receive overflow not detected.
 *  0b1..Receive overflow detected.
 */
#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)

#define I2S_RCSR_SEF_MASK                        (0x80000U)
#define I2S_RCSR_SEF_SHIFT                       (19U)
/*! SEF - Sync Error Flag
 *  0b0..Sync error not detected.
 *  0b1..Frame sync error detected.
 */
#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)

#define I2S_RCSR_WSF_MASK                        (0x100000U)
#define I2S_RCSR_WSF_SHIFT                       (20U)
/*! WSF - Word Start Flag
 *  0b0..Start of word not detected.
 *  0b1..Start of word detected.
 */
#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)

#define I2S_RCSR_SR_MASK                         (0x1000000U)
#define I2S_RCSR_SR_SHIFT                        (24U)
/*! SR - Software Reset
 *  0b0..No effect.
 *  0b1..Software reset.
 */
#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)

#define I2S_RCSR_FR_MASK                         (0x2000000U)
#define I2S_RCSR_FR_SHIFT                        (25U)
/*! FR - FIFO Reset
 *  0b0..No effect.
 *  0b1..FIFO reset.
 */
#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)

#define I2S_RCSR_BCE_MASK                        (0x10000000U)
#define I2S_RCSR_BCE_SHIFT                       (28U)
/*! BCE - Bit Clock Enable
 *  0b0..Receive bit clock is disabled.
 *  0b1..Receive bit clock is enabled.
 */
#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)

#define I2S_RCSR_DBGE_MASK                       (0x20000000U)
#define I2S_RCSR_DBGE_SHIFT                      (29U)
/*! DBGE - Debug Enable
 *  0b0..Receiver is disabled in Debug mode, after completing the current frame.
 *  0b1..Receiver is enabled in Debug mode.
 */
#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)

#define I2S_RCSR_STOPE_MASK                      (0x40000000U)
#define I2S_RCSR_STOPE_SHIFT                     (30U)
/*! STOPE - Stop Enable
 *  0b0..Receiver disabled in Stop mode.
 *  0b1..Receiver enabled in Stop mode.
 */
#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)

#define I2S_RCSR_RE_MASK                         (0x80000000U)
#define I2S_RCSR_RE_SHIFT                        (31U)
/*! RE - Receiver Enable
 *  0b0..Receiver is disabled.
 *  0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
 */
#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
/*! @} */

/*! @name RCR1 - Receive Configuration 1 */
/*! @{ */

#define I2S_RCR1_RFW_MASK                        (0xFU)
#define I2S_RCR1_RFW_SHIFT                       (0U)
/*! RFW - Receive FIFO Watermark */
#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
/*! @} */

/*! @name RCR2 - Receive Configuration 2 */
/*! @{ */

#define I2S_RCR2_DIV_MASK                        (0xFFU)
#define I2S_RCR2_DIV_SHIFT                       (0U)
/*! DIV - Bit Clock Divide */
#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)

#define I2S_RCR2_BYP_MASK                        (0x800000U)
#define I2S_RCR2_BYP_SHIFT                       (23U)
/*! BYP - Bit Clock Bypass
 *  0b0..Internal bit clock is generated from bit clock divider.
 *  0b1..Internal bit clock is divide by one of the audio master clock.
 */
#define I2S_RCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)

#define I2S_RCR2_BCD_MASK                        (0x1000000U)
#define I2S_RCR2_BCD_SHIFT                       (24U)
/*! BCD - Bit Clock Direction
 *  0b0..Bit clock is generated externally in Slave mode.
 *  0b1..Bit clock is generated internally in Master mode.
 */
#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)

#define I2S_RCR2_BCP_MASK                        (0x2000000U)
#define I2S_RCR2_BCP_SHIFT                       (25U)
/*! BCP - Bit Clock Polarity
 *  0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
 *  0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
 */
#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)

#define I2S_RCR2_MSEL_MASK                       (0xC000000U)
#define I2S_RCR2_MSEL_SHIFT                      (26U)
/*! MSEL - MCLK Select
 *  0b00..Bus Clock selected.
 *  0b01..Master Clock (MCLK) 1 option selected.
 *  0b10..Master Clock (MCLK) 2 option selected.
 *  0b11..Master Clock (MCLK) 3 option selected.
 */
#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)

#define I2S_RCR2_BCI_MASK                        (0x10000000U)
#define I2S_RCR2_BCI_SHIFT                       (28U)
/*! BCI - Bit Clock Input
 *  0b0..No effect.
 *  0b1..Internal logic is clocked as if bit clock was externally generated.
 */
#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)

#define I2S_RCR2_BCS_MASK                        (0x20000000U)
#define I2S_RCR2_BCS_SHIFT                       (29U)
/*! BCS - Bit Clock Swap
 *  0b0..Use the normal bit clock source.
 *  0b1..Swap the bit clock source.
 */
#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)

#define I2S_RCR2_SYNC_MASK                       (0xC0000000U)
#define I2S_RCR2_SYNC_SHIFT                      (30U)
/*! SYNC - Synchronous Mode
 *  0b00..Asynchronous mode.
 *  0b01..Synchronous with transmitter.
 *  0b10..Synchronous with another SAI receiver.
 *  0b11..Synchronous with another SAI transmitter.
 */
#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
/*! @} */

/*! @name RCR3 - Receive Configuration 3 */
/*! @{ */

#define I2S_RCR3_WDFL_MASK                       (0x1FU)
#define I2S_RCR3_WDFL_SHIFT                      (0U)
/*! WDFL - Word Flag Configuration */
#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)

#define I2S_RCR3_RCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
#define I2S_RCR3_RCE_SHIFT                       (16U)
/*! RCE - Receive Channel Enable */
#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */

#define I2S_RCR3_CFR_MASK                        (0xF000000U)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
#define I2S_RCR3_CFR_SHIFT                       (24U)
/*! CFR - Channel FIFO Reset */
#define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
/*! @} */

/*! @name RCR4 - Receive Configuration 4 */
/*! @{ */

#define I2S_RCR4_FSD_MASK                        (0x1U)
#define I2S_RCR4_FSD_SHIFT                       (0U)
/*! FSD - Frame Sync Direction
 *  0b0..Frame Sync is generated externally in Slave mode.
 *  0b1..Frame Sync is generated internally in Master mode.
 */
#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)

#define I2S_RCR4_FSP_MASK                        (0x2U)
#define I2S_RCR4_FSP_SHIFT                       (1U)
/*! FSP - Frame Sync Polarity
 *  0b0..Frame sync is active high.
 *  0b1..Frame sync is active low.
 */
#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)

#define I2S_RCR4_ONDEM_MASK                      (0x4U)
#define I2S_RCR4_ONDEM_SHIFT                     (2U)
/*! ONDEM - On Demand Mode
 *  0b0..Internal frame sync is generated continuously.
 *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
 */
#define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)

#define I2S_RCR4_FSE_MASK                        (0x8U)
#define I2S_RCR4_FSE_SHIFT                       (3U)
/*! FSE - Frame Sync Early
 *  0b0..Frame sync asserts with the first bit of the frame.
 *  0b1..Frame sync asserts one bit before the first bit of the frame.
 */
#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)

#define I2S_RCR4_MF_MASK                         (0x10U)
#define I2S_RCR4_MF_SHIFT                        (4U)
/*! MF - MSB First
 *  0b0..LSB is received first.
 *  0b1..MSB is received first.
 */
#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)

#define I2S_RCR4_SYWD_MASK                       (0x1F00U)
#define I2S_RCR4_SYWD_SHIFT                      (8U)
/*! SYWD - Sync Width */
#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)

#define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
#define I2S_RCR4_FRSZ_SHIFT                      (16U)
/*! FRSZ - Frame Size */
#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)

#define I2S_RCR4_FPACK_MASK                      (0x3000000U)
#define I2S_RCR4_FPACK_SHIFT                     (24U)
/*! FPACK - FIFO Packing Mode
 *  0b00..FIFO packing is disabled
 *  0b01..Reserved.
 *  0b10..8-bit FIFO packing is enabled
 *  0b11..16-bit FIFO packing is enabled
 */
#define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)

#define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
#define I2S_RCR4_FCOMB_SHIFT                     (26U)
/*! FCOMB - FIFO Combine Mode
 *  0b00..FIFO combine mode disabled.
 *  0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
 *  0b10..FIFO combine mode enabled on FIFO reads (by software).
 *  0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
 */
#define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)

#define I2S_RCR4_FCONT_MASK                      (0x10000000U)
#define I2S_RCR4_FCONT_SHIFT                     (28U)
/*! FCONT - FIFO Continue on Error
 *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
 *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
 */
#define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
/*! @} */

/*! @name RCR5 - Receive Configuration 5 */
/*! @{ */

#define I2S_RCR5_FBT_MASK                        (0x1F00U)
#define I2S_RCR5_FBT_SHIFT                       (8U)
/*! FBT - First Bit Shifted */
#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)

#define I2S_RCR5_W0W_MASK                        (0x1F0000U)
#define I2S_RCR5_W0W_SHIFT                       (16U)
/*! W0W - Word 0 Width */
#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)

#define I2S_RCR5_WNW_MASK                        (0x1F000000U)
#define I2S_RCR5_WNW_SHIFT                       (24U)
/*! WNW - Word N Width */
#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
/*! @} */

/*! @name RDR - Receive Data */
/*! @{ */

#define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
#define I2S_RDR_RDR_SHIFT                        (0U)
/*! RDR - Receive Data Register */
#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
/*! @} */

/* The count of I2S_RDR */
#define I2S_RDR_COUNT                            (4U)

/*! @name RFR - Receive FIFO */
/*! @{ */

#define I2S_RFR_RFP_MASK                         (0x1FU)
#define I2S_RFR_RFP_SHIFT                        (0U)
/*! RFP - Read FIFO Pointer */
#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)

#define I2S_RFR_RCP_MASK                         (0x8000U)
#define I2S_RFR_RCP_SHIFT                        (15U)
/*! RCP - Receive Channel Pointer
 *  0b0..No effect.
 *  0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
 */
#define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)

#define I2S_RFR_WFP_MASK                         (0x1F0000U)
#define I2S_RFR_WFP_SHIFT                        (16U)
/*! WFP - Write FIFO Pointer */
#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
/*! @} */

/* The count of I2S_RFR */
#define I2S_RFR_COUNT                            (4U)

/*! @name RMR - Receive Mask */
/*! @{ */

#define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
#define I2S_RMR_RWM_SHIFT                        (0U)
/*! RWM - Receive Word Mask
 *  0b00000000000000000000000000000000..Word N is enabled.
 *  0b00000000000000000000000000000001..Word N is masked.
 */
#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
/*! @} */

/*! @name RTCR - Receive Timestamp Control */
/*! @{ */

#define I2S_RTCR_TSEN_MASK                       (0x1U)
#define I2S_RTCR_TSEN_SHIFT                      (0U)
/*! TSEN - Timestamp Enable
 *  0b0..Timestamp counter is disabled.
 *  0b1..Timestamp counter is enabled.
 */
#define I2S_RTCR_TSEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSEN_SHIFT)) & I2S_RTCR_TSEN_MASK)

#define I2S_RTCR_TSINC_MASK                      (0x2U)
#define I2S_RTCR_TSINC_SHIFT                     (1U)
/*! TSINC - Timestamp Increment
 *  0b0..Timestamp counter starts to increment when enabled and the bit counter has incremented.
 *  0b1..Timestamp counter starts to increment when enabled.
 */
#define I2S_RTCR_TSINC(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSINC_SHIFT)) & I2S_RTCR_TSINC_MASK)

#define I2S_RTCR_RTSC_MASK                       (0x100U)
#define I2S_RTCR_RTSC_SHIFT                      (8U)
/*! RTSC - Reset Timestamp Counter
 *  0b0..Timestamp counter is not reset.
 *  0b1..Timestamp counter is reset.
 */
#define I2S_RTCR_RTSC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RTSC_SHIFT)) & I2S_RTCR_RTSC_MASK)

#define I2S_RTCR_RBC_MASK                        (0x200U)
#define I2S_RTCR_RBC_SHIFT                       (9U)
/*! RBC - Reset Bit Counter
 *  0b0..Bit counter is not reset.
 *  0b1..Bit counter is reset.
 */
#define I2S_RTCR_RBC(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RBC_SHIFT)) & I2S_RTCR_RBC_MASK)
/*! @} */

/*! @name RTSR - Receive Timestamp */
/*! @{ */

#define I2S_RTSR_TSC_MASK                        (0xFFFFFFFFU)
#define I2S_RTSR_TSC_SHIFT                       (0U)
/*! TSC - Timestamp Counter */
#define I2S_RTSR_TSC(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RTSR_TSC_SHIFT)) & I2S_RTSR_TSC_MASK)
/*! @} */

/*! @name RBCR - Receive Bit Count */
/*! @{ */

#define I2S_RBCR_BCNT_MASK                       (0xFFFFFFFFU)
#define I2S_RBCR_BCNT_SHIFT                      (0U)
/*! BCNT - Bit Counter */
#define I2S_RBCR_BCNT(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RBCR_BCNT_SHIFT)) & I2S_RBCR_BCNT_MASK)
/*! @} */

/*! @name RBCTR - Receive Bit Count Timestamp */
/*! @{ */

#define I2S_RBCTR_BCTS_MASK                      (0xFFFFFFFFU)
#define I2S_RBCTR_BCTS_SHIFT                     (0U)
/*! BCTS - Bit Timestamp */
#define I2S_RBCTR_BCTS(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RBCTR_BCTS_SHIFT)) & I2S_RBCTR_BCTS_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group I2S_Register_Masks */


/* I2S - Peripheral instance base addresses */
/** Peripheral SAI0 base address */
#define SAI0_BASE                                (0x2809C000u)
/** Peripheral SAI0 base pointer */
#define SAI0                                     ((I2S_Type *)SAI0_BASE)
/** Peripheral SAI1 base address */
#define SAI1_BASE                                (0x2809D000u)
/** Peripheral SAI1 base pointer */
#define SAI1                                     ((I2S_Type *)SAI1_BASE)
/** Peripheral SAI2 base address */
#define SAI2_BASE                                (0x2810F000u)
/** Peripheral SAI2 base pointer */
#define SAI2                                     ((I2S_Type *)SAI2_BASE)
/** Peripheral SAI3 base address */
#define SAI3_BASE                                (0x28110000u)
/** Peripheral SAI3 base pointer */
#define SAI3                                     ((I2S_Type *)SAI3_BASE)
/** Peripheral SAI4 base address */
#define SAI4_BASE                                (0x29880000u)
/** Peripheral SAI4 base pointer */
#define SAI4                                     ((I2S_Type *)SAI4_BASE)
/** Peripheral SAI5 base address */
#define SAI5_BASE                                (0x29890000u)
/** Peripheral SAI5 base pointer */
#define SAI5                                     ((I2S_Type *)SAI5_BASE)
/** Peripheral SAI6 base address */
#define SAI6_BASE                                (0x2DA90000u)
/** Peripheral SAI6 base pointer */
#define SAI6                                     ((I2S_Type *)SAI6_BASE)
/** Peripheral SAI7 base address */
#define SAI7_BASE                                (0x2DAA0000u)
/** Peripheral SAI7 base pointer */
#define SAI7                                     ((I2S_Type *)SAI7_BASE)
/** Array initializer of I2S peripheral base addresses */
#define I2S_BASE_ADDRS                           { SAI0_BASE, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE, SAI5_BASE, SAI6_BASE, SAI7_BASE }
/** Array initializer of I2S peripheral base pointers */
#define I2S_BASE_PTRS                            { SAI0, SAI1, SAI2, SAI3, SAI4, SAI5, SAI6, SAI7 }
/** Interrupt vectors for the I2S peripheral type */
#define I2S_RX_IRQS                              { SAI0_IRQn, SAI1_IRQn, NotAvail_IRQn, NotAvail_IRQn, SAI4_IRQn, SAI5_IRQn, SAI6_IRQn, SAI7_IRQn }
#define I2S_TX_IRQS                              { SAI0_IRQn, SAI1_IRQn, NotAvail_IRQn, NotAvail_IRQn, SAI4_IRQn, SAI5_IRQn, SAI6_IRQn, SAI7_IRQn }

/*!
 * @}
 */ /* end of group I2S_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I3C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer
 * @{
 */

/** I3C - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCONFIG;                           /**< Master Configuration Register, offset: 0x0 */
  __IO uint32_t SCONFIG;                           /**< Slave Configuration Register, offset: 0x4 */
  __IO uint32_t SSTATUS;                           /**< Slave Status Register, offset: 0x8 */
  __IO uint32_t SCTRL;                             /**< Slave Control Register, offset: 0xC */
  __IO uint32_t SINTSET;                           /**< Slave Interrupt Set Register, offset: 0x10 */
  __IO uint32_t SINTCLR;                           /**< Slave Interrupt Clear Register, offset: 0x14 */
  __I  uint32_t SINTMASKED;                        /**< Slave Interrupt Mask Register, offset: 0x18 */
  __IO uint32_t SERRWARN;                          /**< Slave Errors and Warnings Register, offset: 0x1C */
  __IO uint32_t SDMACTRL;                          /**< Slave DMA Control Register, offset: 0x20 */
       uint8_t RESERVED_0[8];
  __IO uint32_t SDATACTRL;                         /**< Slave Data Control Register, offset: 0x2C */
  __O  uint32_t SWDATAB;                           /**< Slave Write Data Byte Register, offset: 0x30 */
  __O  uint32_t SWDATABE;                          /**< Slave Write Data Byte End, offset: 0x34 */
  __O  uint32_t SWDATAH;                           /**< Slave Write Data Half-word Register, offset: 0x38 */
  __O  uint32_t SWDATAHE;                          /**< Slave Write Data Half-word End Register, offset: 0x3C */
  __I  uint32_t SRDATAB;                           /**< Slave Read Data Byte Register, offset: 0x40 */
       uint8_t RESERVED_1[4];
  __I  uint32_t SRDATAH;                           /**< Slave Read Data Half-word Register, offset: 0x48 */
       uint8_t RESERVED_2[20];
  __I  uint32_t SCAPABILITIES;                     /**< Slave Capabilities Register, offset: 0x60 */
  __IO uint32_t SDYNADDR;                          /**< Slave Dynamic Address Register, offset: 0x64 */
  __IO uint32_t SMAXLIMITS;                        /**< Slave Maximum Limits Register, offset: 0x68 */
  __IO uint32_t SIDPARTNO;                         /**< Slave ID Part Number Register, offset: 0x6C */
  __IO uint32_t SIDEXT;                            /**< Slave ID Extension Register, offset: 0x70 */
  __IO uint32_t SVENDORID;                         /**< Slave Vendor ID Register, offset: 0x74 */
  __IO uint32_t STCCLOCK;                          /**< Slave Time Control Clock Register, offset: 0x78 */
  __I  uint32_t SMSGMAPADDR;                       /**< Slave Message-Mapped Address Register, offset: 0x7C */
       uint8_t RESERVED_3[4];
  __IO uint32_t MCTRL;                             /**< Master Main Control Register, offset: 0x84 */
  __IO uint32_t MSTATUS;                           /**< Master Status Register, offset: 0x88 */
  __IO uint32_t MIBIRULES;                         /**< Master In-band Interrupt Registry and Rules Register, offset: 0x8C */
  __IO uint32_t MINTSET;                           /**< Master Interrupt Set Register, offset: 0x90 */
  __O  uint32_t MINTCLR;                           /**< Master Interrupt Clear Register, offset: 0x94 */
  __I  uint32_t MINTMASKED;                        /**< Master Interrupt Mask Register, offset: 0x98 */
  __IO uint32_t MERRWARN;                          /**< Master Errors and Warnings Register, offset: 0x9C */
  __IO uint32_t MDMACTRL;                          /**< Master DMA Control Register, offset: 0xA0 */
       uint8_t RESERVED_4[8];
  __IO uint32_t MDATACTRL;                         /**< Master Data Control Register, offset: 0xAC */
  __O  uint32_t MWDATAB;                           /**< Master Write Data Byte Register, offset: 0xB0 */
  __O  uint32_t MWDATABE;                          /**< Master Write Data Byte End Register, offset: 0xB4 */
  __O  uint32_t MWDATAH;                           /**< Master Write Data Half-word Register, offset: 0xB8 */
  __O  uint32_t MWDATAHE;                          /**< Master Write Data Byte End Register, offset: 0xBC */
  __I  uint32_t MRDATAB;                           /**< Master Read Data Byte Register, offset: 0xC0 */
       uint8_t RESERVED_5[4];
  __I  uint32_t MRDATAH;                           /**< Master Read Data Half-word Register, offset: 0xC8 */
  __O  uint32_t MWDATAB1;                          /**< Write Byte Data 1 (to bus), offset: 0xCC */
  union {                                          /* offset: 0xD0 */
    __O  uint32_t MWMSG_SDR_CONTROL;                 /**< Master Write Message in SDR mode, offset: 0xD0 */
    __O  uint32_t MWMSG_SDR_DATA;                    /**< Master Write Message Data in SDR mode, offset: 0xD0 */
  };
  __I  uint32_t MRMSG_SDR;                         /**< Master Read Message in SDR mode, offset: 0xD4 */
  union {                                          /* offset: 0xD8 */
    __O  uint32_t MWMSG_DDR_CONTROL;                 /**< Master Write Message in DDR mode, offset: 0xD8 */
    __O  uint32_t MWMSG_DDR_DATA;                    /**< Master Write Message Data in DDR mode, offset: 0xD8 */
  };
  __IO uint32_t MRMSG_DDR;                         /**< Master Read Message in DDR mode, offset: 0xDC */
       uint8_t RESERVED_6[4];
  __IO uint32_t MDYNADDR;                          /**< Master Dynamic Address Register, offset: 0xE4 */
       uint8_t RESERVED_7[3860];
  __I  uint32_t SID;                               /**< Slave Module ID Register, offset: 0xFFC */
} I3C_Type;

/* ----------------------------------------------------------------------------
   -- I3C Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I3C_Register_Masks I3C Register Masks
 * @{
 */

/*! @name MCONFIG - Master Configuration Register */
/*! @{ */

#define I3C_MCONFIG_MSTENA_MASK                  (0x3U)
#define I3C_MCONFIG_MSTENA_SHIFT                 (0U)
/*! MSTENA - Master enable
 *  0b00..MASTER_OFF
 *  0b01..MASTER_ON
 *  0b10..MASTER_CAPABLE
 *  0b11..
 */
#define I3C_MCONFIG_MSTENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK)

#define I3C_MCONFIG_DISTO_MASK                   (0x8U)
#define I3C_MCONFIG_DISTO_SHIFT                  (3U)
/*! DISTO - Disable Timeout */
#define I3C_MCONFIG_DISTO(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK)

#define I3C_MCONFIG_HKEEP_MASK                   (0x30U)
#define I3C_MCONFIG_HKEEP_SHIFT                  (4U)
/*! HKEEP - High-Keeper
 *  0b00..NONE
 *  0b01..WIRED_IN
 *  0b10..PASSIVE_SDA
 *  0b11..PASSIVE_ON_SDA_SCL
 */
#define I3C_MCONFIG_HKEEP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK)

#define I3C_MCONFIG_ODSTOP_MASK                  (0x40U)
#define I3C_MCONFIG_ODSTOP_SHIFT                 (6U)
/*! ODSTOP - Open drain stop */
#define I3C_MCONFIG_ODSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK)

#define I3C_MCONFIG_PPBAUD_MASK                  (0xF00U)
#define I3C_MCONFIG_PPBAUD_SHIFT                 (8U)
/*! PPBAUD - Push-pull baud rate */
#define I3C_MCONFIG_PPBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK)

#define I3C_MCONFIG_PPLOW_MASK                   (0xF000U)
#define I3C_MCONFIG_PPLOW_SHIFT                  (12U)
/*! PPLOW - Push-Pull low */
#define I3C_MCONFIG_PPLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)

#define I3C_MCONFIG_ODBAUD_MASK                  (0xFF0000U)
#define I3C_MCONFIG_ODBAUD_SHIFT                 (16U)
/*! ODBAUD - Open drain baud rate */
#define I3C_MCONFIG_ODBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK)

#define I3C_MCONFIG_ODHPP_MASK                   (0x1000000U)
#define I3C_MCONFIG_ODHPP_SHIFT                  (24U)
/*! ODHPP - Open drain high push-pull */
#define I3C_MCONFIG_ODHPP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)

#define I3C_MCONFIG_SKEW_MASK                    (0xE000000U)
#define I3C_MCONFIG_SKEW_SHIFT                   (25U)
/*! SKEW - Skew */
#define I3C_MCONFIG_SKEW(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK)

#define I3C_MCONFIG_I2CBAUD_MASK                 (0xF0000000U)
#define I3C_MCONFIG_I2CBAUD_SHIFT                (28U)
/*! I2CBAUD - I2C baud rate */
#define I3C_MCONFIG_I2CBAUD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK)
/*! @} */

/*! @name SCONFIG - Slave Configuration Register */
/*! @{ */

#define I3C_SCONFIG_SLVENA_MASK                  (0x1U)
#define I3C_SCONFIG_SLVENA_SHIFT                 (0U)
/*! SLVENA - Slave enable */
#define I3C_SCONFIG_SLVENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)

#define I3C_SCONFIG_NACK_MASK                    (0x2U)
#define I3C_SCONFIG_NACK_SHIFT                   (1U)
/*! NACK - Not acknowledge */
#define I3C_SCONFIG_NACK(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK)

#define I3C_SCONFIG_MATCHSS_MASK                 (0x4U)
#define I3C_SCONFIG_MATCHSS_SHIFT                (2U)
/*! MATCHSS - Match START or STOP */
#define I3C_SCONFIG_MATCHSS(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK)

#define I3C_SCONFIG_S0IGNORE_MASK                (0x8U)
#define I3C_SCONFIG_S0IGNORE_SHIFT               (3U)
/*! S0IGNORE - S0/S1 errors ignore */
#define I3C_SCONFIG_S0IGNORE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK)

#define I3C_SCONFIG_DDROK_MASK                   (0x10U)
#define I3C_SCONFIG_DDROK_SHIFT                  (4U)
/*! DDROK - Double Data Rate OK */
#define I3C_SCONFIG_DDROK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_DDROK_SHIFT)) & I3C_SCONFIG_DDROK_MASK)

#define I3C_SCONFIG_IDRAND_MASK                  (0x100U)
#define I3C_SCONFIG_IDRAND_SHIFT                 (8U)
/*! IDRAND - ID random */
#define I3C_SCONFIG_IDRAND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_IDRAND_SHIFT)) & I3C_SCONFIG_IDRAND_MASK)

#define I3C_SCONFIG_OFFLINE_MASK                 (0x200U)
#define I3C_SCONFIG_OFFLINE_SHIFT                (9U)
/*! OFFLINE - Offline */
#define I3C_SCONFIG_OFFLINE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK)

#define I3C_SCONFIG_BAMATCH_MASK                 (0xFF0000U)
#define I3C_SCONFIG_BAMATCH_SHIFT                (16U)
/*! BAMATCH - Bus available match */
#define I3C_SCONFIG_BAMATCH(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK)

#define I3C_SCONFIG_SADDR_MASK                   (0xFE000000U)
#define I3C_SCONFIG_SADDR_SHIFT                  (25U)
/*! SADDR - Static address */
#define I3C_SCONFIG_SADDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK)
/*! @} */

/*! @name SSTATUS - Slave Status Register */
/*! @{ */

#define I3C_SSTATUS_STNOTSTOP_MASK               (0x1U)
#define I3C_SSTATUS_STNOTSTOP_SHIFT              (0U)
/*! STNOTSTOP - Status not stop */
#define I3C_SSTATUS_STNOTSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK)

#define I3C_SSTATUS_STMSG_MASK                   (0x2U)
#define I3C_SSTATUS_STMSG_SHIFT                  (1U)
/*! STMSG - Status message */
#define I3C_SSTATUS_STMSG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK)

#define I3C_SSTATUS_STCCCH_MASK                  (0x4U)
#define I3C_SSTATUS_STCCCH_SHIFT                 (2U)
/*! STCCCH - Status Common Command Code Handler */
#define I3C_SSTATUS_STCCCH(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK)

#define I3C_SSTATUS_STREQRD_MASK                 (0x8U)
#define I3C_SSTATUS_STREQRD_SHIFT                (3U)
/*! STREQRD - Status required */
#define I3C_SSTATUS_STREQRD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK)

#define I3C_SSTATUS_STREQWR_MASK                 (0x10U)
#define I3C_SSTATUS_STREQWR_SHIFT                (4U)
/*! STREQWR - Status request write */
#define I3C_SSTATUS_STREQWR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK)

#define I3C_SSTATUS_STDAA_MASK                   (0x20U)
#define I3C_SSTATUS_STDAA_SHIFT                  (5U)
/*! STDAA - Status Dynamic Address Assignment */
#define I3C_SSTATUS_STDAA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK)

#define I3C_SSTATUS_STHDR_MASK                   (0x40U)
#define I3C_SSTATUS_STHDR_SHIFT                  (6U)
/*! STHDR - Status High Data Rate */
#define I3C_SSTATUS_STHDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK)

#define I3C_SSTATUS_START_MASK                   (0x100U)
#define I3C_SSTATUS_START_SHIFT                  (8U)
/*! START - Start */
#define I3C_SSTATUS_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK)

#define I3C_SSTATUS_MATCHED_MASK                 (0x200U)
#define I3C_SSTATUS_MATCHED_SHIFT                (9U)
/*! MATCHED - Matched */
#define I3C_SSTATUS_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK)

#define I3C_SSTATUS_STOP_MASK                    (0x400U)
#define I3C_SSTATUS_STOP_SHIFT                   (10U)
/*! STOP - Stop */
#define I3C_SSTATUS_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK)

#define I3C_SSTATUS_RX_PEND_MASK                 (0x800U)
#define I3C_SSTATUS_RX_PEND_SHIFT                (11U)
/*! RX_PEND - Received message pending */
#define I3C_SSTATUS_RX_PEND(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK)

#define I3C_SSTATUS_TXNOTFULL_MASK               (0x1000U)
#define I3C_SSTATUS_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - Transmit buffer is not full */
#define I3C_SSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK)

#define I3C_SSTATUS_DACHG_MASK                   (0x2000U)
#define I3C_SSTATUS_DACHG_SHIFT                  (13U)
/*! DACHG - DACHG */
#define I3C_SSTATUS_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK)

#define I3C_SSTATUS_CCC_MASK                     (0x4000U)
#define I3C_SSTATUS_CCC_SHIFT                    (14U)
/*! CCC - Common Command Code */
#define I3C_SSTATUS_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK)

#define I3C_SSTATUS_ERRWARN_MASK                 (0x8000U)
#define I3C_SSTATUS_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error warning */
#define I3C_SSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK)

#define I3C_SSTATUS_HDRMATCH_MASK                (0x10000U)
#define I3C_SSTATUS_HDRMATCH_SHIFT               (16U)
/*! HDRMATCH - High Data Rate command match */
#define I3C_SSTATUS_HDRMATCH(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK)

#define I3C_SSTATUS_CHANDLED_MASK                (0x20000U)
#define I3C_SSTATUS_CHANDLED_SHIFT               (17U)
/*! CHANDLED - Common-Command-Code handled */
#define I3C_SSTATUS_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK)

#define I3C_SSTATUS_EVENT_MASK                   (0x40000U)
#define I3C_SSTATUS_EVENT_SHIFT                  (18U)
/*! EVENT - Event */
#define I3C_SSTATUS_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK)

#define I3C_SSTATUS_EVDET_MASK                   (0x300000U)
#define I3C_SSTATUS_EVDET_SHIFT                  (20U)
/*! EVDET - Event details
 *  0b00..NONE
 *  0b01..NO_REQUEST
 *  0b10..NACKED
 *  0b11..ACKED
 */
#define I3C_SSTATUS_EVDET(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK)

#define I3C_SSTATUS_IBIDIS_MASK                  (0x1000000U)
#define I3C_SSTATUS_IBIDIS_SHIFT                 (24U)
/*! IBIDIS - In-Band Interrupts are disabled */
#define I3C_SSTATUS_IBIDIS(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK)

#define I3C_SSTATUS_MRDIS_MASK                   (0x2000000U)
#define I3C_SSTATUS_MRDIS_SHIFT                  (25U)
/*! MRDIS - Master requests are disabled */
#define I3C_SSTATUS_MRDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK)

#define I3C_SSTATUS_HJDIS_MASK                   (0x8000000U)
#define I3C_SSTATUS_HJDIS_SHIFT                  (27U)
/*! HJDIS - Hot-Join is disabled */
#define I3C_SSTATUS_HJDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK)

#define I3C_SSTATUS_ACTSTATE_MASK                (0x30000000U)
#define I3C_SSTATUS_ACTSTATE_SHIFT               (28U)
/*! ACTSTATE - Activity state from Common Command Codes (CCC)
 *  0b00..NO_LATENCY
 *  0b01..LATENCY_1MS
 *  0b10..LATENCY_100MS
 *  0b11..LATENCY_10S
 */
#define I3C_SSTATUS_ACTSTATE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK)

#define I3C_SSTATUS_TIMECTRL_MASK                (0xC0000000U)
#define I3C_SSTATUS_TIMECTRL_SHIFT               (30U)
/*! TIMECTRL - Time control
 *  0b00..NO_TIME_CONTROL
 *  0b01..
 *  0b10..ASYNC_MODE
 *  0b11..
 */
#define I3C_SSTATUS_TIMECTRL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK)
/*! @} */

/*! @name SCTRL - Slave Control Register */
/*! @{ */

#define I3C_SCTRL_EVENT_MASK                     (0x3U)
#define I3C_SCTRL_EVENT_SHIFT                    (0U)
/*! EVENT - EVENT
 *  0b00..NORMAL_MODE
 *  0b01..IBI
 *  0b10..MASTER_REQUEST
 *  0b11..HOT_JOIN_REQUEST
 */
#define I3C_SCTRL_EVENT(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK)

#define I3C_SCTRL_IBIDATA_MASK                   (0xFF00U)
#define I3C_SCTRL_IBIDATA_SHIFT                  (8U)
/*! IBIDATA - In-Band Interrupt Data */
#define I3C_SCTRL_IBIDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK)

#define I3C_SCTRL_PENDINT_MASK                   (0xF0000U)
#define I3C_SCTRL_PENDINT_SHIFT                  (16U)
/*! PENDINT - Pending interrupt */
#define I3C_SCTRL_PENDINT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK)

#define I3C_SCTRL_ACTSTATE_MASK                  (0x300000U)
#define I3C_SCTRL_ACTSTATE_SHIFT                 (20U)
/*! ACTSTATE - Activity state (of slave) */
#define I3C_SCTRL_ACTSTATE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK)

#define I3C_SCTRL_VENDINFO_MASK                  (0xFF000000U)
#define I3C_SCTRL_VENDINFO_SHIFT                 (24U)
/*! VENDINFO - Vendor information */
#define I3C_SCTRL_VENDINFO(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK)
/*! @} */

/*! @name SINTSET - Slave Interrupt Set Register */
/*! @{ */

#define I3C_SINTSET_START_MASK                   (0x100U)
#define I3C_SINTSET_START_SHIFT                  (8U)
/*! START - Start interrupt enable */
#define I3C_SINTSET_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK)

#define I3C_SINTSET_MATCHED_MASK                 (0x200U)
#define I3C_SINTSET_MATCHED_SHIFT                (9U)
/*! MATCHED - Match interrupt enable */
#define I3C_SINTSET_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK)

#define I3C_SINTSET_STOP_MASK                    (0x400U)
#define I3C_SINTSET_STOP_SHIFT                   (10U)
/*! STOP - Stop interrupt enable */
#define I3C_SINTSET_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK)

#define I3C_SINTSET_RXPEND_MASK                  (0x800U)
#define I3C_SINTSET_RXPEND_SHIFT                 (11U)
/*! RXPEND - Receive interrupt enable */
#define I3C_SINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK)

#define I3C_SINTSET_TXSEND_MASK                  (0x1000U)
#define I3C_SINTSET_TXSEND_SHIFT                 (12U)
/*! TXSEND - Transmit interrupt enable */
#define I3C_SINTSET_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK)

#define I3C_SINTSET_DACHG_MASK                   (0x2000U)
#define I3C_SINTSET_DACHG_SHIFT                  (13U)
/*! DACHG - Dynamic address change interrupt enable */
#define I3C_SINTSET_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK)

#define I3C_SINTSET_CCC_MASK                     (0x4000U)
#define I3C_SINTSET_CCC_SHIFT                    (14U)
/*! CCC - Common Command Code (CCC) (that was not handled by I3C module) interrupt enable */
#define I3C_SINTSET_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK)

#define I3C_SINTSET_ERRWARN_MASK                 (0x8000U)
#define I3C_SINTSET_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error/warning interrupt enable */
#define I3C_SINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK)

#define I3C_SINTSET_DDRMATCHED_MASK              (0x10000U)
#define I3C_SINTSET_DDRMATCHED_SHIFT             (16U)
/*! DDRMATCHED - Double Data Rate (DDR) interrupt enable */
#define I3C_SINTSET_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK)

#define I3C_SINTSET_CHANDLED_MASK                (0x20000U)
#define I3C_SINTSET_CHANDLED_SHIFT               (17U)
/*! CHANDLED - Common Command Code (CCC) (that was handled by I3C module) interrupt enable */
#define I3C_SINTSET_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK)

#define I3C_SINTSET_EVENT_MASK                   (0x40000U)
#define I3C_SINTSET_EVENT_SHIFT                  (18U)
/*! EVENT - Event interrupt enable */
#define I3C_SINTSET_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK)
/*! @} */

/*! @name SINTCLR - Slave Interrupt Clear Register */
/*! @{ */

#define I3C_SINTCLR_START_MASK                   (0x100U)
#define I3C_SINTCLR_START_SHIFT                  (8U)
/*! START - START interrupt enable clear */
#define I3C_SINTCLR_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK)

#define I3C_SINTCLR_MATCHED_MASK                 (0x200U)
#define I3C_SINTCLR_MATCHED_SHIFT                (9U)
/*! MATCHED - MATCHED interrupt enable clear */
#define I3C_SINTCLR_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK)

#define I3C_SINTCLR_STOP_MASK                    (0x400U)
#define I3C_SINTCLR_STOP_SHIFT                   (10U)
/*! STOP - STOP interrupt enable clear */
#define I3C_SINTCLR_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK)

#define I3C_SINTCLR_RXPEND_MASK                  (0x800U)
#define I3C_SINTCLR_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND interrupt enable clear */
#define I3C_SINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK)

#define I3C_SINTCLR_TXSEND_MASK                  (0x1000U)
#define I3C_SINTCLR_TXSEND_SHIFT                 (12U)
/*! TXSEND - TXSEND interrupt enable clear */
#define I3C_SINTCLR_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK)

#define I3C_SINTCLR_DACHG_MASK                   (0x2000U)
#define I3C_SINTCLR_DACHG_SHIFT                  (13U)
/*! DACHG - DACHG interrupt enable clear */
#define I3C_SINTCLR_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK)

#define I3C_SINTCLR_CCC_MASK                     (0x4000U)
#define I3C_SINTCLR_CCC_SHIFT                    (14U)
/*! CCC - CCC interrupt enable clear */
#define I3C_SINTCLR_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK)

#define I3C_SINTCLR_ERRWARN_MASK                 (0x8000U)
#define I3C_SINTCLR_ERRWARN_SHIFT                (15U)
/*! ERRWARN - ERRWARN interrupt enable clear */
#define I3C_SINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK)

#define I3C_SINTCLR_DDRMATCHED_MASK              (0x10000U)
#define I3C_SINTCLR_DDRMATCHED_SHIFT             (16U)
/*! DDRMATCHED - DDRMATCHED interrupt enable clear */
#define I3C_SINTCLR_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK)

#define I3C_SINTCLR_CHANDLED_MASK                (0x20000U)
#define I3C_SINTCLR_CHANDLED_SHIFT               (17U)
/*! CHANDLED - CHANDLED interrupt enable clear */
#define I3C_SINTCLR_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK)

#define I3C_SINTCLR_EVENT_MASK                   (0x40000U)
#define I3C_SINTCLR_EVENT_SHIFT                  (18U)
/*! EVENT - EVENT interrupt enable clear */
#define I3C_SINTCLR_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK)
/*! @} */

/*! @name SINTMASKED - Slave Interrupt Mask Register */
/*! @{ */

#define I3C_SINTMASKED_START_MASK                (0x100U)
#define I3C_SINTMASKED_START_SHIFT               (8U)
/*! START - START interrupt mask */
#define I3C_SINTMASKED_START(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK)

#define I3C_SINTMASKED_MATCHED_MASK              (0x200U)
#define I3C_SINTMASKED_MATCHED_SHIFT             (9U)
/*! MATCHED - MATCHED interrupt mask */
#define I3C_SINTMASKED_MATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK)

#define I3C_SINTMASKED_STOP_MASK                 (0x400U)
#define I3C_SINTMASKED_STOP_SHIFT                (10U)
/*! STOP - STOP interrupt mask */
#define I3C_SINTMASKED_STOP(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK)

#define I3C_SINTMASKED_RXPEND_MASK               (0x800U)
#define I3C_SINTMASKED_RXPEND_SHIFT              (11U)
/*! RXPEND - RXPEND interrupt mask */
#define I3C_SINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK)

#define I3C_SINTMASKED_TXSEND_MASK               (0x1000U)
#define I3C_SINTMASKED_TXSEND_SHIFT              (12U)
/*! TXSEND - TXSEND interrupt mask */
#define I3C_SINTMASKED_TXSEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK)

#define I3C_SINTMASKED_DACHG_MASK                (0x2000U)
#define I3C_SINTMASKED_DACHG_SHIFT               (13U)
/*! DACHG - DACHG interrupt mask */
#define I3C_SINTMASKED_DACHG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK)

#define I3C_SINTMASKED_CCC_MASK                  (0x4000U)
#define I3C_SINTMASKED_CCC_SHIFT                 (14U)
/*! CCC - CCC interrupt mask */
#define I3C_SINTMASKED_CCC(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK)

#define I3C_SINTMASKED_ERRWARN_MASK              (0x8000U)
#define I3C_SINTMASKED_ERRWARN_SHIFT             (15U)
/*! ERRWARN - ERRWARN interrupt mask */
#define I3C_SINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK)

#define I3C_SINTMASKED_DDRMATCHED_MASK           (0x10000U)
#define I3C_SINTMASKED_DDRMATCHED_SHIFT          (16U)
/*! DDRMATCHED - DDRMATCHED interrupt mask */
#define I3C_SINTMASKED_DDRMATCHED(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK)

#define I3C_SINTMASKED_CHANDLED_MASK             (0x20000U)
#define I3C_SINTMASKED_CHANDLED_SHIFT            (17U)
/*! CHANDLED - CHANDLED interrupt mask */
#define I3C_SINTMASKED_CHANDLED(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK)

#define I3C_SINTMASKED_EVENT_MASK                (0x40000U)
#define I3C_SINTMASKED_EVENT_SHIFT               (18U)
/*! EVENT - EVENT interrupt mask */
#define I3C_SINTMASKED_EVENT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK)
/*! @} */

/*! @name SERRWARN - Slave Errors and Warnings Register */
/*! @{ */

#define I3C_SERRWARN_ORUN_MASK                   (0x1U)
#define I3C_SERRWARN_ORUN_SHIFT                  (0U)
/*! ORUN - Overrun error */
#define I3C_SERRWARN_ORUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK)

#define I3C_SERRWARN_URUN_MASK                   (0x2U)
#define I3C_SERRWARN_URUN_SHIFT                  (1U)
/*! URUN - Underrun error */
#define I3C_SERRWARN_URUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK)

#define I3C_SERRWARN_URUNNACK_MASK               (0x4U)
#define I3C_SERRWARN_URUNNACK_SHIFT              (2U)
/*! URUNNACK - Underrun and Not Acknowledged (NACKed) error */
#define I3C_SERRWARN_URUNNACK(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK)

#define I3C_SERRWARN_TERM_MASK                   (0x8U)
#define I3C_SERRWARN_TERM_SHIFT                  (3U)
/*! TERM - Terminated error */
#define I3C_SERRWARN_TERM(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK)

#define I3C_SERRWARN_INVSTART_MASK               (0x10U)
#define I3C_SERRWARN_INVSTART_SHIFT              (4U)
/*! INVSTART - Invalid start error */
#define I3C_SERRWARN_INVSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK)

#define I3C_SERRWARN_SPAR_MASK                   (0x100U)
#define I3C_SERRWARN_SPAR_SHIFT                  (8U)
/*! SPAR - SDR parity error */
#define I3C_SERRWARN_SPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK)

#define I3C_SERRWARN_HPAR_MASK                   (0x200U)
#define I3C_SERRWARN_HPAR_SHIFT                  (9U)
/*! HPAR - HDR parity error */
#define I3C_SERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK)

#define I3C_SERRWARN_HCRC_MASK                   (0x400U)
#define I3C_SERRWARN_HCRC_SHIFT                  (10U)
/*! HCRC - HDR-DDR CRC error */
#define I3C_SERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK)

#define I3C_SERRWARN_S0S1_MASK                   (0x800U)
#define I3C_SERRWARN_S0S1_SHIFT                  (11U)
/*! S0S1 - S0 or S1 error */
#define I3C_SERRWARN_S0S1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK)

#define I3C_SERRWARN_OREAD_MASK                  (0x10000U)
#define I3C_SERRWARN_OREAD_SHIFT                 (16U)
/*! OREAD - Over-read error */
#define I3C_SERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK)

#define I3C_SERRWARN_OWRITE_MASK                 (0x20000U)
#define I3C_SERRWARN_OWRITE_SHIFT                (17U)
/*! OWRITE - Over-write error */
#define I3C_SERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK)
/*! @} */

/*! @name SDMACTRL - Slave DMA Control Register */
/*! @{ */

#define I3C_SDMACTRL_DMAFB_MASK                  (0x3U)
#define I3C_SDMACTRL_DMAFB_SHIFT                 (0U)
/*! DMAFB - DMA Read (From-bus) trigger
 *  0b00..DMA not used
 *  0b01..DMA is enabled for 1 frame
 *  0b10..DMA enable
 */
#define I3C_SDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK)

#define I3C_SDMACTRL_DMATB_MASK                  (0xCU)
#define I3C_SDMACTRL_DMATB_SHIFT                 (2U)
/*! DMATB - DMA Write (To-bus) trigger
 *  0b00..NOT_USED
 *  0b01..ENABLE_ONE_FRAME
 *  0b10..ENABLE
 */
#define I3C_SDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK)

#define I3C_SDMACTRL_DMAWIDTH_MASK               (0x30U)
#define I3C_SDMACTRL_DMAWIDTH_SHIFT              (4U)
/*! DMAWIDTH - Width of DMA operations
 *  0b00..BYTE
 *  0b01..BYTE_AGAIN
 *  0b10..HALF_WORD: Half word (16 bits). This will make sure that 2 bytes are free/available in the FIFO.
 *  0b11..
 */
#define I3C_SDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK)
/*! @} */

/*! @name SDATACTRL - Slave Data Control Register */
/*! @{ */

#define I3C_SDATACTRL_FLUSHTB_MASK               (0x1U)
#define I3C_SDATACTRL_FLUSHTB_SHIFT              (0U)
/*! FLUSHTB - Flush the to-bus buffer/FIFO */
#define I3C_SDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK)

#define I3C_SDATACTRL_FLUSHFB_MASK               (0x2U)
#define I3C_SDATACTRL_FLUSHFB_SHIFT              (1U)
/*! FLUSHFB - Flushes the from-bus buffer/FIFO */
#define I3C_SDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK)

#define I3C_SDATACTRL_UNLOCK_MASK                (0x8U)
#define I3C_SDATACTRL_UNLOCK_SHIFT               (3U)
/*! UNLOCK - Unlock */
#define I3C_SDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK)

#define I3C_SDATACTRL_TXTRIG_MASK                (0x30U)
#define I3C_SDATACTRL_TXTRIG_SHIFT               (4U)
/*! TXTRIG - Trigger level for TX FIFO emptiness
 *  0b00..Trigger on empty
 *  0b01..Trigger on ¼ full or less
 *  0b10..Trigger on .5 full or less
 *  0b11..Trigger on 1 less than full or less (Default)
 */
#define I3C_SDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK)

#define I3C_SDATACTRL_RXTRIG_MASK                (0xC0U)
#define I3C_SDATACTRL_RXTRIG_SHIFT               (6U)
/*! RXTRIG - Trigger level for RX FIFO fullness
 *  0b00..Trigger on not empty
 *  0b01..Trigger on ¼ or more full
 *  0b10..Trigger on .5 or more full
 *  0b11..Trigger on 3/4 or more full
 */
#define I3C_SDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK)

#define I3C_SDATACTRL_TXCOUNT_MASK               (0x1F0000U)
#define I3C_SDATACTRL_TXCOUNT_SHIFT              (16U)
/*! TXCOUNT - Count of bytes in TX */
#define I3C_SDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK)

#define I3C_SDATACTRL_RXCOUNT_MASK               (0x1F000000U)
#define I3C_SDATACTRL_RXCOUNT_SHIFT              (24U)
/*! RXCOUNT - Count of bytes in RX */
#define I3C_SDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK)

#define I3C_SDATACTRL_TXFULL_MASK                (0x40000000U)
#define I3C_SDATACTRL_TXFULL_SHIFT               (30U)
/*! TXFULL - TX is full
 *  0b1..TX is full
 *  0b0..TX is not full
 */
#define I3C_SDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK)

#define I3C_SDATACTRL_RXEMPTY_MASK               (0x80000000U)
#define I3C_SDATACTRL_RXEMPTY_SHIFT              (31U)
/*! RXEMPTY - RX is empty
 *  0b1..RX is empty
 *  0b0..RX is not empty
 */
#define I3C_SDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK)
/*! @} */

/*! @name SWDATAB - Slave Write Data Byte Register */
/*! @{ */

#define I3C_SWDATAB_DATA_MASK                    (0xFFU)
#define I3C_SWDATAB_DATA_SHIFT                   (0U)
/*! DATA - The data byte to send to the master */
#define I3C_SWDATAB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK)

#define I3C_SWDATAB_END_MASK                     (0x100U)
#define I3C_SWDATAB_END_SHIFT                    (8U)
/*! END - End */
#define I3C_SWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK)

#define I3C_SWDATAB_END_ALSO_MASK                (0x10000U)
#define I3C_SWDATAB_END_ALSO_SHIFT               (16U)
/*! END_ALSO - End also */
#define I3C_SWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK)
/*! @} */

/*! @name SWDATABE - Slave Write Data Byte End */
/*! @{ */

#define I3C_SWDATABE_DATA_MASK                   (0xFFU)
#define I3C_SWDATABE_DATA_SHIFT                  (0U)
/*! DATA - The data byte to send to the master */
#define I3C_SWDATABE_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK)
/*! @} */

/*! @name SWDATAH - Slave Write Data Half-word Register */
/*! @{ */

#define I3C_SWDATAH_DATA0_MASK                   (0xFFU)
#define I3C_SWDATAH_DATA0_SHIFT                  (0U)
/*! DATA0 - The 1st byte to send to the master */
#define I3C_SWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK)

#define I3C_SWDATAH_DATA1_MASK                   (0xFF00U)
#define I3C_SWDATAH_DATA1_SHIFT                  (8U)
/*! DATA1 - The 2nd byte to send to the master */
#define I3C_SWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK)

#define I3C_SWDATAH_END_MASK                     (0x10000U)
#define I3C_SWDATAH_END_SHIFT                    (16U)
/*! END - End of message */
#define I3C_SWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK)
/*! @} */

/*! @name SWDATAHE - Slave Write Data Half-word End Register */
/*! @{ */

#define I3C_SWDATAHE_DATA0_MASK                  (0xFFU)
#define I3C_SWDATAHE_DATA0_SHIFT                 (0U)
/*! DATA0 - The 1st byte to send to the master */
#define I3C_SWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK)

#define I3C_SWDATAHE_DATA1_MASK                  (0xFF00U)
#define I3C_SWDATAHE_DATA1_SHIFT                 (8U)
/*! DATA1 - The 2nd byte to send to the master */
#define I3C_SWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK)
/*! @} */

/*! @name SRDATAB - Slave Read Data Byte Register */
/*! @{ */

#define I3C_SRDATAB_DATA0_MASK                   (0xFFU)
#define I3C_SRDATAB_DATA0_SHIFT                  (0U)
/*! DATA0 - Byte read from the master */
#define I3C_SRDATAB_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK)
/*! @} */

/*! @name SRDATAH - Slave Read Data Half-word Register */
/*! @{ */

#define I3C_SRDATAH_LSB_MASK                     (0xFFU)
#define I3C_SRDATAH_LSB_SHIFT                    (0U)
/*! LSB - The 1st byte read from the slave */
#define I3C_SRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK)

#define I3C_SRDATAH_MSB_MASK                     (0xFF00U)
#define I3C_SRDATAH_MSB_SHIFT                    (8U)
/*! MSB - The 2nd byte read from the slave */
#define I3C_SRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK)
/*! @} */

/*! @name SCAPABILITIES - Slave Capabilities Register */
/*! @{ */

#define I3C_SCAPABILITIES_IDENA_MASK             (0x3U)
#define I3C_SCAPABILITIES_IDENA_SHIFT            (0U)
/*! IDENA - ID 48b handler
 *  0b00..APPLICATION
 *  0b01..HW
 *  0b10..HW_BUT
 *  0b11..PARTNO
 */
#define I3C_SCAPABILITIES_IDENA(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK)

#define I3C_SCAPABILITIES_IDREG_MASK             (0x3CU)
#define I3C_SCAPABILITIES_IDREG_SHIFT            (2U)
/*! IDREG - ID register */
#define I3C_SCAPABILITIES_IDREG(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK)

#define I3C_SCAPABILITIES_HDRSUPP_MASK           (0x1C0U)
#define I3C_SCAPABILITIES_HDRSUPP_SHIFT          (6U)
/*! HDRSUPP - HDR support */
#define I3C_SCAPABILITIES_HDRSUPP(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK)

#define I3C_SCAPABILITIES_MASTER_MASK            (0x200U)
#define I3C_SCAPABILITIES_MASTER_SHIFT           (9U)
/*! MASTER - Master
 *  0b0..MASTERNOTSUPPORTED
 *  0b1..MASTERSUPPORTED
 */
#define I3C_SCAPABILITIES_MASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK)

#define I3C_SCAPABILITIES_SADDR_MASK             (0xC00U)
#define I3C_SCAPABILITIES_SADDR_SHIFT            (10U)
/*! SADDR - Static address
 *  0b00..NO_STATIC
 *  0b01..STATIC
 *  0b10..HW_CONTROL
 *  0b11..CONFIG
 */
#define I3C_SCAPABILITIES_SADDR(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK)

#define I3C_SCAPABILITIES_CCCHANDLE_MASK         (0xF000U)
#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT        (12U)
/*! CCCHANDLE - Common Command Codes (CCC) handling */
#define I3C_SCAPABILITIES_CCCHANDLE(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK)

#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK         (0x1F0000U)
#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT        (16U)
/*! IBI_MR_HJ - In-Band Interrupts, Master Requests, Hot Join events */
#define I3C_SCAPABILITIES_IBI_MR_HJ(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK)

#define I3C_SCAPABILITIES_TIMECTRL_MASK          (0x200000U)
#define I3C_SCAPABILITIES_TIMECTRL_SHIFT         (21U)
/*! TIMECTRL - Time control
 *  0b0..NO_TIME_CONTROL_TYPE
 *  0b1..NO_TIME_CONTROL_TYPE
 */
#define I3C_SCAPABILITIES_TIMECTRL(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK)

#define I3C_SCAPABILITIES_EXTFIFO_MASK           (0x3800000U)
#define I3C_SCAPABILITIES_EXTFIFO_SHIFT          (23U)
/*! EXTFIFO - External FIFO
 *  0b001..STD_EXT_FIFO:
 *  0b011..
 */
#define I3C_SCAPABILITIES_EXTFIFO(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK)

#define I3C_SCAPABILITIES_FIFOTX_MASK            (0xC000000U)
#define I3C_SCAPABILITIES_FIFOTX_SHIFT           (26U)
/*! FIFOTX - FIFO transmit
 *  0b00..FIFO_2BYTE
 *  0b01..FIFO_4BYTE
 *  0b10..FIFO_8BYTE
 *  0b11..FIFO_16BYTE
 */
#define I3C_SCAPABILITIES_FIFOTX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK)

#define I3C_SCAPABILITIES_FIFORX_MASK            (0x30000000U)
#define I3C_SCAPABILITIES_FIFORX_SHIFT           (28U)
/*! FIFORX - FIFO receive
 *  0b00..FIFO_2BYTE
 *  0b01..FIFO_4BYTE
 *  0b10..FIFO_8BYTE
 *  0b11..FIFO_16BYTE
 */
#define I3C_SCAPABILITIES_FIFORX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK)

#define I3C_SCAPABILITIES_INT_MASK               (0x40000000U)
#define I3C_SCAPABILITIES_INT_SHIFT              (30U)
/*! INT - Interrupt
 *  0b1..Interrupts are supported.
 *  0b0..Interrupts are not supported
 */
#define I3C_SCAPABILITIES_INT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK)

#define I3C_SCAPABILITIES_DMA_MASK               (0x80000000U)
#define I3C_SCAPABILITIES_DMA_SHIFT              (31U)
/*! DMA - DMA
 *  0b1..DMA is supported
 *  0b0..DMA is not supported
 */
#define I3C_SCAPABILITIES_DMA(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK)
/*! @} */

/*! @name SDYNADDR - Slave Dynamic Address Register */
/*! @{ */

#define I3C_SDYNADDR_DAVALID_MASK                (0x1U)
#define I3C_SDYNADDR_DAVALID_SHIFT               (0U)
/*! DAVALID - DAVALID
 *  0b0..DANOTASSIGNED
 *  0b1..DAASSIGNED
 */
#define I3C_SDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK)

#define I3C_SDYNADDR_DADDR_MASK                  (0xFEU)
#define I3C_SDYNADDR_DADDR_SHIFT                 (1U)
/*! DADDR - Dynamic address */
#define I3C_SDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK)

#define I3C_SDYNADDR_MAPIDX_MASK                 (0xF00U)
#define I3C_SDYNADDR_MAPIDX_SHIFT                (8U)
/*! MAPIDX - Mapped Dynamic Address */
#define I3C_SDYNADDR_MAPIDX(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPIDX_SHIFT)) & I3C_SDYNADDR_MAPIDX_MASK)

#define I3C_SDYNADDR_MAPSA_MASK                  (0x1000U)
#define I3C_SDYNADDR_MAPSA_SHIFT                 (12U)
/*! MAPSA - Map a Static Address */
#define I3C_SDYNADDR_MAPSA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK)

#define I3C_SDYNADDR_KEY_MASK                    (0xFFFF0000U)
#define I3C_SDYNADDR_KEY_SHIFT                   (16U)
/*! KEY - Key */
#define I3C_SDYNADDR_KEY(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK)
/*! @} */

/*! @name SMAXLIMITS - Slave Maximum Limits Register */
/*! @{ */

#define I3C_SMAXLIMITS_MAXRD_MASK                (0xFFFU)
#define I3C_SMAXLIMITS_MAXRD_SHIFT               (0U)
/*! MAXRD - Maximum read length */
#define I3C_SMAXLIMITS_MAXRD(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK)

#define I3C_SMAXLIMITS_MAXWR_MASK                (0xFFF0000U)
#define I3C_SMAXLIMITS_MAXWR_SHIFT               (16U)
/*! MAXWR - Maximum write length */
#define I3C_SMAXLIMITS_MAXWR(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK)
/*! @} */

/*! @name SIDPARTNO - Slave ID Part Number Register */
/*! @{ */

#define I3C_SIDPARTNO_PARTNO_MASK                (0xFFFFFFFFU)
#define I3C_SIDPARTNO_PARTNO_SHIFT               (0U)
/*! PARTNO - Part number */
#define I3C_SIDPARTNO_PARTNO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK)
/*! @} */

/*! @name SIDEXT - Slave ID Extension Register */
/*! @{ */

#define I3C_SIDEXT_DCR_MASK                      (0xFF00U)
#define I3C_SIDEXT_DCR_SHIFT                     (8U)
/*! DCR - Device Characteristic Register */
#define I3C_SIDEXT_DCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK)

#define I3C_SIDEXT_BCR_MASK                      (0xFF0000U)
#define I3C_SIDEXT_BCR_SHIFT                     (16U)
/*! BCR - Bus Characteristics Register */
#define I3C_SIDEXT_BCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK)
/*! @} */

/*! @name SVENDORID - Slave Vendor ID Register */
/*! @{ */

#define I3C_SVENDORID_VID_MASK                   (0x7FFFU)
#define I3C_SVENDORID_VID_SHIFT                  (0U)
/*! VID - Vendor ID */
#define I3C_SVENDORID_VID(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK)
/*! @} */

/*! @name STCCLOCK - Slave Time Control Clock Register */
/*! @{ */

#define I3C_STCCLOCK_ACCURACY_MASK               (0xFFU)
#define I3C_STCCLOCK_ACCURACY_SHIFT              (0U)
/*! ACCURACY - Clock accuracy */
#define I3C_STCCLOCK_ACCURACY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK)

#define I3C_STCCLOCK_FREQ_MASK                   (0xFF00U)
#define I3C_STCCLOCK_FREQ_SHIFT                  (8U)
/*! FREQ - Clock frequency */
#define I3C_STCCLOCK_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK)
/*! @} */

/*! @name SMSGMAPADDR - Slave Message-Mapped Address Register */
/*! @{ */

#define I3C_SMSGMAPADDR_MAPLAST_MASK             (0xFU)
#define I3C_SMSGMAPADDR_MAPLAST_SHIFT            (0U)
/*! MAPLAST - Matched address index */
#define I3C_SMSGMAPADDR_MAPLAST(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK)

#define I3C_SMSGMAPADDR_MAPLASTM1_MASK           (0xF00U)
#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT          (8U)
/*! MAPLASTM1 - Previous match index 1 */
#define I3C_SMSGMAPADDR_MAPLASTM1(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK)

#define I3C_SMSGMAPADDR_MAPLASTM2_MASK           (0xF0000U)
#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT          (16U)
/*! MAPLASTM2 - Previous match index 2 */
#define I3C_SMSGMAPADDR_MAPLASTM2(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK)
/*! @} */

/*! @name MCTRL - Master Main Control Register */
/*! @{ */

#define I3C_MCTRL_REQUEST_MASK                   (0x7U)
#define I3C_MCTRL_REQUEST_SHIFT                  (0U)
/*! REQUEST - Request
 *  0b000..NONE
 *  0b001..EMITSTARTADDR
 *  0b010..EMITSTOP
 *  0b011..IBIACKNACK
 *  0b100..PROCESSDAA
 *  0b101..
 *  0b110..FORCEEXIT and IBHR
 *  0b111..AUTOIBI
 */
#define I3C_MCTRL_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK)

#define I3C_MCTRL_TYPE_MASK                      (0x30U)
#define I3C_MCTRL_TYPE_SHIFT                     (4U)
/*! TYPE - Bus type with START
 *  0b00..I3C
 *  0b01..I2C
 *  0b10..DDR
 *  0b11..For ForcedExit, this is forced IBHR.
 */
#define I3C_MCTRL_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK)

#define I3C_MCTRL_IBIRESP_MASK                   (0xC0U)
#define I3C_MCTRL_IBIRESP_SHIFT                  (6U)
/*! IBIRESP - In-Band Interrupt (IBI) response
 *  0b00..ACK
 *  0b01..NACK
 *  0b10..ACK_WITH_MANDATORY
 *  0b11..MANUAL
 */
#define I3C_MCTRL_IBIRESP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK)

#define I3C_MCTRL_DIR_MASK                       (0x100U)
#define I3C_MCTRL_DIR_SHIFT                      (8U)
/*! DIR - DIR
 *  0b0..DIRWRITE: Write
 *  0b1..DIRREAD: Read
 */
#define I3C_MCTRL_DIR(x)                         (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK)

#define I3C_MCTRL_ADDR_MASK                      (0xFE00U)
#define I3C_MCTRL_ADDR_SHIFT                     (9U)
/*! ADDR - ADDR */
#define I3C_MCTRL_ADDR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)

#define I3C_MCTRL_RDTERM_MASK                    (0xFF0000U)
#define I3C_MCTRL_RDTERM_SHIFT                   (16U)
/*! RDTERM - Read terminate */
#define I3C_MCTRL_RDTERM(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK)
/*! @} */

/*! @name MSTATUS - Master Status Register */
/*! @{ */

#define I3C_MSTATUS_STATE_MASK                   (0x7U)
#define I3C_MSTATUS_STATE_SHIFT                  (0U)
/*! STATE - State of the master
 *  0b000..IDLE
 *  0b001..SLVREQ
 *  0b010..MSGSDR
 *  0b011..NORMACT
 *  0b100..MSGDDR
 *  0b101..DAA
 *  0b110..IBIACK
 *  0b111..IBIRCV
 */
#define I3C_MSTATUS_STATE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK)

#define I3C_MSTATUS_BETWEEN_MASK                 (0x10U)
#define I3C_MSTATUS_BETWEEN_SHIFT                (4U)
/*! BETWEEN - Between
 *  0b0..Inactive
 *  0b1..Active
 */
#define I3C_MSTATUS_BETWEEN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK)

#define I3C_MSTATUS_NACKED_MASK                  (0x20U)
#define I3C_MSTATUS_NACKED_SHIFT                 (5U)
/*! NACKED - Not acknowledged */
#define I3C_MSTATUS_NACKED(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK)

#define I3C_MSTATUS_IBITYPE_MASK                 (0xC0U)
#define I3C_MSTATUS_IBITYPE_SHIFT                (6U)
/*! IBITYPE - In-Band Interrupt (IBI) type
 *  0b00..NONE
 *  0b01..IBI
 *  0b10..MR
 *  0b11..HJ
 */
#define I3C_MSTATUS_IBITYPE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK)

#define I3C_MSTATUS_SLVSTART_MASK                (0x100U)
#define I3C_MSTATUS_SLVSTART_SHIFT               (8U)
/*! SLVSTART - Slave start */
#define I3C_MSTATUS_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK)

#define I3C_MSTATUS_MCTRLDONE_MASK               (0x200U)
#define I3C_MSTATUS_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - Master control done */
#define I3C_MSTATUS_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK)

#define I3C_MSTATUS_COMPLETE_MASK                (0x400U)
#define I3C_MSTATUS_COMPLETE_SHIFT               (10U)
/*! COMPLETE - COMPLETE */
#define I3C_MSTATUS_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK)

#define I3C_MSTATUS_RXPEND_MASK                  (0x800U)
#define I3C_MSTATUS_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND */
#define I3C_MSTATUS_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK)

#define I3C_MSTATUS_TXNOTFULL_MASK               (0x1000U)
#define I3C_MSTATUS_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TX buffer/FIFO not yet full */
#define I3C_MSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK)

#define I3C_MSTATUS_IBIWON_MASK                  (0x2000U)
#define I3C_MSTATUS_IBIWON_SHIFT                 (13U)
/*! IBIWON - In-Band Interrupt (IBI) won */
#define I3C_MSTATUS_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK)

#define I3C_MSTATUS_ERRWARN_MASK                 (0x8000U)
#define I3C_MSTATUS_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error or warning */
#define I3C_MSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK)

#define I3C_MSTATUS_NOWMASTER_MASK               (0x80000U)
#define I3C_MSTATUS_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - Now master (now this module is a master) */
#define I3C_MSTATUS_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK)

#define I3C_MSTATUS_IBIADDR_MASK                 (0x7F000000U)
#define I3C_MSTATUS_IBIADDR_SHIFT                (24U)
/*! IBIADDR - IBI address */
#define I3C_MSTATUS_IBIADDR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK)
/*! @} */

/*! @name MIBIRULES - Master In-band Interrupt Registry and Rules Register */
/*! @{ */

#define I3C_MIBIRULES_ADDR0_MASK                 (0x3FU)
#define I3C_MIBIRULES_ADDR0_SHIFT                (0U)
/*! ADDR0 - ADDR0 */
#define I3C_MIBIRULES_ADDR0(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK)

#define I3C_MIBIRULES_ADDR1_MASK                 (0xFC0U)
#define I3C_MIBIRULES_ADDR1_SHIFT                (6U)
/*! ADDR1 - ADDR1 */
#define I3C_MIBIRULES_ADDR1(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK)

#define I3C_MIBIRULES_ADDR2_MASK                 (0x3F000U)
#define I3C_MIBIRULES_ADDR2_SHIFT                (12U)
/*! ADDR2 - ADDR2 */
#define I3C_MIBIRULES_ADDR2(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK)

#define I3C_MIBIRULES_ADDR3_MASK                 (0xFC0000U)
#define I3C_MIBIRULES_ADDR3_SHIFT                (18U)
/*! ADDR3 - ADDR3 */
#define I3C_MIBIRULES_ADDR3(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK)

#define I3C_MIBIRULES_ADDR4_MASK                 (0x3F000000U)
#define I3C_MIBIRULES_ADDR4_SHIFT                (24U)
/*! ADDR4 - ADDR4 */
#define I3C_MIBIRULES_ADDR4(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK)

#define I3C_MIBIRULES_MSB0_MASK                  (0x40000000U)
#define I3C_MIBIRULES_MSB0_SHIFT                 (30U)
/*! MSB0 - Set Most Significant address Bit to 0 */
#define I3C_MIBIRULES_MSB0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK)

#define I3C_MIBIRULES_NOBYTE_MASK                (0x80000000U)
#define I3C_MIBIRULES_NOBYTE_SHIFT               (31U)
/*! NOBYTE - No IBI byte */
#define I3C_MIBIRULES_NOBYTE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK)
/*! @} */

/*! @name MINTSET - Master Interrupt Set Register */
/*! @{ */

#define I3C_MINTSET_SLVSTART_MASK                (0x100U)
#define I3C_MINTSET_SLVSTART_SHIFT               (8U)
/*! SLVSTART - Slave start interrupt enable */
#define I3C_MINTSET_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK)

#define I3C_MINTSET_MCTRLDONE_MASK               (0x200U)
#define I3C_MINTSET_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - Master control done interrupt enable */
#define I3C_MINTSET_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK)

#define I3C_MINTSET_COMPLETE_MASK                (0x400U)
#define I3C_MINTSET_COMPLETE_SHIFT               (10U)
/*! COMPLETE - Completed message interrupt enable */
#define I3C_MINTSET_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK)

#define I3C_MINTSET_RXPEND_MASK                  (0x800U)
#define I3C_MINTSET_RXPEND_SHIFT                 (11U)
/*! RXPEND - RX pending interrupt enable */
#define I3C_MINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK)

#define I3C_MINTSET_TXNOTFULL_MASK               (0x1000U)
#define I3C_MINTSET_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TX buffer/FIFO is not full interrupt enable */
#define I3C_MINTSET_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK)

#define I3C_MINTSET_IBIWON_MASK                  (0x2000U)
#define I3C_MINTSET_IBIWON_SHIFT                 (13U)
/*! IBIWON - In-Band Interrupt (IBI) won interrupt enable */
#define I3C_MINTSET_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK)

#define I3C_MINTSET_ERRWARN_MASK                 (0x8000U)
#define I3C_MINTSET_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error or warning (ERRWARN) interrupt enable */
#define I3C_MINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK)

#define I3C_MINTSET_NOWMASTER_MASK               (0x80000U)
#define I3C_MINTSET_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - Now master (now this I3C module is a master) interrupt enable */
#define I3C_MINTSET_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK)
/*! @} */

/*! @name MINTCLR - Master Interrupt Clear Register */
/*! @{ */

#define I3C_MINTCLR_SLVSTART_MASK                (0x100U)
#define I3C_MINTCLR_SLVSTART_SHIFT               (8U)
/*! SLVSTART - SLVSTART interrupt enable clear */
#define I3C_MINTCLR_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK)

#define I3C_MINTCLR_MCTRLDONE_MASK               (0x200U)
#define I3C_MINTCLR_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - MCTRLDONE interrupt enable clear */
#define I3C_MINTCLR_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK)

#define I3C_MINTCLR_COMPLETE_MASK                (0x400U)
#define I3C_MINTCLR_COMPLETE_SHIFT               (10U)
/*! COMPLETE - COMPLETE interrupt enable clear */
#define I3C_MINTCLR_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK)

#define I3C_MINTCLR_RXPEND_MASK                  (0x800U)
#define I3C_MINTCLR_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND interrupt enable clear */
#define I3C_MINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK)

#define I3C_MINTCLR_TXNOTFULL_MASK               (0x1000U)
#define I3C_MINTCLR_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TXNOTFULL interrupt enable clear */
#define I3C_MINTCLR_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK)

#define I3C_MINTCLR_IBIWON_MASK                  (0x2000U)
#define I3C_MINTCLR_IBIWON_SHIFT                 (13U)
/*! IBIWON - IBIWON interrupt enable clear */
#define I3C_MINTCLR_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK)

#define I3C_MINTCLR_ERRWARN_MASK                 (0x8000U)
#define I3C_MINTCLR_ERRWARN_SHIFT                (15U)
/*! ERRWARN - ERRWARN interrupt enable clear */
#define I3C_MINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK)

#define I3C_MINTCLR_NOWMASTER_MASK               (0x80000U)
#define I3C_MINTCLR_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - NOWMASTER interrupt enable clear */
#define I3C_MINTCLR_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK)
/*! @} */

/*! @name MINTMASKED - Master Interrupt Mask Register */
/*! @{ */

#define I3C_MINTMASKED_SLVSTART_MASK             (0x100U)
#define I3C_MINTMASKED_SLVSTART_SHIFT            (8U)
/*! SLVSTART - SLVSTART interrupt mask */
#define I3C_MINTMASKED_SLVSTART(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK)

#define I3C_MINTMASKED_MCTRLDONE_MASK            (0x200U)
#define I3C_MINTMASKED_MCTRLDONE_SHIFT           (9U)
/*! MCTRLDONE - MCTRLDONE interrupt mask */
#define I3C_MINTMASKED_MCTRLDONE(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK)

#define I3C_MINTMASKED_COMPLETE_MASK             (0x400U)
#define I3C_MINTMASKED_COMPLETE_SHIFT            (10U)
/*! COMPLETE - COMPLETE interrupt mask */
#define I3C_MINTMASKED_COMPLETE(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK)

#define I3C_MINTMASKED_RXPEND_MASK               (0x800U)
#define I3C_MINTMASKED_RXPEND_SHIFT              (11U)
/*! RXPEND - RXPEND interrupt mask */
#define I3C_MINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK)

#define I3C_MINTMASKED_TXNOTFULL_MASK            (0x1000U)
#define I3C_MINTMASKED_TXNOTFULL_SHIFT           (12U)
/*! TXNOTFULL - TXNOTFULL interrupt mask */
#define I3C_MINTMASKED_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK)

#define I3C_MINTMASKED_IBIWON_MASK               (0x2000U)
#define I3C_MINTMASKED_IBIWON_SHIFT              (13U)
/*! IBIWON - IBIWON interrupt mask */
#define I3C_MINTMASKED_IBIWON(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK)

#define I3C_MINTMASKED_ERRWARN_MASK              (0x8000U)
#define I3C_MINTMASKED_ERRWARN_SHIFT             (15U)
/*! ERRWARN - ERRWARN interrupt mask */
#define I3C_MINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK)

#define I3C_MINTMASKED_NOWMASTER_MASK            (0x80000U)
#define I3C_MINTMASKED_NOWMASTER_SHIFT           (19U)
/*! NOWMASTER - NOWMASTER interrupt mask */
#define I3C_MINTMASKED_NOWMASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK)
/*! @} */

/*! @name MERRWARN - Master Errors and Warnings Register */
/*! @{ */

#define I3C_MERRWARN_NACK_MASK                   (0x4U)
#define I3C_MERRWARN_NACK_SHIFT                  (2U)
/*! NACK - Not acknowledge (NACK) error */
#define I3C_MERRWARN_NACK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK)

#define I3C_MERRWARN_WRABT_MASK                  (0x8U)
#define I3C_MERRWARN_WRABT_SHIFT                 (3U)
/*! WRABT - WRABT (Write abort) error */
#define I3C_MERRWARN_WRABT(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK)

#define I3C_MERRWARN_TERM_MASK                   (0x10U)
#define I3C_MERRWARN_TERM_SHIFT                  (4U)
/*! TERM - Terminate error */
#define I3C_MERRWARN_TERM(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK)

#define I3C_MERRWARN_HPAR_MASK                   (0x200U)
#define I3C_MERRWARN_HPAR_SHIFT                  (9U)
/*! HPAR - High data rate parity */
#define I3C_MERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK)

#define I3C_MERRWARN_HCRC_MASK                   (0x400U)
#define I3C_MERRWARN_HCRC_SHIFT                  (10U)
/*! HCRC - High data rate CRC error */
#define I3C_MERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK)

#define I3C_MERRWARN_OREAD_MASK                  (0x10000U)
#define I3C_MERRWARN_OREAD_SHIFT                 (16U)
/*! OREAD - Over-read error */
#define I3C_MERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK)

#define I3C_MERRWARN_OWRITE_MASK                 (0x20000U)
#define I3C_MERRWARN_OWRITE_SHIFT                (17U)
/*! OWRITE - Over-write error */
#define I3C_MERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK)

#define I3C_MERRWARN_MSGERR_MASK                 (0x40000U)
#define I3C_MERRWARN_MSGERR_SHIFT                (18U)
/*! MSGERR - Message error */
#define I3C_MERRWARN_MSGERR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK)

#define I3C_MERRWARN_INVREQ_MASK                 (0x80000U)
#define I3C_MERRWARN_INVREQ_SHIFT                (19U)
/*! INVREQ - Invalid request error */
#define I3C_MERRWARN_INVREQ(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK)

#define I3C_MERRWARN_TIMEOUT_MASK                (0x100000U)
#define I3C_MERRWARN_TIMEOUT_SHIFT               (20U)
/*! TIMEOUT - TIMEOUT error */
#define I3C_MERRWARN_TIMEOUT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK)
/*! @} */

/*! @name MDMACTRL - Master DMA Control Register */
/*! @{ */

#define I3C_MDMACTRL_DMAFB_MASK                  (0x3U)
#define I3C_MDMACTRL_DMAFB_SHIFT                 (0U)
/*! DMAFB - DMA from bus
 *  0b00..NOT_USED. DMA is not used
 *  0b01..ENABLE_ONE_FRAME
 *  0b10..ENABLE
 */
#define I3C_MDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK)

#define I3C_MDMACTRL_DMATB_MASK                  (0xCU)
#define I3C_MDMACTRL_DMATB_SHIFT                 (2U)
/*! DMATB - DMA to bus
 *  0b00..NOT_USED. DMA is not used
 *  0b01..ENABLE_ONE_FRAME
 *  0b10..ENABLE
 */
#define I3C_MDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK)

#define I3C_MDMACTRL_DMAWIDTH_MASK               (0x30U)
#define I3C_MDMACTRL_DMAWIDTH_SHIFT              (4U)
/*! DMAWIDTH - DMA width
 *  0b00..BYTE
 *  0b01..BYTE_AGAIN
 *  0b10..HALF_WORD
 *  0b11..
 */
#define I3C_MDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK)
/*! @} */

/*! @name MDATACTRL - Master Data Control Register */
/*! @{ */

#define I3C_MDATACTRL_FLUSHTB_MASK               (0x1U)
#define I3C_MDATACTRL_FLUSHTB_SHIFT              (0U)
/*! FLUSHTB - Flush to-bus buffer/FIFO */
#define I3C_MDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK)

#define I3C_MDATACTRL_FLUSHFB_MASK               (0x2U)
#define I3C_MDATACTRL_FLUSHFB_SHIFT              (1U)
/*! FLUSHFB - Flush from-bus buffer/FIFO */
#define I3C_MDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK)

#define I3C_MDATACTRL_UNLOCK_MASK                (0x4U)
#define I3C_MDATACTRL_UNLOCK_SHIFT               (2U)
/*! UNLOCK - Unlock */
#define I3C_MDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK)

#define I3C_MDATACTRL_TXTRIG_MASK                (0x30U)
#define I3C_MDATACTRL_TXTRIG_SHIFT               (4U)
/*! TXTRIG - TX trigger level */
#define I3C_MDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK)

#define I3C_MDATACTRL_RXTRIG_MASK                (0xC0U)
#define I3C_MDATACTRL_RXTRIG_SHIFT               (6U)
/*! RXTRIG - RX trigger level */
#define I3C_MDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK)

#define I3C_MDATACTRL_TXCOUNT_MASK               (0x1F0000U)
#define I3C_MDATACTRL_TXCOUNT_SHIFT              (16U)
/*! TXCOUNT - TX byte count */
#define I3C_MDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK)

#define I3C_MDATACTRL_RXCOUNT_MASK               (0x1F000000U)
#define I3C_MDATACTRL_RXCOUNT_SHIFT              (24U)
/*! RXCOUNT - RX byte count */
#define I3C_MDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK)

#define I3C_MDATACTRL_TXFULL_MASK                (0x40000000U)
#define I3C_MDATACTRL_TXFULL_SHIFT               (30U)
/*! TXFULL - TX is full */
#define I3C_MDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK)

#define I3C_MDATACTRL_RXEMPTY_MASK               (0x80000000U)
#define I3C_MDATACTRL_RXEMPTY_SHIFT              (31U)
/*! RXEMPTY - RX is empty */
#define I3C_MDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK)
/*! @} */

/*! @name MWDATAB - Master Write Data Byte Register */
/*! @{ */

#define I3C_MWDATAB_VALUE_MASK                   (0xFFU)
#define I3C_MWDATAB_VALUE_SHIFT                  (0U)
/*! VALUE - Data byte */
#define I3C_MWDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK)

#define I3C_MWDATAB_END_MASK                     (0x100U)
#define I3C_MWDATAB_END_SHIFT                    (8U)
/*! END - End of message */
#define I3C_MWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK)

#define I3C_MWDATAB_END_ALSO_MASK                (0x10000U)
#define I3C_MWDATAB_END_ALSO_SHIFT               (16U)
/*! END_ALSO - End of message also */
#define I3C_MWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK)
/*! @} */

/*! @name MWDATABE - Master Write Data Byte End Register */
/*! @{ */

#define I3C_MWDATABE_VALUE_MASK                  (0xFFU)
#define I3C_MWDATABE_VALUE_SHIFT                 (0U)
/*! VALUE - Data */
#define I3C_MWDATABE_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK)
/*! @} */

/*! @name MWDATAH - Master Write Data Half-word Register */
/*! @{ */

#define I3C_MWDATAH_DATA0_MASK                   (0xFFU)
#define I3C_MWDATAH_DATA0_SHIFT                  (0U)
/*! DATA0 - Data byte 0 */
#define I3C_MWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK)

#define I3C_MWDATAH_DATA1_MASK                   (0xFF00U)
#define I3C_MWDATAH_DATA1_SHIFT                  (8U)
/*! DATA1 - Data byte 1 */
#define I3C_MWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK)

#define I3C_MWDATAH_END_MASK                     (0x10000U)
#define I3C_MWDATAH_END_SHIFT                    (16U)
/*! END - End of message */
#define I3C_MWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK)
/*! @} */

/*! @name MWDATAHE - Master Write Data Byte End Register */
/*! @{ */

#define I3C_MWDATAHE_DATA0_MASK                  (0xFFU)
#define I3C_MWDATAHE_DATA0_SHIFT                 (0U)
/*! DATA0 - DATA 0 */
#define I3C_MWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK)

#define I3C_MWDATAHE_DATA1_MASK                  (0xFF00U)
#define I3C_MWDATAHE_DATA1_SHIFT                 (8U)
/*! DATA1 - DATA 1 */
#define I3C_MWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK)
/*! @} */

/*! @name MRDATAB - Master Read Data Byte Register */
/*! @{ */

#define I3C_MRDATAB_VALUE_MASK                   (0xFFU)
#define I3C_MRDATAB_VALUE_SHIFT                  (0U)
/*! VALUE - VALUE */
#define I3C_MRDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK)
/*! @} */

/*! @name MRDATAH - Master Read Data Half-word Register */
/*! @{ */

#define I3C_MRDATAH_LSB_MASK                     (0xFFU)
#define I3C_MRDATAH_LSB_SHIFT                    (0U)
/*! LSB - LSB */
#define I3C_MRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK)

#define I3C_MRDATAH_MSB_MASK                     (0xFF00U)
#define I3C_MRDATAH_MSB_SHIFT                    (8U)
/*! MSB - MSB */
#define I3C_MRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK)
/*! @} */

/*! @name MWDATAB1 - Write Byte Data 1 (to bus) */
/*! @{ */

#define I3C_MWDATAB1_VALUE_MASK                  (0xFFU)
#define I3C_MWDATAB1_VALUE_SHIFT                 (0U)
/*! VALUE - Value */
#define I3C_MWDATAB1_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK)
/*! @} */

/*! @name MWMSG_SDR_CONTROL - Master Write Message in SDR mode */
/*! @{ */

#define I3C_MWMSG_SDR_CONTROL_DIR_MASK           (0x1U)
#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT          (0U)
/*! DIR - Direction
 *  0b0..Write
 *  0b1..Read
 */
#define I3C_MWMSG_SDR_CONTROL_DIR(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK)

#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK          (0xFEU)
#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT         (1U)
/*! ADDR - Address to be written to */
#define I3C_MWMSG_SDR_CONTROL_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK)

#define I3C_MWMSG_SDR_CONTROL_END_MASK           (0x100U)
#define I3C_MWMSG_SDR_CONTROL_END_SHIFT          (8U)
/*! END - End of SDR message */
#define I3C_MWMSG_SDR_CONTROL_END(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK)

#define I3C_MWMSG_SDR_CONTROL_I2C_MASK           (0x400U)
#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT          (10U)
/*! I2C - I2C
 *  0b0..I3C message
 *  0b1..I2C message
 */
#define I3C_MWMSG_SDR_CONTROL_I2C(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK)

#define I3C_MWMSG_SDR_CONTROL_LEN_MASK           (0xF800U)
#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT          (11U)
/*! LEN - Length */
#define I3C_MWMSG_SDR_CONTROL_LEN(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK)
/*! @} */

/*! @name MWMSG_SDR_DATA - Master Write Message Data in SDR mode */
/*! @{ */

#define I3C_MWMSG_SDR_DATA_DATA16B_MASK          (0xFFFFU)
#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT         (0U)
/*! DATA16B - Data */
#define I3C_MWMSG_SDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK)

#define I3C_MWMSG_SDR_DATA_END_MASK              (0x10000U)
#define I3C_MWMSG_SDR_DATA_END_SHIFT             (16U)
/*! END - End of message */
#define I3C_MWMSG_SDR_DATA_END(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_END_SHIFT)) & I3C_MWMSG_SDR_DATA_END_MASK)
/*! @} */

/*! @name MRMSG_SDR - Master Read Message in SDR mode */
/*! @{ */

#define I3C_MRMSG_SDR_DATA_MASK                  (0xFFFFU)
#define I3C_MRMSG_SDR_DATA_SHIFT                 (0U)
/*! DATA - Data */
#define I3C_MRMSG_SDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK)
/*! @} */

/*! @name MWMSG_DDR_CONTROL - Master Write Message in DDR mode */
/*! @{ */

#define I3C_MWMSG_DDR_CONTROL_LEN_MASK           (0x3FFU)
#define I3C_MWMSG_DDR_CONTROL_LEN_SHIFT          (0U)
/*! LEN - Length of message */
#define I3C_MWMSG_DDR_CONTROL_LEN(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL_LEN_MASK)

#define I3C_MWMSG_DDR_CONTROL_END_MASK           (0x4000U)
#define I3C_MWMSG_DDR_CONTROL_END_SHIFT          (14U)
/*! END - End of message */
#define I3C_MWMSG_DDR_CONTROL_END(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL_END_MASK)
/*! @} */

/*! @name MWMSG_DDR_DATA - Master Write Message Data in DDR mode */
/*! @{ */

#define I3C_MWMSG_DDR_DATA_DATA16B_MASK          (0xFFFFU)
#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT         (0U)
/*! DATA16B - Data */
#define I3C_MWMSG_DDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK)

#define I3C_MWMSG_DDR_DATA_END_MASK              (0x10000U)
#define I3C_MWMSG_DDR_DATA_END_SHIFT             (16U)
/*! END - End of message */
#define I3C_MWMSG_DDR_DATA_END(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_END_SHIFT)) & I3C_MWMSG_DDR_DATA_END_MASK)
/*! @} */

/*! @name MRMSG_DDR - Master Read Message in DDR mode */
/*! @{ */

#define I3C_MRMSG_DDR_DATA_MASK                  (0xFFFFU)
#define I3C_MRMSG_DDR_DATA_SHIFT                 (0U)
/*! DATA - Data */
#define I3C_MRMSG_DDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK)

#define I3C_MRMSG_DDR_CLEN_MASK                  (0x3FF0000U)
#define I3C_MRMSG_DDR_CLEN_SHIFT                 (16U)
/*! CLEN - Current length */
#define I3C_MRMSG_DDR_CLEN(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_CLEN_SHIFT)) & I3C_MRMSG_DDR_CLEN_MASK)
/*! @} */

/*! @name MDYNADDR - Master Dynamic Address Register */
/*! @{ */

#define I3C_MDYNADDR_DAVALID_MASK                (0x1U)
#define I3C_MDYNADDR_DAVALID_SHIFT               (0U)
/*! DAVALID - Dynamic address valid */
#define I3C_MDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK)

#define I3C_MDYNADDR_DADDR_MASK                  (0xFEU)
#define I3C_MDYNADDR_DADDR_SHIFT                 (1U)
/*! DADDR - Dynamic address */
#define I3C_MDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK)
/*! @} */

/*! @name SID - Slave Module ID Register */
/*! @{ */

#define I3C_SID_ID_MASK                          (0xFFFFFFFFU)
#define I3C_SID_ID_SHIFT                         (0U)
/*! ID - ID */
#define I3C_SID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group I3C_Register_Masks */


/* I3C - Peripheral instance base addresses */
/** Peripheral I3C0 base address */
#define I3C0_BASE                                (0x2803D000u)
/** Peripheral I3C0 base pointer */
#define I3C0                                     ((I3C_Type *)I3C0_BASE)
/** Peripheral I3C1 base address */
#define I3C1_BASE                                (0x2810A000u)
/** Peripheral I3C1 base pointer */
#define I3C1                                     ((I3C_Type *)I3C1_BASE)
/** Peripheral I3C2 base address */
#define I3C2_BASE                                (0x29360000u)
/** Peripheral I3C2 base pointer */
#define I3C2                                     ((I3C_Type *)I3C2_BASE)
/** Array initializer of I3C peripheral base addresses */
#define I3C_BASE_ADDRS                           { I3C0_BASE, I3C1_BASE, I3C2_BASE }
/** Array initializer of I3C peripheral base pointers */
#define I3C_BASE_PTRS                            { I3C0, I3C1, I3C2 }

/*!
 * @}
 */ /* end of group I3C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IOMUXC0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOMUXC0_Peripheral_Access_Layer IOMUXC0 Peripheral Access Layer
 * @{
 */

/** IOMUXC0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t PCR0_IOMUXCARRAY0[25];             /**< Pad Control Register, array offset: 0x0, array step: 0x4 */
       uint8_t RESERVED_0[28];
  __IO uint32_t PCR0_IOMUXCARRAY1[16];             /**< Pad Control Register, array offset: 0x80, array step: 0x4 */
       uint8_t RESERVED_1[64];
  __IO uint32_t PCR0_IOMUXCARRAY2[24];             /**< Pad Control Register, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_2[672];
  __IO uint32_t PCR0_IOMUXCARRAY3[2];              /**< Pad Control Register, array offset: 0x400, array step: 0x4 */
       uint8_t RESERVED_3[1016];
  __IO uint32_t PSMI0_IOMUXCARRAY0[5];             /**< Module Input Source Selection Register, array offset: 0x800, array step: 0x4 */
       uint8_t RESERVED_4[132];
  __IO uint32_t PSMI0_IOMUXCARRAY1[3];             /**< Module Input Source Selection Register, array offset: 0x898, array step: 0x4 */
       uint8_t RESERVED_5[12];
  __IO uint32_t PSMI0_IOMUXCARRAY2[4];             /**< Module Input Source Selection Register, array offset: 0x8B0, array step: 0x4 */
       uint8_t RESERVED_6[12];
  __IO uint32_t PSMI0_IOMUXCARRAY3[3];             /**< Module Input Source Selection Register, array offset: 0x8CC, array step: 0x4 */
       uint8_t RESERVED_7[36];
  __IO uint32_t PSMI0_IOMUXCARRAY4[1];             /**< Module Input Source Selection Register, array offset: 0x8FC, array step: 0x4 */
       uint8_t RESERVED_8[40];
  __IO uint32_t PSMI0_IOMUXCARRAY5[10];            /**< Module Input Source Selection Register, array offset: 0x928, array step: 0x4 */
       uint8_t RESERVED_9[8];
  __IO uint32_t PSMI0_IOMUXCARRAY6[3];             /**< Module Input Source Selection Register, array offset: 0x958, array step: 0x4 */
       uint8_t RESERVED_10[16];
  __IO uint32_t PSMI0_IOMUXCARRAY7[15];            /**< Module Input Source Selection Register, array offset: 0x974, array step: 0x4 */
       uint8_t RESERVED_11[8];
  __IO uint32_t PSMI0_IOMUXCARRAY8[15];            /**< Module Input Source Selection Register, array offset: 0x9B8, array step: 0x4 */
       uint8_t RESERVED_12[16];
  __IO uint32_t PSMI0_IOMUXCARRAY9[11];            /**< Module Input Source Selection Register, array offset: 0xA04, array step: 0x4 */
       uint8_t RESERVED_13[4];
  __IO uint32_t PSMI0_IOMUXCARRAY10[24];           /**< Module Input Source Selection Register, array offset: 0xA34, array step: 0x4 */
       uint8_t RESERVED_14[64];
  __IO uint32_t PSMI0_IOMUXCARRAY11[6];            /**< Module Input Source Selection Register, array offset: 0xAD4, array step: 0x4 */
} IOMUXC0_Type;

/* ----------------------------------------------------------------------------
   -- IOMUXC0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOMUXC0_Register_Masks IOMUXC0 Register Masks
 * @{
 */

/*! @name PCR0_IOMUXCARRAY0 - Pad Control Register */
/*! @{ */

#define IOMUXC0_PCR0_IOMUXCARRAY0_PS_MASK        (0x1U)
#define IOMUXC0_PCR0_IOMUXCARRAY0_PS_SHIFT       (0U)
/*! PS - Pull Select
 *  0b0..Pull-down selected
 *  0b1..Pull-up selected
 */
#define IOMUXC0_PCR0_IOMUXCARRAY0_PS(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY0_PS_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY0_PS_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY0_PE_MASK        (0x2U)
#define IOMUXC0_PCR0_IOMUXCARRAY0_PE_SHIFT       (1U)
/*! PE - Pull-up Enable
 *  0b0..pull disabled
 *  0b1..pull enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY0_PE(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY0_PE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY0_PE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY0_SRE_MASK       (0x4U)
#define IOMUXC0_PCR0_IOMUXCARRAY0_SRE_SHIFT      (2U)
/*! SRE - Slew Rate Enable
 *  0b0..Standard Slew Rate
 *  0b1..Slow Slew Rate
 */
#define IOMUXC0_PCR0_IOMUXCARRAY0_SRE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY0_SRE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY0_SRE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY0_ODE_MASK       (0x20U)
#define IOMUXC0_PCR0_IOMUXCARRAY0_ODE_SHIFT      (5U)
/*! ODE - Open-drain Enable
 *  0b0..Push-pull Output
 *  0b1..Open-drain Output
 */
#define IOMUXC0_PCR0_IOMUXCARRAY0_ODE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY0_ODE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY0_ODE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY0_DSE_MASK       (0x40U)
#define IOMUXC0_PCR0_IOMUXCARRAY0_DSE_SHIFT      (6U)
/*! DSE - Drive Strength Enable
 *  0b0..Standard Drive Strength
 *  0b1..Hi Drive Strength
 */
#define IOMUXC0_PCR0_IOMUXCARRAY0_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY0_DSE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY0_DSE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY0_MUX_MASK       (0xF00U)
#define IOMUXC0_PCR0_IOMUXCARRAY0_MUX_SHIFT      (8U)
/*! MUX - PAD Mux Selector
 *  0b0000..Alternate function 0 ; Analog / Hiz
 *  0b0001..Refer to "IO Signal Table" for availabre functions and SS values for each PAD.
 */
#define IOMUXC0_PCR0_IOMUXCARRAY0_MUX(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY0_MUX_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY0_MUX_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY0_LK_MASK        (0x8000U)
#define IOMUXC0_PCR0_IOMUXCARRAY0_LK_SHIFT       (15U)
/*! LK - Lock
 *  0b0..Register Unlocked
 *  0b1..Register Locked for write
 */
#define IOMUXC0_PCR0_IOMUXCARRAY0_LK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY0_LK_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY0_LK_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY0_IBE_MASK       (0x10000U)
#define IOMUXC0_PCR0_IOMUXCARRAY0_IBE_SHIFT      (16U)
/*! IBE - Input Buffer Enable
 *  0b0..Input Buffer enable depends on selected function
 *  0b1..Input buffer forced enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY0_IBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY0_IBE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY0_IBE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY0_OBE_MASK       (0x20000U)
#define IOMUXC0_PCR0_IOMUXCARRAY0_OBE_SHIFT      (17U)
/*! OBE - Output Buffer Enable
 *  0b0..Output Buffer enable depends on selected function
 *  0b1..Output buffer forced enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY0_OBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY0_OBE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY0_OBE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY0_DFE_MASK       (0x100000U)
#define IOMUXC0_PCR0_IOMUXCARRAY0_DFE_SHIFT      (20U)
/*! DFE - Digital Filter Enable
 *  0b0..Digital filter disabled
 *  0b1..Digital filter enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY0_DFE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY0_DFE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY0_DFE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY0_DFCS_MASK      (0x200000U)
#define IOMUXC0_PCR0_IOMUXCARRAY0_DFCS_SHIFT     (21U)
/*! DFCS - Digital Filter Clock Select
 *  0b0..Digital filter is running out of PCTL* Bus clock
 *  0b1..Digital filter is running out RTC 1kHz clock
 */
#define IOMUXC0_PCR0_IOMUXCARRAY0_DFCS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY0_DFCS_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY0_DFCS_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY0_DFD_MASK       (0x7C00000U)
#define IOMUXC0_PCR0_IOMUXCARRAY0_DFD_SHIFT      (22U)
/*! DFD - Digital Filter Duration
 *  0b00000..Digital filter is disabled
 *  0b00001..Filter window count value
 */
#define IOMUXC0_PCR0_IOMUXCARRAY0_DFD(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY0_DFD_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY0_DFD_MASK)
/*! @} */

/* The count of IOMUXC0_PCR0_IOMUXCARRAY0 */
#define IOMUXC0_PCR0_IOMUXCARRAY0_COUNT          (25U)

/*! @name PCR0_IOMUXCARRAY1 - Pad Control Register */
/*! @{ */

#define IOMUXC0_PCR0_IOMUXCARRAY1_PS_MASK        (0x1U)
#define IOMUXC0_PCR0_IOMUXCARRAY1_PS_SHIFT       (0U)
/*! PS - Pull Select
 *  0b0..Pull-down selected
 *  0b1..Pull-up selected
 */
#define IOMUXC0_PCR0_IOMUXCARRAY1_PS(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY1_PS_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY1_PS_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY1_PE_MASK        (0x2U)
#define IOMUXC0_PCR0_IOMUXCARRAY1_PE_SHIFT       (1U)
/*! PE - Pull-up Enable
 *  0b0..pull disabled
 *  0b1..pull enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY1_PE(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY1_PE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY1_PE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY1_SRE_MASK       (0x4U)
#define IOMUXC0_PCR0_IOMUXCARRAY1_SRE_SHIFT      (2U)
/*! SRE - Slew Rate Enable
 *  0b0..Standard Slew Rate
 *  0b1..Slow Slew Rate
 */
#define IOMUXC0_PCR0_IOMUXCARRAY1_SRE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY1_SRE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY1_SRE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY1_ODE_MASK       (0x20U)
#define IOMUXC0_PCR0_IOMUXCARRAY1_ODE_SHIFT      (5U)
/*! ODE - Open-drain Enable
 *  0b0..Push-pull Output
 *  0b1..Open-drain Output
 */
#define IOMUXC0_PCR0_IOMUXCARRAY1_ODE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY1_ODE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY1_ODE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY1_DSE_MASK       (0x40U)
#define IOMUXC0_PCR0_IOMUXCARRAY1_DSE_SHIFT      (6U)
/*! DSE - Drive Strength Enable
 *  0b0..Standard Drive Strength
 *  0b1..Hi Drive Strength
 */
#define IOMUXC0_PCR0_IOMUXCARRAY1_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY1_DSE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY1_DSE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY1_MUX_MASK       (0xF00U)
#define IOMUXC0_PCR0_IOMUXCARRAY1_MUX_SHIFT      (8U)
/*! MUX - PAD Mux Selector
 *  0b0000..Alternate function 0 ; Analog / Hiz
 *  0b0001..Refer to "IO Signal Table" for availabre functions and SS values for each PAD.
 */
#define IOMUXC0_PCR0_IOMUXCARRAY1_MUX(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY1_MUX_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY1_MUX_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY1_LK_MASK        (0x8000U)
#define IOMUXC0_PCR0_IOMUXCARRAY1_LK_SHIFT       (15U)
/*! LK - Lock
 *  0b0..Register Unlocked
 *  0b1..Register Locked for write
 */
#define IOMUXC0_PCR0_IOMUXCARRAY1_LK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY1_LK_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY1_LK_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY1_IBE_MASK       (0x10000U)
#define IOMUXC0_PCR0_IOMUXCARRAY1_IBE_SHIFT      (16U)
/*! IBE - Input Buffer Enable
 *  0b0..Input Buffer enable depends on selected function
 *  0b1..Input buffer forced enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY1_IBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY1_IBE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY1_IBE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY1_OBE_MASK       (0x20000U)
#define IOMUXC0_PCR0_IOMUXCARRAY1_OBE_SHIFT      (17U)
/*! OBE - Output Buffer Enable
 *  0b0..Output Buffer enable depends on selected function
 *  0b1..Output buffer forced enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY1_OBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY1_OBE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY1_OBE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY1_DFE_MASK       (0x100000U)
#define IOMUXC0_PCR0_IOMUXCARRAY1_DFE_SHIFT      (20U)
/*! DFE - Digital Filter Enable
 *  0b0..Digital filter disabled
 *  0b1..Digital filter enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY1_DFE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY1_DFE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY1_DFE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY1_DFCS_MASK      (0x200000U)
#define IOMUXC0_PCR0_IOMUXCARRAY1_DFCS_SHIFT     (21U)
/*! DFCS - Digital Filter Clock Select
 *  0b0..Digital filter is running out of PCTL* Bus clock
 *  0b1..Digital filter is running out RTC 1kHz clock
 */
#define IOMUXC0_PCR0_IOMUXCARRAY1_DFCS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY1_DFCS_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY1_DFCS_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY1_DFD_MASK       (0x7C00000U)
#define IOMUXC0_PCR0_IOMUXCARRAY1_DFD_SHIFT      (22U)
/*! DFD - Digital Filter Duration
 *  0b00000..Digital filter is disabled
 *  0b00001..Filter window count value
 */
#define IOMUXC0_PCR0_IOMUXCARRAY1_DFD(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY1_DFD_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY1_DFD_MASK)
/*! @} */

/* The count of IOMUXC0_PCR0_IOMUXCARRAY1 */
#define IOMUXC0_PCR0_IOMUXCARRAY1_COUNT          (16U)

/*! @name PCR0_IOMUXCARRAY2 - Pad Control Register */
/*! @{ */

#define IOMUXC0_PCR0_IOMUXCARRAY2_PS_MASK        (0x1U)
#define IOMUXC0_PCR0_IOMUXCARRAY2_PS_SHIFT       (0U)
/*! PS - Pull Select
 *  0b0..Pull-down selected
 *  0b1..Pull-up selected
 */
#define IOMUXC0_PCR0_IOMUXCARRAY2_PS(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY2_PS_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY2_PS_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY2_PE_MASK        (0x2U)
#define IOMUXC0_PCR0_IOMUXCARRAY2_PE_SHIFT       (1U)
/*! PE - Pull-up Enable
 *  0b0..pull disabled
 *  0b1..pull enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY2_PE(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY2_PE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY2_PE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY2_SRE_MASK       (0x4U)
#define IOMUXC0_PCR0_IOMUXCARRAY2_SRE_SHIFT      (2U)
/*! SRE - Slew Rate Enable
 *  0b0..Standard Slew Rate
 *  0b1..Slow Slew Rate
 */
#define IOMUXC0_PCR0_IOMUXCARRAY2_SRE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY2_SRE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY2_SRE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY2_ODE_MASK       (0x20U)
#define IOMUXC0_PCR0_IOMUXCARRAY2_ODE_SHIFT      (5U)
/*! ODE - Open-drain Enable
 *  0b0..Push-pull Output
 *  0b1..Open-drain Output
 */
#define IOMUXC0_PCR0_IOMUXCARRAY2_ODE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY2_ODE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY2_ODE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY2_DSE_MASK       (0x40U)
#define IOMUXC0_PCR0_IOMUXCARRAY2_DSE_SHIFT      (6U)
/*! DSE - Drive Strength Enable
 *  0b0..Standard Drive Strength
 *  0b1..Hi Drive Strength
 */
#define IOMUXC0_PCR0_IOMUXCARRAY2_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY2_DSE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY2_DSE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY2_MUX_MASK       (0xF00U)
#define IOMUXC0_PCR0_IOMUXCARRAY2_MUX_SHIFT      (8U)
/*! MUX - PAD Mux Selector
 *  0b0000..Alternate function 0 ; Analog / Hiz
 *  0b0001..Refer to "IO Signal Table" for availabre functions and SS values for each PAD.
 */
#define IOMUXC0_PCR0_IOMUXCARRAY2_MUX(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY2_MUX_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY2_MUX_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY2_LK_MASK        (0x8000U)
#define IOMUXC0_PCR0_IOMUXCARRAY2_LK_SHIFT       (15U)
/*! LK - Lock
 *  0b0..Register Unlocked
 *  0b1..Register Locked for write
 */
#define IOMUXC0_PCR0_IOMUXCARRAY2_LK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY2_LK_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY2_LK_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY2_IBE_MASK       (0x10000U)
#define IOMUXC0_PCR0_IOMUXCARRAY2_IBE_SHIFT      (16U)
/*! IBE - Input Buffer Enable
 *  0b0..Input Buffer enable depends on selected function
 *  0b1..Input buffer forced enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY2_IBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY2_IBE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY2_IBE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY2_OBE_MASK       (0x20000U)
#define IOMUXC0_PCR0_IOMUXCARRAY2_OBE_SHIFT      (17U)
/*! OBE - Output Buffer Enable
 *  0b0..Output Buffer enable depends on selected function
 *  0b1..Output buffer forced enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY2_OBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY2_OBE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY2_OBE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY2_DFE_MASK       (0x100000U)
#define IOMUXC0_PCR0_IOMUXCARRAY2_DFE_SHIFT      (20U)
/*! DFE - Digital Filter Enable
 *  0b0..Digital filter disabled
 *  0b1..Digital filter enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY2_DFE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY2_DFE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY2_DFE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY2_DFCS_MASK      (0x200000U)
#define IOMUXC0_PCR0_IOMUXCARRAY2_DFCS_SHIFT     (21U)
/*! DFCS - Digital Filter Clock Select
 *  0b0..Digital filter is running out of PCTL* Bus clock
 *  0b1..Digital filter is running out RTC 1kHz clock
 */
#define IOMUXC0_PCR0_IOMUXCARRAY2_DFCS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY2_DFCS_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY2_DFCS_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY2_DFD_MASK       (0x7C00000U)
#define IOMUXC0_PCR0_IOMUXCARRAY2_DFD_SHIFT      (22U)
/*! DFD - Digital Filter Duration
 *  0b00000..Digital filter is disabled
 *  0b00001..Filter window count value
 */
#define IOMUXC0_PCR0_IOMUXCARRAY2_DFD(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY2_DFD_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY2_DFD_MASK)
/*! @} */

/* The count of IOMUXC0_PCR0_IOMUXCARRAY2 */
#define IOMUXC0_PCR0_IOMUXCARRAY2_COUNT          (24U)

/*! @name PCR0_IOMUXCARRAY3 - Pad Control Register */
/*! @{ */

#define IOMUXC0_PCR0_IOMUXCARRAY3_PS_MASK        (0x1U)
#define IOMUXC0_PCR0_IOMUXCARRAY3_PS_SHIFT       (0U)
/*! PS - Pull Select
 *  0b0..Pull-down selected
 *  0b1..Pull-up selected
 */
#define IOMUXC0_PCR0_IOMUXCARRAY3_PS(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY3_PS_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY3_PS_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY3_PE_MASK        (0x2U)
#define IOMUXC0_PCR0_IOMUXCARRAY3_PE_SHIFT       (1U)
/*! PE - Pull-up Enable
 *  0b0..pull disabled
 *  0b1..pull enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY3_PE(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY3_PE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY3_PE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY3_SRE_MASK       (0x4U)
#define IOMUXC0_PCR0_IOMUXCARRAY3_SRE_SHIFT      (2U)
/*! SRE - Slew Rate Enable
 *  0b0..Standard Slew Rate
 *  0b1..Slow Slew Rate
 */
#define IOMUXC0_PCR0_IOMUXCARRAY3_SRE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY3_SRE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY3_SRE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY3_ODE_MASK       (0x20U)
#define IOMUXC0_PCR0_IOMUXCARRAY3_ODE_SHIFT      (5U)
/*! ODE - Open-drain Enable
 *  0b0..Push-pull Output
 *  0b1..Open-drain Output
 */
#define IOMUXC0_PCR0_IOMUXCARRAY3_ODE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY3_ODE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY3_ODE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY3_DSE_MASK       (0x40U)
#define IOMUXC0_PCR0_IOMUXCARRAY3_DSE_SHIFT      (6U)
/*! DSE - Drive Strength Enable
 *  0b0..Standard Drive Strength
 *  0b1..Hi Drive Strength
 */
#define IOMUXC0_PCR0_IOMUXCARRAY3_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY3_DSE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY3_DSE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY3_MUX_MASK       (0xF00U)
#define IOMUXC0_PCR0_IOMUXCARRAY3_MUX_SHIFT      (8U)
/*! MUX - PAD Mux Selector
 *  0b0000..Alternate function 0 ; Analog / Hiz
 *  0b0001..Refer to "IO Signal Table" for availabre functions and SS values for each PAD.
 */
#define IOMUXC0_PCR0_IOMUXCARRAY3_MUX(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY3_MUX_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY3_MUX_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY3_LK_MASK        (0x8000U)
#define IOMUXC0_PCR0_IOMUXCARRAY3_LK_SHIFT       (15U)
/*! LK - Lock
 *  0b0..Register Unlocked
 *  0b1..Register Locked for write
 */
#define IOMUXC0_PCR0_IOMUXCARRAY3_LK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY3_LK_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY3_LK_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY3_IBE_MASK       (0x10000U)
#define IOMUXC0_PCR0_IOMUXCARRAY3_IBE_SHIFT      (16U)
/*! IBE - Input Buffer Enable
 *  0b0..Input Buffer enable depends on selected function
 *  0b1..Input buffer forced enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY3_IBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY3_IBE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY3_IBE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY3_OBE_MASK       (0x20000U)
#define IOMUXC0_PCR0_IOMUXCARRAY3_OBE_SHIFT      (17U)
/*! OBE - Output Buffer Enable
 *  0b0..Output Buffer enable depends on selected function
 *  0b1..Output buffer forced enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY3_OBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY3_OBE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY3_OBE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY3_DFE_MASK       (0x100000U)
#define IOMUXC0_PCR0_IOMUXCARRAY3_DFE_SHIFT      (20U)
/*! DFE - Digital Filter Enable
 *  0b0..Digital filter disabled
 *  0b1..Digital filter enabled
 */
#define IOMUXC0_PCR0_IOMUXCARRAY3_DFE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY3_DFE_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY3_DFE_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY3_DFCS_MASK      (0x200000U)
#define IOMUXC0_PCR0_IOMUXCARRAY3_DFCS_SHIFT     (21U)
/*! DFCS - Digital Filter Clock Select
 *  0b0..Digital filter is running out of PCTL* Bus clock
 *  0b1..Digital filter is running out RTC 1kHz clock
 */
#define IOMUXC0_PCR0_IOMUXCARRAY3_DFCS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY3_DFCS_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY3_DFCS_MASK)

#define IOMUXC0_PCR0_IOMUXCARRAY3_DFD_MASK       (0x7C00000U)
#define IOMUXC0_PCR0_IOMUXCARRAY3_DFD_SHIFT      (22U)
/*! DFD - Digital Filter Duration
 *  0b00000..Digital filter is disabled
 *  0b00001..Filter window count value
 */
#define IOMUXC0_PCR0_IOMUXCARRAY3_DFD(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PCR0_IOMUXCARRAY3_DFD_SHIFT)) & IOMUXC0_PCR0_IOMUXCARRAY3_DFD_MASK)
/*! @} */

/* The count of IOMUXC0_PCR0_IOMUXCARRAY3 */
#define IOMUXC0_PCR0_IOMUXCARRAY3_COUNT          (2U)

/*! @name PSMI0_IOMUXCARRAY0 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC0_PSMI0_IOMUXCARRAY0_SSS_MASK      (0xFU)
#define IOMUXC0_PSMI0_IOMUXCARRAY0_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY0_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY0_SSS_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY0_SSS_MASK)

#define IOMUXC0_PSMI0_IOMUXCARRAY0_INV_MASK      (0x8000U)
#define IOMUXC0_PSMI0_IOMUXCARRAY0_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY0_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY0_INV_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY0_INV_MASK)
/*! @} */

/* The count of IOMUXC0_PSMI0_IOMUXCARRAY0 */
#define IOMUXC0_PSMI0_IOMUXCARRAY0_COUNT         (5U)

/*! @name PSMI0_IOMUXCARRAY1 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC0_PSMI0_IOMUXCARRAY1_SSS_MASK      (0xFU)
#define IOMUXC0_PSMI0_IOMUXCARRAY1_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY1_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY1_SSS_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY1_SSS_MASK)

#define IOMUXC0_PSMI0_IOMUXCARRAY1_INV_MASK      (0x8000U)
#define IOMUXC0_PSMI0_IOMUXCARRAY1_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY1_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY1_INV_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY1_INV_MASK)
/*! @} */

/* The count of IOMUXC0_PSMI0_IOMUXCARRAY1 */
#define IOMUXC0_PSMI0_IOMUXCARRAY1_COUNT         (3U)

/*! @name PSMI0_IOMUXCARRAY2 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC0_PSMI0_IOMUXCARRAY2_SSS_MASK      (0xFU)
#define IOMUXC0_PSMI0_IOMUXCARRAY2_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY2_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY2_SSS_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY2_SSS_MASK)

#define IOMUXC0_PSMI0_IOMUXCARRAY2_INV_MASK      (0x8000U)
#define IOMUXC0_PSMI0_IOMUXCARRAY2_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY2_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY2_INV_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY2_INV_MASK)
/*! @} */

/* The count of IOMUXC0_PSMI0_IOMUXCARRAY2 */
#define IOMUXC0_PSMI0_IOMUXCARRAY2_COUNT         (4U)

/*! @name PSMI0_IOMUXCARRAY3 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC0_PSMI0_IOMUXCARRAY3_SSS_MASK      (0xFU)
#define IOMUXC0_PSMI0_IOMUXCARRAY3_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY3_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY3_SSS_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY3_SSS_MASK)

#define IOMUXC0_PSMI0_IOMUXCARRAY3_INV_MASK      (0x8000U)
#define IOMUXC0_PSMI0_IOMUXCARRAY3_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY3_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY3_INV_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY3_INV_MASK)
/*! @} */

/* The count of IOMUXC0_PSMI0_IOMUXCARRAY3 */
#define IOMUXC0_PSMI0_IOMUXCARRAY3_COUNT         (3U)

/*! @name PSMI0_IOMUXCARRAY4 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC0_PSMI0_IOMUXCARRAY4_SSS_MASK      (0xFU)
#define IOMUXC0_PSMI0_IOMUXCARRAY4_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY4_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY4_SSS_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY4_SSS_MASK)

#define IOMUXC0_PSMI0_IOMUXCARRAY4_INV_MASK      (0x8000U)
#define IOMUXC0_PSMI0_IOMUXCARRAY4_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY4_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY4_INV_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY4_INV_MASK)
/*! @} */

/* The count of IOMUXC0_PSMI0_IOMUXCARRAY4 */
#define IOMUXC0_PSMI0_IOMUXCARRAY4_COUNT         (1U)

/*! @name PSMI0_IOMUXCARRAY5 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC0_PSMI0_IOMUXCARRAY5_SSS_MASK      (0xFU)
#define IOMUXC0_PSMI0_IOMUXCARRAY5_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY5_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY5_SSS_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY5_SSS_MASK)

#define IOMUXC0_PSMI0_IOMUXCARRAY5_INV_MASK      (0x8000U)
#define IOMUXC0_PSMI0_IOMUXCARRAY5_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY5_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY5_INV_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY5_INV_MASK)
/*! @} */

/* The count of IOMUXC0_PSMI0_IOMUXCARRAY5 */
#define IOMUXC0_PSMI0_IOMUXCARRAY5_COUNT         (10U)

/*! @name PSMI0_IOMUXCARRAY6 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC0_PSMI0_IOMUXCARRAY6_SSS_MASK      (0xFU)
#define IOMUXC0_PSMI0_IOMUXCARRAY6_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY6_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY6_SSS_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY6_SSS_MASK)

#define IOMUXC0_PSMI0_IOMUXCARRAY6_INV_MASK      (0x8000U)
#define IOMUXC0_PSMI0_IOMUXCARRAY6_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY6_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY6_INV_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY6_INV_MASK)
/*! @} */

/* The count of IOMUXC0_PSMI0_IOMUXCARRAY6 */
#define IOMUXC0_PSMI0_IOMUXCARRAY6_COUNT         (3U)

/*! @name PSMI0_IOMUXCARRAY7 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC0_PSMI0_IOMUXCARRAY7_SSS_MASK      (0xFU)
#define IOMUXC0_PSMI0_IOMUXCARRAY7_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY7_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY7_SSS_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY7_SSS_MASK)

#define IOMUXC0_PSMI0_IOMUXCARRAY7_INV_MASK      (0x8000U)
#define IOMUXC0_PSMI0_IOMUXCARRAY7_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY7_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY7_INV_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY7_INV_MASK)
/*! @} */

/* The count of IOMUXC0_PSMI0_IOMUXCARRAY7 */
#define IOMUXC0_PSMI0_IOMUXCARRAY7_COUNT         (15U)

/*! @name PSMI0_IOMUXCARRAY8 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC0_PSMI0_IOMUXCARRAY8_SSS_MASK      (0xFU)
#define IOMUXC0_PSMI0_IOMUXCARRAY8_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY8_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY8_SSS_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY8_SSS_MASK)

#define IOMUXC0_PSMI0_IOMUXCARRAY8_INV_MASK      (0x8000U)
#define IOMUXC0_PSMI0_IOMUXCARRAY8_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY8_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY8_INV_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY8_INV_MASK)
/*! @} */

/* The count of IOMUXC0_PSMI0_IOMUXCARRAY8 */
#define IOMUXC0_PSMI0_IOMUXCARRAY8_COUNT         (15U)

/*! @name PSMI0_IOMUXCARRAY9 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC0_PSMI0_IOMUXCARRAY9_SSS_MASK      (0xFU)
#define IOMUXC0_PSMI0_IOMUXCARRAY9_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY9_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY9_SSS_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY9_SSS_MASK)

#define IOMUXC0_PSMI0_IOMUXCARRAY9_INV_MASK      (0x8000U)
#define IOMUXC0_PSMI0_IOMUXCARRAY9_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY9_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY9_INV_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY9_INV_MASK)
/*! @} */

/* The count of IOMUXC0_PSMI0_IOMUXCARRAY9 */
#define IOMUXC0_PSMI0_IOMUXCARRAY9_COUNT         (11U)

/*! @name PSMI0_IOMUXCARRAY10 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC0_PSMI0_IOMUXCARRAY10_SSS_MASK     (0xFU)
#define IOMUXC0_PSMI0_IOMUXCARRAY10_SSS_SHIFT    (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY10_SSS(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY10_SSS_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY10_SSS_MASK)

#define IOMUXC0_PSMI0_IOMUXCARRAY10_INV_MASK     (0x8000U)
#define IOMUXC0_PSMI0_IOMUXCARRAY10_INV_SHIFT    (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY10_INV(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY10_INV_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY10_INV_MASK)
/*! @} */

/* The count of IOMUXC0_PSMI0_IOMUXCARRAY10 */
#define IOMUXC0_PSMI0_IOMUXCARRAY10_COUNT        (24U)

/*! @name PSMI0_IOMUXCARRAY11 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC0_PSMI0_IOMUXCARRAY11_SSS_MASK     (0xFU)
#define IOMUXC0_PSMI0_IOMUXCARRAY11_SSS_SHIFT    (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY11_SSS(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY11_SSS_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY11_SSS_MASK)

#define IOMUXC0_PSMI0_IOMUXCARRAY11_INV_MASK     (0x8000U)
#define IOMUXC0_PSMI0_IOMUXCARRAY11_INV_SHIFT    (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC0_PSMI0_IOMUXCARRAY11_INV(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC0_PSMI0_IOMUXCARRAY11_INV_SHIFT)) & IOMUXC0_PSMI0_IOMUXCARRAY11_INV_MASK)
/*! @} */

/* The count of IOMUXC0_PSMI0_IOMUXCARRAY11 */
#define IOMUXC0_PSMI0_IOMUXCARRAY11_COUNT        (6U)


/*!
 * @}
 */ /* end of group IOMUXC0_Register_Masks */


/* IOMUXC0 - Peripheral instance base addresses */
/** Peripheral IOMUXC0 base address */
#define IOMUXC0_BASE                             (0x280A1000u)
/** Peripheral IOMUXC0 base pointer */
#define IOMUXC0                                  ((IOMUXC0_Type *)IOMUXC0_BASE)
/** Array initializer of IOMUXC0 peripheral base addresses */
#define IOMUXC0_BASE_ADDRS                       { IOMUXC0_BASE }
/** Array initializer of IOMUXC0 peripheral base pointers */
#define IOMUXC0_BASE_PTRS                        { IOMUXC0 }

/*!
 * @}
 */ /* end of group IOMUXC0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IOMUXC1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOMUXC1_Peripheral_Access_Layer IOMUXC1 Peripheral Access Layer
 * @{
 */

/** IOMUXC1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t PCR1_IOMUXCARRAY0[24];             /**< Pad Control Register, array offset: 0x0, array step: 0x4 */
       uint8_t RESERVED_0[32];
  __IO uint32_t PCR1_IOMUXCARRAY1[24];             /**< Pad Control Register, array offset: 0x80, array step: 0x4 */
       uint8_t RESERVED_1[32];
  __IO uint32_t PCR1_IOMUXCARRAY2[32];             /**< Pad Control Register, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_2[1664];
  __IO uint32_t PSMI1_IOMUXCARRAY0[10];            /**< Module Input Source Selection Register, array offset: 0x800, array step: 0x4 */
       uint8_t RESERVED_3[16];
  __IO uint32_t PSMI1_IOMUXCARRAY1[61];            /**< Module Input Source Selection Register, array offset: 0x838, array step: 0x4 */
       uint8_t RESERVED_4[40];
  __IO uint32_t PSMI1_IOMUXCARRAY2[12];            /**< Module Input Source Selection Register, array offset: 0x954, array step: 0x4 */
       uint8_t RESERVED_5[16];
  __IO uint32_t PSMI1_IOMUXCARRAY3[20];            /**< Module Input Source Selection Register, array offset: 0x994, array step: 0x4 */
       uint8_t RESERVED_6[116];
  __IO uint32_t PSMI1_IOMUXCARRAY4[75];            /**< Module Input Source Selection Register, array offset: 0xA58, array step: 0x4 */
} IOMUXC1_Type;

/* ----------------------------------------------------------------------------
   -- IOMUXC1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOMUXC1_Register_Masks IOMUXC1 Register Masks
 * @{
 */

/*! @name PCR1_IOMUXCARRAY0 - Pad Control Register */
/*! @{ */

#define IOMUXC1_PCR1_IOMUXCARRAY0_PS_MASK        (0x1U)
#define IOMUXC1_PCR1_IOMUXCARRAY0_PS_SHIFT       (0U)
/*! PS - Pull Select
 *  0b0..Pull-down selected
 *  0b1..Pull-up selected
 */
#define IOMUXC1_PCR1_IOMUXCARRAY0_PS(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY0_PS_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY0_PS_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY0_PE_MASK        (0x2U)
#define IOMUXC1_PCR1_IOMUXCARRAY0_PE_SHIFT       (1U)
/*! PE - Pull-up Enable
 *  0b0..pull disabled
 *  0b1..pull enabled
 */
#define IOMUXC1_PCR1_IOMUXCARRAY0_PE(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY0_PE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY0_PE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY0_SRE_MASK       (0x4U)
#define IOMUXC1_PCR1_IOMUXCARRAY0_SRE_SHIFT      (2U)
/*! SRE - Slew Rate Enable
 *  0b0..Standard Slew Rate
 *  0b1..Slow Slew Rate
 */
#define IOMUXC1_PCR1_IOMUXCARRAY0_SRE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY0_SRE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY0_SRE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY0_ODE_MASK       (0x20U)
#define IOMUXC1_PCR1_IOMUXCARRAY0_ODE_SHIFT      (5U)
/*! ODE - Open-drain Enable
 *  0b0..Push-pull Output
 *  0b1..Open-drain Output
 */
#define IOMUXC1_PCR1_IOMUXCARRAY0_ODE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY0_ODE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY0_ODE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY0_DSE_MASK       (0x40U)
#define IOMUXC1_PCR1_IOMUXCARRAY0_DSE_SHIFT      (6U)
/*! DSE - Drive Strength Enable
 *  0b0..Standard Drive Strength
 *  0b1..Hi Drive Strength
 */
#define IOMUXC1_PCR1_IOMUXCARRAY0_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY0_DSE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY0_DSE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY0_MUX_MASK       (0xF00U)
#define IOMUXC1_PCR1_IOMUXCARRAY0_MUX_SHIFT      (8U)
/*! MUX - PAD Mux Selector
 *  0b0000..Alternate function 0 ; Analog / Hiz
 *  0b0001..Refer to "IO Signal Table" for availabre functions and SS values for each PAD.
 */
#define IOMUXC1_PCR1_IOMUXCARRAY0_MUX(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY0_MUX_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY0_MUX_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY0_LK_MASK        (0x8000U)
#define IOMUXC1_PCR1_IOMUXCARRAY0_LK_SHIFT       (15U)
/*! LK - Lock
 *  0b0..Register Unlocked
 *  0b1..Register Locked for write
 */
#define IOMUXC1_PCR1_IOMUXCARRAY0_LK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY0_LK_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY0_LK_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY0_IBE_MASK       (0x10000U)
#define IOMUXC1_PCR1_IOMUXCARRAY0_IBE_SHIFT      (16U)
/*! IBE - Input Buffer Enable
 *  0b0..Input Buffer enable depends on selected function
 *  0b1..Input buffer forced enabled
 */
#define IOMUXC1_PCR1_IOMUXCARRAY0_IBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY0_IBE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY0_IBE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY0_OBE_MASK       (0x20000U)
#define IOMUXC1_PCR1_IOMUXCARRAY0_OBE_SHIFT      (17U)
/*! OBE - Output Buffer Enable
 *  0b0..Output Buffer enable depends on selected function
 *  0b1..Output buffer forced enabled
 */
#define IOMUXC1_PCR1_IOMUXCARRAY0_OBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY0_OBE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY0_OBE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY0_DFE_MASK       (0x100000U)
#define IOMUXC1_PCR1_IOMUXCARRAY0_DFE_SHIFT      (20U)
/*! DFE - Digital Filter Enable
 *  0b0..Digital filter disabled
 *  0b1..Digital filter enabled
 */
#define IOMUXC1_PCR1_IOMUXCARRAY0_DFE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY0_DFE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY0_DFE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY0_DFCS_MASK      (0x200000U)
#define IOMUXC1_PCR1_IOMUXCARRAY0_DFCS_SHIFT     (21U)
/*! DFCS - Digital Filter Clock Select
 *  0b0..Digital filter is running out of PCTL* Bus clock
 *  0b1..Digital filter is running out RTC 1kHz clock
 */
#define IOMUXC1_PCR1_IOMUXCARRAY0_DFCS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY0_DFCS_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY0_DFCS_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY0_DFD_MASK       (0x7C00000U)
#define IOMUXC1_PCR1_IOMUXCARRAY0_DFD_SHIFT      (22U)
/*! DFD - Digital Filter Duration
 *  0b00000..Digital filter is disabled
 *  0b00001..Filter window count value
 */
#define IOMUXC1_PCR1_IOMUXCARRAY0_DFD(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY0_DFD_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY0_DFD_MASK)
/*! @} */

/* The count of IOMUXC1_PCR1_IOMUXCARRAY0 */
#define IOMUXC1_PCR1_IOMUXCARRAY0_COUNT          (24U)

/*! @name PCR1_IOMUXCARRAY1 - Pad Control Register */
/*! @{ */

#define IOMUXC1_PCR1_IOMUXCARRAY1_PS_MASK        (0x1U)
#define IOMUXC1_PCR1_IOMUXCARRAY1_PS_SHIFT       (0U)
/*! PS - Pull Select
 *  0b0..Pull-down selected
 *  0b1..Pull-up selected
 */
#define IOMUXC1_PCR1_IOMUXCARRAY1_PS(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY1_PS_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY1_PS_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY1_PE_MASK        (0x2U)
#define IOMUXC1_PCR1_IOMUXCARRAY1_PE_SHIFT       (1U)
/*! PE - Pull-up Enable
 *  0b0..pull disabled
 *  0b1..pull enabled
 */
#define IOMUXC1_PCR1_IOMUXCARRAY1_PE(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY1_PE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY1_PE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY1_SRE_MASK       (0x4U)
#define IOMUXC1_PCR1_IOMUXCARRAY1_SRE_SHIFT      (2U)
/*! SRE - Slew Rate Enable
 *  0b0..Standard Slew Rate
 *  0b1..Slow Slew Rate
 */
#define IOMUXC1_PCR1_IOMUXCARRAY1_SRE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY1_SRE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY1_SRE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY1_ODE_MASK       (0x20U)
#define IOMUXC1_PCR1_IOMUXCARRAY1_ODE_SHIFT      (5U)
/*! ODE - Open-drain Enable
 *  0b0..Push-pull Output
 *  0b1..Open-drain Output
 */
#define IOMUXC1_PCR1_IOMUXCARRAY1_ODE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY1_ODE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY1_ODE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY1_DSE_MASK       (0x40U)
#define IOMUXC1_PCR1_IOMUXCARRAY1_DSE_SHIFT      (6U)
/*! DSE - Drive Strength Enable
 *  0b0..Standard Drive Strength
 *  0b1..Hi Drive Strength
 */
#define IOMUXC1_PCR1_IOMUXCARRAY1_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY1_DSE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY1_DSE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY1_MUX_MASK       (0xF00U)
#define IOMUXC1_PCR1_IOMUXCARRAY1_MUX_SHIFT      (8U)
/*! MUX - PAD Mux Selector
 *  0b0000..Alternate function 0 ; Analog / Hiz
 *  0b0001..Refer to "IO Signal Table" for availabre functions and SS values for each PAD.
 */
#define IOMUXC1_PCR1_IOMUXCARRAY1_MUX(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY1_MUX_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY1_MUX_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY1_LK_MASK        (0x8000U)
#define IOMUXC1_PCR1_IOMUXCARRAY1_LK_SHIFT       (15U)
/*! LK - Lock
 *  0b0..Register Unlocked
 *  0b1..Register Locked for write
 */
#define IOMUXC1_PCR1_IOMUXCARRAY1_LK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY1_LK_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY1_LK_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY1_IBE_MASK       (0x10000U)
#define IOMUXC1_PCR1_IOMUXCARRAY1_IBE_SHIFT      (16U)
/*! IBE - Input Buffer Enable
 *  0b0..Input Buffer enable depends on selected function
 *  0b1..Input buffer forced enabled
 */
#define IOMUXC1_PCR1_IOMUXCARRAY1_IBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY1_IBE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY1_IBE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY1_OBE_MASK       (0x20000U)
#define IOMUXC1_PCR1_IOMUXCARRAY1_OBE_SHIFT      (17U)
/*! OBE - Output Buffer Enable
 *  0b0..Output Buffer enable depends on selected function
 *  0b1..Output buffer forced enabled
 */
#define IOMUXC1_PCR1_IOMUXCARRAY1_OBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY1_OBE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY1_OBE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY1_DFE_MASK       (0x100000U)
#define IOMUXC1_PCR1_IOMUXCARRAY1_DFE_SHIFT      (20U)
/*! DFE - Digital Filter Enable
 *  0b0..Digital filter disabled
 *  0b1..Digital filter enabled
 */
#define IOMUXC1_PCR1_IOMUXCARRAY1_DFE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY1_DFE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY1_DFE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY1_DFCS_MASK      (0x200000U)
#define IOMUXC1_PCR1_IOMUXCARRAY1_DFCS_SHIFT     (21U)
/*! DFCS - Digital Filter Clock Select
 *  0b0..Digital filter is running out of PCTL* Bus clock
 *  0b1..Digital filter is running out RTC 1kHz clock
 */
#define IOMUXC1_PCR1_IOMUXCARRAY1_DFCS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY1_DFCS_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY1_DFCS_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY1_DFD_MASK       (0x7C00000U)
#define IOMUXC1_PCR1_IOMUXCARRAY1_DFD_SHIFT      (22U)
/*! DFD - Digital Filter Duration
 *  0b00000..Digital filter is disabled
 *  0b00001..Filter window count value
 */
#define IOMUXC1_PCR1_IOMUXCARRAY1_DFD(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY1_DFD_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY1_DFD_MASK)
/*! @} */

/* The count of IOMUXC1_PCR1_IOMUXCARRAY1 */
#define IOMUXC1_PCR1_IOMUXCARRAY1_COUNT          (24U)

/*! @name PCR1_IOMUXCARRAY2 - Pad Control Register */
/*! @{ */

#define IOMUXC1_PCR1_IOMUXCARRAY2_PS_MASK        (0x1U)
#define IOMUXC1_PCR1_IOMUXCARRAY2_PS_SHIFT       (0U)
/*! PS - Pull Select
 *  0b0..Pull-down selected
 *  0b1..Pull-up selected
 */
#define IOMUXC1_PCR1_IOMUXCARRAY2_PS(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY2_PS_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY2_PS_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY2_PE_MASK        (0x2U)
#define IOMUXC1_PCR1_IOMUXCARRAY2_PE_SHIFT       (1U)
/*! PE - Pull-up Enable
 *  0b0..pull disabled
 *  0b1..pull enabled
 */
#define IOMUXC1_PCR1_IOMUXCARRAY2_PE(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY2_PE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY2_PE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY2_SRE_MASK       (0x4U)
#define IOMUXC1_PCR1_IOMUXCARRAY2_SRE_SHIFT      (2U)
/*! SRE - Slew Rate Enable
 *  0b0..Standard Slew Rate
 *  0b1..Slow Slew Rate
 */
#define IOMUXC1_PCR1_IOMUXCARRAY2_SRE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY2_SRE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY2_SRE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY2_ODE_MASK       (0x20U)
#define IOMUXC1_PCR1_IOMUXCARRAY2_ODE_SHIFT      (5U)
/*! ODE - Open-drain Enable
 *  0b0..Push-pull Output
 *  0b1..Open-drain Output
 */
#define IOMUXC1_PCR1_IOMUXCARRAY2_ODE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY2_ODE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY2_ODE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY2_DSE_MASK       (0x40U)
#define IOMUXC1_PCR1_IOMUXCARRAY2_DSE_SHIFT      (6U)
/*! DSE - Drive Strength Enable
 *  0b0..Standard Drive Strength
 *  0b1..Hi Drive Strength
 */
#define IOMUXC1_PCR1_IOMUXCARRAY2_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY2_DSE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY2_DSE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY2_MUX_MASK       (0xF00U)
#define IOMUXC1_PCR1_IOMUXCARRAY2_MUX_SHIFT      (8U)
/*! MUX - PAD Mux Selector
 *  0b0000..Alternate function 0 ; Analog / Hiz
 *  0b0001..Refer to "IO Signal Table" for availabre functions and SS values for each PAD.
 */
#define IOMUXC1_PCR1_IOMUXCARRAY2_MUX(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY2_MUX_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY2_MUX_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY2_LK_MASK        (0x8000U)
#define IOMUXC1_PCR1_IOMUXCARRAY2_LK_SHIFT       (15U)
/*! LK - Lock
 *  0b0..Register Unlocked
 *  0b1..Register Locked for write
 */
#define IOMUXC1_PCR1_IOMUXCARRAY2_LK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY2_LK_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY2_LK_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY2_IBE_MASK       (0x10000U)
#define IOMUXC1_PCR1_IOMUXCARRAY2_IBE_SHIFT      (16U)
/*! IBE - Input Buffer Enable
 *  0b0..Input Buffer enable depends on selected function
 *  0b1..Input buffer forced enabled
 */
#define IOMUXC1_PCR1_IOMUXCARRAY2_IBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY2_IBE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY2_IBE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY2_OBE_MASK       (0x20000U)
#define IOMUXC1_PCR1_IOMUXCARRAY2_OBE_SHIFT      (17U)
/*! OBE - Output Buffer Enable
 *  0b0..Output Buffer enable depends on selected function
 *  0b1..Output buffer forced enabled
 */
#define IOMUXC1_PCR1_IOMUXCARRAY2_OBE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY2_OBE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY2_OBE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY2_DFE_MASK       (0x100000U)
#define IOMUXC1_PCR1_IOMUXCARRAY2_DFE_SHIFT      (20U)
/*! DFE - Digital Filter Enable
 *  0b0..Digital filter disabled
 *  0b1..Digital filter enabled
 */
#define IOMUXC1_PCR1_IOMUXCARRAY2_DFE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY2_DFE_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY2_DFE_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY2_DFCS_MASK      (0x200000U)
#define IOMUXC1_PCR1_IOMUXCARRAY2_DFCS_SHIFT     (21U)
/*! DFCS - Digital Filter Clock Select
 *  0b0..Digital filter is running out of PCTL* Bus clock
 *  0b1..Digital filter is running out RTC 1kHz clock
 */
#define IOMUXC1_PCR1_IOMUXCARRAY2_DFCS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY2_DFCS_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY2_DFCS_MASK)

#define IOMUXC1_PCR1_IOMUXCARRAY2_DFD_MASK       (0x7C00000U)
#define IOMUXC1_PCR1_IOMUXCARRAY2_DFD_SHIFT      (22U)
/*! DFD - Digital Filter Duration
 *  0b00000..Digital filter is disabled
 *  0b00001..Filter window count value
 */
#define IOMUXC1_PCR1_IOMUXCARRAY2_DFD(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PCR1_IOMUXCARRAY2_DFD_SHIFT)) & IOMUXC1_PCR1_IOMUXCARRAY2_DFD_MASK)
/*! @} */

/* The count of IOMUXC1_PCR1_IOMUXCARRAY2 */
#define IOMUXC1_PCR1_IOMUXCARRAY2_COUNT          (32U)

/*! @name PSMI1_IOMUXCARRAY0 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC1_PSMI1_IOMUXCARRAY0_SSS_MASK      (0xFU)
#define IOMUXC1_PSMI1_IOMUXCARRAY0_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC1_PSMI1_IOMUXCARRAY0_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PSMI1_IOMUXCARRAY0_SSS_SHIFT)) & IOMUXC1_PSMI1_IOMUXCARRAY0_SSS_MASK)

#define IOMUXC1_PSMI1_IOMUXCARRAY0_INV_MASK      (0x8000U)
#define IOMUXC1_PSMI1_IOMUXCARRAY0_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC1_PSMI1_IOMUXCARRAY0_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PSMI1_IOMUXCARRAY0_INV_SHIFT)) & IOMUXC1_PSMI1_IOMUXCARRAY0_INV_MASK)
/*! @} */

/* The count of IOMUXC1_PSMI1_IOMUXCARRAY0 */
#define IOMUXC1_PSMI1_IOMUXCARRAY0_COUNT         (10U)

/*! @name PSMI1_IOMUXCARRAY1 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC1_PSMI1_IOMUXCARRAY1_SSS_MASK      (0xFU)
#define IOMUXC1_PSMI1_IOMUXCARRAY1_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC1_PSMI1_IOMUXCARRAY1_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PSMI1_IOMUXCARRAY1_SSS_SHIFT)) & IOMUXC1_PSMI1_IOMUXCARRAY1_SSS_MASK)

#define IOMUXC1_PSMI1_IOMUXCARRAY1_INV_MASK      (0x8000U)
#define IOMUXC1_PSMI1_IOMUXCARRAY1_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC1_PSMI1_IOMUXCARRAY1_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PSMI1_IOMUXCARRAY1_INV_SHIFT)) & IOMUXC1_PSMI1_IOMUXCARRAY1_INV_MASK)
/*! @} */

/* The count of IOMUXC1_PSMI1_IOMUXCARRAY1 */
#define IOMUXC1_PSMI1_IOMUXCARRAY1_COUNT         (61U)

/*! @name PSMI1_IOMUXCARRAY2 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC1_PSMI1_IOMUXCARRAY2_SSS_MASK      (0xFU)
#define IOMUXC1_PSMI1_IOMUXCARRAY2_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC1_PSMI1_IOMUXCARRAY2_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PSMI1_IOMUXCARRAY2_SSS_SHIFT)) & IOMUXC1_PSMI1_IOMUXCARRAY2_SSS_MASK)

#define IOMUXC1_PSMI1_IOMUXCARRAY2_INV_MASK      (0x8000U)
#define IOMUXC1_PSMI1_IOMUXCARRAY2_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC1_PSMI1_IOMUXCARRAY2_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PSMI1_IOMUXCARRAY2_INV_SHIFT)) & IOMUXC1_PSMI1_IOMUXCARRAY2_INV_MASK)
/*! @} */

/* The count of IOMUXC1_PSMI1_IOMUXCARRAY2 */
#define IOMUXC1_PSMI1_IOMUXCARRAY2_COUNT         (12U)

/*! @name PSMI1_IOMUXCARRAY3 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC1_PSMI1_IOMUXCARRAY3_SSS_MASK      (0xFU)
#define IOMUXC1_PSMI1_IOMUXCARRAY3_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC1_PSMI1_IOMUXCARRAY3_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PSMI1_IOMUXCARRAY3_SSS_SHIFT)) & IOMUXC1_PSMI1_IOMUXCARRAY3_SSS_MASK)

#define IOMUXC1_PSMI1_IOMUXCARRAY3_INV_MASK      (0x8000U)
#define IOMUXC1_PSMI1_IOMUXCARRAY3_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC1_PSMI1_IOMUXCARRAY3_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PSMI1_IOMUXCARRAY3_INV_SHIFT)) & IOMUXC1_PSMI1_IOMUXCARRAY3_INV_MASK)
/*! @} */

/* The count of IOMUXC1_PSMI1_IOMUXCARRAY3 */
#define IOMUXC1_PSMI1_IOMUXCARRAY3_COUNT         (20U)

/*! @name PSMI1_IOMUXCARRAY4 - Module Input Source Selection Register */
/*! @{ */

#define IOMUXC1_PSMI1_IOMUXCARRAY4_SSS_MASK      (0xFU)
#define IOMUXC1_PSMI1_IOMUXCARRAY4_SSS_SHIFT     (0U)
/*! SSS - Source Selection
 *  0b0000..No input Pad is selected. Module input is in safe state
 *  0b0001..Defines Pad source
 */
#define IOMUXC1_PSMI1_IOMUXCARRAY4_SSS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PSMI1_IOMUXCARRAY4_SSS_SHIFT)) & IOMUXC1_PSMI1_IOMUXCARRAY4_SSS_MASK)

#define IOMUXC1_PSMI1_IOMUXCARRAY4_INV_MASK      (0x8000U)
#define IOMUXC1_PSMI1_IOMUXCARRAY4_INV_SHIFT     (15U)
/*! INV - Input path inversion
 *  0b0..Do not inverts signal polarity
 *  0b1..Inverts signal polarity
 */
#define IOMUXC1_PSMI1_IOMUXCARRAY4_INV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC1_PSMI1_IOMUXCARRAY4_INV_SHIFT)) & IOMUXC1_PSMI1_IOMUXCARRAY4_INV_MASK)
/*! @} */

/* The count of IOMUXC1_PSMI1_IOMUXCARRAY4 */
#define IOMUXC1_PSMI1_IOMUXCARRAY4_COUNT         (75U)


/*!
 * @}
 */ /* end of group IOMUXC1_Register_Masks */


/* IOMUXC1 - Peripheral instance base addresses */
/** Peripheral IOMUXC1 base address */
#define IOMUXC1_BASE                             (0x298C0000u)
/** Peripheral IOMUXC1 base pointer */
#define IOMUXC1                                  ((IOMUXC1_Type *)IOMUXC1_BASE)
/** Array initializer of IOMUXC1 peripheral base addresses */
#define IOMUXC1_BASE_ADDRS                       { IOMUXC1_BASE }
/** Array initializer of IOMUXC1 peripheral base pointers */
#define IOMUXC1_BASE_PTRS                        { IOMUXC1 }

/*!
 * @}
 */ /* end of group IOMUXC1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ISI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ISI_Peripheral_Access_Layer ISI Peripheral Access Layer
 * @{
 */

/** ISI - Register Layout Typedef */
typedef struct {
  __IO uint32_t CHNL_CTRL;                         /**< Channel Control Register, offset: 0x0 */
  __IO uint32_t CHNL_IMG_CTRL;                     /**< Channel Image Control Register, offset: 0x4 */
  __IO uint32_t CHNL_OUT_BUF_CTRL;                 /**< Channel Output Buffer Control Register, offset: 0x8 */
  __IO uint32_t CHNL_IMG_CFG;                      /**< Channel Image Configuration, offset: 0xC */
  __IO uint32_t CHNL_IER;                          /**< Channel Interrupt Enable Register, offset: 0x10 */
  __IO uint32_t CHNL_STS;                          /**< Channel Status Register, offset: 0x14 */
  __IO uint32_t CHNL_SCALE_FACTOR;                 /**< Channel Scale Factor Register, offset: 0x18 */
  __IO uint32_t CHNL_SCALE_OFFSET;                 /**< Channel Scale Offset Register, offset: 0x1C */
  __IO uint32_t CHNL_CROP_ULC;                     /**< Channel Crop Upper Left Corner Coordinate Register, offset: 0x20 */
  __IO uint32_t CHNL_CROP_LRC;                     /**< Channel Crop Lower Right Corner Coordinate Register, offset: 0x24 */
  __IO uint32_t CHNL_CSC_COEFF0;                   /**< Channel Color Space Conversion Coefficient Register 0, offset: 0x28 */
  __IO uint32_t CHNL_CSC_COEFF1;                   /**< Channel Color Space Conversion Coefficient Register 1, offset: 0x2C */
  __IO uint32_t CHNL_CSC_COEFF2;                   /**< Channel Color Space Conversion Coefficient Register 2, offset: 0x30 */
  __IO uint32_t CHNL_CSC_COEFF3;                   /**< Channel Color Space Conversion Coefficient Register 3, offset: 0x34 */
  __IO uint32_t CHNL_CSC_COEFF4;                   /**< Channel Color Space Conversion Coefficient Register 4, offset: 0x38 */
  __IO uint32_t CHNL_CSC_COEFF5;                   /**< Channel Color Space Conversion Coefficient Register 5, offset: 0x3C */
  struct {                                         /* offset: 0x40, array step: 0xC */
    __IO uint32_t CHNL_ROI_ALPHA;                    /**< Channel Alpha Value Register for Region of Interest 0..Channel Alpha Value Register for Region of Interest 3, array offset: 0x40, array step: 0xC */
    __IO uint32_t CHNL_ROI_ULC;                      /**< Channel Upper Left Coordinate Register for Region of Interest 0..Channel Upper Left Coordinate Register for Region of Interest 3, array offset: 0x44, array step: 0xC */
    __IO uint32_t CHNL_ROI_LRC;                      /**< Channel Lower Right Coordinate Register for Region of Interest 0..Channel Lower Right Coordinate Register for Region of Interest 3, array offset: 0x48, array step: 0xC */
  } ROI[4];
  __IO uint32_t CHNL_OUT_BUF1_ADDR_Y;              /**< Channel RGB or Luma (Y) Output Buffer 1 Address, offset: 0x70 */
  __IO uint32_t CHNL_OUT_BUF1_ADDR_U;              /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address, offset: 0x74 */
  __IO uint32_t CHNL_OUT_BUF1_ADDR_V;              /**< Channel Chroma (V/Cr) Output Buffer 1 Address, offset: 0x78 */
  __IO uint32_t CHNL_OUT_BUF_PITCH;                /**< Channel Output Buffer Pitch, offset: 0x7C */
  __IO uint32_t CHNL_IN_BUF_ADDR;                  /**< Channel Input Buffer Address, offset: 0x80 */
  __IO uint32_t CHNL_IN_BUF_PITCH;                 /**< Channel Input Buffer Pitch, offset: 0x84 */
  __IO uint32_t CHNL_MEM_RD_CTRL;                  /**< Channel Memory Read Control, offset: 0x88 */
  __IO uint32_t CHNL_OUT_BUF2_ADDR_Y;              /**< Channel RGB or Luma (Y) Output Buffer 2 Address, offset: 0x8C */
  __IO uint32_t CHNL_OUT_BUF2_ADDR_U;              /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address, offset: 0x90 */
  __IO uint32_t CHNL_OUT_BUF2_ADDR_V;              /**< Channel Chroma (V/Cr) Output Buffer 2 Address, offset: 0x94 */
  __IO uint32_t CHNL_SCL_IMG_CFG;                  /**< Channel Scaled Image Configuration, offset: 0x98 */
  __IO uint32_t CHNL_FLOW_CTRL;                    /**< Channel Flow Control Register, offset: 0x9C */
} ISI_Type;

/* ----------------------------------------------------------------------------
   -- ISI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ISI_Register_Masks ISI Register Masks
 * @{
 */

/*! @name CHNL_CTRL - Channel Control Register */
/*! @{ */

#define ISI_CHNL_CTRL_SRC_MASK                   (0x1U)
#define ISI_CHNL_CTRL_SRC_SHIFT                  (0U)
/*! SRC - Input image source port selection
 *  0b0..Image will be sourced from input port 0 of the Pixel Link Crossbar
 *  0b1..Image will be sourced from input port 1 of the Pixel Link Crossbar
 */
#define ISI_CHNL_CTRL_SRC(x)                     (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_SHIFT)) & ISI_CHNL_CTRL_SRC_MASK)

#define ISI_CHNL_CTRL_SRC_TYPE_MASK              (0x10U)
#define ISI_CHNL_CTRL_SRC_TYPE_SHIFT             (4U)
/*! SRC_TYPE - Type of selected input image source
 *  0b0..Image input source is Pixel Link
 *  0b1..Image input source is Memory
 */
#define ISI_CHNL_CTRL_SRC_TYPE(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_TYPE_SHIFT)) & ISI_CHNL_CTRL_SRC_TYPE_MASK)

#define ISI_CHNL_CTRL_VC_ID_MASK                 (0xC0U)
#define ISI_CHNL_CTRL_VC_ID_SHIFT                (6U)
/*! VC_ID - Virtual channel ID
 *  0b00..Virtual Channel 0 selected or no virtual channel used
 *  0b01..Virtual Channel 1 selected
 *  0b10..Virtual Channel 2 selected
 *  0b11..Virtual Channel 3 selected
 */
#define ISI_CHNL_CTRL_VC_ID(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_VC_ID_SHIFT)) & ISI_CHNL_CTRL_VC_ID_MASK)

#define ISI_CHNL_CTRL_SEC_LB_SRC_MASK            (0x700U)
#define ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT           (8U)
/*! SEC_LB_SRC - Secondary line buffer source */
#define ISI_CHNL_CTRL_SEC_LB_SRC(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT)) & ISI_CHNL_CTRL_SEC_LB_SRC_MASK)

#define ISI_CHNL_CTRL_VER_ID_MASK                (0x3C0000U)
#define ISI_CHNL_CTRL_VER_ID_SHIFT               (18U)
/*! VER_ID - Version ID for the IP */
#define ISI_CHNL_CTRL_VER_ID(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_VER_ID_SHIFT)) & ISI_CHNL_CTRL_VER_ID_MASK)

#define ISI_CHNL_CTRL_SW_RST_MASK                (0x1000000U)
#define ISI_CHNL_CTRL_SW_RST_SHIFT               (24U)
/*! SW_RST - Software reset bit
 *  0b0..No Reset
 *  0b1..Channel pipeline is under software reset
 */
#define ISI_CHNL_CTRL_SW_RST(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SW_RST_SHIFT)) & ISI_CHNL_CTRL_SW_RST_MASK)

#define ISI_CHNL_CTRL_CHAIN_BUF_MASK             (0x6000000U)
#define ISI_CHNL_CTRL_CHAIN_BUF_SHIFT            (25U)
/*! CHAIN_BUF - Chain line buffer control
 *  0b00..No line buffers chained (supports 2048 or less horizontal resolution)
 *  0b01..2 line buffers chained (supports 4096 horizontal resolution). Line buffers of channels 'n' and 'n+1' are chained.
 *  0b10..Reserved for future use
 *  0b11..Reserved for future use
 */
#define ISI_CHNL_CTRL_CHAIN_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHAIN_BUF_SHIFT)) & ISI_CHNL_CTRL_CHAIN_BUF_MASK)

#define ISI_CHNL_CTRL_CHNL_BYPASS_MASK           (0x20000000U)
#define ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT          (29U)
/*! CHNL_BYPASS - Channel bypass enable
 *  0b0..Channel is not bypassed
 *  0b1..Channel is bypassed
 */
#define ISI_CHNL_CTRL_CHNL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT)) & ISI_CHNL_CTRL_CHNL_BYPASS_MASK)

#define ISI_CHNL_CTRL_CLK_EN_MASK                (0x40000000U)
#define ISI_CHNL_CTRL_CLK_EN_SHIFT               (30U)
/*! CLK_EN - Channel clock enable
 *  0b0..Channel processing clock is disabled
 *  0b1..Channel processing clock is enabled
 */
#define ISI_CHNL_CTRL_CLK_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CLK_EN_SHIFT)) & ISI_CHNL_CTRL_CLK_EN_MASK)

#define ISI_CHNL_CTRL_CHNL_EN_MASK               (0x80000000U)
#define ISI_CHNL_CTRL_CHNL_EN_SHIFT              (31U)
/*! CHNL_EN - Enable channel processing
 *  0b0..Processing channel is disabled
 *  0b1..Processing channel is enabled
 */
#define ISI_CHNL_CTRL_CHNL_EN(x)                 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_EN_SHIFT)) & ISI_CHNL_CTRL_CHNL_EN_MASK)
/*! @} */

/*! @name CHNL_IMG_CTRL - Channel Image Control Register */
/*! @{ */

#define ISI_CHNL_IMG_CTRL_CSC_BYP_MASK           (0x1U)
#define ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT          (0U)
/*! CSC_BYP - Color Space Conversion bypass control
 *  0b0..CSC is operational
 *  0b1..CSC is bypassed
 */
#define ISI_CHNL_IMG_CTRL_CSC_BYP(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_BYP_MASK)

#define ISI_CHNL_IMG_CTRL_CSC_MODE_MASK          (0x6U)
#define ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT         (1U)
/*! CSC_MODE - Color Space Conversion operating mode
 *  0b00..Convert from YUV to RGB
 *  0b01..Convert from YCbCr to RGB
 *  0b10..Convert from RGB to YUV
 *  0b11..Convert from RGB to YCbCr
 */
#define ISI_CHNL_IMG_CTRL_CSC_MODE(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_MODE_MASK)

#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK        (0x8U)
#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT       (3U)
/*! YCBCR_MODE - YCbCr Mode
 *  0b0..YCbCr mode is disabled
 *  0b1..YCbCr mode is enabled
 */
#define ISI_CHNL_IMG_CTRL_YCBCR_MODE(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK)

#define ISI_CHNL_IMG_CTRL_RSVD2_MASK             (0x10U)
#define ISI_CHNL_IMG_CTRL_RSVD2_SHIFT            (4U)
/*! RSVD2 - Reserved field. Reads only zeros */
#define ISI_CHNL_IMG_CTRL_RSVD2(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_RSVD2_SHIFT)) & ISI_CHNL_IMG_CTRL_RSVD2_MASK)

#define ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK          (0x20U)
#define ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT         (5U)
/*! HFLIP_EN - Horizontal flip control
 *  0b0..Horizantal image flip disabled
 *  0b1..Horizontal image flip enabled
 */
#define ISI_CHNL_IMG_CTRL_HFLIP_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK)

#define ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK          (0x40U)
#define ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT         (6U)
/*! VFLIP_EN - Veritical flip control
 *  0b0..Vertical image flip disabled
 *  0b1..Vertical image flip enabled
 */
#define ISI_CHNL_IMG_CTRL_VFLIP_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK)

#define ISI_CHNL_IMG_CTRL_CROP_EN_MASK           (0x80U)
#define ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT          (7U)
/*! CROP_EN - Output image cropping enable
 *  0b0..Image cropping is disabled
 *  0b1..Image cropping is enabled
 */
#define ISI_CHNL_IMG_CTRL_CROP_EN(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_CROP_EN_MASK)

#define ISI_CHNL_IMG_CTRL_DEC_Y_MASK             (0x300U)
#define ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT            (8U)
/*! DEC_Y - Vertical pre-decimation control
 *  0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational.
 *  0b01..Decimate by 2
 *  0b10..Decimate by 4
 *  0b11..Decimate by 8
 */
#define ISI_CHNL_IMG_CTRL_DEC_Y(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_Y_MASK)

#define ISI_CHNL_IMG_CTRL_DEC_X_MASK             (0xC00U)
#define ISI_CHNL_IMG_CTRL_DEC_X_SHIFT            (10U)
/*! DEC_X - Horizontal pre-decimation control
 *  0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational.
 *  0b01..Decimate by 2
 *  0b10..Decimate by 4
 *  0b11..Decimate by 8
 */
#define ISI_CHNL_IMG_CTRL_DEC_X(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_X_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_X_MASK)

#define ISI_CHNL_IMG_CTRL_DEINT_MASK             (0x7000U)
#define ISI_CHNL_IMG_CTRL_DEINT_SHIFT            (12U)
/*! DEINT - De-interlace control
 *  0b000, 0b001..No de-interlacing done
 *  0b010..Weave de-interlacing (Odd, Even) method used
 *  0b011..Weave de-interlacing (Even, Odd) method used
 */
#define ISI_CHNL_IMG_CTRL_DEINT(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEINT_SHIFT)) & ISI_CHNL_IMG_CTRL_DEINT_MASK)

#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK      (0x8000U)
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT     (15U)
/*! GBL_ALPHA_EN - Global alpha value insertion enable
 *  0b0..Global Alpha value insertion is disabled
 *  0b1..Global Alpha value insertion is enabled
 */
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK)

#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK     (0xFF0000U)
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT    (16U)
/*! GBL_ALPHA_VAL - Global alpha value
 *  0b00000000-0b11111111..Alpha value to be inserted with all RGB pixels
 */
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK)

#define ISI_CHNL_IMG_CTRL_FORMAT_MASK            (0x7F000000U)
#define ISI_CHNL_IMG_CTRL_FORMAT_SHIFT           (24U)
/*! FORMAT - Output image format
 *  0b0000000..RGBA8888 - RGB format with alpha in LSB; 8-bits per component. 'A' indicates alpha value.
 *  0b0000001..ABGR8888 - BGR format with alpha in MSB; 8-bits per component. 'A' indicates alpha value.
 *  0b0000010..ARGB8888 - RGB format with alpha in MSB; 8-bits per component. 'A' indicates alpha value.
 *  0b0000011..RGBX888 - RGB format with 8-bits per color component (unpacked and MSB-alinged in 32-bit DWORD). 'X' indicates the waste bits.
 *  0b0000100..XBGR888 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits.
 *  0b0000101..XRGB888 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits.
 *  0b0000110..RGB888P - RGB format with 8-bits per color component (packed into 24-bits). No waste bits.
 *  0b0000111..BGR888P - BGR format with 8-bits per color component (packed into 24-bits). No waste bits.
 *  0b0001000..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component. 'A' indicates alpha value.
 *  0b0001001..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component. 'A' indicates alpha value.
 *  0b0001010..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 16-bits WORD). No waste bits.
 *  0b0001011..RAW8 - 8-bit RAW data packed into 32-bit DWORD
 *  0b0001100..RAW10 - 10-bit RAW data packed into 16-bit WORD with 6 LSBs waste bits
 *  0b0001101..RAW10P - 10-bit RAW data packed into 32-bit DWORD
 *  0b0001110..RAW12 - 12-bit RAW data packed into 16-bit DWORD with 4 LSBs waste bits
 *  0b0001111..RAW16 - 16-bit RAW data packed into 32-bit DWORD
 *  0b0010000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
 *  0b0010001..YUV444_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
 *  0b0010010..YUV444_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
 *  0b0010011..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in 32-bit DWORD)
 *  0b0010100..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b0010101..YUV444_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b0010110..YUV444_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b0010111..Reserved for future use
 *  0b0011000..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b0011001..YUV444_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b0011010..YUV444_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b0011011..Reserved for future use
 *  0b0011100..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b0011101..YUV444_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b0011110..YUV444_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b0011111..Reserved for future use
 *  0b0100000..YUV422_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
 *  0b0100001..YUV422_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
 *  0b0100010..YUV422_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
 *  0b0100011..Reserved for future use
 *  0b0100100..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b0100101..YUV422_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b0100110..YUV422_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b0100111..Reserved for future use
 *  0b0101000..YUV422_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b0101001..YUV422_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b0101010..YUV422_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b0101011..Reserved for future use
 *  0b0101100..YUV422_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b0101101..YUV422_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b0101110..YUV422_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b0101111..Reserved for future use
 *  0b0110000..Reserved for future use
 *  0b0110001..YUV420_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
 *  0b0110010..YUV420_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
 *  0b0110011..Reserved for future use
 *  0b0110100..Reserved for future use
 *  0b0110101..YUV420_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b0110110..YUV420_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b0110111..Reserved for future use
 *  0b0111000..Reserved for future use
 *  0b0111001..YUV420_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b0111010..YUV420_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b0111011..Reserved for future use
 *  0b0111100..Reserved for future use
 *  0b0111101..YUV420_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b0111110..YUV420_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b0111111..Reserved for future use
 *  0b1000000..RAW32 - 32bit RAW data packed into 32-bit DWORD
 *  0b1000001..RAW14 - 14bit RAW data packed into 32-bit DWORD
 */
#define ISI_CHNL_IMG_CTRL_FORMAT(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_FORMAT_SHIFT)) & ISI_CHNL_IMG_CTRL_FORMAT_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF_CTRL - Channel Output Buffer Control Register */
/*! @{ */

#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK (0xFU)
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT (0U)
/*! PANIC_SET_THD_Y - Overflow panic set threshold value for Y/RGB output buffer
 *  0b0000..No panic alert will be asserted
 *  0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15
 */
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK)

#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK (0xF00U)
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT (8U)
/*! PANIC_SET_THD_U - Overflow panic set threshold value for U output buffer
 *  0b0000..No panic alert will be asserted
 *  0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15
 */
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK)

#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK (0x4000U)
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT (14U)
/*! LOAD_BUF1_ADDR - Load Buffer 1 Address from CHNLOUT_BUF1_ADDR_* registers */
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK)

#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK (0x8000U)
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT (15U)
/*! LOAD_BUF2_ADDR - Load Buffer 2 Address from CHNLOUT_BUF2_ADDR_* registers */
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK)

#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK (0xF0000U)
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT (16U)
/*! PANIC_SET_THD_V - Overflow panic set threshold value for V output buffer
 *  0b0000..No panic alert will be asserted
 *  0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15
 */
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK)

#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK (0x40000000U)
#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT (30U)
/*! MAX_WR_BEATS_UV - Maximum AXI write beats for U and V-buffers
 *  0b0..Maximum write beats per write request are 8 (i.e. 128 bytes)
 *  0b1..Maximum write beats per write request are 16 (i.e. 256 bytes)
 */
#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK)

#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK (0x80000000U)
#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT (31U)
/*! MAX_WR_BEATS_Y - Maximum AXI write beats for Y-buffer
 *  0b0..Maximum write beats per write request are 8 (i.e. 128 bytes)
 *  0b1..Maximum write beats per write request are 16 (i.e. 256 bytes)
 */
#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK)
/*! @} */

/*! @name CHNL_IMG_CFG - Channel Image Configuration */
/*! @{ */

#define ISI_CHNL_IMG_CFG_WIDTH_MASK              (0x1FFFU)
#define ISI_CHNL_IMG_CFG_WIDTH_SHIFT             (0U)
/*! WIDTH - Input image width (pixels) */
#define ISI_CHNL_IMG_CFG_WIDTH(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_IMG_CFG_WIDTH_MASK)

#define ISI_CHNL_IMG_CFG_RSVD0_MASK              (0xE000U)
#define ISI_CHNL_IMG_CFG_RSVD0_SHIFT             (13U)
/*! RSVD0 - Reserved field. Reads only zeros. */
#define ISI_CHNL_IMG_CFG_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD0_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD0_MASK)

#define ISI_CHNL_IMG_CFG_HEIGHT_MASK             (0x1FFF0000U)
#define ISI_CHNL_IMG_CFG_HEIGHT_SHIFT            (16U)
/*! HEIGHT - Input image height (lines) */
#define ISI_CHNL_IMG_CFG_HEIGHT(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_IMG_CFG_HEIGHT_MASK)

#define ISI_CHNL_IMG_CFG_RSVD1_MASK              (0xE0000000U)
#define ISI_CHNL_IMG_CFG_RSVD1_SHIFT             (29U)
/*! RSVD1 - Reserved field. Reads only zeros. */
#define ISI_CHNL_IMG_CFG_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD1_MASK)
/*! @} */

/*! @name CHNL_IER - Channel Interrupt Enable Register */
/*! @{ */

#define ISI_CHNL_IER_RSVD0_MASK                  (0xFFFFU)
#define ISI_CHNL_IER_RSVD0_SHIFT                 (0U)
/*! RSVD0 - Reserved field. Reads only zeros. */
#define ISI_CHNL_IER_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_RSVD0_SHIFT)) & ISI_CHNL_IER_RSVD0_MASK)

#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK      (0x10000U)
#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT     (16U)
/*! LATE_VSYNC_ERR_EN - VSYNC timing (Late) error interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK)

#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK     (0x20000U)
#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT    (17U)
/*! EARLY_VSYNC_ERR_EN - VSYNC timing (Early) error interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK)

#define ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK          (0x40000U)
#define ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT         (18U)
/*! OFLW_Y_BUF_EN - Y output buffer overflow interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_OFLW_Y_BUF_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK)

#define ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK         (0x80000U)
#define ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT        (19U)
/*! PANIC_Y_BUF_EN - Y output buffer potential overflow panic interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_PANIC_Y_BUF_EN(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK)

#define ISI_CHNL_IER_OFLW_U_BUF_EN_MASK          (0x100000U)
#define ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT         (20U)
/*! OFLW_U_BUF_EN - U output buffer overflow interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_OFLW_U_BUF_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_U_BUF_EN_MASK)

#define ISI_CHNL_IER_PANIC_U_BUF_EN_MASK         (0x200000U)
#define ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT        (21U)
/*! PANIC_U_BUF_EN - U output buffer potential overflow panic interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_PANIC_U_BUF_EN(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_U_BUF_EN_MASK)

#define ISI_CHNL_IER_OFLW_V_BUF_EN_MASK          (0x400000U)
#define ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT         (22U)
/*! OFLW_V_BUF_EN - V output buffer overflow interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_OFLW_V_BUF_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_V_BUF_EN_MASK)

#define ISI_CHNL_IER_PANIC_V_BUF_EN_MASK         (0x800000U)
#define ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT        (23U)
/*! PANIC_V_BUF_EN - V output buffer potential overflow panic interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_PANIC_V_BUF_EN(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_V_BUF_EN_MASK)

#define ISI_CHNL_IER_AXI_RD_ERR_EN_MASK          (0x2000000U)
#define ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT         (25U)
/*! AXI_RD_ERR_EN - AXI bus read error interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_AXI_RD_ERR_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT)) & ISI_CHNL_IER_AXI_RD_ERR_EN_MASK)

#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK        (0x4000000U)
#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT       (26U)
/*! AXI_WR_ERR_Y_EN - AXI bus read error interrupt enable bit for Y/RGB data buffer
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK)

#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK        (0x8000000U)
#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT       (27U)
/*! AXI_WR_ERR_U_EN - AXI bus read error interrupt enable bit for U data buffer
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_AXI_WR_ERR_U_EN(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK)

#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK        (0x10000000U)
#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT       (28U)
/*! AXI_WR_ERR_V_EN - AXI bus read error interrupt enable bit for V data buffer
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_AXI_WR_ERR_V_EN(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK)

#define ISI_CHNL_IER_FRM_RCVD_EN_MASK            (0x20000000U)
#define ISI_CHNL_IER_FRM_RCVD_EN_SHIFT           (29U)
/*! FRM_RCVD_EN - Frame received interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_FRM_RCVD_EN(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_FRM_RCVD_EN_SHIFT)) & ISI_CHNL_IER_FRM_RCVD_EN_MASK)

#define ISI_CHNL_IER_LINE_RCVD_EN_MASK           (0x40000000U)
#define ISI_CHNL_IER_LINE_RCVD_EN_SHIFT          (30U)
/*! LINE_RCVD_EN - Line received interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_LINE_RCVD_EN(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LINE_RCVD_EN_SHIFT)) & ISI_CHNL_IER_LINE_RCVD_EN_MASK)

#define ISI_CHNL_IER_MEM_RD_DONE_EN_MASK         (0x80000000U)
#define ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT        (31U)
/*! MEM_RD_DONE_EN - Memory read complete interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_MEM_RD_DONE_EN(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT)) & ISI_CHNL_IER_MEM_RD_DONE_EN_MASK)
/*! @} */

/*! @name CHNL_STS - Channel Status Register */
/*! @{ */

#define ISI_CHNL_STS_BUF1_ACTIVE_MASK            (0x100U)
#define ISI_CHNL_STS_BUF1_ACTIVE_SHIFT           (8U)
/*! BUF1_ACTIVE - Current frame being stored in Buffer 1 Address
 *  0b0..Buffer 1 Address inactive
 *  0b1..Buffer 1 Address in use
 */
#define ISI_CHNL_STS_BUF1_ACTIVE(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF1_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF1_ACTIVE_MASK)

#define ISI_CHNL_STS_BUF2_ACTIVE_MASK            (0x200U)
#define ISI_CHNL_STS_BUF2_ACTIVE_SHIFT           (9U)
/*! BUF2_ACTIVE - Current frame being stored in Buffer 2 Address
 *  0b0..Buffer 2 Address inactive
 *  0b1..Buffer 2 Address in use
 */
#define ISI_CHNL_STS_BUF2_ACTIVE(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF2_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF2_ACTIVE_MASK)

#define ISI_CHNL_STS_MEM_RD_OFLOW_MASK           (0x400U)
#define ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT          (10U)
/*! MEM_RD_OFLOW - Memory read FIFO overflow error status
 *  0b0..No overflow occurred during memory read
 *  0b1..FIFO overflow occurred during memory read
 */
#define ISI_CHNL_STS_MEM_RD_OFLOW(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT)) & ISI_CHNL_STS_MEM_RD_OFLOW_MASK)

#define ISI_CHNL_STS_RSVD1_MASK                  (0xF800U)
#define ISI_CHNL_STS_RSVD1_SHIFT                 (11U)
/*! RSVD1 - Reserved field. Reads only zeros. */
#define ISI_CHNL_STS_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_RSVD1_SHIFT)) & ISI_CHNL_STS_RSVD1_MASK)

#define ISI_CHNL_STS_LATE_VSYNC_ERR_MASK         (0x10000U)
#define ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT        (16U)
/*! LATE_VSYNC_ERR - VSYNC timing (Late) error interrupt flag
 *  0b0..No error
 *  0b1..VSYNC detected later than expected
 */
#define ISI_CHNL_STS_LATE_VSYNC_ERR(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_LATE_VSYNC_ERR_MASK)

#define ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK        (0x20000U)
#define ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT       (17U)
/*! EARLY_VSYNC_ERR - VSYNC timing (Early) error interrupt flag
 *  0b0..No error
 *  0b1..VSYNC detected earlier than expected
 */
#define ISI_CHNL_STS_EARLY_VSYNC_ERR(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK)

#define ISI_CHNL_STS_OFLW_Y_BUF_MASK             (0x40000U)
#define ISI_CHNL_STS_OFLW_Y_BUF_SHIFT            (18U)
/*! OFLW_Y_BUF - Overflow in Y/RGB output buffer interrupt flag
 *  0b0..No overflow
 *  0b1..Overflow has occured in the channel
 */
#define ISI_CHNL_STS_OFLW_Y_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_Y_BUF_MASK)

#define ISI_CHNL_STS_PANIC_Y_BUF_MASK            (0x80000U)
#define ISI_CHNL_STS_PANIC_Y_BUF_SHIFT           (19U)
/*! PANIC_Y_BUF - Y/RGB output buffer potential overflow panic alert interrupt flag
 *  0b0..Buffer has not crossed the panic threshold limit
 *  0b1..Panic threshold limit crossed. Software must take action.
 */
#define ISI_CHNL_STS_PANIC_Y_BUF(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_Y_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_Y_BUF_MASK)

#define ISI_CHNL_STS_OFLW_U_BUF_MASK             (0x100000U)
#define ISI_CHNL_STS_OFLW_U_BUF_SHIFT            (20U)
/*! OFLW_U_BUF - Overflow in U output buffer interrupt flag
 *  0b0..No overflow
 *  0b1..Overflow has occured in the channel
 */
#define ISI_CHNL_STS_OFLW_U_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_U_BUF_MASK)

#define ISI_CHNL_STS_PANIC_U_BUF_MASK            (0x200000U)
#define ISI_CHNL_STS_PANIC_U_BUF_SHIFT           (21U)
/*! PANIC_U_BUF - U output buffer potential overflow panic alert interrupt flag
 *  0b0..Buffer has not crossed the panic threshold limit
 *  0b1..Panic threshold limit crossed. Software must take action.
 */
#define ISI_CHNL_STS_PANIC_U_BUF(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_U_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_U_BUF_MASK)

#define ISI_CHNL_STS_OFLW_V_BUF_MASK             (0x400000U)
#define ISI_CHNL_STS_OFLW_V_BUF_SHIFT            (22U)
/*! OFLW_V_BUF - Overflow in U output buffer interrupt flag
 *  0b0..No overflow
 *  0b1..Overflow has occured in the channel
 */
#define ISI_CHNL_STS_OFLW_V_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_V_BUF_MASK)

#define ISI_CHNL_STS_PANIC_V_BUF_MASK            (0x800000U)
#define ISI_CHNL_STS_PANIC_V_BUF_SHIFT           (23U)
/*! PANIC_V_BUF - V output buffer potential overflow panic alert interrupt flag
 *  0b0..Buffer has not crossed the panic threshold limit
 *  0b1..Panic threshold limit crossed. Software must take action.
 */
#define ISI_CHNL_STS_PANIC_V_BUF(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_V_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_V_BUF_MASK)

#define ISI_CHNL_STS_AXI_RD_ERR_MASK             (0x2000000U)
#define ISI_CHNL_STS_AXI_RD_ERR_SHIFT            (25U)
/*! AXI_RD_ERR - AXI Bus read error interrupt flag
 *  0b0..No error
 *  0b1..Error occured during read
 */
#define ISI_CHNL_STS_AXI_RD_ERR(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_RD_ERR_SHIFT)) & ISI_CHNL_STS_AXI_RD_ERR_MASK)

#define ISI_CHNL_STS_AXI_WR_ERR_Y_MASK           (0x4000000U)
#define ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT          (26U)
/*! AXI_WR_ERR_Y - AXI Bus write error interrupt flag for Y/RGB data buffer
 *  0b0..No error
 *  0b1..Error occured during write
 */
#define ISI_CHNL_STS_AXI_WR_ERR_Y(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_Y_MASK)

#define ISI_CHNL_STS_AXI_WR_ERR_U_MASK           (0x8000000U)
#define ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT          (27U)
/*! AXI_WR_ERR_U - AXI Bus write error interrupt flag for U data buffer
 *  0b0..No error
 *  0b1..Error occured during write
 */
#define ISI_CHNL_STS_AXI_WR_ERR_U(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_U_MASK)

#define ISI_CHNL_STS_AXI_WR_ERR_V_MASK           (0x10000000U)
#define ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT          (28U)
/*! AXI_WR_ERR_V - AXI Bus write error interrupt flag for V data buffer
 *  0b0..No error
 *  0b1..Error occured during write
 */
#define ISI_CHNL_STS_AXI_WR_ERR_V(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_V_MASK)

#define ISI_CHNL_STS_FRM_STRD_MASK               (0x20000000U)
#define ISI_CHNL_STS_FRM_STRD_SHIFT              (29U)
/*! FRM_STRD - Frame stored successfully interrupt flag
 *  0b0..No frame being received or in progress
 *  0b1..One full frame has been received and stored in memory
 */
#define ISI_CHNL_STS_FRM_STRD(x)                 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_FRM_STRD_SHIFT)) & ISI_CHNL_STS_FRM_STRD_MASK)

#define ISI_CHNL_STS_LINE_STRD_MASK              (0x40000000U)
#define ISI_CHNL_STS_LINE_STRD_SHIFT             (30U)
/*! LINE_STRD - Line received and stored interrupt flag
 *  0b0..No new line received
 *  0b1..New line received and stored into memory
 */
#define ISI_CHNL_STS_LINE_STRD(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LINE_STRD_SHIFT)) & ISI_CHNL_STS_LINE_STRD_MASK)

#define ISI_CHNL_STS_MEM_RD_DONE_MASK            (0x80000000U)
#define ISI_CHNL_STS_MEM_RD_DONE_SHIFT           (31U)
/*! MEM_RD_DONE - Memory read complete interrupt flag
 *  0b0..Image read from memory not complete or not started
 *  0b1..Image read from memory completed
 */
#define ISI_CHNL_STS_MEM_RD_DONE(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_DONE_SHIFT)) & ISI_CHNL_STS_MEM_RD_DONE_MASK)
/*! @} */

/*! @name CHNL_SCALE_FACTOR - Channel Scale Factor Register */
/*! @{ */

#define ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK       (0x3FFFU)
#define ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT      (0U)
/*! X_SCALE - Horizontal scaling factor */
#define ISI_CHNL_SCALE_FACTOR_X_SCALE(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK)

#define ISI_CHNL_SCALE_FACTOR_RSVD1_MASK         (0xC000U)
#define ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT        (14U)
/*! RSVD1 - Reserved field. Reads only zeros */
#define ISI_CHNL_SCALE_FACTOR_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD1_MASK)

#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK       (0x3FFF0000U)
#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT      (16U)
/*! Y_SCALE - Vertical scaling factor */
#define ISI_CHNL_SCALE_FACTOR_Y_SCALE(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK)

#define ISI_CHNL_SCALE_FACTOR_RSVD0_MASK         (0xC0000000U)
#define ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT        (30U)
/*! RSVD0 - Reserved field. Reads only zeros */
#define ISI_CHNL_SCALE_FACTOR_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD0_MASK)
/*! @} */

/*! @name CHNL_SCALE_OFFSET - Channel Scale Offset Register */
/*! @{ */

#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK      (0xFFFU)
#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT     (0U)
/*! X_OFFSET - Horizontal scaling offset */
#define ISI_CHNL_SCALE_OFFSET_X_OFFSET(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK)

#define ISI_CHNL_SCALE_OFFSET_RSVD1_MASK         (0xF000U)
#define ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT        (12U)
/*! RSVD1 - Reserved field. Reads only zeros */
#define ISI_CHNL_SCALE_OFFSET_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD1_MASK)

#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK      (0xFFF0000U)
#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT     (16U)
/*! Y_OFFSET - Vertical scaling offset */
#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK)

#define ISI_CHNL_SCALE_OFFSET_RSVD0_MASK         (0xF0000000U)
#define ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT        (28U)
/*! RSVD0 - Reserved field. Reads only zeros */
#define ISI_CHNL_SCALE_OFFSET_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CROP_ULC - Channel Crop Upper Left Corner Coordinate Register */
/*! @{ */

#define ISI_CHNL_CROP_ULC_Y_MASK                 (0xFFFU)
#define ISI_CHNL_CROP_ULC_Y_SHIFT                (0U)
/*! Y - Upper Left Y-coordinate */
#define ISI_CHNL_CROP_ULC_Y(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_Y_SHIFT)) & ISI_CHNL_CROP_ULC_Y_MASK)

#define ISI_CHNL_CROP_ULC_RSVD1_MASK             (0xF000U)
#define ISI_CHNL_CROP_ULC_RSVD1_SHIFT            (12U)
/*! RSVD1 - Reserved field. Reads only zeros */
#define ISI_CHNL_CROP_ULC_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD1_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD1_MASK)

#define ISI_CHNL_CROP_ULC_X_MASK                 (0xFFF0000U)
#define ISI_CHNL_CROP_ULC_X_SHIFT                (16U)
/*! X - Upper Left X-coordinate */
#define ISI_CHNL_CROP_ULC_X(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_X_SHIFT)) & ISI_CHNL_CROP_ULC_X_MASK)

#define ISI_CHNL_CROP_ULC_RSVD0_MASK             (0xF0000000U)
#define ISI_CHNL_CROP_ULC_RSVD0_SHIFT            (28U)
/*! RSVD0 - Reserved field. Reads only zeros */
#define ISI_CHNL_CROP_ULC_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD0_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CROP_LRC - Channel Crop Lower Right Corner Coordinate Register */
/*! @{ */

#define ISI_CHNL_CROP_LRC_Y_MASK                 (0xFFFU)
#define ISI_CHNL_CROP_LRC_Y_SHIFT                (0U)
/*! Y - Lower Right Y-coordinate */
#define ISI_CHNL_CROP_LRC_Y(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_Y_SHIFT)) & ISI_CHNL_CROP_LRC_Y_MASK)

#define ISI_CHNL_CROP_LRC_RSVD1_MASK             (0xF000U)
#define ISI_CHNL_CROP_LRC_RSVD1_SHIFT            (12U)
/*! RSVD1 - Reserved field. Reads only zeros */
#define ISI_CHNL_CROP_LRC_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD1_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD1_MASK)

#define ISI_CHNL_CROP_LRC_X_MASK                 (0xFFF0000U)
#define ISI_CHNL_CROP_LRC_X_SHIFT                (16U)
/*! X - Lower Right X-coordinate */
#define ISI_CHNL_CROP_LRC_X(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_X_SHIFT)) & ISI_CHNL_CROP_LRC_X_MASK)

#define ISI_CHNL_CROP_LRC_RSVD0_MASK             (0xF0000000U)
#define ISI_CHNL_CROP_LRC_RSVD0_SHIFT            (28U)
/*! RSVD0 - Reserved field. Reads only zeros */
#define ISI_CHNL_CROP_LRC_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD0_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CSC_COEFF0 - Channel Color Space Conversion Coefficient Register 0 */
/*! @{ */

#define ISI_CHNL_CSC_COEFF0_A1_MASK              (0x7FFU)
#define ISI_CHNL_CSC_COEFF0_A1_SHIFT             (0U)
/*! A1 - CSC Coefficient A1 value */
#define ISI_CHNL_CSC_COEFF0_A1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A1_SHIFT)) & ISI_CHNL_CSC_COEFF0_A1_MASK)

#define ISI_CHNL_CSC_COEFF0_RSVD1_MASK           (0xF800U)
#define ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT          (11U)
/*! RSVD1 - Reserved Field. Reads only zeros */
#define ISI_CHNL_CSC_COEFF0_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD1_MASK)

#define ISI_CHNL_CSC_COEFF0_A2_MASK              (0x7FF0000U)
#define ISI_CHNL_CSC_COEFF0_A2_SHIFT             (16U)
/*! A2 - CSC Coefficient A2 value */
#define ISI_CHNL_CSC_COEFF0_A2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A2_SHIFT)) & ISI_CHNL_CSC_COEFF0_A2_MASK)

#define ISI_CHNL_CSC_COEFF0_RSVD0_MASK           (0xF8000000U)
#define ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT          (27U)
/*! RSVD0 - Reserved Field. Reads only zeros */
#define ISI_CHNL_CSC_COEFF0_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CSC_COEFF1 - Channel Color Space Conversion Coefficient Register 1 */
/*! @{ */

#define ISI_CHNL_CSC_COEFF1_A3_MASK              (0x7FFU)
#define ISI_CHNL_CSC_COEFF1_A3_SHIFT             (0U)
/*! A3 - CSC Coefficient A3 value */
#define ISI_CHNL_CSC_COEFF1_A3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_A3_SHIFT)) & ISI_CHNL_CSC_COEFF1_A3_MASK)

#define ISI_CHNL_CSC_COEFF1_RSVD1_MASK           (0xF800U)
#define ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT          (11U)
/*! RSVD1 - Reserved Field. Reads only zeros */
#define ISI_CHNL_CSC_COEFF1_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD1_MASK)

#define ISI_CHNL_CSC_COEFF1_B1_MASK              (0x7FF0000U)
#define ISI_CHNL_CSC_COEFF1_B1_SHIFT             (16U)
/*! B1 - CSC Coefficient B1 value */
#define ISI_CHNL_CSC_COEFF1_B1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_B1_SHIFT)) & ISI_CHNL_CSC_COEFF1_B1_MASK)

#define ISI_CHNL_CSC_COEFF1_RSVD0_MASK           (0xF8000000U)
#define ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT          (27U)
/*! RSVD0 - Reserved Field. Reads only zeros */
#define ISI_CHNL_CSC_COEFF1_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CSC_COEFF2 - Channel Color Space Conversion Coefficient Register 2 */
/*! @{ */

#define ISI_CHNL_CSC_COEFF2_B2_MASK              (0x7FFU)
#define ISI_CHNL_CSC_COEFF2_B2_SHIFT             (0U)
/*! B2 - CSC Coefficient B2 value */
#define ISI_CHNL_CSC_COEFF2_B2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B2_SHIFT)) & ISI_CHNL_CSC_COEFF2_B2_MASK)

#define ISI_CHNL_CSC_COEFF2_RSVD1_MASK           (0xF800U)
#define ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT          (11U)
/*! RSVD1 - Reserved Field. Reads only zeros */
#define ISI_CHNL_CSC_COEFF2_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD1_MASK)

#define ISI_CHNL_CSC_COEFF2_B3_MASK              (0x7FF0000U)
#define ISI_CHNL_CSC_COEFF2_B3_SHIFT             (16U)
/*! B3 - CSC Coefficient B3 value */
#define ISI_CHNL_CSC_COEFF2_B3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B3_SHIFT)) & ISI_CHNL_CSC_COEFF2_B3_MASK)

#define ISI_CHNL_CSC_COEFF2_RSVD0_MASK           (0xF8000000U)
#define ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT          (27U)
/*! RSVD0 - Reserved Field. Reads only zeros */
#define ISI_CHNL_CSC_COEFF2_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CSC_COEFF3 - Channel Color Space Conversion Coefficient Register 3 */
/*! @{ */

#define ISI_CHNL_CSC_COEFF3_C1_MASK              (0x7FFU)
#define ISI_CHNL_CSC_COEFF3_C1_SHIFT             (0U)
/*! C1 - CSC Coefficient C1 value */
#define ISI_CHNL_CSC_COEFF3_C1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C1_SHIFT)) & ISI_CHNL_CSC_COEFF3_C1_MASK)

#define ISI_CHNL_CSC_COEFF3_RSVD1_MASK           (0xF800U)
#define ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT          (11U)
/*! RSVD1 - Reserved Field. Reads only zeros */
#define ISI_CHNL_CSC_COEFF3_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD1_MASK)

#define ISI_CHNL_CSC_COEFF3_C2_MASK              (0x7FF0000U)
#define ISI_CHNL_CSC_COEFF3_C2_SHIFT             (16U)
/*! C2 - CSC Coefficient C2 value */
#define ISI_CHNL_CSC_COEFF3_C2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C2_SHIFT)) & ISI_CHNL_CSC_COEFF3_C2_MASK)

#define ISI_CHNL_CSC_COEFF3_RSVD0_MASK           (0xF8000000U)
#define ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT          (27U)
/*! RSVD0 - Reserved Field. Reads only zeros */
#define ISI_CHNL_CSC_COEFF3_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CSC_COEFF4 - Channel Color Space Conversion Coefficient Register 4 */
/*! @{ */

#define ISI_CHNL_CSC_COEFF4_C3_MASK              (0x7FFU)
#define ISI_CHNL_CSC_COEFF4_C3_SHIFT             (0U)
/*! C3 - CSC Coefficient C3 value */
#define ISI_CHNL_CSC_COEFF4_C3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_C3_SHIFT)) & ISI_CHNL_CSC_COEFF4_C3_MASK)

#define ISI_CHNL_CSC_COEFF4_RSVD1_MASK           (0xF800U)
#define ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT          (11U)
/*! RSVD1 - Reserved Field. Reads only zeros */
#define ISI_CHNL_CSC_COEFF4_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD1_MASK)

#define ISI_CHNL_CSC_COEFF4_D1_MASK              (0x1FF0000U)
#define ISI_CHNL_CSC_COEFF4_D1_SHIFT             (16U)
/*! D1 - CSC Coefficient D1 value */
#define ISI_CHNL_CSC_COEFF4_D1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_D1_SHIFT)) & ISI_CHNL_CSC_COEFF4_D1_MASK)

#define ISI_CHNL_CSC_COEFF4_RSVD0_MASK           (0xFE000000U)
#define ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT          (25U)
/*! RSVD0 - Reserved Field. Reads only zeros */
#define ISI_CHNL_CSC_COEFF4_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CSC_COEFF5 - Channel Color Space Conversion Coefficient Register 5 */
/*! @{ */

#define ISI_CHNL_CSC_COEFF5_D2_MASK              (0x1FFU)
#define ISI_CHNL_CSC_COEFF5_D2_SHIFT             (0U)
/*! D2 - CSC Coefficient D2 value */
#define ISI_CHNL_CSC_COEFF5_D2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D2_SHIFT)) & ISI_CHNL_CSC_COEFF5_D2_MASK)

#define ISI_CHNL_CSC_COEFF5_RSVD1_MASK           (0xFE00U)
#define ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT          (9U)
/*! RSVD1 - Reserved Field. Reads only zeros */
#define ISI_CHNL_CSC_COEFF5_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD1_MASK)

#define ISI_CHNL_CSC_COEFF5_D3_MASK              (0x1FF0000U)
#define ISI_CHNL_CSC_COEFF5_D3_SHIFT             (16U)
/*! D3 - CSC Coefficient D3 value */
#define ISI_CHNL_CSC_COEFF5_D3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D3_SHIFT)) & ISI_CHNL_CSC_COEFF5_D3_MASK)

#define ISI_CHNL_CSC_COEFF5_RSVD0_MASK           (0xFE000000U)
#define ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT          (25U)
/*! RSVD0 - Reserved Field. Reads only zeros */
#define ISI_CHNL_CSC_COEFF5_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD0_MASK)
/*! @} */

/*! @name CHNL_ROI_ALPHA - Channel Alpha Value Register for Region of Interest 0..Channel Alpha Value Register for Region of Interest 3 */
/*! @{ */

#define ISI_CHNL_ROI_ALPHA_RSVD1_MASK            (0xFFFFU)
#define ISI_CHNL_ROI_ALPHA_RSVD1_SHIFT           (0U)
/*! RSVD1 - Reserved field. Reads only zeros */
#define ISI_CHNL_ROI_ALPHA_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_ALPHA_RSVD1_MASK)

#define ISI_CHNL_ROI_ALPHA_ALPHA_EN_MASK         (0x10000U)
#define ISI_CHNL_ROI_ALPHA_ALPHA_EN_SHIFT        (16U)
/*! ALPHA_EN - Alpha value insertion enable
 *  0b0..Alpha value insertion is disabled
 *  0b1..Alpha value insertion is enabled
 */
#define ISI_CHNL_ROI_ALPHA_ALPHA_EN(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_ALPHA_ALPHA_EN_MASK)

#define ISI_CHNL_ROI_ALPHA_RSVD0_MASK            (0xFE0000U)
#define ISI_CHNL_ROI_ALPHA_RSVD0_SHIFT           (17U)
/*! RSVD0 - Reserved field. Reads only zeros */
#define ISI_CHNL_ROI_ALPHA_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_ALPHA_RSVD0_MASK)

#define ISI_CHNL_ROI_ALPHA_ALPHA_MASK            (0xFF000000U)
#define ISI_CHNL_ROI_ALPHA_ALPHA_SHIFT           (24U)
/*! ALPHA - Alpha Value to be inserted with image */
#define ISI_CHNL_ROI_ALPHA_ALPHA(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_ALPHA_ALPHA_MASK)
/*! @} */

/* The count of ISI_CHNL_ROI_ALPHA */
#define ISI_CHNL_ROI_ALPHA_COUNT                 (4U)

/*! @name CHNL_ROI_ULC - Channel Upper Left Coordinate Register for Region of Interest 0..Channel Upper Left Coordinate Register for Region of Interest 3 */
/*! @{ */

#define ISI_CHNL_ROI_ULC_Y_MASK                  (0xFFFU)
#define ISI_CHNL_ROI_ULC_Y_SHIFT                 (0U)
/*! Y - Upper Left Y-coordinate */
#define ISI_CHNL_ROI_ULC_Y(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_Y_SHIFT)) & ISI_CHNL_ROI_ULC_Y_MASK)

#define ISI_CHNL_ROI_ULC_RSVD1_MASK              (0xF000U)
#define ISI_CHNL_ROI_ULC_RSVD1_SHIFT             (12U)
/*! RSVD1 - Reserved field. Reads only zeros */
#define ISI_CHNL_ROI_ULC_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_ULC_RSVD1_MASK)

#define ISI_CHNL_ROI_ULC_X_MASK                  (0xFFF0000U)
#define ISI_CHNL_ROI_ULC_X_SHIFT                 (16U)
/*! X - Upper Left X-coordinate */
#define ISI_CHNL_ROI_ULC_X(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_X_SHIFT)) & ISI_CHNL_ROI_ULC_X_MASK)

#define ISI_CHNL_ROI_ULC_RSVD0_MASK              (0xF0000000U)
#define ISI_CHNL_ROI_ULC_RSVD0_SHIFT             (28U)
/*! RSVD0 - Reserved field. Reads only zeros */
#define ISI_CHNL_ROI_ULC_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_ULC_RSVD0_MASK)
/*! @} */

/* The count of ISI_CHNL_ROI_ULC */
#define ISI_CHNL_ROI_ULC_COUNT                   (4U)

/*! @name CHNL_ROI_LRC - Channel Lower Right Coordinate Register for Region of Interest 0..Channel Lower Right Coordinate Register for Region of Interest 3 */
/*! @{ */

#define ISI_CHNL_ROI_LRC_Y_MASK                  (0xFFFU)
#define ISI_CHNL_ROI_LRC_Y_SHIFT                 (0U)
/*! Y - Lower Right Y-coordinate */
#define ISI_CHNL_ROI_LRC_Y(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_Y_SHIFT)) & ISI_CHNL_ROI_LRC_Y_MASK)

#define ISI_CHNL_ROI_LRC_RSVD1_MASK              (0xF000U)
#define ISI_CHNL_ROI_LRC_RSVD1_SHIFT             (12U)
/*! RSVD1 - Reserved field. Reads only zeros */
#define ISI_CHNL_ROI_LRC_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_LRC_RSVD1_MASK)

#define ISI_CHNL_ROI_LRC_X_MASK                  (0xFFF0000U)
#define ISI_CHNL_ROI_LRC_X_SHIFT                 (16U)
/*! X - Lower Right X-coordinate */
#define ISI_CHNL_ROI_LRC_X(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_X_SHIFT)) & ISI_CHNL_ROI_LRC_X_MASK)

#define ISI_CHNL_ROI_LRC_RSVD0_MASK              (0xF0000000U)
#define ISI_CHNL_ROI_LRC_RSVD0_SHIFT             (28U)
/*! RSVD0 - Reserved field. Reads only zeros */
#define ISI_CHNL_ROI_LRC_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_LRC_RSVD0_MASK)
/*! @} */

/* The count of ISI_CHNL_ROI_LRC */
#define ISI_CHNL_ROI_LRC_COUNT                   (4U)

/*! @name CHNL_OUT_BUF1_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 1 Address */
/*! @{ */

#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK       (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT      (0U)
/*! ADDR - Starting address for the RGB or Y (luma) memory location */
#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF1_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */
/*! @{ */

#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK       (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT      (0U)
/*! ADDR - Starting address for the U/Cb or 2 plane UV/CbCr Chroma memory location */
#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF1_ADDR_V - Channel Chroma (V/Cr) Output Buffer 1 Address */
/*! @{ */

#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK       (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT      (0U)
/*! ADDR - Starting address for the V/Cr memory location */
#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF_PITCH - Channel Output Buffer Pitch */
/*! @{ */

#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK   (0xFFFFU)
#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT  (0U)
/*! LINE_PITCH - Output Buffer Line Pitch */
#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH(x)     (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK)
/*! @} */

/*! @name CHNL_IN_BUF_ADDR - Channel Input Buffer Address */
/*! @{ */

#define ISI_CHNL_IN_BUF_ADDR_ADDR_MASK           (0xFFFFFFFFU)
#define ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT          (0U)
#define ISI_CHNL_IN_BUF_ADDR_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT)) & ISI_CHNL_IN_BUF_ADDR_ADDR_MASK)
/*! @} */

/*! @name CHNL_IN_BUF_PITCH - Channel Input Buffer Pitch */
/*! @{ */

#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK    (0xFFFFU)
#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT   (0U)
/*! LINE_PITCH - Line Pitch */
#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH(x)      (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK)

#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK     (0xFFFF0000U)
#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT    (16U)
/*! FRM_PITCH - Frame Pitch */
#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK)
/*! @} */

/*! @name CHNL_MEM_RD_CTRL - Channel Memory Read Control */
/*! @{ */

#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK       (0x1U)
#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT      (0U)
/*! READ_MEM - Initiate read from memory
 *  0b0..No reads from memory done
 *  0b1..Reads from memory initiated
 */
#define ISI_CHNL_MEM_RD_CTRL_READ_MEM(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK)

#define ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK          (0xFFFFFFEU)
#define ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT         (1U)
/*! RSVD0 - Reserved field. Reads only zeros */
#define ISI_CHNL_MEM_RD_CTRL_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK)

#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK       (0xF0000000U)
#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT      (28U)
/*! IMG_TYPE - Input image format
 *  0b0000..BGR8P - BGR format with 8-bits per color component (packed into 32-bit DWORD)
 *  0b0001..RGB8P - RGB format with 8-bits per color component (packed into 32-bit DWORD)
 *  0b0010..XRGB8 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD)
 *  0b0011..RGBX8 - RGB format with 8-bits per color component (unpacked and MSBalinged in 32-bit DWORD)
 *  0b0100..XBGR8 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD)
 *  0b0101..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 32-bit DWORD)
 *  0b0110..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component
 *  0b0111..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component
 *  0b1000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
 *  0b1001..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b1010..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit WORD)
 *  0b1011..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b1100..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in 32-bit DWORD)
 *  0b1101..YUV422_1P8P with 8-bits per color component; 1-plane YUV interleaved packed bytes
 *  0b1110..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b1111..YUV422_1P12 with 12-bits per color component; 1-plane, YUV interleaved packed bytes (4 MSBs waste bits in 16-bit WORD)
 */
#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF2_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 2 Address */
/*! @{ */

#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK       (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT      (0U)
/*! ADDR - Starting address for the RGB or Y (luma) memory location */
#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF2_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */
/*! @{ */

#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK       (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT      (0U)
/*! ADDR - Starting address for the U/Cb or 2 plane UV/CbCr Chroma memory location */
#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF2_ADDR_V - Channel Chroma (V/Cr) Output Buffer 2 Address */
/*! @{ */

#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK       (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT      (0U)
/*! ADDR - Starting address for the V/Cr memory location */
#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK)
/*! @} */

/*! @name CHNL_SCL_IMG_CFG - Channel Scaled Image Configuration */
/*! @{ */

#define ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK          (0x1FFFU)
#define ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT         (0U)
/*! WIDTH - Scaled image width (pixels) */
#define ISI_CHNL_SCL_IMG_CFG_WIDTH(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK)

#define ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK          (0xE000U)
#define ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT         (13U)
/*! RSVD1 - Reserved field. Reads only zeros. */
#define ISI_CHNL_SCL_IMG_CFG_RSVD1(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK)

#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK         (0x1FFF0000U)
#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT        (16U)
/*! HEIGHT - Scaled image height (lines) */
#define ISI_CHNL_SCL_IMG_CFG_HEIGHT(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK)

#define ISI_CHNL_SCL_IMG_CFG_RSVD3_MASK          (0xE0000000U)
#define ISI_CHNL_SCL_IMG_CFG_RSVD3_SHIFT         (29U)
/*! RSVD3 - Reserved field. Reads only zeros. */
#define ISI_CHNL_SCL_IMG_CFG_RSVD3(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD3_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD3_MASK)
/*! @} */

/*! @name CHNL_FLOW_CTRL - Channel Flow Control Register */
/*! @{ */

#define ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK         (0xFFU)
#define ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT        (0U)
/*! FC_DENOM - Denominator value of fraction of usable bandwidth
 *  0b00000000..Invalid value. Flow control will be disabled.
 */
#define ISI_CHNL_FLOW_CTRL_FC_DENOM(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK)

#define ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK         (0xFF0000U)
#define ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT        (16U)
/*! FC_NUMER - Numertor value of fraction of usable bandwidth
 *  0b00000000..Flow control is disabled.
 */
#define ISI_CHNL_FLOW_CTRL_FC_NUMER(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ISI_Register_Masks */


/* ISI - Peripheral instance base addresses */
/** Peripheral ISI0 base address */
#define ISI0_BASE                                (0x2DAC0000u)
/** Peripheral ISI0 base pointer */
#define ISI0                                     ((ISI_Type *)ISI0_BASE)
/** Array initializer of ISI peripheral base addresses */
#define ISI_BASE_ADDRS                           { ISI0_BASE }
/** Array initializer of ISI peripheral base pointers */
#define ISI_BASE_PTRS                            { ISI0 }

/*!
 * @}
 */ /* end of group ISI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LCDIF Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
 * @{
 */

/** LCDIF - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[4672];
  __IO uint32_t FRAMEBUFFERCONFIG0;                /**< Frame Buffer Configuration 0, offset: 0x1240 */
       uint8_t RESERVED_1[28];
  __IO uint32_t FRAMEBUFFERADDRESS0;               /**< Starting Address of the Frame Buffer, offset: 0x1260 */
       uint8_t RESERVED_2[28];
  __IO uint32_t FRAMEBUFFERSTRIDE0;                /**< Stride of the Frame Buffer in Bytes, offset: 0x1280 */
       uint8_t RESERVED_3[220];
  __IO uint32_t DISPLAYDITHERCONFIG0;              /**< Configuration for Dithering, offset: 0x1360 */
       uint8_t RESERVED_4[28];
  __IO uint32_t DISPLAYDITHERTABLELOW0;            /**< Dither Table Low, offset: 0x1380 */
       uint8_t RESERVED_5[28];
  __IO uint32_t DISPLAYDITHERTABLEHIGH0;           /**< Dither Table High, offset: 0x13A0 */
       uint8_t RESERVED_6[28];
  __IO uint32_t PANELCONFIG0;                      /**< Panel Configuration, offset: 0x13C0 */
       uint8_t RESERVED_7[28];
  __IO uint32_t PANELTIMING0;                      /**< Timing for Hardware Panel Sequencing, offset: 0x13E0 */
       uint8_t RESERVED_8[28];
  __IO uint32_t HDISPLAY0;                         /**< Horizontal Total and Display End Counters, offset: 0x1400 */
       uint8_t RESERVED_9[28];
  __IO uint32_t HSYNC0;                            /**< Horizontal Sync Counters, offset: 0x1420 */
       uint8_t RESERVED_10[92];
  __IO uint32_t VDISPLAY0;                         /**< Vertical Total and Display End Counters, offset: 0x1480 */
       uint8_t RESERVED_11[28];
  __IO uint32_t VSYNC0;                            /**< Vertical Sync Counters, offset: 0x14A0 */
       uint8_t RESERVED_12[28];
  __I  uint32_t DISPLAYCURRENTLOCATION0;           /**< Current x,y Location of Display Controller, offset: 0x14C0 */
       uint8_t RESERVED_13[28];
  __IO uint32_t GAMMAINDEX0;                       /**< Index into Gamma Table, offset: 0x14E0 */
       uint8_t RESERVED_14[28];
  __IO uint32_t GAMMADATA0;                        /**< Translation Values for the Gamma Table, offset: 0x1500 */
       uint8_t RESERVED_15[28];
  __IO uint32_t CURSORCONFIG;                      /**< Configuration for the Cursor, offset: 0x1520 */
       uint8_t RESERVED_16[12];
  __IO uint32_t CURSORADDRESS;                     /**< Address of the Cursor Shape, offset: 0x1530 */
       uint8_t RESERVED_17[12];
  __IO uint32_t CURSORLOCATION;                    /**< Location of the cursor on the owning display, offset: 0x1540 */
       uint8_t RESERVED_18[12];
  __IO uint32_t CURSORBACKGROUND;                  /**< Background Color for Masked Cursors, offset: 0x1550 */
       uint8_t RESERVED_19[12];
  __IO uint32_t CURSORFOREGROUND;                  /**< Foreground Color for Masked Cursors, offset: 0x1560 */
       uint8_t RESERVED_20[156];
  __IO uint32_t DISPLAYINTR;                       /**< Display Interrupt, offset: 0x1600 */
       uint8_t RESERVED_21[12];
  __IO uint32_t DISPLAYINTRENABLE;                 /**< Interrupt Enable for Display_0 (and Display_1 if present), offset: 0x1610 */
       uint8_t RESERVED_22[12];
  __IO uint32_t DBICONFIG0;                        /**< DBI Configuration 0, offset: 0x1620 */
       uint8_t RESERVED_23[28];
  __O  uint32_t DBIIFRESET0;                       /**< Reset DBI Interface to Idle State, offset: 0x1640 */
       uint8_t RESERVED_24[28];
  __IO uint32_t DBIWRCHAR10;                       /**< DBI Write Characteristics 1, offset: 0x1660 */
       uint8_t RESERVED_25[28];
  __IO uint32_t DBIWRCHAR20;                       /**< DBI Write Characteristics 2, offset: 0x1680 */
       uint8_t RESERVED_26[28];
  __O  uint32_t DBICMD0;                           /**< DBI Command In/Out Port, offset: 0x16A0 */
       uint8_t RESERVED_27[28];
  __IO uint32_t DPICONFIG0;                        /**< DPI Configuration 0, offset: 0x16C0 */
       uint8_t RESERVED_28[44];
  __I  uint32_t DCCHIPREV;                         /**< Revision for the LCDIF Peripheral in BCD, offset: 0x16F0 */
       uint8_t RESERVED_29[12];
  __I  uint32_t DCCHIPDATE;                        /**< Shows the release date for the IP in YYYYMMDD (year, month), offset: 0x1700 */
       uint8_t RESERVED_30[28];
  __I  uint32_t DCCHIPPATCHREV;                    /**< Patch Revision, offset: 0x1720 */
       uint8_t RESERVED_31[28];
  __IO uint32_t DCTILEINCFG0;                      /**< Tile Input Configuration, offset: 0x1740 */
       uint8_t RESERVED_32[28];
  __IO uint32_t DCTILEUVFRAMEBUFFERADR0;           /**< UV Frame Buffer Address when Tile Input, offset: 0x1760 */
       uint8_t RESERVED_33[28];
  __IO uint32_t DCTILEUVFRAMEBUFFERSTR0;           /**< UV Frame Buffer Stride when Tile Input, offset: 0x1780 */
       uint8_t RESERVED_34[44];
  __I  uint32_t DCPRODUCTID;                       /**< Product ID, offset: 0x17B0 */
       uint8_t RESERVED_35[76];
  __IO uint32_t DCSTATUS0;                         /**< DC Status 0, offset: 0x1800 */
       uint8_t RESERVED_36[28];
  __IO uint32_t DEBUGCOUNTERSELECT0;               /**< Debug Counter Select, offset: 0x1820 */
       uint8_t RESERVED_37[28];
  __IO uint32_t DEBUGCOUNTERVALUE0;                /**< Debug Counter Value, offset: 0x1840 */
} LCDIF_Type;

/* ----------------------------------------------------------------------------
   -- LCDIF Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
 * @{
 */

/*! @name FRAMEBUFFERCONFIG0 - Frame Buffer Configuration 0 */
/*! @{ */

#define LCDIF_FRAMEBUFFERCONFIG0_FORMAT_MASK     (0x7U)
#define LCDIF_FRAMEBUFFERCONFIG0_FORMAT_SHIFT    (0U)
/*! FORMAT - The format of the frame buffer. */
#define LCDIF_FRAMEBUFFERCONFIG0_FORMAT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_FORMAT_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_FORMAT_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_MODE_MASK       (0x10U)
#define LCDIF_FRAMEBUFFERCONFIG0_MODE_SHIFT      (4U)
/*! MODE - Mode of the frame buffer.
 *  0b0..LINEAR
 *  0b1..TILE4x4 INPUT
 */
#define LCDIF_FRAMEBUFFERCONFIG0_MODE(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_MODE_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_MODE_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_OUTPUT_MASK     (0x100U)
#define LCDIF_FRAMEBUFFERCONFIG0_OUTPUT_SHIFT    (8U)
/*! OUTPUT - Output
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LCDIF_FRAMEBUFFERCONFIG0_OUTPUT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_OUTPUT_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_OUTPUT_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL_MASK (0x200U)
#define LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL_SHIFT (9U)
/*! SWITCHPANEL - Switch Panel
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_GAMMA_MASK      (0x1000U)
#define LCDIF_FRAMEBUFFERCONFIG0_GAMMA_SHIFT     (12U)
/*! GAMMA - Gamma
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LCDIF_FRAMEBUFFERCONFIG0_GAMMA(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_GAMMA_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_GAMMA_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_VALID_MASK      (0x10000U)
#define LCDIF_FRAMEBUFFERCONFIG0_VALID_SHIFT     (16U)
/*! VALID - Valid
 *  0b0..Working
 *  0b1..Pending
 */
#define LCDIF_FRAMEBUFFERCONFIG0_VALID(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_VALID_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_VALID_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_RESET_MASK      (0x100000U)
#define LCDIF_FRAMEBUFFERCONFIG0_RESET_SHIFT     (20U)
/*! RESET - Reset
 *  0b0..For DBI, this field should be = 0.
 *  0b1..Enable DPI Timing, start a DPI transfer.
 */
#define LCDIF_FRAMEBUFFERCONFIG0_RESET(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_RESET_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_RESET_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW_MASK  (0x1000000U)
#define LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW_SHIFT (24U)
/*! UNDERFLOW - Underflow
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS_MASK (0x10000000U)
#define LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS_SHIFT (28U)
/*! FLIP_IN_PROGRESS - Flip in Progress
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS_MASK)

#define LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE_MASK (0x20000000U)
#define LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE_SHIFT (29U)
/*! BACK_PRESSURE_DISABLE - Disable Back Pressure
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE_MASK)
/*! @} */

/*! @name FRAMEBUFFERADDRESS0 - Starting Address of the Frame Buffer */
/*! @{ */

#define LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_MASK   (0x7FFFFFFFU)
#define LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_SHIFT  (0U)
/*! ADDRESS - Address */
#define LCDIF_FRAMEBUFFERADDRESS0_ADDRESS(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_SHIFT)) & LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_MASK)

#define LCDIF_FRAMEBUFFERADDRESS0_TYPE_MASK      (0x80000000U)
#define LCDIF_FRAMEBUFFERADDRESS0_TYPE_SHIFT     (31U)
/*! TYPE - System Type
 *  0b0..System
 *  0b1..Virtual system
 */
#define LCDIF_FRAMEBUFFERADDRESS0_TYPE(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERADDRESS0_TYPE_SHIFT)) & LCDIF_FRAMEBUFFERADDRESS0_TYPE_MASK)
/*! @} */

/*! @name FRAMEBUFFERSTRIDE0 - Stride of the Frame Buffer in Bytes */
/*! @{ */

#define LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_MASK     (0x1FFFFU)
#define LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_SHIFT    (0U)
/*! STRIDE - Number of bytes from start of one line to next line. This value needs to be 128 byte aligned. */
#define LCDIF_FRAMEBUFFERSTRIDE0_STRIDE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_SHIFT)) & LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_MASK)
/*! @} */

/*! @name DISPLAYDITHERCONFIG0 - Configuration for Dithering */
/*! @{ */

#define LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE_MASK (0xFU)
#define LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE_SHIFT (0U)
/*! BLUE_SIZE - Blue Size */
#define LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE_SHIFT)) & LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE_MASK)

#define LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE_MASK (0xF00U)
#define LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE_SHIFT (8U)
/*! GREEN_SIZE - Green Size */
#define LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE_SHIFT)) & LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE_MASK)

#define LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE_MASK (0xF0000U)
#define LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE_SHIFT (16U)
/*! RED_SIZE - Red Size */
#define LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE_SHIFT)) & LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE_MASK)

#define LCDIF_DISPLAYDITHERCONFIG0_ENABLE_MASK   (0x80000000U)
#define LCDIF_DISPLAYDITHERCONFIG0_ENABLE_SHIFT  (31U)
/*! ENABLE - Enable Dithering
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LCDIF_DISPLAYDITHERCONFIG0_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERCONFIG0_ENABLE_SHIFT)) & LCDIF_DISPLAYDITHERCONFIG0_ENABLE_MASK)
/*! @} */

/*! @name DISPLAYDITHERTABLELOW0 - Dither Table Low */
/*! @{ */

#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_MASK  (0xFU)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_SHIFT (0U)
/*! Y0_X0 - Dither threshold value for x,y=0,0. */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_MASK  (0xF0U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_SHIFT (4U)
/*! Y0_X1 - Dither threshold value for x,y=1,0. */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_MASK  (0xF00U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_SHIFT (8U)
/*! Y0_X2 - Dither threshold value for x,y=2,0. */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_MASK  (0xF000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_SHIFT (12U)
/*! Y0_X3 - Dither threshold value for x,y=3,0. */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_MASK  (0xF0000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_SHIFT (16U)
/*! Y1_X0 - Dither threshold value for x,y=0,1. */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_MASK  (0xF00000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_SHIFT (20U)
/*! Y1_X1 - Dither threshold value for x,y=1,1. */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_MASK  (0xF000000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_SHIFT (24U)
/*! Y1_X2 - Dither threshold value for x,y=2,1. */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_MASK)

#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_MASK  (0xF0000000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_SHIFT (28U)
/*! Y1_X3 - Dither threshold value for x,y=3,1. */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_MASK)
/*! @} */

/*! @name DISPLAYDITHERTABLEHIGH0 - Dither Table High */
/*! @{ */

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_MASK (0xFU)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_SHIFT (0U)
/*! Y2_X0 - Dither threshold value for x,y=0,2. */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_MASK (0xF0U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_SHIFT (4U)
/*! Y2_X1 - Dither threshold value for x,y=1,2. */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_MASK (0xF00U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_SHIFT (8U)
/*! Y2_X2 - Dither threshold value for x,y=2,2. */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_MASK (0xF000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_SHIFT (12U)
/*! Y2_X3 - Dither threshold value for x,y=3,2. */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_MASK (0xF0000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_SHIFT (16U)
/*! Y3_X0 - Dither threshold value for x,y=0,3. */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_MASK (0xF00000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_SHIFT (20U)
/*! Y3_X1 - Dither threshold value for x,y=1,3. */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_MASK (0xF000000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_SHIFT (24U)
/*! Y3_X2 - Dither threshold value for x,y=2,3. */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_MASK)

#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_MASK (0xF0000000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_SHIFT (28U)
/*! Y3_X3 - Dither threshold value for x,y=3,3. */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_MASK)
/*! @} */

/*! @name PANELCONFIG0 - Panel Configuration */
/*! @{ */

#define LCDIF_PANELCONFIG0_DE_MASK               (0x1U)
#define LCDIF_PANELCONFIG0_DE_SHIFT              (0U)
/*! DE - Data Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LCDIF_PANELCONFIG0_DE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_DE_SHIFT)) & LCDIF_PANELCONFIG0_DE_MASK)

#define LCDIF_PANELCONFIG0_DE_POLARITY_MASK      (0x2U)
#define LCDIF_PANELCONFIG0_DE_POLARITY_SHIFT     (1U)
/*! DE_POLARITY - Data Enable Polarity
 *  0b0..Positive
 *  0b1..Negative
 */
#define LCDIF_PANELCONFIG0_DE_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_DE_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_DE_POLARITY_MASK)

#define LCDIF_PANELCONFIG0_DATA_POLARITY_MASK    (0x20U)
#define LCDIF_PANELCONFIG0_DATA_POLARITY_SHIFT   (5U)
/*! DATA_POLARITY - Data Polarity
 *  0b0..Positive
 *  0b1..Negative
 */
#define LCDIF_PANELCONFIG0_DATA_POLARITY(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_DATA_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_DATA_POLARITY_MASK)

#define LCDIF_PANELCONFIG0_CLOCK_MASK            (0x100U)
#define LCDIF_PANELCONFIG0_CLOCK_SHIFT           (8U)
/*! CLOCK - Clock Enable/Disable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LCDIF_PANELCONFIG0_CLOCK(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_CLOCK_SHIFT)) & LCDIF_PANELCONFIG0_CLOCK_MASK)

#define LCDIF_PANELCONFIG0_CLOCK_POLARITY_MASK   (0x200U)
#define LCDIF_PANELCONFIG0_CLOCK_POLARITY_SHIFT  (9U)
/*! CLOCK_POLARITY - Clock Polarity
 *  0b0..Positive
 *  0b1..Negative
 */
#define LCDIF_PANELCONFIG0_CLOCK_POLARITY(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_CLOCK_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_CLOCK_POLARITY_MASK)

#define LCDIF_PANELCONFIG0_SEQUENCING_MASK       (0x80000000U)
#define LCDIF_PANELCONFIG0_SEQUENCING_SHIFT      (31U)
/*! SEQUENCING - Enable software or hardware panel sequencing.
 *  0b0..Hardware
 *  0b1..Software
 */
#define LCDIF_PANELCONFIG0_SEQUENCING(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_SEQUENCING_SHIFT)) & LCDIF_PANELCONFIG0_SEQUENCING_MASK)
/*! @} */

/*! @name PANELTIMING0 - Timing for Hardware Panel Sequencing */
/*! @{ */

#define LCDIF_PANELTIMING0_POWER_ENABLE_MASK     (0xFU)
#define LCDIF_PANELTIMING0_POWER_ENABLE_SHIFT    (0U)
/*! POWER_ENABLE - Number of VSYNCsto wait after power has been enabled. */
#define LCDIF_PANELTIMING0_POWER_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_POWER_ENABLE_SHIFT)) & LCDIF_PANELTIMING0_POWER_ENABLE_MASK)

#define LCDIF_PANELTIMING0_BACKLIGHT_ENABLE_MASK (0xF0U)
#define LCDIF_PANELTIMING0_BACKLIGHT_ENABLE_SHIFT (4U)
/*! BACKLIGHT_ENABLE - Number of VSYNCs to wait after backlight has been enabled. */
#define LCDIF_PANELTIMING0_BACKLIGHT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_BACKLIGHT_ENABLE_SHIFT)) & LCDIF_PANELTIMING0_BACKLIGHT_ENABLE_MASK)

#define LCDIF_PANELTIMING0_CLOCK_ENABLE_MASK     (0xF00U)
#define LCDIF_PANELTIMING0_CLOCK_ENABLE_SHIFT    (8U)
/*! CLOCK_ENABLE - Number of VSYNCs to wait after clock has been enabled. */
#define LCDIF_PANELTIMING0_CLOCK_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_CLOCK_ENABLE_SHIFT)) & LCDIF_PANELTIMING0_CLOCK_ENABLE_MASK)

#define LCDIF_PANELTIMING0_DATA_ENABLE_MASK      (0xF000U)
#define LCDIF_PANELTIMING0_DATA_ENABLE_SHIFT     (12U)
/*! DATA_ENABLE - Number of VSYNCs to wait after data has been enabled. */
#define LCDIF_PANELTIMING0_DATA_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_DATA_ENABLE_SHIFT)) & LCDIF_PANELTIMING0_DATA_ENABLE_MASK)

#define LCDIF_PANELTIMING0_DATA_DISABLE_MASK     (0xF0000U)
#define LCDIF_PANELTIMING0_DATA_DISABLE_SHIFT    (16U)
/*! DATA_DISABLE - Number of VSYNCs to wait after data has been disabled. */
#define LCDIF_PANELTIMING0_DATA_DISABLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_DATA_DISABLE_SHIFT)) & LCDIF_PANELTIMING0_DATA_DISABLE_MASK)

#define LCDIF_PANELTIMING0_CLOCK_DISABLE_MASK    (0xF00000U)
#define LCDIF_PANELTIMING0_CLOCK_DISABLE_SHIFT   (20U)
/*! CLOCK_DISABLE - Number of VSYNCs to wait after clock has been disabled. */
#define LCDIF_PANELTIMING0_CLOCK_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_CLOCK_DISABLE_SHIFT)) & LCDIF_PANELTIMING0_CLOCK_DISABLE_MASK)

#define LCDIF_PANELTIMING0_BACKLIGHT_DISABLE_MASK (0xF000000U)
#define LCDIF_PANELTIMING0_BACKLIGHT_DISABLE_SHIFT (24U)
/*! BACKLIGHT_DISABLE - Number of VSYNCs to wait after backlight has been disabled. */
#define LCDIF_PANELTIMING0_BACKLIGHT_DISABLE(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_BACKLIGHT_DISABLE_SHIFT)) & LCDIF_PANELTIMING0_BACKLIGHT_DISABLE_MASK)

#define LCDIF_PANELTIMING0_POWER_DISABLE_MASK    (0xF0000000U)
#define LCDIF_PANELTIMING0_POWER_DISABLE_SHIFT   (28U)
/*! POWER_DISABLE - Number of VSYNCs to wait after power has been disabled. */
#define LCDIF_PANELTIMING0_POWER_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_POWER_DISABLE_SHIFT)) & LCDIF_PANELTIMING0_POWER_DISABLE_MASK)
/*! @} */

/*! @name HDISPLAY0 - Horizontal Total and Display End Counters */
/*! @{ */

#define LCDIF_HDISPLAY0_DISPLAY_END_MASK         (0x1FFFU)
#define LCDIF_HDISPLAY0_DISPLAY_END_SHIFT        (0U)
/*! DISPLAY_END - Number of visible horizontal pixels. */
#define LCDIF_HDISPLAY0_DISPLAY_END(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_HDISPLAY0_DISPLAY_END_SHIFT)) & LCDIF_HDISPLAY0_DISPLAY_END_MASK)

#define LCDIF_HDISPLAY0_TOTAL_MASK               (0x1FFF0000U)
#define LCDIF_HDISPLAY0_TOTAL_SHIFT              (16U)
/*! TOTAL - Total number of horizontal pixels. */
#define LCDIF_HDISPLAY0_TOTAL(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_HDISPLAY0_TOTAL_SHIFT)) & LCDIF_HDISPLAY0_TOTAL_MASK)
/*! @} */

/*! @name HSYNC0 - Horizontal Sync Counters */
/*! @{ */

#define LCDIF_HSYNC0_START_MASK                  (0x1FFFU)
#define LCDIF_HSYNC0_START_SHIFT                 (0U)
/*! START - Start of horizontal sync pulse. */
#define LCDIF_HSYNC0_START(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_START_SHIFT)) & LCDIF_HSYNC0_START_MASK)

#define LCDIF_HSYNC0_END_MASK                    (0x1FFF0000U)
#define LCDIF_HSYNC0_END_SHIFT                   (16U)
/*! END - End of horizontal sync pulse. */
#define LCDIF_HSYNC0_END(x)                      (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_END_SHIFT)) & LCDIF_HSYNC0_END_MASK)

#define LCDIF_HSYNC0_PULSE_MASK                  (0x40000000U)
#define LCDIF_HSYNC0_PULSE_SHIFT                 (30U)
/*! PULSE - Horizontal sync pulse control.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LCDIF_HSYNC0_PULSE(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_PULSE_SHIFT)) & LCDIF_HSYNC0_PULSE_MASK)

#define LCDIF_HSYNC0_POLARITY_MASK               (0x80000000U)
#define LCDIF_HSYNC0_POLARITY_SHIFT              (31U)
/*! POLARITY - Polarity of the horizontal sync pulse
 *  0b0..Positive
 *  0b1..Negative
 */
#define LCDIF_HSYNC0_POLARITY(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_POLARITY_SHIFT)) & LCDIF_HSYNC0_POLARITY_MASK)
/*! @} */

/*! @name VDISPLAY0 - Vertical Total and Display End Counters */
/*! @{ */

#define LCDIF_VDISPLAY0_DISPLAY_END_MASK         (0xFFFU)
#define LCDIF_VDISPLAY0_DISPLAY_END_SHIFT        (0U)
/*! DISPLAY_END - Number of visible vertical lines. */
#define LCDIF_VDISPLAY0_DISPLAY_END(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDISPLAY0_DISPLAY_END_SHIFT)) & LCDIF_VDISPLAY0_DISPLAY_END_MASK)

#define LCDIF_VDISPLAY0_TOTAL_MASK               (0xFFF0000U)
#define LCDIF_VDISPLAY0_TOTAL_SHIFT              (16U)
/*! TOTAL - Total number of vertical lines. */
#define LCDIF_VDISPLAY0_TOTAL(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDISPLAY0_TOTAL_SHIFT)) & LCDIF_VDISPLAY0_TOTAL_MASK)
/*! @} */

/*! @name VSYNC0 - Vertical Sync Counters */
/*! @{ */

#define LCDIF_VSYNC0_START_MASK                  (0xFFFU)
#define LCDIF_VSYNC0_START_SHIFT                 (0U)
/*! START - Start of the vertical sync pulse. */
#define LCDIF_VSYNC0_START(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_START_SHIFT)) & LCDIF_VSYNC0_START_MASK)

#define LCDIF_VSYNC0_END_MASK                    (0xFFF0000U)
#define LCDIF_VSYNC0_END_SHIFT                   (16U)
/*! END - End of the vertical sync pulse. */
#define LCDIF_VSYNC0_END(x)                      (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_END_SHIFT)) & LCDIF_VSYNC0_END_MASK)

#define LCDIF_VSYNC0_PULSE_MASK                  (0x40000000U)
#define LCDIF_VSYNC0_PULSE_SHIFT                 (30U)
/*! PULSE - Vertical sync pulse control.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LCDIF_VSYNC0_PULSE(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_PULSE_SHIFT)) & LCDIF_VSYNC0_PULSE_MASK)

#define LCDIF_VSYNC0_POLARITY_MASK               (0x80000000U)
#define LCDIF_VSYNC0_POLARITY_SHIFT              (31U)
/*! POLARITY - Polarity of the vertical sync pulse.
 *  0b0..Positive
 *  0b1..Active-low
 */
#define LCDIF_VSYNC0_POLARITY(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_POLARITY_SHIFT)) & LCDIF_VSYNC0_POLARITY_MASK)
/*! @} */

/*! @name DISPLAYCURRENTLOCATION0 - Current x,y Location of Display Controller */
/*! @{ */

#define LCDIF_DISPLAYCURRENTLOCATION0_X_MASK     (0xFFFFU)
#define LCDIF_DISPLAYCURRENTLOCATION0_X_SHIFT    (0U)
/*! X - Current X location. */
#define LCDIF_DISPLAYCURRENTLOCATION0_X(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYCURRENTLOCATION0_X_SHIFT)) & LCDIF_DISPLAYCURRENTLOCATION0_X_MASK)

#define LCDIF_DISPLAYCURRENTLOCATION0_Y_MASK     (0xFFFF0000U)
#define LCDIF_DISPLAYCURRENTLOCATION0_Y_SHIFT    (16U)
/*! Y - Current Y location. */
#define LCDIF_DISPLAYCURRENTLOCATION0_Y(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYCURRENTLOCATION0_Y_SHIFT)) & LCDIF_DISPLAYCURRENTLOCATION0_Y_MASK)
/*! @} */

/*! @name GAMMAINDEX0 - Index into Gamma Table */
/*! @{ */

#define LCDIF_GAMMAINDEX0_INDEX_MASK             (0xFFU)
#define LCDIF_GAMMAINDEX0_INDEX_SHIFT            (0U)
/*! INDEX - Index into Gamma Table. */
#define LCDIF_GAMMAINDEX0_INDEX(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMAINDEX0_INDEX_SHIFT)) & LCDIF_GAMMAINDEX0_INDEX_MASK)
/*! @} */

/*! @name GAMMADATA0 - Translation Values for the Gamma Table */
/*! @{ */

#define LCDIF_GAMMADATA0_BLUE_MASK               (0xFFU)
#define LCDIF_GAMMADATA0_BLUE_SHIFT              (0U)
/*! BLUE - Blue translation value. */
#define LCDIF_GAMMADATA0_BLUE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMADATA0_BLUE_SHIFT)) & LCDIF_GAMMADATA0_BLUE_MASK)

#define LCDIF_GAMMADATA0_GREEN_MASK              (0xFF00U)
#define LCDIF_GAMMADATA0_GREEN_SHIFT             (8U)
/*! GREEN - Green translation value. */
#define LCDIF_GAMMADATA0_GREEN(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMADATA0_GREEN_SHIFT)) & LCDIF_GAMMADATA0_GREEN_MASK)

#define LCDIF_GAMMADATA0_RED_MASK                (0xFF0000U)
#define LCDIF_GAMMADATA0_RED_SHIFT               (16U)
/*! RED - Red translation value. */
#define LCDIF_GAMMADATA0_RED(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMADATA0_RED_SHIFT)) & LCDIF_GAMMADATA0_RED_MASK)
/*! @} */

/*! @name CURSORCONFIG - Configuration for the Cursor */
/*! @{ */

#define LCDIF_CURSORCONFIG_FORMAT_MASK           (0x3U)
#define LCDIF_CURSORCONFIG_FORMAT_SHIFT          (0U)
/*! FORMAT - Format of the cursor.
 *  0b00..DISABLED
 *  0b01..MASKED
 *  0b10..A8R8G8B8
 */
#define LCDIF_CURSORCONFIG_FORMAT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_FORMAT_SHIFT)) & LCDIF_CURSORCONFIG_FORMAT_MASK)

#define LCDIF_CURSORCONFIG_DISPLAY_MASK          (0x10U)
#define LCDIF_CURSORCONFIG_DISPLAY_SHIFT         (4U)
/*! DISPLAY - Display Controller owning the cursor.
 *  0b0..DISPLAY0
 *  0b1..DISPLAY1
 */
#define LCDIF_CURSORCONFIG_DISPLAY(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_DISPLAY_SHIFT)) & LCDIF_CURSORCONFIG_DISPLAY_MASK)

#define LCDIF_CURSORCONFIG_HOT_SPOT_Y_MASK       (0x1F00U)
#define LCDIF_CURSORCONFIG_HOT_SPOT_Y_SHIFT      (8U)
/*! HOT_SPOT_Y - Vertical offset to cursor hotspot. */
#define LCDIF_CURSORCONFIG_HOT_SPOT_Y(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_HOT_SPOT_Y_SHIFT)) & LCDIF_CURSORCONFIG_HOT_SPOT_Y_MASK)

#define LCDIF_CURSORCONFIG_HOT_SPOT_X_MASK       (0x1F0000U)
#define LCDIF_CURSORCONFIG_HOT_SPOT_X_SHIFT      (16U)
/*! HOT_SPOT_X - Horizontal offset to cursor hotspot. */
#define LCDIF_CURSORCONFIG_HOT_SPOT_X(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_HOT_SPOT_X_SHIFT)) & LCDIF_CURSORCONFIG_HOT_SPOT_X_MASK)

#define LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS_MASK (0x80000000U)
#define LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS_SHIFT (31U)
/*! FLIP_IN_PROGRESS - When the cursor address gets written to, this bit gets set to one. */
#define LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS_SHIFT)) & LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS_MASK)
/*! @} */

/*! @name CURSORADDRESS - Address of the Cursor Shape */
/*! @{ */

#define LCDIF_CURSORADDRESS_ADDRESS_MASK         (0x7FFFFFFFU)
#define LCDIF_CURSORADDRESS_ADDRESS_SHIFT        (0U)
/*! ADDRESS - ADDRESS */
#define LCDIF_CURSORADDRESS_ADDRESS(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORADDRESS_ADDRESS_SHIFT)) & LCDIF_CURSORADDRESS_ADDRESS_MASK)

#define LCDIF_CURSORADDRESS_TYPE_MASK            (0x80000000U)
#define LCDIF_CURSORADDRESS_TYPE_SHIFT           (31U)
/*! TYPE - System Type
 *  0b0..System.
 *  0b1..Virtual system.
 */
#define LCDIF_CURSORADDRESS_TYPE(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORADDRESS_TYPE_SHIFT)) & LCDIF_CURSORADDRESS_TYPE_MASK)
/*! @} */

/*! @name CURSORLOCATION - Location of the cursor on the owning display */
/*! @{ */

#define LCDIF_CURSORLOCATION_X_MASK              (0x1FFFU)
#define LCDIF_CURSORLOCATION_X_SHIFT             (0U)
/*! X - X location of cursor's hotspot. */
#define LCDIF_CURSORLOCATION_X(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORLOCATION_X_SHIFT)) & LCDIF_CURSORLOCATION_X_MASK)

#define LCDIF_CURSORLOCATION_Y_MASK              (0xFFF0000U)
#define LCDIF_CURSORLOCATION_Y_SHIFT             (16U)
/*! Y - Y location of cursor's hotspot. */
#define LCDIF_CURSORLOCATION_Y(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORLOCATION_Y_SHIFT)) & LCDIF_CURSORLOCATION_Y_MASK)
/*! @} */

/*! @name CURSORBACKGROUND - Background Color for Masked Cursors */
/*! @{ */

#define LCDIF_CURSORBACKGROUND_BLUE_MASK         (0xFFU)
#define LCDIF_CURSORBACKGROUND_BLUE_SHIFT        (0U)
/*! BLUE - Blue value */
#define LCDIF_CURSORBACKGROUND_BLUE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORBACKGROUND_BLUE_SHIFT)) & LCDIF_CURSORBACKGROUND_BLUE_MASK)

#define LCDIF_CURSORBACKGROUND_GREEN_MASK        (0xFF00U)
#define LCDIF_CURSORBACKGROUND_GREEN_SHIFT       (8U)
/*! GREEN - Green value */
#define LCDIF_CURSORBACKGROUND_GREEN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORBACKGROUND_GREEN_SHIFT)) & LCDIF_CURSORBACKGROUND_GREEN_MASK)

#define LCDIF_CURSORBACKGROUND_RED_MASK          (0xFF0000U)
#define LCDIF_CURSORBACKGROUND_RED_SHIFT         (16U)
/*! RED - Red value */
#define LCDIF_CURSORBACKGROUND_RED(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORBACKGROUND_RED_SHIFT)) & LCDIF_CURSORBACKGROUND_RED_MASK)
/*! @} */

/*! @name CURSORFOREGROUND - Foreground Color for Masked Cursors */
/*! @{ */

#define LCDIF_CURSORFOREGROUND_BLUE_MASK         (0xFFU)
#define LCDIF_CURSORFOREGROUND_BLUE_SHIFT        (0U)
/*! BLUE - Blue value */
#define LCDIF_CURSORFOREGROUND_BLUE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORFOREGROUND_BLUE_SHIFT)) & LCDIF_CURSORFOREGROUND_BLUE_MASK)

#define LCDIF_CURSORFOREGROUND_GREEN_MASK        (0xFF00U)
#define LCDIF_CURSORFOREGROUND_GREEN_SHIFT       (8U)
/*! GREEN - Green value */
#define LCDIF_CURSORFOREGROUND_GREEN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORFOREGROUND_GREEN_SHIFT)) & LCDIF_CURSORFOREGROUND_GREEN_MASK)

#define LCDIF_CURSORFOREGROUND_RED_MASK          (0xFF0000U)
#define LCDIF_CURSORFOREGROUND_RED_SHIFT         (16U)
/*! RED - Red value */
#define LCDIF_CURSORFOREGROUND_RED(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORFOREGROUND_RED_SHIFT)) & LCDIF_CURSORFOREGROUND_RED_MASK)
/*! @} */

/*! @name DISPLAYINTR - Display Interrupt */
/*! @{ */

#define LCDIF_DISPLAYINTR_DISP0_MASK             (0x1U)
#define LCDIF_DISPLAYINTR_DISP0_SHIFT            (0U)
/*! DISP0 - Display0 Interrupt */
#define LCDIF_DISPLAYINTR_DISP0(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTR_DISP0_SHIFT)) & LCDIF_DISPLAYINTR_DISP0_MASK)
/*! @} */

/*! @name DISPLAYINTRENABLE - Interrupt Enable for Display_0 (and Display_1 if present) */
/*! @{ */

#define LCDIF_DISPLAYINTRENABLE_DISP0_MASK       (0x1U)
#define LCDIF_DISPLAYINTRENABLE_DISP0_SHIFT      (0U)
/*! DISP0 - Display0 Interrupt Enable */
#define LCDIF_DISPLAYINTRENABLE_DISP0(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTRENABLE_DISP0_SHIFT)) & LCDIF_DISPLAYINTRENABLE_DISP0_MASK)
/*! @} */

/*! @name DBICONFIG0 - DBI Configuration 0 */
/*! @{ */

#define LCDIF_DBICONFIG0_DBI_TYPE_MASK           (0x3U)
#define LCDIF_DBICONFIG0_DBI_TYPE_SHIFT          (0U)
/*! DBI_TYPE - DBI Type Select
 *  0b00..TYPE_AFIXED_E
 *  0b01..TYPE_ACLOCK_E
 *  0b10..TYPE_B
 *  0b11..TYPE_C
 */
#define LCDIF_DBICONFIG0_DBI_TYPE(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_TYPE_SHIFT)) & LCDIF_DBICONFIG0_DBI_TYPE_MASK)

#define LCDIF_DBICONFIG0_DBI_DATA_FORMAT_MASK    (0x3CU)
#define LCDIF_DBICONFIG0_DBI_DATA_FORMAT_SHIFT   (2U)
/*! DBI_DATA_FORMAT - DBI Interface Data Format. */
#define LCDIF_DBICONFIG0_DBI_DATA_FORMAT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_DATA_FORMAT_SHIFT)) & LCDIF_DBICONFIG0_DBI_DATA_FORMAT_MASK)

#define LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_MASK     (0x40U)
#define LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_SHIFT    (6U)
/*! BUS_OUTPUT_SEL - Output Bus Select
 *  0b0..DPI
 *  0b1..DBI
 */
#define LCDIF_DBICONFIG0_BUS_OUTPUT_SEL(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_SHIFT)) & LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_MASK)

#define LCDIF_DBICONFIG0_DBIX_POLARITY_MASK      (0x80U)
#define LCDIF_DBICONFIG0_DBIX_POLARITY_SHIFT     (7U)
/*! DBIX_POLARITY - D/CX Pin polarity.
 *  0b0..Default
 *  0b1..Reverse
 */
#define LCDIF_DBICONFIG0_DBIX_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBIX_POLARITY_SHIFT)) & LCDIF_DBICONFIG0_DBIX_POLARITY_MASK)

#define LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_MASK   (0xF00U)
#define LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_SHIFT  (8U)
/*! DBI_AC_TIME_UNIT - Time Unit for AC Characteristics */
#define LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_SHIFT)) & LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_MASK)

#define LCDIF_DBICONFIG0_DBI_TYPEC_OPT_MASK      (0x3000U)
#define LCDIF_DBICONFIG0_DBI_TYPEC_OPT_SHIFT     (12U)
/*! DBI_TYPEC_OPT - Options for DBI Type C Interface Read/Write Sequence
 *  0b00..Option 1
 *  0b01..Option 2
 *  0b10..Option 3
 *  0b11..
 */
#define LCDIF_DBICONFIG0_DBI_TYPEC_OPT(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_TYPEC_OPT_SHIFT)) & LCDIF_DBICONFIG0_DBI_TYPEC_OPT_MASK)
/*! @} */

/*! @name DBIIFRESET0 - Reset DBI Interface to Idle State */
/*! @{ */

#define LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_MASK (0x1U)
#define LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_SHIFT (0U)
/*! DBI_IF_LEVEL_RESET - Reset DBI interface to idle state 1=RESET; */
#define LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_SHIFT)) & LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_MASK)
/*! @} */

/*! @name DBIWRCHAR10 - DBI Write Characteristics 1 */
/*! @{ */

#define LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_MASK     (0xFFU)
#define LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_SHIFT    (0U)
/*! DBI_WR_PERIOD - Single Write Period Duration */
#define LCDIF_DBIWRCHAR10_DBI_WR_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_SHIFT)) & LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_MASK)

#define LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_MASK (0xF00U)
#define LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_SHIFT (8U)
/*! DBI_WR_EOR_WR_ASSERT - Cycle number=Setting*(DbiAcTimeUnit+1). */
#define LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_SHIFT)) & LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_MASK)

#define LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_MASK  (0xF000U)
#define LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_SHIFT (12U)
/*! DBI_WR_CS_ASSERT - Cycle number=Setting*(DbiAcTimeUnit+1). */
#define LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_SHIFT)) & LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_MASK)
/*! @} */

/*! @name DBIWRCHAR20 - DBI Write Characteristics 2 */
/*! @{ */

#define LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_MASK (0xFFU)
#define LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_SHIFT (0U)
/*! DBI_WR_EOR_WR_DE_ASRT - Cycle number=Setting*(DbiAcTimeUnit+1). */
#define LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_SHIFT)) & LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_MASK)

#define LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_MASK (0xFF00U)
#define LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_SHIFT (8U)
/*! DBI_WR_CS_DE_ASRT - Cycle number=Setting*(DbiAcTimeUnit+1). */
#define LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_SHIFT)) & LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_MASK)
/*! @} */

/*! @name DBICMD0 - DBI Command In/Out Port */
/*! @{ */

#define LCDIF_DBICMD0_DBI_COMMAND_WORD_MASK      (0xFFFFU)
#define LCDIF_DBICMD0_DBI_COMMAND_WORD_SHIFT     (0U)
/*! DBI_COMMAND_WORD - DBI Command Word */
#define LCDIF_DBICMD0_DBI_COMMAND_WORD(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICMD0_DBI_COMMAND_WORD_SHIFT)) & LCDIF_DBICMD0_DBI_COMMAND_WORD_MASK)

#define LCDIF_DBICMD0_DBI_COMMANDFLAG_MASK       (0xC0000000U)
#define LCDIF_DBICMD0_DBI_COMMANDFLAG_SHIFT      (30U)
/*! DBI_COMMANDFLAG - DBI Command Flag
 *  0b00..ADDRESS
 *  0b01..WRITE_MEM_START
 *  0b10..PARAMETER_OR_DATA
 *  0b11..Not used
 */
#define LCDIF_DBICMD0_DBI_COMMANDFLAG(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICMD0_DBI_COMMANDFLAG_SHIFT)) & LCDIF_DBICMD0_DBI_COMMANDFLAG_MASK)
/*! @} */

/*! @name DPICONFIG0 - DPI Configuration 0 */
/*! @{ */

#define LCDIF_DPICONFIG0_DPI_DATA_FORMAT_MASK    (0x7U)
#define LCDIF_DPICONFIG0_DPI_DATA_FORMAT_SHIFT   (0U)
/*! DPI_DATA_FORMAT - DPI Interface Data Format
 *  0b000..D16CFG1
 *  0b001..D16CFG2
 *  0b010..D16CFG3
 *  0b011..D18CFG1
 *  0b100..D18CFG2
 *  0b101..D24
 *  0b110-0b111..-
 */
#define LCDIF_DPICONFIG0_DPI_DATA_FORMAT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_DPICONFIG0_DPI_DATA_FORMAT_SHIFT)) & LCDIF_DPICONFIG0_DPI_DATA_FORMAT_MASK)
/*! @} */

/*! @name DCCHIPREV - Revision for the LCDIF Peripheral in BCD */
/*! @{ */

#define LCDIF_DCCHIPREV_REV_MASK                 (0xFFFFFFFFU)
#define LCDIF_DCCHIPREV_REV_SHIFT                (0U)
/*! REV - Revision */
#define LCDIF_DCCHIPREV_REV(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_DCCHIPREV_REV_SHIFT)) & LCDIF_DCCHIPREV_REV_MASK)
/*! @} */

/*! @name DCCHIPDATE - Shows the release date for the IP in YYYYMMDD (year, month) */
/*! @{ */

#define LCDIF_DCCHIPDATE_DATE_MASK               (0xFFFFFFFFU)
#define LCDIF_DCCHIPDATE_DATE_SHIFT              (0U)
/*! DATE - Date */
#define LCDIF_DCCHIPDATE_DATE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_DCCHIPDATE_DATE_SHIFT)) & LCDIF_DCCHIPDATE_DATE_MASK)
/*! @} */

/*! @name DCCHIPPATCHREV - Patch Revision */
/*! @{ */

#define LCDIF_DCCHIPPATCHREV_PATCH_REV_MASK      (0xFFFFFFFFU)
#define LCDIF_DCCHIPPATCHREV_PATCH_REV_SHIFT     (0U)
/*! PATCH_REV - Patch Revision */
#define LCDIF_DCCHIPPATCHREV_PATCH_REV(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DCCHIPPATCHREV_PATCH_REV_SHIFT)) & LCDIF_DCCHIPPATCHREV_PATCH_REV_MASK)
/*! @} */

/*! @name DCTILEINCFG0 - Tile Input Configuration */
/*! @{ */

#define LCDIF_DCTILEINCFG0_TILE_FORMAT_MASK      (0x3U)
#define LCDIF_DCTILEINCFG0_TILE_FORMAT_SHIFT     (0U)
/*! TILE_FORMAT - Tile Format */
#define LCDIF_DCTILEINCFG0_TILE_FORMAT(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_TILE_FORMAT_SHIFT)) & LCDIF_DCTILEINCFG0_TILE_FORMAT_MASK)

#define LCDIF_DCTILEINCFG0_YUV_STANDARD_MASK     (0xCU)
#define LCDIF_DCTILEINCFG0_YUV_STANDARD_SHIFT    (2U)
/*! YUV_STANDARD - YUV Standard Select
 *  0b00..BT601
 *  0b01..BT709
 */
#define LCDIF_DCTILEINCFG0_YUV_STANDARD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_YUV_STANDARD_SHIFT)) & LCDIF_DCTILEINCFG0_YUV_STANDARD_MASK)

#define LCDIF_DCTILEINCFG0_YUV2_RGB_EN_MASK      (0x10U)
#define LCDIF_DCTILEINCFG0_YUV2_RGB_EN_SHIFT     (4U)
/*! YUV2_RGB_EN - YUV2RGB Module Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LCDIF_DCTILEINCFG0_YUV2_RGB_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_YUV2_RGB_EN_SHIFT)) & LCDIF_DCTILEINCFG0_YUV2_RGB_EN_MASK)

#define LCDIF_DCTILEINCFG0_CFG_MODE_EN_MASK      (0x20U)
#define LCDIF_DCTILEINCFG0_CFG_MODE_EN_SHIFT     (5U)
/*! CFG_MODE_EN - Configuration Mode Enable.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LCDIF_DCTILEINCFG0_CFG_MODE_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_CFG_MODE_EN_SHIFT)) & LCDIF_DCTILEINCFG0_CFG_MODE_EN_MASK)
/*! @} */

/*! @name DCTILEUVFRAMEBUFFERADR0 - UV Frame Buffer Address when Tile Input */
/*! @{ */

#define LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_MASK (0xFFFFFFFFU)
#define LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_SHIFT (0U)
/*! ADDRESS - UV Frame Buffer Address when Tile Input */
#define LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_SHIFT)) & LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_MASK)
/*! @} */

/*! @name DCTILEUVFRAMEBUFFERSTR0 - UV Frame Buffer Stride when Tile Input */
/*! @{ */

#define LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_MASK (0xFFFFU)
#define LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_SHIFT (0U)
/*! STRIDE - UV Frame Buffer Stride when Tile Input */
#define LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_SHIFT)) & LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_MASK)
/*! @} */

/*! @name DCPRODUCTID - Product ID */
/*! @{ */

#define LCDIF_DCPRODUCTID_PRODUCT_ID_MASK        (0xFFFFFFFFU)
#define LCDIF_DCPRODUCTID_PRODUCT_ID_SHIFT       (0U)
/*! PRODUCT_ID - Product ID */
#define LCDIF_DCPRODUCTID_PRODUCT_ID(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_DCPRODUCTID_PRODUCT_ID_SHIFT)) & LCDIF_DCPRODUCTID_PRODUCT_ID_MASK)
/*! @} */

/*! @name DCSTATUS0 - DC Status 0 */
/*! @{ */

#define LCDIF_DCSTATUS0_DBI_TYPEC_FIFO_FULL_MASK (0x1U)
#define LCDIF_DCSTATUS0_DBI_TYPEC_FIFO_FULL_SHIFT (0U)
/*! DBI_TYPEC_FIFO_FULL - DBI Type C afifo full. */
#define LCDIF_DCSTATUS0_DBI_TYPEC_FIFO_FULL(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DCSTATUS0_DBI_TYPEC_FIFO_FULL_SHIFT)) & LCDIF_DCSTATUS0_DBI_TYPEC_FIFO_FULL_MASK)
/*! @} */

/*! @name DEBUGCOUNTERSELECT0 - Debug Counter Select */
/*! @{ */

#define LCDIF_DEBUGCOUNTERSELECT0_SELECT_MASK    (0xFFU)
#define LCDIF_DEBUGCOUNTERSELECT0_SELECT_SHIFT   (0U)
/*! SELECT - Select */
#define LCDIF_DEBUGCOUNTERSELECT0_SELECT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_DEBUGCOUNTERSELECT0_SELECT_SHIFT)) & LCDIF_DEBUGCOUNTERSELECT0_SELECT_MASK)
/*! @} */

/*! @name DEBUGCOUNTERVALUE0 - Debug Counter Value */
/*! @{ */

#define LCDIF_DEBUGCOUNTERVALUE0_VALUE_MASK      (0xFFFFFFFFU)
#define LCDIF_DEBUGCOUNTERVALUE0_VALUE_SHIFT     (0U)
/*! VALUE - Selected Debug Counter Value */
#define LCDIF_DEBUGCOUNTERVALUE0_VALUE(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DEBUGCOUNTERVALUE0_VALUE_SHIFT)) & LCDIF_DEBUGCOUNTERVALUE0_VALUE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LCDIF_Register_Masks */


/* LCDIF - Peripheral instance base addresses */
/** Peripheral LCDIF base address */
#define LCDIF_BASE                               (0x2E050000u)
/** Peripheral LCDIF base pointer */
#define LCDIF                                    ((LCDIF_Type *)LCDIF_BASE)
/** Array initializer of LCDIF peripheral base addresses */
#define LCDIF_BASE_ADDRS                         { LCDIF_BASE }
/** Array initializer of LCDIF peripheral base pointers */
#define LCDIF_BASE_PTRS                          { LCDIF }

/*!
 * @}
 */ /* end of group LCDIF_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPDDR Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPDDR_Peripheral_Access_Layer LPDDR Peripheral Access Layer
 * @{
 */

/** LPDDR - Register Layout Typedef */
typedef struct {
  __IO uint32_t DENALI_CTL[615];                   /**< DENALI_CTL_0..DENALI_CTL_614, array offset: 0x0, array step: 0x4, irregular array, not all indices are valid */
       uint8_t RESERVED_0[5732];
  __IO uint32_t DENALI_PI_0;                       /**< DENALI_PI_0, offset: 0x2000 */
       uint8_t RESERVED_1[8];
  __IO uint32_t DENALI_PI_3;                       /**< DENALI_PI_3, offset: 0x200C */
  __IO uint32_t DENALI_PI_4;                       /**< DENALI_PI_4, offset: 0x2010 */
  __IO uint32_t DENALI_PI_5;                       /**< DENALI_PI_5, offset: 0x2014 */
       uint8_t RESERVED_2[20];
  __IO uint32_t DENALI_PI_11;                      /**< DENALI_PI_11, offset: 0x202C */
  __IO uint32_t DENALI_PI_12;                      /**< DENALI_PI_12, offset: 0x2030 */
  __IO uint32_t DENALI_PI_13;                      /**< DENALI_PI_13, offset: 0x2034 */
  __IO uint32_t DENALI_PI_14;                      /**< DENALI_PI_14, offset: 0x2038 */
  __IO uint32_t DENALI_PI_15;                      /**< DENALI_PI_15, offset: 0x203C */
  __IO uint32_t DENALI_PI_16;                      /**< DENALI_PI_16, offset: 0x2040 */
       uint8_t RESERVED_3[48];
  __IO uint32_t DENALI_PI_29;                      /**< DENALI_PI_29, offset: 0x2074 */
       uint8_t RESERVED_4[56];
  __IO uint32_t DENALI_PI_44;                      /**< DENALI_PI_44, offset: 0x20B0 */
  __IO uint32_t DENALI_PI_45;                      /**< DENALI_PI_45, offset: 0x20B4 */
       uint8_t RESERVED_5[36];
  __IO uint32_t DENALI_PI_55;                      /**< DENALI_PI_55, offset: 0x20DC */
       uint8_t RESERVED_6[32];
  __IO uint32_t DENALI_PI_64;                      /**< DENALI_PI_64, offset: 0x2100 */
       uint8_t RESERVED_7[20];
  __IO uint32_t DENALI_PI_70;                      /**< DENALI_PI_70, offset: 0x2118 */
  __IO uint32_t DENALI_PI_71;                      /**< DENALI_PI_71, offset: 0x211C */
       uint8_t RESERVED_8[80];
  __IO uint32_t DENALI_PI_92;                      /**< DENALI_PI_92, offset: 0x2170 */
       uint8_t RESERVED_9[272];
  __IO uint32_t DENALI_PI_161;                     /**< DENALI_PI_161, offset: 0x2284 */
  __IO uint32_t DENALI_PI_162;                     /**< DENALI_PI_162, offset: 0x2288 */
  __IO uint32_t DENALI_PI_163;                     /**< DENALI_PI_163, offset: 0x228C */
  __IO uint32_t DENALI_PI_164;                     /**< DENALI_PI_164, offset: 0x2290 */
  __IO uint32_t DENALI_PI_165;                     /**< DENALI_PI_165, offset: 0x2294 */
  __IO uint32_t DENALI_PI_166;                     /**< DENALI_PI_166, offset: 0x2298 */
  __IO uint32_t DENALI_PI_167;                     /**< DENALI_PI_167, offset: 0x229C */
  __IO uint32_t DENALI_PI_168;                     /**< DENALI_PI_168, offset: 0x22A0 */
  __IO uint32_t DENALI_PI_169;                     /**< DENALI_PI_169, offset: 0x22A4 */
  __IO uint32_t DENALI_PI_170;                     /**< DENALI_PI_170, offset: 0x22A8 */
  __IO uint32_t DENALI_PI_171;                     /**< DENALI_PI_171, offset: 0x22AC */
  __IO uint32_t DENALI_PI_172;                     /**< DENALI_PI_172, offset: 0x22B0 */
  __IO uint32_t DENALI_PI_173;                     /**< DENALI_PI_173, offset: 0x22B4 */
  __IO uint32_t DENALI_PI_174;                     /**< DENALI_PI_174, offset: 0x22B8 */
  __IO uint32_t DENALI_PI_175;                     /**< DENALI_PI_175, offset: 0x22BC */
  __IO uint32_t DENALI_PI_176;                     /**< DENALI_PI_176, offset: 0x22C0 */
  __IO uint32_t DENALI_PI_177;                     /**< DENALI_PI_177, offset: 0x22C4 */
  __IO uint32_t DENALI_PI_178;                     /**< DENALI_PI_178, offset: 0x22C8 */
       uint8_t RESERVED_10[8];
  __IO uint32_t DENALI_PI_181;                     /**< DENALI_PI_181, offset: 0x22D4 */
  __IO uint32_t DENALI_PI_182;                     /**< DENALI_PI_182, offset: 0x22D8 */
       uint8_t RESERVED_11[12];
  __IO uint32_t DENALI_PI_186;                     /**< DENALI_PI_186, offset: 0x22E8 */
  __IO uint32_t DENALI_PI_187;                     /**< DENALI_PI_187, offset: 0x22EC */
  __IO uint32_t DENALI_PI_188;                     /**< DENALI_PI_188, offset: 0x22F0 */
  __IO uint32_t DENALI_PI_189;                     /**< DENALI_PI_189, offset: 0x22F4 */
  __IO uint32_t DENALI_PI_190;                     /**< DENALI_PI_190, offset: 0x22F8 */
  __IO uint32_t DENALI_PI_191;                     /**< DENALI_PI_191, offset: 0x22FC */
  __IO uint32_t DENALI_PI_192;                     /**< DENALI_PI_192, offset: 0x2300 */
  __IO uint32_t DENALI_PI_193;                     /**< DENALI_PI_193, offset: 0x2304 */
  __IO uint32_t DENALI_PI_194;                     /**< DENALI_PI_194, offset: 0x2308 */
  __IO uint32_t DENALI_PI_195;                     /**< DENALI_PI_195, offset: 0x230C */
  __IO uint32_t DENALI_PI_196;                     /**< DENALI_PI_196, offset: 0x2310 */
  __IO uint32_t DENALI_PI_197;                     /**< DENALI_PI_197, offset: 0x2314 */
  __IO uint32_t DENALI_PI_198;                     /**< DENALI_PI_198, offset: 0x2318 */
  __IO uint32_t DENALI_PI_199;                     /**< DENALI_PI_199, offset: 0x231C */
  __IO uint32_t DENALI_PI_200;                     /**< DENALI_PI_200, offset: 0x2320 */
  __IO uint32_t DENALI_PI_201;                     /**< DENALI_PI_201, offset: 0x2324 */
  __IO uint32_t DENALI_PI_202;                     /**< DENALI_PI_202, offset: 0x2328 */
  __IO uint32_t DENALI_PI_203;                     /**< DENALI_PI_203, offset: 0x232C */
  __IO uint32_t DENALI_PI_204;                     /**< DENALI_PI_204, offset: 0x2330 */
  __IO uint32_t DENALI_PI_205;                     /**< DENALI_PI_205, offset: 0x2334 */
  __IO uint32_t DENALI_PI_206;                     /**< DENALI_PI_206, offset: 0x2338 */
  __IO uint32_t DENALI_PI_207;                     /**< DENALI_PI_207, offset: 0x233C */
  __IO uint32_t DENALI_PI_208;                     /**< DENALI_PI_208, offset: 0x2340 */
  __IO uint32_t DENALI_PI_209;                     /**< DENALI_PI_209, offset: 0x2344 */
  __IO uint32_t DENALI_PI_210;                     /**< DENALI_PI_210, offset: 0x2348 */
  __IO uint32_t DENALI_PI_211;                     /**< DENALI_PI_211, offset: 0x234C */
  __IO uint32_t DENALI_PI_212;                     /**< DENALI_PI_212, offset: 0x2350 */
  __IO uint32_t DENALI_PI_213;                     /**< DENALI_PI_213, offset: 0x2354 */
  __IO uint32_t DENALI_PI_214;                     /**< DENALI_PI_214, offset: 0x2358 */
  __IO uint32_t DENALI_PI_215;                     /**< DENALI_PI_215, offset: 0x235C */
  __IO uint32_t DENALI_PI_216;                     /**< DENALI_PI_216, offset: 0x2360 */
  __IO uint32_t DENALI_PI_217;                     /**< DENALI_PI_217, offset: 0x2364 */
  __IO uint32_t DENALI_PI_218;                     /**< DENALI_PI_218, offset: 0x2368 */
  __IO uint32_t DENALI_PI_219;                     /**< DENALI_PI_219, offset: 0x236C */
  __IO uint32_t DENALI_PI_220;                     /**< DENALI_PI_220, offset: 0x2370 */
  __IO uint32_t DENALI_PI_221;                     /**< DENALI_PI_221, offset: 0x2374 */
  __IO uint32_t DENALI_PI_222;                     /**< DENALI_PI_222, offset: 0x2378 */
  __IO uint32_t DENALI_PI_223;                     /**< DENALI_PI_223, offset: 0x237C */
  __IO uint32_t DENALI_PI_224;                     /**< DENALI_PI_224, offset: 0x2380 */
  __IO uint32_t DENALI_PI_225;                     /**< DENALI_PI_225, offset: 0x2384 */
  __IO uint32_t DENALI_PI_226;                     /**< DENALI_PI_226, offset: 0x2388 */
  __IO uint32_t DENALI_PI_227;                     /**< DENALI_PI_227, offset: 0x238C */
  __IO uint32_t DENALI_PI_228;                     /**< DENALI_PI_228, offset: 0x2390 */
  __IO uint32_t DENALI_PI_229;                     /**< DENALI_PI_229, offset: 0x2394 */
  __IO uint32_t DENALI_PI_230;                     /**< DENALI_PI_230, offset: 0x2398 */
  __IO uint32_t DENALI_PI_231;                     /**< DENALI_PI_231, offset: 0x239C */
  __IO uint32_t DENALI_PI_232;                     /**< DENALI_PI_232, offset: 0x23A0 */
  __IO uint32_t DENALI_PI_233;                     /**< DENALI_PI_233, offset: 0x23A4 */
  __IO uint32_t DENALI_PI_234;                     /**< DENALI_PI_234, offset: 0x23A8 */
  __IO uint32_t DENALI_PI_235;                     /**< DENALI_PI_235, offset: 0x23AC */
  __IO uint32_t DENALI_PI_236;                     /**< DENALI_PI_236, offset: 0x23B0 */
  __IO uint32_t DENALI_PI_237;                     /**< DENALI_PI_237, offset: 0x23B4 */
  __IO uint32_t DENALI_PI_238;                     /**< DENALI_PI_238, offset: 0x23B8 */
  __IO uint32_t DENALI_PI_239;                     /**< DENALI_PI_239, offset: 0x23BC */
       uint8_t RESERVED_12[8];
  __IO uint32_t DENALI_PI_242;                     /**< DENALI_PI_242, offset: 0x23C8 */
  __IO uint32_t DENALI_PI_243;                     /**< DENALI_PI_243, offset: 0x23CC */
  __IO uint32_t DENALI_PI_244;                     /**< DENALI_PI_244, offset: 0x23D0 */
       uint8_t RESERVED_13[4];
  __IO uint32_t DENALI_PI_246;                     /**< DENALI_PI_246, offset: 0x23D8 */
  __IO uint32_t DENALI_PI_247;                     /**< DENALI_PI_247, offset: 0x23DC */
  __IO uint32_t DENALI_PI_248;                     /**< DENALI_PI_248, offset: 0x23E0 */
  __IO uint32_t DENALI_PI_249;                     /**< DENALI_PI_249, offset: 0x23E4 */
       uint8_t RESERVED_14[4];
  __IO uint32_t DENALI_PI_251;                     /**< DENALI_PI_251, offset: 0x23EC */
  __IO uint32_t DENALI_PI_252;                     /**< DENALI_PI_252, offset: 0x23F0 */
  __IO uint32_t DENALI_PI_253;                     /**< DENALI_PI_253, offset: 0x23F4 */
  __IO uint32_t DENALI_PI_254;                     /**< DENALI_PI_254, offset: 0x23F8 */
  __IO uint32_t DENALI_PI_255;                     /**< DENALI_PI_255, offset: 0x23FC */
  __IO uint32_t DENALI_PI_256;                     /**< DENALI_PI_256, offset: 0x2400 */
  __IO uint32_t DENALI_PI_257;                     /**< DENALI_PI_257, offset: 0x2404 */
  __IO uint32_t DENALI_PI_258;                     /**< DENALI_PI_258, offset: 0x2408 */
       uint8_t RESERVED_15[8];
  __IO uint32_t DENALI_PI_261;                     /**< DENALI_PI_261, offset: 0x2414 */
       uint8_t RESERVED_16[60];
  __IO uint32_t DENALI_PI_277;                     /**< DENALI_PI_277, offset: 0x2454 */
  __IO uint32_t DENALI_PI_278;                     /**< DENALI_PI_278, offset: 0x2458 */
  __IO uint32_t DENALI_PI_279;                     /**< DENALI_PI_279, offset: 0x245C */
  __IO uint32_t DENALI_PI_280;                     /**< DENALI_PI_280, offset: 0x2460 */
  __IO uint32_t DENALI_PI_281;                     /**< DENALI_PI_281, offset: 0x2464 */
  __IO uint32_t DENALI_PI_282;                     /**< DENALI_PI_282, offset: 0x2468 */
       uint8_t RESERVED_17[4];
  __IO uint32_t DENALI_PI_284;                     /**< DENALI_PI_284, offset: 0x2470 */
  __IO uint32_t DENALI_PI_285;                     /**< DENALI_PI_285, offset: 0x2474 */
  __IO uint32_t DENALI_PI_286;                     /**< DENALI_PI_286, offset: 0x2478 */
  __IO uint32_t DENALI_PI_287;                     /**< DENALI_PI_287, offset: 0x247C */
  __IO uint32_t DENALI_PI_288;                     /**< DENALI_PI_288, offset: 0x2480 */
  __IO uint32_t DENALI_PI_289;                     /**< DENALI_PI_289, offset: 0x2484 */
  __IO uint32_t DENALI_PI_290;                     /**< DENALI_PI_290, offset: 0x2488 */
  __IO uint32_t DENALI_PI_291;                     /**< DENALI_PI_291, offset: 0x248C */
  __IO uint32_t DENALI_PI_292;                     /**< DENALI_PI_292, offset: 0x2490 */
  __IO uint32_t DENALI_PI_293;                     /**< DENALI_PI_293, offset: 0x2494 */
  __IO uint32_t DENALI_PI_294;                     /**< DENALI_PI_294, offset: 0x2498 */
  __IO uint32_t DENALI_PI_295;                     /**< DENALI_PI_295, offset: 0x249C */
  __IO uint32_t DENALI_PI_296;                     /**< DENALI_PI_296, offset: 0x24A0 */
  __IO uint32_t DENALI_PI_297;                     /**< DENALI_PI_297, offset: 0x24A4 */
       uint8_t RESERVED_18[7124];
  __IO uint32_t DENALI_PHY_31;                     /**< DENALI_PHY_31, offset: 0x407C */
       uint8_t RESERVED_19[4];
  __IO uint32_t DENALI_PHY_33;                     /**< DENALI_PHY_33, offset: 0x4084 */
       uint8_t RESERVED_20[152];
  __IO uint32_t DENALI_PHY_72;                     /**< DENALI_PHY_72, offset: 0x4120 */
  __IO uint32_t DENALI_PHY_73;                     /**< DENALI_PHY_73, offset: 0x4124 */
  __IO uint32_t DENALI_PHY_74;                     /**< DENALI_PHY_74, offset: 0x4128 */
  __IO uint32_t DENALI_PHY_75;                     /**< DENALI_PHY_75, offset: 0x412C */
       uint8_t RESERVED_21[16];
  __IO uint32_t DENALI_PHY_80;                     /**< DENALI_PHY_80, offset: 0x4140 */
       uint8_t RESERVED_22[28];
  __IO uint32_t DENALI_PHY_88;                     /**< DENALI_PHY_88, offset: 0x4160 */
  __IO uint32_t DENALI_PHY_89;                     /**< DENALI_PHY_89, offset: 0x4164 */
  __IO uint32_t DENALI_PHY_90;                     /**< DENALI_PHY_90, offset: 0x4168 */
       uint8_t RESERVED_23[4];
  __IO uint32_t DENALI_PHY_92;                     /**< DENALI_PHY_92, offset: 0x4170 */
  __IO uint32_t DENALI_PHY_93;                     /**< DENALI_PHY_93, offset: 0x4174 */
       uint8_t RESERVED_24[4];
  __IO uint32_t DENALI_PHY_95;                     /**< DENALI_PHY_95, offset: 0x417C */
  __IO uint32_t DENALI_PHY_96;                     /**< DENALI_PHY_96, offset: 0x4180 */
  __IO uint32_t DENALI_PHY_97;                     /**< DENALI_PHY_97, offset: 0x4184 */
  __IO uint32_t DENALI_PHY_98;                     /**< DENALI_PHY_98, offset: 0x4188 */
       uint8_t RESERVED_25[4];
  __IO uint32_t DENALI_PHY_100;                    /**< DENALI_PHY_100, offset: 0x4190 */
  __IO uint32_t DENALI_PHY_101;                    /**< DENALI_PHY_101, offset: 0x4194 */
  __IO uint32_t DENALI_PHY_102;                    /**< DENALI_PHY_102, offset: 0x4198 */
  __IO uint32_t DENALI_PHY_103;                    /**< DENALI_PHY_103, offset: 0x419C */
  __IO uint32_t DENALI_PHY_104;                    /**< DENALI_PHY_104, offset: 0x41A0 */
       uint8_t RESERVED_26[36];
  __IO uint32_t DENALI_PHY_114;                    /**< DENALI_PHY_114, offset: 0x41C8 */
       uint8_t RESERVED_27[688];
  __IO uint32_t DENALI_PHY_287;                    /**< DENALI_PHY_287, offset: 0x447C */
       uint8_t RESERVED_28[4];
  __IO uint32_t DENALI_PHY_289;                    /**< DENALI_PHY_289, offset: 0x4484 */
       uint8_t RESERVED_29[152];
  __IO uint32_t DENALI_PHY_328;                    /**< DENALI_PHY_328, offset: 0x4520 */
  __IO uint32_t DENALI_PHY_329;                    /**< DENALI_PHY_329, offset: 0x4524 */
  __IO uint32_t DENALI_PHY_330;                    /**< DENALI_PHY_330, offset: 0x4528 */
  __IO uint32_t DENALI_PHY_331;                    /**< DENALI_PHY_331, offset: 0x452C */
       uint8_t RESERVED_30[16];
  __IO uint32_t DENALI_PHY_336;                    /**< DENALI_PHY_336, offset: 0x4540 */
       uint8_t RESERVED_31[28];
  __IO uint32_t DENALI_PHY_344;                    /**< DENALI_PHY_344, offset: 0x4560 */
  __IO uint32_t DENALI_PHY_345;                    /**< DENALI_PHY_345, offset: 0x4564 */
  __IO uint32_t DENALI_PHY_346;                    /**< DENALI_PHY_346, offset: 0x4568 */
       uint8_t RESERVED_32[4];
  __IO uint32_t DENALI_PHY_348;                    /**< DENALI_PHY_348, offset: 0x4570 */
  __IO uint32_t DENALI_PHY_349;                    /**< DENALI_PHY_349, offset: 0x4574 */
       uint8_t RESERVED_33[4];
  __IO uint32_t DENALI_PHY_351;                    /**< DENALI_PHY_351, offset: 0x457C */
  __IO uint32_t DENALI_PHY_352;                    /**< DENALI_PHY_352, offset: 0x4580 */
  __IO uint32_t DENALI_PHY_353;                    /**< DENALI_PHY_353, offset: 0x4584 */
  __IO uint32_t DENALI_PHY_354;                    /**< DENALI_PHY_354, offset: 0x4588 */
       uint8_t RESERVED_34[4];
  __IO uint32_t DENALI_PHY_356;                    /**< DENALI_PHY_356, offset: 0x4590 */
  __IO uint32_t DENALI_PHY_357;                    /**< DENALI_PHY_357, offset: 0x4594 */
  __IO uint32_t DENALI_PHY_358;                    /**< DENALI_PHY_358, offset: 0x4598 */
  __IO uint32_t DENALI_PHY_359;                    /**< DENALI_PHY_359, offset: 0x459C */
  __IO uint32_t DENALI_PHY_360;                    /**< DENALI_PHY_360, offset: 0x45A0 */
       uint8_t RESERVED_35[36];
  __IO uint32_t DENALI_PHY_370;                    /**< DENALI_PHY_370, offset: 0x45C8 */
       uint8_t RESERVED_36[688];
  __IO uint32_t DENALI_PHY_543;                    /**< DENALI_PHY_543, offset: 0x487C */
       uint8_t RESERVED_37[4];
  __IO uint32_t DENALI_PHY_545;                    /**< DENALI_PHY_545, offset: 0x4884 */
       uint8_t RESERVED_38[152];
  __IO uint32_t DENALI_PHY_584;                    /**< DENALI_PHY_584, offset: 0x4920 */
  __IO uint32_t DENALI_PHY_585;                    /**< DENALI_PHY_585, offset: 0x4924 */
  __IO uint32_t DENALI_PHY_586;                    /**< DENALI_PHY_586, offset: 0x4928 */
  __IO uint32_t DENALI_PHY_587;                    /**< DENALI_PHY_587, offset: 0x492C */
       uint8_t RESERVED_39[16];
  __IO uint32_t DENALI_PHY_592;                    /**< DENALI_PHY_592, offset: 0x4940 */
       uint8_t RESERVED_40[28];
  __IO uint32_t DENALI_PHY_600;                    /**< DENALI_PHY_600, offset: 0x4960 */
  __IO uint32_t DENALI_PHY_601;                    /**< DENALI_PHY_601, offset: 0x4964 */
  __IO uint32_t DENALI_PHY_602;                    /**< DENALI_PHY_602, offset: 0x4968 */
       uint8_t RESERVED_41[4];
  __IO uint32_t DENALI_PHY_604;                    /**< DENALI_PHY_604, offset: 0x4970 */
  __IO uint32_t DENALI_PHY_605;                    /**< DENALI_PHY_605, offset: 0x4974 */
       uint8_t RESERVED_42[4];
  __IO uint32_t DENALI_PHY_607;                    /**< DENALI_PHY_607, offset: 0x497C */
  __IO uint32_t DENALI_PHY_608;                    /**< DENALI_PHY_608, offset: 0x4980 */
  __IO uint32_t DENALI_PHY_609;                    /**< DENALI_PHY_609, offset: 0x4984 */
  __IO uint32_t DENALI_PHY_610;                    /**< DENALI_PHY_610, offset: 0x4988 */
       uint8_t RESERVED_43[4];
  __IO uint32_t DENALI_PHY_612;                    /**< DENALI_PHY_612, offset: 0x4990 */
  __IO uint32_t DENALI_PHY_613;                    /**< DENALI_PHY_613, offset: 0x4994 */
  __IO uint32_t DENALI_PHY_614;                    /**< DENALI_PHY_614, offset: 0x4998 */
  __IO uint32_t DENALI_PHY_615;                    /**< DENALI_PHY_615, offset: 0x499C */
  __IO uint32_t DENALI_PHY_616;                    /**< DENALI_PHY_616, offset: 0x49A0 */
       uint8_t RESERVED_44[36];
  __IO uint32_t DENALI_PHY_626;                    /**< DENALI_PHY_626, offset: 0x49C8 */
       uint8_t RESERVED_45[688];
  __IO uint32_t DENALI_PHY_799;                    /**< DENALI_PHY_799, offset: 0x4C7C */
       uint8_t RESERVED_46[4];
  __IO uint32_t DENALI_PHY_801;                    /**< DENALI_PHY_801, offset: 0x4C84 */
       uint8_t RESERVED_47[152];
  __IO uint32_t DENALI_PHY_840;                    /**< DENALI_PHY_840, offset: 0x4D20 */
  __IO uint32_t DENALI_PHY_841;                    /**< DENALI_PHY_841, offset: 0x4D24 */
  __IO uint32_t DENALI_PHY_842;                    /**< DENALI_PHY_842, offset: 0x4D28 */
  __IO uint32_t DENALI_PHY_843;                    /**< DENALI_PHY_843, offset: 0x4D2C */
       uint8_t RESERVED_48[16];
  __IO uint32_t DENALI_PHY_848;                    /**< DENALI_PHY_848, offset: 0x4D40 */
       uint8_t RESERVED_49[28];
  __IO uint32_t DENALI_PHY_856;                    /**< DENALI_PHY_856, offset: 0x4D60 */
  __IO uint32_t DENALI_PHY_857;                    /**< DENALI_PHY_857, offset: 0x4D64 */
  __IO uint32_t DENALI_PHY_858;                    /**< DENALI_PHY_858, offset: 0x4D68 */
       uint8_t RESERVED_50[4];
  __IO uint32_t DENALI_PHY_860;                    /**< DENALI_PHY_860, offset: 0x4D70 */
  __IO uint32_t DENALI_PHY_861;                    /**< DENALI_PHY_861, offset: 0x4D74 */
       uint8_t RESERVED_51[4];
  __IO uint32_t DENALI_PHY_863;                    /**< DENALI_PHY_863, offset: 0x4D7C */
  __IO uint32_t DENALI_PHY_864;                    /**< DENALI_PHY_864, offset: 0x4D80 */
  __IO uint32_t DENALI_PHY_865;                    /**< DENALI_PHY_865, offset: 0x4D84 */
  __IO uint32_t DENALI_PHY_866;                    /**< DENALI_PHY_866, offset: 0x4D88 */
       uint8_t RESERVED_52[4];
  __IO uint32_t DENALI_PHY_868;                    /**< DENALI_PHY_868, offset: 0x4D90 */
  __IO uint32_t DENALI_PHY_869;                    /**< DENALI_PHY_869, offset: 0x4D94 */
  __IO uint32_t DENALI_PHY_870;                    /**< DENALI_PHY_870, offset: 0x4D98 */
  __IO uint32_t DENALI_PHY_871;                    /**< DENALI_PHY_871, offset: 0x4D9C */
  __IO uint32_t DENALI_PHY_872;                    /**< DENALI_PHY_872, offset: 0x4DA0 */
       uint8_t RESERVED_53[36];
  __IO uint32_t DENALI_PHY_882;                    /**< DENALI_PHY_882, offset: 0x4DC8 */
       uint8_t RESERVED_54[588];
  __IO uint32_t DENALI_PHY_1030;                   /**< DENALI_PHY_1030, offset: 0x5018 */
       uint8_t RESERVED_55[96];
  __IO uint32_t DENALI_PHY_1055;                   /**< DENALI_PHY_1055, offset: 0x507C */
       uint8_t RESERVED_56[28];
  __IO uint32_t DENALI_PHY_1063;                   /**< DENALI_PHY_1063, offset: 0x509C */
       uint8_t RESERVED_57[888];
  __IO uint32_t DENALI_PHY_1286;                   /**< DENALI_PHY_1286, offset: 0x5418 */
       uint8_t RESERVED_58[96];
  __IO uint32_t DENALI_PHY_1311;                   /**< DENALI_PHY_1311, offset: 0x547C */
       uint8_t RESERVED_59[28];
  __IO uint32_t DENALI_PHY_1319;                   /**< DENALI_PHY_1319, offset: 0x549C */
       uint8_t RESERVED_60[864];
  __IO uint32_t DENALI_PHY_1536;                   /**< DENALI_PHY_1536, offset: 0x5800 */
  __IO uint32_t DENALI_PHY_1537;                   /**< DENALI_PHY_1537, offset: 0x5804 */
       uint8_t RESERVED_61[36];
  __IO uint32_t DENALI_PHY_1547;                   /**< DENALI_PHY_1547, offset: 0x582C */
       uint8_t RESERVED_62[28];
  __IO uint32_t DENALI_PHY_1555;                   /**< DENALI_PHY_1555, offset: 0x584C */
       uint8_t RESERVED_63[32];
  __I  uint32_t DENALI_PHY_1564;                   /**< DENALI_PHY_1564, offset: 0x5870 */
  __IO uint32_t DENALI_PHY_1565;                   /**< DENALI_PHY_1565, offset: 0x5874 */
  __IO uint32_t DENALI_PHY_1566;                   /**< DENALI_PHY_1566, offset: 0x5878 */
       uint8_t RESERVED_64[8];
  __IO uint32_t DENALI_PHY_1569;                   /**< DENALI_PHY_1569, offset: 0x5884 */
       uint8_t RESERVED_65[40];
  __IO uint32_t DENALI_PHY_1580;                   /**< DENALI_PHY_1580, offset: 0x58B0 */
       uint8_t RESERVED_66[52];
  __IO uint32_t DENALI_PHY_1594;                   /**< DENALI_PHY_1594, offset: 0x58E8 */
       uint8_t RESERVED_67[48];
  __IO uint32_t DENALI_PHY_1607;                   /**< DENALI_PHY_1607, offset: 0x591C */
       uint8_t RESERVED_68[64];
  __IO uint32_t DENALI_PHY_1624;                   /**< DENALI_PHY_1624, offset: 0x5960 */
  __IO uint32_t DENALI_PHY_1625;                   /**< DENALI_PHY_1625, offset: 0x5964 */
  __IO uint32_t DENALI_PHY_1626;                   /**< DENALI_PHY_1626, offset: 0x5968 */
       uint8_t RESERVED_69[32];
  __IO uint32_t DENALI_PHY_1635;                   /**< DENALI_PHY_1635, offset: 0x598C */
       uint8_t RESERVED_70[4];
  __IO uint32_t DENALI_PHY_1637;                   /**< DENALI_PHY_1637, offset: 0x5994 */
       uint8_t RESERVED_71[4];
  __IO uint32_t DENALI_PHY_1639;                   /**< DENALI_PHY_1639, offset: 0x599C */
       uint8_t RESERVED_72[4];
  __IO uint32_t DENALI_PHY_1641;                   /**< DENALI_PHY_1641, offset: 0x59A4 */
       uint8_t RESERVED_73[4];
  __IO uint32_t DENALI_PHY_1643;                   /**< DENALI_PHY_1643, offset: 0x59AC */
       uint8_t RESERVED_74[4];
  __IO uint32_t DENALI_PHY_1645;                   /**< DENALI_PHY_1645, offset: 0x59B4 */
       uint8_t RESERVED_75[4];
  __IO uint32_t DENALI_PHY_1647;                   /**< DENALI_PHY_1647, offset: 0x59BC */
       uint8_t RESERVED_76[4];
  __IO uint32_t DENALI_PHY_1649;                   /**< DENALI_PHY_1649, offset: 0x59C4 */
       uint8_t RESERVED_77[4];
  __IO uint32_t DENALI_PHY_1651;                   /**< DENALI_PHY_1651, offset: 0x59CC */
       uint8_t RESERVED_78[4];
  __IO uint32_t DENALI_PHY_1653;                   /**< DENALI_PHY_1653, offset: 0x59D4 */
} LPDDR_Type;

/* ----------------------------------------------------------------------------
   -- LPDDR Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPDDR_Register_Masks LPDDR Register Masks
 * @{
 */

/*! @name DENALI_CTL - DENALI_CTL_0..DENALI_CTL_614 */
/*! @{ */

#define LPDDR_DENALI_CTL_ADDR_CMP_EN_MASK        (0x1U)
#define LPDDR_DENALI_CTL_ADDR_CMP_EN_SHIFT       (0U)
/*! ADDR_CMP_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_ADDR_CMP_EN(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ADDR_CMP_EN_SHIFT)) & LPDDR_DENALI_CTL_ADDR_CMP_EN_MASK)

#define LPDDR_DENALI_CTL_AP_MASK                 (0x1U)
#define LPDDR_DENALI_CTL_AP_SHIFT                (0U)
/*! AP
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_AP(x)                   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AP_SHIFT)) & LPDDR_DENALI_CTL_AP_MASK)

#define LPDDR_DENALI_CTL_AXI0_R_PRIORITY_MASK    (0x7U)
#define LPDDR_DENALI_CTL_AXI0_R_PRIORITY_SHIFT   (0U)
#define LPDDR_DENALI_CTL_AXI0_R_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI0_R_PRIORITY_SHIFT)) & LPDDR_DENALI_CTL_AXI0_R_PRIORITY_MASK)

#define LPDDR_DENALI_CTL_AXI1_FIXED_PORT_PRIORITY_ENABLE_MASK (0x1U)
#define LPDDR_DENALI_CTL_AXI1_FIXED_PORT_PRIORITY_ENABLE_SHIFT (0U)
#define LPDDR_DENALI_CTL_AXI1_FIXED_PORT_PRIORITY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI1_FIXED_PORT_PRIORITY_ENABLE_SHIFT)) & LPDDR_DENALI_CTL_AXI1_FIXED_PORT_PRIORITY_ENABLE_MASK)

#define LPDDR_DENALI_CTL_AXI2_ALL_STROBES_USED_ENABLE_MASK (0x1U)
#define LPDDR_DENALI_CTL_AXI2_ALL_STROBES_USED_ENABLE_SHIFT (0U)
#define LPDDR_DENALI_CTL_AXI2_ALL_STROBES_USED_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI2_ALL_STROBES_USED_ENABLE_SHIFT)) & LPDDR_DENALI_CTL_AXI2_ALL_STROBES_USED_ENABLE_MASK)

#define LPDDR_DENALI_CTL_AXI2_FIFO_TYPE_REG_MASK (0x3U)
#define LPDDR_DENALI_CTL_AXI2_FIFO_TYPE_REG_SHIFT (0U)
#define LPDDR_DENALI_CTL_AXI2_FIFO_TYPE_REG(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI2_FIFO_TYPE_REG_SHIFT)) & LPDDR_DENALI_CTL_AXI2_FIFO_TYPE_REG_MASK)

#define LPDDR_DENALI_CTL_AXI3_W_PRIORITY_MASK    (0x7U)
#define LPDDR_DENALI_CTL_AXI3_W_PRIORITY_SHIFT   (0U)
#define LPDDR_DENALI_CTL_AXI3_W_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI3_W_PRIORITY_SHIFT)) & LPDDR_DENALI_CTL_AXI3_W_PRIORITY_MASK)

#define LPDDR_DENALI_CTL_BANK_ADDR_INTLV_EN_MASK (0x1U)
#define LPDDR_DENALI_CTL_BANK_ADDR_INTLV_EN_SHIFT (0U)
/*! BANK_ADDR_INTLV_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_BANK_ADDR_INTLV_EN(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_BANK_ADDR_INTLV_EN_SHIFT)) & LPDDR_DENALI_CTL_BANK_ADDR_INTLV_EN_MASK)

#define LPDDR_DENALI_CTL_CASLAT_LIN_F0_MASK      (0x7FU)
#define LPDDR_DENALI_CTL_CASLAT_LIN_F0_SHIFT     (0U)
#define LPDDR_DENALI_CTL_CASLAT_LIN_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CASLAT_LIN_F0_SHIFT)) & LPDDR_DENALI_CTL_CASLAT_LIN_F0_MASK)

#define LPDDR_DENALI_CTL_CASLAT_LIN_F2_MASK      (0x7FU)
#define LPDDR_DENALI_CTL_CASLAT_LIN_F2_SHIFT     (0U)
#define LPDDR_DENALI_CTL_CASLAT_LIN_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CASLAT_LIN_F2_SHIFT)) & LPDDR_DENALI_CTL_CASLAT_LIN_F2_MASK)

#define LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F1_MASK  (0x1U)
#define LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F1_SHIFT (0U)
#define LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F1_SHIFT)) & LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F1_MASK)

#define LPDDR_DENALI_CTL_CKE_INACTIVE_MASK       (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_CKE_INACTIVE_SHIFT      (0U)
#define LPDDR_DENALI_CTL_CKE_INACTIVE(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CKE_INACTIVE_SHIFT)) & LPDDR_DENALI_CTL_CKE_INACTIVE_MASK)

#define LPDDR_DENALI_CTL_CTRLUPD_REQ_PER_AREF_EN_MASK (0x1U)
#define LPDDR_DENALI_CTL_CTRLUPD_REQ_PER_AREF_EN_SHIFT (0U)
/*! CTRLUPD_REQ_PER_AREF_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_CTRLUPD_REQ_PER_AREF_EN(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CTRLUPD_REQ_PER_AREF_EN_SHIFT)) & LPDDR_DENALI_CTL_CTRLUPD_REQ_PER_AREF_EN_MASK)

#define LPDDR_DENALI_CTL_DEVICE1_BYTE0_CS1_MASK  (0xFU)
#define LPDDR_DENALI_CTL_DEVICE1_BYTE0_CS1_SHIFT (0U)
#define LPDDR_DENALI_CTL_DEVICE1_BYTE0_CS1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DEVICE1_BYTE0_CS1_SHIFT)) & LPDDR_DENALI_CTL_DEVICE1_BYTE0_CS1_MASK)

#define LPDDR_DENALI_CTL_DEVICE2_BYTE0_CS0_MASK  (0xFU)
#define LPDDR_DENALI_CTL_DEVICE2_BYTE0_CS0_SHIFT (0U)
#define LPDDR_DENALI_CTL_DEVICE2_BYTE0_CS0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DEVICE2_BYTE0_CS0_SHIFT)) & LPDDR_DENALI_CTL_DEVICE2_BYTE0_CS0_MASK)

#define LPDDR_DENALI_CTL_DFIBUS_BOOT_FREQ_MASK   (0x3U)
#define LPDDR_DENALI_CTL_DFIBUS_BOOT_FREQ_SHIFT  (0U)
/*! DFIBUS_BOOT_FREQ - Defines the DFI bus boot frequency. */
#define LPDDR_DENALI_CTL_DFIBUS_BOOT_FREQ(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DFIBUS_BOOT_FREQ_SHIFT)) & LPDDR_DENALI_CTL_DFIBUS_BOOT_FREQ_MASK)

#define LPDDR_DENALI_CTL_DFI_ERROR_MASK          (0x1FU)
#define LPDDR_DENALI_CTL_DFI_ERROR_SHIFT         (0U)
#define LPDDR_DENALI_CTL_DFI_ERROR(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DFI_ERROR_SHIFT)) & LPDDR_DENALI_CTL_DFI_ERROR_MASK)

#define LPDDR_DENALI_CTL_DFS_ALWAYS_WRITE_FSP_MASK (0x1U)
#define LPDDR_DENALI_CTL_DFS_ALWAYS_WRITE_FSP_SHIFT (0U)
/*! DFS_ALWAYS_WRITE_FSP
 *  0b0..The FSP mode registers may or may not be written
 *  0b1..Write the FSP mode registers
 */
#define LPDDR_DENALI_CTL_DFS_ALWAYS_WRITE_FSP(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DFS_ALWAYS_WRITE_FSP_SHIFT)) & LPDDR_DENALI_CTL_DFS_ALWAYS_WRITE_FSP_MASK)

#define LPDDR_DENALI_CTL_DISABLE_RD_INTERLEAVE_MASK (0x1U)
#define LPDDR_DENALI_CTL_DISABLE_RD_INTERLEAVE_SHIFT (0U)
/*! DISABLE_RD_INTERLEAVE
 *  0b0..Allow read data interleaving
 *  0b1..Disable read data interleaving
 */
#define LPDDR_DENALI_CTL_DISABLE_RD_INTERLEAVE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DISABLE_RD_INTERLEAVE_SHIFT)) & LPDDR_DENALI_CTL_DISABLE_RD_INTERLEAVE_MASK)

#define LPDDR_DENALI_CTL_DQS_OSC_PERIOD_MASK     (0x7FFFU)
#define LPDDR_DENALI_CTL_DQS_OSC_PERIOD_SHIFT    (0U)
#define LPDDR_DENALI_CTL_DQS_OSC_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DQS_OSC_PERIOD_SHIFT)) & LPDDR_DENALI_CTL_DQS_OSC_PERIOD_MASK)

#define LPDDR_DENALI_CTL_EN_ODT_ASSERT_EXCEPT_RD_MASK (0x1U)
#define LPDDR_DENALI_CTL_EN_ODT_ASSERT_EXCEPT_RD_SHIFT (0U)
/*! EN_ODT_ASSERT_EXCEPT_RD
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_EN_ODT_ASSERT_EXCEPT_RD(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_EN_ODT_ASSERT_EXCEPT_RD_SHIFT)) & LPDDR_DENALI_CTL_EN_ODT_ASSERT_EXCEPT_RD_MASK)

#define LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F0_MASK (0x3U)
#define LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F0_SHIFT (0U)
/*! FREQ_CHANGE_TYPE_F0 - Defines the encoded frequency driven out on the cntrl_freq_change_req_type signal during a frequency change operation. */
#define LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F0_SHIFT)) & LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F0_MASK)

#define LPDDR_DENALI_CTL_INT_ACK_FREQ_MASK       (0xFFU)
#define LPDDR_DENALI_CTL_INT_ACK_FREQ_SHIFT      (0U)
#define LPDDR_DENALI_CTL_INT_ACK_FREQ(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_ACK_FREQ_SHIFT)) & LPDDR_DENALI_CTL_INT_ACK_FREQ_MASK)

#define LPDDR_DENALI_CTL_INT_ACK_TIMEOUT_MASK    (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_INT_ACK_TIMEOUT_SHIFT   (0U)
#define LPDDR_DENALI_CTL_INT_ACK_TIMEOUT(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_ACK_TIMEOUT_SHIFT)) & LPDDR_DENALI_CTL_INT_ACK_TIMEOUT_MASK)

#define LPDDR_DENALI_CTL_INT_ACK_TRAINING_MASK   (0xFFFFU)
#define LPDDR_DENALI_CTL_INT_ACK_TRAINING_SHIFT  (0U)
#define LPDDR_DENALI_CTL_INT_ACK_TRAINING(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_ACK_TRAINING_SHIFT)) & LPDDR_DENALI_CTL_INT_ACK_TRAINING_MASK)

#define LPDDR_DENALI_CTL_INT_MASK_FREQ_MASK      (0xFFU)
#define LPDDR_DENALI_CTL_INT_MASK_FREQ_SHIFT     (0U)
#define LPDDR_DENALI_CTL_INT_MASK_FREQ(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_MASK_FREQ_SHIFT)) & LPDDR_DENALI_CTL_INT_MASK_FREQ_MASK)

#define LPDDR_DENALI_CTL_INT_MASK_MASTER_MASK    (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_INT_MASK_MASTER_SHIFT   (0U)
/*! INT_MASK_MASTER
 *  0b00000000000000000000000000000000..Do not mask interrupt
 *  0b00000000000000000000000000000001..Mask interrupt
 */
#define LPDDR_DENALI_CTL_INT_MASK_MASTER(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_MASK_MASTER_SHIFT)) & LPDDR_DENALI_CTL_INT_MASK_MASTER_MASK)

#define LPDDR_DENALI_CTL_INT_MASK_TIMEOUT_MASK   (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_INT_MASK_TIMEOUT_SHIFT  (0U)
#define LPDDR_DENALI_CTL_INT_MASK_TIMEOUT(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_MASK_TIMEOUT_SHIFT)) & LPDDR_DENALI_CTL_INT_MASK_TIMEOUT_MASK)

#define LPDDR_DENALI_CTL_INT_MASK_TRAINING_MASK  (0xFFFFU)
#define LPDDR_DENALI_CTL_INT_MASK_TRAINING_SHIFT (0U)
#define LPDDR_DENALI_CTL_INT_MASK_TRAINING(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_MASK_TRAINING_SHIFT)) & LPDDR_DENALI_CTL_INT_MASK_TRAINING_MASK)

#define LPDDR_DENALI_CTL_INT_STATUS_FREQ_MASK    (0xFFU)
#define LPDDR_DENALI_CTL_INT_STATUS_FREQ_SHIFT   (0U)
#define LPDDR_DENALI_CTL_INT_STATUS_FREQ(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_STATUS_FREQ_SHIFT)) & LPDDR_DENALI_CTL_INT_STATUS_FREQ_MASK)

#define LPDDR_DENALI_CTL_INT_STATUS_MASTER_MASK  (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_INT_STATUS_MASTER_SHIFT (0U)
#define LPDDR_DENALI_CTL_INT_STATUS_MASTER(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_STATUS_MASTER_SHIFT)) & LPDDR_DENALI_CTL_INT_STATUS_MASTER_MASK)

#define LPDDR_DENALI_CTL_INT_STATUS_TIMEOUT_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_INT_STATUS_TIMEOUT_SHIFT (0U)
#define LPDDR_DENALI_CTL_INT_STATUS_TIMEOUT(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_STATUS_TIMEOUT_SHIFT)) & LPDDR_DENALI_CTL_INT_STATUS_TIMEOUT_MASK)

#define LPDDR_DENALI_CTL_INT_STATUS_TRAINING_MASK (0xFFFFU)
#define LPDDR_DENALI_CTL_INT_STATUS_TRAINING_SHIFT (0U)
#define LPDDR_DENALI_CTL_INT_STATUS_TRAINING(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_STATUS_TRAINING_SHIFT)) & LPDDR_DENALI_CTL_INT_STATUS_TRAINING_MASK)

#define LPDDR_DENALI_CTL_IN_ORDER_ACCEPT_MASK    (0x1U)
#define LPDDR_DENALI_CTL_IN_ORDER_ACCEPT_SHIFT   (0U)
/*! IN_ORDER_ACCEPT - Forces the controller to accept commands in the order in which they are placed in the command queue.
 *  0b0..Uses the selection logic to select the ideal command for execution
 *  0b1..Disables the selection logic and executes commands in order
 */
#define LPDDR_DENALI_CTL_IN_ORDER_ACCEPT(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_IN_ORDER_ACCEPT_SHIFT)) & LPDDR_DENALI_CTL_IN_ORDER_ACCEPT_MASK)

#define LPDDR_DENALI_CTL_LPDDR2_S4_MASK          (0x1U)
#define LPDDR_DENALI_CTL_LPDDR2_S4_SHIFT         (0U)
#define LPDDR_DENALI_CTL_LPDDR2_S4(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_LPDDR2_S4_SHIFT)) & LPDDR_DENALI_CTL_LPDDR2_S4_MASK)

#define LPDDR_DENALI_CTL_MR1_DATA_F0_0_MASK      (0xFFU)
#define LPDDR_DENALI_CTL_MR1_DATA_F0_0_SHIFT     (0U)
#define LPDDR_DENALI_CTL_MR1_DATA_F0_0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR1_DATA_F0_0_SHIFT)) & LPDDR_DENALI_CTL_MR1_DATA_F0_0_MASK)

#define LPDDR_DENALI_CTL_MR1_DATA_F1_1_MASK      (0xFFU)
#define LPDDR_DENALI_CTL_MR1_DATA_F1_1_SHIFT     (0U)
#define LPDDR_DENALI_CTL_MR1_DATA_F1_1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR1_DATA_F1_1_SHIFT)) & LPDDR_DENALI_CTL_MR1_DATA_F1_1_MASK)

#define LPDDR_DENALI_CTL_MR1_DATA_F2_0_MASK      (0xFFU)
#define LPDDR_DENALI_CTL_MR1_DATA_F2_0_SHIFT     (0U)
#define LPDDR_DENALI_CTL_MR1_DATA_F2_0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR1_DATA_F2_0_SHIFT)) & LPDDR_DENALI_CTL_MR1_DATA_F2_0_MASK)

#define LPDDR_DENALI_CTL_MR3_DATA_F1_0_MASK      (0xFFU)
#define LPDDR_DENALI_CTL_MR3_DATA_F1_0_SHIFT     (0U)
#define LPDDR_DENALI_CTL_MR3_DATA_F1_0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR3_DATA_F1_0_SHIFT)) & LPDDR_DENALI_CTL_MR3_DATA_F1_0_MASK)

#define LPDDR_DENALI_CTL_MR4_DATA_F0_1_MASK      (0xFFU)
#define LPDDR_DENALI_CTL_MR4_DATA_F0_1_SHIFT     (0U)
#define LPDDR_DENALI_CTL_MR4_DATA_F0_1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR4_DATA_F0_1_SHIFT)) & LPDDR_DENALI_CTL_MR4_DATA_F0_1_MASK)

#define LPDDR_DENALI_CTL_MR4_DATA_F2_0_MASK      (0xFFU)
#define LPDDR_DENALI_CTL_MR4_DATA_F2_0_SHIFT     (0U)
#define LPDDR_DENALI_CTL_MR4_DATA_F2_0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR4_DATA_F2_0_SHIFT)) & LPDDR_DENALI_CTL_MR4_DATA_F2_0_MASK)

#define LPDDR_DENALI_CTL_MR11_DATA_F0_1_MASK     (0xFFU)
#define LPDDR_DENALI_CTL_MR11_DATA_F0_1_SHIFT    (0U)
#define LPDDR_DENALI_CTL_MR11_DATA_F0_1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR11_DATA_F0_1_SHIFT)) & LPDDR_DENALI_CTL_MR11_DATA_F0_1_MASK)

#define LPDDR_DENALI_CTL_MR11_DATA_F2_0_MASK     (0xFFU)
#define LPDDR_DENALI_CTL_MR11_DATA_F2_0_SHIFT    (0U)
#define LPDDR_DENALI_CTL_MR11_DATA_F2_0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR11_DATA_F2_0_SHIFT)) & LPDDR_DENALI_CTL_MR11_DATA_F2_0_MASK)

#define LPDDR_DENALI_CTL_MR12_DATA_F1_1_MASK     (0xFFU)
#define LPDDR_DENALI_CTL_MR12_DATA_F1_1_SHIFT    (0U)
#define LPDDR_DENALI_CTL_MR12_DATA_F1_1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR12_DATA_F1_1_SHIFT)) & LPDDR_DENALI_CTL_MR12_DATA_F1_1_MASK)

#define LPDDR_DENALI_CTL_MR14_DATA_F1_1_MASK     (0xFFU)
#define LPDDR_DENALI_CTL_MR14_DATA_F1_1_SHIFT    (0U)
#define LPDDR_DENALI_CTL_MR14_DATA_F1_1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR14_DATA_F1_1_SHIFT)) & LPDDR_DENALI_CTL_MR14_DATA_F1_1_MASK)

#define LPDDR_DENALI_CTL_MR20_DATA_1_MASK        (0xFFU)
#define LPDDR_DENALI_CTL_MR20_DATA_1_SHIFT       (0U)
#define LPDDR_DENALI_CTL_MR20_DATA_1(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR20_DATA_1_SHIFT)) & LPDDR_DENALI_CTL_MR20_DATA_1_MASK)

#define LPDDR_DENALI_CTL_MR22_DATA_F1_0_MASK     (0xFFU)
#define LPDDR_DENALI_CTL_MR22_DATA_F1_0_SHIFT    (0U)
#define LPDDR_DENALI_CTL_MR22_DATA_F1_0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR22_DATA_F1_0_SHIFT)) & LPDDR_DENALI_CTL_MR22_DATA_F1_0_MASK)

#define LPDDR_DENALI_CTL_MR23_DATA_MASK          (0xFFU)
#define LPDDR_DENALI_CTL_MR23_DATA_SHIFT         (0U)
/*! MR23_DATA - Data to program into memory mode register 23. */
#define LPDDR_DENALI_CTL_MR23_DATA(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR23_DATA_SHIFT)) & LPDDR_DENALI_CTL_MR23_DATA_MASK)

#define LPDDR_DENALI_CTL_MRR_ERROR_STATUS_MASK   (0x1U)
#define LPDDR_DENALI_CTL_MRR_ERROR_STATUS_SHIFT  (0U)
/*! MRR_ERROR_STATUS
 *  0b0..MRR was not issued while in self-refresh
 *  0b1..MRR was issued while in self-refresh
 */
#define LPDDR_DENALI_CTL_MRR_ERROR_STATUS(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MRR_ERROR_STATUS_SHIFT)) & LPDDR_DENALI_CTL_MRR_ERROR_STATUS_MASK)

#define LPDDR_DENALI_CTL_MRSINGLE_DATA_1_MASK    (0xFFU)
#define LPDDR_DENALI_CTL_MRSINGLE_DATA_1_SHIFT   (0U)
#define LPDDR_DENALI_CTL_MRSINGLE_DATA_1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MRSINGLE_DATA_1_SHIFT)) & LPDDR_DENALI_CTL_MRSINGLE_DATA_1_MASK)

#define LPDDR_DENALI_CTL_MRW_DFS_UPDATE_FRC_MASK (0x3U)
#define LPDDR_DENALI_CTL_MRW_DFS_UPDATE_FRC_SHIFT (0U)
#define LPDDR_DENALI_CTL_MRW_DFS_UPDATE_FRC(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MRW_DFS_UPDATE_FRC_SHIFT)) & LPDDR_DENALI_CTL_MRW_DFS_UPDATE_FRC_MASK)

#define LPDDR_DENALI_CTL_NWR_F1_MASK             (0xFFU)
#define LPDDR_DENALI_CTL_NWR_F1_SHIFT            (0U)
#define LPDDR_DENALI_CTL_NWR_F1(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_NWR_F1_SHIFT)) & LPDDR_DENALI_CTL_NWR_F1_MASK)

#define LPDDR_DENALI_CTL_ODT_RD_MAP_CS0_MASK     (0x3U)
#define LPDDR_DENALI_CTL_ODT_RD_MAP_CS0_SHIFT    (0U)
#define LPDDR_DENALI_CTL_ODT_RD_MAP_CS0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ODT_RD_MAP_CS0_SHIFT)) & LPDDR_DENALI_CTL_ODT_RD_MAP_CS0_MASK)

#define LPDDR_DENALI_CTL_PBR_BANK_SELECT_DELAY_MASK (0xFU)
#define LPDDR_DENALI_CTL_PBR_BANK_SELECT_DELAY_SHIFT (0U)
/*! PBR_BANK_SELECT_DELAY - Defines the PBR bank select to command delay, the time from bank
 *    selection to when the command queue bank selection logic is guaranteed to have blocked the bank.
 */
#define LPDDR_DENALI_CTL_PBR_BANK_SELECT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PBR_BANK_SELECT_DELAY_SHIFT)) & LPDDR_DENALI_CTL_PBR_BANK_SELECT_DELAY_MASK)

#define LPDDR_DENALI_CTL_PBR_EN_MASK             (0x1U)
#define LPDDR_DENALI_CTL_PBR_EN_SHIFT            (0U)
/*! PBR_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_PBR_EN(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PBR_EN_SHIFT)) & LPDDR_DENALI_CTL_PBR_EN_MASK)

#define LPDDR_DENALI_CTL_PHY_INDEP_TRAIN_MODE_MASK (0x1U)
#define LPDDR_DENALI_CTL_PHY_INDEP_TRAIN_MODE_SHIFT (0U)
/*! PHY_INDEP_TRAIN_MODE
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_PHY_INDEP_TRAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PHY_INDEP_TRAIN_MODE_SHIFT)) & LPDDR_DENALI_CTL_PHY_INDEP_TRAIN_MODE_MASK)

#define LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F2_MASK (0x3U)
#define LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F2_SHIFT (0U)
/*! PREAMBLE_SUPPORT_F2 - Selects the preamble for read and write burst transfers for frequency set 2. */
#define LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F2_SHIFT)) & LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F2_MASK)

#define LPDDR_DENALI_CTL_PRIORITY_EN_MASK        (0x1U)
#define LPDDR_DENALI_CTL_PRIORITY_EN_SHIFT       (0U)
/*! PRIORITY_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_PRIORITY_EN(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PRIORITY_EN_SHIFT)) & LPDDR_DENALI_CTL_PRIORITY_EN_MASK)

#define LPDDR_DENALI_CTL_PWRUP_SREFRESH_EXIT_MASK (0x1U)
#define LPDDR_DENALI_CTL_PWRUP_SREFRESH_EXIT_SHIFT (0U)
/*! PWRUP_SREFRESH_EXIT
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_PWRUP_SREFRESH_EXIT(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PWRUP_SREFRESH_EXIT_SHIFT)) & LPDDR_DENALI_CTL_PWRUP_SREFRESH_EXIT_MASK)

#define LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F1_MASK  (0x1FU)
#define LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F1_SHIFT (0U)
#define LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F1_SHIFT)) & LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F1_MASK)

#define LPDDR_DENALI_CTL_RDLAT_ADJ_F0_MASK       (0x7FU)
#define LPDDR_DENALI_CTL_RDLAT_ADJ_F0_SHIFT      (0U)
#define LPDDR_DENALI_CTL_RDLAT_ADJ_F0(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RDLAT_ADJ_F0_SHIFT)) & LPDDR_DENALI_CTL_RDLAT_ADJ_F0_MASK)

#define LPDDR_DENALI_CTL_RDLAT_ADJ_F1_MASK       (0x7FU)
#define LPDDR_DENALI_CTL_RDLAT_ADJ_F1_SHIFT      (0U)
#define LPDDR_DENALI_CTL_RDLAT_ADJ_F1(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RDLAT_ADJ_F1_SHIFT)) & LPDDR_DENALI_CTL_RDLAT_ADJ_F1_MASK)

#define LPDDR_DENALI_CTL_RDLAT_ADJ_F2_MASK       (0x7FU)
#define LPDDR_DENALI_CTL_RDLAT_ADJ_F2_SHIFT      (0U)
#define LPDDR_DENALI_CTL_RDLAT_ADJ_F2(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RDLAT_ADJ_F2_SHIFT)) & LPDDR_DENALI_CTL_RDLAT_ADJ_F2_MASK)

#define LPDDR_DENALI_CTL_RD_TO_ODTH_F0_MASK      (0x3FU)
#define LPDDR_DENALI_CTL_RD_TO_ODTH_F0_SHIFT     (0U)
#define LPDDR_DENALI_CTL_RD_TO_ODTH_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RD_TO_ODTH_F0_SHIFT)) & LPDDR_DENALI_CTL_RD_TO_ODTH_F0_MASK)

#define LPDDR_DENALI_CTL_RL3_SUPPORT_EN_MASK     (0x3U)
#define LPDDR_DENALI_CTL_RL3_SUPPORT_EN_SHIFT    (0U)
#define LPDDR_DENALI_CTL_RL3_SUPPORT_EN(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RL3_SUPPORT_EN_SHIFT)) & LPDDR_DENALI_CTL_RL3_SUPPORT_EN_MASK)

#define LPDDR_DENALI_CTL_RW2MRW_DLY_F1_MASK      (0x1FU)
#define LPDDR_DENALI_CTL_RW2MRW_DLY_F1_SHIFT     (0U)
#define LPDDR_DENALI_CTL_RW2MRW_DLY_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RW2MRW_DLY_F1_SHIFT)) & LPDDR_DENALI_CTL_RW2MRW_DLY_F1_MASK)

#define LPDDR_DENALI_CTL_START_MASK              (0x1U)
#define LPDDR_DENALI_CTL_START_SHIFT             (0U)
/*! START
 *  0b0..Controller is not in active mode.
 *  0b1..Initiate active mode for the controller.
 */
#define LPDDR_DENALI_CTL_START(x)                (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_START_SHIFT)) & LPDDR_DENALI_CTL_START_MASK)

#define LPDDR_DENALI_CTL_TCKELCMD_F0_MASK        (0x1FU)
#define LPDDR_DENALI_CTL_TCKELCMD_F0_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TCKELCMD_F0(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKELCMD_F0_SHIFT)) & LPDDR_DENALI_CTL_TCKELCMD_F0_MASK)

#define LPDDR_DENALI_CTL_TCKELCMD_F1_MASK        (0x1FU)
#define LPDDR_DENALI_CTL_TCKELCMD_F1_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TCKELCMD_F1(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKELCMD_F1_SHIFT)) & LPDDR_DENALI_CTL_TCKELCMD_F1_MASK)

#define LPDDR_DENALI_CTL_TCKELCMD_F2_MASK        (0x1FU)
#define LPDDR_DENALI_CTL_TCKELCMD_F2_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TCKELCMD_F2(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKELCMD_F2_SHIFT)) & LPDDR_DENALI_CTL_TCKELCMD_F2_MASK)

#define LPDDR_DENALI_CTL_TCKELCS_F1_MASK         (0x1FU)
#define LPDDR_DENALI_CTL_TCKELCS_F1_SHIFT        (0U)
#define LPDDR_DENALI_CTL_TCKELCS_F1(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKELCS_F1_SHIFT)) & LPDDR_DENALI_CTL_TCKELCS_F1_MASK)

#define LPDDR_DENALI_CTL_TCKESR_F0_MASK          (0xFFU)
#define LPDDR_DENALI_CTL_TCKESR_F0_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TCKESR_F0(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKESR_F0_SHIFT)) & LPDDR_DENALI_CTL_TCKESR_F0_MASK)

#define LPDDR_DENALI_CTL_TCKESR_F1_MASK          (0xFFU)
#define LPDDR_DENALI_CTL_TCKESR_F1_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TCKESR_F1(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKESR_F1_SHIFT)) & LPDDR_DENALI_CTL_TCKESR_F1_MASK)

#define LPDDR_DENALI_CTL_TCKESR_F2_MASK          (0xFFU)
#define LPDDR_DENALI_CTL_TCKESR_F2_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TCKESR_F2(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKESR_F2_SHIFT)) & LPDDR_DENALI_CTL_TCKESR_F2_MASK)

#define LPDDR_DENALI_CTL_TCKFSPE_F0_MASK         (0x1FU)
#define LPDDR_DENALI_CTL_TCKFSPE_F0_SHIFT        (0U)
#define LPDDR_DENALI_CTL_TCKFSPE_F0(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKFSPE_F0_SHIFT)) & LPDDR_DENALI_CTL_TCKFSPE_F0_MASK)

#define LPDDR_DENALI_CTL_TDAL_F1_MASK            (0xFFU)
#define LPDDR_DENALI_CTL_TDAL_F1_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TDAL_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDAL_F1_SHIFT)) & LPDDR_DENALI_CTL_TDAL_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F0_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F0_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F1_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F1_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F2_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F2_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_CTRLUPD_INTERVAL_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F0_MASK (0x1FFFFFU)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F0_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F1_MASK (0x1FFFFFU)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F1_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F2_MASK (0x1FFFFFU)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F2_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_CTRLUPD_MAX_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_MIN_MASK   (0xFFFFU)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_MIN_SHIFT  (0U)
#define LPDDR_DENALI_CTL_TDFI_CTRLUPD_MIN(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_CTRLUPD_MIN_SHIFT)) & LPDDR_DENALI_CTL_TDFI_CTRLUPD_MIN_MASK)

#define LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F2_MASK (0xFU)
#define LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F2_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F2(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F0_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F0_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F1_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F1_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F2_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F2_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F0_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F1_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F2_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE0_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F0_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F1_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F2_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE1_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F0_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F1_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F2_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE2_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F0_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F1_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F2_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_MAX_TYPE3_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F0_MASK (0xFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F0_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F1_MASK (0xFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F1_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F2_MASK (0xFFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F2_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYMSTR_RESP_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F0_MASK (0x7FFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F0_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F1_MASK (0x7FFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F1_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F2_MASK (0x7FFFFFU)
#define LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F2_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHYUPD_RESP_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F2_MASK  (0x7FU)
#define LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F2_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F1_MASK (0x7U)
#define LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F1_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F1(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHY_WRLAT_MASK     (0x7FU)
#define LPDDR_DENALI_CTL_TDFI_PHY_WRLAT_SHIFT    (0U)
#define LPDDR_DENALI_CTL_TDFI_PHY_WRLAT(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHY_WRLAT_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHY_WRLAT_MASK)

#define LPDDR_DENALI_CTL_TDFI_RDCSLAT_F1_MASK    (0x7FU)
#define LPDDR_DENALI_CTL_TDFI_RDCSLAT_F1_SHIFT   (0U)
#define LPDDR_DENALI_CTL_TDFI_RDCSLAT_F1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_RDCSLAT_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_RDCSLAT_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_WRDATA_DELAY_MASK  (0xFFU)
#define LPDDR_DENALI_CTL_TDFI_WRDATA_DELAY_SHIFT (0U)
#define LPDDR_DENALI_CTL_TDFI_WRDATA_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_WRDATA_DELAY_SHIFT)) & LPDDR_DENALI_CTL_TDFI_WRDATA_DELAY_MASK)

#define LPDDR_DENALI_CTL_TDQSCK_MAX_F0_MASK      (0xFU)
#define LPDDR_DENALI_CTL_TDQSCK_MAX_F0_SHIFT     (0U)
#define LPDDR_DENALI_CTL_TDQSCK_MAX_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDQSCK_MAX_F0_SHIFT)) & LPDDR_DENALI_CTL_TDQSCK_MAX_F0_MASK)

#define LPDDR_DENALI_CTL_TDQSCK_MAX_F2_MASK      (0xFU)
#define LPDDR_DENALI_CTL_TDQSCK_MAX_F2_SHIFT     (0U)
#define LPDDR_DENALI_CTL_TDQSCK_MAX_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDQSCK_MAX_F2_SHIFT)) & LPDDR_DENALI_CTL_TDQSCK_MAX_F2_MASK)

#define LPDDR_DENALI_CTL_TESCKE_F0_MASK          (0x7U)
#define LPDDR_DENALI_CTL_TESCKE_F0_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TESCKE_F0(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TESCKE_F0_SHIFT)) & LPDDR_DENALI_CTL_TESCKE_F0_MASK)

#define LPDDR_DENALI_CTL_TESCKE_F1_MASK          (0x7U)
#define LPDDR_DENALI_CTL_TESCKE_F1_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TESCKE_F1(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TESCKE_F1_SHIFT)) & LPDDR_DENALI_CTL_TESCKE_F1_MASK)

#define LPDDR_DENALI_CTL_TESCKE_F2_MASK          (0x7U)
#define LPDDR_DENALI_CTL_TESCKE_F2_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TESCKE_F2(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TESCKE_F2_SHIFT)) & LPDDR_DENALI_CTL_TESCKE_F2_MASK)

#define LPDDR_DENALI_CTL_TFAW_F0_MASK            (0x1FFU)
#define LPDDR_DENALI_CTL_TFAW_F0_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TFAW_F0(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TFAW_F0_SHIFT)) & LPDDR_DENALI_CTL_TFAW_F0_MASK)

#define LPDDR_DENALI_CTL_TFAW_F2_MASK            (0x1FFU)
#define LPDDR_DENALI_CTL_TFAW_F2_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TFAW_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TFAW_F2_SHIFT)) & LPDDR_DENALI_CTL_TFAW_F2_MASK)

#define LPDDR_DENALI_CTL_TFC_F1_MASK             (0x3FFU)
#define LPDDR_DENALI_CTL_TFC_F1_SHIFT            (0U)
#define LPDDR_DENALI_CTL_TFC_F1(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TFC_F1_SHIFT)) & LPDDR_DENALI_CTL_TFC_F1_MASK)

#define LPDDR_DENALI_CTL_TFC_F2_MASK             (0x3FFU)
#define LPDDR_DENALI_CTL_TFC_F2_SHIFT            (0U)
#define LPDDR_DENALI_CTL_TFC_F2(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TFC_F2_SHIFT)) & LPDDR_DENALI_CTL_TFC_F2_MASK)

#define LPDDR_DENALI_CTL_TINIT3_F0_MASK          (0xFFFFFFU)
#define LPDDR_DENALI_CTL_TINIT3_F0_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TINIT3_F0(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TINIT3_F0_SHIFT)) & LPDDR_DENALI_CTL_TINIT3_F0_MASK)

#define LPDDR_DENALI_CTL_TINIT3_F1_MASK          (0xFFFFFFU)
#define LPDDR_DENALI_CTL_TINIT3_F1_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TINIT3_F1(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TINIT3_F1_SHIFT)) & LPDDR_DENALI_CTL_TINIT3_F1_MASK)

#define LPDDR_DENALI_CTL_TINIT3_F2_MASK          (0xFFFFFFU)
#define LPDDR_DENALI_CTL_TINIT3_F2_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TINIT3_F2(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TINIT3_F2_SHIFT)) & LPDDR_DENALI_CTL_TINIT3_F2_MASK)

#define LPDDR_DENALI_CTL_TINIT4_F0_MASK          (0xFFFFFFU)
#define LPDDR_DENALI_CTL_TINIT4_F0_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TINIT4_F0(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TINIT4_F0_SHIFT)) & LPDDR_DENALI_CTL_TINIT4_F0_MASK)

#define LPDDR_DENALI_CTL_TINIT4_F1_MASK          (0xFFFFFFU)
#define LPDDR_DENALI_CTL_TINIT4_F1_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TINIT4_F1(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TINIT4_F1_SHIFT)) & LPDDR_DENALI_CTL_TINIT4_F1_MASK)

#define LPDDR_DENALI_CTL_TINIT4_F2_MASK          (0xFFFFFFU)
#define LPDDR_DENALI_CTL_TINIT4_F2_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TINIT4_F2(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TINIT4_F2_SHIFT)) & LPDDR_DENALI_CTL_TINIT4_F2_MASK)

#define LPDDR_DENALI_CTL_TINIT5_F0_MASK          (0xFFFFFFU)
#define LPDDR_DENALI_CTL_TINIT5_F0_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TINIT5_F0(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TINIT5_F0_SHIFT)) & LPDDR_DENALI_CTL_TINIT5_F0_MASK)

#define LPDDR_DENALI_CTL_TINIT5_F1_MASK          (0xFFFFFFU)
#define LPDDR_DENALI_CTL_TINIT5_F1_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TINIT5_F1(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TINIT5_F1_SHIFT)) & LPDDR_DENALI_CTL_TINIT5_F1_MASK)

#define LPDDR_DENALI_CTL_TINIT5_F2_MASK          (0xFFFFFFU)
#define LPDDR_DENALI_CTL_TINIT5_F2_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TINIT5_F2(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TINIT5_F2_SHIFT)) & LPDDR_DENALI_CTL_TINIT5_F2_MASK)

#define LPDDR_DENALI_CTL_TINIT_F1_MASK           (0xFFFFFFU)
#define LPDDR_DENALI_CTL_TINIT_F1_SHIFT          (0U)
#define LPDDR_DENALI_CTL_TINIT_F1(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TINIT_F1_SHIFT)) & LPDDR_DENALI_CTL_TINIT_F1_MASK)

#define LPDDR_DENALI_CTL_TINIT_F2_MASK           (0xFFFFFFU)
#define LPDDR_DENALI_CTL_TINIT_F2_SHIFT          (0U)
#define LPDDR_DENALI_CTL_TINIT_F2(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TINIT_F2_SHIFT)) & LPDDR_DENALI_CTL_TINIT_F2_MASK)

#define LPDDR_DENALI_CTL_TMRD_F0_MASK            (0xFFU)
#define LPDDR_DENALI_CTL_TMRD_F0_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TMRD_F0(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TMRD_F0_SHIFT)) & LPDDR_DENALI_CTL_TMRD_F0_MASK)

#define LPDDR_DENALI_CTL_TMRRI_F2_MASK           (0xFFU)
#define LPDDR_DENALI_CTL_TMRRI_F2_SHIFT          (0U)
#define LPDDR_DENALI_CTL_TMRRI_F2(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TMRRI_F2_SHIFT)) & LPDDR_DENALI_CTL_TMRRI_F2_MASK)

#define LPDDR_DENALI_CTL_TMRWCKEL_F0_MASK        (0x1FU)
#define LPDDR_DENALI_CTL_TMRWCKEL_F0_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TMRWCKEL_F0(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TMRWCKEL_F0_SHIFT)) & LPDDR_DENALI_CTL_TMRWCKEL_F0_MASK)

#define LPDDR_DENALI_CTL_TMRWCKEL_F2_MASK        (0x1FU)
#define LPDDR_DENALI_CTL_TMRWCKEL_F2_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TMRWCKEL_F2(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TMRWCKEL_F2_SHIFT)) & LPDDR_DENALI_CTL_TMRWCKEL_F2_MASK)

#define LPDDR_DENALI_CTL_TODTH_RD_F2_MASK        (0xFU)
#define LPDDR_DENALI_CTL_TODTH_RD_F2_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TODTH_RD_F2(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TODTH_RD_F2_SHIFT)) & LPDDR_DENALI_CTL_TODTH_RD_F2_MASK)

#define LPDDR_DENALI_CTL_TODTH_WR_F1_MASK        (0xFU)
#define LPDDR_DENALI_CTL_TODTH_WR_F1_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TODTH_WR_F1(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TODTH_WR_F1_SHIFT)) & LPDDR_DENALI_CTL_TODTH_WR_F1_MASK)

#define LPDDR_DENALI_CTL_TODTL_2CMD_F0_MASK      (0xFFU)
#define LPDDR_DENALI_CTL_TODTL_2CMD_F0_SHIFT     (0U)
#define LPDDR_DENALI_CTL_TODTL_2CMD_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TODTL_2CMD_F0_SHIFT)) & LPDDR_DENALI_CTL_TODTL_2CMD_F0_MASK)

#define LPDDR_DENALI_CTL_TOSCO_F1_MASK           (0xFFU)
#define LPDDR_DENALI_CTL_TOSCO_F1_SHIFT          (0U)
#define LPDDR_DENALI_CTL_TOSCO_F1(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TOSCO_F1_SHIFT)) & LPDDR_DENALI_CTL_TOSCO_F1_MASK)

#define LPDDR_DENALI_CTL_TPDEX_F0_MASK           (0xFFFFU)
#define LPDDR_DENALI_CTL_TPDEX_F0_SHIFT          (0U)
#define LPDDR_DENALI_CTL_TPDEX_F0(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TPDEX_F0_SHIFT)) & LPDDR_DENALI_CTL_TPDEX_F0_MASK)

#define LPDDR_DENALI_CTL_TPDEX_F2_MASK           (0xFFFFU)
#define LPDDR_DENALI_CTL_TPDEX_F2_SHIFT          (0U)
#define LPDDR_DENALI_CTL_TPDEX_F2(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TPDEX_F2_SHIFT)) & LPDDR_DENALI_CTL_TPDEX_F2_MASK)

#define LPDDR_DENALI_CTL_TRAS_MAX_F0_MASK        (0x1FFFFU)
#define LPDDR_DENALI_CTL_TRAS_MAX_F0_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TRAS_MAX_F0(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRAS_MAX_F0_SHIFT)) & LPDDR_DENALI_CTL_TRAS_MAX_F0_MASK)

#define LPDDR_DENALI_CTL_TRAS_MAX_F1_MASK        (0x1FFFFU)
#define LPDDR_DENALI_CTL_TRAS_MAX_F1_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TRAS_MAX_F1(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRAS_MAX_F1_SHIFT)) & LPDDR_DENALI_CTL_TRAS_MAX_F1_MASK)

#define LPDDR_DENALI_CTL_TRAS_MAX_F2_MASK        (0x1FFFFU)
#define LPDDR_DENALI_CTL_TRAS_MAX_F2_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TRAS_MAX_F2(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRAS_MAX_F2_SHIFT)) & LPDDR_DENALI_CTL_TRAS_MAX_F2_MASK)

#define LPDDR_DENALI_CTL_TRAS_MIN_F0_MASK        (0x1FFU)
#define LPDDR_DENALI_CTL_TRAS_MIN_F0_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TRAS_MIN_F0(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRAS_MIN_F0_SHIFT)) & LPDDR_DENALI_CTL_TRAS_MIN_F0_MASK)

#define LPDDR_DENALI_CTL_TRAS_MIN_F2_MASK        (0x1FFU)
#define LPDDR_DENALI_CTL_TRAS_MIN_F2_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TRAS_MIN_F2(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRAS_MIN_F2_SHIFT)) & LPDDR_DENALI_CTL_TRAS_MIN_F2_MASK)

#define LPDDR_DENALI_CTL_TRC_F1_MASK             (0x1FFU)
#define LPDDR_DENALI_CTL_TRC_F1_SHIFT            (0U)
#define LPDDR_DENALI_CTL_TRC_F1(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRC_F1_SHIFT)) & LPDDR_DENALI_CTL_TRC_F1_MASK)

#define LPDDR_DENALI_CTL_TREFI_PB_F0_MASK        (0xFFFFU)
#define LPDDR_DENALI_CTL_TREFI_PB_F0_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TREFI_PB_F0(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TREFI_PB_F0_SHIFT)) & LPDDR_DENALI_CTL_TREFI_PB_F0_MASK)

#define LPDDR_DENALI_CTL_TREFI_PB_F1_MASK        (0xFFFFU)
#define LPDDR_DENALI_CTL_TREFI_PB_F1_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TREFI_PB_F1(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TREFI_PB_F1_SHIFT)) & LPDDR_DENALI_CTL_TREFI_PB_F1_MASK)

#define LPDDR_DENALI_CTL_TREFI_PB_F2_MASK        (0xFFFFU)
#define LPDDR_DENALI_CTL_TREFI_PB_F2_SHIFT       (0U)
#define LPDDR_DENALI_CTL_TREFI_PB_F2(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TREFI_PB_F2_SHIFT)) & LPDDR_DENALI_CTL_TREFI_PB_F2_MASK)

#define LPDDR_DENALI_CTL_TREF_F0_MASK            (0xFFFFFU)
#define LPDDR_DENALI_CTL_TREF_F0_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TREF_F0(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TREF_F0_SHIFT)) & LPDDR_DENALI_CTL_TREF_F0_MASK)

#define LPDDR_DENALI_CTL_TREF_F1_MASK            (0xFFFFFU)
#define LPDDR_DENALI_CTL_TREF_F1_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TREF_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TREF_F1_SHIFT)) & LPDDR_DENALI_CTL_TREF_F1_MASK)

#define LPDDR_DENALI_CTL_TREF_F2_MASK            (0xFFFFFU)
#define LPDDR_DENALI_CTL_TREF_F2_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TREF_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TREF_F2_SHIFT)) & LPDDR_DENALI_CTL_TREF_F2_MASK)

#define LPDDR_DENALI_CTL_TREF_INTERVAL_MASK      (0xFFFFFU)
#define LPDDR_DENALI_CTL_TREF_INTERVAL_SHIFT     (0U)
/*! TREF_INTERVAL - Defines the cycles between refreshes to different chip selects. */
#define LPDDR_DENALI_CTL_TREF_INTERVAL(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TREF_INTERVAL_SHIFT)) & LPDDR_DENALI_CTL_TREF_INTERVAL_MASK)

#define LPDDR_DENALI_CTL_TRFC_F1_MASK            (0x3FFU)
#define LPDDR_DENALI_CTL_TRFC_F1_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TRFC_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRFC_F1_SHIFT)) & LPDDR_DENALI_CTL_TRFC_F1_MASK)

#define LPDDR_DENALI_CTL_TRFC_F2_MASK            (0x3FFU)
#define LPDDR_DENALI_CTL_TRFC_F2_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TRFC_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRFC_F2_SHIFT)) & LPDDR_DENALI_CTL_TRFC_F2_MASK)

#define LPDDR_DENALI_CTL_TRP_AB_F1_MASK          (0xFFU)
#define LPDDR_DENALI_CTL_TRP_AB_F1_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TRP_AB_F1(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRP_AB_F1_SHIFT)) & LPDDR_DENALI_CTL_TRP_AB_F1_MASK)

#define LPDDR_DENALI_CTL_TRRD_F0_MASK            (0xFFU)
#define LPDDR_DENALI_CTL_TRRD_F0_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TRRD_F0(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRRD_F0_SHIFT)) & LPDDR_DENALI_CTL_TRRD_F0_MASK)

#define LPDDR_DENALI_CTL_TRRD_F2_MASK            (0xFFU)
#define LPDDR_DENALI_CTL_TRRD_F2_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TRRD_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRRD_F2_SHIFT)) & LPDDR_DENALI_CTL_TRRD_F2_MASK)

#define LPDDR_DENALI_CTL_TRST_PWRON_MASK         (0xFFFFFFFFU)
#define LPDDR_DENALI_CTL_TRST_PWRON_SHIFT        (0U)
#define LPDDR_DENALI_CTL_TRST_PWRON(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRST_PWRON_SHIFT)) & LPDDR_DENALI_CTL_TRST_PWRON_MASK)

#define LPDDR_DENALI_CTL_TVRCG_DISABLE_F0_MASK   (0x3FFU)
#define LPDDR_DENALI_CTL_TVRCG_DISABLE_F0_SHIFT  (0U)
#define LPDDR_DENALI_CTL_TVRCG_DISABLE_F0(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TVRCG_DISABLE_F0_SHIFT)) & LPDDR_DENALI_CTL_TVRCG_DISABLE_F0_MASK)

#define LPDDR_DENALI_CTL_TVRCG_ENABLE_F1_MASK    (0x3FFU)
#define LPDDR_DENALI_CTL_TVRCG_ENABLE_F1_SHIFT   (0U)
#define LPDDR_DENALI_CTL_TVRCG_ENABLE_F1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TVRCG_ENABLE_F1_SHIFT)) & LPDDR_DENALI_CTL_TVRCG_ENABLE_F1_MASK)

#define LPDDR_DENALI_CTL_TVRCG_ENABLE_F2_MASK    (0x3FFU)
#define LPDDR_DENALI_CTL_TVRCG_ENABLE_F2_SHIFT   (0U)
#define LPDDR_DENALI_CTL_TVRCG_ENABLE_F2(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TVRCG_ENABLE_F2_SHIFT)) & LPDDR_DENALI_CTL_TVRCG_ENABLE_F2_MASK)

#define LPDDR_DENALI_CTL_TVREF_LONG_F0_MASK      (0xFFFFFU)
#define LPDDR_DENALI_CTL_TVREF_LONG_F0_SHIFT     (0U)
#define LPDDR_DENALI_CTL_TVREF_LONG_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TVREF_LONG_F0_SHIFT)) & LPDDR_DENALI_CTL_TVREF_LONG_F0_MASK)

#define LPDDR_DENALI_CTL_TVREF_LONG_F1_MASK      (0xFFFFFU)
#define LPDDR_DENALI_CTL_TVREF_LONG_F1_SHIFT     (0U)
#define LPDDR_DENALI_CTL_TVREF_LONG_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TVREF_LONG_F1_SHIFT)) & LPDDR_DENALI_CTL_TVREF_LONG_F1_MASK)

#define LPDDR_DENALI_CTL_TVREF_LONG_F2_MASK      (0xFFFFFU)
#define LPDDR_DENALI_CTL_TVREF_LONG_F2_SHIFT     (0U)
#define LPDDR_DENALI_CTL_TVREF_LONG_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TVREF_LONG_F2_SHIFT)) & LPDDR_DENALI_CTL_TVREF_LONG_F2_MASK)

#define LPDDR_DENALI_CTL_TWR_F1_MASK             (0xFFU)
#define LPDDR_DENALI_CTL_TWR_F1_SHIFT            (0U)
#define LPDDR_DENALI_CTL_TWR_F1(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TWR_F1_SHIFT)) & LPDDR_DENALI_CTL_TWR_F1_MASK)

#define LPDDR_DENALI_CTL_TWTR_F1_MASK            (0x3FU)
#define LPDDR_DENALI_CTL_TWTR_F1_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TWTR_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TWTR_F1_SHIFT)) & LPDDR_DENALI_CTL_TWTR_F1_MASK)

#define LPDDR_DENALI_CTL_TXSR_F0_MASK            (0xFFFFU)
#define LPDDR_DENALI_CTL_TXSR_F0_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TXSR_F0(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TXSR_F0_SHIFT)) & LPDDR_DENALI_CTL_TXSR_F0_MASK)

#define LPDDR_DENALI_CTL_TXSR_F1_MASK            (0xFFFFU)
#define LPDDR_DENALI_CTL_TXSR_F1_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TXSR_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TXSR_F1_SHIFT)) & LPDDR_DENALI_CTL_TXSR_F1_MASK)

#define LPDDR_DENALI_CTL_TXSR_F2_MASK            (0xFFFFU)
#define LPDDR_DENALI_CTL_TXSR_F2_SHIFT           (0U)
#define LPDDR_DENALI_CTL_TXSR_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TXSR_F2_SHIFT)) & LPDDR_DENALI_CTL_TXSR_F2_MASK)

#define LPDDR_DENALI_CTL_TZQCAL_F1_MASK          (0xFFFU)
#define LPDDR_DENALI_CTL_TZQCAL_F1_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TZQCAL_F1(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TZQCAL_F1_SHIFT)) & LPDDR_DENALI_CTL_TZQCAL_F1_MASK)

#define LPDDR_DENALI_CTL_TZQLAT_F0_MASK          (0x7FU)
#define LPDDR_DENALI_CTL_TZQLAT_F0_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TZQLAT_F0(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TZQLAT_F0_SHIFT)) & LPDDR_DENALI_CTL_TZQLAT_F0_MASK)

#define LPDDR_DENALI_CTL_TZQLAT_F2_MASK          (0x7FU)
#define LPDDR_DENALI_CTL_TZQLAT_F2_SHIFT         (0U)
#define LPDDR_DENALI_CTL_TZQLAT_F2(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TZQLAT_F2_SHIFT)) & LPDDR_DENALI_CTL_TZQLAT_F2_MASK)

#define LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F0_MASK  (0x1FU)
#define LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F0_SHIFT (0U)
#define LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F0_SHIFT)) & LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F0_MASK)

#define LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F1_MASK  (0x1FU)
#define LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F1_SHIFT (0U)
#define LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F1_SHIFT)) & LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F1_MASK)

#define LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F2_MASK  (0x1FU)
#define LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F2_SHIFT (0U)
#define LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F2_SHIFT)) & LPDDR_DENALI_CTL_W2R_DIFFCS_DLY_F2_MASK)

#define LPDDR_DENALI_CTL_W2R_SPLIT_EN_MASK       (0x1U)
#define LPDDR_DENALI_CTL_W2R_SPLIT_EN_SHIFT      (0U)
/*! W2R_SPLIT_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_W2R_SPLIT_EN(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_W2R_SPLIT_EN_SHIFT)) & LPDDR_DENALI_CTL_W2R_SPLIT_EN_MASK)

#define LPDDR_DENALI_CTL_WRITEINTERP_MASK        (0x1U)
#define LPDDR_DENALI_CTL_WRITEINTERP_SHIFT       (0U)
#define LPDDR_DENALI_CTL_WRITEINTERP(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_WRITEINTERP_SHIFT)) & LPDDR_DENALI_CTL_WRITEINTERP_MASK)

#define LPDDR_DENALI_CTL_WRITE_MODEREG_MASK      (0x7FFFFFFU)
#define LPDDR_DENALI_CTL_WRITE_MODEREG_SHIFT     (0U)
#define LPDDR_DENALI_CTL_WRITE_MODEREG(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_WRITE_MODEREG_SHIFT)) & LPDDR_DENALI_CTL_WRITE_MODEREG_MASK)

#define LPDDR_DENALI_CTL_ZQCL_F1_MASK            (0xFFFU)
#define LPDDR_DENALI_CTL_ZQCL_F1_SHIFT           (0U)
#define LPDDR_DENALI_CTL_ZQCL_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQCL_F1_SHIFT)) & LPDDR_DENALI_CTL_ZQCL_F1_MASK)

#define LPDDR_DENALI_CTL_ZQCS_F0_MASK            (0xFFFU)
#define LPDDR_DENALI_CTL_ZQCS_F0_SHIFT           (0U)
#define LPDDR_DENALI_CTL_ZQCS_F0(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQCS_F0_SHIFT)) & LPDDR_DENALI_CTL_ZQCS_F0_MASK)

#define LPDDR_DENALI_CTL_ZQCS_F2_MASK            (0xFFFU)
#define LPDDR_DENALI_CTL_ZQCS_F2_SHIFT           (0U)
#define LPDDR_DENALI_CTL_ZQCS_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQCS_F2_SHIFT)) & LPDDR_DENALI_CTL_ZQCS_F2_MASK)

#define LPDDR_DENALI_CTL_ZQINIT_F2_MASK          (0xFFFU)
#define LPDDR_DENALI_CTL_ZQINIT_F2_SHIFT         (0U)
#define LPDDR_DENALI_CTL_ZQINIT_F2(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQINIT_F2_SHIFT)) & LPDDR_DENALI_CTL_ZQINIT_F2_MASK)

#define LPDDR_DENALI_CTL_ZQRESET_F0_MASK         (0xFFFU)
#define LPDDR_DENALI_CTL_ZQRESET_F0_SHIFT        (0U)
#define LPDDR_DENALI_CTL_ZQRESET_F0(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQRESET_F0_SHIFT)) & LPDDR_DENALI_CTL_ZQRESET_F0_MASK)

#define LPDDR_DENALI_CTL_ZQRESET_F2_MASK         (0xFFFU)
#define LPDDR_DENALI_CTL_ZQRESET_F2_SHIFT        (0U)
#define LPDDR_DENALI_CTL_ZQRESET_F2(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQRESET_F2_SHIFT)) & LPDDR_DENALI_CTL_ZQRESET_F2_MASK)

#define LPDDR_DENALI_CTL_ADDR_COLLISION_MPM_DIS_MASK (0x100U)
#define LPDDR_DENALI_CTL_ADDR_COLLISION_MPM_DIS_SHIFT (8U)
/*! ADDR_COLLISION_MPM_DIS
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_ADDR_COLLISION_MPM_DIS(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ADDR_COLLISION_MPM_DIS_SHIFT)) & LPDDR_DENALI_CTL_ADDR_COLLISION_MPM_DIS_MASK)

#define LPDDR_DENALI_CTL_APREBIT_MASK            (0x1F00U)
#define LPDDR_DENALI_CTL_APREBIT_SHIFT           (8U)
#define LPDDR_DENALI_CTL_APREBIT(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_APREBIT_SHIFT)) & LPDDR_DENALI_CTL_APREBIT_MASK)

#define LPDDR_DENALI_CTL_AXI0_W_PRIORITY_MASK    (0x700U)
#define LPDDR_DENALI_CTL_AXI0_W_PRIORITY_SHIFT   (8U)
#define LPDDR_DENALI_CTL_AXI0_W_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI0_W_PRIORITY_SHIFT)) & LPDDR_DENALI_CTL_AXI0_W_PRIORITY_MASK)

#define LPDDR_DENALI_CTL_AXI1_R_PRIORITY_MASK    (0x700U)
#define LPDDR_DENALI_CTL_AXI1_R_PRIORITY_SHIFT   (8U)
#define LPDDR_DENALI_CTL_AXI1_R_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI1_R_PRIORITY_SHIFT)) & LPDDR_DENALI_CTL_AXI1_R_PRIORITY_MASK)

#define LPDDR_DENALI_CTL_AXI2_FIXED_PORT_PRIORITY_ENABLE_MASK (0x100U)
#define LPDDR_DENALI_CTL_AXI2_FIXED_PORT_PRIORITY_ENABLE_SHIFT (8U)
#define LPDDR_DENALI_CTL_AXI2_FIXED_PORT_PRIORITY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI2_FIXED_PORT_PRIORITY_ENABLE_SHIFT)) & LPDDR_DENALI_CTL_AXI2_FIXED_PORT_PRIORITY_ENABLE_MASK)

#define LPDDR_DENALI_CTL_AXI3_ALL_STROBES_USED_ENABLE_MASK (0x100U)
#define LPDDR_DENALI_CTL_AXI3_ALL_STROBES_USED_ENABLE_SHIFT (8U)
#define LPDDR_DENALI_CTL_AXI3_ALL_STROBES_USED_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI3_ALL_STROBES_USED_ENABLE_SHIFT)) & LPDDR_DENALI_CTL_AXI3_ALL_STROBES_USED_ENABLE_MASK)

#define LPDDR_DENALI_CTL_AXI3_FIFO_TYPE_REG_MASK (0x300U)
#define LPDDR_DENALI_CTL_AXI3_FIFO_TYPE_REG_SHIFT (8U)
#define LPDDR_DENALI_CTL_AXI3_FIFO_TYPE_REG(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI3_FIFO_TYPE_REG_SHIFT)) & LPDDR_DENALI_CTL_AXI3_FIFO_TYPE_REG_MASK)

#define LPDDR_DENALI_CTL_CONCURRENTAP_MASK       (0x100U)
#define LPDDR_DENALI_CTL_CONCURRENTAP_SHIFT      (8U)
/*! CONCURRENTAP
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_CONCURRENTAP(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CONCURRENTAP_SHIFT)) & LPDDR_DENALI_CTL_CONCURRENTAP_MASK)

#define LPDDR_DENALI_CTL_CS_COMPARISON_FOR_REFRESH_DEPTH_MASK (0x1F00U)
#define LPDDR_DENALI_CTL_CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT (8U)
#define LPDDR_DENALI_CTL_CS_COMPARISON_FOR_REFRESH_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT)) & LPDDR_DENALI_CTL_CS_COMPARISON_FOR_REFRESH_DEPTH_MASK)

#define LPDDR_DENALI_CTL_CTRLUPD_AREF_HP_ENABLE_MASK (0x100U)
#define LPDDR_DENALI_CTL_CTRLUPD_AREF_HP_ENABLE_SHIFT (8U)
#define LPDDR_DENALI_CTL_CTRLUPD_AREF_HP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CTRLUPD_AREF_HP_ENABLE_SHIFT)) & LPDDR_DENALI_CTL_CTRLUPD_AREF_HP_ENABLE_MASK)

#define LPDDR_DENALI_CTL_DEVICE2_BYTE0_CS1_MASK  (0xF00U)
#define LPDDR_DENALI_CTL_DEVICE2_BYTE0_CS1_SHIFT (8U)
#define LPDDR_DENALI_CTL_DEVICE2_BYTE0_CS1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DEVICE2_BYTE0_CS1_SHIFT)) & LPDDR_DENALI_CTL_DEVICE2_BYTE0_CS1_MASK)

#define LPDDR_DENALI_CTL_DEVICE3_BYTE0_CS0_MASK  (0xF00U)
#define LPDDR_DENALI_CTL_DEVICE3_BYTE0_CS0_SHIFT (8U)
#define LPDDR_DENALI_CTL_DEVICE3_BYTE0_CS0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DEVICE3_BYTE0_CS0_SHIFT)) & LPDDR_DENALI_CTL_DEVICE3_BYTE0_CS0_MASK)

#define LPDDR_DENALI_CTL_DFIBUS_FREQ_F0_MASK     (0x1F00U)
#define LPDDR_DENALI_CTL_DFIBUS_FREQ_F0_SHIFT    (8U)
/*! DFIBUS_FREQ_F0 - Defines the DFI bus frequency for frequency set 0. */
#define LPDDR_DENALI_CTL_DFIBUS_FREQ_F0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DFIBUS_FREQ_F0_SHIFT)) & LPDDR_DENALI_CTL_DFIBUS_FREQ_F0_MASK)

#define LPDDR_DENALI_CTL_DFI_ERROR_INFO_MASK     (0xFFFFF00U)
#define LPDDR_DENALI_CTL_DFI_ERROR_INFO_SHIFT    (8U)
#define LPDDR_DENALI_CTL_DFI_ERROR_INFO(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DFI_ERROR_INFO_SHIFT)) & LPDDR_DENALI_CTL_DFI_ERROR_INFO_MASK)

#define LPDDR_DENALI_CTL_DFI_INV_DATA_CS_MASK    (0x100U)
#define LPDDR_DENALI_CTL_DFI_INV_DATA_CS_SHIFT   (8U)
#define LPDDR_DENALI_CTL_DFI_INV_DATA_CS(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DFI_INV_DATA_CS_SHIFT)) & LPDDR_DENALI_CTL_DFI_INV_DATA_CS_MASK)

#define LPDDR_DENALI_CTL_DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK (0x300U)
#define LPDDR_DENALI_CTL_DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT (8U)
/*! DISABLE_RW_GROUP_W_BNK_CONFLICT
 *  0b00..Allowed
 *  0b01..Prohibited
 */
#define LPDDR_DENALI_CTL_DISABLE_RW_GROUP_W_BNK_CONFLICT(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT)) & LPDDR_DENALI_CTL_DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK)

#define LPDDR_DENALI_CTL_DRAM_CLASS_MASK         (0xF00U)
#define LPDDR_DENALI_CTL_DRAM_CLASS_SHIFT        (8U)
/*! DRAM_CLASS - Defines the class of DRAM memory which is connected to the controller. */
#define LPDDR_DENALI_CTL_DRAM_CLASS(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DRAM_CLASS_SHIFT)) & LPDDR_DENALI_CTL_DRAM_CLASS_MASK)

#define LPDDR_DENALI_CTL_EN_1T_TIMING_MASK       (0x100U)
#define LPDDR_DENALI_CTL_EN_1T_TIMING_SHIFT      (8U)
/*! EN_1T_TIMING
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_EN_1T_TIMING(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_EN_1T_TIMING_SHIFT)) & LPDDR_DENALI_CTL_EN_1T_TIMING_MASK)

#define LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F1_MASK (0x300U)
#define LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F1_SHIFT (8U)
/*! FREQ_CHANGE_TYPE_F1 - Defines the encoded frequency driven out on the cntrl_freq_change_req_type signal during a frequency change operation. */
#define LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F1_SHIFT)) & LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F1_MASK)

#define LPDDR_DENALI_CTL_FSP_STATUS_MASK         (0x100U)
#define LPDDR_DENALI_CTL_FSP_STATUS_SHIFT        (8U)
/*! FSP_STATUS
 *  0b0..No change
 *  0b1..FSP registers were updated
 */
#define LPDDR_DENALI_CTL_FSP_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_FSP_STATUS_SHIFT)) & LPDDR_DENALI_CTL_FSP_STATUS_MASK)

#define LPDDR_DENALI_CTL_INHIBIT_DRAM_CMD_MASK   (0x300U)
#define LPDDR_DENALI_CTL_INHIBIT_DRAM_CMD_SHIFT  (8U)
#define LPDDR_DENALI_CTL_INHIBIT_DRAM_CMD(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INHIBIT_DRAM_CMD_SHIFT)) & LPDDR_DENALI_CTL_INHIBIT_DRAM_CMD_MASK)

#define LPDDR_DENALI_CTL_INT_ACK_INIT_MASK       (0xFF00U)
#define LPDDR_DENALI_CTL_INT_ACK_INIT_SHIFT      (8U)
#define LPDDR_DENALI_CTL_INT_ACK_INIT(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_ACK_INIT_SHIFT)) & LPDDR_DENALI_CTL_INT_ACK_INIT_MASK)

#define LPDDR_DENALI_CTL_INT_MASK_INIT_MASK      (0xFF00U)
#define LPDDR_DENALI_CTL_INT_MASK_INIT_SHIFT     (8U)
#define LPDDR_DENALI_CTL_INT_MASK_INIT(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_MASK_INIT_SHIFT)) & LPDDR_DENALI_CTL_INT_MASK_INIT_MASK)

#define LPDDR_DENALI_CTL_INT_STATUS_INIT_MASK    (0xFF00U)
#define LPDDR_DENALI_CTL_INT_STATUS_INIT_SHIFT   (8U)
#define LPDDR_DENALI_CTL_INT_STATUS_INIT(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_STATUS_INIT_SHIFT)) & LPDDR_DENALI_CTL_INT_STATUS_INIT_MASK)

#define LPDDR_DENALI_CTL_MEMDATA_RATIO_0_MASK    (0x700U)
#define LPDDR_DENALI_CTL_MEMDATA_RATIO_0_SHIFT   (8U)
#define LPDDR_DENALI_CTL_MEMDATA_RATIO_0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MEMDATA_RATIO_0_SHIFT)) & LPDDR_DENALI_CTL_MEMDATA_RATIO_0_MASK)

#define LPDDR_DENALI_CTL_MR2_DATA_F0_0_MASK      (0xFF00U)
#define LPDDR_DENALI_CTL_MR2_DATA_F0_0_SHIFT     (8U)
#define LPDDR_DENALI_CTL_MR2_DATA_F0_0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR2_DATA_F0_0_SHIFT)) & LPDDR_DENALI_CTL_MR2_DATA_F0_0_MASK)

#define LPDDR_DENALI_CTL_MR2_DATA_F1_1_MASK      (0xFF00U)
#define LPDDR_DENALI_CTL_MR2_DATA_F1_1_SHIFT     (8U)
#define LPDDR_DENALI_CTL_MR2_DATA_F1_1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR2_DATA_F1_1_SHIFT)) & LPDDR_DENALI_CTL_MR2_DATA_F1_1_MASK)

#define LPDDR_DENALI_CTL_MR2_DATA_F2_0_MASK      (0xFF00U)
#define LPDDR_DENALI_CTL_MR2_DATA_F2_0_SHIFT     (8U)
#define LPDDR_DENALI_CTL_MR2_DATA_F2_0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR2_DATA_F2_0_SHIFT)) & LPDDR_DENALI_CTL_MR2_DATA_F2_0_MASK)

#define LPDDR_DENALI_CTL_MR3_DATA_F0_1_MASK      (0xFF00U)
#define LPDDR_DENALI_CTL_MR3_DATA_F0_1_SHIFT     (8U)
#define LPDDR_DENALI_CTL_MR3_DATA_F0_1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR3_DATA_F0_1_SHIFT)) & LPDDR_DENALI_CTL_MR3_DATA_F0_1_MASK)

#define LPDDR_DENALI_CTL_MR3_DATA_F2_0_MASK      (0xFF00U)
#define LPDDR_DENALI_CTL_MR3_DATA_F2_0_SHIFT     (8U)
#define LPDDR_DENALI_CTL_MR3_DATA_F2_0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR3_DATA_F2_0_SHIFT)) & LPDDR_DENALI_CTL_MR3_DATA_F2_0_MASK)

#define LPDDR_DENALI_CTL_MR4_DATA_F1_1_MASK      (0xFF00U)
#define LPDDR_DENALI_CTL_MR4_DATA_F1_1_SHIFT     (8U)
#define LPDDR_DENALI_CTL_MR4_DATA_F1_1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR4_DATA_F1_1_SHIFT)) & LPDDR_DENALI_CTL_MR4_DATA_F1_1_MASK)

#define LPDDR_DENALI_CTL_MR8_DATA_0_MASK         (0xFF00U)
#define LPDDR_DENALI_CTL_MR8_DATA_0_SHIFT        (8U)
#define LPDDR_DENALI_CTL_MR8_DATA_0(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR8_DATA_0_SHIFT)) & LPDDR_DENALI_CTL_MR8_DATA_0_MASK)

#define LPDDR_DENALI_CTL_MR11_DATA_F1_1_MASK     (0xFF00U)
#define LPDDR_DENALI_CTL_MR11_DATA_F1_1_SHIFT    (8U)
#define LPDDR_DENALI_CTL_MR11_DATA_F1_1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR11_DATA_F1_1_SHIFT)) & LPDDR_DENALI_CTL_MR11_DATA_F1_1_MASK)

#define LPDDR_DENALI_CTL_MR12_DATA_F0_0_MASK     (0xFF00U)
#define LPDDR_DENALI_CTL_MR12_DATA_F0_0_SHIFT    (8U)
#define LPDDR_DENALI_CTL_MR12_DATA_F0_0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR12_DATA_F0_0_SHIFT)) & LPDDR_DENALI_CTL_MR12_DATA_F0_0_MASK)

#define LPDDR_DENALI_CTL_MR12_DATA_F2_1_MASK     (0xFF00U)
#define LPDDR_DENALI_CTL_MR12_DATA_F2_1_SHIFT    (8U)
#define LPDDR_DENALI_CTL_MR12_DATA_F2_1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR12_DATA_F2_1_SHIFT)) & LPDDR_DENALI_CTL_MR12_DATA_F2_1_MASK)

#define LPDDR_DENALI_CTL_MR14_DATA_F2_1_MASK     (0xFF00U)
#define LPDDR_DENALI_CTL_MR14_DATA_F2_1_SHIFT    (8U)
#define LPDDR_DENALI_CTL_MR14_DATA_F2_1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR14_DATA_F2_1_SHIFT)) & LPDDR_DENALI_CTL_MR14_DATA_F2_1_MASK)

#define LPDDR_DENALI_CTL_MR22_DATA_F0_1_MASK     (0xFF00U)
#define LPDDR_DENALI_CTL_MR22_DATA_F0_1_SHIFT    (8U)
#define LPDDR_DENALI_CTL_MR22_DATA_F0_1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR22_DATA_F0_1_SHIFT)) & LPDDR_DENALI_CTL_MR22_DATA_F0_1_MASK)

#define LPDDR_DENALI_CTL_MR22_DATA_F2_0_MASK     (0xFF00U)
#define LPDDR_DENALI_CTL_MR22_DATA_F2_0_SHIFT    (8U)
#define LPDDR_DENALI_CTL_MR22_DATA_F2_0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR22_DATA_F2_0_SHIFT)) & LPDDR_DENALI_CTL_MR22_DATA_F2_0_MASK)

#define LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F0_MASK (0x100U)
#define LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F0_SHIFT (8U)
/*! MR_FSP_DATA_VALID_F0
 *  0b0..Memory training is in progress or was not performed
 *  0b1..Memory was trained
 */
#define LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F0_SHIFT)) & LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F0_MASK)

#define LPDDR_DENALI_CTL_NWR_F2_MASK             (0xFF00U)
#define LPDDR_DENALI_CTL_NWR_F2_SHIFT            (8U)
#define LPDDR_DENALI_CTL_NWR_F2(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_NWR_F2_SHIFT)) & LPDDR_DENALI_CTL_NWR_F2_MASK)

#define LPDDR_DENALI_CTL_ODT_EN_F0_MASK          (0x100U)
#define LPDDR_DENALI_CTL_ODT_EN_F0_SHIFT         (8U)
#define LPDDR_DENALI_CTL_ODT_EN_F0(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ODT_EN_F0_SHIFT)) & LPDDR_DENALI_CTL_ODT_EN_F0_MASK)

#define LPDDR_DENALI_CTL_ODT_WR_MAP_CS0_MASK     (0x300U)
#define LPDDR_DENALI_CTL_ODT_WR_MAP_CS0_SHIFT    (8U)
#define LPDDR_DENALI_CTL_ODT_WR_MAP_CS0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ODT_WR_MAP_CS0_SHIFT)) & LPDDR_DENALI_CTL_ODT_WR_MAP_CS0_MASK)

#define LPDDR_DENALI_CTL_PBR_CONT_REQ_EN_MASK    (0x100U)
#define LPDDR_DENALI_CTL_PBR_CONT_REQ_EN_SHIFT   (8U)
/*! PBR_CONT_REQ_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_PBR_CONT_REQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PBR_CONT_REQ_EN_SHIFT)) & LPDDR_DENALI_CTL_PBR_CONT_REQ_EN_MASK)

#define LPDDR_DENALI_CTL_PBR_NUMERIC_ORDER_MASK  (0x100U)
#define LPDDR_DENALI_CTL_PBR_NUMERIC_ORDER_SHIFT (8U)
/*! PBR_NUMERIC_ORDER
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_PBR_NUMERIC_ORDER(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PBR_NUMERIC_ORDER_SHIFT)) & LPDDR_DENALI_CTL_PBR_NUMERIC_ORDER_MASK)

#define LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F2_MASK  (0x1F00U)
#define LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F2_SHIFT (8U)
#define LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F2_SHIFT)) & LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F2_MASK)

#define LPDDR_DENALI_CTL_RD_PREAMBLE_TRAINING_EN_MASK (0x100U)
#define LPDDR_DENALI_CTL_RD_PREAMBLE_TRAINING_EN_SHIFT (8U)
/*! RD_PREAMBLE_TRAINING_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_RD_PREAMBLE_TRAINING_EN(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RD_PREAMBLE_TRAINING_EN_SHIFT)) & LPDDR_DENALI_CTL_RD_PREAMBLE_TRAINING_EN_MASK)

#define LPDDR_DENALI_CTL_RD_TO_ODTH_F1_MASK      (0x3F00U)
#define LPDDR_DENALI_CTL_RD_TO_ODTH_F1_SHIFT     (8U)
#define LPDDR_DENALI_CTL_RD_TO_ODTH_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RD_TO_ODTH_F1_SHIFT)) & LPDDR_DENALI_CTL_RD_TO_ODTH_F1_MASK)

#define LPDDR_DENALI_CTL_RW2MRW_DLY_F2_MASK      (0x1F00U)
#define LPDDR_DENALI_CTL_RW2MRW_DLY_F2_SHIFT     (8U)
#define LPDDR_DENALI_CTL_RW2MRW_DLY_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RW2MRW_DLY_F2_SHIFT)) & LPDDR_DENALI_CTL_RW2MRW_DLY_F2_MASK)

#define LPDDR_DENALI_CTL_RW_SAME_EN_MASK         (0x100U)
#define LPDDR_DENALI_CTL_RW_SAME_EN_SHIFT        (8U)
/*! RW_SAME_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_RW_SAME_EN(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RW_SAME_EN_SHIFT)) & LPDDR_DENALI_CTL_RW_SAME_EN_MASK)

#define LPDDR_DENALI_CTL_TCKEHCMD_F0_MASK        (0x1F00U)
#define LPDDR_DENALI_CTL_TCKEHCMD_F0_SHIFT       (8U)
#define LPDDR_DENALI_CTL_TCKEHCMD_F0(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKEHCMD_F0_SHIFT)) & LPDDR_DENALI_CTL_TCKEHCMD_F0_MASK)

#define LPDDR_DENALI_CTL_TCKEHCMD_F1_MASK        (0x1F00U)
#define LPDDR_DENALI_CTL_TCKEHCMD_F1_SHIFT       (8U)
#define LPDDR_DENALI_CTL_TCKEHCMD_F1(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKEHCMD_F1_SHIFT)) & LPDDR_DENALI_CTL_TCKEHCMD_F1_MASK)

#define LPDDR_DENALI_CTL_TCKEHCMD_F2_MASK        (0x1F00U)
#define LPDDR_DENALI_CTL_TCKEHCMD_F2_SHIFT       (8U)
#define LPDDR_DENALI_CTL_TCKEHCMD_F2(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKEHCMD_F2_SHIFT)) & LPDDR_DENALI_CTL_TCKEHCMD_F2_MASK)

#define LPDDR_DENALI_CTL_TCKEHCS_F1_MASK         (0x1F00U)
#define LPDDR_DENALI_CTL_TCKEHCS_F1_SHIFT        (8U)
#define LPDDR_DENALI_CTL_TCKEHCS_F1(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKEHCS_F1_SHIFT)) & LPDDR_DENALI_CTL_TCKEHCS_F1_MASK)

#define LPDDR_DENALI_CTL_TCKELPD_F0_MASK         (0x1F00U)
#define LPDDR_DENALI_CTL_TCKELPD_F0_SHIFT        (8U)
#define LPDDR_DENALI_CTL_TCKELPD_F0(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKELPD_F0_SHIFT)) & LPDDR_DENALI_CTL_TCKELPD_F0_MASK)

#define LPDDR_DENALI_CTL_TCKELPD_F1_MASK         (0x1F00U)
#define LPDDR_DENALI_CTL_TCKELPD_F1_SHIFT        (8U)
#define LPDDR_DENALI_CTL_TCKELPD_F1(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKELPD_F1_SHIFT)) & LPDDR_DENALI_CTL_TCKELPD_F1_MASK)

#define LPDDR_DENALI_CTL_TCKELPD_F2_MASK         (0x1F00U)
#define LPDDR_DENALI_CTL_TCKELPD_F2_SHIFT        (8U)
#define LPDDR_DENALI_CTL_TCKELPD_F2(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKELPD_F2_SHIFT)) & LPDDR_DENALI_CTL_TCKELPD_F2_MASK)

#define LPDDR_DENALI_CTL_TCKFSPX_F0_MASK         (0x1F00U)
#define LPDDR_DENALI_CTL_TCKFSPX_F0_SHIFT        (8U)
#define LPDDR_DENALI_CTL_TCKFSPX_F0(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKFSPX_F0_SHIFT)) & LPDDR_DENALI_CTL_TCKFSPX_F0_MASK)

#define LPDDR_DENALI_CTL_TCSCKE_F0_MASK          (0x1F00U)
#define LPDDR_DENALI_CTL_TCSCKE_F0_SHIFT         (8U)
#define LPDDR_DENALI_CTL_TCSCKE_F0(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCSCKE_F0_SHIFT)) & LPDDR_DENALI_CTL_TCSCKE_F0_MASK)

#define LPDDR_DENALI_CTL_TCSCKE_F2_MASK          (0x1F00U)
#define LPDDR_DENALI_CTL_TCSCKE_F2_SHIFT         (8U)
#define LPDDR_DENALI_CTL_TCSCKE_F2(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCSCKE_F2_SHIFT)) & LPDDR_DENALI_CTL_TCSCKE_F2_MASK)

#define LPDDR_DENALI_CTL_TDAL_F2_MASK            (0xFF00U)
#define LPDDR_DENALI_CTL_TDAL_F2_SHIFT           (8U)
#define LPDDR_DENALI_CTL_TDAL_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDAL_F2_SHIFT)) & LPDDR_DENALI_CTL_TDAL_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_DRAM_CLK_DISABLE_MASK (0xF00U)
#define LPDDR_DENALI_CTL_TDFI_DRAM_CLK_DISABLE_SHIFT (8U)
#define LPDDR_DENALI_CTL_TDFI_DRAM_CLK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_DRAM_CLK_DISABLE_SHIFT)) & LPDDR_DENALI_CTL_TDFI_DRAM_CLK_DISABLE_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F2_MASK (0x700U)
#define LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F2_SHIFT (8U)
#define LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F2(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_RDDATA_EN_MASK     (0x7F00U)
#define LPDDR_DENALI_CTL_TDFI_RDDATA_EN_SHIFT    (8U)
#define LPDDR_DENALI_CTL_TDFI_RDDATA_EN(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_RDDATA_EN_SHIFT)) & LPDDR_DENALI_CTL_TDFI_RDDATA_EN_MASK)

#define LPDDR_DENALI_CTL_TDFI_WRCSLAT_F1_MASK    (0x7F00U)
#define LPDDR_DENALI_CTL_TDFI_WRCSLAT_F1_SHIFT   (8U)
#define LPDDR_DENALI_CTL_TDFI_WRCSLAT_F1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_WRCSLAT_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_WRCSLAT_F1_MASK)

#define LPDDR_DENALI_CTL_TDQSCK_MIN_F0_MASK      (0x700U)
#define LPDDR_DENALI_CTL_TDQSCK_MIN_F0_SHIFT     (8U)
#define LPDDR_DENALI_CTL_TDQSCK_MIN_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDQSCK_MIN_F0_SHIFT)) & LPDDR_DENALI_CTL_TDQSCK_MIN_F0_MASK)

#define LPDDR_DENALI_CTL_TDQSCK_MIN_F2_MASK      (0x700U)
#define LPDDR_DENALI_CTL_TDQSCK_MIN_F2_SHIFT     (8U)
#define LPDDR_DENALI_CTL_TDQSCK_MIN_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDQSCK_MIN_F2_SHIFT)) & LPDDR_DENALI_CTL_TDQSCK_MIN_F2_MASK)

#define LPDDR_DENALI_CTL_TINIT_F0_MASK           (0xFFFFFF00U)
#define LPDDR_DENALI_CTL_TINIT_F0_SHIFT          (8U)
#define LPDDR_DENALI_CTL_TINIT_F0(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TINIT_F0_SHIFT)) & LPDDR_DENALI_CTL_TINIT_F0_MASK)

#define LPDDR_DENALI_CTL_TMOD_F0_MASK            (0xFF00U)
#define LPDDR_DENALI_CTL_TMOD_F0_SHIFT           (8U)
#define LPDDR_DENALI_CTL_TMOD_F0(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TMOD_F0_SHIFT)) & LPDDR_DENALI_CTL_TMOD_F0_MASK)

#define LPDDR_DENALI_CTL_TODTH_RD_F1_MASK        (0xF00U)
#define LPDDR_DENALI_CTL_TODTH_RD_F1_SHIFT       (8U)
#define LPDDR_DENALI_CTL_TODTH_RD_F1(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TODTH_RD_F1_SHIFT)) & LPDDR_DENALI_CTL_TODTH_RD_F1_MASK)

#define LPDDR_DENALI_CTL_TODTH_WR_F0_MASK        (0xF00U)
#define LPDDR_DENALI_CTL_TODTH_WR_F0_SHIFT       (8U)
#define LPDDR_DENALI_CTL_TODTH_WR_F0(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TODTH_WR_F0_SHIFT)) & LPDDR_DENALI_CTL_TODTH_WR_F0_MASK)

#define LPDDR_DENALI_CTL_TOSCO_F2_MASK           (0xFF00U)
#define LPDDR_DENALI_CTL_TOSCO_F2_SHIFT          (8U)
#define LPDDR_DENALI_CTL_TOSCO_F2(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TOSCO_F2_SHIFT)) & LPDDR_DENALI_CTL_TOSCO_F2_MASK)

#define LPDDR_DENALI_CTL_TPPD_MASK               (0x700U)
#define LPDDR_DENALI_CTL_TPPD_SHIFT              (8U)
#define LPDDR_DENALI_CTL_TPPD(x)                 (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TPPD_SHIFT)) & LPDDR_DENALI_CTL_TPPD_MASK)

#define LPDDR_DENALI_CTL_TRCD_F0_MASK            (0xFF00U)
#define LPDDR_DENALI_CTL_TRCD_F0_SHIFT           (8U)
#define LPDDR_DENALI_CTL_TRCD_F0(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRCD_F0_SHIFT)) & LPDDR_DENALI_CTL_TRCD_F0_MASK)

#define LPDDR_DENALI_CTL_TRCD_F2_MASK            (0xFF00U)
#define LPDDR_DENALI_CTL_TRCD_F2_SHIFT           (8U)
#define LPDDR_DENALI_CTL_TRCD_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRCD_F2_SHIFT)) & LPDDR_DENALI_CTL_TRCD_F2_MASK)

#define LPDDR_DENALI_CTL_TRC_F0_MASK             (0x1FF00U)
#define LPDDR_DENALI_CTL_TRC_F0_SHIFT            (8U)
#define LPDDR_DENALI_CTL_TRC_F0(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRC_F0_SHIFT)) & LPDDR_DENALI_CTL_TRC_F0_MASK)

#define LPDDR_DENALI_CTL_TRC_F2_MASK             (0x1FF00U)
#define LPDDR_DENALI_CTL_TRC_F2_SHIFT            (8U)
#define LPDDR_DENALI_CTL_TRC_F2(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRC_F2_SHIFT)) & LPDDR_DENALI_CTL_TRC_F2_MASK)

#define LPDDR_DENALI_CTL_TRP_AB_F2_MASK          (0xFF00U)
#define LPDDR_DENALI_CTL_TRP_AB_F2_SHIFT         (8U)
#define LPDDR_DENALI_CTL_TRP_AB_F2(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRP_AB_F2_SHIFT)) & LPDDR_DENALI_CTL_TRP_AB_F2_MASK)

#define LPDDR_DENALI_CTL_TRP_F1_MASK             (0xFF00U)
#define LPDDR_DENALI_CTL_TRP_F1_SHIFT            (8U)
#define LPDDR_DENALI_CTL_TRP_F1(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRP_F1_SHIFT)) & LPDDR_DENALI_CTL_TRP_F1_MASK)

#define LPDDR_DENALI_CTL_TRTP_F1_MASK            (0xFF00U)
#define LPDDR_DENALI_CTL_TRTP_F1_SHIFT           (8U)
#define LPDDR_DENALI_CTL_TRTP_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRTP_F1_SHIFT)) & LPDDR_DENALI_CTL_TRTP_F1_MASK)

#define LPDDR_DENALI_CTL_TRTP_F2_MASK            (0xFF00U)
#define LPDDR_DENALI_CTL_TRTP_F2_SHIFT           (8U)
#define LPDDR_DENALI_CTL_TRTP_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRTP_F2_SHIFT)) & LPDDR_DENALI_CTL_TRTP_F2_MASK)

#define LPDDR_DENALI_CTL_TSREF2PHYMSTR_MASK      (0x3F00U)
#define LPDDR_DENALI_CTL_TSREF2PHYMSTR_SHIFT     (8U)
#define LPDDR_DENALI_CTL_TSREF2PHYMSTR(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TSREF2PHYMSTR_SHIFT)) & LPDDR_DENALI_CTL_TSREF2PHYMSTR_MASK)

#define LPDDR_DENALI_CTL_TZQCKE_F0_MASK          (0xF00U)
#define LPDDR_DENALI_CTL_TZQCKE_F0_SHIFT         (8U)
#define LPDDR_DENALI_CTL_TZQCKE_F0(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TZQCKE_F0_SHIFT)) & LPDDR_DENALI_CTL_TZQCKE_F0_MASK)

#define LPDDR_DENALI_CTL_TZQCKE_F2_MASK          (0xF00U)
#define LPDDR_DENALI_CTL_TZQCKE_F2_SHIFT         (8U)
#define LPDDR_DENALI_CTL_TZQCKE_F2(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TZQCKE_F2_SHIFT)) & LPDDR_DENALI_CTL_TZQCKE_F2_MASK)

#define LPDDR_DENALI_CTL_UPDATE_ERROR_STATUS_MASK (0x7F00U)
#define LPDDR_DENALI_CTL_UPDATE_ERROR_STATUS_SHIFT (8U)
#define LPDDR_DENALI_CTL_UPDATE_ERROR_STATUS(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_UPDATE_ERROR_STATUS_SHIFT)) & LPDDR_DENALI_CTL_UPDATE_ERROR_STATUS_MASK)

#define LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F0_MASK  (0x1F00U)
#define LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F0_SHIFT (8U)
#define LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F0_SHIFT)) & LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F0_MASK)

#define LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F1_MASK  (0x1F00U)
#define LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F1_SHIFT (8U)
#define LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F1_SHIFT)) & LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F1_MASK)

#define LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F2_MASK  (0x1F00U)
#define LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F2_SHIFT (8U)
#define LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F2_SHIFT)) & LPDDR_DENALI_CTL_W2W_DIFFCS_DLY_F2_MASK)

#define LPDDR_DENALI_CTL_WRLAT_ADJ_F0_MASK       (0x7F00U)
#define LPDDR_DENALI_CTL_WRLAT_ADJ_F0_SHIFT      (8U)
#define LPDDR_DENALI_CTL_WRLAT_ADJ_F0(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_WRLAT_ADJ_F0_SHIFT)) & LPDDR_DENALI_CTL_WRLAT_ADJ_F0_MASK)

#define LPDDR_DENALI_CTL_WRLAT_ADJ_F1_MASK       (0x7F00U)
#define LPDDR_DENALI_CTL_WRLAT_ADJ_F1_SHIFT      (8U)
#define LPDDR_DENALI_CTL_WRLAT_ADJ_F1(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_WRLAT_ADJ_F1_SHIFT)) & LPDDR_DENALI_CTL_WRLAT_ADJ_F1_MASK)

#define LPDDR_DENALI_CTL_WRLAT_ADJ_F2_MASK       (0x7F00U)
#define LPDDR_DENALI_CTL_WRLAT_ADJ_F2_SHIFT      (8U)
#define LPDDR_DENALI_CTL_WRLAT_ADJ_F2(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_WRLAT_ADJ_F2_SHIFT)) & LPDDR_DENALI_CTL_WRLAT_ADJ_F2_MASK)

#define LPDDR_DENALI_CTL_WRLAT_F0_MASK           (0x7F00U)
#define LPDDR_DENALI_CTL_WRLAT_F0_SHIFT          (8U)
#define LPDDR_DENALI_CTL_WRLAT_F0(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_WRLAT_F0_SHIFT)) & LPDDR_DENALI_CTL_WRLAT_F0_MASK)

#define LPDDR_DENALI_CTL_WRLAT_F2_MASK           (0x7F00U)
#define LPDDR_DENALI_CTL_WRLAT_F2_SHIFT          (8U)
#define LPDDR_DENALI_CTL_WRLAT_F2(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_WRLAT_F2_SHIFT)) & LPDDR_DENALI_CTL_WRLAT_F2_MASK)

#define LPDDR_DENALI_CTL_WR_ORDER_REQ_MASK       (0x300U)
#define LPDDR_DENALI_CTL_WR_ORDER_REQ_SHIFT      (8U)
#define LPDDR_DENALI_CTL_WR_ORDER_REQ(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_WR_ORDER_REQ_SHIFT)) & LPDDR_DENALI_CTL_WR_ORDER_REQ_MASK)

#define LPDDR_DENALI_CTL_WR_TO_ODTH_F0_MASK      (0x3F00U)
#define LPDDR_DENALI_CTL_WR_TO_ODTH_F0_SHIFT     (8U)
#define LPDDR_DENALI_CTL_WR_TO_ODTH_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_WR_TO_ODTH_F0_SHIFT)) & LPDDR_DENALI_CTL_WR_TO_ODTH_F0_MASK)

#define LPDDR_DENALI_CTL_ZQINIT_F1_MASK          (0xFFF00U)
#define LPDDR_DENALI_CTL_ZQINIT_F1_SHIFT         (8U)
#define LPDDR_DENALI_CTL_ZQINIT_F1(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQINIT_F1_SHIFT)) & LPDDR_DENALI_CTL_ZQINIT_F1_MASK)

#define LPDDR_DENALI_CTL_ZQ_SW_REQ_START_LATCH_MAP_MASK (0x300U)
#define LPDDR_DENALI_CTL_ZQ_SW_REQ_START_LATCH_MAP_SHIFT (8U)
/*! ZQ_SW_REQ_START_LATCH_MAP - Specifies which chip selects will simultaneously receive a ZQ start
 *    or latch command once the ZQ_REQ bit is written with a ZQ Start or ZQ Latch command.
 */
#define LPDDR_DENALI_CTL_ZQ_SW_REQ_START_LATCH_MAP(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQ_SW_REQ_START_LATCH_MAP_SHIFT)) & LPDDR_DENALI_CTL_ZQ_SW_REQ_START_LATCH_MAP_MASK)

#define LPDDR_DENALI_CTL_AGE_COUNT_MASK          (0xFF0000U)
#define LPDDR_DENALI_CTL_AGE_COUNT_SHIFT         (16U)
#define LPDDR_DENALI_CTL_AGE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AGE_COUNT_SHIFT)) & LPDDR_DENALI_CTL_AGE_COUNT_MASK)

#define LPDDR_DENALI_CTL_AREF_PBR_CONT_EN_THRESHOLD_MASK (0x1F0000U)
#define LPDDR_DENALI_CTL_AREF_PBR_CONT_EN_THRESHOLD_SHIFT (16U)
/*! AREF_PBR_CONT_EN_THRESHOLD - Sets the auto-refresh request count threshold when the PBR continuous refresh request enable will be asserted. */
#define LPDDR_DENALI_CTL_AREF_PBR_CONT_EN_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AREF_PBR_CONT_EN_THRESHOLD_SHIFT)) & LPDDR_DENALI_CTL_AREF_PBR_CONT_EN_THRESHOLD_MASK)

#define LPDDR_DENALI_CTL_AXI0_ALL_STROBES_USED_ENABLE_MASK (0x10000U)
#define LPDDR_DENALI_CTL_AXI0_ALL_STROBES_USED_ENABLE_SHIFT (16U)
#define LPDDR_DENALI_CTL_AXI0_ALL_STROBES_USED_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI0_ALL_STROBES_USED_ENABLE_SHIFT)) & LPDDR_DENALI_CTL_AXI0_ALL_STROBES_USED_ENABLE_MASK)

#define LPDDR_DENALI_CTL_AXI0_FIFO_TYPE_REG_MASK (0x30000U)
#define LPDDR_DENALI_CTL_AXI0_FIFO_TYPE_REG_SHIFT (16U)
#define LPDDR_DENALI_CTL_AXI0_FIFO_TYPE_REG(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI0_FIFO_TYPE_REG_SHIFT)) & LPDDR_DENALI_CTL_AXI0_FIFO_TYPE_REG_MASK)

#define LPDDR_DENALI_CTL_AXI1_W_PRIORITY_MASK    (0x70000U)
#define LPDDR_DENALI_CTL_AXI1_W_PRIORITY_SHIFT   (16U)
#define LPDDR_DENALI_CTL_AXI1_W_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI1_W_PRIORITY_SHIFT)) & LPDDR_DENALI_CTL_AXI1_W_PRIORITY_MASK)

#define LPDDR_DENALI_CTL_AXI2_R_PRIORITY_MASK    (0x70000U)
#define LPDDR_DENALI_CTL_AXI2_R_PRIORITY_SHIFT   (16U)
#define LPDDR_DENALI_CTL_AXI2_R_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI2_R_PRIORITY_SHIFT)) & LPDDR_DENALI_CTL_AXI2_R_PRIORITY_MASK)

#define LPDDR_DENALI_CTL_AXI3_FIXED_PORT_PRIORITY_ENABLE_MASK (0x10000U)
#define LPDDR_DENALI_CTL_AXI3_FIXED_PORT_PRIORITY_ENABLE_SHIFT (16U)
#define LPDDR_DENALI_CTL_AXI3_FIXED_PORT_PRIORITY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI3_FIXED_PORT_PRIORITY_ENABLE_SHIFT)) & LPDDR_DENALI_CTL_AXI3_FIXED_PORT_PRIORITY_ENABLE_MASK)

#define LPDDR_DENALI_CTL_BANK_DIFF_MASK          (0x30000U)
#define LPDDR_DENALI_CTL_BANK_DIFF_SHIFT         (16U)
#define LPDDR_DENALI_CTL_BANK_DIFF(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_BANK_DIFF_SHIFT)) & LPDDR_DENALI_CTL_BANK_DIFF_MASK)

#define LPDDR_DENALI_CTL_BANK_SPLIT_EN_MASK      (0x10000U)
#define LPDDR_DENALI_CTL_BANK_SPLIT_EN_SHIFT     (16U)
/*! BANK_SPLIT_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_BANK_SPLIT_EN(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_BANK_SPLIT_EN_SHIFT)) & LPDDR_DENALI_CTL_BANK_SPLIT_EN_MASK)

#define LPDDR_DENALI_CTL_BSTLEN_MASK             (0x1F0000U)
#define LPDDR_DENALI_CTL_BSTLEN_SHIFT            (16U)
#define LPDDR_DENALI_CTL_BSTLEN(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_BSTLEN_SHIFT)) & LPDDR_DENALI_CTL_BSTLEN_MASK)

#define LPDDR_DENALI_CTL_CASLAT_LIN_F1_MASK      (0x7F0000U)
#define LPDDR_DENALI_CTL_CASLAT_LIN_F1_SHIFT     (16U)
#define LPDDR_DENALI_CTL_CASLAT_LIN_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CASLAT_LIN_F1_SHIFT)) & LPDDR_DENALI_CTL_CASLAT_LIN_F1_MASK)

#define LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F0_MASK  (0x10000U)
#define LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F0_SHIFT (16U)
#define LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F0_SHIFT)) & LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F0_MASK)

#define LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F2_MASK  (0x10000U)
#define LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F2_SHIFT (16U)
#define LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F2_SHIFT)) & LPDDR_DENALI_CTL_CA_DEFAULT_VAL_F2_MASK)

#define LPDDR_DENALI_CTL_CONTROLLER_BUSY_MASK    (0x10000U)
#define LPDDR_DENALI_CTL_CONTROLLER_BUSY_SHIFT   (16U)
/*! CONTROLLER_BUSY
 *  0b0..Controller is not busy
 *  0b1..Controller is busy
 */
#define LPDDR_DENALI_CTL_CONTROLLER_BUSY(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CONTROLLER_BUSY_SHIFT)) & LPDDR_DENALI_CTL_CONTROLLER_BUSY_MASK)

#define LPDDR_DENALI_CTL_CONTROLLER_ID_MASK      (0xFFFF0000U)
#define LPDDR_DENALI_CTL_CONTROLLER_ID_SHIFT     (16U)
#define LPDDR_DENALI_CTL_CONTROLLER_ID(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CONTROLLER_ID_SHIFT)) & LPDDR_DENALI_CTL_CONTROLLER_ID_MASK)

#define LPDDR_DENALI_CTL_CS_LOWER_ADDR_EN_MASK   (0x10000U)
#define LPDDR_DENALI_CTL_CS_LOWER_ADDR_EN_SHIFT  (16U)
/*! CS_LOWER_ADDR_EN
 *  0b0..The address map is CS - Row - Bank - Column - Datapath
 *  0b1..The address map is Row - CS - Bank - Column - Datapath
 */
#define LPDDR_DENALI_CTL_CS_LOWER_ADDR_EN(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CS_LOWER_ADDR_EN_SHIFT)) & LPDDR_DENALI_CTL_CS_LOWER_ADDR_EN_MASK)

#define LPDDR_DENALI_CTL_CS_MAP_MASK             (0x30000U)
#define LPDDR_DENALI_CTL_CS_MAP_SHIFT            (16U)
#define LPDDR_DENALI_CTL_CS_MAP(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CS_MAP_SHIFT)) & LPDDR_DENALI_CTL_CS_MAP_MASK)

#define LPDDR_DENALI_CTL_DEVICE0_BYTE0_CS0_MASK  (0xF0000U)
#define LPDDR_DENALI_CTL_DEVICE0_BYTE0_CS0_SHIFT (16U)
#define LPDDR_DENALI_CTL_DEVICE0_BYTE0_CS0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DEVICE0_BYTE0_CS0_SHIFT)) & LPDDR_DENALI_CTL_DEVICE0_BYTE0_CS0_MASK)

#define LPDDR_DENALI_CTL_DEVICE3_BYTE0_CS1_MASK  (0xF0000U)
#define LPDDR_DENALI_CTL_DEVICE3_BYTE0_CS1_SHIFT (16U)
#define LPDDR_DENALI_CTL_DEVICE3_BYTE0_CS1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DEVICE3_BYTE0_CS1_SHIFT)) & LPDDR_DENALI_CTL_DEVICE3_BYTE0_CS1_MASK)

#define LPDDR_DENALI_CTL_DFIBUS_FREQ_F1_MASK     (0x1F0000U)
#define LPDDR_DENALI_CTL_DFIBUS_FREQ_F1_SHIFT    (16U)
/*! DFIBUS_FREQ_F1 - Defines the DFI bus frequency for frequency set 1. */
#define LPDDR_DENALI_CTL_DFIBUS_FREQ_F1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DFIBUS_FREQ_F1_SHIFT)) & LPDDR_DENALI_CTL_DFIBUS_FREQ_F1_MASK)

#define LPDDR_DENALI_CTL_DISABLE_MEMORY_MASKED_WRITE_MASK (0x10000U)
#define LPDDR_DENALI_CTL_DISABLE_MEMORY_MASKED_WRITE_SHIFT (16U)
/*! DISABLE_MEMORY_MASKED_WRITE
 *  0b0..Allow masked writes
 *  0b1..Restrict masked writes
 */
#define LPDDR_DENALI_CTL_DISABLE_MEMORY_MASKED_WRITE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DISABLE_MEMORY_MASKED_WRITE_SHIFT)) & LPDDR_DENALI_CTL_DISABLE_MEMORY_MASKED_WRITE_MASK)

#define LPDDR_DENALI_CTL_DQS_OSC_IN_PROGRESS_STATUS_MASK (0x10000U)
#define LPDDR_DENALI_CTL_DQS_OSC_IN_PROGRESS_STATUS_SHIFT (16U)
/*! DQS_OSC_IN_PROGRESS_STATUS
 *  0b0..Not in progress
 *  0b1..In progress
 */
#define LPDDR_DENALI_CTL_DQS_OSC_IN_PROGRESS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DQS_OSC_IN_PROGRESS_STATUS_SHIFT)) & LPDDR_DENALI_CTL_DQS_OSC_IN_PROGRESS_STATUS_MASK)

#define LPDDR_DENALI_CTL_DRAM_CLK_DISABLE_MASK   (0x30000U)
#define LPDDR_DENALI_CTL_DRAM_CLK_DISABLE_SHIFT  (16U)
/*! DRAM_CLK_DISABLE
 *  0b00..Enable
 *  0b01..Disable
 */
#define LPDDR_DENALI_CTL_DRAM_CLK_DISABLE(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DRAM_CLK_DISABLE_SHIFT)) & LPDDR_DENALI_CTL_DRAM_CLK_DISABLE_MASK)

#define LPDDR_DENALI_CTL_ENABLE_QUICK_SREFRESH_MASK (0x10000U)
#define LPDDR_DENALI_CTL_ENABLE_QUICK_SREFRESH_SHIFT (16U)
#define LPDDR_DENALI_CTL_ENABLE_QUICK_SREFRESH(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ENABLE_QUICK_SREFRESH_SHIFT)) & LPDDR_DENALI_CTL_ENABLE_QUICK_SREFRESH_MASK)

#define LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F2_MASK (0x30000U)
#define LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F2_SHIFT (16U)
/*! FREQ_CHANGE_TYPE_F2 - Defines the encoded frequency driven out on the cntrl_freq_change_req_type signal during a frequency change operation. */
#define LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F2_SHIFT)) & LPDDR_DENALI_CTL_FREQ_CHANGE_TYPE_F2_MASK)

#define LPDDR_DENALI_CTL_FSP_OP_CURRENT_MASK     (0x10000U)
#define LPDDR_DENALI_CTL_FSP_OP_CURRENT_SHIFT    (16U)
/*! FSP_OP_CURRENT
 *  0b0..FSP set 0
 *  0b1..FSP set 1
 */
#define LPDDR_DENALI_CTL_FSP_OP_CURRENT(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_FSP_OP_CURRENT_SHIFT)) & LPDDR_DENALI_CTL_FSP_OP_CURRENT_MASK)

#define LPDDR_DENALI_CTL_FUNC_VALID_CYCLES_MASK  (0xF0000U)
#define LPDDR_DENALI_CTL_FUNC_VALID_CYCLES_SHIFT (16U)
/*! FUNC_VALID_CYCLES - Number of cycles to hold dfi_function_valid asserted. */
#define LPDDR_DENALI_CTL_FUNC_VALID_CYCLES(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_FUNC_VALID_CYCLES_SHIFT)) & LPDDR_DENALI_CTL_FUNC_VALID_CYCLES_MASK)

#define LPDDR_DENALI_CTL_INT_ACK_LOWPOWER_MASK   (0xFFFF0000U)
#define LPDDR_DENALI_CTL_INT_ACK_LOWPOWER_SHIFT  (16U)
#define LPDDR_DENALI_CTL_INT_ACK_LOWPOWER(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_ACK_LOWPOWER_SHIFT)) & LPDDR_DENALI_CTL_INT_ACK_LOWPOWER_MASK)

#define LPDDR_DENALI_CTL_INT_ACK_MISC_MASK       (0xFF0000U)
#define LPDDR_DENALI_CTL_INT_ACK_MISC_SHIFT      (16U)
#define LPDDR_DENALI_CTL_INT_ACK_MISC(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_ACK_MISC_SHIFT)) & LPDDR_DENALI_CTL_INT_ACK_MISC_MASK)

#define LPDDR_DENALI_CTL_INT_ACK_USERIF_MASK     (0xFFFF0000U)
#define LPDDR_DENALI_CTL_INT_ACK_USERIF_SHIFT    (16U)
#define LPDDR_DENALI_CTL_INT_ACK_USERIF(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_ACK_USERIF_SHIFT)) & LPDDR_DENALI_CTL_INT_ACK_USERIF_MASK)

#define LPDDR_DENALI_CTL_INT_MASK_LOWPOWER_MASK  (0xFFFF0000U)
#define LPDDR_DENALI_CTL_INT_MASK_LOWPOWER_SHIFT (16U)
#define LPDDR_DENALI_CTL_INT_MASK_LOWPOWER(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_MASK_LOWPOWER_SHIFT)) & LPDDR_DENALI_CTL_INT_MASK_LOWPOWER_MASK)

#define LPDDR_DENALI_CTL_INT_MASK_MISC_MASK      (0xFF0000U)
#define LPDDR_DENALI_CTL_INT_MASK_MISC_SHIFT     (16U)
#define LPDDR_DENALI_CTL_INT_MASK_MISC(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_MASK_MISC_SHIFT)) & LPDDR_DENALI_CTL_INT_MASK_MISC_MASK)

#define LPDDR_DENALI_CTL_INT_MASK_USERIF_MASK    (0xFFFF0000U)
#define LPDDR_DENALI_CTL_INT_MASK_USERIF_SHIFT   (16U)
#define LPDDR_DENALI_CTL_INT_MASK_USERIF(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_MASK_USERIF_SHIFT)) & LPDDR_DENALI_CTL_INT_MASK_USERIF_MASK)

#define LPDDR_DENALI_CTL_INT_STATUS_LOWPOWER_MASK (0xFFFF0000U)
#define LPDDR_DENALI_CTL_INT_STATUS_LOWPOWER_SHIFT (16U)
#define LPDDR_DENALI_CTL_INT_STATUS_LOWPOWER(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_STATUS_LOWPOWER_SHIFT)) & LPDDR_DENALI_CTL_INT_STATUS_LOWPOWER_MASK)

#define LPDDR_DENALI_CTL_INT_STATUS_MISC_MASK    (0xFF0000U)
#define LPDDR_DENALI_CTL_INT_STATUS_MISC_SHIFT   (16U)
#define LPDDR_DENALI_CTL_INT_STATUS_MISC(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_STATUS_MISC_SHIFT)) & LPDDR_DENALI_CTL_INT_STATUS_MISC_MASK)

#define LPDDR_DENALI_CTL_INT_STATUS_USERIF_MASK  (0xFFFF0000U)
#define LPDDR_DENALI_CTL_INT_STATUS_USERIF_SHIFT (16U)
#define LPDDR_DENALI_CTL_INT_STATUS_USERIF(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_STATUS_USERIF_SHIFT)) & LPDDR_DENALI_CTL_INT_STATUS_USERIF_MASK)

#define LPDDR_DENALI_CTL_MEMDATA_RATIO_1_MASK    (0x70000U)
#define LPDDR_DENALI_CTL_MEMDATA_RATIO_1_SHIFT   (16U)
#define LPDDR_DENALI_CTL_MEMDATA_RATIO_1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MEMDATA_RATIO_1_SHIFT)) & LPDDR_DENALI_CTL_MEMDATA_RATIO_1_MASK)

#define LPDDR_DENALI_CTL_MR1_DATA_F0_1_MASK      (0xFF0000U)
#define LPDDR_DENALI_CTL_MR1_DATA_F0_1_SHIFT     (16U)
#define LPDDR_DENALI_CTL_MR1_DATA_F0_1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR1_DATA_F0_1_SHIFT)) & LPDDR_DENALI_CTL_MR1_DATA_F0_1_MASK)

#define LPDDR_DENALI_CTL_MR1_DATA_F1_0_MASK      (0xFF0000U)
#define LPDDR_DENALI_CTL_MR1_DATA_F1_0_SHIFT     (16U)
#define LPDDR_DENALI_CTL_MR1_DATA_F1_0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR1_DATA_F1_0_SHIFT)) & LPDDR_DENALI_CTL_MR1_DATA_F1_0_MASK)

#define LPDDR_DENALI_CTL_MR1_DATA_F2_1_MASK      (0xFF0000U)
#define LPDDR_DENALI_CTL_MR1_DATA_F2_1_SHIFT     (16U)
#define LPDDR_DENALI_CTL_MR1_DATA_F2_1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR1_DATA_F2_1_SHIFT)) & LPDDR_DENALI_CTL_MR1_DATA_F2_1_MASK)

#define LPDDR_DENALI_CTL_MR3_DATA_F1_1_MASK      (0xFF0000U)
#define LPDDR_DENALI_CTL_MR3_DATA_F1_1_SHIFT     (16U)
#define LPDDR_DENALI_CTL_MR3_DATA_F1_1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR3_DATA_F1_1_SHIFT)) & LPDDR_DENALI_CTL_MR3_DATA_F1_1_MASK)

#define LPDDR_DENALI_CTL_MR4_DATA_F0_0_MASK      (0xFF0000U)
#define LPDDR_DENALI_CTL_MR4_DATA_F0_0_SHIFT     (16U)
#define LPDDR_DENALI_CTL_MR4_DATA_F0_0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR4_DATA_F0_0_SHIFT)) & LPDDR_DENALI_CTL_MR4_DATA_F0_0_MASK)

#define LPDDR_DENALI_CTL_MR4_DATA_F2_1_MASK      (0xFF0000U)
#define LPDDR_DENALI_CTL_MR4_DATA_F2_1_SHIFT     (16U)
#define LPDDR_DENALI_CTL_MR4_DATA_F2_1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR4_DATA_F2_1_SHIFT)) & LPDDR_DENALI_CTL_MR4_DATA_F2_1_MASK)

#define LPDDR_DENALI_CTL_MR11_DATA_F0_0_MASK     (0xFF0000U)
#define LPDDR_DENALI_CTL_MR11_DATA_F0_0_SHIFT    (16U)
#define LPDDR_DENALI_CTL_MR11_DATA_F0_0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR11_DATA_F0_0_SHIFT)) & LPDDR_DENALI_CTL_MR11_DATA_F0_0_MASK)

#define LPDDR_DENALI_CTL_MR11_DATA_F2_1_MASK     (0xFF0000U)
#define LPDDR_DENALI_CTL_MR11_DATA_F2_1_SHIFT    (16U)
#define LPDDR_DENALI_CTL_MR11_DATA_F2_1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR11_DATA_F2_1_SHIFT)) & LPDDR_DENALI_CTL_MR11_DATA_F2_1_MASK)

#define LPDDR_DENALI_CTL_MR12_DATA_F1_0_MASK     (0xFF0000U)
#define LPDDR_DENALI_CTL_MR12_DATA_F1_0_SHIFT    (16U)
#define LPDDR_DENALI_CTL_MR12_DATA_F1_0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR12_DATA_F1_0_SHIFT)) & LPDDR_DENALI_CTL_MR12_DATA_F1_0_MASK)

#define LPDDR_DENALI_CTL_MR13_DATA_1_MASK        (0xFF0000U)
#define LPDDR_DENALI_CTL_MR13_DATA_1_SHIFT       (16U)
#define LPDDR_DENALI_CTL_MR13_DATA_1(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR13_DATA_1_SHIFT)) & LPDDR_DENALI_CTL_MR13_DATA_1_MASK)

#define LPDDR_DENALI_CTL_MR16_DATA_1_MASK        (0xFF0000U)
#define LPDDR_DENALI_CTL_MR16_DATA_1_SHIFT       (16U)
#define LPDDR_DENALI_CTL_MR16_DATA_1(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR16_DATA_1_SHIFT)) & LPDDR_DENALI_CTL_MR16_DATA_1_MASK)

#define LPDDR_DENALI_CTL_MR22_DATA_F1_1_MASK     (0xFF0000U)
#define LPDDR_DENALI_CTL_MR22_DATA_F1_1_SHIFT    (16U)
#define LPDDR_DENALI_CTL_MR22_DATA_F1_1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR22_DATA_F1_1_SHIFT)) & LPDDR_DENALI_CTL_MR22_DATA_F1_1_MASK)

#define LPDDR_DENALI_CTL_MRSINGLE_DATA_0_MASK    (0xFF0000U)
#define LPDDR_DENALI_CTL_MRSINGLE_DATA_0_SHIFT   (16U)
#define LPDDR_DENALI_CTL_MRSINGLE_DATA_0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MRSINGLE_DATA_0_SHIFT)) & LPDDR_DENALI_CTL_MRSINGLE_DATA_0_MASK)

#define LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F1_MASK (0x10000U)
#define LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F1_SHIFT (16U)
/*! MR_FSP_DATA_VALID_F1
 *  0b0..Memory training is in progress or was not performed
 *  0b1..Memory was trained
 */
#define LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F1_SHIFT)) & LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F1_MASK)

#define LPDDR_DENALI_CTL_NO_MRW_INIT_MASK        (0x10000U)
#define LPDDR_DENALI_CTL_NO_MRW_INIT_SHIFT       (16U)
#define LPDDR_DENALI_CTL_NO_MRW_INIT(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_NO_MRW_INIT_SHIFT)) & LPDDR_DENALI_CTL_NO_MRW_INIT_MASK)

#define LPDDR_DENALI_CTL_NO_ZQ_INIT_MASK         (0x10000U)
#define LPDDR_DENALI_CTL_NO_ZQ_INIT_SHIFT        (16U)
/*! NO_ZQ_INIT
 *  0b0..ZQ operations allowed during initialization
 *  0b1..ZQ operations disabled during initialization
 */
#define LPDDR_DENALI_CTL_NO_ZQ_INIT(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_NO_ZQ_INIT_SHIFT)) & LPDDR_DENALI_CTL_NO_ZQ_INIT_MASK)

#define LPDDR_DENALI_CTL_NUM_Q_ENTRIES_ACT_DISABLE_MASK (0xF0000U)
#define LPDDR_DENALI_CTL_NUM_Q_ENTRIES_ACT_DISABLE_SHIFT (16U)
#define LPDDR_DENALI_CTL_NUM_Q_ENTRIES_ACT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_NUM_Q_ENTRIES_ACT_DISABLE_SHIFT)) & LPDDR_DENALI_CTL_NUM_Q_ENTRIES_ACT_DISABLE_MASK)

#define LPDDR_DENALI_CTL_ODT_EN_F1_MASK          (0x10000U)
#define LPDDR_DENALI_CTL_ODT_EN_F1_SHIFT         (16U)
#define LPDDR_DENALI_CTL_ODT_EN_F1(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ODT_EN_F1_SHIFT)) & LPDDR_DENALI_CTL_ODT_EN_F1_MASK)

#define LPDDR_DENALI_CTL_ODT_RD_MAP_CS1_MASK     (0x30000U)
#define LPDDR_DENALI_CTL_ODT_RD_MAP_CS1_SHIFT    (16U)
#define LPDDR_DENALI_CTL_ODT_RD_MAP_CS1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ODT_RD_MAP_CS1_SHIFT)) & LPDDR_DENALI_CTL_ODT_RD_MAP_CS1_MASK)

#define LPDDR_DENALI_CTL_PBR_MAX_BANK_WAIT_MASK  (0xFFFF0000U)
#define LPDDR_DENALI_CTL_PBR_MAX_BANK_WAIT_SHIFT (16U)
/*! PBR_MAX_BANK_WAIT - Defines the maximum number of cycles that the PBR module will wait for
 *    Strategy to release the target bank until the PBR will assert the inhibit and close the target bank.
 */
#define LPDDR_DENALI_CTL_PBR_MAX_BANK_WAIT(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PBR_MAX_BANK_WAIT_SHIFT)) & LPDDR_DENALI_CTL_PBR_MAX_BANK_WAIT_MASK)

#define LPDDR_DENALI_CTL_PHY_INDEP_INIT_MODE_MASK (0x10000U)
#define LPDDR_DENALI_CTL_PHY_INDEP_INIT_MODE_SHIFT (16U)
/*! PHY_INDEP_INIT_MODE
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_PHY_INDEP_INIT_MODE(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PHY_INDEP_INIT_MODE_SHIFT)) & LPDDR_DENALI_CTL_PHY_INDEP_INIT_MODE_MASK)

#define LPDDR_DENALI_CTL_PORT_ADDR_PROTECTION_EN_MASK (0x10000U)
#define LPDDR_DENALI_CTL_PORT_ADDR_PROTECTION_EN_SHIFT (16U)
#define LPDDR_DENALI_CTL_PORT_ADDR_PROTECTION_EN(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PORT_ADDR_PROTECTION_EN_SHIFT)) & LPDDR_DENALI_CTL_PORT_ADDR_PROTECTION_EN_MASK)

#define LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F0_MASK (0x30000U)
#define LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F0_SHIFT (16U)
/*! PREAMBLE_SUPPORT_F0 - Selects the preamble for read and write burst transfers for frequency set 0. */
#define LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F0_SHIFT)) & LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F0_MASK)

#define LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F0_MASK  (0x1F0000U)
#define LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F0_SHIFT (16U)
#define LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F0_SHIFT)) & LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F0_MASK)

#define LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F1_MASK  (0x1F0000U)
#define LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F1_SHIFT (16U)
#define LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F1_SHIFT)) & LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F1_MASK)

#define LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F2_MASK  (0x1F0000U)
#define LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F2_SHIFT (16U)
#define LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F2_SHIFT)) & LPDDR_DENALI_CTL_R2R_DIFFCS_DLY_F2_MASK)

#define LPDDR_DENALI_CTL_R2R_SAMECS_DLY_MASK     (0x1F0000U)
#define LPDDR_DENALI_CTL_R2R_SAMECS_DLY_SHIFT    (16U)
#define LPDDR_DENALI_CTL_R2R_SAMECS_DLY(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_R2R_SAMECS_DLY_SHIFT)) & LPDDR_DENALI_CTL_R2R_SAMECS_DLY_MASK)

#define LPDDR_DENALI_CTL_RD_TO_ODTH_F2_MASK      (0x3F0000U)
#define LPDDR_DENALI_CTL_RD_TO_ODTH_F2_SHIFT     (16U)
#define LPDDR_DENALI_CTL_RD_TO_ODTH_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RD_TO_ODTH_F2_SHIFT)) & LPDDR_DENALI_CTL_RD_TO_ODTH_F2_MASK)

#define LPDDR_DENALI_CTL_RW_SAME_PAGE_EN_MASK    (0x10000U)
#define LPDDR_DENALI_CTL_RW_SAME_PAGE_EN_SHIFT   (16U)
/*! RW_SAME_PAGE_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_RW_SAME_PAGE_EN(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RW_SAME_PAGE_EN_SHIFT)) & LPDDR_DENALI_CTL_RW_SAME_PAGE_EN_MASK)

#define LPDDR_DENALI_CTL_TBST_INT_INTERVAL_MASK  (0x70000U)
#define LPDDR_DENALI_CTL_TBST_INT_INTERVAL_SHIFT (16U)
#define LPDDR_DENALI_CTL_TBST_INT_INTERVAL(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TBST_INT_INTERVAL_SHIFT)) & LPDDR_DENALI_CTL_TBST_INT_INTERVAL_MASK)

#define LPDDR_DENALI_CTL_TCCDMW_MASK             (0x3F0000U)
#define LPDDR_DENALI_CTL_TCCDMW_SHIFT            (16U)
#define LPDDR_DENALI_CTL_TCCDMW(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCCDMW_SHIFT)) & LPDDR_DENALI_CTL_TCCDMW_MASK)

#define LPDDR_DENALI_CTL_TCKCKEL_F0_MASK         (0x1F0000U)
#define LPDDR_DENALI_CTL_TCKCKEL_F0_SHIFT        (16U)
#define LPDDR_DENALI_CTL_TCKCKEL_F0(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKCKEL_F0_SHIFT)) & LPDDR_DENALI_CTL_TCKCKEL_F0_MASK)

#define LPDDR_DENALI_CTL_TCKCKEL_F1_MASK         (0x1F0000U)
#define LPDDR_DENALI_CTL_TCKCKEL_F1_SHIFT        (16U)
#define LPDDR_DENALI_CTL_TCKCKEL_F1(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKCKEL_F1_SHIFT)) & LPDDR_DENALI_CTL_TCKCKEL_F1_MASK)

#define LPDDR_DENALI_CTL_TCKCKEL_F2_MASK         (0x1F0000U)
#define LPDDR_DENALI_CTL_TCKCKEL_F2_SHIFT        (16U)
#define LPDDR_DENALI_CTL_TCKCKEL_F2(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKCKEL_F2_SHIFT)) & LPDDR_DENALI_CTL_TCKCKEL_F2_MASK)

#define LPDDR_DENALI_CTL_TCKELCS_F0_MASK         (0x1F0000U)
#define LPDDR_DENALI_CTL_TCKELCS_F0_SHIFT        (16U)
#define LPDDR_DENALI_CTL_TCKELCS_F0(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKELCS_F0_SHIFT)) & LPDDR_DENALI_CTL_TCKELCS_F0_MASK)

#define LPDDR_DENALI_CTL_TCKELCS_F2_MASK         (0x1F0000U)
#define LPDDR_DENALI_CTL_TCKELCS_F2_SHIFT        (16U)
#define LPDDR_DENALI_CTL_TCKELCS_F2(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKELCS_F2_SHIFT)) & LPDDR_DENALI_CTL_TCKELCS_F2_MASK)

#define LPDDR_DENALI_CTL_TCKFSPE_F1_MASK         (0x1F0000U)
#define LPDDR_DENALI_CTL_TCKFSPE_F1_SHIFT        (16U)
#define LPDDR_DENALI_CTL_TCKFSPE_F1(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKFSPE_F1_SHIFT)) & LPDDR_DENALI_CTL_TCKFSPE_F1_MASK)

#define LPDDR_DENALI_CTL_TCKFSPE_F2_MASK         (0x1F0000U)
#define LPDDR_DENALI_CTL_TCKFSPE_F2_SHIFT        (16U)
#define LPDDR_DENALI_CTL_TCKFSPE_F2(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKFSPE_F2_SHIFT)) & LPDDR_DENALI_CTL_TCKFSPE_F2_MASK)

#define LPDDR_DENALI_CTL_TCSCKEH_F0_MASK         (0x1F0000U)
#define LPDDR_DENALI_CTL_TCSCKEH_F0_SHIFT        (16U)
#define LPDDR_DENALI_CTL_TCSCKEH_F0(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCSCKEH_F0_SHIFT)) & LPDDR_DENALI_CTL_TCSCKEH_F0_MASK)

#define LPDDR_DENALI_CTL_TCSCKEH_F1_MASK         (0x1F0000U)
#define LPDDR_DENALI_CTL_TCSCKEH_F1_SHIFT        (16U)
#define LPDDR_DENALI_CTL_TCSCKEH_F1(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCSCKEH_F1_SHIFT)) & LPDDR_DENALI_CTL_TCSCKEH_F1_MASK)

#define LPDDR_DENALI_CTL_TCSCKEH_F2_MASK         (0x1F0000U)
#define LPDDR_DENALI_CTL_TCSCKEH_F2_SHIFT        (16U)
#define LPDDR_DENALI_CTL_TCSCKEH_F2(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCSCKEH_F2_SHIFT)) & LPDDR_DENALI_CTL_TCSCKEH_F2_MASK)

#define LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F0_MASK (0xF0000U)
#define LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F0_SHIFT (16U)
#define LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F0(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_DRAM_CLK_ENABLE_MASK (0xF0000U)
#define LPDDR_DENALI_CTL_TDFI_DRAM_CLK_ENABLE_SHIFT (16U)
#define LPDDR_DENALI_CTL_TDFI_DRAM_CLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_DRAM_CLK_ENABLE_SHIFT)) & LPDDR_DENALI_CTL_TDFI_DRAM_CLK_ENABLE_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F0_MASK  (0x7F0000U)
#define LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F0_SHIFT (16U)
/*! TDFI_PHY_RDLAT_F0 - Defines the DFI tPHY_RDLAT timing parameter (in DFI PHY clocks), the maximum
 *    cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion.
 */
#define LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_RDCSLAT_F0_MASK    (0x7F0000U)
#define LPDDR_DENALI_CTL_TDFI_RDCSLAT_F0_SHIFT   (16U)
#define LPDDR_DENALI_CTL_TDFI_RDCSLAT_F0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_RDCSLAT_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_RDCSLAT_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_RDCSLAT_F2_MASK    (0x7F0000U)
#define LPDDR_DENALI_CTL_TDFI_RDCSLAT_F2_SHIFT   (16U)
#define LPDDR_DENALI_CTL_TDFI_RDCSLAT_F2(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_RDCSLAT_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_RDCSLAT_F2_MASK)

#define LPDDR_DENALI_CTL_TDQSCK_MAX_F1_MASK      (0xF0000U)
#define LPDDR_DENALI_CTL_TDQSCK_MAX_F1_SHIFT     (16U)
#define LPDDR_DENALI_CTL_TDQSCK_MAX_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDQSCK_MAX_F1_SHIFT)) & LPDDR_DENALI_CTL_TDQSCK_MAX_F1_MASK)

#define LPDDR_DENALI_CTL_TFAW_F1_MASK            (0x1FF0000U)
#define LPDDR_DENALI_CTL_TFAW_F1_SHIFT           (16U)
#define LPDDR_DENALI_CTL_TFAW_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TFAW_F1_SHIFT)) & LPDDR_DENALI_CTL_TFAW_F1_MASK)

#define LPDDR_DENALI_CTL_TFC_F0_MASK             (0x3FF0000U)
#define LPDDR_DENALI_CTL_TFC_F0_SHIFT            (16U)
#define LPDDR_DENALI_CTL_TFC_F0(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TFC_F0_SHIFT)) & LPDDR_DENALI_CTL_TFC_F0_MASK)

#define LPDDR_DENALI_CTL_TMRD_F1_MASK            (0xFF0000U)
#define LPDDR_DENALI_CTL_TMRD_F1_SHIFT           (16U)
#define LPDDR_DENALI_CTL_TMRD_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TMRD_F1_SHIFT)) & LPDDR_DENALI_CTL_TMRD_F1_MASK)

#define LPDDR_DENALI_CTL_TMRD_F2_MASK            (0xFF0000U)
#define LPDDR_DENALI_CTL_TMRD_F2_SHIFT           (16U)
#define LPDDR_DENALI_CTL_TMRD_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TMRD_F2_SHIFT)) & LPDDR_DENALI_CTL_TMRD_F2_MASK)

#define LPDDR_DENALI_CTL_TMRRI_F0_MASK           (0xFF0000U)
#define LPDDR_DENALI_CTL_TMRRI_F0_SHIFT          (16U)
#define LPDDR_DENALI_CTL_TMRRI_F0(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TMRRI_F0_SHIFT)) & LPDDR_DENALI_CTL_TMRRI_F0_MASK)

#define LPDDR_DENALI_CTL_TMRWCKEL_F1_MASK        (0x1F0000U)
#define LPDDR_DENALI_CTL_TMRWCKEL_F1_SHIFT       (16U)
#define LPDDR_DENALI_CTL_TMRWCKEL_F1(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TMRWCKEL_F1_SHIFT)) & LPDDR_DENALI_CTL_TMRWCKEL_F1_MASK)

#define LPDDR_DENALI_CTL_TODTH_RD_F0_MASK        (0xF0000U)
#define LPDDR_DENALI_CTL_TODTH_RD_F0_SHIFT       (16U)
#define LPDDR_DENALI_CTL_TODTH_RD_F0(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TODTH_RD_F0_SHIFT)) & LPDDR_DENALI_CTL_TODTH_RD_F0_MASK)

#define LPDDR_DENALI_CTL_TODTL_2CMD_F2_MASK      (0xFF0000U)
#define LPDDR_DENALI_CTL_TODTL_2CMD_F2_SHIFT     (16U)
#define LPDDR_DENALI_CTL_TODTL_2CMD_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TODTL_2CMD_F2_SHIFT)) & LPDDR_DENALI_CTL_TODTL_2CMD_F2_MASK)

#define LPDDR_DENALI_CTL_TPDEX_F1_MASK           (0xFFFF0000U)
#define LPDDR_DENALI_CTL_TPDEX_F1_SHIFT          (16U)
#define LPDDR_DENALI_CTL_TPDEX_F1(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TPDEX_F1_SHIFT)) & LPDDR_DENALI_CTL_TPDEX_F1_MASK)

#define LPDDR_DENALI_CTL_TRAS_LOCKOUT_MASK       (0x10000U)
#define LPDDR_DENALI_CTL_TRAS_LOCKOUT_SHIFT      (16U)
/*! TRAS_LOCKOUT
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_TRAS_LOCKOUT(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRAS_LOCKOUT_SHIFT)) & LPDDR_DENALI_CTL_TRAS_LOCKOUT_MASK)

#define LPDDR_DENALI_CTL_TRAS_MIN_F1_MASK        (0x1FF0000U)
#define LPDDR_DENALI_CTL_TRAS_MIN_F1_SHIFT       (16U)
#define LPDDR_DENALI_CTL_TRAS_MIN_F1(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRAS_MIN_F1_SHIFT)) & LPDDR_DENALI_CTL_TRAS_MIN_F1_MASK)

#define LPDDR_DENALI_CTL_TRFC_F0_MASK            (0x3FF0000U)
#define LPDDR_DENALI_CTL_TRFC_F0_SHIFT           (16U)
#define LPDDR_DENALI_CTL_TRFC_F0(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRFC_F0_SHIFT)) & LPDDR_DENALI_CTL_TRFC_F0_MASK)

#define LPDDR_DENALI_CTL_TRFC_PB_F0_MASK         (0x3FF0000U)
#define LPDDR_DENALI_CTL_TRFC_PB_F0_SHIFT        (16U)
#define LPDDR_DENALI_CTL_TRFC_PB_F0(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRFC_PB_F0_SHIFT)) & LPDDR_DENALI_CTL_TRFC_PB_F0_MASK)

#define LPDDR_DENALI_CTL_TRFC_PB_F1_MASK         (0x3FF0000U)
#define LPDDR_DENALI_CTL_TRFC_PB_F1_SHIFT        (16U)
#define LPDDR_DENALI_CTL_TRFC_PB_F1(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRFC_PB_F1_SHIFT)) & LPDDR_DENALI_CTL_TRFC_PB_F1_MASK)

#define LPDDR_DENALI_CTL_TRFC_PB_F2_MASK         (0x3FF0000U)
#define LPDDR_DENALI_CTL_TRFC_PB_F2_SHIFT        (16U)
#define LPDDR_DENALI_CTL_TRFC_PB_F2(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRFC_PB_F2_SHIFT)) & LPDDR_DENALI_CTL_TRFC_PB_F2_MASK)

#define LPDDR_DENALI_CTL_TRRD_F1_MASK            (0xFF0000U)
#define LPDDR_DENALI_CTL_TRRD_F1_SHIFT           (16U)
#define LPDDR_DENALI_CTL_TRRD_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRRD_F1_SHIFT)) & LPDDR_DENALI_CTL_TRRD_F1_MASK)

#define LPDDR_DENALI_CTL_TVRCG_DISABLE_F1_MASK   (0x3FF0000U)
#define LPDDR_DENALI_CTL_TVRCG_DISABLE_F1_SHIFT  (16U)
#define LPDDR_DENALI_CTL_TVRCG_DISABLE_F1(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TVRCG_DISABLE_F1_SHIFT)) & LPDDR_DENALI_CTL_TVRCG_DISABLE_F1_MASK)

#define LPDDR_DENALI_CTL_TVRCG_DISABLE_F2_MASK   (0x3FF0000U)
#define LPDDR_DENALI_CTL_TVRCG_DISABLE_F2_SHIFT  (16U)
#define LPDDR_DENALI_CTL_TVRCG_DISABLE_F2(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TVRCG_DISABLE_F2_SHIFT)) & LPDDR_DENALI_CTL_TVRCG_DISABLE_F2_MASK)

#define LPDDR_DENALI_CTL_TVRCG_ENABLE_F0_MASK    (0x3FF0000U)
#define LPDDR_DENALI_CTL_TVRCG_ENABLE_F0_SHIFT   (16U)
#define LPDDR_DENALI_CTL_TVRCG_ENABLE_F0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TVRCG_ENABLE_F0_SHIFT)) & LPDDR_DENALI_CTL_TVRCG_ENABLE_F0_MASK)

#define LPDDR_DENALI_CTL_TWR_F0_MASK             (0xFF0000U)
#define LPDDR_DENALI_CTL_TWR_F0_SHIFT            (16U)
#define LPDDR_DENALI_CTL_TWR_F0(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TWR_F0_SHIFT)) & LPDDR_DENALI_CTL_TWR_F0_MASK)

#define LPDDR_DENALI_CTL_TWR_F2_MASK             (0xFF0000U)
#define LPDDR_DENALI_CTL_TWR_F2_SHIFT            (16U)
#define LPDDR_DENALI_CTL_TWR_F2(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TWR_F2_SHIFT)) & LPDDR_DENALI_CTL_TWR_F2_MASK)

#define LPDDR_DENALI_CTL_TWTR_F0_MASK            (0x3F0000U)
#define LPDDR_DENALI_CTL_TWTR_F0_SHIFT           (16U)
#define LPDDR_DENALI_CTL_TWTR_F0(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TWTR_F0_SHIFT)) & LPDDR_DENALI_CTL_TWTR_F0_MASK)

#define LPDDR_DENALI_CTL_TWTR_F2_MASK            (0x3F0000U)
#define LPDDR_DENALI_CTL_TWTR_F2_SHIFT           (16U)
#define LPDDR_DENALI_CTL_TWTR_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TWTR_F2_SHIFT)) & LPDDR_DENALI_CTL_TWTR_F2_MASK)

#define LPDDR_DENALI_CTL_TXSNR_F0_MASK           (0xFFFF0000U)
#define LPDDR_DENALI_CTL_TXSNR_F0_SHIFT          (16U)
#define LPDDR_DENALI_CTL_TXSNR_F0(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TXSNR_F0_SHIFT)) & LPDDR_DENALI_CTL_TXSNR_F0_MASK)

#define LPDDR_DENALI_CTL_TXSNR_F1_MASK           (0xFFFF0000U)
#define LPDDR_DENALI_CTL_TXSNR_F1_SHIFT          (16U)
#define LPDDR_DENALI_CTL_TXSNR_F1(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TXSNR_F1_SHIFT)) & LPDDR_DENALI_CTL_TXSNR_F1_MASK)

#define LPDDR_DENALI_CTL_TXSNR_F2_MASK           (0xFFFF0000U)
#define LPDDR_DENALI_CTL_TXSNR_F2_SHIFT          (16U)
#define LPDDR_DENALI_CTL_TXSNR_F2(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TXSNR_F2_SHIFT)) & LPDDR_DENALI_CTL_TXSNR_F2_MASK)

#define LPDDR_DENALI_CTL_TZQCAL_F0_MASK          (0xFFF0000U)
#define LPDDR_DENALI_CTL_TZQCAL_F0_SHIFT         (16U)
#define LPDDR_DENALI_CTL_TZQCAL_F0(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TZQCAL_F0_SHIFT)) & LPDDR_DENALI_CTL_TZQCAL_F0_MASK)

#define LPDDR_DENALI_CTL_TZQCAL_F2_MASK          (0xFFF0000U)
#define LPDDR_DENALI_CTL_TZQCAL_F2_SHIFT         (16U)
#define LPDDR_DENALI_CTL_TZQCAL_F2(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TZQCAL_F2_SHIFT)) & LPDDR_DENALI_CTL_TZQCAL_F2_MASK)

#define LPDDR_DENALI_CTL_TZQLAT_F1_MASK          (0x7F0000U)
#define LPDDR_DENALI_CTL_TZQLAT_F1_SHIFT         (16U)
#define LPDDR_DENALI_CTL_TZQLAT_F1(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TZQLAT_F1_SHIFT)) & LPDDR_DENALI_CTL_TZQLAT_F1_MASK)

#define LPDDR_DENALI_CTL_W2R_SAMECS_DLY_MASK     (0x1F0000U)
#define LPDDR_DENALI_CTL_W2R_SAMECS_DLY_SHIFT    (16U)
#define LPDDR_DENALI_CTL_W2R_SAMECS_DLY(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_W2R_SAMECS_DLY_SHIFT)) & LPDDR_DENALI_CTL_W2R_SAMECS_DLY_MASK)

#define LPDDR_DENALI_CTL_WR_DBI_EN_MASK          (0x10000U)
#define LPDDR_DENALI_CTL_WR_DBI_EN_SHIFT         (16U)
/*! WR_DBI_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_WR_DBI_EN(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_WR_DBI_EN_SHIFT)) & LPDDR_DENALI_CTL_WR_DBI_EN_MASK)

#define LPDDR_DENALI_CTL_WR_TO_ODTH_F1_MASK      (0x3F0000U)
#define LPDDR_DENALI_CTL_WR_TO_ODTH_F1_SHIFT     (16U)
#define LPDDR_DENALI_CTL_WR_TO_ODTH_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_WR_TO_ODTH_F1_SHIFT)) & LPDDR_DENALI_CTL_WR_TO_ODTH_F1_MASK)

#define LPDDR_DENALI_CTL_ZQCL_F2_MASK            (0xFFF0000U)
#define LPDDR_DENALI_CTL_ZQCL_F2_SHIFT           (16U)
#define LPDDR_DENALI_CTL_ZQCL_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQCL_F2_SHIFT)) & LPDDR_DENALI_CTL_ZQCL_F2_MASK)

#define LPDDR_DENALI_CTL_ZQCS_F1_MASK            (0xFFF0000U)
#define LPDDR_DENALI_CTL_ZQCS_F1_SHIFT           (16U)
#define LPDDR_DENALI_CTL_ZQCS_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQCS_F1_SHIFT)) & LPDDR_DENALI_CTL_ZQCS_F1_MASK)

#define LPDDR_DENALI_CTL_ZQRESET_F1_MASK         (0xFFF0000U)
#define LPDDR_DENALI_CTL_ZQRESET_F1_SHIFT        (16U)
#define LPDDR_DENALI_CTL_ZQRESET_F1(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQRESET_F1_SHIFT)) & LPDDR_DENALI_CTL_ZQRESET_F1_MASK)

#define LPDDR_DENALI_CTL_ZQ_REQ_MASK             (0xF0000U)
#define LPDDR_DENALI_CTL_ZQ_REQ_SHIFT            (16U)
#define LPDDR_DENALI_CTL_ZQ_REQ(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQ_REQ_SHIFT)) & LPDDR_DENALI_CTL_ZQ_REQ_MASK)

#define LPDDR_DENALI_CTL_AREF_PBR_CONT_DIS_THRESHOLD_MASK (0x1F000000U)
#define LPDDR_DENALI_CTL_AREF_PBR_CONT_DIS_THRESHOLD_SHIFT (24U)
/*! AREF_PBR_CONT_DIS_THRESHOLD - Sets the auto-refresh request count threshold when the PBR continuous refresh request enable will be deasserted. */
#define LPDDR_DENALI_CTL_AREF_PBR_CONT_DIS_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AREF_PBR_CONT_DIS_THRESHOLD_SHIFT)) & LPDDR_DENALI_CTL_AREF_PBR_CONT_DIS_THRESHOLD_MASK)

#define LPDDR_DENALI_CTL_AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK (0x1000000U)
#define LPDDR_DENALI_CTL_AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT (24U)
#define LPDDR_DENALI_CTL_AXI0_FIXED_PORT_PRIORITY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT)) & LPDDR_DENALI_CTL_AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK)

#define LPDDR_DENALI_CTL_AXI1_ALL_STROBES_USED_ENABLE_MASK (0x1000000U)
#define LPDDR_DENALI_CTL_AXI1_ALL_STROBES_USED_ENABLE_SHIFT (24U)
#define LPDDR_DENALI_CTL_AXI1_ALL_STROBES_USED_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI1_ALL_STROBES_USED_ENABLE_SHIFT)) & LPDDR_DENALI_CTL_AXI1_ALL_STROBES_USED_ENABLE_MASK)

#define LPDDR_DENALI_CTL_AXI1_FIFO_TYPE_REG_MASK (0x3000000U)
#define LPDDR_DENALI_CTL_AXI1_FIFO_TYPE_REG_SHIFT (24U)
#define LPDDR_DENALI_CTL_AXI1_FIFO_TYPE_REG(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI1_FIFO_TYPE_REG_SHIFT)) & LPDDR_DENALI_CTL_AXI1_FIFO_TYPE_REG_MASK)

#define LPDDR_DENALI_CTL_AXI2_W_PRIORITY_MASK    (0x7000000U)
#define LPDDR_DENALI_CTL_AXI2_W_PRIORITY_SHIFT   (24U)
#define LPDDR_DENALI_CTL_AXI2_W_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI2_W_PRIORITY_SHIFT)) & LPDDR_DENALI_CTL_AXI2_W_PRIORITY_MASK)

#define LPDDR_DENALI_CTL_AXI3_R_PRIORITY_MASK    (0x7000000U)
#define LPDDR_DENALI_CTL_AXI3_R_PRIORITY_SHIFT   (24U)
#define LPDDR_DENALI_CTL_AXI3_R_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_AXI3_R_PRIORITY_SHIFT)) & LPDDR_DENALI_CTL_AXI3_R_PRIORITY_MASK)

#define LPDDR_DENALI_CTL_BANK_START_BIT_MASK     (0x1F000000U)
#define LPDDR_DENALI_CTL_BANK_START_BIT_SHIFT    (24U)
/*! BANK_START_BIT - Defines the LSbit of the bank address within the page of the user address when the BANK_ADDR_INTLV_EN bit is set. */
#define LPDDR_DENALI_CTL_BANK_START_BIT(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_BANK_START_BIT_SHIFT)) & LPDDR_DENALI_CTL_BANK_START_BIT_MASK)

#define LPDDR_DENALI_CTL_BL_ON_FLY_ENABLE_MASK   (0x1000000U)
#define LPDDR_DENALI_CTL_BL_ON_FLY_ENABLE_SHIFT  (24U)
/*! BL_ON_FLY_ENABLE
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_BL_ON_FLY_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_BL_ON_FLY_ENABLE_SHIFT)) & LPDDR_DENALI_CTL_BL_ON_FLY_ENABLE_MASK)

#define LPDDR_DENALI_CTL_COMMAND_AGE_COUNT_MASK  (0xFF000000U)
#define LPDDR_DENALI_CTL_COMMAND_AGE_COUNT_SHIFT (24U)
#define LPDDR_DENALI_CTL_COMMAND_AGE_COUNT(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_COMMAND_AGE_COUNT_SHIFT)) & LPDDR_DENALI_CTL_COMMAND_AGE_COUNT_MASK)

#define LPDDR_DENALI_CTL_CS_SAME_EN_MASK         (0x1000000U)
#define LPDDR_DENALI_CTL_CS_SAME_EN_SHIFT        (24U)
/*! CS_SAME_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_CS_SAME_EN(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CS_SAME_EN_SHIFT)) & LPDDR_DENALI_CTL_CS_SAME_EN_MASK)

#define LPDDR_DENALI_CTL_CTRLUPD_REQ_MASK        (0x1000000U)
#define LPDDR_DENALI_CTL_CTRLUPD_REQ_SHIFT       (24U)
/*! CTRLUPD_REQ
 *  0b0..No action
 *  0b1..Trigger a controller-initiate update request
 */
#define LPDDR_DENALI_CTL_CTRLUPD_REQ(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_CTRLUPD_REQ_SHIFT)) & LPDDR_DENALI_CTL_CTRLUPD_REQ_MASK)

#define LPDDR_DENALI_CTL_DEVICE0_BYTE0_CS1_MASK  (0xF000000U)
#define LPDDR_DENALI_CTL_DEVICE0_BYTE0_CS1_SHIFT (24U)
#define LPDDR_DENALI_CTL_DEVICE0_BYTE0_CS1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DEVICE0_BYTE0_CS1_SHIFT)) & LPDDR_DENALI_CTL_DEVICE0_BYTE0_CS1_MASK)

#define LPDDR_DENALI_CTL_DEVICE1_BYTE0_CS0_MASK  (0xF000000U)
#define LPDDR_DENALI_CTL_DEVICE1_BYTE0_CS0_SHIFT (24U)
#define LPDDR_DENALI_CTL_DEVICE1_BYTE0_CS0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DEVICE1_BYTE0_CS0_SHIFT)) & LPDDR_DENALI_CTL_DEVICE1_BYTE0_CS0_MASK)

#define LPDDR_DENALI_CTL_DFIBUS_FREQ_F2_MASK     (0x1F000000U)
#define LPDDR_DENALI_CTL_DFIBUS_FREQ_F2_SHIFT    (24U)
/*! DFIBUS_FREQ_F2 - Defines the DFI bus frequency for frequency set 2. */
#define LPDDR_DENALI_CTL_DFIBUS_FREQ_F2(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DFIBUS_FREQ_F2_SHIFT)) & LPDDR_DENALI_CTL_DFIBUS_FREQ_F2_MASK)

#define LPDDR_DENALI_CTL_DFIBUS_FREQ_INIT_MASK   (0x3000000U)
#define LPDDR_DENALI_CTL_DFIBUS_FREQ_INIT_SHIFT  (24U)
/*! DFIBUS_FREQ_INIT - Defines the initial DFI bus frequency. */
#define LPDDR_DENALI_CTL_DFIBUS_FREQ_INIT(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_DFIBUS_FREQ_INIT_SHIFT)) & LPDDR_DENALI_CTL_DFIBUS_FREQ_INIT_MASK)

#define LPDDR_DENALI_CTL_FSP_PHY_UPDATE_MRW_MASK (0x1000000U)
#define LPDDR_DENALI_CTL_FSP_PHY_UPDATE_MRW_SHIFT (24U)
/*! FSP_PHY_UPDATE_MRW
 *  0b0..Controller
 *  0b1..PHY or PI
 */
#define LPDDR_DENALI_CTL_FSP_PHY_UPDATE_MRW(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_FSP_PHY_UPDATE_MRW_SHIFT)) & LPDDR_DENALI_CTL_FSP_PHY_UPDATE_MRW_MASK)

#define LPDDR_DENALI_CTL_FSP_WR_CURRENT_MASK     (0x1000000U)
#define LPDDR_DENALI_CTL_FSP_WR_CURRENT_SHIFT    (24U)
/*! FSP_WR_CURRENT
 *  0b0..FSP set 0
 *  0b1..FSP set 1
 */
#define LPDDR_DENALI_CTL_FSP_WR_CURRENT(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_FSP_WR_CURRENT_SHIFT)) & LPDDR_DENALI_CTL_FSP_WR_CURRENT_MASK)

#define LPDDR_DENALI_CTL_INT_ACK_MODE_MASK       (0xFF000000U)
#define LPDDR_DENALI_CTL_INT_ACK_MODE_SHIFT      (24U)
#define LPDDR_DENALI_CTL_INT_ACK_MODE(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_ACK_MODE_SHIFT)) & LPDDR_DENALI_CTL_INT_ACK_MODE_MASK)

#define LPDDR_DENALI_CTL_INT_MASK_MODE_MASK      (0xFF000000U)
#define LPDDR_DENALI_CTL_INT_MASK_MODE_SHIFT     (24U)
#define LPDDR_DENALI_CTL_INT_MASK_MODE(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_MASK_MODE_SHIFT)) & LPDDR_DENALI_CTL_INT_MASK_MODE_MASK)

#define LPDDR_DENALI_CTL_INT_STATUS_MODE_MASK    (0xFF000000U)
#define LPDDR_DENALI_CTL_INT_STATUS_MODE_SHIFT   (24U)
#define LPDDR_DENALI_CTL_INT_STATUS_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_INT_STATUS_MODE_SHIFT)) & LPDDR_DENALI_CTL_INT_STATUS_MODE_MASK)

#define LPDDR_DENALI_CTL_MR2_DATA_F0_1_MASK      (0xFF000000U)
#define LPDDR_DENALI_CTL_MR2_DATA_F0_1_SHIFT     (24U)
#define LPDDR_DENALI_CTL_MR2_DATA_F0_1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR2_DATA_F0_1_SHIFT)) & LPDDR_DENALI_CTL_MR2_DATA_F0_1_MASK)

#define LPDDR_DENALI_CTL_MR2_DATA_F1_0_MASK      (0xFF000000U)
#define LPDDR_DENALI_CTL_MR2_DATA_F1_0_SHIFT     (24U)
#define LPDDR_DENALI_CTL_MR2_DATA_F1_0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR2_DATA_F1_0_SHIFT)) & LPDDR_DENALI_CTL_MR2_DATA_F1_0_MASK)

#define LPDDR_DENALI_CTL_MR2_DATA_F2_1_MASK      (0xFF000000U)
#define LPDDR_DENALI_CTL_MR2_DATA_F2_1_SHIFT     (24U)
#define LPDDR_DENALI_CTL_MR2_DATA_F2_1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR2_DATA_F2_1_SHIFT)) & LPDDR_DENALI_CTL_MR2_DATA_F2_1_MASK)

#define LPDDR_DENALI_CTL_MR3_DATA_F0_0_MASK      (0xFF000000U)
#define LPDDR_DENALI_CTL_MR3_DATA_F0_0_SHIFT     (24U)
#define LPDDR_DENALI_CTL_MR3_DATA_F0_0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR3_DATA_F0_0_SHIFT)) & LPDDR_DENALI_CTL_MR3_DATA_F0_0_MASK)

#define LPDDR_DENALI_CTL_MR3_DATA_F2_1_MASK      (0xFF000000U)
#define LPDDR_DENALI_CTL_MR3_DATA_F2_1_SHIFT     (24U)
#define LPDDR_DENALI_CTL_MR3_DATA_F2_1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR3_DATA_F2_1_SHIFT)) & LPDDR_DENALI_CTL_MR3_DATA_F2_1_MASK)

#define LPDDR_DENALI_CTL_MR4_DATA_F1_0_MASK      (0xFF000000U)
#define LPDDR_DENALI_CTL_MR4_DATA_F1_0_SHIFT     (24U)
#define LPDDR_DENALI_CTL_MR4_DATA_F1_0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR4_DATA_F1_0_SHIFT)) & LPDDR_DENALI_CTL_MR4_DATA_F1_0_MASK)

#define LPDDR_DENALI_CTL_MR8_DATA_1_MASK         (0xFF000000U)
#define LPDDR_DENALI_CTL_MR8_DATA_1_SHIFT        (24U)
#define LPDDR_DENALI_CTL_MR8_DATA_1(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR8_DATA_1_SHIFT)) & LPDDR_DENALI_CTL_MR8_DATA_1_MASK)

#define LPDDR_DENALI_CTL_MR11_DATA_F1_0_MASK     (0xFF000000U)
#define LPDDR_DENALI_CTL_MR11_DATA_F1_0_SHIFT    (24U)
#define LPDDR_DENALI_CTL_MR11_DATA_F1_0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR11_DATA_F1_0_SHIFT)) & LPDDR_DENALI_CTL_MR11_DATA_F1_0_MASK)

#define LPDDR_DENALI_CTL_MR12_DATA_F0_1_MASK     (0xFF000000U)
#define LPDDR_DENALI_CTL_MR12_DATA_F0_1_SHIFT    (24U)
#define LPDDR_DENALI_CTL_MR12_DATA_F0_1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR12_DATA_F0_1_SHIFT)) & LPDDR_DENALI_CTL_MR12_DATA_F0_1_MASK)

#define LPDDR_DENALI_CTL_MR12_DATA_F2_0_MASK     (0xFF000000U)
#define LPDDR_DENALI_CTL_MR12_DATA_F2_0_SHIFT    (24U)
#define LPDDR_DENALI_CTL_MR12_DATA_F2_0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR12_DATA_F2_0_SHIFT)) & LPDDR_DENALI_CTL_MR12_DATA_F2_0_MASK)

#define LPDDR_DENALI_CTL_MR14_DATA_F0_1_MASK     (0xFF000000U)
#define LPDDR_DENALI_CTL_MR14_DATA_F0_1_SHIFT    (24U)
#define LPDDR_DENALI_CTL_MR14_DATA_F0_1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR14_DATA_F0_1_SHIFT)) & LPDDR_DENALI_CTL_MR14_DATA_F0_1_MASK)

#define LPDDR_DENALI_CTL_MR17_DATA_1_MASK        (0xFF000000U)
#define LPDDR_DENALI_CTL_MR17_DATA_1_SHIFT       (24U)
#define LPDDR_DENALI_CTL_MR17_DATA_1(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR17_DATA_1_SHIFT)) & LPDDR_DENALI_CTL_MR17_DATA_1_MASK)

#define LPDDR_DENALI_CTL_MR22_DATA_F2_1_MASK     (0xFF000000U)
#define LPDDR_DENALI_CTL_MR22_DATA_F2_1_SHIFT    (24U)
#define LPDDR_DENALI_CTL_MR22_DATA_F2_1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR22_DATA_F2_1_SHIFT)) & LPDDR_DENALI_CTL_MR22_DATA_F2_1_MASK)

#define LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F2_MASK (0x1000000U)
#define LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F2_SHIFT (24U)
/*! MR_FSP_DATA_VALID_F2
 *  0b0..Memory training is in progress or was not performed
 *  0b1..Memory was trained
 */
#define LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F2_SHIFT)) & LPDDR_DENALI_CTL_MR_FSP_DATA_VALID_F2_MASK)

#define LPDDR_DENALI_CTL_NO_AUTO_MRR_INIT_MASK   (0x1000000U)
#define LPDDR_DENALI_CTL_NO_AUTO_MRR_INIT_SHIFT  (24U)
/*! NO_AUTO_MRR_INIT
 *  0b0..No restrictions on MRR commands during initialization.
 *  0b1..Do not issue MRR commands during DLL initialization of the DRAM memories.
 */
#define LPDDR_DENALI_CTL_NO_AUTO_MRR_INIT(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_NO_AUTO_MRR_INIT_SHIFT)) & LPDDR_DENALI_CTL_NO_AUTO_MRR_INIT_MASK)

#define LPDDR_DENALI_CTL_NWR_F0_MASK             (0xFF000000U)
#define LPDDR_DENALI_CTL_NWR_F0_SHIFT            (24U)
#define LPDDR_DENALI_CTL_NWR_F0(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_NWR_F0_SHIFT)) & LPDDR_DENALI_CTL_NWR_F0_MASK)

#define LPDDR_DENALI_CTL_ODT_EN_F2_MASK          (0x1000000U)
#define LPDDR_DENALI_CTL_ODT_EN_F2_SHIFT         (24U)
#define LPDDR_DENALI_CTL_ODT_EN_F2(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ODT_EN_F2_SHIFT)) & LPDDR_DENALI_CTL_ODT_EN_F2_MASK)

#define LPDDR_DENALI_CTL_ODT_VALUE_MASK          (0x1000000U)
#define LPDDR_DENALI_CTL_ODT_VALUE_SHIFT         (24U)
/*! ODT_VALUE - When using LPDDR4, this value will be driven out on the dfi_odt signal. */
#define LPDDR_DENALI_CTL_ODT_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ODT_VALUE_SHIFT)) & LPDDR_DENALI_CTL_ODT_VALUE_MASK)

#define LPDDR_DENALI_CTL_ODT_WR_MAP_CS1_MASK     (0x3000000U)
#define LPDDR_DENALI_CTL_ODT_WR_MAP_CS1_SHIFT    (24U)
#define LPDDR_DENALI_CTL_ODT_WR_MAP_CS1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ODT_WR_MAP_CS1_SHIFT)) & LPDDR_DENALI_CTL_ODT_WR_MAP_CS1_MASK)

#define LPDDR_DENALI_CTL_PHYMSTR_NO_AREF_MASK    (0x1000000U)
#define LPDDR_DENALI_CTL_PHYMSTR_NO_AREF_SHIFT   (24U)
/*! PHYMSTR_NO_AREF
 *  0b0..Allow refreshes while the dfi_phymstr_req and dfi_phymstr_ack signals are asserted.
 *  0b1..Disable refreshes while the dfi_phymstr_req and dfi_phymstr_ack signals are asserted.
 */
#define LPDDR_DENALI_CTL_PHYMSTR_NO_AREF(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PHYMSTR_NO_AREF_SHIFT)) & LPDDR_DENALI_CTL_PHYMSTR_NO_AREF_MASK)

#define LPDDR_DENALI_CTL_PLACEMENT_EN_MASK       (0x1000000U)
#define LPDDR_DENALI_CTL_PLACEMENT_EN_SHIFT      (24U)
/*! PLACEMENT_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_PLACEMENT_EN(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PLACEMENT_EN_SHIFT)) & LPDDR_DENALI_CTL_PLACEMENT_EN_MASK)

#define LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F1_MASK (0x3000000U)
#define LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F1_SHIFT (24U)
/*! PREAMBLE_SUPPORT_F1 - Selects the preamble for read and write burst transfers for frequency set 1. */
#define LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F1_SHIFT)) & LPDDR_DENALI_CTL_PREAMBLE_SUPPORT_F1_MASK)

#define LPDDR_DENALI_CTL_Q_FULLNESS_MASK         (0xF000000U)
#define LPDDR_DENALI_CTL_Q_FULLNESS_SHIFT        (24U)
#define LPDDR_DENALI_CTL_Q_FULLNESS(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_Q_FULLNESS_SHIFT)) & LPDDR_DENALI_CTL_Q_FULLNESS_MASK)

#define LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F0_MASK  (0x1F000000U)
#define LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F0_SHIFT (24U)
#define LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F0_SHIFT)) & LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F0_MASK)

#define LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F1_MASK  (0x1F000000U)
#define LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F1_SHIFT (24U)
#define LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F1_SHIFT)) & LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F1_MASK)

#define LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F2_MASK  (0x1F000000U)
#define LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F2_SHIFT (24U)
#define LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F2_SHIFT)) & LPDDR_DENALI_CTL_R2W_DIFFCS_DLY_F2_MASK)

#define LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F0_MASK  (0x1F000000U)
#define LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F0_SHIFT (24U)
#define LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F0_SHIFT)) & LPDDR_DENALI_CTL_R2W_SAMECS_DLY_F0_MASK)

#define LPDDR_DENALI_CTL_RD_DBI_EN_MASK          (0x1000000U)
#define LPDDR_DENALI_CTL_RD_DBI_EN_SHIFT         (24U)
/*! RD_DBI_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_RD_DBI_EN(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RD_DBI_EN_SHIFT)) & LPDDR_DENALI_CTL_RD_DBI_EN_MASK)

#define LPDDR_DENALI_CTL_REDUC_MASK              (0x1000000U)
#define LPDDR_DENALI_CTL_REDUC_SHIFT             (24U)
#define LPDDR_DENALI_CTL_REDUC(x)                (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_REDUC_SHIFT)) & LPDDR_DENALI_CTL_REDUC_MASK)

#define LPDDR_DENALI_CTL_ROW_DIFF_MASK           (0x7000000U)
#define LPDDR_DENALI_CTL_ROW_DIFF_SHIFT          (24U)
#define LPDDR_DENALI_CTL_ROW_DIFF(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ROW_DIFF_SHIFT)) & LPDDR_DENALI_CTL_ROW_DIFF_MASK)

#define LPDDR_DENALI_CTL_RW2MRW_DLY_F0_MASK      (0x1F000000U)
#define LPDDR_DENALI_CTL_RW2MRW_DLY_F0_SHIFT     (24U)
#define LPDDR_DENALI_CTL_RW2MRW_DLY_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_RW2MRW_DLY_F0_SHIFT)) & LPDDR_DENALI_CTL_RW2MRW_DLY_F0_MASK)

#define LPDDR_DENALI_CTL_SWAP_EN_MASK            (0x1000000U)
#define LPDDR_DENALI_CTL_SWAP_EN_SHIFT           (24U)
/*! SWAP_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_CTL_SWAP_EN(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_SWAP_EN_SHIFT)) & LPDDR_DENALI_CTL_SWAP_EN_MASK)

#define LPDDR_DENALI_CTL_TCCD_MASK               (0x1F000000U)
#define LPDDR_DENALI_CTL_TCCD_SHIFT              (24U)
#define LPDDR_DENALI_CTL_TCCD(x)                 (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCCD_SHIFT)) & LPDDR_DENALI_CTL_TCCD_MASK)

#define LPDDR_DENALI_CTL_TCKEHCS_F0_MASK         (0x1F000000U)
#define LPDDR_DENALI_CTL_TCKEHCS_F0_SHIFT        (24U)
#define LPDDR_DENALI_CTL_TCKEHCS_F0(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKEHCS_F0_SHIFT)) & LPDDR_DENALI_CTL_TCKEHCS_F0_MASK)

#define LPDDR_DENALI_CTL_TCKEHCS_F2_MASK         (0x1F000000U)
#define LPDDR_DENALI_CTL_TCKEHCS_F2_SHIFT        (24U)
#define LPDDR_DENALI_CTL_TCKEHCS_F2(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKEHCS_F2_SHIFT)) & LPDDR_DENALI_CTL_TCKEHCS_F2_MASK)

#define LPDDR_DENALI_CTL_TCKE_F0_MASK            (0x1F000000U)
#define LPDDR_DENALI_CTL_TCKE_F0_SHIFT           (24U)
#define LPDDR_DENALI_CTL_TCKE_F0(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKE_F0_SHIFT)) & LPDDR_DENALI_CTL_TCKE_F0_MASK)

#define LPDDR_DENALI_CTL_TCKE_F1_MASK            (0x1F000000U)
#define LPDDR_DENALI_CTL_TCKE_F1_SHIFT           (24U)
#define LPDDR_DENALI_CTL_TCKE_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKE_F1_SHIFT)) & LPDDR_DENALI_CTL_TCKE_F1_MASK)

#define LPDDR_DENALI_CTL_TCKE_F2_MASK            (0x1F000000U)
#define LPDDR_DENALI_CTL_TCKE_F2_SHIFT           (24U)
#define LPDDR_DENALI_CTL_TCKE_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKE_F2_SHIFT)) & LPDDR_DENALI_CTL_TCKE_F2_MASK)

#define LPDDR_DENALI_CTL_TCKFSPX_F1_MASK         (0x1F000000U)
#define LPDDR_DENALI_CTL_TCKFSPX_F1_SHIFT        (24U)
#define LPDDR_DENALI_CTL_TCKFSPX_F1(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKFSPX_F1_SHIFT)) & LPDDR_DENALI_CTL_TCKFSPX_F1_MASK)

#define LPDDR_DENALI_CTL_TCKFSPX_F2_MASK         (0x1F000000U)
#define LPDDR_DENALI_CTL_TCKFSPX_F2_SHIFT        (24U)
#define LPDDR_DENALI_CTL_TCKFSPX_F2(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCKFSPX_F2_SHIFT)) & LPDDR_DENALI_CTL_TCKFSPX_F2_MASK)

#define LPDDR_DENALI_CTL_TCMDCKE_F0_MASK         (0x1F000000U)
#define LPDDR_DENALI_CTL_TCMDCKE_F0_SHIFT        (24U)
#define LPDDR_DENALI_CTL_TCMDCKE_F0(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCMDCKE_F0_SHIFT)) & LPDDR_DENALI_CTL_TCMDCKE_F0_MASK)

#define LPDDR_DENALI_CTL_TCMDCKE_F1_MASK         (0x1F000000U)
#define LPDDR_DENALI_CTL_TCMDCKE_F1_SHIFT        (24U)
#define LPDDR_DENALI_CTL_TCMDCKE_F1(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCMDCKE_F1_SHIFT)) & LPDDR_DENALI_CTL_TCMDCKE_F1_MASK)

#define LPDDR_DENALI_CTL_TCMDCKE_F2_MASK         (0x1F000000U)
#define LPDDR_DENALI_CTL_TCMDCKE_F2_SHIFT        (24U)
#define LPDDR_DENALI_CTL_TCMDCKE_F2(x)           (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCMDCKE_F2_SHIFT)) & LPDDR_DENALI_CTL_TCMDCKE_F2_MASK)

#define LPDDR_DENALI_CTL_TCSCKE_F1_MASK          (0x1F000000U)
#define LPDDR_DENALI_CTL_TCSCKE_F1_SHIFT         (24U)
#define LPDDR_DENALI_CTL_TCSCKE_F1(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TCSCKE_F1_SHIFT)) & LPDDR_DENALI_CTL_TCSCKE_F1_MASK)

#define LPDDR_DENALI_CTL_TDAL_F0_MASK            (0xFF000000U)
#define LPDDR_DENALI_CTL_TDAL_F0_SHIFT           (24U)
#define LPDDR_DENALI_CTL_TDAL_F0(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDAL_F0_SHIFT)) & LPDDR_DENALI_CTL_TDAL_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F1_MASK (0xF000000U)
#define LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F1_SHIFT (24U)
#define LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F1(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_CTRL_DELAY_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F1_MASK  (0x7F000000U)
#define LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F1_SHIFT (24U)
/*! TDFI_PHY_RDLAT_F1 - Defines the DFI tPHY_RDLAT timing parameter (in DFI PHY clocks), the maximum
 *    cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion.
 */
#define LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F1_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHY_RDLAT_F1_MASK)

#define LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F0_MASK (0x7000000U)
#define LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F0_SHIFT (24U)
#define LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F0(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_PHY_WRDATA_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_WRCSLAT_F0_MASK    (0x7F000000U)
#define LPDDR_DENALI_CTL_TDFI_WRCSLAT_F0_SHIFT   (24U)
#define LPDDR_DENALI_CTL_TDFI_WRCSLAT_F0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_WRCSLAT_F0_SHIFT)) & LPDDR_DENALI_CTL_TDFI_WRCSLAT_F0_MASK)

#define LPDDR_DENALI_CTL_TDFI_WRCSLAT_F2_MASK    (0x7F000000U)
#define LPDDR_DENALI_CTL_TDFI_WRCSLAT_F2_SHIFT   (24U)
#define LPDDR_DENALI_CTL_TDFI_WRCSLAT_F2(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDFI_WRCSLAT_F2_SHIFT)) & LPDDR_DENALI_CTL_TDFI_WRCSLAT_F2_MASK)

#define LPDDR_DENALI_CTL_TDQSCK_MIN_F1_MASK      (0x7000000U)
#define LPDDR_DENALI_CTL_TDQSCK_MIN_F1_SHIFT     (24U)
#define LPDDR_DENALI_CTL_TDQSCK_MIN_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TDQSCK_MIN_F1_SHIFT)) & LPDDR_DENALI_CTL_TDQSCK_MIN_F1_MASK)

#define LPDDR_DENALI_CTL_TMOD_F1_MASK            (0xFF000000U)
#define LPDDR_DENALI_CTL_TMOD_F1_SHIFT           (24U)
#define LPDDR_DENALI_CTL_TMOD_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TMOD_F1_SHIFT)) & LPDDR_DENALI_CTL_TMOD_F1_MASK)

#define LPDDR_DENALI_CTL_TMOD_F2_MASK            (0xFF000000U)
#define LPDDR_DENALI_CTL_TMOD_F2_SHIFT           (24U)
#define LPDDR_DENALI_CTL_TMOD_F2(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TMOD_F2_SHIFT)) & LPDDR_DENALI_CTL_TMOD_F2_MASK)

#define LPDDR_DENALI_CTL_TMRR_MASK               (0xF000000U)
#define LPDDR_DENALI_CTL_TMRR_SHIFT              (24U)
#define LPDDR_DENALI_CTL_TMRR(x)                 (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TMRR_SHIFT)) & LPDDR_DENALI_CTL_TMRR_MASK)

#define LPDDR_DENALI_CTL_TMRRI_F1_MASK           (0xFF000000U)
#define LPDDR_DENALI_CTL_TMRRI_F1_SHIFT          (24U)
#define LPDDR_DENALI_CTL_TMRRI_F1(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TMRRI_F1_SHIFT)) & LPDDR_DENALI_CTL_TMRRI_F1_MASK)

#define LPDDR_DENALI_CTL_TODTH_WR_F2_MASK        (0xF000000U)
#define LPDDR_DENALI_CTL_TODTH_WR_F2_SHIFT       (24U)
#define LPDDR_DENALI_CTL_TODTH_WR_F2(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TODTH_WR_F2_SHIFT)) & LPDDR_DENALI_CTL_TODTH_WR_F2_MASK)

#define LPDDR_DENALI_CTL_TODTL_2CMD_F1_MASK      (0xFF000000U)
#define LPDDR_DENALI_CTL_TODTL_2CMD_F1_SHIFT     (24U)
#define LPDDR_DENALI_CTL_TODTL_2CMD_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TODTL_2CMD_F1_SHIFT)) & LPDDR_DENALI_CTL_TODTL_2CMD_F1_MASK)

#define LPDDR_DENALI_CTL_TOSCO_F0_MASK           (0xFF000000U)
#define LPDDR_DENALI_CTL_TOSCO_F0_SHIFT          (24U)
#define LPDDR_DENALI_CTL_TOSCO_F0(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TOSCO_F0_SHIFT)) & LPDDR_DENALI_CTL_TOSCO_F0_MASK)

#define LPDDR_DENALI_CTL_TRCD_F1_MASK            (0xFF000000U)
#define LPDDR_DENALI_CTL_TRCD_F1_SHIFT           (24U)
#define LPDDR_DENALI_CTL_TRCD_F1(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRCD_F1_SHIFT)) & LPDDR_DENALI_CTL_TRCD_F1_MASK)

#define LPDDR_DENALI_CTL_TRP_AB_F0_MASK          (0xFF000000U)
#define LPDDR_DENALI_CTL_TRP_AB_F0_SHIFT         (24U)
#define LPDDR_DENALI_CTL_TRP_AB_F0(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRP_AB_F0_SHIFT)) & LPDDR_DENALI_CTL_TRP_AB_F0_MASK)

#define LPDDR_DENALI_CTL_TRP_F0_MASK             (0xFF000000U)
#define LPDDR_DENALI_CTL_TRP_F0_SHIFT            (24U)
#define LPDDR_DENALI_CTL_TRP_F0(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRP_F0_SHIFT)) & LPDDR_DENALI_CTL_TRP_F0_MASK)

#define LPDDR_DENALI_CTL_TRP_F2_MASK             (0xFF000000U)
#define LPDDR_DENALI_CTL_TRP_F2_SHIFT            (24U)
#define LPDDR_DENALI_CTL_TRP_F2(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRP_F2_SHIFT)) & LPDDR_DENALI_CTL_TRP_F2_MASK)

#define LPDDR_DENALI_CTL_TRTP_F0_MASK            (0xFF000000U)
#define LPDDR_DENALI_CTL_TRTP_F0_SHIFT           (24U)
#define LPDDR_DENALI_CTL_TRTP_F0(x)              (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TRTP_F0_SHIFT)) & LPDDR_DENALI_CTL_TRTP_F0_MASK)

#define LPDDR_DENALI_CTL_TSR_F0_MASK             (0xFF000000U)
#define LPDDR_DENALI_CTL_TSR_F0_SHIFT            (24U)
#define LPDDR_DENALI_CTL_TSR_F0(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TSR_F0_SHIFT)) & LPDDR_DENALI_CTL_TSR_F0_MASK)

#define LPDDR_DENALI_CTL_TSR_F1_MASK             (0xFF000000U)
#define LPDDR_DENALI_CTL_TSR_F1_SHIFT            (24U)
#define LPDDR_DENALI_CTL_TSR_F1(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TSR_F1_SHIFT)) & LPDDR_DENALI_CTL_TSR_F1_MASK)

#define LPDDR_DENALI_CTL_TSR_F2_MASK             (0xFF000000U)
#define LPDDR_DENALI_CTL_TSR_F2_SHIFT            (24U)
#define LPDDR_DENALI_CTL_TSR_F2(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TSR_F2_SHIFT)) & LPDDR_DENALI_CTL_TSR_F2_MASK)

#define LPDDR_DENALI_CTL_TZQCKE_F1_MASK          (0xF000000U)
#define LPDDR_DENALI_CTL_TZQCKE_F1_SHIFT         (24U)
#define LPDDR_DENALI_CTL_TZQCKE_F1(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_TZQCKE_F1_SHIFT)) & LPDDR_DENALI_CTL_TZQCKE_F1_MASK)

#define LPDDR_DENALI_CTL_W2W_SAMECS_DLY_MASK     (0x1F000000U)
#define LPDDR_DENALI_CTL_W2W_SAMECS_DLY_SHIFT    (24U)
#define LPDDR_DENALI_CTL_W2W_SAMECS_DLY(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_W2W_SAMECS_DLY_SHIFT)) & LPDDR_DENALI_CTL_W2W_SAMECS_DLY_MASK)

#define LPDDR_DENALI_CTL_WRLAT_F1_MASK           (0x7F000000U)
#define LPDDR_DENALI_CTL_WRLAT_F1_SHIFT          (24U)
#define LPDDR_DENALI_CTL_WRLAT_F1(x)             (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_WRLAT_F1_SHIFT)) & LPDDR_DENALI_CTL_WRLAT_F1_MASK)

#define LPDDR_DENALI_CTL_WR_TO_ODTH_F2_MASK      (0x3F000000U)
#define LPDDR_DENALI_CTL_WR_TO_ODTH_F2_SHIFT     (24U)
#define LPDDR_DENALI_CTL_WR_TO_ODTH_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_WR_TO_ODTH_F2_SHIFT)) & LPDDR_DENALI_CTL_WR_TO_ODTH_F2_MASK)

#define LPDDR_DENALI_CTL_ZQCS_ROTATE_MASK        (0x1000000U)
#define LPDDR_DENALI_CTL_ZQCS_ROTATE_SHIFT       (24U)
#define LPDDR_DENALI_CTL_ZQCS_ROTATE(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQCS_ROTATE_SHIFT)) & LPDDR_DENALI_CTL_ZQCS_ROTATE_MASK)

#define LPDDR_DENALI_CTL_ZQ_REQ_PENDING_MASK     (0x1000000U)
#define LPDDR_DENALI_CTL_ZQ_REQ_PENDING_SHIFT    (24U)
/*! ZQ_REQ_PENDING
 *  0b0..Not in progress or waiting
 *  0b1..In progress or Waiting. No writes should occur to zq_req while this bit is set to 'b1.
 */
#define LPDDR_DENALI_CTL_ZQ_REQ_PENDING(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_CTL_ZQ_REQ_PENDING_SHIFT)) & LPDDR_DENALI_CTL_ZQ_REQ_PENDING_MASK)
/*! @} */

/* The count of LPDDR_DENALI_CTL */
#define LPDDR_DENALI_CTL_COUNT                   (615U)

/*! @name DENALI_PI_0 - DENALI_PI_0 */
/*! @{ */

#define LPDDR_DENALI_PI_0_PI_START_MASK          (0x1U)
#define LPDDR_DENALI_PI_0_PI_START_SHIFT         (0U)
#define LPDDR_DENALI_PI_0_PI_START(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_0_PI_START_SHIFT)) & LPDDR_DENALI_PI_0_PI_START_MASK)

#define LPDDR_DENALI_PI_0_PI_DRAM_CLASS_MASK     (0xF00U)
#define LPDDR_DENALI_PI_0_PI_DRAM_CLASS_SHIFT    (8U)
#define LPDDR_DENALI_PI_0_PI_DRAM_CLASS(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_0_PI_DRAM_CLASS_SHIFT)) & LPDDR_DENALI_PI_0_PI_DRAM_CLASS_MASK)
/*! @} */

/*! @name DENALI_PI_3 - DENALI_PI_3 */
/*! @{ */

#define LPDDR_DENALI_PI_3_PI_ID_MASK             (0xFFFFU)
#define LPDDR_DENALI_PI_3_PI_ID_SHIFT            (0U)
#define LPDDR_DENALI_PI_3_PI_ID(x)               (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_3_PI_ID_SHIFT)) & LPDDR_DENALI_PI_3_PI_ID_MASK)

#define LPDDR_DENALI_PI_3_PI_RELEASE_DFI_MASK    (0x10000U)
#define LPDDR_DENALI_PI_3_PI_RELEASE_DFI_SHIFT   (16U)
/*! PI_RELEASE_DFI
 *  0b0..DFI is released
 *  0b1..DFI under PI control
 */
#define LPDDR_DENALI_PI_3_PI_RELEASE_DFI(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_3_PI_RELEASE_DFI_SHIFT)) & LPDDR_DENALI_PI_3_PI_RELEASE_DFI_MASK)

#define LPDDR_DENALI_PI_3_PI_NORMAL_LVL_SEQ_MASK (0x1000000U)
#define LPDDR_DENALI_PI_3_PI_NORMAL_LVL_SEQ_SHIFT (24U)
/*! PI_NORMAL_LVL_SEQ
 *  0b0..Return DFI bus to the controller after current leveling request is complete (except for initialization)
 *  0b1..Return DFI bus to the controller after all pending leveling requests are complete
 */
#define LPDDR_DENALI_PI_3_PI_NORMAL_LVL_SEQ(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_3_PI_NORMAL_LVL_SEQ_SHIFT)) & LPDDR_DENALI_PI_3_PI_NORMAL_LVL_SEQ_MASK)
/*! @} */

/*! @name DENALI_PI_4 - DENALI_PI_4 */
/*! @{ */

#define LPDDR_DENALI_PI_4_PI_INIT_LVL_EN_MASK    (0x1U)
#define LPDDR_DENALI_PI_4_PI_INIT_LVL_EN_SHIFT   (0U)
/*! PI_INIT_LVL_EN
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPDDR_DENALI_PI_4_PI_INIT_LVL_EN(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_4_PI_INIT_LVL_EN_SHIFT)) & LPDDR_DENALI_PI_4_PI_INIT_LVL_EN_MASK)

#define LPDDR_DENALI_PI_4_PI_NOTCARE_PHYUPD_MASK (0x300U)
#define LPDDR_DENALI_PI_4_PI_NOTCARE_PHYUPD_SHIFT (8U)
/*! PI_NOTCARE_PHYUPD
 *  0b00..PI not issue master request
 *  0b01..PI issue master request
 */
#define LPDDR_DENALI_PI_4_PI_NOTCARE_PHYUPD(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_4_PI_NOTCARE_PHYUPD_SHIFT)) & LPDDR_DENALI_PI_4_PI_NOTCARE_PHYUPD_MASK)

#define LPDDR_DENALI_PI_4_PI_TCMD_GAP_MASK       (0xFFFF0000U)
#define LPDDR_DENALI_PI_4_PI_TCMD_GAP_SHIFT      (16U)
#define LPDDR_DENALI_PI_4_PI_TCMD_GAP(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_4_PI_TCMD_GAP_SHIFT)) & LPDDR_DENALI_PI_4_PI_TCMD_GAP_MASK)
/*! @} */

/*! @name DENALI_PI_5 - DENALI_PI_5 */
/*! @{ */

#define LPDDR_DENALI_PI_5_PI_TRAIN_ALL_FREQ_REQ_MASK (0x100U)
#define LPDDR_DENALI_PI_5_PI_TRAIN_ALL_FREQ_REQ_SHIFT (8U)
#define LPDDR_DENALI_PI_5_PI_TRAIN_ALL_FREQ_REQ(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_5_PI_TRAIN_ALL_FREQ_REQ_SHIFT)) & LPDDR_DENALI_PI_5_PI_TRAIN_ALL_FREQ_REQ_MASK)

#define LPDDR_DENALI_PI_5_PI_DFI_VERSION_MASK    (0x10000U)
#define LPDDR_DENALI_PI_5_PI_DFI_VERSION_SHIFT   (16U)
/*! PI_DFI_VERSION
 *  0b0..DFI 4.0 version
 *  0b1..DFI 4.1 version
 */
#define LPDDR_DENALI_PI_5_PI_DFI_VERSION(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_5_PI_DFI_VERSION_SHIFT)) & LPDDR_DENALI_PI_5_PI_DFI_VERSION_MASK)

#define LPDDR_DENALI_PI_5_PI_DFI_PHYMSTR_TYPE_MASK (0x3000000U)
#define LPDDR_DENALI_PI_5_PI_DFI_PHYMSTR_TYPE_SHIFT (24U)
/*! PI_DFI_PHYMSTR_TYPE
 *  0b00..IDLE. The MC should close all pages.
 *  0b01..IDLE or Self Refresh.
 */
#define LPDDR_DENALI_PI_5_PI_DFI_PHYMSTR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_5_PI_DFI_PHYMSTR_TYPE_SHIFT)) & LPDDR_DENALI_PI_5_PI_DFI_PHYMSTR_TYPE_MASK)
/*! @} */

/*! @name DENALI_PI_11 - DENALI_PI_11 */
/*! @{ */

#define LPDDR_DENALI_PI_11_PI_EXIT_AFTER_INIT_CALVL_MASK (0x1U)
#define LPDDR_DENALI_PI_11_PI_EXIT_AFTER_INIT_CALVL_SHIFT (0U)
#define LPDDR_DENALI_PI_11_PI_EXIT_AFTER_INIT_CALVL(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_11_PI_EXIT_AFTER_INIT_CALVL_SHIFT)) & LPDDR_DENALI_PI_11_PI_EXIT_AFTER_INIT_CALVL_MASK)

#define LPDDR_DENALI_PI_11_PI_INIT_WORK_FREQ_MASK (0x1F00U)
#define LPDDR_DENALI_PI_11_PI_INIT_WORK_FREQ_SHIFT (8U)
/*! PI_INIT_WORK_FREQ - Indicates the initial work frequency after initialization and initial leveling sequence. */
#define LPDDR_DENALI_PI_11_PI_INIT_WORK_FREQ(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_11_PI_INIT_WORK_FREQ_SHIFT)) & LPDDR_DENALI_PI_11_PI_INIT_WORK_FREQ_MASK)

#define LPDDR_DENALI_PI_11_PI_INIT_DFS_CALVL_ONLY_MASK (0x10000U)
#define LPDDR_DENALI_PI_11_PI_INIT_DFS_CALVL_ONLY_SHIFT (16U)
/*! PI_INIT_DFS_CALVL_ONLY
 *  0b0..Perform all trainings at each frequency.
 *  0b1..Perform frequency training only for CA leveling.
 */
#define LPDDR_DENALI_PI_11_PI_INIT_DFS_CALVL_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_11_PI_INIT_DFS_CALVL_ONLY_SHIFT)) & LPDDR_DENALI_PI_11_PI_INIT_DFS_CALVL_ONLY_MASK)
/*! @} */

/*! @name DENALI_PI_12 - DENALI_PI_12 */
/*! @{ */

#define LPDDR_DENALI_PI_12_PI_FREQ_MAP_MASK      (0xFFFFFFFFU)
#define LPDDR_DENALI_PI_12_PI_FREQ_MAP_SHIFT     (0U)
#define LPDDR_DENALI_PI_12_PI_FREQ_MAP(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_12_PI_FREQ_MAP_SHIFT)) & LPDDR_DENALI_PI_12_PI_FREQ_MAP_MASK)
/*! @} */

/*! @name DENALI_PI_13 - DENALI_PI_13 */
/*! @{ */

#define LPDDR_DENALI_PI_13_PI_SW_RST_N_MASK      (0x1U)
#define LPDDR_DENALI_PI_13_PI_SW_RST_N_SHIFT     (0U)
#define LPDDR_DENALI_PI_13_PI_SW_RST_N(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_13_PI_SW_RST_N_SHIFT)) & LPDDR_DENALI_PI_13_PI_SW_RST_N_MASK)

#define LPDDR_DENALI_PI_13_PI_CS_MAP_MASK        (0xF0000U)
#define LPDDR_DENALI_PI_13_PI_CS_MAP_SHIFT       (16U)
/*! PI_CS_MAP - Defines which chip selects are active. */
#define LPDDR_DENALI_PI_13_PI_CS_MAP(x)          (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_13_PI_CS_MAP_SHIFT)) & LPDDR_DENALI_PI_13_PI_CS_MAP_MASK)

#define LPDDR_DENALI_PI_13_PI_RANK_NUM_PER_CKE_MASK (0x1F000000U)
#define LPDDR_DENALI_PI_13_PI_RANK_NUM_PER_CKE_SHIFT (24U)
/*! PI_RANK_NUM_PER_CKE - Defines the number of chip selects share one cke */
#define LPDDR_DENALI_PI_13_PI_RANK_NUM_PER_CKE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_13_PI_RANK_NUM_PER_CKE_SHIFT)) & LPDDR_DENALI_PI_13_PI_RANK_NUM_PER_CKE_MASK)
/*! @} */

/*! @name DENALI_PI_14 - DENALI_PI_14 */
/*! @{ */

#define LPDDR_DENALI_PI_14_PI_SRX_LVL_TARGET_CS_EN_MASK (0x1U)
#define LPDDR_DENALI_PI_14_PI_SRX_LVL_TARGET_CS_EN_SHIFT (0U)
/*! PI_SRX_LVL_TARGET_CS_EN
 *  0b0..All CS defined by pi_cs_map
 *  0b1..Only target CS
 */
#define LPDDR_DENALI_PI_14_PI_SRX_LVL_TARGET_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_14_PI_SRX_LVL_TARGET_CS_EN_SHIFT)) & LPDDR_DENALI_PI_14_PI_SRX_LVL_TARGET_CS_EN_MASK)

#define LPDDR_DENALI_PI_14_PI_TMRR_MASK          (0xF00U)
#define LPDDR_DENALI_PI_14_PI_TMRR_SHIFT         (8U)
/*! PI_TMRR - DRAM tMRR value in memory clock cycles. */
#define LPDDR_DENALI_PI_14_PI_TMRR(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_14_PI_TMRR_SHIFT)) & LPDDR_DENALI_PI_14_PI_TMRR_MASK)

#define LPDDR_DENALI_PI_14_PI_PREAMBLE_SUPPORT_MASK (0x30000U)
#define LPDDR_DENALI_PI_14_PI_PREAMBLE_SUPPORT_SHIFT (16U)
#define LPDDR_DENALI_PI_14_PI_PREAMBLE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_14_PI_PREAMBLE_SUPPORT_SHIFT)) & LPDDR_DENALI_PI_14_PI_PREAMBLE_SUPPORT_MASK)

#define LPDDR_DENALI_PI_14_PI_VRCG_EN_MASK       (0x3000000U)
#define LPDDR_DENALI_PI_14_PI_VRCG_EN_SHIFT      (24U)
#define LPDDR_DENALI_PI_14_PI_VRCG_EN(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_14_PI_VRCG_EN_SHIFT)) & LPDDR_DENALI_PI_14_PI_VRCG_EN_MASK)
/*! @} */

/*! @name DENALI_PI_15 - DENALI_PI_15 */
/*! @{ */

#define LPDDR_DENALI_PI_15_PI_MCAREF_FORWARD_ONLY_MASK (0x1U)
#define LPDDR_DENALI_PI_15_PI_MCAREF_FORWARD_ONLY_SHIFT (0U)
/*! PI_MCAREF_FORWARD_ONLY
 *  0b0..PI generates AREF commands
 *  0b1..PI does not generate AREF; only forwards AREF from the memory controller
 */
#define LPDDR_DENALI_PI_15_PI_MCAREF_FORWARD_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_15_PI_MCAREF_FORWARD_ONLY_SHIFT)) & LPDDR_DENALI_PI_15_PI_MCAREF_FORWARD_ONLY_MASK)
/*! @} */

/*! @name DENALI_PI_16 - DENALI_PI_16 */
/*! @{ */

#define LPDDR_DENALI_PI_16_PI_TREF_INTERVAL_MASK (0xFFFFFU)
#define LPDDR_DENALI_PI_16_PI_TREF_INTERVAL_SHIFT (0U)
/*! PI_TREF_INTERVAL - Defines the cycles between refreshes to different chip selects. */
#define LPDDR_DENALI_PI_16_PI_TREF_INTERVAL(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_16_PI_TREF_INTERVAL_SHIFT)) & LPDDR_DENALI_PI_16_PI_TREF_INTERVAL_MASK)

#define LPDDR_DENALI_PI_16_PI_ON_DFIBUS_MASK     (0x1000000U)
#define LPDDR_DENALI_PI_16_PI_ON_DFIBUS_SHIFT    (24U)
/*! PI_ON_DFIBUS
 *  0b0..PI not controlling the DFI bus
 *  0b1..PI in control of the DFI bus
 */
#define LPDDR_DENALI_PI_16_PI_ON_DFIBUS(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_16_PI_ON_DFIBUS_SHIFT)) & LPDDR_DENALI_PI_16_PI_ON_DFIBUS_MASK)
/*! @} */

/*! @name DENALI_PI_29 - DENALI_PI_29 */
/*! @{ */

#define LPDDR_DENALI_PI_29_PI_WRLVL_CS_MAP_MASK  (0xFU)
#define LPDDR_DENALI_PI_29_PI_WRLVL_CS_MAP_SHIFT (0U)
#define LPDDR_DENALI_PI_29_PI_WRLVL_CS_MAP(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_29_PI_WRLVL_CS_MAP_SHIFT)) & LPDDR_DENALI_PI_29_PI_WRLVL_CS_MAP_MASK)

#define LPDDR_DENALI_PI_29_PI_WRLVL_ERROR_STATUS_MASK (0x100U)
#define LPDDR_DENALI_PI_29_PI_WRLVL_ERROR_STATUS_SHIFT (8U)
#define LPDDR_DENALI_PI_29_PI_WRLVL_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_29_PI_WRLVL_ERROR_STATUS_SHIFT)) & LPDDR_DENALI_PI_29_PI_WRLVL_ERROR_STATUS_MASK)

#define LPDDR_DENALI_PI_29_PI_TDFI_WRLVL_EN_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_29_PI_TDFI_WRLVL_EN_SHIFT (16U)
#define LPDDR_DENALI_PI_29_PI_TDFI_WRLVL_EN(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_29_PI_TDFI_WRLVL_EN_SHIFT)) & LPDDR_DENALI_PI_29_PI_TDFI_WRLVL_EN_MASK)
/*! @} */

/*! @name DENALI_PI_44 - DENALI_PI_44 */
/*! @{ */

#define LPDDR_DENALI_PI_44_PI_RDLVL_CS_MAP_MASK  (0xF0000U)
#define LPDDR_DENALI_PI_44_PI_RDLVL_CS_MAP_SHIFT (16U)
/*! PI_RDLVL_CS_MAP
 *  0b0000..Do not use this chip for data eye training
 *  0b0001..Use this chip for data eye training
 */
#define LPDDR_DENALI_PI_44_PI_RDLVL_CS_MAP(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_44_PI_RDLVL_CS_MAP_SHIFT)) & LPDDR_DENALI_PI_44_PI_RDLVL_CS_MAP_MASK)

#define LPDDR_DENALI_PI_44_PI_RDLVL_GATE_CS_MAP_MASK (0xF000000U)
#define LPDDR_DENALI_PI_44_PI_RDLVL_GATE_CS_MAP_SHIFT (24U)
/*! PI_RDLVL_GATE_CS_MAP
 *  0b0000..Do not use this chip for gate training
 *  0b0001..Use this chip for gate training
 */
#define LPDDR_DENALI_PI_44_PI_RDLVL_GATE_CS_MAP(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_44_PI_RDLVL_GATE_CS_MAP_SHIFT)) & LPDDR_DENALI_PI_44_PI_RDLVL_GATE_CS_MAP_MASK)
/*! @} */

/*! @name DENALI_PI_45 - DENALI_PI_45 */
/*! @{ */

#define LPDDR_DENALI_PI_45_PI_TDFI_RDLVL_RR_MASK (0x3FFU)
#define LPDDR_DENALI_PI_45_PI_TDFI_RDLVL_RR_SHIFT (0U)
#define LPDDR_DENALI_PI_45_PI_TDFI_RDLVL_RR(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_45_PI_TDFI_RDLVL_RR_SHIFT)) & LPDDR_DENALI_PI_45_PI_TDFI_RDLVL_RR_MASK)
/*! @} */

/*! @name DENALI_PI_55 - DENALI_PI_55 */
/*! @{ */

#define LPDDR_DENALI_PI_55_PI_CALVL_CS_MAP_MASK  (0xF00U)
#define LPDDR_DENALI_PI_55_PI_CALVL_CS_MAP_SHIFT (8U)
#define LPDDR_DENALI_PI_55_PI_CALVL_CS_MAP(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_55_PI_CALVL_CS_MAP_SHIFT)) & LPDDR_DENALI_PI_55_PI_CALVL_CS_MAP_MASK)

#define LPDDR_DENALI_PI_55_PI_TDFI_CALVL_EN_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_55_PI_TDFI_CALVL_EN_SHIFT (16U)
#define LPDDR_DENALI_PI_55_PI_TDFI_CALVL_EN(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_55_PI_TDFI_CALVL_EN_SHIFT)) & LPDDR_DENALI_PI_55_PI_TDFI_CALVL_EN_MASK)
/*! @} */

/*! @name DENALI_PI_64 - DENALI_PI_64 */
/*! @{ */

#define LPDDR_DENALI_PI_64_PI_WDQLVL_BST_NUM_MASK (0x7U)
#define LPDDR_DENALI_PI_64_PI_WDQLVL_BST_NUM_SHIFT (0U)
/*! PI_WDQLVL_BST_NUM - Defines the number of write/read bursts issued at each step in write DQ training. */
#define LPDDR_DENALI_PI_64_PI_WDQLVL_BST_NUM(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_64_PI_WDQLVL_BST_NUM_SHIFT)) & LPDDR_DENALI_PI_64_PI_WDQLVL_BST_NUM_MASK)

#define LPDDR_DENALI_PI_64_PI_WDQLVL_RESP_MASK_MASK (0xF00U)
#define LPDDR_DENALI_PI_64_PI_WDQLVL_RESP_MASK_SHIFT (8U)
#define LPDDR_DENALI_PI_64_PI_WDQLVL_RESP_MASK(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_64_PI_WDQLVL_RESP_MASK_SHIFT)) & LPDDR_DENALI_PI_64_PI_WDQLVL_RESP_MASK_MASK)

#define LPDDR_DENALI_PI_64_PI_WDQLVL_CS_MAP_MASK (0xF000000U)
#define LPDDR_DENALI_PI_64_PI_WDQLVL_CS_MAP_SHIFT (24U)
/*! PI_WDQLVL_CS_MAP
 *  0b0000..Do not use this chip for data eye training
 *  0b0001..Use this chip for data eye training
 */
#define LPDDR_DENALI_PI_64_PI_WDQLVL_CS_MAP(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_64_PI_WDQLVL_CS_MAP_SHIFT)) & LPDDR_DENALI_PI_64_PI_WDQLVL_CS_MAP_MASK)
/*! @} */

/*! @name DENALI_PI_70 - DENALI_PI_70 */
/*! @{ */

#define LPDDR_DENALI_PI_70_PI_WDQLVL_DISABLE_DFS_MASK (0x1U)
#define LPDDR_DENALI_PI_70_PI_WDQLVL_DISABLE_DFS_SHIFT (0U)
/*! PI_WDQLVL_DISABLE_DFS
 *  0b0..Enabled
 *  0b1..Disabled
 */
#define LPDDR_DENALI_PI_70_PI_WDQLVL_DISABLE_DFS(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_70_PI_WDQLVL_DISABLE_DFS_SHIFT)) & LPDDR_DENALI_PI_70_PI_WDQLVL_DISABLE_DFS_MASK)

#define LPDDR_DENALI_PI_70_PI_WDQLVL_OSC_EN_MASK (0x10000U)
#define LPDDR_DENALI_PI_70_PI_WDQLVL_OSC_EN_SHIFT (16U)
/*! PI_WDQLVL_OSC_EN - Enable for DQS oscillator triggered write DQ training.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPDDR_DENALI_PI_70_PI_WDQLVL_OSC_EN(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_70_PI_WDQLVL_OSC_EN_SHIFT)) & LPDDR_DENALI_PI_70_PI_WDQLVL_OSC_EN_MASK)

#define LPDDR_DENALI_PI_70_PI_PARALLEL_WDQLVL_EN_MASK (0x1000000U)
#define LPDDR_DENALI_PI_70_PI_PARALLEL_WDQLVL_EN_SHIFT (24U)
/*! PI_PARALLEL_WDQLVL_EN
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPDDR_DENALI_PI_70_PI_PARALLEL_WDQLVL_EN(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_70_PI_PARALLEL_WDQLVL_EN_SHIFT)) & LPDDR_DENALI_PI_70_PI_PARALLEL_WDQLVL_EN_MASK)
/*! @} */

/*! @name DENALI_PI_71 - DENALI_PI_71 */
/*! @{ */

#define LPDDR_DENALI_PI_71_PI_BANK_DIFF_MASK     (0x3U)
#define LPDDR_DENALI_PI_71_PI_BANK_DIFF_SHIFT    (0U)
#define LPDDR_DENALI_PI_71_PI_BANK_DIFF(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_71_PI_BANK_DIFF_SHIFT)) & LPDDR_DENALI_PI_71_PI_BANK_DIFF_MASK)

#define LPDDR_DENALI_PI_71_PI_ROW_DIFF_MASK      (0x700U)
#define LPDDR_DENALI_PI_71_PI_ROW_DIFF_SHIFT     (8U)
#define LPDDR_DENALI_PI_71_PI_ROW_DIFF(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_71_PI_ROW_DIFF_SHIFT)) & LPDDR_DENALI_PI_71_PI_ROW_DIFF_MASK)

#define LPDDR_DENALI_PI_71_PI_TCCD_MASK          (0x1F0000U)
#define LPDDR_DENALI_PI_71_PI_TCCD_SHIFT         (16U)
#define LPDDR_DENALI_PI_71_PI_TCCD(x)            (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_71_PI_TCCD_SHIFT)) & LPDDR_DENALI_PI_71_PI_TCCD_MASK)
/*! @} */

/*! @name DENALI_PI_92 - DENALI_PI_92 */
/*! @{ */

#define LPDDR_DENALI_PI_92_PI_UPDATE_ERROR_STATUS_MASK (0x3U)
#define LPDDR_DENALI_PI_92_PI_UPDATE_ERROR_STATUS_SHIFT (0U)
#define LPDDR_DENALI_PI_92_PI_UPDATE_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_92_PI_UPDATE_ERROR_STATUS_SHIFT)) & LPDDR_DENALI_PI_92_PI_UPDATE_ERROR_STATUS_MASK)

#define LPDDR_DENALI_PI_92_PI_BIST_GO_MASK       (0x100U)
#define LPDDR_DENALI_PI_92_PI_BIST_GO_SHIFT      (8U)
#define LPDDR_DENALI_PI_92_PI_BIST_GO(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_92_PI_BIST_GO_SHIFT)) & LPDDR_DENALI_PI_92_PI_BIST_GO_MASK)

#define LPDDR_DENALI_PI_92_PI_BIST_RESULT_MASK   (0x30000U)
#define LPDDR_DENALI_PI_92_PI_BIST_RESULT_SHIFT  (16U)
#define LPDDR_DENALI_PI_92_PI_BIST_RESULT(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_92_PI_BIST_RESULT_SHIFT)) & LPDDR_DENALI_PI_92_PI_BIST_RESULT_MASK)

#define LPDDR_DENALI_PI_92_PI_BIST_LFSR_PATTERN_DONE_MASK (0x1000000U)
#define LPDDR_DENALI_PI_92_PI_BIST_LFSR_PATTERN_DONE_SHIFT (24U)
#define LPDDR_DENALI_PI_92_PI_BIST_LFSR_PATTERN_DONE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_92_PI_BIST_LFSR_PATTERN_DONE_SHIFT)) & LPDDR_DENALI_PI_92_PI_BIST_LFSR_PATTERN_DONE_MASK)
/*! @} */

/*! @name DENALI_PI_161 - DENALI_PI_161 */
/*! @{ */

#define LPDDR_DENALI_PI_161_PI_NOTCARE_MC_INIT_START_MASK (0x1U)
#define LPDDR_DENALI_PI_161_PI_NOTCARE_MC_INIT_START_SHIFT (0U)
/*! PI_NOTCARE_MC_INIT_START
 *  0b0..No waiting for dfi_init_start.
 *  0b1..Wait for dfi_init_start
 */
#define LPDDR_DENALI_PI_161_PI_NOTCARE_MC_INIT_START(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_161_PI_NOTCARE_MC_INIT_START_SHIFT)) & LPDDR_DENALI_PI_161_PI_NOTCARE_MC_INIT_START_MASK)

#define LPDDR_DENALI_PI_161_PI_TSDO_F0_MASK      (0xFF0000U)
#define LPDDR_DENALI_PI_161_PI_TSDO_F0_SHIFT     (16U)
/*! PI_TSDO_F0 - The delay from the read preamble training MRS command to the data strobe drive out for frequency set 0, in PI clocks. */
#define LPDDR_DENALI_PI_161_PI_TSDO_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_161_PI_TSDO_F0_SHIFT)) & LPDDR_DENALI_PI_161_PI_TSDO_F0_MASK)

#define LPDDR_DENALI_PI_161_PI_TSDO_F1_MASK      (0xFF000000U)
#define LPDDR_DENALI_PI_161_PI_TSDO_F1_SHIFT     (24U)
/*! PI_TSDO_F1 - The delay from the read preamble training MRS command to the data strobe drive out for frequency set 1, in PI clocks. */
#define LPDDR_DENALI_PI_161_PI_TSDO_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_161_PI_TSDO_F1_SHIFT)) & LPDDR_DENALI_PI_161_PI_TSDO_F1_MASK)
/*! @} */

/*! @name DENALI_PI_162 - DENALI_PI_162 */
/*! @{ */

#define LPDDR_DENALI_PI_162_PI_TSDO_F2_MASK      (0xFFU)
#define LPDDR_DENALI_PI_162_PI_TSDO_F2_SHIFT     (0U)
/*! PI_TSDO_F2 - The delay from the read preamble training MRS command to the data strobe drive out for frequency set 2, in PI clocks */
#define LPDDR_DENALI_PI_162_PI_TSDO_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_162_PI_TSDO_F2_SHIFT)) & LPDDR_DENALI_PI_162_PI_TSDO_F2_MASK)
/*! @} */

/*! @name DENALI_PI_163 - DENALI_PI_163 */
/*! @{ */

#define LPDDR_DENALI_PI_163_PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK (0xFFU)
#define LPDDR_DENALI_PI_163_PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT (0U)
#define LPDDR_DENALI_PI_163_PI_TDELAY_RDWR_2_BUS_IDLE_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_163_PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT)) & LPDDR_DENALI_PI_163_PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK)
/*! @} */

/*! @name DENALI_PI_164 - DENALI_PI_164 */
/*! @{ */

#define LPDDR_DENALI_PI_164_PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK (0xFFU)
#define LPDDR_DENALI_PI_164_PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_164_PI_TDELAY_RDWR_2_BUS_IDLE_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_164_PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT)) & LPDDR_DENALI_PI_164_PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK)
/*! @} */

/*! @name DENALI_PI_165 - DENALI_PI_165 */
/*! @{ */

#define LPDDR_DENALI_PI_165_PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK (0xFFU)
#define LPDDR_DENALI_PI_165_PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT (0U)
#define LPDDR_DENALI_PI_165_PI_TDELAY_RDWR_2_BUS_IDLE_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_165_PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT)) & LPDDR_DENALI_PI_165_PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK)

#define LPDDR_DENALI_PI_165_PI_ZQINIT_F0_MASK    (0xFFF00U)
#define LPDDR_DENALI_PI_165_PI_ZQINIT_F0_SHIFT   (8U)
#define LPDDR_DENALI_PI_165_PI_ZQINIT_F0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_165_PI_ZQINIT_F0_SHIFT)) & LPDDR_DENALI_PI_165_PI_ZQINIT_F0_MASK)
/*! @} */

/*! @name DENALI_PI_166 - DENALI_PI_166 */
/*! @{ */

#define LPDDR_DENALI_PI_166_PI_ZQINIT_F1_MASK    (0xFFFU)
#define LPDDR_DENALI_PI_166_PI_ZQINIT_F1_SHIFT   (0U)
#define LPDDR_DENALI_PI_166_PI_ZQINIT_F1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_166_PI_ZQINIT_F1_SHIFT)) & LPDDR_DENALI_PI_166_PI_ZQINIT_F1_MASK)

#define LPDDR_DENALI_PI_166_PI_ZQINIT_F2_MASK    (0xFFF0000U)
#define LPDDR_DENALI_PI_166_PI_ZQINIT_F2_SHIFT   (16U)
#define LPDDR_DENALI_PI_166_PI_ZQINIT_F2(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_166_PI_ZQINIT_F2_SHIFT)) & LPDDR_DENALI_PI_166_PI_ZQINIT_F2_MASK)
/*! @} */

/*! @name DENALI_PI_167 - DENALI_PI_167 */
/*! @{ */

#define LPDDR_DENALI_PI_167_PI_WRLAT_F0_MASK     (0x7FU)
#define LPDDR_DENALI_PI_167_PI_WRLAT_F0_SHIFT    (0U)
#define LPDDR_DENALI_PI_167_PI_WRLAT_F0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_167_PI_WRLAT_F0_SHIFT)) & LPDDR_DENALI_PI_167_PI_WRLAT_F0_MASK)

#define LPDDR_DENALI_PI_167_PI_CASLAT_LIN_F0_MASK (0x7F00U)
#define LPDDR_DENALI_PI_167_PI_CASLAT_LIN_F0_SHIFT (8U)
#define LPDDR_DENALI_PI_167_PI_CASLAT_LIN_F0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_167_PI_CASLAT_LIN_F0_SHIFT)) & LPDDR_DENALI_PI_167_PI_CASLAT_LIN_F0_MASK)

#define LPDDR_DENALI_PI_167_PI_WRLAT_F1_MASK     (0x7F0000U)
#define LPDDR_DENALI_PI_167_PI_WRLAT_F1_SHIFT    (16U)
#define LPDDR_DENALI_PI_167_PI_WRLAT_F1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_167_PI_WRLAT_F1_SHIFT)) & LPDDR_DENALI_PI_167_PI_WRLAT_F1_MASK)

#define LPDDR_DENALI_PI_167_PI_CASLAT_LIN_F1_MASK (0x7F000000U)
#define LPDDR_DENALI_PI_167_PI_CASLAT_LIN_F1_SHIFT (24U)
#define LPDDR_DENALI_PI_167_PI_CASLAT_LIN_F1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_167_PI_CASLAT_LIN_F1_SHIFT)) & LPDDR_DENALI_PI_167_PI_CASLAT_LIN_F1_MASK)
/*! @} */

/*! @name DENALI_PI_168 - DENALI_PI_168 */
/*! @{ */

#define LPDDR_DENALI_PI_168_PI_WRLAT_F2_MASK     (0x7FU)
#define LPDDR_DENALI_PI_168_PI_WRLAT_F2_SHIFT    (0U)
#define LPDDR_DENALI_PI_168_PI_WRLAT_F2(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_168_PI_WRLAT_F2_SHIFT)) & LPDDR_DENALI_PI_168_PI_WRLAT_F2_MASK)

#define LPDDR_DENALI_PI_168_PI_CASLAT_LIN_F2_MASK (0x7F00U)
#define LPDDR_DENALI_PI_168_PI_CASLAT_LIN_F2_SHIFT (8U)
#define LPDDR_DENALI_PI_168_PI_CASLAT_LIN_F2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_168_PI_CASLAT_LIN_F2_SHIFT)) & LPDDR_DENALI_PI_168_PI_CASLAT_LIN_F2_MASK)

#define LPDDR_DENALI_PI_168_PI_TRFC_F0_MASK      (0x3FF0000U)
#define LPDDR_DENALI_PI_168_PI_TRFC_F0_SHIFT     (16U)
#define LPDDR_DENALI_PI_168_PI_TRFC_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_168_PI_TRFC_F0_SHIFT)) & LPDDR_DENALI_PI_168_PI_TRFC_F0_MASK)
/*! @} */

/*! @name DENALI_PI_169 - DENALI_PI_169 */
/*! @{ */

#define LPDDR_DENALI_PI_169_PI_TREF_F0_MASK      (0xFFFFFU)
#define LPDDR_DENALI_PI_169_PI_TREF_F0_SHIFT     (0U)
#define LPDDR_DENALI_PI_169_PI_TREF_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_169_PI_TREF_F0_SHIFT)) & LPDDR_DENALI_PI_169_PI_TREF_F0_MASK)
/*! @} */

/*! @name DENALI_PI_170 - DENALI_PI_170 */
/*! @{ */

#define LPDDR_DENALI_PI_170_PI_TRFC_F1_MASK      (0x3FFU)
#define LPDDR_DENALI_PI_170_PI_TRFC_F1_SHIFT     (0U)
#define LPDDR_DENALI_PI_170_PI_TRFC_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_170_PI_TRFC_F1_SHIFT)) & LPDDR_DENALI_PI_170_PI_TRFC_F1_MASK)
/*! @} */

/*! @name DENALI_PI_171 - DENALI_PI_171 */
/*! @{ */

#define LPDDR_DENALI_PI_171_PI_TREF_F1_MASK      (0xFFFFFU)
#define LPDDR_DENALI_PI_171_PI_TREF_F1_SHIFT     (0U)
#define LPDDR_DENALI_PI_171_PI_TREF_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_171_PI_TREF_F1_SHIFT)) & LPDDR_DENALI_PI_171_PI_TREF_F1_MASK)
/*! @} */

/*! @name DENALI_PI_172 - DENALI_PI_172 */
/*! @{ */

#define LPDDR_DENALI_PI_172_PI_TRFC_F2_MASK      (0x3FFU)
#define LPDDR_DENALI_PI_172_PI_TRFC_F2_SHIFT     (0U)
#define LPDDR_DENALI_PI_172_PI_TRFC_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_172_PI_TRFC_F2_SHIFT)) & LPDDR_DENALI_PI_172_PI_TRFC_F2_MASK)
/*! @} */

/*! @name DENALI_PI_173 - DENALI_PI_173 */
/*! @{ */

#define LPDDR_DENALI_PI_173_PI_TREF_F2_MASK      (0xFFFFFU)
#define LPDDR_DENALI_PI_173_PI_TREF_F2_SHIFT     (0U)
#define LPDDR_DENALI_PI_173_PI_TREF_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_173_PI_TREF_F2_SHIFT)) & LPDDR_DENALI_PI_173_PI_TREF_F2_MASK)

#define LPDDR_DENALI_PI_173_PI_TDFI_CTRL_DELAY_F0_MASK (0xF000000U)
#define LPDDR_DENALI_PI_173_PI_TDFI_CTRL_DELAY_F0_SHIFT (24U)
#define LPDDR_DENALI_PI_173_PI_TDFI_CTRL_DELAY_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_173_PI_TDFI_CTRL_DELAY_F0_SHIFT)) & LPDDR_DENALI_PI_173_PI_TDFI_CTRL_DELAY_F0_MASK)
/*! @} */

/*! @name DENALI_PI_174 - DENALI_PI_174 */
/*! @{ */

#define LPDDR_DENALI_PI_174_PI_TDFI_CTRL_DELAY_F1_MASK (0xFU)
#define LPDDR_DENALI_PI_174_PI_TDFI_CTRL_DELAY_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_174_PI_TDFI_CTRL_DELAY_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_174_PI_TDFI_CTRL_DELAY_F1_SHIFT)) & LPDDR_DENALI_PI_174_PI_TDFI_CTRL_DELAY_F1_MASK)

#define LPDDR_DENALI_PI_174_PI_TDFI_CTRL_DELAY_F2_MASK (0xF00U)
#define LPDDR_DENALI_PI_174_PI_TDFI_CTRL_DELAY_F2_SHIFT (8U)
#define LPDDR_DENALI_PI_174_PI_TDFI_CTRL_DELAY_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_174_PI_TDFI_CTRL_DELAY_F2_SHIFT)) & LPDDR_DENALI_PI_174_PI_TDFI_CTRL_DELAY_F2_MASK)

#define LPDDR_DENALI_PI_174_PI_WRLVL_EN_F0_MASK  (0x30000U)
#define LPDDR_DENALI_PI_174_PI_WRLVL_EN_F0_SHIFT (16U)
#define LPDDR_DENALI_PI_174_PI_WRLVL_EN_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_174_PI_WRLVL_EN_F0_SHIFT)) & LPDDR_DENALI_PI_174_PI_WRLVL_EN_F0_MASK)

#define LPDDR_DENALI_PI_174_PI_WRLVL_EN_F1_MASK  (0x3000000U)
#define LPDDR_DENALI_PI_174_PI_WRLVL_EN_F1_SHIFT (24U)
#define LPDDR_DENALI_PI_174_PI_WRLVL_EN_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_174_PI_WRLVL_EN_F1_SHIFT)) & LPDDR_DENALI_PI_174_PI_WRLVL_EN_F1_MASK)
/*! @} */

/*! @name DENALI_PI_175 - DENALI_PI_175 */
/*! @{ */

#define LPDDR_DENALI_PI_175_PI_WRLVL_EN_F2_MASK  (0x3U)
#define LPDDR_DENALI_PI_175_PI_WRLVL_EN_F2_SHIFT (0U)
#define LPDDR_DENALI_PI_175_PI_WRLVL_EN_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_175_PI_WRLVL_EN_F2_SHIFT)) & LPDDR_DENALI_PI_175_PI_WRLVL_EN_F2_MASK)

#define LPDDR_DENALI_PI_175_PI_TDFI_WRLVL_WW_F0_MASK (0x3FF00U)
#define LPDDR_DENALI_PI_175_PI_TDFI_WRLVL_WW_F0_SHIFT (8U)
#define LPDDR_DENALI_PI_175_PI_TDFI_WRLVL_WW_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_175_PI_TDFI_WRLVL_WW_F0_SHIFT)) & LPDDR_DENALI_PI_175_PI_TDFI_WRLVL_WW_F0_MASK)
/*! @} */

/*! @name DENALI_PI_176 - DENALI_PI_176 */
/*! @{ */

#define LPDDR_DENALI_PI_176_PI_TDFI_WRLVL_WW_F1_MASK (0x3FFU)
#define LPDDR_DENALI_PI_176_PI_TDFI_WRLVL_WW_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_176_PI_TDFI_WRLVL_WW_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_176_PI_TDFI_WRLVL_WW_F1_SHIFT)) & LPDDR_DENALI_PI_176_PI_TDFI_WRLVL_WW_F1_MASK)

#define LPDDR_DENALI_PI_176_PI_TDFI_WRLVL_WW_F2_MASK (0x3FF0000U)
#define LPDDR_DENALI_PI_176_PI_TDFI_WRLVL_WW_F2_SHIFT (16U)
#define LPDDR_DENALI_PI_176_PI_TDFI_WRLVL_WW_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_176_PI_TDFI_WRLVL_WW_F2_SHIFT)) & LPDDR_DENALI_PI_176_PI_TDFI_WRLVL_WW_F2_MASK)
/*! @} */

/*! @name DENALI_PI_177 - DENALI_PI_177 */
/*! @{ */

#define LPDDR_DENALI_PI_177_PI_TODTL_2CMD_F0_MASK (0xFFU)
#define LPDDR_DENALI_PI_177_PI_TODTL_2CMD_F0_SHIFT (0U)
#define LPDDR_DENALI_PI_177_PI_TODTL_2CMD_F0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_177_PI_TODTL_2CMD_F0_SHIFT)) & LPDDR_DENALI_PI_177_PI_TODTL_2CMD_F0_MASK)

#define LPDDR_DENALI_PI_177_PI_ODT_EN_F0_MASK    (0x100U)
#define LPDDR_DENALI_PI_177_PI_ODT_EN_F0_SHIFT   (8U)
#define LPDDR_DENALI_PI_177_PI_ODT_EN_F0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_177_PI_ODT_EN_F0_SHIFT)) & LPDDR_DENALI_PI_177_PI_ODT_EN_F0_MASK)

#define LPDDR_DENALI_PI_177_PI_TODTL_2CMD_F1_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_177_PI_TODTL_2CMD_F1_SHIFT (16U)
#define LPDDR_DENALI_PI_177_PI_TODTL_2CMD_F1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_177_PI_TODTL_2CMD_F1_SHIFT)) & LPDDR_DENALI_PI_177_PI_TODTL_2CMD_F1_MASK)

#define LPDDR_DENALI_PI_177_PI_ODT_EN_F1_MASK    (0x1000000U)
#define LPDDR_DENALI_PI_177_PI_ODT_EN_F1_SHIFT   (24U)
#define LPDDR_DENALI_PI_177_PI_ODT_EN_F1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_177_PI_ODT_EN_F1_SHIFT)) & LPDDR_DENALI_PI_177_PI_ODT_EN_F1_MASK)
/*! @} */

/*! @name DENALI_PI_178 - DENALI_PI_178 */
/*! @{ */

#define LPDDR_DENALI_PI_178_PI_TODTL_2CMD_F2_MASK (0xFFU)
#define LPDDR_DENALI_PI_178_PI_TODTL_2CMD_F2_SHIFT (0U)
#define LPDDR_DENALI_PI_178_PI_TODTL_2CMD_F2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_178_PI_TODTL_2CMD_F2_SHIFT)) & LPDDR_DENALI_PI_178_PI_TODTL_2CMD_F2_MASK)

#define LPDDR_DENALI_PI_178_PI_ODT_EN_F2_MASK    (0x100U)
#define LPDDR_DENALI_PI_178_PI_ODT_EN_F2_SHIFT   (8U)
#define LPDDR_DENALI_PI_178_PI_ODT_EN_F2(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_178_PI_ODT_EN_F2_SHIFT)) & LPDDR_DENALI_PI_178_PI_ODT_EN_F2_MASK)

#define LPDDR_DENALI_PI_178_PI_ODTLON_F0_MASK    (0xF0000U)
#define LPDDR_DENALI_PI_178_PI_ODTLON_F0_SHIFT   (16U)
/*! PI_ODTLON_F0 - Defines the latency from a CAS-2 command to the tODTon reference for frequency set 0. */
#define LPDDR_DENALI_PI_178_PI_ODTLON_F0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_178_PI_ODTLON_F0_SHIFT)) & LPDDR_DENALI_PI_178_PI_ODTLON_F0_MASK)

#define LPDDR_DENALI_PI_178_PI_TODTON_MIN_F0_MASK (0xF000000U)
#define LPDDR_DENALI_PI_178_PI_TODTON_MIN_F0_SHIFT (24U)
/*! PI_TODTON_MIN_F0 - Defines the point in time when the device termination circuit leaves High-Z
 *    and ODT resistance begins to turn on for frequency set 0.
 */
#define LPDDR_DENALI_PI_178_PI_TODTON_MIN_F0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_178_PI_TODTON_MIN_F0_SHIFT)) & LPDDR_DENALI_PI_178_PI_TODTON_MIN_F0_MASK)
/*! @} */

/*! @name DENALI_PI_181 - DENALI_PI_181 */
/*! @{ */

#define LPDDR_DENALI_PI_181_PI_RD_TO_ODTH_F1_MASK (0x3FU)
#define LPDDR_DENALI_PI_181_PI_RD_TO_ODTH_F1_SHIFT (0U)
/*! PI_RD_TO_ODTH_F1 - Defines the delay from a read command to ODT assertion for frequency set 1. */
#define LPDDR_DENALI_PI_181_PI_RD_TO_ODTH_F1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_181_PI_RD_TO_ODTH_F1_SHIFT)) & LPDDR_DENALI_PI_181_PI_RD_TO_ODTH_F1_MASK)

#define LPDDR_DENALI_PI_181_PI_RD_TO_ODTH_F2_MASK (0x3F00U)
#define LPDDR_DENALI_PI_181_PI_RD_TO_ODTH_F2_SHIFT (8U)
/*! PI_RD_TO_ODTH_F2 - Defines the delay from a read command to ODT assertion for frequency set 2. */
#define LPDDR_DENALI_PI_181_PI_RD_TO_ODTH_F2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_181_PI_RD_TO_ODTH_F2_SHIFT)) & LPDDR_DENALI_PI_181_PI_RD_TO_ODTH_F2_MASK)

#define LPDDR_DENALI_PI_181_PI_RDLVL_EN_F0_MASK  (0x30000U)
#define LPDDR_DENALI_PI_181_PI_RDLVL_EN_F0_SHIFT (16U)
#define LPDDR_DENALI_PI_181_PI_RDLVL_EN_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_181_PI_RDLVL_EN_F0_SHIFT)) & LPDDR_DENALI_PI_181_PI_RDLVL_EN_F0_MASK)

#define LPDDR_DENALI_PI_181_PI_RDLVL_GATE_EN_F0_MASK (0x3000000U)
#define LPDDR_DENALI_PI_181_PI_RDLVL_GATE_EN_F0_SHIFT (24U)
#define LPDDR_DENALI_PI_181_PI_RDLVL_GATE_EN_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_181_PI_RDLVL_GATE_EN_F0_SHIFT)) & LPDDR_DENALI_PI_181_PI_RDLVL_GATE_EN_F0_MASK)
/*! @} */

/*! @name DENALI_PI_182 - DENALI_PI_182 */
/*! @{ */

#define LPDDR_DENALI_PI_182_PI_RDLVL_EN_F1_MASK  (0x3U)
#define LPDDR_DENALI_PI_182_PI_RDLVL_EN_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_182_PI_RDLVL_EN_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_182_PI_RDLVL_EN_F1_SHIFT)) & LPDDR_DENALI_PI_182_PI_RDLVL_EN_F1_MASK)

#define LPDDR_DENALI_PI_182_PI_RDLVL_GATE_EN_F1_MASK (0x300U)
#define LPDDR_DENALI_PI_182_PI_RDLVL_GATE_EN_F1_SHIFT (8U)
#define LPDDR_DENALI_PI_182_PI_RDLVL_GATE_EN_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_182_PI_RDLVL_GATE_EN_F1_SHIFT)) & LPDDR_DENALI_PI_182_PI_RDLVL_GATE_EN_F1_MASK)

#define LPDDR_DENALI_PI_182_PI_RDLVL_EN_F2_MASK  (0x30000U)
#define LPDDR_DENALI_PI_182_PI_RDLVL_EN_F2_SHIFT (16U)
#define LPDDR_DENALI_PI_182_PI_RDLVL_EN_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_182_PI_RDLVL_EN_F2_SHIFT)) & LPDDR_DENALI_PI_182_PI_RDLVL_EN_F2_MASK)

#define LPDDR_DENALI_PI_182_PI_RDLVL_GATE_EN_F2_MASK (0x3000000U)
#define LPDDR_DENALI_PI_182_PI_RDLVL_GATE_EN_F2_SHIFT (24U)
#define LPDDR_DENALI_PI_182_PI_RDLVL_GATE_EN_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_182_PI_RDLVL_GATE_EN_F2_SHIFT)) & LPDDR_DENALI_PI_182_PI_RDLVL_GATE_EN_F2_MASK)
/*! @} */

/*! @name DENALI_PI_186 - DENALI_PI_186 */
/*! @{ */

#define LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F0_MASK (0x7FU)
#define LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F0_SHIFT (0U)
#define LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F0(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F0_SHIFT)) & LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F0_MASK)

#define LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F1_MASK (0x7F00U)
#define LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F1_SHIFT (8U)
#define LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F1(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F1_SHIFT)) & LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F1_MASK)

#define LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F2_MASK (0x7F0000U)
#define LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F2_SHIFT (16U)
#define LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F2(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F2_SHIFT)) & LPDDR_DENALI_PI_186_PI_RDLAT_ADJ_F2_MASK)

#define LPDDR_DENALI_PI_186_PI_WRLAT_ADJ_F0_MASK (0x7F000000U)
#define LPDDR_DENALI_PI_186_PI_WRLAT_ADJ_F0_SHIFT (24U)
#define LPDDR_DENALI_PI_186_PI_WRLAT_ADJ_F0(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_186_PI_WRLAT_ADJ_F0_SHIFT)) & LPDDR_DENALI_PI_186_PI_WRLAT_ADJ_F0_MASK)
/*! @} */

/*! @name DENALI_PI_187 - DENALI_PI_187 */
/*! @{ */

#define LPDDR_DENALI_PI_187_PI_WRLAT_ADJ_F1_MASK (0x7FU)
#define LPDDR_DENALI_PI_187_PI_WRLAT_ADJ_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_187_PI_WRLAT_ADJ_F1(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_187_PI_WRLAT_ADJ_F1_SHIFT)) & LPDDR_DENALI_PI_187_PI_WRLAT_ADJ_F1_MASK)

#define LPDDR_DENALI_PI_187_PI_WRLAT_ADJ_F2_MASK (0x7F00U)
#define LPDDR_DENALI_PI_187_PI_WRLAT_ADJ_F2_SHIFT (8U)
#define LPDDR_DENALI_PI_187_PI_WRLAT_ADJ_F2(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_187_PI_WRLAT_ADJ_F2_SHIFT)) & LPDDR_DENALI_PI_187_PI_WRLAT_ADJ_F2_MASK)

#define LPDDR_DENALI_PI_187_PI_TDFI_PHY_WRDATA_F0_MASK (0x70000U)
#define LPDDR_DENALI_PI_187_PI_TDFI_PHY_WRDATA_F0_SHIFT (16U)
/*! PI_TDFI_PHY_WRDATA_F0 - Defines the DFI tPHY_WRDATA timing (in DFI PHY clocks) for frequency set
 *    0, the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal.
 */
#define LPDDR_DENALI_PI_187_PI_TDFI_PHY_WRDATA_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_187_PI_TDFI_PHY_WRDATA_F0_SHIFT)) & LPDDR_DENALI_PI_187_PI_TDFI_PHY_WRDATA_F0_MASK)

#define LPDDR_DENALI_PI_187_PI_TDFI_PHY_WRDATA_F1_MASK (0x7000000U)
#define LPDDR_DENALI_PI_187_PI_TDFI_PHY_WRDATA_F1_SHIFT (24U)
/*! PI_TDFI_PHY_WRDATA_F1 - Defines the DFI tPHY_WRDATA timing (in DFI PHY clocks) for frequency set
 *    1, the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal.
 */
#define LPDDR_DENALI_PI_187_PI_TDFI_PHY_WRDATA_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_187_PI_TDFI_PHY_WRDATA_F1_SHIFT)) & LPDDR_DENALI_PI_187_PI_TDFI_PHY_WRDATA_F1_MASK)
/*! @} */

/*! @name DENALI_PI_188 - DENALI_PI_188 */
/*! @{ */

#define LPDDR_DENALI_PI_188_PI_TDFI_PHY_WRDATA_F2_MASK (0x7U)
#define LPDDR_DENALI_PI_188_PI_TDFI_PHY_WRDATA_F2_SHIFT (0U)
/*! PI_TDFI_PHY_WRDATA_F2 - Defines the DFI tPHY_WRDATA timing (in DFI PHY clocks) for frequency set
 *    2, the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal.
 */
#define LPDDR_DENALI_PI_188_PI_TDFI_PHY_WRDATA_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_188_PI_TDFI_PHY_WRDATA_F2_SHIFT)) & LPDDR_DENALI_PI_188_PI_TDFI_PHY_WRDATA_F2_MASK)

#define LPDDR_DENALI_PI_188_PI_TDFI_CALVL_CC_F0_MASK (0x3FF00U)
#define LPDDR_DENALI_PI_188_PI_TDFI_CALVL_CC_F0_SHIFT (8U)
#define LPDDR_DENALI_PI_188_PI_TDFI_CALVL_CC_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_188_PI_TDFI_CALVL_CC_F0_SHIFT)) & LPDDR_DENALI_PI_188_PI_TDFI_CALVL_CC_F0_MASK)
/*! @} */

/*! @name DENALI_PI_189 - DENALI_PI_189 */
/*! @{ */

#define LPDDR_DENALI_PI_189_PI_TDFI_CALVL_CAPTURE_F0_MASK (0x3FFU)
#define LPDDR_DENALI_PI_189_PI_TDFI_CALVL_CAPTURE_F0_SHIFT (0U)
#define LPDDR_DENALI_PI_189_PI_TDFI_CALVL_CAPTURE_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_189_PI_TDFI_CALVL_CAPTURE_F0_SHIFT)) & LPDDR_DENALI_PI_189_PI_TDFI_CALVL_CAPTURE_F0_MASK)

#define LPDDR_DENALI_PI_189_PI_TDFI_CALVL_CC_F1_MASK (0x3FF0000U)
#define LPDDR_DENALI_PI_189_PI_TDFI_CALVL_CC_F1_SHIFT (16U)
#define LPDDR_DENALI_PI_189_PI_TDFI_CALVL_CC_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_189_PI_TDFI_CALVL_CC_F1_SHIFT)) & LPDDR_DENALI_PI_189_PI_TDFI_CALVL_CC_F1_MASK)
/*! @} */

/*! @name DENALI_PI_190 - DENALI_PI_190 */
/*! @{ */

#define LPDDR_DENALI_PI_190_PI_TDFI_CALVL_CAPTURE_F1_MASK (0x3FFU)
#define LPDDR_DENALI_PI_190_PI_TDFI_CALVL_CAPTURE_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_190_PI_TDFI_CALVL_CAPTURE_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_190_PI_TDFI_CALVL_CAPTURE_F1_SHIFT)) & LPDDR_DENALI_PI_190_PI_TDFI_CALVL_CAPTURE_F1_MASK)

#define LPDDR_DENALI_PI_190_PI_TDFI_CALVL_CC_F2_MASK (0x3FF0000U)
#define LPDDR_DENALI_PI_190_PI_TDFI_CALVL_CC_F2_SHIFT (16U)
#define LPDDR_DENALI_PI_190_PI_TDFI_CALVL_CC_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_190_PI_TDFI_CALVL_CC_F2_SHIFT)) & LPDDR_DENALI_PI_190_PI_TDFI_CALVL_CC_F2_MASK)
/*! @} */

/*! @name DENALI_PI_191 - DENALI_PI_191 */
/*! @{ */

#define LPDDR_DENALI_PI_191_PI_TDFI_CALVL_CAPTURE_F2_MASK (0x3FFU)
#define LPDDR_DENALI_PI_191_PI_TDFI_CALVL_CAPTURE_F2_SHIFT (0U)
#define LPDDR_DENALI_PI_191_PI_TDFI_CALVL_CAPTURE_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_191_PI_TDFI_CALVL_CAPTURE_F2_SHIFT)) & LPDDR_DENALI_PI_191_PI_TDFI_CALVL_CAPTURE_F2_MASK)

#define LPDDR_DENALI_PI_191_PI_CALVL_EN_F0_MASK  (0x30000U)
#define LPDDR_DENALI_PI_191_PI_CALVL_EN_F0_SHIFT (16U)
/*! PI_CALVL_EN_F0
 *  0b00..Disable
 *  0b01..Enable
 */
#define LPDDR_DENALI_PI_191_PI_CALVL_EN_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_191_PI_CALVL_EN_F0_SHIFT)) & LPDDR_DENALI_PI_191_PI_CALVL_EN_F0_MASK)

#define LPDDR_DENALI_PI_191_PI_CALVL_EN_F1_MASK  (0x3000000U)
#define LPDDR_DENALI_PI_191_PI_CALVL_EN_F1_SHIFT (24U)
/*! PI_CALVL_EN_F1
 *  0b00..Disable
 *  0b01..Enable
 */
#define LPDDR_DENALI_PI_191_PI_CALVL_EN_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_191_PI_CALVL_EN_F1_SHIFT)) & LPDDR_DENALI_PI_191_PI_CALVL_EN_F1_MASK)
/*! @} */

/*! @name DENALI_PI_192 - DENALI_PI_192 */
/*! @{ */

#define LPDDR_DENALI_PI_192_PI_CALVL_EN_F2_MASK  (0x3U)
#define LPDDR_DENALI_PI_192_PI_CALVL_EN_F2_SHIFT (0U)
/*! PI_CALVL_EN_F2
 *  0b00..Disable
 *  0b01..Enable
 */
#define LPDDR_DENALI_PI_192_PI_CALVL_EN_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_192_PI_CALVL_EN_F2_SHIFT)) & LPDDR_DENALI_PI_192_PI_CALVL_EN_F2_MASK)

#define LPDDR_DENALI_PI_192_PI_TMRZ_F0_MASK      (0x1F00U)
#define LPDDR_DENALI_PI_192_PI_TMRZ_F0_SHIFT     (8U)
#define LPDDR_DENALI_PI_192_PI_TMRZ_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_192_PI_TMRZ_F0_SHIFT)) & LPDDR_DENALI_PI_192_PI_TMRZ_F0_MASK)

#define LPDDR_DENALI_PI_192_PI_TCAENT_F0_MASK    (0x3FFF0000U)
#define LPDDR_DENALI_PI_192_PI_TCAENT_F0_SHIFT   (16U)
#define LPDDR_DENALI_PI_192_PI_TCAENT_F0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_192_PI_TCAENT_F0_SHIFT)) & LPDDR_DENALI_PI_192_PI_TCAENT_F0_MASK)
/*! @} */

/*! @name DENALI_PI_193 - DENALI_PI_193 */
/*! @{ */

#define LPDDR_DENALI_PI_193_PI_TMRZ_F1_MASK      (0x1FU)
#define LPDDR_DENALI_PI_193_PI_TMRZ_F1_SHIFT     (0U)
#define LPDDR_DENALI_PI_193_PI_TMRZ_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_193_PI_TMRZ_F1_SHIFT)) & LPDDR_DENALI_PI_193_PI_TMRZ_F1_MASK)

#define LPDDR_DENALI_PI_193_PI_TCAENT_F1_MASK    (0x3FFF00U)
#define LPDDR_DENALI_PI_193_PI_TCAENT_F1_SHIFT   (8U)
#define LPDDR_DENALI_PI_193_PI_TCAENT_F1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_193_PI_TCAENT_F1_SHIFT)) & LPDDR_DENALI_PI_193_PI_TCAENT_F1_MASK)

#define LPDDR_DENALI_PI_193_PI_TMRZ_F2_MASK      (0x1F000000U)
#define LPDDR_DENALI_PI_193_PI_TMRZ_F2_SHIFT     (24U)
#define LPDDR_DENALI_PI_193_PI_TMRZ_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_193_PI_TMRZ_F2_SHIFT)) & LPDDR_DENALI_PI_193_PI_TMRZ_F2_MASK)
/*! @} */

/*! @name DENALI_PI_194 - DENALI_PI_194 */
/*! @{ */

#define LPDDR_DENALI_PI_194_PI_TCAENT_F2_MASK    (0x3FFFU)
#define LPDDR_DENALI_PI_194_PI_TCAENT_F2_SHIFT   (0U)
#define LPDDR_DENALI_PI_194_PI_TCAENT_F2(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_194_PI_TCAENT_F2_SHIFT)) & LPDDR_DENALI_PI_194_PI_TCAENT_F2_MASK)

#define LPDDR_DENALI_PI_194_PI_TDFI_CACSCA_F0_MASK (0x1F0000U)
#define LPDDR_DENALI_PI_194_PI_TDFI_CACSCA_F0_SHIFT (16U)
#define LPDDR_DENALI_PI_194_PI_TDFI_CACSCA_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_194_PI_TDFI_CACSCA_F0_SHIFT)) & LPDDR_DENALI_PI_194_PI_TDFI_CACSCA_F0_MASK)

#define LPDDR_DENALI_PI_194_PI_TDFI_CASEL_F0_MASK (0x1F000000U)
#define LPDDR_DENALI_PI_194_PI_TDFI_CASEL_F0_SHIFT (24U)
#define LPDDR_DENALI_PI_194_PI_TDFI_CASEL_F0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_194_PI_TDFI_CASEL_F0_SHIFT)) & LPDDR_DENALI_PI_194_PI_TDFI_CASEL_F0_MASK)
/*! @} */

/*! @name DENALI_PI_195 - DENALI_PI_195 */
/*! @{ */

#define LPDDR_DENALI_PI_195_PI_TVREF_SHORT_F0_MASK (0x3FFU)
#define LPDDR_DENALI_PI_195_PI_TVREF_SHORT_F0_SHIFT (0U)
#define LPDDR_DENALI_PI_195_PI_TVREF_SHORT_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_195_PI_TVREF_SHORT_F0_SHIFT)) & LPDDR_DENALI_PI_195_PI_TVREF_SHORT_F0_MASK)

#define LPDDR_DENALI_PI_195_PI_TVREF_LONG_F0_MASK (0x3FF0000U)
#define LPDDR_DENALI_PI_195_PI_TVREF_LONG_F0_SHIFT (16U)
#define LPDDR_DENALI_PI_195_PI_TVREF_LONG_F0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_195_PI_TVREF_LONG_F0_SHIFT)) & LPDDR_DENALI_PI_195_PI_TVREF_LONG_F0_MASK)
/*! @} */

/*! @name DENALI_PI_196 - DENALI_PI_196 */
/*! @{ */

#define LPDDR_DENALI_PI_196_PI_TDFI_CACSCA_F1_MASK (0x1FU)
#define LPDDR_DENALI_PI_196_PI_TDFI_CACSCA_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_196_PI_TDFI_CACSCA_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_196_PI_TDFI_CACSCA_F1_SHIFT)) & LPDDR_DENALI_PI_196_PI_TDFI_CACSCA_F1_MASK)

#define LPDDR_DENALI_PI_196_PI_TDFI_CASEL_F1_MASK (0x1F00U)
#define LPDDR_DENALI_PI_196_PI_TDFI_CASEL_F1_SHIFT (8U)
#define LPDDR_DENALI_PI_196_PI_TDFI_CASEL_F1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_196_PI_TDFI_CASEL_F1_SHIFT)) & LPDDR_DENALI_PI_196_PI_TDFI_CASEL_F1_MASK)

#define LPDDR_DENALI_PI_196_PI_TVREF_SHORT_F1_MASK (0x3FF0000U)
#define LPDDR_DENALI_PI_196_PI_TVREF_SHORT_F1_SHIFT (16U)
#define LPDDR_DENALI_PI_196_PI_TVREF_SHORT_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_196_PI_TVREF_SHORT_F1_SHIFT)) & LPDDR_DENALI_PI_196_PI_TVREF_SHORT_F1_MASK)
/*! @} */

/*! @name DENALI_PI_197 - DENALI_PI_197 */
/*! @{ */

#define LPDDR_DENALI_PI_197_PI_TVREF_LONG_F1_MASK (0x3FFU)
#define LPDDR_DENALI_PI_197_PI_TVREF_LONG_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_197_PI_TVREF_LONG_F1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_197_PI_TVREF_LONG_F1_SHIFT)) & LPDDR_DENALI_PI_197_PI_TVREF_LONG_F1_MASK)

#define LPDDR_DENALI_PI_197_PI_TDFI_CACSCA_F2_MASK (0x1F0000U)
#define LPDDR_DENALI_PI_197_PI_TDFI_CACSCA_F2_SHIFT (16U)
#define LPDDR_DENALI_PI_197_PI_TDFI_CACSCA_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_197_PI_TDFI_CACSCA_F2_SHIFT)) & LPDDR_DENALI_PI_197_PI_TDFI_CACSCA_F2_MASK)

#define LPDDR_DENALI_PI_197_PI_TDFI_CASEL_F2_MASK (0x1F000000U)
#define LPDDR_DENALI_PI_197_PI_TDFI_CASEL_F2_SHIFT (24U)
#define LPDDR_DENALI_PI_197_PI_TDFI_CASEL_F2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_197_PI_TDFI_CASEL_F2_SHIFT)) & LPDDR_DENALI_PI_197_PI_TDFI_CASEL_F2_MASK)
/*! @} */

/*! @name DENALI_PI_198 - DENALI_PI_198 */
/*! @{ */

#define LPDDR_DENALI_PI_198_PI_TVREF_SHORT_F2_MASK (0x3FFU)
#define LPDDR_DENALI_PI_198_PI_TVREF_SHORT_F2_SHIFT (0U)
#define LPDDR_DENALI_PI_198_PI_TVREF_SHORT_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_198_PI_TVREF_SHORT_F2_SHIFT)) & LPDDR_DENALI_PI_198_PI_TVREF_SHORT_F2_MASK)

#define LPDDR_DENALI_PI_198_PI_TVREF_LONG_F2_MASK (0x3FF0000U)
#define LPDDR_DENALI_PI_198_PI_TVREF_LONG_F2_SHIFT (16U)
#define LPDDR_DENALI_PI_198_PI_TVREF_LONG_F2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_198_PI_TVREF_LONG_F2_SHIFT)) & LPDDR_DENALI_PI_198_PI_TVREF_LONG_F2_MASK)
/*! @} */

/*! @name DENALI_PI_199 - DENALI_PI_199 */
/*! @{ */

#define LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK (0x7FU)
#define LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT (0U)
#define LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_START_POINT_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT)) & LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK)

#define LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK (0x7F00U)
#define LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT (8U)
#define LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_STOP_POINT_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT)) & LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK)

#define LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK (0x7F0000U)
#define LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT (16U)
#define LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_START_POINT_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT)) & LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK)

#define LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK (0x7F000000U)
#define LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT (24U)
#define LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_STOP_POINT_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT)) & LPDDR_DENALI_PI_199_PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK)
/*! @} */

/*! @name DENALI_PI_200 - DENALI_PI_200 */
/*! @{ */

#define LPDDR_DENALI_PI_200_PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK (0x7FU)
#define LPDDR_DENALI_PI_200_PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT (0U)
#define LPDDR_DENALI_PI_200_PI_CALVL_VREF_INITIAL_START_POINT_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_200_PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT)) & LPDDR_DENALI_PI_200_PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK)

#define LPDDR_DENALI_PI_200_PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK (0x7F00U)
#define LPDDR_DENALI_PI_200_PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT (8U)
#define LPDDR_DENALI_PI_200_PI_CALVL_VREF_INITIAL_STOP_POINT_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_200_PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT)) & LPDDR_DENALI_PI_200_PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK)

#define LPDDR_DENALI_PI_200_PI_CALVL_VREF_DELTA_F0_MASK (0xF0000U)
#define LPDDR_DENALI_PI_200_PI_CALVL_VREF_DELTA_F0_SHIFT (16U)
#define LPDDR_DENALI_PI_200_PI_CALVL_VREF_DELTA_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_200_PI_CALVL_VREF_DELTA_F0_SHIFT)) & LPDDR_DENALI_PI_200_PI_CALVL_VREF_DELTA_F0_MASK)

#define LPDDR_DENALI_PI_200_PI_CALVL_VREF_DELTA_F1_MASK (0xF000000U)
#define LPDDR_DENALI_PI_200_PI_CALVL_VREF_DELTA_F1_SHIFT (24U)
#define LPDDR_DENALI_PI_200_PI_CALVL_VREF_DELTA_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_200_PI_CALVL_VREF_DELTA_F1_SHIFT)) & LPDDR_DENALI_PI_200_PI_CALVL_VREF_DELTA_F1_MASK)
/*! @} */

/*! @name DENALI_PI_201 - DENALI_PI_201 */
/*! @{ */

#define LPDDR_DENALI_PI_201_PI_CALVL_VREF_DELTA_F2_MASK (0xFU)
#define LPDDR_DENALI_PI_201_PI_CALVL_VREF_DELTA_F2_SHIFT (0U)
#define LPDDR_DENALI_PI_201_PI_CALVL_VREF_DELTA_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_201_PI_CALVL_VREF_DELTA_F2_SHIFT)) & LPDDR_DENALI_PI_201_PI_CALVL_VREF_DELTA_F2_MASK)

#define LPDDR_DENALI_PI_201_PI_TDFI_CALVL_STROBE_F0_MASK (0xF00U)
#define LPDDR_DENALI_PI_201_PI_TDFI_CALVL_STROBE_F0_SHIFT (8U)
#define LPDDR_DENALI_PI_201_PI_TDFI_CALVL_STROBE_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_201_PI_TDFI_CALVL_STROBE_F0_SHIFT)) & LPDDR_DENALI_PI_201_PI_TDFI_CALVL_STROBE_F0_MASK)

#define LPDDR_DENALI_PI_201_PI_TXP_F0_MASK       (0x1F0000U)
#define LPDDR_DENALI_PI_201_PI_TXP_F0_SHIFT      (16U)
#define LPDDR_DENALI_PI_201_PI_TXP_F0(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_201_PI_TXP_F0_SHIFT)) & LPDDR_DENALI_PI_201_PI_TXP_F0_MASK)

#define LPDDR_DENALI_PI_201_PI_TMRWCKEL_F0_MASK  (0xFF000000U)
#define LPDDR_DENALI_PI_201_PI_TMRWCKEL_F0_SHIFT (24U)
#define LPDDR_DENALI_PI_201_PI_TMRWCKEL_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_201_PI_TMRWCKEL_F0_SHIFT)) & LPDDR_DENALI_PI_201_PI_TMRWCKEL_F0_MASK)
/*! @} */

/*! @name DENALI_PI_202 - DENALI_PI_202 */
/*! @{ */

#define LPDDR_DENALI_PI_202_PI_TCKELCK_F0_MASK   (0x1FU)
#define LPDDR_DENALI_PI_202_PI_TCKELCK_F0_SHIFT  (0U)
#define LPDDR_DENALI_PI_202_PI_TCKELCK_F0(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_202_PI_TCKELCK_F0_SHIFT)) & LPDDR_DENALI_PI_202_PI_TCKELCK_F0_MASK)

#define LPDDR_DENALI_PI_202_PI_TDFI_CALVL_STROBE_F1_MASK (0xF00U)
#define LPDDR_DENALI_PI_202_PI_TDFI_CALVL_STROBE_F1_SHIFT (8U)
#define LPDDR_DENALI_PI_202_PI_TDFI_CALVL_STROBE_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_202_PI_TDFI_CALVL_STROBE_F1_SHIFT)) & LPDDR_DENALI_PI_202_PI_TDFI_CALVL_STROBE_F1_MASK)

#define LPDDR_DENALI_PI_202_PI_TXP_F1_MASK       (0x1F0000U)
#define LPDDR_DENALI_PI_202_PI_TXP_F1_SHIFT      (16U)
#define LPDDR_DENALI_PI_202_PI_TXP_F1(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_202_PI_TXP_F1_SHIFT)) & LPDDR_DENALI_PI_202_PI_TXP_F1_MASK)

#define LPDDR_DENALI_PI_202_PI_TMRWCKEL_F1_MASK  (0xFF000000U)
#define LPDDR_DENALI_PI_202_PI_TMRWCKEL_F1_SHIFT (24U)
#define LPDDR_DENALI_PI_202_PI_TMRWCKEL_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_202_PI_TMRWCKEL_F1_SHIFT)) & LPDDR_DENALI_PI_202_PI_TMRWCKEL_F1_MASK)
/*! @} */

/*! @name DENALI_PI_203 - DENALI_PI_203 */
/*! @{ */

#define LPDDR_DENALI_PI_203_PI_TCKELCK_F1_MASK   (0x1FU)
#define LPDDR_DENALI_PI_203_PI_TCKELCK_F1_SHIFT  (0U)
#define LPDDR_DENALI_PI_203_PI_TCKELCK_F1(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_203_PI_TCKELCK_F1_SHIFT)) & LPDDR_DENALI_PI_203_PI_TCKELCK_F1_MASK)

#define LPDDR_DENALI_PI_203_PI_TDFI_CALVL_STROBE_F2_MASK (0xF00U)
#define LPDDR_DENALI_PI_203_PI_TDFI_CALVL_STROBE_F2_SHIFT (8U)
#define LPDDR_DENALI_PI_203_PI_TDFI_CALVL_STROBE_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_203_PI_TDFI_CALVL_STROBE_F2_SHIFT)) & LPDDR_DENALI_PI_203_PI_TDFI_CALVL_STROBE_F2_MASK)

#define LPDDR_DENALI_PI_203_PI_TXP_F2_MASK       (0x1F0000U)
#define LPDDR_DENALI_PI_203_PI_TXP_F2_SHIFT      (16U)
#define LPDDR_DENALI_PI_203_PI_TXP_F2(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_203_PI_TXP_F2_SHIFT)) & LPDDR_DENALI_PI_203_PI_TXP_F2_MASK)

#define LPDDR_DENALI_PI_203_PI_TMRWCKEL_F2_MASK  (0xFF000000U)
#define LPDDR_DENALI_PI_203_PI_TMRWCKEL_F2_SHIFT (24U)
#define LPDDR_DENALI_PI_203_PI_TMRWCKEL_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_203_PI_TMRWCKEL_F2_SHIFT)) & LPDDR_DENALI_PI_203_PI_TMRWCKEL_F2_MASK)
/*! @} */

/*! @name DENALI_PI_204 - DENALI_PI_204 */
/*! @{ */

#define LPDDR_DENALI_PI_204_PI_TCKELCK_F2_MASK   (0x1FU)
#define LPDDR_DENALI_PI_204_PI_TCKELCK_F2_SHIFT  (0U)
#define LPDDR_DENALI_PI_204_PI_TCKELCK_F2(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_204_PI_TCKELCK_F2_SHIFT)) & LPDDR_DENALI_PI_204_PI_TCKELCK_F2_MASK)

#define LPDDR_DENALI_PI_204_PI_TDFI_INIT_START_F0_MASK (0x3FF00U)
#define LPDDR_DENALI_PI_204_PI_TDFI_INIT_START_F0_SHIFT (8U)
#define LPDDR_DENALI_PI_204_PI_TDFI_INIT_START_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_204_PI_TDFI_INIT_START_F0_SHIFT)) & LPDDR_DENALI_PI_204_PI_TDFI_INIT_START_F0_MASK)
/*! @} */

/*! @name DENALI_PI_205 - DENALI_PI_205 */
/*! @{ */

#define LPDDR_DENALI_PI_205_PI_TDFI_INIT_COMPLETE_F0_MASK (0xFFFFU)
#define LPDDR_DENALI_PI_205_PI_TDFI_INIT_COMPLETE_F0_SHIFT (0U)
#define LPDDR_DENALI_PI_205_PI_TDFI_INIT_COMPLETE_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_205_PI_TDFI_INIT_COMPLETE_F0_SHIFT)) & LPDDR_DENALI_PI_205_PI_TDFI_INIT_COMPLETE_F0_MASK)

#define LPDDR_DENALI_PI_205_PI_TDFI_INIT_START_F1_MASK (0x3FF0000U)
#define LPDDR_DENALI_PI_205_PI_TDFI_INIT_START_F1_SHIFT (16U)
#define LPDDR_DENALI_PI_205_PI_TDFI_INIT_START_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_205_PI_TDFI_INIT_START_F1_SHIFT)) & LPDDR_DENALI_PI_205_PI_TDFI_INIT_START_F1_MASK)
/*! @} */

/*! @name DENALI_PI_206 - DENALI_PI_206 */
/*! @{ */

#define LPDDR_DENALI_PI_206_PI_TDFI_INIT_COMPLETE_F1_MASK (0xFFFFU)
#define LPDDR_DENALI_PI_206_PI_TDFI_INIT_COMPLETE_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_206_PI_TDFI_INIT_COMPLETE_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_206_PI_TDFI_INIT_COMPLETE_F1_SHIFT)) & LPDDR_DENALI_PI_206_PI_TDFI_INIT_COMPLETE_F1_MASK)

#define LPDDR_DENALI_PI_206_PI_TDFI_INIT_START_F2_MASK (0x3FF0000U)
#define LPDDR_DENALI_PI_206_PI_TDFI_INIT_START_F2_SHIFT (16U)
#define LPDDR_DENALI_PI_206_PI_TDFI_INIT_START_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_206_PI_TDFI_INIT_START_F2_SHIFT)) & LPDDR_DENALI_PI_206_PI_TDFI_INIT_START_F2_MASK)
/*! @} */

/*! @name DENALI_PI_207 - DENALI_PI_207 */
/*! @{ */

#define LPDDR_DENALI_PI_207_PI_TDFI_INIT_COMPLETE_F2_MASK (0xFFFFU)
#define LPDDR_DENALI_PI_207_PI_TDFI_INIT_COMPLETE_F2_SHIFT (0U)
#define LPDDR_DENALI_PI_207_PI_TDFI_INIT_COMPLETE_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_207_PI_TDFI_INIT_COMPLETE_F2_SHIFT)) & LPDDR_DENALI_PI_207_PI_TDFI_INIT_COMPLETE_F2_MASK)

#define LPDDR_DENALI_PI_207_PI_TCKEHDQS_F0_MASK  (0x3F0000U)
#define LPDDR_DENALI_PI_207_PI_TCKEHDQS_F0_SHIFT (16U)
#define LPDDR_DENALI_PI_207_PI_TCKEHDQS_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_207_PI_TCKEHDQS_F0_SHIFT)) & LPDDR_DENALI_PI_207_PI_TCKEHDQS_F0_MASK)
/*! @} */

/*! @name DENALI_PI_208 - DENALI_PI_208 */
/*! @{ */

#define LPDDR_DENALI_PI_208_PI_TFC_F0_MASK       (0x3FFU)
#define LPDDR_DENALI_PI_208_PI_TFC_F0_SHIFT      (0U)
#define LPDDR_DENALI_PI_208_PI_TFC_F0(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_208_PI_TFC_F0_SHIFT)) & LPDDR_DENALI_PI_208_PI_TFC_F0_MASK)

#define LPDDR_DENALI_PI_208_PI_TCKEHDQS_F1_MASK  (0x3F0000U)
#define LPDDR_DENALI_PI_208_PI_TCKEHDQS_F1_SHIFT (16U)
#define LPDDR_DENALI_PI_208_PI_TCKEHDQS_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_208_PI_TCKEHDQS_F1_SHIFT)) & LPDDR_DENALI_PI_208_PI_TCKEHDQS_F1_MASK)
/*! @} */

/*! @name DENALI_PI_209 - DENALI_PI_209 */
/*! @{ */

#define LPDDR_DENALI_PI_209_PI_TFC_F1_MASK       (0x3FFU)
#define LPDDR_DENALI_PI_209_PI_TFC_F1_SHIFT      (0U)
#define LPDDR_DENALI_PI_209_PI_TFC_F1(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_209_PI_TFC_F1_SHIFT)) & LPDDR_DENALI_PI_209_PI_TFC_F1_MASK)

#define LPDDR_DENALI_PI_209_PI_TCKEHDQS_F2_MASK  (0x3F0000U)
#define LPDDR_DENALI_PI_209_PI_TCKEHDQS_F2_SHIFT (16U)
#define LPDDR_DENALI_PI_209_PI_TCKEHDQS_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_209_PI_TCKEHDQS_F2_SHIFT)) & LPDDR_DENALI_PI_209_PI_TCKEHDQS_F2_MASK)
/*! @} */

/*! @name DENALI_PI_210 - DENALI_PI_210 */
/*! @{ */

#define LPDDR_DENALI_PI_210_PI_TFC_F2_MASK       (0x3FFU)
#define LPDDR_DENALI_PI_210_PI_TFC_F2_SHIFT      (0U)
#define LPDDR_DENALI_PI_210_PI_TFC_F2(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_210_PI_TFC_F2_SHIFT)) & LPDDR_DENALI_PI_210_PI_TFC_F2_MASK)

#define LPDDR_DENALI_PI_210_PI_TDFI_WDQLVL_WR_F0_MASK (0x3FF0000U)
#define LPDDR_DENALI_PI_210_PI_TDFI_WDQLVL_WR_F0_SHIFT (16U)
/*! PI_TDFI_WDQLVL_WR_F0 - Switch time from write to read for frequency set 0. */
#define LPDDR_DENALI_PI_210_PI_TDFI_WDQLVL_WR_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_210_PI_TDFI_WDQLVL_WR_F0_SHIFT)) & LPDDR_DENALI_PI_210_PI_TDFI_WDQLVL_WR_F0_MASK)
/*! @} */

/*! @name DENALI_PI_211 - DENALI_PI_211 */
/*! @{ */

#define LPDDR_DENALI_PI_211_PI_TDFI_WDQLVL_RW_F0_MASK (0x3FFU)
#define LPDDR_DENALI_PI_211_PI_TDFI_WDQLVL_RW_F0_SHIFT (0U)
/*! PI_TDFI_WDQLVL_RW_F0 - Switch time from read to write for frequency set 0. */
#define LPDDR_DENALI_PI_211_PI_TDFI_WDQLVL_RW_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_211_PI_TDFI_WDQLVL_RW_F0_SHIFT)) & LPDDR_DENALI_PI_211_PI_TDFI_WDQLVL_RW_F0_MASK)

#define LPDDR_DENALI_PI_211_PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK (0x7F0000U)
#define LPDDR_DENALI_PI_211_PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT (16U)
#define LPDDR_DENALI_PI_211_PI_WDQLVL_VREF_INITIAL_START_POINT_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_211_PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT)) & LPDDR_DENALI_PI_211_PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK)

#define LPDDR_DENALI_PI_211_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK (0x7F000000U)
#define LPDDR_DENALI_PI_211_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT (24U)
#define LPDDR_DENALI_PI_211_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_211_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT)) & LPDDR_DENALI_PI_211_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK)
/*! @} */

/*! @name DENALI_PI_212 - DENALI_PI_212 */
/*! @{ */

#define LPDDR_DENALI_PI_212_PI_WDQLVL_VREF_DELTA_F0_MASK (0xFU)
#define LPDDR_DENALI_PI_212_PI_WDQLVL_VREF_DELTA_F0_SHIFT (0U)
#define LPDDR_DENALI_PI_212_PI_WDQLVL_VREF_DELTA_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_212_PI_WDQLVL_VREF_DELTA_F0_SHIFT)) & LPDDR_DENALI_PI_212_PI_WDQLVL_VREF_DELTA_F0_MASK)

#define LPDDR_DENALI_PI_212_PI_WDQLVL_EN_F0_MASK (0x300U)
#define LPDDR_DENALI_PI_212_PI_WDQLVL_EN_F0_SHIFT (8U)
#define LPDDR_DENALI_PI_212_PI_WDQLVL_EN_F0(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_212_PI_WDQLVL_EN_F0_SHIFT)) & LPDDR_DENALI_PI_212_PI_WDQLVL_EN_F0_MASK)

#define LPDDR_DENALI_PI_212_PI_NTP_TRAIN_EN_F0_MASK (0x30000U)
#define LPDDR_DENALI_PI_212_PI_NTP_TRAIN_EN_F0_SHIFT (16U)
#define LPDDR_DENALI_PI_212_PI_NTP_TRAIN_EN_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_212_PI_NTP_TRAIN_EN_F0_SHIFT)) & LPDDR_DENALI_PI_212_PI_NTP_TRAIN_EN_F0_MASK)
/*! @} */

/*! @name DENALI_PI_213 - DENALI_PI_213 */
/*! @{ */

#define LPDDR_DENALI_PI_213_PI_TDFI_WDQLVL_WR_F1_MASK (0x3FFU)
#define LPDDR_DENALI_PI_213_PI_TDFI_WDQLVL_WR_F1_SHIFT (0U)
/*! PI_TDFI_WDQLVL_WR_F1 - Switch time from write to read for frequency set 1. */
#define LPDDR_DENALI_PI_213_PI_TDFI_WDQLVL_WR_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_213_PI_TDFI_WDQLVL_WR_F1_SHIFT)) & LPDDR_DENALI_PI_213_PI_TDFI_WDQLVL_WR_F1_MASK)

#define LPDDR_DENALI_PI_213_PI_TDFI_WDQLVL_RW_F1_MASK (0x3FF0000U)
#define LPDDR_DENALI_PI_213_PI_TDFI_WDQLVL_RW_F1_SHIFT (16U)
/*! PI_TDFI_WDQLVL_RW_F1 - Switch time from read to write for frequency set 1. */
#define LPDDR_DENALI_PI_213_PI_TDFI_WDQLVL_RW_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_213_PI_TDFI_WDQLVL_RW_F1_SHIFT)) & LPDDR_DENALI_PI_213_PI_TDFI_WDQLVL_RW_F1_MASK)
/*! @} */

/*! @name DENALI_PI_214 - DENALI_PI_214 */
/*! @{ */

#define LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK (0x7FU)
#define LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_INITIAL_START_POINT_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT)) & LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK)

#define LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK (0x7F00U)
#define LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT (8U)
#define LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT)) & LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK)

#define LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_DELTA_F1_MASK (0xF0000U)
#define LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_DELTA_F1_SHIFT (16U)
#define LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_DELTA_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_DELTA_F1_SHIFT)) & LPDDR_DENALI_PI_214_PI_WDQLVL_VREF_DELTA_F1_MASK)

#define LPDDR_DENALI_PI_214_PI_WDQLVL_EN_F1_MASK (0x3000000U)
#define LPDDR_DENALI_PI_214_PI_WDQLVL_EN_F1_SHIFT (24U)
#define LPDDR_DENALI_PI_214_PI_WDQLVL_EN_F1(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_214_PI_WDQLVL_EN_F1_SHIFT)) & LPDDR_DENALI_PI_214_PI_WDQLVL_EN_F1_MASK)
/*! @} */

/*! @name DENALI_PI_215 - DENALI_PI_215 */
/*! @{ */

#define LPDDR_DENALI_PI_215_PI_NTP_TRAIN_EN_F1_MASK (0x3U)
#define LPDDR_DENALI_PI_215_PI_NTP_TRAIN_EN_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_215_PI_NTP_TRAIN_EN_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_215_PI_NTP_TRAIN_EN_F1_SHIFT)) & LPDDR_DENALI_PI_215_PI_NTP_TRAIN_EN_F1_MASK)

#define LPDDR_DENALI_PI_215_PI_TDFI_WDQLVL_WR_F2_MASK (0x3FF00U)
#define LPDDR_DENALI_PI_215_PI_TDFI_WDQLVL_WR_F2_SHIFT (8U)
/*! PI_TDFI_WDQLVL_WR_F2 - Switch time from write to read for frequency set 2. */
#define LPDDR_DENALI_PI_215_PI_TDFI_WDQLVL_WR_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_215_PI_TDFI_WDQLVL_WR_F2_SHIFT)) & LPDDR_DENALI_PI_215_PI_TDFI_WDQLVL_WR_F2_MASK)
/*! @} */

/*! @name DENALI_PI_216 - DENALI_PI_216 */
/*! @{ */

#define LPDDR_DENALI_PI_216_PI_TDFI_WDQLVL_RW_F2_MASK (0x3FFU)
#define LPDDR_DENALI_PI_216_PI_TDFI_WDQLVL_RW_F2_SHIFT (0U)
/*! PI_TDFI_WDQLVL_RW_F2 - Switch time from read to write for frequency set 2. */
#define LPDDR_DENALI_PI_216_PI_TDFI_WDQLVL_RW_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_216_PI_TDFI_WDQLVL_RW_F2_SHIFT)) & LPDDR_DENALI_PI_216_PI_TDFI_WDQLVL_RW_F2_MASK)

#define LPDDR_DENALI_PI_216_PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK (0x7F0000U)
#define LPDDR_DENALI_PI_216_PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT (16U)
#define LPDDR_DENALI_PI_216_PI_WDQLVL_VREF_INITIAL_START_POINT_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_216_PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT)) & LPDDR_DENALI_PI_216_PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK)

#define LPDDR_DENALI_PI_216_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK (0x7F000000U)
#define LPDDR_DENALI_PI_216_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT (24U)
#define LPDDR_DENALI_PI_216_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_216_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT)) & LPDDR_DENALI_PI_216_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK)
/*! @} */

/*! @name DENALI_PI_217 - DENALI_PI_217 */
/*! @{ */

#define LPDDR_DENALI_PI_217_PI_WDQLVL_VREF_DELTA_F2_MASK (0xFU)
#define LPDDR_DENALI_PI_217_PI_WDQLVL_VREF_DELTA_F2_SHIFT (0U)
#define LPDDR_DENALI_PI_217_PI_WDQLVL_VREF_DELTA_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_217_PI_WDQLVL_VREF_DELTA_F2_SHIFT)) & LPDDR_DENALI_PI_217_PI_WDQLVL_VREF_DELTA_F2_MASK)

#define LPDDR_DENALI_PI_217_PI_WDQLVL_EN_F2_MASK (0x300U)
#define LPDDR_DENALI_PI_217_PI_WDQLVL_EN_F2_SHIFT (8U)
#define LPDDR_DENALI_PI_217_PI_WDQLVL_EN_F2(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_217_PI_WDQLVL_EN_F2_SHIFT)) & LPDDR_DENALI_PI_217_PI_WDQLVL_EN_F2_MASK)

#define LPDDR_DENALI_PI_217_PI_NTP_TRAIN_EN_F2_MASK (0x30000U)
#define LPDDR_DENALI_PI_217_PI_NTP_TRAIN_EN_F2_SHIFT (16U)
#define LPDDR_DENALI_PI_217_PI_NTP_TRAIN_EN_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_217_PI_NTP_TRAIN_EN_F2_SHIFT)) & LPDDR_DENALI_PI_217_PI_NTP_TRAIN_EN_F2_MASK)

#define LPDDR_DENALI_PI_217_PI_TRTP_F0_MASK      (0xFF000000U)
#define LPDDR_DENALI_PI_217_PI_TRTP_F0_SHIFT     (24U)
#define LPDDR_DENALI_PI_217_PI_TRTP_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_217_PI_TRTP_F0_SHIFT)) & LPDDR_DENALI_PI_217_PI_TRTP_F0_MASK)
/*! @} */

/*! @name DENALI_PI_218 - DENALI_PI_218 */
/*! @{ */

#define LPDDR_DENALI_PI_218_PI_TRP_F0_MASK       (0xFFU)
#define LPDDR_DENALI_PI_218_PI_TRP_F0_SHIFT      (0U)
#define LPDDR_DENALI_PI_218_PI_TRP_F0(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_218_PI_TRP_F0_SHIFT)) & LPDDR_DENALI_PI_218_PI_TRP_F0_MASK)

#define LPDDR_DENALI_PI_218_PI_TRCD_F0_MASK      (0xFF00U)
#define LPDDR_DENALI_PI_218_PI_TRCD_F0_SHIFT     (8U)
#define LPDDR_DENALI_PI_218_PI_TRCD_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_218_PI_TRCD_F0_SHIFT)) & LPDDR_DENALI_PI_218_PI_TRCD_F0_MASK)

#define LPDDR_DENALI_PI_218_PI_TWTR_F0_MASK      (0x3F0000U)
#define LPDDR_DENALI_PI_218_PI_TWTR_F0_SHIFT     (16U)
#define LPDDR_DENALI_PI_218_PI_TWTR_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_218_PI_TWTR_F0_SHIFT)) & LPDDR_DENALI_PI_218_PI_TWTR_F0_MASK)

#define LPDDR_DENALI_PI_218_PI_TWR_F0_MASK       (0xFF000000U)
#define LPDDR_DENALI_PI_218_PI_TWR_F0_SHIFT      (24U)
#define LPDDR_DENALI_PI_218_PI_TWR_F0(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_218_PI_TWR_F0_SHIFT)) & LPDDR_DENALI_PI_218_PI_TWR_F0_MASK)
/*! @} */

/*! @name DENALI_PI_219 - DENALI_PI_219 */
/*! @{ */

#define LPDDR_DENALI_PI_219_PI_TRAS_MAX_F0_MASK  (0x1FFFFU)
#define LPDDR_DENALI_PI_219_PI_TRAS_MAX_F0_SHIFT (0U)
#define LPDDR_DENALI_PI_219_PI_TRAS_MAX_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_219_PI_TRAS_MAX_F0_SHIFT)) & LPDDR_DENALI_PI_219_PI_TRAS_MAX_F0_MASK)
/*! @} */

/*! @name DENALI_PI_220 - DENALI_PI_220 */
/*! @{ */

#define LPDDR_DENALI_PI_220_PI_TRAS_MIN_F0_MASK  (0x1FFU)
#define LPDDR_DENALI_PI_220_PI_TRAS_MIN_F0_SHIFT (0U)
#define LPDDR_DENALI_PI_220_PI_TRAS_MIN_F0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_220_PI_TRAS_MIN_F0_SHIFT)) & LPDDR_DENALI_PI_220_PI_TRAS_MIN_F0_MASK)

#define LPDDR_DENALI_PI_220_PI_TDQSCK_MAX_F0_MASK (0xF0000U)
#define LPDDR_DENALI_PI_220_PI_TDQSCK_MAX_F0_SHIFT (16U)
#define LPDDR_DENALI_PI_220_PI_TDQSCK_MAX_F0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_220_PI_TDQSCK_MAX_F0_SHIFT)) & LPDDR_DENALI_PI_220_PI_TDQSCK_MAX_F0_MASK)

#define LPDDR_DENALI_PI_220_PI_TCCDMW_F0_MASK    (0x3F000000U)
#define LPDDR_DENALI_PI_220_PI_TCCDMW_F0_SHIFT   (24U)
#define LPDDR_DENALI_PI_220_PI_TCCDMW_F0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_220_PI_TCCDMW_F0_SHIFT)) & LPDDR_DENALI_PI_220_PI_TCCDMW_F0_MASK)
/*! @} */

/*! @name DENALI_PI_221 - DENALI_PI_221 */
/*! @{ */

#define LPDDR_DENALI_PI_221_PI_TSR_F0_MASK       (0xFFU)
#define LPDDR_DENALI_PI_221_PI_TSR_F0_SHIFT      (0U)
#define LPDDR_DENALI_PI_221_PI_TSR_F0(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_221_PI_TSR_F0_SHIFT)) & LPDDR_DENALI_PI_221_PI_TSR_F0_MASK)

#define LPDDR_DENALI_PI_221_PI_TMRD_F0_MASK      (0xFF00U)
#define LPDDR_DENALI_PI_221_PI_TMRD_F0_SHIFT     (8U)
#define LPDDR_DENALI_PI_221_PI_TMRD_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_221_PI_TMRD_F0_SHIFT)) & LPDDR_DENALI_PI_221_PI_TMRD_F0_MASK)

#define LPDDR_DENALI_PI_221_PI_TMRW_F0_MASK      (0xFF0000U)
#define LPDDR_DENALI_PI_221_PI_TMRW_F0_SHIFT     (16U)
#define LPDDR_DENALI_PI_221_PI_TMRW_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_221_PI_TMRW_F0_SHIFT)) & LPDDR_DENALI_PI_221_PI_TMRW_F0_MASK)

#define LPDDR_DENALI_PI_221_PI_TRTP_F1_MASK      (0xFF000000U)
#define LPDDR_DENALI_PI_221_PI_TRTP_F1_SHIFT     (24U)
#define LPDDR_DENALI_PI_221_PI_TRTP_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_221_PI_TRTP_F1_SHIFT)) & LPDDR_DENALI_PI_221_PI_TRTP_F1_MASK)
/*! @} */

/*! @name DENALI_PI_222 - DENALI_PI_222 */
/*! @{ */

#define LPDDR_DENALI_PI_222_PI_TRP_F1_MASK       (0xFFU)
#define LPDDR_DENALI_PI_222_PI_TRP_F1_SHIFT      (0U)
#define LPDDR_DENALI_PI_222_PI_TRP_F1(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_222_PI_TRP_F1_SHIFT)) & LPDDR_DENALI_PI_222_PI_TRP_F1_MASK)

#define LPDDR_DENALI_PI_222_PI_TRCD_F1_MASK      (0xFF00U)
#define LPDDR_DENALI_PI_222_PI_TRCD_F1_SHIFT     (8U)
#define LPDDR_DENALI_PI_222_PI_TRCD_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_222_PI_TRCD_F1_SHIFT)) & LPDDR_DENALI_PI_222_PI_TRCD_F1_MASK)

#define LPDDR_DENALI_PI_222_PI_TWTR_F1_MASK      (0x3F0000U)
#define LPDDR_DENALI_PI_222_PI_TWTR_F1_SHIFT     (16U)
#define LPDDR_DENALI_PI_222_PI_TWTR_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_222_PI_TWTR_F1_SHIFT)) & LPDDR_DENALI_PI_222_PI_TWTR_F1_MASK)

#define LPDDR_DENALI_PI_222_PI_TWR_F1_MASK       (0xFF000000U)
#define LPDDR_DENALI_PI_222_PI_TWR_F1_SHIFT      (24U)
#define LPDDR_DENALI_PI_222_PI_TWR_F1(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_222_PI_TWR_F1_SHIFT)) & LPDDR_DENALI_PI_222_PI_TWR_F1_MASK)
/*! @} */

/*! @name DENALI_PI_223 - DENALI_PI_223 */
/*! @{ */

#define LPDDR_DENALI_PI_223_PI_TRAS_MAX_F1_MASK  (0x1FFFFU)
#define LPDDR_DENALI_PI_223_PI_TRAS_MAX_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_223_PI_TRAS_MAX_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_223_PI_TRAS_MAX_F1_SHIFT)) & LPDDR_DENALI_PI_223_PI_TRAS_MAX_F1_MASK)
/*! @} */

/*! @name DENALI_PI_224 - DENALI_PI_224 */
/*! @{ */

#define LPDDR_DENALI_PI_224_PI_TRAS_MIN_F1_MASK  (0x1FFU)
#define LPDDR_DENALI_PI_224_PI_TRAS_MIN_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_224_PI_TRAS_MIN_F1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_224_PI_TRAS_MIN_F1_SHIFT)) & LPDDR_DENALI_PI_224_PI_TRAS_MIN_F1_MASK)

#define LPDDR_DENALI_PI_224_PI_TDQSCK_MAX_F1_MASK (0xF0000U)
#define LPDDR_DENALI_PI_224_PI_TDQSCK_MAX_F1_SHIFT (16U)
#define LPDDR_DENALI_PI_224_PI_TDQSCK_MAX_F1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_224_PI_TDQSCK_MAX_F1_SHIFT)) & LPDDR_DENALI_PI_224_PI_TDQSCK_MAX_F1_MASK)

#define LPDDR_DENALI_PI_224_PI_TCCDMW_F1_MASK    (0x3F000000U)
#define LPDDR_DENALI_PI_224_PI_TCCDMW_F1_SHIFT   (24U)
#define LPDDR_DENALI_PI_224_PI_TCCDMW_F1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_224_PI_TCCDMW_F1_SHIFT)) & LPDDR_DENALI_PI_224_PI_TCCDMW_F1_MASK)
/*! @} */

/*! @name DENALI_PI_225 - DENALI_PI_225 */
/*! @{ */

#define LPDDR_DENALI_PI_225_PI_TSR_F1_MASK       (0xFFU)
#define LPDDR_DENALI_PI_225_PI_TSR_F1_SHIFT      (0U)
#define LPDDR_DENALI_PI_225_PI_TSR_F1(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_225_PI_TSR_F1_SHIFT)) & LPDDR_DENALI_PI_225_PI_TSR_F1_MASK)

#define LPDDR_DENALI_PI_225_PI_TMRD_F1_MASK      (0xFF00U)
#define LPDDR_DENALI_PI_225_PI_TMRD_F1_SHIFT     (8U)
#define LPDDR_DENALI_PI_225_PI_TMRD_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_225_PI_TMRD_F1_SHIFT)) & LPDDR_DENALI_PI_225_PI_TMRD_F1_MASK)

#define LPDDR_DENALI_PI_225_PI_TMRW_F1_MASK      (0xFF0000U)
#define LPDDR_DENALI_PI_225_PI_TMRW_F1_SHIFT     (16U)
#define LPDDR_DENALI_PI_225_PI_TMRW_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_225_PI_TMRW_F1_SHIFT)) & LPDDR_DENALI_PI_225_PI_TMRW_F1_MASK)

#define LPDDR_DENALI_PI_225_PI_TRTP_F2_MASK      (0xFF000000U)
#define LPDDR_DENALI_PI_225_PI_TRTP_F2_SHIFT     (24U)
#define LPDDR_DENALI_PI_225_PI_TRTP_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_225_PI_TRTP_F2_SHIFT)) & LPDDR_DENALI_PI_225_PI_TRTP_F2_MASK)
/*! @} */

/*! @name DENALI_PI_226 - DENALI_PI_226 */
/*! @{ */

#define LPDDR_DENALI_PI_226_PI_TRP_F2_MASK       (0xFFU)
#define LPDDR_DENALI_PI_226_PI_TRP_F2_SHIFT      (0U)
#define LPDDR_DENALI_PI_226_PI_TRP_F2(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_226_PI_TRP_F2_SHIFT)) & LPDDR_DENALI_PI_226_PI_TRP_F2_MASK)

#define LPDDR_DENALI_PI_226_PI_TRCD_F2_MASK      (0xFF00U)
#define LPDDR_DENALI_PI_226_PI_TRCD_F2_SHIFT     (8U)
#define LPDDR_DENALI_PI_226_PI_TRCD_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_226_PI_TRCD_F2_SHIFT)) & LPDDR_DENALI_PI_226_PI_TRCD_F2_MASK)

#define LPDDR_DENALI_PI_226_PI_TWTR_F2_MASK      (0x3F0000U)
#define LPDDR_DENALI_PI_226_PI_TWTR_F2_SHIFT     (16U)
#define LPDDR_DENALI_PI_226_PI_TWTR_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_226_PI_TWTR_F2_SHIFT)) & LPDDR_DENALI_PI_226_PI_TWTR_F2_MASK)

#define LPDDR_DENALI_PI_226_PI_TWR_F2_MASK       (0xFF000000U)
#define LPDDR_DENALI_PI_226_PI_TWR_F2_SHIFT      (24U)
#define LPDDR_DENALI_PI_226_PI_TWR_F2(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_226_PI_TWR_F2_SHIFT)) & LPDDR_DENALI_PI_226_PI_TWR_F2_MASK)
/*! @} */

/*! @name DENALI_PI_227 - DENALI_PI_227 */
/*! @{ */

#define LPDDR_DENALI_PI_227_PI_TRAS_MAX_F2_MASK  (0x1FFFFU)
#define LPDDR_DENALI_PI_227_PI_TRAS_MAX_F2_SHIFT (0U)
#define LPDDR_DENALI_PI_227_PI_TRAS_MAX_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_227_PI_TRAS_MAX_F2_SHIFT)) & LPDDR_DENALI_PI_227_PI_TRAS_MAX_F2_MASK)
/*! @} */

/*! @name DENALI_PI_228 - DENALI_PI_228 */
/*! @{ */

#define LPDDR_DENALI_PI_228_PI_TRAS_MIN_F2_MASK  (0x1FFU)
#define LPDDR_DENALI_PI_228_PI_TRAS_MIN_F2_SHIFT (0U)
#define LPDDR_DENALI_PI_228_PI_TRAS_MIN_F2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_228_PI_TRAS_MIN_F2_SHIFT)) & LPDDR_DENALI_PI_228_PI_TRAS_MIN_F2_MASK)

#define LPDDR_DENALI_PI_228_PI_TDQSCK_MAX_F2_MASK (0xF0000U)
#define LPDDR_DENALI_PI_228_PI_TDQSCK_MAX_F2_SHIFT (16U)
#define LPDDR_DENALI_PI_228_PI_TDQSCK_MAX_F2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_228_PI_TDQSCK_MAX_F2_SHIFT)) & LPDDR_DENALI_PI_228_PI_TDQSCK_MAX_F2_MASK)

#define LPDDR_DENALI_PI_228_PI_TCCDMW_F2_MASK    (0x3F000000U)
#define LPDDR_DENALI_PI_228_PI_TCCDMW_F2_SHIFT   (24U)
#define LPDDR_DENALI_PI_228_PI_TCCDMW_F2(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_228_PI_TCCDMW_F2_SHIFT)) & LPDDR_DENALI_PI_228_PI_TCCDMW_F2_MASK)
/*! @} */

/*! @name DENALI_PI_229 - DENALI_PI_229 */
/*! @{ */

#define LPDDR_DENALI_PI_229_PI_TSR_F2_MASK       (0xFFU)
#define LPDDR_DENALI_PI_229_PI_TSR_F2_SHIFT      (0U)
#define LPDDR_DENALI_PI_229_PI_TSR_F2(x)         (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_229_PI_TSR_F2_SHIFT)) & LPDDR_DENALI_PI_229_PI_TSR_F2_MASK)

#define LPDDR_DENALI_PI_229_PI_TMRD_F2_MASK      (0xFF00U)
#define LPDDR_DENALI_PI_229_PI_TMRD_F2_SHIFT     (8U)
#define LPDDR_DENALI_PI_229_PI_TMRD_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_229_PI_TMRD_F2_SHIFT)) & LPDDR_DENALI_PI_229_PI_TMRD_F2_MASK)

#define LPDDR_DENALI_PI_229_PI_TMRW_F2_MASK      (0xFF0000U)
#define LPDDR_DENALI_PI_229_PI_TMRW_F2_SHIFT     (16U)
#define LPDDR_DENALI_PI_229_PI_TMRW_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_229_PI_TMRW_F2_SHIFT)) & LPDDR_DENALI_PI_229_PI_TMRW_F2_MASK)
/*! @} */

/*! @name DENALI_PI_230 - DENALI_PI_230 */
/*! @{ */

#define LPDDR_DENALI_PI_230_PI_TDFI_CTRLUPD_MAX_F0_MASK (0x1FFFFFU)
#define LPDDR_DENALI_PI_230_PI_TDFI_CTRLUPD_MAX_F0_SHIFT (0U)
#define LPDDR_DENALI_PI_230_PI_TDFI_CTRLUPD_MAX_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_230_PI_TDFI_CTRLUPD_MAX_F0_SHIFT)) & LPDDR_DENALI_PI_230_PI_TDFI_CTRLUPD_MAX_F0_MASK)
/*! @} */

/*! @name DENALI_PI_231 - DENALI_PI_231 */
/*! @{ */

#define LPDDR_DENALI_PI_231_PI_TDFI_CTRLUPD_INTERVAL_F0_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_PI_231_PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT (0U)
#define LPDDR_DENALI_PI_231_PI_TDFI_CTRLUPD_INTERVAL_F0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_231_PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT)) & LPDDR_DENALI_PI_231_PI_TDFI_CTRLUPD_INTERVAL_F0_MASK)
/*! @} */

/*! @name DENALI_PI_232 - DENALI_PI_232 */
/*! @{ */

#define LPDDR_DENALI_PI_232_PI_TDFI_CTRLUPD_MAX_F1_MASK (0x1FFFFFU)
#define LPDDR_DENALI_PI_232_PI_TDFI_CTRLUPD_MAX_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_232_PI_TDFI_CTRLUPD_MAX_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_232_PI_TDFI_CTRLUPD_MAX_F1_SHIFT)) & LPDDR_DENALI_PI_232_PI_TDFI_CTRLUPD_MAX_F1_MASK)
/*! @} */

/*! @name DENALI_PI_233 - DENALI_PI_233 */
/*! @{ */

#define LPDDR_DENALI_PI_233_PI_TDFI_CTRLUPD_INTERVAL_F1_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_PI_233_PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT (0U)
#define LPDDR_DENALI_PI_233_PI_TDFI_CTRLUPD_INTERVAL_F1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_233_PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT)) & LPDDR_DENALI_PI_233_PI_TDFI_CTRLUPD_INTERVAL_F1_MASK)
/*! @} */

/*! @name DENALI_PI_234 - DENALI_PI_234 */
/*! @{ */

#define LPDDR_DENALI_PI_234_PI_TDFI_CTRLUPD_MAX_F2_MASK (0x1FFFFFU)
#define LPDDR_DENALI_PI_234_PI_TDFI_CTRLUPD_MAX_F2_SHIFT (0U)
#define LPDDR_DENALI_PI_234_PI_TDFI_CTRLUPD_MAX_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_234_PI_TDFI_CTRLUPD_MAX_F2_SHIFT)) & LPDDR_DENALI_PI_234_PI_TDFI_CTRLUPD_MAX_F2_MASK)
/*! @} */

/*! @name DENALI_PI_235 - DENALI_PI_235 */
/*! @{ */

#define LPDDR_DENALI_PI_235_PI_TDFI_CTRLUPD_INTERVAL_F2_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_PI_235_PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT (0U)
#define LPDDR_DENALI_PI_235_PI_TDFI_CTRLUPD_INTERVAL_F2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_235_PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT)) & LPDDR_DENALI_PI_235_PI_TDFI_CTRLUPD_INTERVAL_F2_MASK)
/*! @} */

/*! @name DENALI_PI_236 - DENALI_PI_236 */
/*! @{ */

#define LPDDR_DENALI_PI_236_PI_TXSR_F0_MASK      (0xFFFFU)
#define LPDDR_DENALI_PI_236_PI_TXSR_F0_SHIFT     (0U)
#define LPDDR_DENALI_PI_236_PI_TXSR_F0(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_236_PI_TXSR_F0_SHIFT)) & LPDDR_DENALI_PI_236_PI_TXSR_F0_MASK)

#define LPDDR_DENALI_PI_236_PI_TXSR_F1_MASK      (0xFFFF0000U)
#define LPDDR_DENALI_PI_236_PI_TXSR_F1_SHIFT     (16U)
#define LPDDR_DENALI_PI_236_PI_TXSR_F1(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_236_PI_TXSR_F1_SHIFT)) & LPDDR_DENALI_PI_236_PI_TXSR_F1_MASK)
/*! @} */

/*! @name DENALI_PI_237 - DENALI_PI_237 */
/*! @{ */

#define LPDDR_DENALI_PI_237_PI_TXSR_F2_MASK      (0xFFFFU)
#define LPDDR_DENALI_PI_237_PI_TXSR_F2_SHIFT     (0U)
#define LPDDR_DENALI_PI_237_PI_TXSR_F2(x)        (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_237_PI_TXSR_F2_SHIFT)) & LPDDR_DENALI_PI_237_PI_TXSR_F2_MASK)

#define LPDDR_DENALI_PI_237_PI_TEXCKE_F0_MASK    (0x3F0000U)
#define LPDDR_DENALI_PI_237_PI_TEXCKE_F0_SHIFT   (16U)
#define LPDDR_DENALI_PI_237_PI_TEXCKE_F0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_237_PI_TEXCKE_F0_SHIFT)) & LPDDR_DENALI_PI_237_PI_TEXCKE_F0_MASK)

#define LPDDR_DENALI_PI_237_PI_TEXCKE_F1_MASK    (0x3F000000U)
#define LPDDR_DENALI_PI_237_PI_TEXCKE_F1_SHIFT   (24U)
#define LPDDR_DENALI_PI_237_PI_TEXCKE_F1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_237_PI_TEXCKE_F1_SHIFT)) & LPDDR_DENALI_PI_237_PI_TEXCKE_F1_MASK)
/*! @} */

/*! @name DENALI_PI_238 - DENALI_PI_238 */
/*! @{ */

#define LPDDR_DENALI_PI_238_PI_TEXCKE_F2_MASK    (0x3FU)
#define LPDDR_DENALI_PI_238_PI_TEXCKE_F2_SHIFT   (0U)
#define LPDDR_DENALI_PI_238_PI_TEXCKE_F2(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_238_PI_TEXCKE_F2_SHIFT)) & LPDDR_DENALI_PI_238_PI_TEXCKE_F2_MASK)

#define LPDDR_DENALI_PI_238_PI_TINIT_F0_MASK     (0xFFFFFF00U)
#define LPDDR_DENALI_PI_238_PI_TINIT_F0_SHIFT    (8U)
#define LPDDR_DENALI_PI_238_PI_TINIT_F0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_238_PI_TINIT_F0_SHIFT)) & LPDDR_DENALI_PI_238_PI_TINIT_F0_MASK)
/*! @} */

/*! @name DENALI_PI_239 - DENALI_PI_239 */
/*! @{ */

#define LPDDR_DENALI_PI_239_PI_TINIT3_F0_MASK    (0xFFFFFFU)
#define LPDDR_DENALI_PI_239_PI_TINIT3_F0_SHIFT   (0U)
#define LPDDR_DENALI_PI_239_PI_TINIT3_F0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_239_PI_TINIT3_F0_SHIFT)) & LPDDR_DENALI_PI_239_PI_TINIT3_F0_MASK)
/*! @} */

/*! @name DENALI_PI_242 - DENALI_PI_242 */
/*! @{ */

#define LPDDR_DENALI_PI_242_PI_TXSNR_F0_MASK     (0xFFFFU)
#define LPDDR_DENALI_PI_242_PI_TXSNR_F0_SHIFT    (0U)
#define LPDDR_DENALI_PI_242_PI_TXSNR_F0(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_242_PI_TXSNR_F0_SHIFT)) & LPDDR_DENALI_PI_242_PI_TXSNR_F0_MASK)
/*! @} */

/*! @name DENALI_PI_243 - DENALI_PI_243 */
/*! @{ */

#define LPDDR_DENALI_PI_243_PI_TINIT_F1_MASK     (0xFFFFFFU)
#define LPDDR_DENALI_PI_243_PI_TINIT_F1_SHIFT    (0U)
#define LPDDR_DENALI_PI_243_PI_TINIT_F1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_243_PI_TINIT_F1_SHIFT)) & LPDDR_DENALI_PI_243_PI_TINIT_F1_MASK)
/*! @} */

/*! @name DENALI_PI_244 - DENALI_PI_244 */
/*! @{ */

#define LPDDR_DENALI_PI_244_PI_TINIT3_F1_MASK    (0xFFFFFFU)
#define LPDDR_DENALI_PI_244_PI_TINIT3_F1_SHIFT   (0U)
#define LPDDR_DENALI_PI_244_PI_TINIT3_F1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_244_PI_TINIT3_F1_SHIFT)) & LPDDR_DENALI_PI_244_PI_TINIT3_F1_MASK)
/*! @} */

/*! @name DENALI_PI_246 - DENALI_PI_246 */
/*! @{ */

#define LPDDR_DENALI_PI_246_PI_TINIT5_F1_MASK    (0xFFFFFFU)
#define LPDDR_DENALI_PI_246_PI_TINIT5_F1_SHIFT   (0U)
#define LPDDR_DENALI_PI_246_PI_TINIT5_F1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_246_PI_TINIT5_F1_SHIFT)) & LPDDR_DENALI_PI_246_PI_TINIT5_F1_MASK)
/*! @} */

/*! @name DENALI_PI_247 - DENALI_PI_247 */
/*! @{ */

#define LPDDR_DENALI_PI_247_PI_TXSNR_F1_MASK     (0xFFFFU)
#define LPDDR_DENALI_PI_247_PI_TXSNR_F1_SHIFT    (0U)
#define LPDDR_DENALI_PI_247_PI_TXSNR_F1(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_247_PI_TXSNR_F1_SHIFT)) & LPDDR_DENALI_PI_247_PI_TXSNR_F1_MASK)
/*! @} */

/*! @name DENALI_PI_248 - DENALI_PI_248 */
/*! @{ */

#define LPDDR_DENALI_PI_248_PI_TINIT_F2_MASK     (0xFFFFFFU)
#define LPDDR_DENALI_PI_248_PI_TINIT_F2_SHIFT    (0U)
#define LPDDR_DENALI_PI_248_PI_TINIT_F2(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_248_PI_TINIT_F2_SHIFT)) & LPDDR_DENALI_PI_248_PI_TINIT_F2_MASK)
/*! @} */

/*! @name DENALI_PI_249 - DENALI_PI_249 */
/*! @{ */

#define LPDDR_DENALI_PI_249_PI_TINIT3_F2_MASK    (0xFFFFFFU)
#define LPDDR_DENALI_PI_249_PI_TINIT3_F2_SHIFT   (0U)
#define LPDDR_DENALI_PI_249_PI_TINIT3_F2(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_249_PI_TINIT3_F2_SHIFT)) & LPDDR_DENALI_PI_249_PI_TINIT3_F2_MASK)
/*! @} */

/*! @name DENALI_PI_251 - DENALI_PI_251 */
/*! @{ */

#define LPDDR_DENALI_PI_251_PI_TINIT5_F2_MASK    (0xFFFFFFU)
#define LPDDR_DENALI_PI_251_PI_TINIT5_F2_SHIFT   (0U)
#define LPDDR_DENALI_PI_251_PI_TINIT5_F2(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_251_PI_TINIT5_F2_SHIFT)) & LPDDR_DENALI_PI_251_PI_TINIT5_F2_MASK)
/*! @} */

/*! @name DENALI_PI_252 - DENALI_PI_252 */
/*! @{ */

#define LPDDR_DENALI_PI_252_PI_TXSNR_F2_MASK     (0xFFFFU)
#define LPDDR_DENALI_PI_252_PI_TXSNR_F2_SHIFT    (0U)
#define LPDDR_DENALI_PI_252_PI_TXSNR_F2(x)       (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_252_PI_TXSNR_F2_SHIFT)) & LPDDR_DENALI_PI_252_PI_TXSNR_F2_MASK)
/*! @} */

/*! @name DENALI_PI_253 - DENALI_PI_253 */
/*! @{ */

#define LPDDR_DENALI_PI_253_PI_TZQCAL_F0_MASK    (0xFFF0000U)
#define LPDDR_DENALI_PI_253_PI_TZQCAL_F0_SHIFT   (16U)
#define LPDDR_DENALI_PI_253_PI_TZQCAL_F0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_253_PI_TZQCAL_F0_SHIFT)) & LPDDR_DENALI_PI_253_PI_TZQCAL_F0_MASK)
/*! @} */

/*! @name DENALI_PI_254 - DENALI_PI_254 */
/*! @{ */

#define LPDDR_DENALI_PI_254_PI_TZQLAT_F0_MASK    (0x7FU)
#define LPDDR_DENALI_PI_254_PI_TZQLAT_F0_SHIFT   (0U)
#define LPDDR_DENALI_PI_254_PI_TZQLAT_F0(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_254_PI_TZQLAT_F0_SHIFT)) & LPDDR_DENALI_PI_254_PI_TZQLAT_F0_MASK)
/*! @} */

/*! @name DENALI_PI_255 - DENALI_PI_255 */
/*! @{ */

#define LPDDR_DENALI_PI_255_PI_TZQCAL_F1_MASK    (0xFFF0000U)
#define LPDDR_DENALI_PI_255_PI_TZQCAL_F1_SHIFT   (16U)
#define LPDDR_DENALI_PI_255_PI_TZQCAL_F1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_255_PI_TZQCAL_F1_SHIFT)) & LPDDR_DENALI_PI_255_PI_TZQCAL_F1_MASK)
/*! @} */

/*! @name DENALI_PI_256 - DENALI_PI_256 */
/*! @{ */

#define LPDDR_DENALI_PI_256_PI_TZQLAT_F1_MASK    (0x7FU)
#define LPDDR_DENALI_PI_256_PI_TZQLAT_F1_SHIFT   (0U)
#define LPDDR_DENALI_PI_256_PI_TZQLAT_F1(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_256_PI_TZQLAT_F1_SHIFT)) & LPDDR_DENALI_PI_256_PI_TZQLAT_F1_MASK)
/*! @} */

/*! @name DENALI_PI_257 - DENALI_PI_257 */
/*! @{ */

#define LPDDR_DENALI_PI_257_PI_TZQCAL_F2_MASK    (0xFFF0000U)
#define LPDDR_DENALI_PI_257_PI_TZQCAL_F2_SHIFT   (16U)
#define LPDDR_DENALI_PI_257_PI_TZQCAL_F2(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_257_PI_TZQCAL_F2_SHIFT)) & LPDDR_DENALI_PI_257_PI_TZQCAL_F2_MASK)
/*! @} */

/*! @name DENALI_PI_258 - DENALI_PI_258 */
/*! @{ */

#define LPDDR_DENALI_PI_258_PI_TZQLAT_F2_MASK    (0x7FU)
#define LPDDR_DENALI_PI_258_PI_TZQLAT_F2_SHIFT   (0U)
#define LPDDR_DENALI_PI_258_PI_TZQLAT_F2(x)      (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_258_PI_TZQLAT_F2_SHIFT)) & LPDDR_DENALI_PI_258_PI_TZQLAT_F2_MASK)
/*! @} */

/*! @name DENALI_PI_261 - DENALI_PI_261 */
/*! @{ */

#define LPDDR_DENALI_PI_261_PI_ODT_RD_MAP_CS0_MASK (0xFU)
#define LPDDR_DENALI_PI_261_PI_ODT_RD_MAP_CS0_SHIFT (0U)
#define LPDDR_DENALI_PI_261_PI_ODT_RD_MAP_CS0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_261_PI_ODT_RD_MAP_CS0_SHIFT)) & LPDDR_DENALI_PI_261_PI_ODT_RD_MAP_CS0_MASK)

#define LPDDR_DENALI_PI_261_PI_ODT_WR_MAP_CS0_MASK (0xF00U)
#define LPDDR_DENALI_PI_261_PI_ODT_WR_MAP_CS0_SHIFT (8U)
#define LPDDR_DENALI_PI_261_PI_ODT_WR_MAP_CS0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_261_PI_ODT_WR_MAP_CS0_SHIFT)) & LPDDR_DENALI_PI_261_PI_ODT_WR_MAP_CS0_MASK)

#define LPDDR_DENALI_PI_261_PI_ODT_RD_MAP_CS1_MASK (0xF0000U)
#define LPDDR_DENALI_PI_261_PI_ODT_RD_MAP_CS1_SHIFT (16U)
#define LPDDR_DENALI_PI_261_PI_ODT_RD_MAP_CS1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_261_PI_ODT_RD_MAP_CS1_SHIFT)) & LPDDR_DENALI_PI_261_PI_ODT_RD_MAP_CS1_MASK)

#define LPDDR_DENALI_PI_261_PI_ODT_WR_MAP_CS1_MASK (0xF000000U)
#define LPDDR_DENALI_PI_261_PI_ODT_WR_MAP_CS1_SHIFT (24U)
#define LPDDR_DENALI_PI_261_PI_ODT_WR_MAP_CS1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_261_PI_ODT_WR_MAP_CS1_SHIFT)) & LPDDR_DENALI_PI_261_PI_ODT_WR_MAP_CS1_MASK)
/*! @} */

/*! @name DENALI_PI_277 - DENALI_PI_277 */
/*! @{ */

#define LPDDR_DENALI_PI_277_PI_MR1_DATA_F0_0_MASK (0xFFU)
#define LPDDR_DENALI_PI_277_PI_MR1_DATA_F0_0_SHIFT (0U)
#define LPDDR_DENALI_PI_277_PI_MR1_DATA_F0_0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_277_PI_MR1_DATA_F0_0_SHIFT)) & LPDDR_DENALI_PI_277_PI_MR1_DATA_F0_0_MASK)

#define LPDDR_DENALI_PI_277_PI_MR2_DATA_F0_0_MASK (0xFF00U)
#define LPDDR_DENALI_PI_277_PI_MR2_DATA_F0_0_SHIFT (8U)
#define LPDDR_DENALI_PI_277_PI_MR2_DATA_F0_0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_277_PI_MR2_DATA_F0_0_SHIFT)) & LPDDR_DENALI_PI_277_PI_MR2_DATA_F0_0_MASK)

#define LPDDR_DENALI_PI_277_PI_MR3_DATA_F0_0_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_277_PI_MR3_DATA_F0_0_SHIFT (16U)
#define LPDDR_DENALI_PI_277_PI_MR3_DATA_F0_0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_277_PI_MR3_DATA_F0_0_SHIFT)) & LPDDR_DENALI_PI_277_PI_MR3_DATA_F0_0_MASK)

#define LPDDR_DENALI_PI_277_PI_MR11_DATA_F0_0_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_277_PI_MR11_DATA_F0_0_SHIFT (24U)
#define LPDDR_DENALI_PI_277_PI_MR11_DATA_F0_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_277_PI_MR11_DATA_F0_0_SHIFT)) & LPDDR_DENALI_PI_277_PI_MR11_DATA_F0_0_MASK)
/*! @} */

/*! @name DENALI_PI_278 - DENALI_PI_278 */
/*! @{ */

#define LPDDR_DENALI_PI_278_PI_MR12_DATA_F0_0_MASK (0xFFU)
#define LPDDR_DENALI_PI_278_PI_MR12_DATA_F0_0_SHIFT (0U)
#define LPDDR_DENALI_PI_278_PI_MR12_DATA_F0_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_278_PI_MR12_DATA_F0_0_SHIFT)) & LPDDR_DENALI_PI_278_PI_MR12_DATA_F0_0_MASK)

#define LPDDR_DENALI_PI_278_PI_MR14_DATA_F0_0_MASK (0xFF00U)
#define LPDDR_DENALI_PI_278_PI_MR14_DATA_F0_0_SHIFT (8U)
#define LPDDR_DENALI_PI_278_PI_MR14_DATA_F0_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_278_PI_MR14_DATA_F0_0_SHIFT)) & LPDDR_DENALI_PI_278_PI_MR14_DATA_F0_0_MASK)

#define LPDDR_DENALI_PI_278_PI_MR22_DATA_F0_0_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_278_PI_MR22_DATA_F0_0_SHIFT (16U)
#define LPDDR_DENALI_PI_278_PI_MR22_DATA_F0_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_278_PI_MR22_DATA_F0_0_SHIFT)) & LPDDR_DENALI_PI_278_PI_MR22_DATA_F0_0_MASK)

#define LPDDR_DENALI_PI_278_PI_MR1_DATA_F1_0_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_278_PI_MR1_DATA_F1_0_SHIFT (24U)
#define LPDDR_DENALI_PI_278_PI_MR1_DATA_F1_0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_278_PI_MR1_DATA_F1_0_SHIFT)) & LPDDR_DENALI_PI_278_PI_MR1_DATA_F1_0_MASK)
/*! @} */

/*! @name DENALI_PI_279 - DENALI_PI_279 */
/*! @{ */

#define LPDDR_DENALI_PI_279_PI_MR2_DATA_F1_0_MASK (0xFFU)
#define LPDDR_DENALI_PI_279_PI_MR2_DATA_F1_0_SHIFT (0U)
#define LPDDR_DENALI_PI_279_PI_MR2_DATA_F1_0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_279_PI_MR2_DATA_F1_0_SHIFT)) & LPDDR_DENALI_PI_279_PI_MR2_DATA_F1_0_MASK)

#define LPDDR_DENALI_PI_279_PI_MR3_DATA_F1_0_MASK (0xFF00U)
#define LPDDR_DENALI_PI_279_PI_MR3_DATA_F1_0_SHIFT (8U)
#define LPDDR_DENALI_PI_279_PI_MR3_DATA_F1_0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_279_PI_MR3_DATA_F1_0_SHIFT)) & LPDDR_DENALI_PI_279_PI_MR3_DATA_F1_0_MASK)

#define LPDDR_DENALI_PI_279_PI_MR11_DATA_F1_0_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_279_PI_MR11_DATA_F1_0_SHIFT (16U)
#define LPDDR_DENALI_PI_279_PI_MR11_DATA_F1_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_279_PI_MR11_DATA_F1_0_SHIFT)) & LPDDR_DENALI_PI_279_PI_MR11_DATA_F1_0_MASK)

#define LPDDR_DENALI_PI_279_PI_MR12_DATA_F1_0_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_279_PI_MR12_DATA_F1_0_SHIFT (24U)
#define LPDDR_DENALI_PI_279_PI_MR12_DATA_F1_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_279_PI_MR12_DATA_F1_0_SHIFT)) & LPDDR_DENALI_PI_279_PI_MR12_DATA_F1_0_MASK)
/*! @} */

/*! @name DENALI_PI_280 - DENALI_PI_280 */
/*! @{ */

#define LPDDR_DENALI_PI_280_PI_MR14_DATA_F1_0_MASK (0xFFU)
#define LPDDR_DENALI_PI_280_PI_MR14_DATA_F1_0_SHIFT (0U)
#define LPDDR_DENALI_PI_280_PI_MR14_DATA_F1_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_280_PI_MR14_DATA_F1_0_SHIFT)) & LPDDR_DENALI_PI_280_PI_MR14_DATA_F1_0_MASK)

#define LPDDR_DENALI_PI_280_PI_MR22_DATA_F1_0_MASK (0xFF00U)
#define LPDDR_DENALI_PI_280_PI_MR22_DATA_F1_0_SHIFT (8U)
#define LPDDR_DENALI_PI_280_PI_MR22_DATA_F1_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_280_PI_MR22_DATA_F1_0_SHIFT)) & LPDDR_DENALI_PI_280_PI_MR22_DATA_F1_0_MASK)

#define LPDDR_DENALI_PI_280_PI_MR1_DATA_F2_0_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_280_PI_MR1_DATA_F2_0_SHIFT (16U)
#define LPDDR_DENALI_PI_280_PI_MR1_DATA_F2_0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_280_PI_MR1_DATA_F2_0_SHIFT)) & LPDDR_DENALI_PI_280_PI_MR1_DATA_F2_0_MASK)

#define LPDDR_DENALI_PI_280_PI_MR2_DATA_F2_0_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_280_PI_MR2_DATA_F2_0_SHIFT (24U)
#define LPDDR_DENALI_PI_280_PI_MR2_DATA_F2_0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_280_PI_MR2_DATA_F2_0_SHIFT)) & LPDDR_DENALI_PI_280_PI_MR2_DATA_F2_0_MASK)
/*! @} */

/*! @name DENALI_PI_281 - DENALI_PI_281 */
/*! @{ */

#define LPDDR_DENALI_PI_281_PI_MR3_DATA_F2_0_MASK (0xFFU)
#define LPDDR_DENALI_PI_281_PI_MR3_DATA_F2_0_SHIFT (0U)
#define LPDDR_DENALI_PI_281_PI_MR3_DATA_F2_0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_281_PI_MR3_DATA_F2_0_SHIFT)) & LPDDR_DENALI_PI_281_PI_MR3_DATA_F2_0_MASK)

#define LPDDR_DENALI_PI_281_PI_MR11_DATA_F2_0_MASK (0xFF00U)
#define LPDDR_DENALI_PI_281_PI_MR11_DATA_F2_0_SHIFT (8U)
#define LPDDR_DENALI_PI_281_PI_MR11_DATA_F2_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_281_PI_MR11_DATA_F2_0_SHIFT)) & LPDDR_DENALI_PI_281_PI_MR11_DATA_F2_0_MASK)

#define LPDDR_DENALI_PI_281_PI_MR12_DATA_F2_0_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_281_PI_MR12_DATA_F2_0_SHIFT (16U)
#define LPDDR_DENALI_PI_281_PI_MR12_DATA_F2_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_281_PI_MR12_DATA_F2_0_SHIFT)) & LPDDR_DENALI_PI_281_PI_MR12_DATA_F2_0_MASK)

#define LPDDR_DENALI_PI_281_PI_MR14_DATA_F2_0_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_281_PI_MR14_DATA_F2_0_SHIFT (24U)
#define LPDDR_DENALI_PI_281_PI_MR14_DATA_F2_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_281_PI_MR14_DATA_F2_0_SHIFT)) & LPDDR_DENALI_PI_281_PI_MR14_DATA_F2_0_MASK)
/*! @} */

/*! @name DENALI_PI_282 - DENALI_PI_282 */
/*! @{ */

#define LPDDR_DENALI_PI_282_PI_MR22_DATA_F2_0_MASK (0xFFU)
#define LPDDR_DENALI_PI_282_PI_MR22_DATA_F2_0_SHIFT (0U)
#define LPDDR_DENALI_PI_282_PI_MR22_DATA_F2_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_282_PI_MR22_DATA_F2_0_SHIFT)) & LPDDR_DENALI_PI_282_PI_MR22_DATA_F2_0_MASK)

#define LPDDR_DENALI_PI_282_PI_MR1_DATA_F0_1_MASK (0xFF00U)
#define LPDDR_DENALI_PI_282_PI_MR1_DATA_F0_1_SHIFT (8U)
#define LPDDR_DENALI_PI_282_PI_MR1_DATA_F0_1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_282_PI_MR1_DATA_F0_1_SHIFT)) & LPDDR_DENALI_PI_282_PI_MR1_DATA_F0_1_MASK)

#define LPDDR_DENALI_PI_282_PI_MR2_DATA_F0_1_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_282_PI_MR2_DATA_F0_1_SHIFT (16U)
#define LPDDR_DENALI_PI_282_PI_MR2_DATA_F0_1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_282_PI_MR2_DATA_F0_1_SHIFT)) & LPDDR_DENALI_PI_282_PI_MR2_DATA_F0_1_MASK)

#define LPDDR_DENALI_PI_282_PI_MR3_DATA_F0_1_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_282_PI_MR3_DATA_F0_1_SHIFT (24U)
#define LPDDR_DENALI_PI_282_PI_MR3_DATA_F0_1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_282_PI_MR3_DATA_F0_1_SHIFT)) & LPDDR_DENALI_PI_282_PI_MR3_DATA_F0_1_MASK)
/*! @} */

/*! @name DENALI_PI_284 - DENALI_PI_284 */
/*! @{ */

#define LPDDR_DENALI_PI_284_PI_MR1_DATA_F1_1_MASK (0xFFU)
#define LPDDR_DENALI_PI_284_PI_MR1_DATA_F1_1_SHIFT (0U)
#define LPDDR_DENALI_PI_284_PI_MR1_DATA_F1_1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_284_PI_MR1_DATA_F1_1_SHIFT)) & LPDDR_DENALI_PI_284_PI_MR1_DATA_F1_1_MASK)

#define LPDDR_DENALI_PI_284_PI_MR2_DATA_F1_1_MASK (0xFF00U)
#define LPDDR_DENALI_PI_284_PI_MR2_DATA_F1_1_SHIFT (8U)
#define LPDDR_DENALI_PI_284_PI_MR2_DATA_F1_1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_284_PI_MR2_DATA_F1_1_SHIFT)) & LPDDR_DENALI_PI_284_PI_MR2_DATA_F1_1_MASK)

#define LPDDR_DENALI_PI_284_PI_MR3_DATA_F1_1_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_284_PI_MR3_DATA_F1_1_SHIFT (16U)
#define LPDDR_DENALI_PI_284_PI_MR3_DATA_F1_1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_284_PI_MR3_DATA_F1_1_SHIFT)) & LPDDR_DENALI_PI_284_PI_MR3_DATA_F1_1_MASK)

#define LPDDR_DENALI_PI_284_PI_MR11_DATA_F1_1_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_284_PI_MR11_DATA_F1_1_SHIFT (24U)
#define LPDDR_DENALI_PI_284_PI_MR11_DATA_F1_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_284_PI_MR11_DATA_F1_1_SHIFT)) & LPDDR_DENALI_PI_284_PI_MR11_DATA_F1_1_MASK)
/*! @} */

/*! @name DENALI_PI_285 - DENALI_PI_285 */
/*! @{ */

#define LPDDR_DENALI_PI_285_PI_MR12_DATA_F1_1_MASK (0xFFU)
#define LPDDR_DENALI_PI_285_PI_MR12_DATA_F1_1_SHIFT (0U)
#define LPDDR_DENALI_PI_285_PI_MR12_DATA_F1_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_285_PI_MR12_DATA_F1_1_SHIFT)) & LPDDR_DENALI_PI_285_PI_MR12_DATA_F1_1_MASK)

#define LPDDR_DENALI_PI_285_PI_MR14_DATA_F1_1_MASK (0xFF00U)
#define LPDDR_DENALI_PI_285_PI_MR14_DATA_F1_1_SHIFT (8U)
#define LPDDR_DENALI_PI_285_PI_MR14_DATA_F1_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_285_PI_MR14_DATA_F1_1_SHIFT)) & LPDDR_DENALI_PI_285_PI_MR14_DATA_F1_1_MASK)

#define LPDDR_DENALI_PI_285_PI_MR22_DATA_F1_1_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_285_PI_MR22_DATA_F1_1_SHIFT (16U)
#define LPDDR_DENALI_PI_285_PI_MR22_DATA_F1_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_285_PI_MR22_DATA_F1_1_SHIFT)) & LPDDR_DENALI_PI_285_PI_MR22_DATA_F1_1_MASK)

#define LPDDR_DENALI_PI_285_PI_MR1_DATA_F2_1_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_285_PI_MR1_DATA_F2_1_SHIFT (24U)
#define LPDDR_DENALI_PI_285_PI_MR1_DATA_F2_1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_285_PI_MR1_DATA_F2_1_SHIFT)) & LPDDR_DENALI_PI_285_PI_MR1_DATA_F2_1_MASK)
/*! @} */

/*! @name DENALI_PI_286 - DENALI_PI_286 */
/*! @{ */

#define LPDDR_DENALI_PI_286_PI_MR2_DATA_F2_1_MASK (0xFFU)
#define LPDDR_DENALI_PI_286_PI_MR2_DATA_F2_1_SHIFT (0U)
#define LPDDR_DENALI_PI_286_PI_MR2_DATA_F2_1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_286_PI_MR2_DATA_F2_1_SHIFT)) & LPDDR_DENALI_PI_286_PI_MR2_DATA_F2_1_MASK)

#define LPDDR_DENALI_PI_286_PI_MR3_DATA_F2_1_MASK (0xFF00U)
#define LPDDR_DENALI_PI_286_PI_MR3_DATA_F2_1_SHIFT (8U)
#define LPDDR_DENALI_PI_286_PI_MR3_DATA_F2_1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_286_PI_MR3_DATA_F2_1_SHIFT)) & LPDDR_DENALI_PI_286_PI_MR3_DATA_F2_1_MASK)

#define LPDDR_DENALI_PI_286_PI_MR11_DATA_F2_1_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_286_PI_MR11_DATA_F2_1_SHIFT (16U)
#define LPDDR_DENALI_PI_286_PI_MR11_DATA_F2_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_286_PI_MR11_DATA_F2_1_SHIFT)) & LPDDR_DENALI_PI_286_PI_MR11_DATA_F2_1_MASK)

#define LPDDR_DENALI_PI_286_PI_MR12_DATA_F2_1_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_286_PI_MR12_DATA_F2_1_SHIFT (24U)
#define LPDDR_DENALI_PI_286_PI_MR12_DATA_F2_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_286_PI_MR12_DATA_F2_1_SHIFT)) & LPDDR_DENALI_PI_286_PI_MR12_DATA_F2_1_MASK)
/*! @} */

/*! @name DENALI_PI_287 - DENALI_PI_287 */
/*! @{ */

#define LPDDR_DENALI_PI_287_PI_MR14_DATA_F2_1_MASK (0xFFU)
#define LPDDR_DENALI_PI_287_PI_MR14_DATA_F2_1_SHIFT (0U)
#define LPDDR_DENALI_PI_287_PI_MR14_DATA_F2_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_287_PI_MR14_DATA_F2_1_SHIFT)) & LPDDR_DENALI_PI_287_PI_MR14_DATA_F2_1_MASK)

#define LPDDR_DENALI_PI_287_PI_MR22_DATA_F2_1_MASK (0xFF00U)
#define LPDDR_DENALI_PI_287_PI_MR22_DATA_F2_1_SHIFT (8U)
#define LPDDR_DENALI_PI_287_PI_MR22_DATA_F2_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_287_PI_MR22_DATA_F2_1_SHIFT)) & LPDDR_DENALI_PI_287_PI_MR22_DATA_F2_1_MASK)

#define LPDDR_DENALI_PI_287_PI_MR1_DATA_F0_2_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_287_PI_MR1_DATA_F0_2_SHIFT (16U)
#define LPDDR_DENALI_PI_287_PI_MR1_DATA_F0_2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_287_PI_MR1_DATA_F0_2_SHIFT)) & LPDDR_DENALI_PI_287_PI_MR1_DATA_F0_2_MASK)

#define LPDDR_DENALI_PI_287_PI_MR2_DATA_F0_2_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_287_PI_MR2_DATA_F0_2_SHIFT (24U)
#define LPDDR_DENALI_PI_287_PI_MR2_DATA_F0_2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_287_PI_MR2_DATA_F0_2_SHIFT)) & LPDDR_DENALI_PI_287_PI_MR2_DATA_F0_2_MASK)
/*! @} */

/*! @name DENALI_PI_288 - DENALI_PI_288 */
/*! @{ */

#define LPDDR_DENALI_PI_288_PI_MR3_DATA_F0_2_MASK (0xFFU)
#define LPDDR_DENALI_PI_288_PI_MR3_DATA_F0_2_SHIFT (0U)
#define LPDDR_DENALI_PI_288_PI_MR3_DATA_F0_2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_288_PI_MR3_DATA_F0_2_SHIFT)) & LPDDR_DENALI_PI_288_PI_MR3_DATA_F0_2_MASK)

#define LPDDR_DENALI_PI_288_PI_MR11_DATA_F0_2_MASK (0xFF00U)
#define LPDDR_DENALI_PI_288_PI_MR11_DATA_F0_2_SHIFT (8U)
#define LPDDR_DENALI_PI_288_PI_MR11_DATA_F0_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_288_PI_MR11_DATA_F0_2_SHIFT)) & LPDDR_DENALI_PI_288_PI_MR11_DATA_F0_2_MASK)

#define LPDDR_DENALI_PI_288_PI_MR12_DATA_F0_2_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_288_PI_MR12_DATA_F0_2_SHIFT (16U)
#define LPDDR_DENALI_PI_288_PI_MR12_DATA_F0_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_288_PI_MR12_DATA_F0_2_SHIFT)) & LPDDR_DENALI_PI_288_PI_MR12_DATA_F0_2_MASK)

#define LPDDR_DENALI_PI_288_PI_MR14_DATA_F0_2_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_288_PI_MR14_DATA_F0_2_SHIFT (24U)
#define LPDDR_DENALI_PI_288_PI_MR14_DATA_F0_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_288_PI_MR14_DATA_F0_2_SHIFT)) & LPDDR_DENALI_PI_288_PI_MR14_DATA_F0_2_MASK)
/*! @} */

/*! @name DENALI_PI_289 - DENALI_PI_289 */
/*! @{ */

#define LPDDR_DENALI_PI_289_PI_MR22_DATA_F0_2_MASK (0xFFU)
#define LPDDR_DENALI_PI_289_PI_MR22_DATA_F0_2_SHIFT (0U)
#define LPDDR_DENALI_PI_289_PI_MR22_DATA_F0_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_289_PI_MR22_DATA_F0_2_SHIFT)) & LPDDR_DENALI_PI_289_PI_MR22_DATA_F0_2_MASK)

#define LPDDR_DENALI_PI_289_PI_MR1_DATA_F1_2_MASK (0xFF00U)
#define LPDDR_DENALI_PI_289_PI_MR1_DATA_F1_2_SHIFT (8U)
#define LPDDR_DENALI_PI_289_PI_MR1_DATA_F1_2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_289_PI_MR1_DATA_F1_2_SHIFT)) & LPDDR_DENALI_PI_289_PI_MR1_DATA_F1_2_MASK)

#define LPDDR_DENALI_PI_289_PI_MR2_DATA_F1_2_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_289_PI_MR2_DATA_F1_2_SHIFT (16U)
#define LPDDR_DENALI_PI_289_PI_MR2_DATA_F1_2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_289_PI_MR2_DATA_F1_2_SHIFT)) & LPDDR_DENALI_PI_289_PI_MR2_DATA_F1_2_MASK)

#define LPDDR_DENALI_PI_289_PI_MR3_DATA_F1_2_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_289_PI_MR3_DATA_F1_2_SHIFT (24U)
#define LPDDR_DENALI_PI_289_PI_MR3_DATA_F1_2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_289_PI_MR3_DATA_F1_2_SHIFT)) & LPDDR_DENALI_PI_289_PI_MR3_DATA_F1_2_MASK)
/*! @} */

/*! @name DENALI_PI_290 - DENALI_PI_290 */
/*! @{ */

#define LPDDR_DENALI_PI_290_PI_MR11_DATA_F1_2_MASK (0xFFU)
#define LPDDR_DENALI_PI_290_PI_MR11_DATA_F1_2_SHIFT (0U)
#define LPDDR_DENALI_PI_290_PI_MR11_DATA_F1_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_290_PI_MR11_DATA_F1_2_SHIFT)) & LPDDR_DENALI_PI_290_PI_MR11_DATA_F1_2_MASK)

#define LPDDR_DENALI_PI_290_PI_MR12_DATA_F1_2_MASK (0xFF00U)
#define LPDDR_DENALI_PI_290_PI_MR12_DATA_F1_2_SHIFT (8U)
#define LPDDR_DENALI_PI_290_PI_MR12_DATA_F1_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_290_PI_MR12_DATA_F1_2_SHIFT)) & LPDDR_DENALI_PI_290_PI_MR12_DATA_F1_2_MASK)

#define LPDDR_DENALI_PI_290_PI_MR14_DATA_F1_2_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_290_PI_MR14_DATA_F1_2_SHIFT (16U)
#define LPDDR_DENALI_PI_290_PI_MR14_DATA_F1_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_290_PI_MR14_DATA_F1_2_SHIFT)) & LPDDR_DENALI_PI_290_PI_MR14_DATA_F1_2_MASK)

#define LPDDR_DENALI_PI_290_PI_MR22_DATA_F1_2_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_290_PI_MR22_DATA_F1_2_SHIFT (24U)
#define LPDDR_DENALI_PI_290_PI_MR22_DATA_F1_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_290_PI_MR22_DATA_F1_2_SHIFT)) & LPDDR_DENALI_PI_290_PI_MR22_DATA_F1_2_MASK)
/*! @} */

/*! @name DENALI_PI_291 - DENALI_PI_291 */
/*! @{ */

#define LPDDR_DENALI_PI_291_PI_MR1_DATA_F2_2_MASK (0xFFU)
#define LPDDR_DENALI_PI_291_PI_MR1_DATA_F2_2_SHIFT (0U)
#define LPDDR_DENALI_PI_291_PI_MR1_DATA_F2_2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_291_PI_MR1_DATA_F2_2_SHIFT)) & LPDDR_DENALI_PI_291_PI_MR1_DATA_F2_2_MASK)

#define LPDDR_DENALI_PI_291_PI_MR2_DATA_F2_2_MASK (0xFF00U)
#define LPDDR_DENALI_PI_291_PI_MR2_DATA_F2_2_SHIFT (8U)
#define LPDDR_DENALI_PI_291_PI_MR2_DATA_F2_2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_291_PI_MR2_DATA_F2_2_SHIFT)) & LPDDR_DENALI_PI_291_PI_MR2_DATA_F2_2_MASK)

#define LPDDR_DENALI_PI_291_PI_MR3_DATA_F2_2_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_291_PI_MR3_DATA_F2_2_SHIFT (16U)
#define LPDDR_DENALI_PI_291_PI_MR3_DATA_F2_2(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_291_PI_MR3_DATA_F2_2_SHIFT)) & LPDDR_DENALI_PI_291_PI_MR3_DATA_F2_2_MASK)

#define LPDDR_DENALI_PI_291_PI_MR11_DATA_F2_2_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_291_PI_MR11_DATA_F2_2_SHIFT (24U)
#define LPDDR_DENALI_PI_291_PI_MR11_DATA_F2_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_291_PI_MR11_DATA_F2_2_SHIFT)) & LPDDR_DENALI_PI_291_PI_MR11_DATA_F2_2_MASK)
/*! @} */

/*! @name DENALI_PI_292 - DENALI_PI_292 */
/*! @{ */

#define LPDDR_DENALI_PI_292_PI_MR12_DATA_F2_2_MASK (0xFFU)
#define LPDDR_DENALI_PI_292_PI_MR12_DATA_F2_2_SHIFT (0U)
#define LPDDR_DENALI_PI_292_PI_MR12_DATA_F2_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_292_PI_MR12_DATA_F2_2_SHIFT)) & LPDDR_DENALI_PI_292_PI_MR12_DATA_F2_2_MASK)

#define LPDDR_DENALI_PI_292_PI_MR14_DATA_F2_2_MASK (0xFF00U)
#define LPDDR_DENALI_PI_292_PI_MR14_DATA_F2_2_SHIFT (8U)
#define LPDDR_DENALI_PI_292_PI_MR14_DATA_F2_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_292_PI_MR14_DATA_F2_2_SHIFT)) & LPDDR_DENALI_PI_292_PI_MR14_DATA_F2_2_MASK)

#define LPDDR_DENALI_PI_292_PI_MR22_DATA_F2_2_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_292_PI_MR22_DATA_F2_2_SHIFT (16U)
#define LPDDR_DENALI_PI_292_PI_MR22_DATA_F2_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_292_PI_MR22_DATA_F2_2_SHIFT)) & LPDDR_DENALI_PI_292_PI_MR22_DATA_F2_2_MASK)

#define LPDDR_DENALI_PI_292_PI_MR1_DATA_F0_3_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_292_PI_MR1_DATA_F0_3_SHIFT (24U)
#define LPDDR_DENALI_PI_292_PI_MR1_DATA_F0_3(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_292_PI_MR1_DATA_F0_3_SHIFT)) & LPDDR_DENALI_PI_292_PI_MR1_DATA_F0_3_MASK)
/*! @} */

/*! @name DENALI_PI_293 - DENALI_PI_293 */
/*! @{ */

#define LPDDR_DENALI_PI_293_PI_MR2_DATA_F0_3_MASK (0xFFU)
#define LPDDR_DENALI_PI_293_PI_MR2_DATA_F0_3_SHIFT (0U)
#define LPDDR_DENALI_PI_293_PI_MR2_DATA_F0_3(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_293_PI_MR2_DATA_F0_3_SHIFT)) & LPDDR_DENALI_PI_293_PI_MR2_DATA_F0_3_MASK)

#define LPDDR_DENALI_PI_293_PI_MR3_DATA_F0_3_MASK (0xFF00U)
#define LPDDR_DENALI_PI_293_PI_MR3_DATA_F0_3_SHIFT (8U)
#define LPDDR_DENALI_PI_293_PI_MR3_DATA_F0_3(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_293_PI_MR3_DATA_F0_3_SHIFT)) & LPDDR_DENALI_PI_293_PI_MR3_DATA_F0_3_MASK)

#define LPDDR_DENALI_PI_293_PI_MR11_DATA_F0_3_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_293_PI_MR11_DATA_F0_3_SHIFT (16U)
#define LPDDR_DENALI_PI_293_PI_MR11_DATA_F0_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_293_PI_MR11_DATA_F0_3_SHIFT)) & LPDDR_DENALI_PI_293_PI_MR11_DATA_F0_3_MASK)

#define LPDDR_DENALI_PI_293_PI_MR12_DATA_F0_3_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_293_PI_MR12_DATA_F0_3_SHIFT (24U)
#define LPDDR_DENALI_PI_293_PI_MR12_DATA_F0_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_293_PI_MR12_DATA_F0_3_SHIFT)) & LPDDR_DENALI_PI_293_PI_MR12_DATA_F0_3_MASK)
/*! @} */

/*! @name DENALI_PI_294 - DENALI_PI_294 */
/*! @{ */

#define LPDDR_DENALI_PI_294_PI_MR14_DATA_F0_3_MASK (0xFFU)
#define LPDDR_DENALI_PI_294_PI_MR14_DATA_F0_3_SHIFT (0U)
#define LPDDR_DENALI_PI_294_PI_MR14_DATA_F0_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_294_PI_MR14_DATA_F0_3_SHIFT)) & LPDDR_DENALI_PI_294_PI_MR14_DATA_F0_3_MASK)

#define LPDDR_DENALI_PI_294_PI_MR22_DATA_F0_3_MASK (0xFF00U)
#define LPDDR_DENALI_PI_294_PI_MR22_DATA_F0_3_SHIFT (8U)
#define LPDDR_DENALI_PI_294_PI_MR22_DATA_F0_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_294_PI_MR22_DATA_F0_3_SHIFT)) & LPDDR_DENALI_PI_294_PI_MR22_DATA_F0_3_MASK)

#define LPDDR_DENALI_PI_294_PI_MR1_DATA_F1_3_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_294_PI_MR1_DATA_F1_3_SHIFT (16U)
#define LPDDR_DENALI_PI_294_PI_MR1_DATA_F1_3(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_294_PI_MR1_DATA_F1_3_SHIFT)) & LPDDR_DENALI_PI_294_PI_MR1_DATA_F1_3_MASK)

#define LPDDR_DENALI_PI_294_PI_MR2_DATA_F1_3_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_294_PI_MR2_DATA_F1_3_SHIFT (24U)
#define LPDDR_DENALI_PI_294_PI_MR2_DATA_F1_3(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_294_PI_MR2_DATA_F1_3_SHIFT)) & LPDDR_DENALI_PI_294_PI_MR2_DATA_F1_3_MASK)
/*! @} */

/*! @name DENALI_PI_295 - DENALI_PI_295 */
/*! @{ */

#define LPDDR_DENALI_PI_295_PI_MR3_DATA_F1_3_MASK (0xFFU)
#define LPDDR_DENALI_PI_295_PI_MR3_DATA_F1_3_SHIFT (0U)
#define LPDDR_DENALI_PI_295_PI_MR3_DATA_F1_3(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_295_PI_MR3_DATA_F1_3_SHIFT)) & LPDDR_DENALI_PI_295_PI_MR3_DATA_F1_3_MASK)

#define LPDDR_DENALI_PI_295_PI_MR11_DATA_F1_3_MASK (0xFF00U)
#define LPDDR_DENALI_PI_295_PI_MR11_DATA_F1_3_SHIFT (8U)
#define LPDDR_DENALI_PI_295_PI_MR11_DATA_F1_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_295_PI_MR11_DATA_F1_3_SHIFT)) & LPDDR_DENALI_PI_295_PI_MR11_DATA_F1_3_MASK)

#define LPDDR_DENALI_PI_295_PI_MR12_DATA_F1_3_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_295_PI_MR12_DATA_F1_3_SHIFT (16U)
#define LPDDR_DENALI_PI_295_PI_MR12_DATA_F1_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_295_PI_MR12_DATA_F1_3_SHIFT)) & LPDDR_DENALI_PI_295_PI_MR12_DATA_F1_3_MASK)

#define LPDDR_DENALI_PI_295_PI_MR14_DATA_F1_3_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_295_PI_MR14_DATA_F1_3_SHIFT (24U)
#define LPDDR_DENALI_PI_295_PI_MR14_DATA_F1_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_295_PI_MR14_DATA_F1_3_SHIFT)) & LPDDR_DENALI_PI_295_PI_MR14_DATA_F1_3_MASK)
/*! @} */

/*! @name DENALI_PI_296 - DENALI_PI_296 */
/*! @{ */

#define LPDDR_DENALI_PI_296_PI_MR22_DATA_F1_3_MASK (0xFFU)
#define LPDDR_DENALI_PI_296_PI_MR22_DATA_F1_3_SHIFT (0U)
#define LPDDR_DENALI_PI_296_PI_MR22_DATA_F1_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_296_PI_MR22_DATA_F1_3_SHIFT)) & LPDDR_DENALI_PI_296_PI_MR22_DATA_F1_3_MASK)

#define LPDDR_DENALI_PI_296_PI_MR1_DATA_F2_3_MASK (0xFF00U)
#define LPDDR_DENALI_PI_296_PI_MR1_DATA_F2_3_SHIFT (8U)
#define LPDDR_DENALI_PI_296_PI_MR1_DATA_F2_3(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_296_PI_MR1_DATA_F2_3_SHIFT)) & LPDDR_DENALI_PI_296_PI_MR1_DATA_F2_3_MASK)

#define LPDDR_DENALI_PI_296_PI_MR2_DATA_F2_3_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_296_PI_MR2_DATA_F2_3_SHIFT (16U)
#define LPDDR_DENALI_PI_296_PI_MR2_DATA_F2_3(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_296_PI_MR2_DATA_F2_3_SHIFT)) & LPDDR_DENALI_PI_296_PI_MR2_DATA_F2_3_MASK)

#define LPDDR_DENALI_PI_296_PI_MR3_DATA_F2_3_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_296_PI_MR3_DATA_F2_3_SHIFT (24U)
#define LPDDR_DENALI_PI_296_PI_MR3_DATA_F2_3(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_296_PI_MR3_DATA_F2_3_SHIFT)) & LPDDR_DENALI_PI_296_PI_MR3_DATA_F2_3_MASK)
/*! @} */

/*! @name DENALI_PI_297 - DENALI_PI_297 */
/*! @{ */

#define LPDDR_DENALI_PI_297_PI_MR11_DATA_F2_3_MASK (0xFFU)
#define LPDDR_DENALI_PI_297_PI_MR11_DATA_F2_3_SHIFT (0U)
#define LPDDR_DENALI_PI_297_PI_MR11_DATA_F2_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_297_PI_MR11_DATA_F2_3_SHIFT)) & LPDDR_DENALI_PI_297_PI_MR11_DATA_F2_3_MASK)

#define LPDDR_DENALI_PI_297_PI_MR12_DATA_F2_3_MASK (0xFF00U)
#define LPDDR_DENALI_PI_297_PI_MR12_DATA_F2_3_SHIFT (8U)
#define LPDDR_DENALI_PI_297_PI_MR12_DATA_F2_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_297_PI_MR12_DATA_F2_3_SHIFT)) & LPDDR_DENALI_PI_297_PI_MR12_DATA_F2_3_MASK)

#define LPDDR_DENALI_PI_297_PI_MR14_DATA_F2_3_MASK (0xFF0000U)
#define LPDDR_DENALI_PI_297_PI_MR14_DATA_F2_3_SHIFT (16U)
#define LPDDR_DENALI_PI_297_PI_MR14_DATA_F2_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_297_PI_MR14_DATA_F2_3_SHIFT)) & LPDDR_DENALI_PI_297_PI_MR14_DATA_F2_3_MASK)

#define LPDDR_DENALI_PI_297_PI_MR22_DATA_F2_3_MASK (0xFF000000U)
#define LPDDR_DENALI_PI_297_PI_MR22_DATA_F2_3_SHIFT (24U)
#define LPDDR_DENALI_PI_297_PI_MR22_DATA_F2_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PI_297_PI_MR22_DATA_F2_3_SHIFT)) & LPDDR_DENALI_PI_297_PI_MR22_DATA_F2_3_MASK)
/*! @} */

/*! @name DENALI_PHY_31 - DENALI_PHY_31 */
/*! @{ */

#define LPDDR_DENALI_PHY_31_PHY_WRLVL_UPDT_WAIT_CNT_0_MASK (0xFU)
#define LPDDR_DENALI_PHY_31_PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_31_PHY_WRLVL_UPDT_WAIT_CNT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_31_PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT)) & LPDDR_DENALI_PHY_31_PHY_WRLVL_UPDT_WAIT_CNT_0_MASK)

#define LPDDR_DENALI_PHY_31_PHY_DQ_MASK_0_MASK   (0xFF00U)
#define LPDDR_DENALI_PHY_31_PHY_DQ_MASK_0_SHIFT  (8U)
#define LPDDR_DENALI_PHY_31_PHY_DQ_MASK_0(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_31_PHY_DQ_MASK_0_SHIFT)) & LPDDR_DENALI_PHY_31_PHY_DQ_MASK_0_MASK)

#define LPDDR_DENALI_PHY_31_PHY_GTLVL_CAPTURE_CNT_0_MASK (0x3F0000U)
#define LPDDR_DENALI_PHY_31_PHY_GTLVL_CAPTURE_CNT_0_SHIFT (16U)
#define LPDDR_DENALI_PHY_31_PHY_GTLVL_CAPTURE_CNT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_31_PHY_GTLVL_CAPTURE_CNT_0_SHIFT)) & LPDDR_DENALI_PHY_31_PHY_GTLVL_CAPTURE_CNT_0_MASK)

#define LPDDR_DENALI_PHY_31_PHY_GTLVL_UPDT_WAIT_CNT_0_MASK (0xF000000U)
#define LPDDR_DENALI_PHY_31_PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT (24U)
#define LPDDR_DENALI_PHY_31_PHY_GTLVL_UPDT_WAIT_CNT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_31_PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT)) & LPDDR_DENALI_PHY_31_PHY_GTLVL_UPDT_WAIT_CNT_0_MASK)
/*! @} */

/*! @name DENALI_PHY_33 - DENALI_PHY_33 */
/*! @{ */

#define LPDDR_DENALI_PHY_33_PHY_RDLVL_DATA_MASK_0_MASK (0xFFU)
#define LPDDR_DENALI_PHY_33_PHY_RDLVL_DATA_MASK_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_33_PHY_RDLVL_DATA_MASK_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_33_PHY_RDLVL_DATA_MASK_0_SHIFT)) & LPDDR_DENALI_PHY_33_PHY_RDLVL_DATA_MASK_0_MASK)

#define LPDDR_DENALI_PHY_33_PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_MASK (0xFF00U)
#define LPDDR_DENALI_PHY_33_PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_SHIFT (8U)
#define LPDDR_DENALI_PHY_33_PHY_WDQLVL_CLK_JITTER_TOLERANCE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_33_PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_SHIFT)) & LPDDR_DENALI_PHY_33_PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_MASK)

#define LPDDR_DENALI_PHY_33_PHY_WDQLVL_BURST_CNT_0_MASK (0x3F0000U)
#define LPDDR_DENALI_PHY_33_PHY_WDQLVL_BURST_CNT_0_SHIFT (16U)
/*! PHY_WDQLVL_BURST_CNT_0 - Defines the write/read burst length in bytes during the write data leveling sequence for slice 0. */
#define LPDDR_DENALI_PHY_33_PHY_WDQLVL_BURST_CNT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_33_PHY_WDQLVL_BURST_CNT_0_SHIFT)) & LPDDR_DENALI_PHY_33_PHY_WDQLVL_BURST_CNT_0_MASK)

#define LPDDR_DENALI_PHY_33_PHY_WDQLVL_PATT_0_MASK (0x7000000U)
#define LPDDR_DENALI_PHY_33_PHY_WDQLVL_PATT_0_SHIFT (24U)
#define LPDDR_DENALI_PHY_33_PHY_WDQLVL_PATT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_33_PHY_WDQLVL_PATT_0_SHIFT)) & LPDDR_DENALI_PHY_33_PHY_WDQLVL_PATT_0_MASK)
/*! @} */

/*! @name DENALI_PHY_72 - DENALI_PHY_72 */
/*! @{ */

#define LPDDR_DENALI_PHY_72_PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK (0x1U)
#define LPDDR_DENALI_PHY_72_PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_72_PHY_SLV_DLY_CTRL_GATE_DISABLE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_72_PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT)) & LPDDR_DENALI_PHY_72_PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK)

#define LPDDR_DENALI_PHY_72_PHY_RDPATH_GATE_DISABLE_0_MASK (0x100U)
#define LPDDR_DENALI_PHY_72_PHY_RDPATH_GATE_DISABLE_0_SHIFT (8U)
#define LPDDR_DENALI_PHY_72_PHY_RDPATH_GATE_DISABLE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_72_PHY_RDPATH_GATE_DISABLE_0_SHIFT)) & LPDDR_DENALI_PHY_72_PHY_RDPATH_GATE_DISABLE_0_MASK)

#define LPDDR_DENALI_PHY_72_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK (0x10000U)
#define LPDDR_DENALI_PHY_72_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT (16U)
#define LPDDR_DENALI_PHY_72_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_72_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT)) & LPDDR_DENALI_PHY_72_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK)

#define LPDDR_DENALI_PHY_72_PHY_SLICE_PWR_RDC_DISABLE_0_MASK (0x1000000U)
#define LPDDR_DENALI_PHY_72_PHY_SLICE_PWR_RDC_DISABLE_0_SHIFT (24U)
#define LPDDR_DENALI_PHY_72_PHY_SLICE_PWR_RDC_DISABLE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_72_PHY_SLICE_PWR_RDC_DISABLE_0_SHIFT)) & LPDDR_DENALI_PHY_72_PHY_SLICE_PWR_RDC_DISABLE_0_MASK)
/*! @} */

/*! @name DENALI_PHY_73 - DENALI_PHY_73 */
/*! @{ */

#define LPDDR_DENALI_PHY_73_PHY_DQ_TSEL_ENABLE_0_MASK (0x7U)
#define LPDDR_DENALI_PHY_73_PHY_DQ_TSEL_ENABLE_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_73_PHY_DQ_TSEL_ENABLE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_73_PHY_DQ_TSEL_ENABLE_0_SHIFT)) & LPDDR_DENALI_PHY_73_PHY_DQ_TSEL_ENABLE_0_MASK)

#define LPDDR_DENALI_PHY_73_PHY_DQ_TSEL_SELECT_0_MASK (0xFFFF00U)
#define LPDDR_DENALI_PHY_73_PHY_DQ_TSEL_SELECT_0_SHIFT (8U)
/*! PHY_DQ_TSEL_SELECT_0 - Operation type tsel select values for DQ/DM signals for slice 0. */
#define LPDDR_DENALI_PHY_73_PHY_DQ_TSEL_SELECT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_73_PHY_DQ_TSEL_SELECT_0_SHIFT)) & LPDDR_DENALI_PHY_73_PHY_DQ_TSEL_SELECT_0_MASK)

#define LPDDR_DENALI_PHY_73_PHY_DQS_TSEL_ENABLE_0_MASK (0x7000000U)
#define LPDDR_DENALI_PHY_73_PHY_DQS_TSEL_ENABLE_0_SHIFT (24U)
#define LPDDR_DENALI_PHY_73_PHY_DQS_TSEL_ENABLE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_73_PHY_DQS_TSEL_ENABLE_0_SHIFT)) & LPDDR_DENALI_PHY_73_PHY_DQS_TSEL_ENABLE_0_MASK)
/*! @} */

/*! @name DENALI_PHY_74 - DENALI_PHY_74 */
/*! @{ */

#define LPDDR_DENALI_PHY_74_PHY_DQS_TSEL_SELECT_0_MASK (0xFFFFU)
#define LPDDR_DENALI_PHY_74_PHY_DQS_TSEL_SELECT_0_SHIFT (0U)
/*! PHY_DQS_TSEL_SELECT_0 - Operation type tsel select values for DQS signals for slice 0. */
#define LPDDR_DENALI_PHY_74_PHY_DQS_TSEL_SELECT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_74_PHY_DQS_TSEL_SELECT_0_SHIFT)) & LPDDR_DENALI_PHY_74_PHY_DQS_TSEL_SELECT_0_MASK)

#define LPDDR_DENALI_PHY_74_PHY_TWO_CYC_PREAMBLE_0_MASK (0x30000U)
#define LPDDR_DENALI_PHY_74_PHY_TWO_CYC_PREAMBLE_0_SHIFT (16U)
#define LPDDR_DENALI_PHY_74_PHY_TWO_CYC_PREAMBLE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_74_PHY_TWO_CYC_PREAMBLE_0_SHIFT)) & LPDDR_DENALI_PHY_74_PHY_TWO_CYC_PREAMBLE_0_MASK)

#define LPDDR_DENALI_PHY_74_PHY_VREF_INITIAL_START_POINT_0_MASK (0x7F000000U)
#define LPDDR_DENALI_PHY_74_PHY_VREF_INITIAL_START_POINT_0_SHIFT (24U)
#define LPDDR_DENALI_PHY_74_PHY_VREF_INITIAL_START_POINT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_74_PHY_VREF_INITIAL_START_POINT_0_SHIFT)) & LPDDR_DENALI_PHY_74_PHY_VREF_INITIAL_START_POINT_0_MASK)
/*! @} */

/*! @name DENALI_PHY_75 - DENALI_PHY_75 */
/*! @{ */

#define LPDDR_DENALI_PHY_75_PHY_VREF_INITIAL_STOP_POINT_0_MASK (0x7FU)
#define LPDDR_DENALI_PHY_75_PHY_VREF_INITIAL_STOP_POINT_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_75_PHY_VREF_INITIAL_STOP_POINT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_75_PHY_VREF_INITIAL_STOP_POINT_0_SHIFT)) & LPDDR_DENALI_PHY_75_PHY_VREF_INITIAL_STOP_POINT_0_MASK)

#define LPDDR_DENALI_PHY_75_PHY_VREF_TRAINING_CTRL_0_MASK (0x300U)
#define LPDDR_DENALI_PHY_75_PHY_VREF_TRAINING_CTRL_0_SHIFT (8U)
#define LPDDR_DENALI_PHY_75_PHY_VREF_TRAINING_CTRL_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_75_PHY_VREF_TRAINING_CTRL_0_SHIFT)) & LPDDR_DENALI_PHY_75_PHY_VREF_TRAINING_CTRL_0_MASK)

#define LPDDR_DENALI_PHY_75_PHY_NTP_TRAIN_EN_0_MASK (0x10000U)
#define LPDDR_DENALI_PHY_75_PHY_NTP_TRAIN_EN_0_SHIFT (16U)
/*! PHY_NTP_TRAIN_EN_0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPDDR_DENALI_PHY_75_PHY_NTP_TRAIN_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_75_PHY_NTP_TRAIN_EN_0_SHIFT)) & LPDDR_DENALI_PHY_75_PHY_NTP_TRAIN_EN_0_MASK)

#define LPDDR_DENALI_PHY_75_PHY_NTP_WDQ_STEP_SIZE_0_MASK (0xFF000000U)
#define LPDDR_DENALI_PHY_75_PHY_NTP_WDQ_STEP_SIZE_0_SHIFT (24U)
#define LPDDR_DENALI_PHY_75_PHY_NTP_WDQ_STEP_SIZE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_75_PHY_NTP_WDQ_STEP_SIZE_0_SHIFT)) & LPDDR_DENALI_PHY_75_PHY_NTP_WDQ_STEP_SIZE_0_MASK)
/*! @} */

/*! @name DENALI_PHY_80 - DENALI_PHY_80 */
/*! @{ */

#define LPDDR_DENALI_PHY_80_PHY_PAD_DQS_RX_DCD_0_MASK (0x1FU)
#define LPDDR_DENALI_PHY_80_PHY_PAD_DQS_RX_DCD_0_SHIFT (0U)
/*! PHY_PAD_DQS_RX_DCD_0 - Controls RX_DCD pin for DQS pad for slice 0. */
#define LPDDR_DENALI_PHY_80_PHY_PAD_DQS_RX_DCD_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_80_PHY_PAD_DQS_RX_DCD_0_SHIFT)) & LPDDR_DENALI_PHY_80_PHY_PAD_DQS_RX_DCD_0_MASK)

#define LPDDR_DENALI_PHY_80_PHY_PAD_FDBK_RX_DCD_0_MASK (0x1F00U)
#define LPDDR_DENALI_PHY_80_PHY_PAD_FDBK_RX_DCD_0_SHIFT (8U)
/*! PHY_PAD_FDBK_RX_DCD_0 - Controls RX_DCD pin for FDBK pad for slice 0. */
#define LPDDR_DENALI_PHY_80_PHY_PAD_FDBK_RX_DCD_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_80_PHY_PAD_FDBK_RX_DCD_0_SHIFT)) & LPDDR_DENALI_PHY_80_PHY_PAD_FDBK_RX_DCD_0_MASK)

#define LPDDR_DENALI_PHY_80_PHY_PAD_DSLICE_IO_CFG_0_MASK (0x7F0000U)
#define LPDDR_DENALI_PHY_80_PHY_PAD_DSLICE_IO_CFG_0_SHIFT (16U)
/*! PHY_PAD_DSLICE_IO_CFG_0 - Controls PCLK/PARK pin for IO pad for slice 0. */
#define LPDDR_DENALI_PHY_80_PHY_PAD_DSLICE_IO_CFG_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_80_PHY_PAD_DSLICE_IO_CFG_0_SHIFT)) & LPDDR_DENALI_PHY_80_PHY_PAD_DSLICE_IO_CFG_0_MASK)
/*! @} */

/*! @name DENALI_PHY_88 - DENALI_PHY_88 */
/*! @{ */

#define LPDDR_DENALI_PHY_88_PHY_VREF_SETTING_TIME_0_MASK (0xFFFFU)
#define LPDDR_DENALI_PHY_88_PHY_VREF_SETTING_TIME_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_88_PHY_VREF_SETTING_TIME_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_88_PHY_VREF_SETTING_TIME_0_SHIFT)) & LPDDR_DENALI_PHY_88_PHY_VREF_SETTING_TIME_0_MASK)

#define LPDDR_DENALI_PHY_88_PHY_PAD_VREF_CTRL_DQ_0_MASK (0xFFF0000U)
#define LPDDR_DENALI_PHY_88_PHY_PAD_VREF_CTRL_DQ_0_SHIFT (16U)
#define LPDDR_DENALI_PHY_88_PHY_PAD_VREF_CTRL_DQ_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_88_PHY_PAD_VREF_CTRL_DQ_0_SHIFT)) & LPDDR_DENALI_PHY_88_PHY_PAD_VREF_CTRL_DQ_0_MASK)
/*! @} */

/*! @name DENALI_PHY_89 - DENALI_PHY_89 */
/*! @{ */

#define LPDDR_DENALI_PHY_89_PHY_PER_CS_TRAINING_EN_0_MASK (0x1U)
#define LPDDR_DENALI_PHY_89_PHY_PER_CS_TRAINING_EN_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_89_PHY_PER_CS_TRAINING_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_89_PHY_PER_CS_TRAINING_EN_0_SHIFT)) & LPDDR_DENALI_PHY_89_PHY_PER_CS_TRAINING_EN_0_MASK)

#define LPDDR_DENALI_PHY_89_PHY_DQ_IE_TIMING_0_MASK (0xFF00U)
#define LPDDR_DENALI_PHY_89_PHY_DQ_IE_TIMING_0_SHIFT (8U)
#define LPDDR_DENALI_PHY_89_PHY_DQ_IE_TIMING_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_89_PHY_DQ_IE_TIMING_0_SHIFT)) & LPDDR_DENALI_PHY_89_PHY_DQ_IE_TIMING_0_MASK)

#define LPDDR_DENALI_PHY_89_PHY_DQS_IE_TIMING_0_MASK (0xFF0000U)
#define LPDDR_DENALI_PHY_89_PHY_DQS_IE_TIMING_0_SHIFT (16U)
#define LPDDR_DENALI_PHY_89_PHY_DQS_IE_TIMING_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_89_PHY_DQS_IE_TIMING_0_SHIFT)) & LPDDR_DENALI_PHY_89_PHY_DQS_IE_TIMING_0_MASK)

#define LPDDR_DENALI_PHY_89_PHY_RDDATA_EN_IE_DLY_0_MASK (0x3000000U)
#define LPDDR_DENALI_PHY_89_PHY_RDDATA_EN_IE_DLY_0_SHIFT (24U)
#define LPDDR_DENALI_PHY_89_PHY_RDDATA_EN_IE_DLY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_89_PHY_RDDATA_EN_IE_DLY_0_SHIFT)) & LPDDR_DENALI_PHY_89_PHY_RDDATA_EN_IE_DLY_0_MASK)
/*! @} */

/*! @name DENALI_PHY_90 - DENALI_PHY_90 */
/*! @{ */

#define LPDDR_DENALI_PHY_90_PHY_IE_MODE_0_MASK   (0x3U)
#define LPDDR_DENALI_PHY_90_PHY_IE_MODE_0_SHIFT  (0U)
#define LPDDR_DENALI_PHY_90_PHY_IE_MODE_0(x)     (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_90_PHY_IE_MODE_0_SHIFT)) & LPDDR_DENALI_PHY_90_PHY_IE_MODE_0_MASK)

#define LPDDR_DENALI_PHY_90_PHY_DBI_MODE_0_MASK  (0x100U)
#define LPDDR_DENALI_PHY_90_PHY_DBI_MODE_0_SHIFT (8U)
/*! PHY_DBI_MODE_0
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_PHY_90_PHY_DBI_MODE_0(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_90_PHY_DBI_MODE_0_SHIFT)) & LPDDR_DENALI_PHY_90_PHY_DBI_MODE_0_MASK)

#define LPDDR_DENALI_PHY_90_PHY_RDDATA_EN_TSEL_DLY_0_MASK (0x1F0000U)
#define LPDDR_DENALI_PHY_90_PHY_RDDATA_EN_TSEL_DLY_0_SHIFT (16U)
#define LPDDR_DENALI_PHY_90_PHY_RDDATA_EN_TSEL_DLY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_90_PHY_RDDATA_EN_TSEL_DLY_0_SHIFT)) & LPDDR_DENALI_PHY_90_PHY_RDDATA_EN_TSEL_DLY_0_MASK)

#define LPDDR_DENALI_PHY_90_PHY_RDDATA_EN_OE_DLY_0_MASK (0x1F000000U)
#define LPDDR_DENALI_PHY_90_PHY_RDDATA_EN_OE_DLY_0_SHIFT (24U)
#define LPDDR_DENALI_PHY_90_PHY_RDDATA_EN_OE_DLY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_90_PHY_RDDATA_EN_OE_DLY_0_SHIFT)) & LPDDR_DENALI_PHY_90_PHY_RDDATA_EN_OE_DLY_0_MASK)
/*! @} */

/*! @name DENALI_PHY_92 - DENALI_PHY_92 */
/*! @{ */

#define LPDDR_DENALI_PHY_92_PHY_MASTER_DELAY_WAIT_0_MASK (0xFFU)
#define LPDDR_DENALI_PHY_92_PHY_MASTER_DELAY_WAIT_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_92_PHY_MASTER_DELAY_WAIT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_92_PHY_MASTER_DELAY_WAIT_0_SHIFT)) & LPDDR_DENALI_PHY_92_PHY_MASTER_DELAY_WAIT_0_MASK)

#define LPDDR_DENALI_PHY_92_PHY_MASTER_DELAY_HALF_MEASURE_0_MASK (0xFF00U)
#define LPDDR_DENALI_PHY_92_PHY_MASTER_DELAY_HALF_MEASURE_0_SHIFT (8U)
/*! PHY_MASTER_DELAY_HALF_MEASURE_0 - Defines the number of delay line elements to be considered in
 *    determing whether to lock to a half clock cycle in the data slice master for slice 0.
 */
#define LPDDR_DENALI_PHY_92_PHY_MASTER_DELAY_HALF_MEASURE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_92_PHY_MASTER_DELAY_HALF_MEASURE_0_SHIFT)) & LPDDR_DENALI_PHY_92_PHY_MASTER_DELAY_HALF_MEASURE_0_MASK)

#define LPDDR_DENALI_PHY_92_PHY_RPTR_UPDATE_0_MASK (0xF0000U)
#define LPDDR_DENALI_PHY_92_PHY_RPTR_UPDATE_0_SHIFT (16U)
#define LPDDR_DENALI_PHY_92_PHY_RPTR_UPDATE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_92_PHY_RPTR_UPDATE_0_SHIFT)) & LPDDR_DENALI_PHY_92_PHY_RPTR_UPDATE_0_MASK)

#define LPDDR_DENALI_PHY_92_PHY_WRLVL_DLY_STEP_0_MASK (0xFF000000U)
#define LPDDR_DENALI_PHY_92_PHY_WRLVL_DLY_STEP_0_SHIFT (24U)
#define LPDDR_DENALI_PHY_92_PHY_WRLVL_DLY_STEP_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_92_PHY_WRLVL_DLY_STEP_0_SHIFT)) & LPDDR_DENALI_PHY_92_PHY_WRLVL_DLY_STEP_0_MASK)
/*! @} */

/*! @name DENALI_PHY_93 - DENALI_PHY_93 */
/*! @{ */

#define LPDDR_DENALI_PHY_93_PHY_WRLVL_DLY_FINE_STEP_0_MASK (0xFU)
#define LPDDR_DENALI_PHY_93_PHY_WRLVL_DLY_FINE_STEP_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_93_PHY_WRLVL_DLY_FINE_STEP_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_93_PHY_WRLVL_DLY_FINE_STEP_0_SHIFT)) & LPDDR_DENALI_PHY_93_PHY_WRLVL_DLY_FINE_STEP_0_MASK)

#define LPDDR_DENALI_PHY_93_PHY_WRLVL_RESP_WAIT_CNT_0_MASK (0x3F00U)
#define LPDDR_DENALI_PHY_93_PHY_WRLVL_RESP_WAIT_CNT_0_SHIFT (8U)
/*! PHY_WRLVL_RESP_WAIT_CNT_0 - Defines the number of cycles to wait between dfi_wrlvl_strobe and
 *    the sampling of the DQs during write leveling for slice 0.
 */
#define LPDDR_DENALI_PHY_93_PHY_WRLVL_RESP_WAIT_CNT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_93_PHY_WRLVL_RESP_WAIT_CNT_0_SHIFT)) & LPDDR_DENALI_PHY_93_PHY_WRLVL_RESP_WAIT_CNT_0_MASK)

#define LPDDR_DENALI_PHY_93_PHY_GTLVL_DLY_STEP_0_MASK (0xF0000U)
#define LPDDR_DENALI_PHY_93_PHY_GTLVL_DLY_STEP_0_SHIFT (16U)
#define LPDDR_DENALI_PHY_93_PHY_GTLVL_DLY_STEP_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_93_PHY_GTLVL_DLY_STEP_0_SHIFT)) & LPDDR_DENALI_PHY_93_PHY_GTLVL_DLY_STEP_0_MASK)

#define LPDDR_DENALI_PHY_93_PHY_GTLVL_RESP_WAIT_CNT_0_MASK (0x1F000000U)
#define LPDDR_DENALI_PHY_93_PHY_GTLVL_RESP_WAIT_CNT_0_SHIFT (24U)
#define LPDDR_DENALI_PHY_93_PHY_GTLVL_RESP_WAIT_CNT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_93_PHY_GTLVL_RESP_WAIT_CNT_0_SHIFT)) & LPDDR_DENALI_PHY_93_PHY_GTLVL_RESP_WAIT_CNT_0_MASK)
/*! @} */

/*! @name DENALI_PHY_95 - DENALI_PHY_95 */
/*! @{ */

#define LPDDR_DENALI_PHY_95_PHY_WDQLVL_DLY_STEP_0_MASK (0xFFU)
#define LPDDR_DENALI_PHY_95_PHY_WDQLVL_DLY_STEP_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_95_PHY_WDQLVL_DLY_STEP_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_95_PHY_WDQLVL_DLY_STEP_0_SHIFT)) & LPDDR_DENALI_PHY_95_PHY_WDQLVL_DLY_STEP_0_MASK)

#define LPDDR_DENALI_PHY_95_PHY_WDQLVL_QTR_DLY_STEP_0_MASK (0xF00U)
#define LPDDR_DENALI_PHY_95_PHY_WDQLVL_QTR_DLY_STEP_0_SHIFT (8U)
#define LPDDR_DENALI_PHY_95_PHY_WDQLVL_QTR_DLY_STEP_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_95_PHY_WDQLVL_QTR_DLY_STEP_0_SHIFT)) & LPDDR_DENALI_PHY_95_PHY_WDQLVL_QTR_DLY_STEP_0_MASK)

#define LPDDR_DENALI_PHY_95_PHY_TOGGLE_PRE_SUPPORT_0_MASK (0x10000U)
#define LPDDR_DENALI_PHY_95_PHY_TOGGLE_PRE_SUPPORT_0_SHIFT (16U)
/*! PHY_TOGGLE_PRE_SUPPORT_0 - Support the toggle read preamble for LPDDR4 for slice 0.
 *  0b0..Static read preamble
 *  0b1..Toggling read preamble
 */
#define LPDDR_DENALI_PHY_95_PHY_TOGGLE_PRE_SUPPORT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_95_PHY_TOGGLE_PRE_SUPPORT_0_SHIFT)) & LPDDR_DENALI_PHY_95_PHY_TOGGLE_PRE_SUPPORT_0_MASK)

#define LPDDR_DENALI_PHY_95_PHY_RDLVL_DLY_STEP_0_MASK (0xF000000U)
#define LPDDR_DENALI_PHY_95_PHY_RDLVL_DLY_STEP_0_SHIFT (24U)
#define LPDDR_DENALI_PHY_95_PHY_RDLVL_DLY_STEP_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_95_PHY_RDLVL_DLY_STEP_0_SHIFT)) & LPDDR_DENALI_PHY_95_PHY_RDLVL_DLY_STEP_0_MASK)
/*! @} */

/*! @name DENALI_PHY_96 - DENALI_PHY_96 */
/*! @{ */

#define LPDDR_DENALI_PHY_96_PHY_RDLVL_MAX_EDGE_0_MASK (0x3FFU)
#define LPDDR_DENALI_PHY_96_PHY_RDLVL_MAX_EDGE_0_SHIFT (0U)
/*! PHY_RDLVL_MAX_EDGE_0 - Provides the maximun rdlvl slave delay search window for read eye training for slice 0. */
#define LPDDR_DENALI_PHY_96_PHY_RDLVL_MAX_EDGE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_96_PHY_RDLVL_MAX_EDGE_0_SHIFT)) & LPDDR_DENALI_PHY_96_PHY_RDLVL_MAX_EDGE_0_MASK)
/*! @} */

/*! @name DENALI_PHY_97 - DENALI_PHY_97 */
/*! @{ */

#define LPDDR_DENALI_PHY_97_PHY_WRPATH_GATE_DISABLE_0_MASK (0x3U)
#define LPDDR_DENALI_PHY_97_PHY_WRPATH_GATE_DISABLE_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_97_PHY_WRPATH_GATE_DISABLE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_97_PHY_WRPATH_GATE_DISABLE_0_SHIFT)) & LPDDR_DENALI_PHY_97_PHY_WRPATH_GATE_DISABLE_0_MASK)

#define LPDDR_DENALI_PHY_97_PHY_WRPATH_GATE_TIMING_0_MASK (0x700U)
#define LPDDR_DENALI_PHY_97_PHY_WRPATH_GATE_TIMING_0_SHIFT (8U)
#define LPDDR_DENALI_PHY_97_PHY_WRPATH_GATE_TIMING_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_97_PHY_WRPATH_GATE_TIMING_0_SHIFT)) & LPDDR_DENALI_PHY_97_PHY_WRPATH_GATE_TIMING_0_MASK)

#define LPDDR_DENALI_PHY_97_PHY_MEAS_DLY_STEP_ENABLE_0_MASK (0x3F0000U)
#define LPDDR_DENALI_PHY_97_PHY_MEAS_DLY_STEP_ENABLE_0_SHIFT (16U)
/*! PHY_MEAS_DLY_STEP_ENABLE_0 - Data slice training step definition using phy_meas_dly_step_value for slice 0. */
#define LPDDR_DENALI_PHY_97_PHY_MEAS_DLY_STEP_ENABLE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_97_PHY_MEAS_DLY_STEP_ENABLE_0_SHIFT)) & LPDDR_DENALI_PHY_97_PHY_MEAS_DLY_STEP_ENABLE_0_MASK)

#define LPDDR_DENALI_PHY_97_PHY_RDDATA_EN_DLY_0_MASK (0x1F000000U)
#define LPDDR_DENALI_PHY_97_PHY_RDDATA_EN_DLY_0_SHIFT (24U)
#define LPDDR_DENALI_PHY_97_PHY_RDDATA_EN_DLY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_97_PHY_RDDATA_EN_DLY_0_SHIFT)) & LPDDR_DENALI_PHY_97_PHY_RDDATA_EN_DLY_0_MASK)
/*! @} */

/*! @name DENALI_PHY_98 - DENALI_PHY_98 */
/*! @{ */

#define LPDDR_DENALI_PHY_98_PHY_DQ_DM_SWIZZLE0_0_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_PHY_98_PHY_DQ_DM_SWIZZLE0_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_98_PHY_DQ_DM_SWIZZLE0_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_98_PHY_DQ_DM_SWIZZLE0_0_SHIFT)) & LPDDR_DENALI_PHY_98_PHY_DQ_DM_SWIZZLE0_0_MASK)
/*! @} */

/*! @name DENALI_PHY_100 - DENALI_PHY_100 */
/*! @{ */

#define LPDDR_DENALI_PHY_100_PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_100_PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT (0U)
/*! PHY_CLK_WRDQ0_SLAVE_DELAY_0 - Write clock slave delay setting for DQ0 for slice 0. */
#define LPDDR_DENALI_PHY_100_PHY_CLK_WRDQ0_SLAVE_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_100_PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT)) & LPDDR_DENALI_PHY_100_PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK)

#define LPDDR_DENALI_PHY_100_PHY_CLK_WRDQ1_SLAVE_DELAY_0_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_100_PHY_CLK_WRDQ1_SLAVE_DELAY_0_SHIFT (16U)
#define LPDDR_DENALI_PHY_100_PHY_CLK_WRDQ1_SLAVE_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_100_PHY_CLK_WRDQ1_SLAVE_DELAY_0_SHIFT)) & LPDDR_DENALI_PHY_100_PHY_CLK_WRDQ1_SLAVE_DELAY_0_MASK)
/*! @} */

/*! @name DENALI_PHY_101 - DENALI_PHY_101 */
/*! @{ */

#define LPDDR_DENALI_PHY_101_PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_101_PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT (0U)
/*! PHY_CLK_WRDQ2_SLAVE_DELAY_0 - Write clock slave delay setting for DQ2 for slice 0. */
#define LPDDR_DENALI_PHY_101_PHY_CLK_WRDQ2_SLAVE_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_101_PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT)) & LPDDR_DENALI_PHY_101_PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK)

#define LPDDR_DENALI_PHY_101_PHY_CLK_WRDQ3_SLAVE_DELAY_0_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_101_PHY_CLK_WRDQ3_SLAVE_DELAY_0_SHIFT (16U)
/*! PHY_CLK_WRDQ3_SLAVE_DELAY_0 - Write clock slave delay setting for DQ3 for slice 0. */
#define LPDDR_DENALI_PHY_101_PHY_CLK_WRDQ3_SLAVE_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_101_PHY_CLK_WRDQ3_SLAVE_DELAY_0_SHIFT)) & LPDDR_DENALI_PHY_101_PHY_CLK_WRDQ3_SLAVE_DELAY_0_MASK)
/*! @} */

/*! @name DENALI_PHY_102 - DENALI_PHY_102 */
/*! @{ */

#define LPDDR_DENALI_PHY_102_PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_102_PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT (0U)
/*! PHY_CLK_WRDQ4_SLAVE_DELAY_0 - Write clock slave delay setting for DQ4 for slice 0. */
#define LPDDR_DENALI_PHY_102_PHY_CLK_WRDQ4_SLAVE_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_102_PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT)) & LPDDR_DENALI_PHY_102_PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK)

#define LPDDR_DENALI_PHY_102_PHY_CLK_WRDQ5_SLAVE_DELAY_0_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_102_PHY_CLK_WRDQ5_SLAVE_DELAY_0_SHIFT (16U)
/*! PHY_CLK_WRDQ5_SLAVE_DELAY_0 - Write clock slave delay setting for DQ5 for slice 0. */
#define LPDDR_DENALI_PHY_102_PHY_CLK_WRDQ5_SLAVE_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_102_PHY_CLK_WRDQ5_SLAVE_DELAY_0_SHIFT)) & LPDDR_DENALI_PHY_102_PHY_CLK_WRDQ5_SLAVE_DELAY_0_MASK)
/*! @} */

/*! @name DENALI_PHY_103 - DENALI_PHY_103 */
/*! @{ */

#define LPDDR_DENALI_PHY_103_PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_103_PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT (0U)
/*! PHY_CLK_WRDQ6_SLAVE_DELAY_0 - Write clock slave delay setting for DQ6 for slice 0. */
#define LPDDR_DENALI_PHY_103_PHY_CLK_WRDQ6_SLAVE_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_103_PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT)) & LPDDR_DENALI_PHY_103_PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK)

#define LPDDR_DENALI_PHY_103_PHY_CLK_WRDQ7_SLAVE_DELAY_0_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_103_PHY_CLK_WRDQ7_SLAVE_DELAY_0_SHIFT (16U)
/*! PHY_CLK_WRDQ7_SLAVE_DELAY_0 - Write clock slave delay setting for DQ7 for slice 0. */
#define LPDDR_DENALI_PHY_103_PHY_CLK_WRDQ7_SLAVE_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_103_PHY_CLK_WRDQ7_SLAVE_DELAY_0_SHIFT)) & LPDDR_DENALI_PHY_103_PHY_CLK_WRDQ7_SLAVE_DELAY_0_MASK)
/*! @} */

/*! @name DENALI_PHY_104 - DENALI_PHY_104 */
/*! @{ */

#define LPDDR_DENALI_PHY_104_PHY_CLK_WRDM_SLAVE_DELAY_0_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_104_PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT (0U)
/*! PHY_CLK_WRDM_SLAVE_DELAY_0 - Write clock slave delay setting for DM for slice 0. */
#define LPDDR_DENALI_PHY_104_PHY_CLK_WRDM_SLAVE_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_104_PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT)) & LPDDR_DENALI_PHY_104_PHY_CLK_WRDM_SLAVE_DELAY_0_MASK)

#define LPDDR_DENALI_PHY_104_PHY_CLK_WRDQS_SLAVE_DELAY_0_MASK (0x3FF0000U)
#define LPDDR_DENALI_PHY_104_PHY_CLK_WRDQS_SLAVE_DELAY_0_SHIFT (16U)
/*! PHY_CLK_WRDQS_SLAVE_DELAY_0 - Write clock slave delay setting for DQS for slice 0. */
#define LPDDR_DENALI_PHY_104_PHY_CLK_WRDQS_SLAVE_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_104_PHY_CLK_WRDQS_SLAVE_DELAY_0_SHIFT)) & LPDDR_DENALI_PHY_104_PHY_CLK_WRDQS_SLAVE_DELAY_0_MASK)
/*! @} */

/*! @name DENALI_PHY_114 - DENALI_PHY_114 */
/*! @{ */

#define LPDDR_DENALI_PHY_114_PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK (0x3FFU)
#define LPDDR_DENALI_PHY_114_PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT (0U)
/*! PHY_RDDQS_DM_FALL_SLAVE_DELAY_0 - Falling edge read DQS slave delay setting for DM for slice 0. */
#define LPDDR_DENALI_PHY_114_PHY_RDDQS_DM_FALL_SLAVE_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_114_PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT)) & LPDDR_DENALI_PHY_114_PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK)

#define LPDDR_DENALI_PHY_114_PHY_RDDQS_GATE_SLAVE_DELAY_0_MASK (0x3FF0000U)
#define LPDDR_DENALI_PHY_114_PHY_RDDQS_GATE_SLAVE_DELAY_0_SHIFT (16U)
/*! PHY_RDDQS_GATE_SLAVE_DELAY_0 - Read DQS slave delay setting for slice 0. */
#define LPDDR_DENALI_PHY_114_PHY_RDDQS_GATE_SLAVE_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_114_PHY_RDDQS_GATE_SLAVE_DELAY_0_SHIFT)) & LPDDR_DENALI_PHY_114_PHY_RDDQS_GATE_SLAVE_DELAY_0_MASK)
/*! @} */

/*! @name DENALI_PHY_287 - DENALI_PHY_287 */
/*! @{ */

#define LPDDR_DENALI_PHY_287_PHY_WRLVL_UPDT_WAIT_CNT_1_MASK (0xFU)
#define LPDDR_DENALI_PHY_287_PHY_WRLVL_UPDT_WAIT_CNT_1_SHIFT (0U)
#define LPDDR_DENALI_PHY_287_PHY_WRLVL_UPDT_WAIT_CNT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_287_PHY_WRLVL_UPDT_WAIT_CNT_1_SHIFT)) & LPDDR_DENALI_PHY_287_PHY_WRLVL_UPDT_WAIT_CNT_1_MASK)

#define LPDDR_DENALI_PHY_287_PHY_DQ_MASK_1_MASK  (0xFF00U)
#define LPDDR_DENALI_PHY_287_PHY_DQ_MASK_1_SHIFT (8U)
#define LPDDR_DENALI_PHY_287_PHY_DQ_MASK_1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_287_PHY_DQ_MASK_1_SHIFT)) & LPDDR_DENALI_PHY_287_PHY_DQ_MASK_1_MASK)

#define LPDDR_DENALI_PHY_287_PHY_GTLVL_CAPTURE_CNT_1_MASK (0x3F0000U)
#define LPDDR_DENALI_PHY_287_PHY_GTLVL_CAPTURE_CNT_1_SHIFT (16U)
#define LPDDR_DENALI_PHY_287_PHY_GTLVL_CAPTURE_CNT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_287_PHY_GTLVL_CAPTURE_CNT_1_SHIFT)) & LPDDR_DENALI_PHY_287_PHY_GTLVL_CAPTURE_CNT_1_MASK)

#define LPDDR_DENALI_PHY_287_PHY_GTLVL_UPDT_WAIT_CNT_1_MASK (0xF000000U)
#define LPDDR_DENALI_PHY_287_PHY_GTLVL_UPDT_WAIT_CNT_1_SHIFT (24U)
#define LPDDR_DENALI_PHY_287_PHY_GTLVL_UPDT_WAIT_CNT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_287_PHY_GTLVL_UPDT_WAIT_CNT_1_SHIFT)) & LPDDR_DENALI_PHY_287_PHY_GTLVL_UPDT_WAIT_CNT_1_MASK)
/*! @} */

/*! @name DENALI_PHY_289 - DENALI_PHY_289 */
/*! @{ */

#define LPDDR_DENALI_PHY_289_PHY_RDLVL_DATA_MASK_1_MASK (0xFFU)
#define LPDDR_DENALI_PHY_289_PHY_RDLVL_DATA_MASK_1_SHIFT (0U)
#define LPDDR_DENALI_PHY_289_PHY_RDLVL_DATA_MASK_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_289_PHY_RDLVL_DATA_MASK_1_SHIFT)) & LPDDR_DENALI_PHY_289_PHY_RDLVL_DATA_MASK_1_MASK)

#define LPDDR_DENALI_PHY_289_PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_MASK (0xFF00U)
#define LPDDR_DENALI_PHY_289_PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_SHIFT (8U)
#define LPDDR_DENALI_PHY_289_PHY_WDQLVL_CLK_JITTER_TOLERANCE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_289_PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_SHIFT)) & LPDDR_DENALI_PHY_289_PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_MASK)

#define LPDDR_DENALI_PHY_289_PHY_WDQLVL_BURST_CNT_1_MASK (0x3F0000U)
#define LPDDR_DENALI_PHY_289_PHY_WDQLVL_BURST_CNT_1_SHIFT (16U)
/*! PHY_WDQLVL_BURST_CNT_1 - Defines the write/read burst length in bytes during the write data leveling sequence for slice 1. */
#define LPDDR_DENALI_PHY_289_PHY_WDQLVL_BURST_CNT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_289_PHY_WDQLVL_BURST_CNT_1_SHIFT)) & LPDDR_DENALI_PHY_289_PHY_WDQLVL_BURST_CNT_1_MASK)

#define LPDDR_DENALI_PHY_289_PHY_WDQLVL_PATT_1_MASK (0x7000000U)
#define LPDDR_DENALI_PHY_289_PHY_WDQLVL_PATT_1_SHIFT (24U)
#define LPDDR_DENALI_PHY_289_PHY_WDQLVL_PATT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_289_PHY_WDQLVL_PATT_1_SHIFT)) & LPDDR_DENALI_PHY_289_PHY_WDQLVL_PATT_1_MASK)
/*! @} */

/*! @name DENALI_PHY_328 - DENALI_PHY_328 */
/*! @{ */

#define LPDDR_DENALI_PHY_328_PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK (0x1U)
#define LPDDR_DENALI_PHY_328_PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT (0U)
#define LPDDR_DENALI_PHY_328_PHY_SLV_DLY_CTRL_GATE_DISABLE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_328_PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT)) & LPDDR_DENALI_PHY_328_PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK)

#define LPDDR_DENALI_PHY_328_PHY_RDPATH_GATE_DISABLE_1_MASK (0x100U)
#define LPDDR_DENALI_PHY_328_PHY_RDPATH_GATE_DISABLE_1_SHIFT (8U)
#define LPDDR_DENALI_PHY_328_PHY_RDPATH_GATE_DISABLE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_328_PHY_RDPATH_GATE_DISABLE_1_SHIFT)) & LPDDR_DENALI_PHY_328_PHY_RDPATH_GATE_DISABLE_1_MASK)

#define LPDDR_DENALI_PHY_328_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK (0x10000U)
#define LPDDR_DENALI_PHY_328_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT (16U)
#define LPDDR_DENALI_PHY_328_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_328_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT)) & LPDDR_DENALI_PHY_328_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK)

#define LPDDR_DENALI_PHY_328_PHY_SLICE_PWR_RDC_DISABLE_1_MASK (0x1000000U)
#define LPDDR_DENALI_PHY_328_PHY_SLICE_PWR_RDC_DISABLE_1_SHIFT (24U)
#define LPDDR_DENALI_PHY_328_PHY_SLICE_PWR_RDC_DISABLE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_328_PHY_SLICE_PWR_RDC_DISABLE_1_SHIFT)) & LPDDR_DENALI_PHY_328_PHY_SLICE_PWR_RDC_DISABLE_1_MASK)
/*! @} */

/*! @name DENALI_PHY_329 - DENALI_PHY_329 */
/*! @{ */

#define LPDDR_DENALI_PHY_329_PHY_DQ_TSEL_ENABLE_1_MASK (0x7U)
#define LPDDR_DENALI_PHY_329_PHY_DQ_TSEL_ENABLE_1_SHIFT (0U)
#define LPDDR_DENALI_PHY_329_PHY_DQ_TSEL_ENABLE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_329_PHY_DQ_TSEL_ENABLE_1_SHIFT)) & LPDDR_DENALI_PHY_329_PHY_DQ_TSEL_ENABLE_1_MASK)

#define LPDDR_DENALI_PHY_329_PHY_DQ_TSEL_SELECT_1_MASK (0xFFFF00U)
#define LPDDR_DENALI_PHY_329_PHY_DQ_TSEL_SELECT_1_SHIFT (8U)
/*! PHY_DQ_TSEL_SELECT_1 - Operation type tsel select values for DQ/DM signals for slice 1. */
#define LPDDR_DENALI_PHY_329_PHY_DQ_TSEL_SELECT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_329_PHY_DQ_TSEL_SELECT_1_SHIFT)) & LPDDR_DENALI_PHY_329_PHY_DQ_TSEL_SELECT_1_MASK)

#define LPDDR_DENALI_PHY_329_PHY_DQS_TSEL_ENABLE_1_MASK (0x7000000U)
#define LPDDR_DENALI_PHY_329_PHY_DQS_TSEL_ENABLE_1_SHIFT (24U)
#define LPDDR_DENALI_PHY_329_PHY_DQS_TSEL_ENABLE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_329_PHY_DQS_TSEL_ENABLE_1_SHIFT)) & LPDDR_DENALI_PHY_329_PHY_DQS_TSEL_ENABLE_1_MASK)
/*! @} */

/*! @name DENALI_PHY_330 - DENALI_PHY_330 */
/*! @{ */

#define LPDDR_DENALI_PHY_330_PHY_DQS_TSEL_SELECT_1_MASK (0xFFFFU)
#define LPDDR_DENALI_PHY_330_PHY_DQS_TSEL_SELECT_1_SHIFT (0U)
/*! PHY_DQS_TSEL_SELECT_1 - Operation type tsel select values for DQS signals for slice 1. */
#define LPDDR_DENALI_PHY_330_PHY_DQS_TSEL_SELECT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_330_PHY_DQS_TSEL_SELECT_1_SHIFT)) & LPDDR_DENALI_PHY_330_PHY_DQS_TSEL_SELECT_1_MASK)

#define LPDDR_DENALI_PHY_330_PHY_TWO_CYC_PREAMBLE_1_MASK (0x30000U)
#define LPDDR_DENALI_PHY_330_PHY_TWO_CYC_PREAMBLE_1_SHIFT (16U)
#define LPDDR_DENALI_PHY_330_PHY_TWO_CYC_PREAMBLE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_330_PHY_TWO_CYC_PREAMBLE_1_SHIFT)) & LPDDR_DENALI_PHY_330_PHY_TWO_CYC_PREAMBLE_1_MASK)

#define LPDDR_DENALI_PHY_330_PHY_VREF_INITIAL_START_POINT_1_MASK (0x7F000000U)
#define LPDDR_DENALI_PHY_330_PHY_VREF_INITIAL_START_POINT_1_SHIFT (24U)
#define LPDDR_DENALI_PHY_330_PHY_VREF_INITIAL_START_POINT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_330_PHY_VREF_INITIAL_START_POINT_1_SHIFT)) & LPDDR_DENALI_PHY_330_PHY_VREF_INITIAL_START_POINT_1_MASK)
/*! @} */

/*! @name DENALI_PHY_331 - DENALI_PHY_331 */
/*! @{ */

#define LPDDR_DENALI_PHY_331_PHY_VREF_INITIAL_STOP_POINT_1_MASK (0x7FU)
#define LPDDR_DENALI_PHY_331_PHY_VREF_INITIAL_STOP_POINT_1_SHIFT (0U)
/*! PHY_VREF_INITIAL_STOP_POINT_1 - Data slice initial VREF training stop value for slice 1. When
 *    programming the write DQ VREF stop point parameter, must set it equal to a multiple of the VREF
 *    (step size + start point).
 */
#define LPDDR_DENALI_PHY_331_PHY_VREF_INITIAL_STOP_POINT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_331_PHY_VREF_INITIAL_STOP_POINT_1_SHIFT)) & LPDDR_DENALI_PHY_331_PHY_VREF_INITIAL_STOP_POINT_1_MASK)

#define LPDDR_DENALI_PHY_331_PHY_VREF_TRAINING_CTRL_1_MASK (0x300U)
#define LPDDR_DENALI_PHY_331_PHY_VREF_TRAINING_CTRL_1_SHIFT (8U)
#define LPDDR_DENALI_PHY_331_PHY_VREF_TRAINING_CTRL_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_331_PHY_VREF_TRAINING_CTRL_1_SHIFT)) & LPDDR_DENALI_PHY_331_PHY_VREF_TRAINING_CTRL_1_MASK)

#define LPDDR_DENALI_PHY_331_PHY_NTP_TRAIN_EN_1_MASK (0x10000U)
#define LPDDR_DENALI_PHY_331_PHY_NTP_TRAIN_EN_1_SHIFT (16U)
/*! PHY_NTP_TRAIN_EN_1
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPDDR_DENALI_PHY_331_PHY_NTP_TRAIN_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_331_PHY_NTP_TRAIN_EN_1_SHIFT)) & LPDDR_DENALI_PHY_331_PHY_NTP_TRAIN_EN_1_MASK)

#define LPDDR_DENALI_PHY_331_PHY_NTP_WDQ_STEP_SIZE_1_MASK (0xFF000000U)
#define LPDDR_DENALI_PHY_331_PHY_NTP_WDQ_STEP_SIZE_1_SHIFT (24U)
#define LPDDR_DENALI_PHY_331_PHY_NTP_WDQ_STEP_SIZE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_331_PHY_NTP_WDQ_STEP_SIZE_1_SHIFT)) & LPDDR_DENALI_PHY_331_PHY_NTP_WDQ_STEP_SIZE_1_MASK)
/*! @} */

/*! @name DENALI_PHY_336 - DENALI_PHY_336 */
/*! @{ */

#define LPDDR_DENALI_PHY_336_PHY_PAD_DQS_RX_DCD_1_MASK (0x1FU)
#define LPDDR_DENALI_PHY_336_PHY_PAD_DQS_RX_DCD_1_SHIFT (0U)
/*! PHY_PAD_DQS_RX_DCD_1 - Controls RX_DCD pin for dqs pad for slice 1. */
#define LPDDR_DENALI_PHY_336_PHY_PAD_DQS_RX_DCD_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_336_PHY_PAD_DQS_RX_DCD_1_SHIFT)) & LPDDR_DENALI_PHY_336_PHY_PAD_DQS_RX_DCD_1_MASK)

#define LPDDR_DENALI_PHY_336_PHY_PAD_FDBK_RX_DCD_1_MASK (0x1F00U)
#define LPDDR_DENALI_PHY_336_PHY_PAD_FDBK_RX_DCD_1_SHIFT (8U)
/*! PHY_PAD_FDBK_RX_DCD_1 - Controls RX_DCD pin for fdbk pad for slice 1. */
#define LPDDR_DENALI_PHY_336_PHY_PAD_FDBK_RX_DCD_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_336_PHY_PAD_FDBK_RX_DCD_1_SHIFT)) & LPDDR_DENALI_PHY_336_PHY_PAD_FDBK_RX_DCD_1_MASK)

#define LPDDR_DENALI_PHY_336_PHY_PAD_DSLICE_IO_CFG_1_MASK (0x7F0000U)
#define LPDDR_DENALI_PHY_336_PHY_PAD_DSLICE_IO_CFG_1_SHIFT (16U)
/*! PHY_PAD_DSLICE_IO_CFG_1 - Controls PCLK/PARK pin for IO pad for slice 1. */
#define LPDDR_DENALI_PHY_336_PHY_PAD_DSLICE_IO_CFG_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_336_PHY_PAD_DSLICE_IO_CFG_1_SHIFT)) & LPDDR_DENALI_PHY_336_PHY_PAD_DSLICE_IO_CFG_1_MASK)
/*! @} */

/*! @name DENALI_PHY_344 - DENALI_PHY_344 */
/*! @{ */

#define LPDDR_DENALI_PHY_344_PHY_VREF_SETTING_TIME_1_MASK (0xFFFFU)
#define LPDDR_DENALI_PHY_344_PHY_VREF_SETTING_TIME_1_SHIFT (0U)
#define LPDDR_DENALI_PHY_344_PHY_VREF_SETTING_TIME_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_344_PHY_VREF_SETTING_TIME_1_SHIFT)) & LPDDR_DENALI_PHY_344_PHY_VREF_SETTING_TIME_1_MASK)

#define LPDDR_DENALI_PHY_344_PHY_PAD_VREF_CTRL_DQ_1_MASK (0xFFF0000U)
#define LPDDR_DENALI_PHY_344_PHY_PAD_VREF_CTRL_DQ_1_SHIFT (16U)
#define LPDDR_DENALI_PHY_344_PHY_PAD_VREF_CTRL_DQ_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_344_PHY_PAD_VREF_CTRL_DQ_1_SHIFT)) & LPDDR_DENALI_PHY_344_PHY_PAD_VREF_CTRL_DQ_1_MASK)
/*! @} */

/*! @name DENALI_PHY_345 - DENALI_PHY_345 */
/*! @{ */

#define LPDDR_DENALI_PHY_345_PHY_PER_CS_TRAINING_EN_1_MASK (0x1U)
#define LPDDR_DENALI_PHY_345_PHY_PER_CS_TRAINING_EN_1_SHIFT (0U)
#define LPDDR_DENALI_PHY_345_PHY_PER_CS_TRAINING_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_345_PHY_PER_CS_TRAINING_EN_1_SHIFT)) & LPDDR_DENALI_PHY_345_PHY_PER_CS_TRAINING_EN_1_MASK)

#define LPDDR_DENALI_PHY_345_PHY_DQ_IE_TIMING_1_MASK (0xFF00U)
#define LPDDR_DENALI_PHY_345_PHY_DQ_IE_TIMING_1_SHIFT (8U)
#define LPDDR_DENALI_PHY_345_PHY_DQ_IE_TIMING_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_345_PHY_DQ_IE_TIMING_1_SHIFT)) & LPDDR_DENALI_PHY_345_PHY_DQ_IE_TIMING_1_MASK)

#define LPDDR_DENALI_PHY_345_PHY_DQS_IE_TIMING_1_MASK (0xFF0000U)
#define LPDDR_DENALI_PHY_345_PHY_DQS_IE_TIMING_1_SHIFT (16U)
#define LPDDR_DENALI_PHY_345_PHY_DQS_IE_TIMING_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_345_PHY_DQS_IE_TIMING_1_SHIFT)) & LPDDR_DENALI_PHY_345_PHY_DQS_IE_TIMING_1_MASK)

#define LPDDR_DENALI_PHY_345_PHY_RDDATA_EN_IE_DLY_1_MASK (0x3000000U)
#define LPDDR_DENALI_PHY_345_PHY_RDDATA_EN_IE_DLY_1_SHIFT (24U)
#define LPDDR_DENALI_PHY_345_PHY_RDDATA_EN_IE_DLY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_345_PHY_RDDATA_EN_IE_DLY_1_SHIFT)) & LPDDR_DENALI_PHY_345_PHY_RDDATA_EN_IE_DLY_1_MASK)
/*! @} */

/*! @name DENALI_PHY_346 - DENALI_PHY_346 */
/*! @{ */

#define LPDDR_DENALI_PHY_346_PHY_IE_MODE_1_MASK  (0x3U)
#define LPDDR_DENALI_PHY_346_PHY_IE_MODE_1_SHIFT (0U)
#define LPDDR_DENALI_PHY_346_PHY_IE_MODE_1(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_346_PHY_IE_MODE_1_SHIFT)) & LPDDR_DENALI_PHY_346_PHY_IE_MODE_1_MASK)

#define LPDDR_DENALI_PHY_346_PHY_DBI_MODE_1_MASK (0x100U)
#define LPDDR_DENALI_PHY_346_PHY_DBI_MODE_1_SHIFT (8U)
/*! PHY_DBI_MODE_1
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_PHY_346_PHY_DBI_MODE_1(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_346_PHY_DBI_MODE_1_SHIFT)) & LPDDR_DENALI_PHY_346_PHY_DBI_MODE_1_MASK)

#define LPDDR_DENALI_PHY_346_PHY_RDDATA_EN_TSEL_DLY_1_MASK (0x1F0000U)
#define LPDDR_DENALI_PHY_346_PHY_RDDATA_EN_TSEL_DLY_1_SHIFT (16U)
#define LPDDR_DENALI_PHY_346_PHY_RDDATA_EN_TSEL_DLY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_346_PHY_RDDATA_EN_TSEL_DLY_1_SHIFT)) & LPDDR_DENALI_PHY_346_PHY_RDDATA_EN_TSEL_DLY_1_MASK)

#define LPDDR_DENALI_PHY_346_PHY_RDDATA_EN_OE_DLY_1_MASK (0x1F000000U)
#define LPDDR_DENALI_PHY_346_PHY_RDDATA_EN_OE_DLY_1_SHIFT (24U)
#define LPDDR_DENALI_PHY_346_PHY_RDDATA_EN_OE_DLY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_346_PHY_RDDATA_EN_OE_DLY_1_SHIFT)) & LPDDR_DENALI_PHY_346_PHY_RDDATA_EN_OE_DLY_1_MASK)
/*! @} */

/*! @name DENALI_PHY_348 - DENALI_PHY_348 */
/*! @{ */

#define LPDDR_DENALI_PHY_348_PHY_MASTER_DELAY_WAIT_1_MASK (0xFFU)
#define LPDDR_DENALI_PHY_348_PHY_MASTER_DELAY_WAIT_1_SHIFT (0U)
#define LPDDR_DENALI_PHY_348_PHY_MASTER_DELAY_WAIT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_348_PHY_MASTER_DELAY_WAIT_1_SHIFT)) & LPDDR_DENALI_PHY_348_PHY_MASTER_DELAY_WAIT_1_MASK)

#define LPDDR_DENALI_PHY_348_PHY_MASTER_DELAY_HALF_MEASURE_1_MASK (0xFF00U)
#define LPDDR_DENALI_PHY_348_PHY_MASTER_DELAY_HALF_MEASURE_1_SHIFT (8U)
/*! PHY_MASTER_DELAY_HALF_MEASURE_1 - Defines the number of delay line elements to be considered in
 *    determing whether to lock to a half clock cycle in the data slice master for slice 1.
 */
#define LPDDR_DENALI_PHY_348_PHY_MASTER_DELAY_HALF_MEASURE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_348_PHY_MASTER_DELAY_HALF_MEASURE_1_SHIFT)) & LPDDR_DENALI_PHY_348_PHY_MASTER_DELAY_HALF_MEASURE_1_MASK)

#define LPDDR_DENALI_PHY_348_PHY_RPTR_UPDATE_1_MASK (0xF0000U)
#define LPDDR_DENALI_PHY_348_PHY_RPTR_UPDATE_1_SHIFT (16U)
#define LPDDR_DENALI_PHY_348_PHY_RPTR_UPDATE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_348_PHY_RPTR_UPDATE_1_SHIFT)) & LPDDR_DENALI_PHY_348_PHY_RPTR_UPDATE_1_MASK)

#define LPDDR_DENALI_PHY_348_PHY_WRLVL_DLY_STEP_1_MASK (0xFF000000U)
#define LPDDR_DENALI_PHY_348_PHY_WRLVL_DLY_STEP_1_SHIFT (24U)
#define LPDDR_DENALI_PHY_348_PHY_WRLVL_DLY_STEP_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_348_PHY_WRLVL_DLY_STEP_1_SHIFT)) & LPDDR_DENALI_PHY_348_PHY_WRLVL_DLY_STEP_1_MASK)
/*! @} */

/*! @name DENALI_PHY_349 - DENALI_PHY_349 */
/*! @{ */

#define LPDDR_DENALI_PHY_349_PHY_WRLVL_DLY_FINE_STEP_1_MASK (0xFU)
#define LPDDR_DENALI_PHY_349_PHY_WRLVL_DLY_FINE_STEP_1_SHIFT (0U)
#define LPDDR_DENALI_PHY_349_PHY_WRLVL_DLY_FINE_STEP_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_349_PHY_WRLVL_DLY_FINE_STEP_1_SHIFT)) & LPDDR_DENALI_PHY_349_PHY_WRLVL_DLY_FINE_STEP_1_MASK)

#define LPDDR_DENALI_PHY_349_PHY_WRLVL_RESP_WAIT_CNT_1_MASK (0x3F00U)
#define LPDDR_DENALI_PHY_349_PHY_WRLVL_RESP_WAIT_CNT_1_SHIFT (8U)
/*! PHY_WRLVL_RESP_WAIT_CNT_1 - Defines the number of cycles to wait between dfi_wrlvl_strobe and
 *    the sampling of the DQs during write leveling for slice 1.
 */
#define LPDDR_DENALI_PHY_349_PHY_WRLVL_RESP_WAIT_CNT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_349_PHY_WRLVL_RESP_WAIT_CNT_1_SHIFT)) & LPDDR_DENALI_PHY_349_PHY_WRLVL_RESP_WAIT_CNT_1_MASK)

#define LPDDR_DENALI_PHY_349_PHY_GTLVL_DLY_STEP_1_MASK (0xF0000U)
#define LPDDR_DENALI_PHY_349_PHY_GTLVL_DLY_STEP_1_SHIFT (16U)
#define LPDDR_DENALI_PHY_349_PHY_GTLVL_DLY_STEP_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_349_PHY_GTLVL_DLY_STEP_1_SHIFT)) & LPDDR_DENALI_PHY_349_PHY_GTLVL_DLY_STEP_1_MASK)

#define LPDDR_DENALI_PHY_349_PHY_GTLVL_RESP_WAIT_CNT_1_MASK (0x1F000000U)
#define LPDDR_DENALI_PHY_349_PHY_GTLVL_RESP_WAIT_CNT_1_SHIFT (24U)
#define LPDDR_DENALI_PHY_349_PHY_GTLVL_RESP_WAIT_CNT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_349_PHY_GTLVL_RESP_WAIT_CNT_1_SHIFT)) & LPDDR_DENALI_PHY_349_PHY_GTLVL_RESP_WAIT_CNT_1_MASK)
/*! @} */

/*! @name DENALI_PHY_351 - DENALI_PHY_351 */
/*! @{ */

#define LPDDR_DENALI_PHY_351_PHY_WDQLVL_DLY_STEP_1_MASK (0xFFU)
#define LPDDR_DENALI_PHY_351_PHY_WDQLVL_DLY_STEP_1_SHIFT (0U)
#define LPDDR_DENALI_PHY_351_PHY_WDQLVL_DLY_STEP_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_351_PHY_WDQLVL_DLY_STEP_1_SHIFT)) & LPDDR_DENALI_PHY_351_PHY_WDQLVL_DLY_STEP_1_MASK)

#define LPDDR_DENALI_PHY_351_PHY_WDQLVL_QTR_DLY_STEP_1_MASK (0xF00U)
#define LPDDR_DENALI_PHY_351_PHY_WDQLVL_QTR_DLY_STEP_1_SHIFT (8U)
#define LPDDR_DENALI_PHY_351_PHY_WDQLVL_QTR_DLY_STEP_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_351_PHY_WDQLVL_QTR_DLY_STEP_1_SHIFT)) & LPDDR_DENALI_PHY_351_PHY_WDQLVL_QTR_DLY_STEP_1_MASK)

#define LPDDR_DENALI_PHY_351_PHY_TOGGLE_PRE_SUPPORT_1_MASK (0x10000U)
#define LPDDR_DENALI_PHY_351_PHY_TOGGLE_PRE_SUPPORT_1_SHIFT (16U)
/*! PHY_TOGGLE_PRE_SUPPORT_1 - Support the toggle read preamble for LPDDR4 for slice 1.
 *  0b0..Static read preamble
 *  0b1..Toggling read preamble
 */
#define LPDDR_DENALI_PHY_351_PHY_TOGGLE_PRE_SUPPORT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_351_PHY_TOGGLE_PRE_SUPPORT_1_SHIFT)) & LPDDR_DENALI_PHY_351_PHY_TOGGLE_PRE_SUPPORT_1_MASK)

#define LPDDR_DENALI_PHY_351_PHY_RDLVL_DLY_STEP_1_MASK (0xF000000U)
#define LPDDR_DENALI_PHY_351_PHY_RDLVL_DLY_STEP_1_SHIFT (24U)
#define LPDDR_DENALI_PHY_351_PHY_RDLVL_DLY_STEP_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_351_PHY_RDLVL_DLY_STEP_1_SHIFT)) & LPDDR_DENALI_PHY_351_PHY_RDLVL_DLY_STEP_1_MASK)
/*! @} */

/*! @name DENALI_PHY_352 - DENALI_PHY_352 */
/*! @{ */

#define LPDDR_DENALI_PHY_352_PHY_RDLVL_MAX_EDGE_1_MASK (0x3FFU)
#define LPDDR_DENALI_PHY_352_PHY_RDLVL_MAX_EDGE_1_SHIFT (0U)
/*! PHY_RDLVL_MAX_EDGE_1 - Provides the maximun rdlvl slave delay search window for read eye training for slice 1. */
#define LPDDR_DENALI_PHY_352_PHY_RDLVL_MAX_EDGE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_352_PHY_RDLVL_MAX_EDGE_1_SHIFT)) & LPDDR_DENALI_PHY_352_PHY_RDLVL_MAX_EDGE_1_MASK)
/*! @} */

/*! @name DENALI_PHY_353 - DENALI_PHY_353 */
/*! @{ */

#define LPDDR_DENALI_PHY_353_PHY_WRPATH_GATE_DISABLE_1_MASK (0x3U)
#define LPDDR_DENALI_PHY_353_PHY_WRPATH_GATE_DISABLE_1_SHIFT (0U)
#define LPDDR_DENALI_PHY_353_PHY_WRPATH_GATE_DISABLE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_353_PHY_WRPATH_GATE_DISABLE_1_SHIFT)) & LPDDR_DENALI_PHY_353_PHY_WRPATH_GATE_DISABLE_1_MASK)

#define LPDDR_DENALI_PHY_353_PHY_WRPATH_GATE_TIMING_1_MASK (0x700U)
#define LPDDR_DENALI_PHY_353_PHY_WRPATH_GATE_TIMING_1_SHIFT (8U)
#define LPDDR_DENALI_PHY_353_PHY_WRPATH_GATE_TIMING_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_353_PHY_WRPATH_GATE_TIMING_1_SHIFT)) & LPDDR_DENALI_PHY_353_PHY_WRPATH_GATE_TIMING_1_MASK)

#define LPDDR_DENALI_PHY_353_PHY_MEAS_DLY_STEP_ENABLE_1_MASK (0x3F0000U)
#define LPDDR_DENALI_PHY_353_PHY_MEAS_DLY_STEP_ENABLE_1_SHIFT (16U)
/*! PHY_MEAS_DLY_STEP_ENABLE_1 - Data slice training step definition using phy_meas_dly_step_value for slice 1. */
#define LPDDR_DENALI_PHY_353_PHY_MEAS_DLY_STEP_ENABLE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_353_PHY_MEAS_DLY_STEP_ENABLE_1_SHIFT)) & LPDDR_DENALI_PHY_353_PHY_MEAS_DLY_STEP_ENABLE_1_MASK)

#define LPDDR_DENALI_PHY_353_PHY_RDDATA_EN_DLY_1_MASK (0x1F000000U)
#define LPDDR_DENALI_PHY_353_PHY_RDDATA_EN_DLY_1_SHIFT (24U)
#define LPDDR_DENALI_PHY_353_PHY_RDDATA_EN_DLY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_353_PHY_RDDATA_EN_DLY_1_SHIFT)) & LPDDR_DENALI_PHY_353_PHY_RDDATA_EN_DLY_1_MASK)
/*! @} */

/*! @name DENALI_PHY_354 - DENALI_PHY_354 */
/*! @{ */

#define LPDDR_DENALI_PHY_354_PHY_DQ_DM_SWIZZLE0_1_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_PHY_354_PHY_DQ_DM_SWIZZLE0_1_SHIFT (0U)
#define LPDDR_DENALI_PHY_354_PHY_DQ_DM_SWIZZLE0_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_354_PHY_DQ_DM_SWIZZLE0_1_SHIFT)) & LPDDR_DENALI_PHY_354_PHY_DQ_DM_SWIZZLE0_1_MASK)
/*! @} */

/*! @name DENALI_PHY_356 - DENALI_PHY_356 */
/*! @{ */

#define LPDDR_DENALI_PHY_356_PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_356_PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT (0U)
/*! PHY_CLK_WRDQ0_SLAVE_DELAY_1 - Write clock slave delay setting for DQ0 for slice 1. */
#define LPDDR_DENALI_PHY_356_PHY_CLK_WRDQ0_SLAVE_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_356_PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT)) & LPDDR_DENALI_PHY_356_PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK)

#define LPDDR_DENALI_PHY_356_PHY_CLK_WRDQ1_SLAVE_DELAY_1_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_356_PHY_CLK_WRDQ1_SLAVE_DELAY_1_SHIFT (16U)
#define LPDDR_DENALI_PHY_356_PHY_CLK_WRDQ1_SLAVE_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_356_PHY_CLK_WRDQ1_SLAVE_DELAY_1_SHIFT)) & LPDDR_DENALI_PHY_356_PHY_CLK_WRDQ1_SLAVE_DELAY_1_MASK)
/*! @} */

/*! @name DENALI_PHY_357 - DENALI_PHY_357 */
/*! @{ */

#define LPDDR_DENALI_PHY_357_PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_357_PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT (0U)
/*! PHY_CLK_WRDQ2_SLAVE_DELAY_1 - Write clock slave delay setting for DQ2 for slice 1. */
#define LPDDR_DENALI_PHY_357_PHY_CLK_WRDQ2_SLAVE_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_357_PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT)) & LPDDR_DENALI_PHY_357_PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK)

#define LPDDR_DENALI_PHY_357_PHY_CLK_WRDQ3_SLAVE_DELAY_1_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_357_PHY_CLK_WRDQ3_SLAVE_DELAY_1_SHIFT (16U)
/*! PHY_CLK_WRDQ3_SLAVE_DELAY_1 - Write clock slave delay setting for DQ3 for slice 1. */
#define LPDDR_DENALI_PHY_357_PHY_CLK_WRDQ3_SLAVE_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_357_PHY_CLK_WRDQ3_SLAVE_DELAY_1_SHIFT)) & LPDDR_DENALI_PHY_357_PHY_CLK_WRDQ3_SLAVE_DELAY_1_MASK)
/*! @} */

/*! @name DENALI_PHY_358 - DENALI_PHY_358 */
/*! @{ */

#define LPDDR_DENALI_PHY_358_PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_358_PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT (0U)
/*! PHY_CLK_WRDQ4_SLAVE_DELAY_1 - Write clock slave delay setting for DQ4 for slice 1. */
#define LPDDR_DENALI_PHY_358_PHY_CLK_WRDQ4_SLAVE_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_358_PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT)) & LPDDR_DENALI_PHY_358_PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK)

#define LPDDR_DENALI_PHY_358_PHY_CLK_WRDQ5_SLAVE_DELAY_1_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_358_PHY_CLK_WRDQ5_SLAVE_DELAY_1_SHIFT (16U)
/*! PHY_CLK_WRDQ5_SLAVE_DELAY_1 - Write clock slave delay setting for DQ5 for slice 1. */
#define LPDDR_DENALI_PHY_358_PHY_CLK_WRDQ5_SLAVE_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_358_PHY_CLK_WRDQ5_SLAVE_DELAY_1_SHIFT)) & LPDDR_DENALI_PHY_358_PHY_CLK_WRDQ5_SLAVE_DELAY_1_MASK)
/*! @} */

/*! @name DENALI_PHY_359 - DENALI_PHY_359 */
/*! @{ */

#define LPDDR_DENALI_PHY_359_PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_359_PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT (0U)
/*! PHY_CLK_WRDQ6_SLAVE_DELAY_1 - Write clock slave delay setting for DQ6 for slice 1. */
#define LPDDR_DENALI_PHY_359_PHY_CLK_WRDQ6_SLAVE_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_359_PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT)) & LPDDR_DENALI_PHY_359_PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK)

#define LPDDR_DENALI_PHY_359_PHY_CLK_WRDQ7_SLAVE_DELAY_1_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_359_PHY_CLK_WRDQ7_SLAVE_DELAY_1_SHIFT (16U)
/*! PHY_CLK_WRDQ7_SLAVE_DELAY_1 - Write clock slave delay setting for DQ7 for slice 1. */
#define LPDDR_DENALI_PHY_359_PHY_CLK_WRDQ7_SLAVE_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_359_PHY_CLK_WRDQ7_SLAVE_DELAY_1_SHIFT)) & LPDDR_DENALI_PHY_359_PHY_CLK_WRDQ7_SLAVE_DELAY_1_MASK)
/*! @} */

/*! @name DENALI_PHY_360 - DENALI_PHY_360 */
/*! @{ */

#define LPDDR_DENALI_PHY_360_PHY_CLK_WRDM_SLAVE_DELAY_1_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_360_PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT (0U)
/*! PHY_CLK_WRDM_SLAVE_DELAY_1 - Write clock slave delay setting for DM for slice 1. */
#define LPDDR_DENALI_PHY_360_PHY_CLK_WRDM_SLAVE_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_360_PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT)) & LPDDR_DENALI_PHY_360_PHY_CLK_WRDM_SLAVE_DELAY_1_MASK)

#define LPDDR_DENALI_PHY_360_PHY_CLK_WRDQS_SLAVE_DELAY_1_MASK (0x3FF0000U)
#define LPDDR_DENALI_PHY_360_PHY_CLK_WRDQS_SLAVE_DELAY_1_SHIFT (16U)
/*! PHY_CLK_WRDQS_SLAVE_DELAY_1 - Write clock slave delay setting for DQS for slice 1. */
#define LPDDR_DENALI_PHY_360_PHY_CLK_WRDQS_SLAVE_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_360_PHY_CLK_WRDQS_SLAVE_DELAY_1_SHIFT)) & LPDDR_DENALI_PHY_360_PHY_CLK_WRDQS_SLAVE_DELAY_1_MASK)
/*! @} */

/*! @name DENALI_PHY_370 - DENALI_PHY_370 */
/*! @{ */

#define LPDDR_DENALI_PHY_370_PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK (0x3FFU)
#define LPDDR_DENALI_PHY_370_PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT (0U)
/*! PHY_RDDQS_DM_FALL_SLAVE_DELAY_1 - Falling edge read DQS slave delay setting for DM for slice 1. */
#define LPDDR_DENALI_PHY_370_PHY_RDDQS_DM_FALL_SLAVE_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_370_PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT)) & LPDDR_DENALI_PHY_370_PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK)

#define LPDDR_DENALI_PHY_370_PHY_RDDQS_GATE_SLAVE_DELAY_1_MASK (0x3FF0000U)
#define LPDDR_DENALI_PHY_370_PHY_RDDQS_GATE_SLAVE_DELAY_1_SHIFT (16U)
/*! PHY_RDDQS_GATE_SLAVE_DELAY_1 - Read DQS slave delay setting for slice 1. */
#define LPDDR_DENALI_PHY_370_PHY_RDDQS_GATE_SLAVE_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_370_PHY_RDDQS_GATE_SLAVE_DELAY_1_SHIFT)) & LPDDR_DENALI_PHY_370_PHY_RDDQS_GATE_SLAVE_DELAY_1_MASK)
/*! @} */

/*! @name DENALI_PHY_543 - DENALI_PHY_543 */
/*! @{ */

#define LPDDR_DENALI_PHY_543_PHY_WRLVL_UPDT_WAIT_CNT_2_MASK (0xFU)
#define LPDDR_DENALI_PHY_543_PHY_WRLVL_UPDT_WAIT_CNT_2_SHIFT (0U)
#define LPDDR_DENALI_PHY_543_PHY_WRLVL_UPDT_WAIT_CNT_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_543_PHY_WRLVL_UPDT_WAIT_CNT_2_SHIFT)) & LPDDR_DENALI_PHY_543_PHY_WRLVL_UPDT_WAIT_CNT_2_MASK)

#define LPDDR_DENALI_PHY_543_PHY_DQ_MASK_2_MASK  (0xFF00U)
#define LPDDR_DENALI_PHY_543_PHY_DQ_MASK_2_SHIFT (8U)
#define LPDDR_DENALI_PHY_543_PHY_DQ_MASK_2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_543_PHY_DQ_MASK_2_SHIFT)) & LPDDR_DENALI_PHY_543_PHY_DQ_MASK_2_MASK)

#define LPDDR_DENALI_PHY_543_PHY_GTLVL_CAPTURE_CNT_2_MASK (0x3F0000U)
#define LPDDR_DENALI_PHY_543_PHY_GTLVL_CAPTURE_CNT_2_SHIFT (16U)
#define LPDDR_DENALI_PHY_543_PHY_GTLVL_CAPTURE_CNT_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_543_PHY_GTLVL_CAPTURE_CNT_2_SHIFT)) & LPDDR_DENALI_PHY_543_PHY_GTLVL_CAPTURE_CNT_2_MASK)

#define LPDDR_DENALI_PHY_543_PHY_GTLVL_UPDT_WAIT_CNT_2_MASK (0xF000000U)
#define LPDDR_DENALI_PHY_543_PHY_GTLVL_UPDT_WAIT_CNT_2_SHIFT (24U)
#define LPDDR_DENALI_PHY_543_PHY_GTLVL_UPDT_WAIT_CNT_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_543_PHY_GTLVL_UPDT_WAIT_CNT_2_SHIFT)) & LPDDR_DENALI_PHY_543_PHY_GTLVL_UPDT_WAIT_CNT_2_MASK)
/*! @} */

/*! @name DENALI_PHY_545 - DENALI_PHY_545 */
/*! @{ */

#define LPDDR_DENALI_PHY_545_PHY_RDLVL_DATA_MASK_2_MASK (0xFFU)
#define LPDDR_DENALI_PHY_545_PHY_RDLVL_DATA_MASK_2_SHIFT (0U)
#define LPDDR_DENALI_PHY_545_PHY_RDLVL_DATA_MASK_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_545_PHY_RDLVL_DATA_MASK_2_SHIFT)) & LPDDR_DENALI_PHY_545_PHY_RDLVL_DATA_MASK_2_MASK)

#define LPDDR_DENALI_PHY_545_PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_MASK (0xFF00U)
#define LPDDR_DENALI_PHY_545_PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_SHIFT (8U)
#define LPDDR_DENALI_PHY_545_PHY_WDQLVL_CLK_JITTER_TOLERANCE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_545_PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_SHIFT)) & LPDDR_DENALI_PHY_545_PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_MASK)

#define LPDDR_DENALI_PHY_545_PHY_WDQLVL_BURST_CNT_2_MASK (0x3F0000U)
#define LPDDR_DENALI_PHY_545_PHY_WDQLVL_BURST_CNT_2_SHIFT (16U)
/*! PHY_WDQLVL_BURST_CNT_2 - Defines the write/read burst length in bytes during the write data leveling sequence for slice 2. */
#define LPDDR_DENALI_PHY_545_PHY_WDQLVL_BURST_CNT_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_545_PHY_WDQLVL_BURST_CNT_2_SHIFT)) & LPDDR_DENALI_PHY_545_PHY_WDQLVL_BURST_CNT_2_MASK)

#define LPDDR_DENALI_PHY_545_PHY_WDQLVL_PATT_2_MASK (0x7000000U)
#define LPDDR_DENALI_PHY_545_PHY_WDQLVL_PATT_2_SHIFT (24U)
#define LPDDR_DENALI_PHY_545_PHY_WDQLVL_PATT_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_545_PHY_WDQLVL_PATT_2_SHIFT)) & LPDDR_DENALI_PHY_545_PHY_WDQLVL_PATT_2_MASK)
/*! @} */

/*! @name DENALI_PHY_584 - DENALI_PHY_584 */
/*! @{ */

#define LPDDR_DENALI_PHY_584_PHY_SLV_DLY_CTRL_GATE_DISABLE_2_MASK (0x1U)
#define LPDDR_DENALI_PHY_584_PHY_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT (0U)
#define LPDDR_DENALI_PHY_584_PHY_SLV_DLY_CTRL_GATE_DISABLE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_584_PHY_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT)) & LPDDR_DENALI_PHY_584_PHY_SLV_DLY_CTRL_GATE_DISABLE_2_MASK)

#define LPDDR_DENALI_PHY_584_PHY_RDPATH_GATE_DISABLE_2_MASK (0x100U)
#define LPDDR_DENALI_PHY_584_PHY_RDPATH_GATE_DISABLE_2_SHIFT (8U)
#define LPDDR_DENALI_PHY_584_PHY_RDPATH_GATE_DISABLE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_584_PHY_RDPATH_GATE_DISABLE_2_SHIFT)) & LPDDR_DENALI_PHY_584_PHY_RDPATH_GATE_DISABLE_2_MASK)

#define LPDDR_DENALI_PHY_584_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_MASK (0x10000U)
#define LPDDR_DENALI_PHY_584_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_SHIFT (16U)
#define LPDDR_DENALI_PHY_584_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_584_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_SHIFT)) & LPDDR_DENALI_PHY_584_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_MASK)

#define LPDDR_DENALI_PHY_584_PHY_SLICE_PWR_RDC_DISABLE_2_MASK (0x1000000U)
#define LPDDR_DENALI_PHY_584_PHY_SLICE_PWR_RDC_DISABLE_2_SHIFT (24U)
#define LPDDR_DENALI_PHY_584_PHY_SLICE_PWR_RDC_DISABLE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_584_PHY_SLICE_PWR_RDC_DISABLE_2_SHIFT)) & LPDDR_DENALI_PHY_584_PHY_SLICE_PWR_RDC_DISABLE_2_MASK)
/*! @} */

/*! @name DENALI_PHY_585 - DENALI_PHY_585 */
/*! @{ */

#define LPDDR_DENALI_PHY_585_PHY_DQ_TSEL_ENABLE_2_MASK (0x7U)
#define LPDDR_DENALI_PHY_585_PHY_DQ_TSEL_ENABLE_2_SHIFT (0U)
#define LPDDR_DENALI_PHY_585_PHY_DQ_TSEL_ENABLE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_585_PHY_DQ_TSEL_ENABLE_2_SHIFT)) & LPDDR_DENALI_PHY_585_PHY_DQ_TSEL_ENABLE_2_MASK)

#define LPDDR_DENALI_PHY_585_PHY_DQ_TSEL_SELECT_2_MASK (0xFFFF00U)
#define LPDDR_DENALI_PHY_585_PHY_DQ_TSEL_SELECT_2_SHIFT (8U)
/*! PHY_DQ_TSEL_SELECT_2 - Operation type tsel select values for DQ/DM signals for slice 2. */
#define LPDDR_DENALI_PHY_585_PHY_DQ_TSEL_SELECT_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_585_PHY_DQ_TSEL_SELECT_2_SHIFT)) & LPDDR_DENALI_PHY_585_PHY_DQ_TSEL_SELECT_2_MASK)

#define LPDDR_DENALI_PHY_585_PHY_DQS_TSEL_ENABLE_2_MASK (0x7000000U)
#define LPDDR_DENALI_PHY_585_PHY_DQS_TSEL_ENABLE_2_SHIFT (24U)
#define LPDDR_DENALI_PHY_585_PHY_DQS_TSEL_ENABLE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_585_PHY_DQS_TSEL_ENABLE_2_SHIFT)) & LPDDR_DENALI_PHY_585_PHY_DQS_TSEL_ENABLE_2_MASK)
/*! @} */

/*! @name DENALI_PHY_586 - DENALI_PHY_586 */
/*! @{ */

#define LPDDR_DENALI_PHY_586_PHY_DQS_TSEL_SELECT_2_MASK (0xFFFFU)
#define LPDDR_DENALI_PHY_586_PHY_DQS_TSEL_SELECT_2_SHIFT (0U)
/*! PHY_DQS_TSEL_SELECT_2 - Operation type tsel select values for DQS signals for slice 2. */
#define LPDDR_DENALI_PHY_586_PHY_DQS_TSEL_SELECT_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_586_PHY_DQS_TSEL_SELECT_2_SHIFT)) & LPDDR_DENALI_PHY_586_PHY_DQS_TSEL_SELECT_2_MASK)

#define LPDDR_DENALI_PHY_586_PHY_TWO_CYC_PREAMBLE_2_MASK (0x30000U)
#define LPDDR_DENALI_PHY_586_PHY_TWO_CYC_PREAMBLE_2_SHIFT (16U)
#define LPDDR_DENALI_PHY_586_PHY_TWO_CYC_PREAMBLE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_586_PHY_TWO_CYC_PREAMBLE_2_SHIFT)) & LPDDR_DENALI_PHY_586_PHY_TWO_CYC_PREAMBLE_2_MASK)

#define LPDDR_DENALI_PHY_586_PHY_VREF_INITIAL_START_POINT_2_MASK (0x7F000000U)
#define LPDDR_DENALI_PHY_586_PHY_VREF_INITIAL_START_POINT_2_SHIFT (24U)
#define LPDDR_DENALI_PHY_586_PHY_VREF_INITIAL_START_POINT_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_586_PHY_VREF_INITIAL_START_POINT_2_SHIFT)) & LPDDR_DENALI_PHY_586_PHY_VREF_INITIAL_START_POINT_2_MASK)
/*! @} */

/*! @name DENALI_PHY_587 - DENALI_PHY_587 */
/*! @{ */

#define LPDDR_DENALI_PHY_587_PHY_VREF_INITIAL_STOP_POINT_2_MASK (0x7FU)
#define LPDDR_DENALI_PHY_587_PHY_VREF_INITIAL_STOP_POINT_2_SHIFT (0U)
/*! PHY_VREF_INITIAL_STOP_POINT_2 - Data slice initial VREF training stop value for slice 2. When
 *    programming the write DQ VREF stop point parameter, must set it equal to a multiple of the VREF
 *    (step size + start point).
 */
#define LPDDR_DENALI_PHY_587_PHY_VREF_INITIAL_STOP_POINT_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_587_PHY_VREF_INITIAL_STOP_POINT_2_SHIFT)) & LPDDR_DENALI_PHY_587_PHY_VREF_INITIAL_STOP_POINT_2_MASK)

#define LPDDR_DENALI_PHY_587_PHY_VREF_TRAINING_CTRL_2_MASK (0x300U)
#define LPDDR_DENALI_PHY_587_PHY_VREF_TRAINING_CTRL_2_SHIFT (8U)
#define LPDDR_DENALI_PHY_587_PHY_VREF_TRAINING_CTRL_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_587_PHY_VREF_TRAINING_CTRL_2_SHIFT)) & LPDDR_DENALI_PHY_587_PHY_VREF_TRAINING_CTRL_2_MASK)

#define LPDDR_DENALI_PHY_587_PHY_NTP_TRAIN_EN_2_MASK (0x10000U)
#define LPDDR_DENALI_PHY_587_PHY_NTP_TRAIN_EN_2_SHIFT (16U)
/*! PHY_NTP_TRAIN_EN_2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPDDR_DENALI_PHY_587_PHY_NTP_TRAIN_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_587_PHY_NTP_TRAIN_EN_2_SHIFT)) & LPDDR_DENALI_PHY_587_PHY_NTP_TRAIN_EN_2_MASK)

#define LPDDR_DENALI_PHY_587_PHY_NTP_WDQ_STEP_SIZE_2_MASK (0xFF000000U)
#define LPDDR_DENALI_PHY_587_PHY_NTP_WDQ_STEP_SIZE_2_SHIFT (24U)
#define LPDDR_DENALI_PHY_587_PHY_NTP_WDQ_STEP_SIZE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_587_PHY_NTP_WDQ_STEP_SIZE_2_SHIFT)) & LPDDR_DENALI_PHY_587_PHY_NTP_WDQ_STEP_SIZE_2_MASK)
/*! @} */

/*! @name DENALI_PHY_592 - DENALI_PHY_592 */
/*! @{ */

#define LPDDR_DENALI_PHY_592_PHY_PAD_DQS_RX_DCD_2_MASK (0x1FU)
#define LPDDR_DENALI_PHY_592_PHY_PAD_DQS_RX_DCD_2_SHIFT (0U)
/*! PHY_PAD_DQS_RX_DCD_2 - Controls RX_DCD pin for dqs pad for slice 2. */
#define LPDDR_DENALI_PHY_592_PHY_PAD_DQS_RX_DCD_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_592_PHY_PAD_DQS_RX_DCD_2_SHIFT)) & LPDDR_DENALI_PHY_592_PHY_PAD_DQS_RX_DCD_2_MASK)

#define LPDDR_DENALI_PHY_592_PHY_PAD_FDBK_RX_DCD_2_MASK (0x1F00U)
#define LPDDR_DENALI_PHY_592_PHY_PAD_FDBK_RX_DCD_2_SHIFT (8U)
/*! PHY_PAD_FDBK_RX_DCD_2 - Controls RX_DCD pin for fdbk pad for slice 2. */
#define LPDDR_DENALI_PHY_592_PHY_PAD_FDBK_RX_DCD_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_592_PHY_PAD_FDBK_RX_DCD_2_SHIFT)) & LPDDR_DENALI_PHY_592_PHY_PAD_FDBK_RX_DCD_2_MASK)

#define LPDDR_DENALI_PHY_592_PHY_PAD_DSLICE_IO_CFG_2_MASK (0x7F0000U)
#define LPDDR_DENALI_PHY_592_PHY_PAD_DSLICE_IO_CFG_2_SHIFT (16U)
/*! PHY_PAD_DSLICE_IO_CFG_2 - Controls PCLK/PARK pin for IO pad for slice 2. */
#define LPDDR_DENALI_PHY_592_PHY_PAD_DSLICE_IO_CFG_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_592_PHY_PAD_DSLICE_IO_CFG_2_SHIFT)) & LPDDR_DENALI_PHY_592_PHY_PAD_DSLICE_IO_CFG_2_MASK)
/*! @} */

/*! @name DENALI_PHY_600 - DENALI_PHY_600 */
/*! @{ */

#define LPDDR_DENALI_PHY_600_PHY_VREF_SETTING_TIME_2_MASK (0xFFFFU)
#define LPDDR_DENALI_PHY_600_PHY_VREF_SETTING_TIME_2_SHIFT (0U)
#define LPDDR_DENALI_PHY_600_PHY_VREF_SETTING_TIME_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_600_PHY_VREF_SETTING_TIME_2_SHIFT)) & LPDDR_DENALI_PHY_600_PHY_VREF_SETTING_TIME_2_MASK)

#define LPDDR_DENALI_PHY_600_PHY_PAD_VREF_CTRL_DQ_2_MASK (0xFFF0000U)
#define LPDDR_DENALI_PHY_600_PHY_PAD_VREF_CTRL_DQ_2_SHIFT (16U)
#define LPDDR_DENALI_PHY_600_PHY_PAD_VREF_CTRL_DQ_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_600_PHY_PAD_VREF_CTRL_DQ_2_SHIFT)) & LPDDR_DENALI_PHY_600_PHY_PAD_VREF_CTRL_DQ_2_MASK)
/*! @} */

/*! @name DENALI_PHY_601 - DENALI_PHY_601 */
/*! @{ */

#define LPDDR_DENALI_PHY_601_PHY_PER_CS_TRAINING_EN_2_MASK (0x1U)
#define LPDDR_DENALI_PHY_601_PHY_PER_CS_TRAINING_EN_2_SHIFT (0U)
#define LPDDR_DENALI_PHY_601_PHY_PER_CS_TRAINING_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_601_PHY_PER_CS_TRAINING_EN_2_SHIFT)) & LPDDR_DENALI_PHY_601_PHY_PER_CS_TRAINING_EN_2_MASK)

#define LPDDR_DENALI_PHY_601_PHY_DQ_IE_TIMING_2_MASK (0xFF00U)
#define LPDDR_DENALI_PHY_601_PHY_DQ_IE_TIMING_2_SHIFT (8U)
#define LPDDR_DENALI_PHY_601_PHY_DQ_IE_TIMING_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_601_PHY_DQ_IE_TIMING_2_SHIFT)) & LPDDR_DENALI_PHY_601_PHY_DQ_IE_TIMING_2_MASK)

#define LPDDR_DENALI_PHY_601_PHY_DQS_IE_TIMING_2_MASK (0xFF0000U)
#define LPDDR_DENALI_PHY_601_PHY_DQS_IE_TIMING_2_SHIFT (16U)
#define LPDDR_DENALI_PHY_601_PHY_DQS_IE_TIMING_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_601_PHY_DQS_IE_TIMING_2_SHIFT)) & LPDDR_DENALI_PHY_601_PHY_DQS_IE_TIMING_2_MASK)

#define LPDDR_DENALI_PHY_601_PHY_RDDATA_EN_IE_DLY_2_MASK (0x3000000U)
#define LPDDR_DENALI_PHY_601_PHY_RDDATA_EN_IE_DLY_2_SHIFT (24U)
#define LPDDR_DENALI_PHY_601_PHY_RDDATA_EN_IE_DLY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_601_PHY_RDDATA_EN_IE_DLY_2_SHIFT)) & LPDDR_DENALI_PHY_601_PHY_RDDATA_EN_IE_DLY_2_MASK)
/*! @} */

/*! @name DENALI_PHY_602 - DENALI_PHY_602 */
/*! @{ */

#define LPDDR_DENALI_PHY_602_PHY_IE_MODE_2_MASK  (0x3U)
#define LPDDR_DENALI_PHY_602_PHY_IE_MODE_2_SHIFT (0U)
#define LPDDR_DENALI_PHY_602_PHY_IE_MODE_2(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_602_PHY_IE_MODE_2_SHIFT)) & LPDDR_DENALI_PHY_602_PHY_IE_MODE_2_MASK)

#define LPDDR_DENALI_PHY_602_PHY_DBI_MODE_2_MASK (0x100U)
#define LPDDR_DENALI_PHY_602_PHY_DBI_MODE_2_SHIFT (8U)
/*! PHY_DBI_MODE_2
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_PHY_602_PHY_DBI_MODE_2(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_602_PHY_DBI_MODE_2_SHIFT)) & LPDDR_DENALI_PHY_602_PHY_DBI_MODE_2_MASK)

#define LPDDR_DENALI_PHY_602_PHY_RDDATA_EN_TSEL_DLY_2_MASK (0x1F0000U)
#define LPDDR_DENALI_PHY_602_PHY_RDDATA_EN_TSEL_DLY_2_SHIFT (16U)
#define LPDDR_DENALI_PHY_602_PHY_RDDATA_EN_TSEL_DLY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_602_PHY_RDDATA_EN_TSEL_DLY_2_SHIFT)) & LPDDR_DENALI_PHY_602_PHY_RDDATA_EN_TSEL_DLY_2_MASK)

#define LPDDR_DENALI_PHY_602_PHY_RDDATA_EN_OE_DLY_2_MASK (0x1F000000U)
#define LPDDR_DENALI_PHY_602_PHY_RDDATA_EN_OE_DLY_2_SHIFT (24U)
#define LPDDR_DENALI_PHY_602_PHY_RDDATA_EN_OE_DLY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_602_PHY_RDDATA_EN_OE_DLY_2_SHIFT)) & LPDDR_DENALI_PHY_602_PHY_RDDATA_EN_OE_DLY_2_MASK)
/*! @} */

/*! @name DENALI_PHY_604 - DENALI_PHY_604 */
/*! @{ */

#define LPDDR_DENALI_PHY_604_PHY_MASTER_DELAY_WAIT_2_MASK (0xFFU)
#define LPDDR_DENALI_PHY_604_PHY_MASTER_DELAY_WAIT_2_SHIFT (0U)
#define LPDDR_DENALI_PHY_604_PHY_MASTER_DELAY_WAIT_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_604_PHY_MASTER_DELAY_WAIT_2_SHIFT)) & LPDDR_DENALI_PHY_604_PHY_MASTER_DELAY_WAIT_2_MASK)

#define LPDDR_DENALI_PHY_604_PHY_MASTER_DELAY_HALF_MEASURE_2_MASK (0xFF00U)
#define LPDDR_DENALI_PHY_604_PHY_MASTER_DELAY_HALF_MEASURE_2_SHIFT (8U)
/*! PHY_MASTER_DELAY_HALF_MEASURE_2 - Defines the number of delay line elements to be considered in
 *    determing whether to lock to a half clock cycle in the data slice master for slice 2.
 */
#define LPDDR_DENALI_PHY_604_PHY_MASTER_DELAY_HALF_MEASURE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_604_PHY_MASTER_DELAY_HALF_MEASURE_2_SHIFT)) & LPDDR_DENALI_PHY_604_PHY_MASTER_DELAY_HALF_MEASURE_2_MASK)

#define LPDDR_DENALI_PHY_604_PHY_RPTR_UPDATE_2_MASK (0xF0000U)
#define LPDDR_DENALI_PHY_604_PHY_RPTR_UPDATE_2_SHIFT (16U)
#define LPDDR_DENALI_PHY_604_PHY_RPTR_UPDATE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_604_PHY_RPTR_UPDATE_2_SHIFT)) & LPDDR_DENALI_PHY_604_PHY_RPTR_UPDATE_2_MASK)

#define LPDDR_DENALI_PHY_604_PHY_WRLVL_DLY_STEP_2_MASK (0xFF000000U)
#define LPDDR_DENALI_PHY_604_PHY_WRLVL_DLY_STEP_2_SHIFT (24U)
#define LPDDR_DENALI_PHY_604_PHY_WRLVL_DLY_STEP_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_604_PHY_WRLVL_DLY_STEP_2_SHIFT)) & LPDDR_DENALI_PHY_604_PHY_WRLVL_DLY_STEP_2_MASK)
/*! @} */

/*! @name DENALI_PHY_605 - DENALI_PHY_605 */
/*! @{ */

#define LPDDR_DENALI_PHY_605_PHY_WRLVL_DLY_FINE_STEP_2_MASK (0xFU)
#define LPDDR_DENALI_PHY_605_PHY_WRLVL_DLY_FINE_STEP_2_SHIFT (0U)
#define LPDDR_DENALI_PHY_605_PHY_WRLVL_DLY_FINE_STEP_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_605_PHY_WRLVL_DLY_FINE_STEP_2_SHIFT)) & LPDDR_DENALI_PHY_605_PHY_WRLVL_DLY_FINE_STEP_2_MASK)

#define LPDDR_DENALI_PHY_605_PHY_WRLVL_RESP_WAIT_CNT_2_MASK (0x3F00U)
#define LPDDR_DENALI_PHY_605_PHY_WRLVL_RESP_WAIT_CNT_2_SHIFT (8U)
/*! PHY_WRLVL_RESP_WAIT_CNT_2 - Defines the number of cycles to wait between dfi_wrlvl_strobe and
 *    the sampling of the DQs during write leveling for slice 2.
 */
#define LPDDR_DENALI_PHY_605_PHY_WRLVL_RESP_WAIT_CNT_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_605_PHY_WRLVL_RESP_WAIT_CNT_2_SHIFT)) & LPDDR_DENALI_PHY_605_PHY_WRLVL_RESP_WAIT_CNT_2_MASK)

#define LPDDR_DENALI_PHY_605_PHY_GTLVL_DLY_STEP_2_MASK (0xF0000U)
#define LPDDR_DENALI_PHY_605_PHY_GTLVL_DLY_STEP_2_SHIFT (16U)
#define LPDDR_DENALI_PHY_605_PHY_GTLVL_DLY_STEP_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_605_PHY_GTLVL_DLY_STEP_2_SHIFT)) & LPDDR_DENALI_PHY_605_PHY_GTLVL_DLY_STEP_2_MASK)

#define LPDDR_DENALI_PHY_605_PHY_GTLVL_RESP_WAIT_CNT_2_MASK (0x1F000000U)
#define LPDDR_DENALI_PHY_605_PHY_GTLVL_RESP_WAIT_CNT_2_SHIFT (24U)
#define LPDDR_DENALI_PHY_605_PHY_GTLVL_RESP_WAIT_CNT_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_605_PHY_GTLVL_RESP_WAIT_CNT_2_SHIFT)) & LPDDR_DENALI_PHY_605_PHY_GTLVL_RESP_WAIT_CNT_2_MASK)
/*! @} */

/*! @name DENALI_PHY_607 - DENALI_PHY_607 */
/*! @{ */

#define LPDDR_DENALI_PHY_607_PHY_WDQLVL_DLY_STEP_2_MASK (0xFFU)
#define LPDDR_DENALI_PHY_607_PHY_WDQLVL_DLY_STEP_2_SHIFT (0U)
#define LPDDR_DENALI_PHY_607_PHY_WDQLVL_DLY_STEP_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_607_PHY_WDQLVL_DLY_STEP_2_SHIFT)) & LPDDR_DENALI_PHY_607_PHY_WDQLVL_DLY_STEP_2_MASK)

#define LPDDR_DENALI_PHY_607_PHY_WDQLVL_QTR_DLY_STEP_2_MASK (0xF00U)
#define LPDDR_DENALI_PHY_607_PHY_WDQLVL_QTR_DLY_STEP_2_SHIFT (8U)
#define LPDDR_DENALI_PHY_607_PHY_WDQLVL_QTR_DLY_STEP_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_607_PHY_WDQLVL_QTR_DLY_STEP_2_SHIFT)) & LPDDR_DENALI_PHY_607_PHY_WDQLVL_QTR_DLY_STEP_2_MASK)

#define LPDDR_DENALI_PHY_607_PHY_TOGGLE_PRE_SUPPORT_2_MASK (0x10000U)
#define LPDDR_DENALI_PHY_607_PHY_TOGGLE_PRE_SUPPORT_2_SHIFT (16U)
/*! PHY_TOGGLE_PRE_SUPPORT_2 - Support the toggle read preamble for LPDDR4 for slice 2.
 *  0b0..Static read preamble
 *  0b1..Toggling read preamble
 */
#define LPDDR_DENALI_PHY_607_PHY_TOGGLE_PRE_SUPPORT_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_607_PHY_TOGGLE_PRE_SUPPORT_2_SHIFT)) & LPDDR_DENALI_PHY_607_PHY_TOGGLE_PRE_SUPPORT_2_MASK)

#define LPDDR_DENALI_PHY_607_PHY_RDLVL_DLY_STEP_2_MASK (0xF000000U)
#define LPDDR_DENALI_PHY_607_PHY_RDLVL_DLY_STEP_2_SHIFT (24U)
#define LPDDR_DENALI_PHY_607_PHY_RDLVL_DLY_STEP_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_607_PHY_RDLVL_DLY_STEP_2_SHIFT)) & LPDDR_DENALI_PHY_607_PHY_RDLVL_DLY_STEP_2_MASK)
/*! @} */

/*! @name DENALI_PHY_608 - DENALI_PHY_608 */
/*! @{ */

#define LPDDR_DENALI_PHY_608_PHY_RDLVL_MAX_EDGE_2_MASK (0x3FFU)
#define LPDDR_DENALI_PHY_608_PHY_RDLVL_MAX_EDGE_2_SHIFT (0U)
/*! PHY_RDLVL_MAX_EDGE_2 - Provides the maximun rdlvl slave delay search window for read eye training for slice 2. */
#define LPDDR_DENALI_PHY_608_PHY_RDLVL_MAX_EDGE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_608_PHY_RDLVL_MAX_EDGE_2_SHIFT)) & LPDDR_DENALI_PHY_608_PHY_RDLVL_MAX_EDGE_2_MASK)
/*! @} */

/*! @name DENALI_PHY_609 - DENALI_PHY_609 */
/*! @{ */

#define LPDDR_DENALI_PHY_609_PHY_WRPATH_GATE_DISABLE_2_MASK (0x3U)
#define LPDDR_DENALI_PHY_609_PHY_WRPATH_GATE_DISABLE_2_SHIFT (0U)
#define LPDDR_DENALI_PHY_609_PHY_WRPATH_GATE_DISABLE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_609_PHY_WRPATH_GATE_DISABLE_2_SHIFT)) & LPDDR_DENALI_PHY_609_PHY_WRPATH_GATE_DISABLE_2_MASK)

#define LPDDR_DENALI_PHY_609_PHY_WRPATH_GATE_TIMING_2_MASK (0x700U)
#define LPDDR_DENALI_PHY_609_PHY_WRPATH_GATE_TIMING_2_SHIFT (8U)
#define LPDDR_DENALI_PHY_609_PHY_WRPATH_GATE_TIMING_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_609_PHY_WRPATH_GATE_TIMING_2_SHIFT)) & LPDDR_DENALI_PHY_609_PHY_WRPATH_GATE_TIMING_2_MASK)

#define LPDDR_DENALI_PHY_609_PHY_MEAS_DLY_STEP_ENABLE_2_MASK (0x3F0000U)
#define LPDDR_DENALI_PHY_609_PHY_MEAS_DLY_STEP_ENABLE_2_SHIFT (16U)
/*! PHY_MEAS_DLY_STEP_ENABLE_2 - Data slice training step definition using phy_meas_dly_step_value for slice 2. */
#define LPDDR_DENALI_PHY_609_PHY_MEAS_DLY_STEP_ENABLE_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_609_PHY_MEAS_DLY_STEP_ENABLE_2_SHIFT)) & LPDDR_DENALI_PHY_609_PHY_MEAS_DLY_STEP_ENABLE_2_MASK)

#define LPDDR_DENALI_PHY_609_PHY_RDDATA_EN_DLY_2_MASK (0x1F000000U)
#define LPDDR_DENALI_PHY_609_PHY_RDDATA_EN_DLY_2_SHIFT (24U)
#define LPDDR_DENALI_PHY_609_PHY_RDDATA_EN_DLY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_609_PHY_RDDATA_EN_DLY_2_SHIFT)) & LPDDR_DENALI_PHY_609_PHY_RDDATA_EN_DLY_2_MASK)
/*! @} */

/*! @name DENALI_PHY_610 - DENALI_PHY_610 */
/*! @{ */

#define LPDDR_DENALI_PHY_610_PHY_DQ_DM_SWIZZLE0_2_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_PHY_610_PHY_DQ_DM_SWIZZLE0_2_SHIFT (0U)
#define LPDDR_DENALI_PHY_610_PHY_DQ_DM_SWIZZLE0_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_610_PHY_DQ_DM_SWIZZLE0_2_SHIFT)) & LPDDR_DENALI_PHY_610_PHY_DQ_DM_SWIZZLE0_2_MASK)
/*! @} */

/*! @name DENALI_PHY_612 - DENALI_PHY_612 */
/*! @{ */

#define LPDDR_DENALI_PHY_612_PHY_CLK_WRDQ0_SLAVE_DELAY_2_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_612_PHY_CLK_WRDQ0_SLAVE_DELAY_2_SHIFT (0U)
/*! PHY_CLK_WRDQ0_SLAVE_DELAY_2 - Write clock slave delay setting for DQ0 for slice 2. */
#define LPDDR_DENALI_PHY_612_PHY_CLK_WRDQ0_SLAVE_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_612_PHY_CLK_WRDQ0_SLAVE_DELAY_2_SHIFT)) & LPDDR_DENALI_PHY_612_PHY_CLK_WRDQ0_SLAVE_DELAY_2_MASK)

#define LPDDR_DENALI_PHY_612_PHY_CLK_WRDQ1_SLAVE_DELAY_2_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_612_PHY_CLK_WRDQ1_SLAVE_DELAY_2_SHIFT (16U)
#define LPDDR_DENALI_PHY_612_PHY_CLK_WRDQ1_SLAVE_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_612_PHY_CLK_WRDQ1_SLAVE_DELAY_2_SHIFT)) & LPDDR_DENALI_PHY_612_PHY_CLK_WRDQ1_SLAVE_DELAY_2_MASK)
/*! @} */

/*! @name DENALI_PHY_613 - DENALI_PHY_613 */
/*! @{ */

#define LPDDR_DENALI_PHY_613_PHY_CLK_WRDQ2_SLAVE_DELAY_2_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_613_PHY_CLK_WRDQ2_SLAVE_DELAY_2_SHIFT (0U)
/*! PHY_CLK_WRDQ2_SLAVE_DELAY_2 - Write clock slave delay setting for DQ2 for slice 2. */
#define LPDDR_DENALI_PHY_613_PHY_CLK_WRDQ2_SLAVE_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_613_PHY_CLK_WRDQ2_SLAVE_DELAY_2_SHIFT)) & LPDDR_DENALI_PHY_613_PHY_CLK_WRDQ2_SLAVE_DELAY_2_MASK)

#define LPDDR_DENALI_PHY_613_PHY_CLK_WRDQ3_SLAVE_DELAY_2_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_613_PHY_CLK_WRDQ3_SLAVE_DELAY_2_SHIFT (16U)
/*! PHY_CLK_WRDQ3_SLAVE_DELAY_2 - Write clock slave delay setting for DQ3 for slice 2. */
#define LPDDR_DENALI_PHY_613_PHY_CLK_WRDQ3_SLAVE_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_613_PHY_CLK_WRDQ3_SLAVE_DELAY_2_SHIFT)) & LPDDR_DENALI_PHY_613_PHY_CLK_WRDQ3_SLAVE_DELAY_2_MASK)
/*! @} */

/*! @name DENALI_PHY_614 - DENALI_PHY_614 */
/*! @{ */

#define LPDDR_DENALI_PHY_614_PHY_CLK_WRDQ4_SLAVE_DELAY_2_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_614_PHY_CLK_WRDQ4_SLAVE_DELAY_2_SHIFT (0U)
/*! PHY_CLK_WRDQ4_SLAVE_DELAY_2 - Write clock slave delay setting for DQ4 for slice 2. */
#define LPDDR_DENALI_PHY_614_PHY_CLK_WRDQ4_SLAVE_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_614_PHY_CLK_WRDQ4_SLAVE_DELAY_2_SHIFT)) & LPDDR_DENALI_PHY_614_PHY_CLK_WRDQ4_SLAVE_DELAY_2_MASK)

#define LPDDR_DENALI_PHY_614_PHY_CLK_WRDQ5_SLAVE_DELAY_2_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_614_PHY_CLK_WRDQ5_SLAVE_DELAY_2_SHIFT (16U)
/*! PHY_CLK_WRDQ5_SLAVE_DELAY_2 - Write clock slave delay setting for DQ5 for slice 2. */
#define LPDDR_DENALI_PHY_614_PHY_CLK_WRDQ5_SLAVE_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_614_PHY_CLK_WRDQ5_SLAVE_DELAY_2_SHIFT)) & LPDDR_DENALI_PHY_614_PHY_CLK_WRDQ5_SLAVE_DELAY_2_MASK)
/*! @} */

/*! @name DENALI_PHY_615 - DENALI_PHY_615 */
/*! @{ */

#define LPDDR_DENALI_PHY_615_PHY_CLK_WRDQ6_SLAVE_DELAY_2_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_615_PHY_CLK_WRDQ6_SLAVE_DELAY_2_SHIFT (0U)
/*! PHY_CLK_WRDQ6_SLAVE_DELAY_2 - Write clock slave delay setting for DQ6 for slice 2. */
#define LPDDR_DENALI_PHY_615_PHY_CLK_WRDQ6_SLAVE_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_615_PHY_CLK_WRDQ6_SLAVE_DELAY_2_SHIFT)) & LPDDR_DENALI_PHY_615_PHY_CLK_WRDQ6_SLAVE_DELAY_2_MASK)

#define LPDDR_DENALI_PHY_615_PHY_CLK_WRDQ7_SLAVE_DELAY_2_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_615_PHY_CLK_WRDQ7_SLAVE_DELAY_2_SHIFT (16U)
/*! PHY_CLK_WRDQ7_SLAVE_DELAY_2 - Write clock slave delay setting for DQ7 for slice 2. */
#define LPDDR_DENALI_PHY_615_PHY_CLK_WRDQ7_SLAVE_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_615_PHY_CLK_WRDQ7_SLAVE_DELAY_2_SHIFT)) & LPDDR_DENALI_PHY_615_PHY_CLK_WRDQ7_SLAVE_DELAY_2_MASK)
/*! @} */

/*! @name DENALI_PHY_616 - DENALI_PHY_616 */
/*! @{ */

#define LPDDR_DENALI_PHY_616_PHY_CLK_WRDM_SLAVE_DELAY_2_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_616_PHY_CLK_WRDM_SLAVE_DELAY_2_SHIFT (0U)
/*! PHY_CLK_WRDM_SLAVE_DELAY_2 - Write clock slave delay setting for DM for slice 2. */
#define LPDDR_DENALI_PHY_616_PHY_CLK_WRDM_SLAVE_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_616_PHY_CLK_WRDM_SLAVE_DELAY_2_SHIFT)) & LPDDR_DENALI_PHY_616_PHY_CLK_WRDM_SLAVE_DELAY_2_MASK)

#define LPDDR_DENALI_PHY_616_PHY_CLK_WRDQS_SLAVE_DELAY_2_MASK (0x3FF0000U)
#define LPDDR_DENALI_PHY_616_PHY_CLK_WRDQS_SLAVE_DELAY_2_SHIFT (16U)
/*! PHY_CLK_WRDQS_SLAVE_DELAY_2 - Write clock slave delay setting for DQS for slice 2. */
#define LPDDR_DENALI_PHY_616_PHY_CLK_WRDQS_SLAVE_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_616_PHY_CLK_WRDQS_SLAVE_DELAY_2_SHIFT)) & LPDDR_DENALI_PHY_616_PHY_CLK_WRDQS_SLAVE_DELAY_2_MASK)
/*! @} */

/*! @name DENALI_PHY_626 - DENALI_PHY_626 */
/*! @{ */

#define LPDDR_DENALI_PHY_626_PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_MASK (0x3FFU)
#define LPDDR_DENALI_PHY_626_PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_SHIFT (0U)
/*! PHY_RDDQS_DM_FALL_SLAVE_DELAY_2 - Falling edge read DQS slave delay setting for DM for slice 2. */
#define LPDDR_DENALI_PHY_626_PHY_RDDQS_DM_FALL_SLAVE_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_626_PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_SHIFT)) & LPDDR_DENALI_PHY_626_PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_MASK)

#define LPDDR_DENALI_PHY_626_PHY_RDDQS_GATE_SLAVE_DELAY_2_MASK (0x3FF0000U)
#define LPDDR_DENALI_PHY_626_PHY_RDDQS_GATE_SLAVE_DELAY_2_SHIFT (16U)
/*! PHY_RDDQS_GATE_SLAVE_DELAY_2 - Read DQS slave delay setting for slice 2. */
#define LPDDR_DENALI_PHY_626_PHY_RDDQS_GATE_SLAVE_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_626_PHY_RDDQS_GATE_SLAVE_DELAY_2_SHIFT)) & LPDDR_DENALI_PHY_626_PHY_RDDQS_GATE_SLAVE_DELAY_2_MASK)
/*! @} */

/*! @name DENALI_PHY_799 - DENALI_PHY_799 */
/*! @{ */

#define LPDDR_DENALI_PHY_799_PHY_WRLVL_UPDT_WAIT_CNT_3_MASK (0xFU)
#define LPDDR_DENALI_PHY_799_PHY_WRLVL_UPDT_WAIT_CNT_3_SHIFT (0U)
#define LPDDR_DENALI_PHY_799_PHY_WRLVL_UPDT_WAIT_CNT_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_799_PHY_WRLVL_UPDT_WAIT_CNT_3_SHIFT)) & LPDDR_DENALI_PHY_799_PHY_WRLVL_UPDT_WAIT_CNT_3_MASK)

#define LPDDR_DENALI_PHY_799_PHY_DQ_MASK_3_MASK  (0xFF00U)
#define LPDDR_DENALI_PHY_799_PHY_DQ_MASK_3_SHIFT (8U)
#define LPDDR_DENALI_PHY_799_PHY_DQ_MASK_3(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_799_PHY_DQ_MASK_3_SHIFT)) & LPDDR_DENALI_PHY_799_PHY_DQ_MASK_3_MASK)

#define LPDDR_DENALI_PHY_799_PHY_GTLVL_CAPTURE_CNT_3_MASK (0x3F0000U)
#define LPDDR_DENALI_PHY_799_PHY_GTLVL_CAPTURE_CNT_3_SHIFT (16U)
#define LPDDR_DENALI_PHY_799_PHY_GTLVL_CAPTURE_CNT_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_799_PHY_GTLVL_CAPTURE_CNT_3_SHIFT)) & LPDDR_DENALI_PHY_799_PHY_GTLVL_CAPTURE_CNT_3_MASK)

#define LPDDR_DENALI_PHY_799_PHY_GTLVL_UPDT_WAIT_CNT_3_MASK (0xF000000U)
#define LPDDR_DENALI_PHY_799_PHY_GTLVL_UPDT_WAIT_CNT_3_SHIFT (24U)
#define LPDDR_DENALI_PHY_799_PHY_GTLVL_UPDT_WAIT_CNT_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_799_PHY_GTLVL_UPDT_WAIT_CNT_3_SHIFT)) & LPDDR_DENALI_PHY_799_PHY_GTLVL_UPDT_WAIT_CNT_3_MASK)
/*! @} */

/*! @name DENALI_PHY_801 - DENALI_PHY_801 */
/*! @{ */

#define LPDDR_DENALI_PHY_801_PHY_RDLVL_DATA_MASK_3_MASK (0xFFU)
#define LPDDR_DENALI_PHY_801_PHY_RDLVL_DATA_MASK_3_SHIFT (0U)
#define LPDDR_DENALI_PHY_801_PHY_RDLVL_DATA_MASK_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_801_PHY_RDLVL_DATA_MASK_3_SHIFT)) & LPDDR_DENALI_PHY_801_PHY_RDLVL_DATA_MASK_3_MASK)

#define LPDDR_DENALI_PHY_801_PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_MASK (0xFF00U)
#define LPDDR_DENALI_PHY_801_PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_SHIFT (8U)
#define LPDDR_DENALI_PHY_801_PHY_WDQLVL_CLK_JITTER_TOLERANCE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_801_PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_SHIFT)) & LPDDR_DENALI_PHY_801_PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_MASK)

#define LPDDR_DENALI_PHY_801_PHY_WDQLVL_BURST_CNT_3_MASK (0x3F0000U)
#define LPDDR_DENALI_PHY_801_PHY_WDQLVL_BURST_CNT_3_SHIFT (16U)
/*! PHY_WDQLVL_BURST_CNT_3 - Defines the write/read burst length in bytes during the write data leveling sequence for slice 3. */
#define LPDDR_DENALI_PHY_801_PHY_WDQLVL_BURST_CNT_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_801_PHY_WDQLVL_BURST_CNT_3_SHIFT)) & LPDDR_DENALI_PHY_801_PHY_WDQLVL_BURST_CNT_3_MASK)

#define LPDDR_DENALI_PHY_801_PHY_WDQLVL_PATT_3_MASK (0x7000000U)
#define LPDDR_DENALI_PHY_801_PHY_WDQLVL_PATT_3_SHIFT (24U)
#define LPDDR_DENALI_PHY_801_PHY_WDQLVL_PATT_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_801_PHY_WDQLVL_PATT_3_SHIFT)) & LPDDR_DENALI_PHY_801_PHY_WDQLVL_PATT_3_MASK)
/*! @} */

/*! @name DENALI_PHY_840 - DENALI_PHY_840 */
/*! @{ */

#define LPDDR_DENALI_PHY_840_PHY_SLV_DLY_CTRL_GATE_DISABLE_3_MASK (0x1U)
#define LPDDR_DENALI_PHY_840_PHY_SLV_DLY_CTRL_GATE_DISABLE_3_SHIFT (0U)
#define LPDDR_DENALI_PHY_840_PHY_SLV_DLY_CTRL_GATE_DISABLE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_840_PHY_SLV_DLY_CTRL_GATE_DISABLE_3_SHIFT)) & LPDDR_DENALI_PHY_840_PHY_SLV_DLY_CTRL_GATE_DISABLE_3_MASK)

#define LPDDR_DENALI_PHY_840_PHY_RDPATH_GATE_DISABLE_3_MASK (0x100U)
#define LPDDR_DENALI_PHY_840_PHY_RDPATH_GATE_DISABLE_3_SHIFT (8U)
#define LPDDR_DENALI_PHY_840_PHY_RDPATH_GATE_DISABLE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_840_PHY_RDPATH_GATE_DISABLE_3_SHIFT)) & LPDDR_DENALI_PHY_840_PHY_RDPATH_GATE_DISABLE_3_MASK)

#define LPDDR_DENALI_PHY_840_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_MASK (0x10000U)
#define LPDDR_DENALI_PHY_840_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_SHIFT (16U)
#define LPDDR_DENALI_PHY_840_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_840_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_SHIFT)) & LPDDR_DENALI_PHY_840_PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_MASK)

#define LPDDR_DENALI_PHY_840_PHY_SLICE_PWR_RDC_DISABLE_3_MASK (0x1000000U)
#define LPDDR_DENALI_PHY_840_PHY_SLICE_PWR_RDC_DISABLE_3_SHIFT (24U)
#define LPDDR_DENALI_PHY_840_PHY_SLICE_PWR_RDC_DISABLE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_840_PHY_SLICE_PWR_RDC_DISABLE_3_SHIFT)) & LPDDR_DENALI_PHY_840_PHY_SLICE_PWR_RDC_DISABLE_3_MASK)
/*! @} */

/*! @name DENALI_PHY_841 - DENALI_PHY_841 */
/*! @{ */

#define LPDDR_DENALI_PHY_841_PHY_DQ_TSEL_ENABLE_3_MASK (0x7U)
#define LPDDR_DENALI_PHY_841_PHY_DQ_TSEL_ENABLE_3_SHIFT (0U)
#define LPDDR_DENALI_PHY_841_PHY_DQ_TSEL_ENABLE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_841_PHY_DQ_TSEL_ENABLE_3_SHIFT)) & LPDDR_DENALI_PHY_841_PHY_DQ_TSEL_ENABLE_3_MASK)

#define LPDDR_DENALI_PHY_841_PHY_DQ_TSEL_SELECT_3_MASK (0xFFFF00U)
#define LPDDR_DENALI_PHY_841_PHY_DQ_TSEL_SELECT_3_SHIFT (8U)
/*! PHY_DQ_TSEL_SELECT_3 - Operation type tsel select values for DQ/DM signals for slice 3. */
#define LPDDR_DENALI_PHY_841_PHY_DQ_TSEL_SELECT_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_841_PHY_DQ_TSEL_SELECT_3_SHIFT)) & LPDDR_DENALI_PHY_841_PHY_DQ_TSEL_SELECT_3_MASK)

#define LPDDR_DENALI_PHY_841_PHY_DQS_TSEL_ENABLE_3_MASK (0x7000000U)
#define LPDDR_DENALI_PHY_841_PHY_DQS_TSEL_ENABLE_3_SHIFT (24U)
#define LPDDR_DENALI_PHY_841_PHY_DQS_TSEL_ENABLE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_841_PHY_DQS_TSEL_ENABLE_3_SHIFT)) & LPDDR_DENALI_PHY_841_PHY_DQS_TSEL_ENABLE_3_MASK)
/*! @} */

/*! @name DENALI_PHY_842 - DENALI_PHY_842 */
/*! @{ */

#define LPDDR_DENALI_PHY_842_PHY_DQS_TSEL_SELECT_3_MASK (0xFFFFU)
#define LPDDR_DENALI_PHY_842_PHY_DQS_TSEL_SELECT_3_SHIFT (0U)
/*! PHY_DQS_TSEL_SELECT_3 - Operation type tsel select values for DQS signals for slice 3. */
#define LPDDR_DENALI_PHY_842_PHY_DQS_TSEL_SELECT_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_842_PHY_DQS_TSEL_SELECT_3_SHIFT)) & LPDDR_DENALI_PHY_842_PHY_DQS_TSEL_SELECT_3_MASK)

#define LPDDR_DENALI_PHY_842_PHY_TWO_CYC_PREAMBLE_3_MASK (0x30000U)
#define LPDDR_DENALI_PHY_842_PHY_TWO_CYC_PREAMBLE_3_SHIFT (16U)
#define LPDDR_DENALI_PHY_842_PHY_TWO_CYC_PREAMBLE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_842_PHY_TWO_CYC_PREAMBLE_3_SHIFT)) & LPDDR_DENALI_PHY_842_PHY_TWO_CYC_PREAMBLE_3_MASK)

#define LPDDR_DENALI_PHY_842_PHY_VREF_INITIAL_START_POINT_3_MASK (0x7F000000U)
#define LPDDR_DENALI_PHY_842_PHY_VREF_INITIAL_START_POINT_3_SHIFT (24U)
#define LPDDR_DENALI_PHY_842_PHY_VREF_INITIAL_START_POINT_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_842_PHY_VREF_INITIAL_START_POINT_3_SHIFT)) & LPDDR_DENALI_PHY_842_PHY_VREF_INITIAL_START_POINT_3_MASK)
/*! @} */

/*! @name DENALI_PHY_843 - DENALI_PHY_843 */
/*! @{ */

#define LPDDR_DENALI_PHY_843_PHY_VREF_INITIAL_STOP_POINT_3_MASK (0x7FU)
#define LPDDR_DENALI_PHY_843_PHY_VREF_INITIAL_STOP_POINT_3_SHIFT (0U)
/*! PHY_VREF_INITIAL_STOP_POINT_3 - Data slice initial VREF training stop value for slice 3. When
 *    programming the write DQ VREF stop point parameter, must set it equal to a multiple of the VREF
 *    (step size + start point).
 */
#define LPDDR_DENALI_PHY_843_PHY_VREF_INITIAL_STOP_POINT_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_843_PHY_VREF_INITIAL_STOP_POINT_3_SHIFT)) & LPDDR_DENALI_PHY_843_PHY_VREF_INITIAL_STOP_POINT_3_MASK)

#define LPDDR_DENALI_PHY_843_PHY_VREF_TRAINING_CTRL_3_MASK (0x300U)
#define LPDDR_DENALI_PHY_843_PHY_VREF_TRAINING_CTRL_3_SHIFT (8U)
#define LPDDR_DENALI_PHY_843_PHY_VREF_TRAINING_CTRL_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_843_PHY_VREF_TRAINING_CTRL_3_SHIFT)) & LPDDR_DENALI_PHY_843_PHY_VREF_TRAINING_CTRL_3_MASK)

#define LPDDR_DENALI_PHY_843_PHY_NTP_TRAIN_EN_3_MASK (0x10000U)
#define LPDDR_DENALI_PHY_843_PHY_NTP_TRAIN_EN_3_SHIFT (16U)
/*! PHY_NTP_TRAIN_EN_3
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPDDR_DENALI_PHY_843_PHY_NTP_TRAIN_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_843_PHY_NTP_TRAIN_EN_3_SHIFT)) & LPDDR_DENALI_PHY_843_PHY_NTP_TRAIN_EN_3_MASK)

#define LPDDR_DENALI_PHY_843_PHY_NTP_WDQ_STEP_SIZE_3_MASK (0xFF000000U)
#define LPDDR_DENALI_PHY_843_PHY_NTP_WDQ_STEP_SIZE_3_SHIFT (24U)
#define LPDDR_DENALI_PHY_843_PHY_NTP_WDQ_STEP_SIZE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_843_PHY_NTP_WDQ_STEP_SIZE_3_SHIFT)) & LPDDR_DENALI_PHY_843_PHY_NTP_WDQ_STEP_SIZE_3_MASK)
/*! @} */

/*! @name DENALI_PHY_848 - DENALI_PHY_848 */
/*! @{ */

#define LPDDR_DENALI_PHY_848_PHY_PAD_DQS_RX_DCD_3_MASK (0x1FU)
#define LPDDR_DENALI_PHY_848_PHY_PAD_DQS_RX_DCD_3_SHIFT (0U)
/*! PHY_PAD_DQS_RX_DCD_3 - Controls RX_DCD pin for dqs pad for slice 3. */
#define LPDDR_DENALI_PHY_848_PHY_PAD_DQS_RX_DCD_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_848_PHY_PAD_DQS_RX_DCD_3_SHIFT)) & LPDDR_DENALI_PHY_848_PHY_PAD_DQS_RX_DCD_3_MASK)

#define LPDDR_DENALI_PHY_848_PHY_PAD_FDBK_RX_DCD_3_MASK (0x1F00U)
#define LPDDR_DENALI_PHY_848_PHY_PAD_FDBK_RX_DCD_3_SHIFT (8U)
/*! PHY_PAD_FDBK_RX_DCD_3 - Controls RX_DCD pin for fdbk pad for slice 3. */
#define LPDDR_DENALI_PHY_848_PHY_PAD_FDBK_RX_DCD_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_848_PHY_PAD_FDBK_RX_DCD_3_SHIFT)) & LPDDR_DENALI_PHY_848_PHY_PAD_FDBK_RX_DCD_3_MASK)

#define LPDDR_DENALI_PHY_848_PHY_PAD_DSLICE_IO_CFG_3_MASK (0x7F0000U)
#define LPDDR_DENALI_PHY_848_PHY_PAD_DSLICE_IO_CFG_3_SHIFT (16U)
/*! PHY_PAD_DSLICE_IO_CFG_3 - Controls PCLK/PARK pin for IO pad for slice 3. */
#define LPDDR_DENALI_PHY_848_PHY_PAD_DSLICE_IO_CFG_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_848_PHY_PAD_DSLICE_IO_CFG_3_SHIFT)) & LPDDR_DENALI_PHY_848_PHY_PAD_DSLICE_IO_CFG_3_MASK)
/*! @} */

/*! @name DENALI_PHY_856 - DENALI_PHY_856 */
/*! @{ */

#define LPDDR_DENALI_PHY_856_PHY_VREF_SETTING_TIME_3_MASK (0xFFFFU)
#define LPDDR_DENALI_PHY_856_PHY_VREF_SETTING_TIME_3_SHIFT (0U)
#define LPDDR_DENALI_PHY_856_PHY_VREF_SETTING_TIME_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_856_PHY_VREF_SETTING_TIME_3_SHIFT)) & LPDDR_DENALI_PHY_856_PHY_VREF_SETTING_TIME_3_MASK)

#define LPDDR_DENALI_PHY_856_PHY_PAD_VREF_CTRL_DQ_3_MASK (0xFFF0000U)
#define LPDDR_DENALI_PHY_856_PHY_PAD_VREF_CTRL_DQ_3_SHIFT (16U)
#define LPDDR_DENALI_PHY_856_PHY_PAD_VREF_CTRL_DQ_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_856_PHY_PAD_VREF_CTRL_DQ_3_SHIFT)) & LPDDR_DENALI_PHY_856_PHY_PAD_VREF_CTRL_DQ_3_MASK)
/*! @} */

/*! @name DENALI_PHY_857 - DENALI_PHY_857 */
/*! @{ */

#define LPDDR_DENALI_PHY_857_PHY_PER_CS_TRAINING_EN_3_MASK (0x1U)
#define LPDDR_DENALI_PHY_857_PHY_PER_CS_TRAINING_EN_3_SHIFT (0U)
#define LPDDR_DENALI_PHY_857_PHY_PER_CS_TRAINING_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_857_PHY_PER_CS_TRAINING_EN_3_SHIFT)) & LPDDR_DENALI_PHY_857_PHY_PER_CS_TRAINING_EN_3_MASK)

#define LPDDR_DENALI_PHY_857_PHY_DQ_IE_TIMING_3_MASK (0xFF00U)
#define LPDDR_DENALI_PHY_857_PHY_DQ_IE_TIMING_3_SHIFT (8U)
#define LPDDR_DENALI_PHY_857_PHY_DQ_IE_TIMING_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_857_PHY_DQ_IE_TIMING_3_SHIFT)) & LPDDR_DENALI_PHY_857_PHY_DQ_IE_TIMING_3_MASK)

#define LPDDR_DENALI_PHY_857_PHY_DQS_IE_TIMING_3_MASK (0xFF0000U)
#define LPDDR_DENALI_PHY_857_PHY_DQS_IE_TIMING_3_SHIFT (16U)
#define LPDDR_DENALI_PHY_857_PHY_DQS_IE_TIMING_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_857_PHY_DQS_IE_TIMING_3_SHIFT)) & LPDDR_DENALI_PHY_857_PHY_DQS_IE_TIMING_3_MASK)

#define LPDDR_DENALI_PHY_857_PHY_RDDATA_EN_IE_DLY_3_MASK (0x3000000U)
#define LPDDR_DENALI_PHY_857_PHY_RDDATA_EN_IE_DLY_3_SHIFT (24U)
#define LPDDR_DENALI_PHY_857_PHY_RDDATA_EN_IE_DLY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_857_PHY_RDDATA_EN_IE_DLY_3_SHIFT)) & LPDDR_DENALI_PHY_857_PHY_RDDATA_EN_IE_DLY_3_MASK)
/*! @} */

/*! @name DENALI_PHY_858 - DENALI_PHY_858 */
/*! @{ */

#define LPDDR_DENALI_PHY_858_PHY_IE_MODE_3_MASK  (0x3U)
#define LPDDR_DENALI_PHY_858_PHY_IE_MODE_3_SHIFT (0U)
#define LPDDR_DENALI_PHY_858_PHY_IE_MODE_3(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_858_PHY_IE_MODE_3_SHIFT)) & LPDDR_DENALI_PHY_858_PHY_IE_MODE_3_MASK)

#define LPDDR_DENALI_PHY_858_PHY_DBI_MODE_3_MASK (0x100U)
#define LPDDR_DENALI_PHY_858_PHY_DBI_MODE_3_SHIFT (8U)
/*! PHY_DBI_MODE_3
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPDDR_DENALI_PHY_858_PHY_DBI_MODE_3(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_858_PHY_DBI_MODE_3_SHIFT)) & LPDDR_DENALI_PHY_858_PHY_DBI_MODE_3_MASK)

#define LPDDR_DENALI_PHY_858_PHY_RDDATA_EN_TSEL_DLY_3_MASK (0x1F0000U)
#define LPDDR_DENALI_PHY_858_PHY_RDDATA_EN_TSEL_DLY_3_SHIFT (16U)
#define LPDDR_DENALI_PHY_858_PHY_RDDATA_EN_TSEL_DLY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_858_PHY_RDDATA_EN_TSEL_DLY_3_SHIFT)) & LPDDR_DENALI_PHY_858_PHY_RDDATA_EN_TSEL_DLY_3_MASK)

#define LPDDR_DENALI_PHY_858_PHY_RDDATA_EN_OE_DLY_3_MASK (0x1F000000U)
#define LPDDR_DENALI_PHY_858_PHY_RDDATA_EN_OE_DLY_3_SHIFT (24U)
#define LPDDR_DENALI_PHY_858_PHY_RDDATA_EN_OE_DLY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_858_PHY_RDDATA_EN_OE_DLY_3_SHIFT)) & LPDDR_DENALI_PHY_858_PHY_RDDATA_EN_OE_DLY_3_MASK)
/*! @} */

/*! @name DENALI_PHY_860 - DENALI_PHY_860 */
/*! @{ */

#define LPDDR_DENALI_PHY_860_PHY_MASTER_DELAY_WAIT_3_MASK (0xFFU)
#define LPDDR_DENALI_PHY_860_PHY_MASTER_DELAY_WAIT_3_SHIFT (0U)
#define LPDDR_DENALI_PHY_860_PHY_MASTER_DELAY_WAIT_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_860_PHY_MASTER_DELAY_WAIT_3_SHIFT)) & LPDDR_DENALI_PHY_860_PHY_MASTER_DELAY_WAIT_3_MASK)

#define LPDDR_DENALI_PHY_860_PHY_MASTER_DELAY_HALF_MEASURE_3_MASK (0xFF00U)
#define LPDDR_DENALI_PHY_860_PHY_MASTER_DELAY_HALF_MEASURE_3_SHIFT (8U)
/*! PHY_MASTER_DELAY_HALF_MEASURE_3 - Defines the number of delay line elements to be considered in
 *    determing whether to lock to a half clock cycle in the data slice master for slice 3.
 */
#define LPDDR_DENALI_PHY_860_PHY_MASTER_DELAY_HALF_MEASURE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_860_PHY_MASTER_DELAY_HALF_MEASURE_3_SHIFT)) & LPDDR_DENALI_PHY_860_PHY_MASTER_DELAY_HALF_MEASURE_3_MASK)

#define LPDDR_DENALI_PHY_860_PHY_RPTR_UPDATE_3_MASK (0xF0000U)
#define LPDDR_DENALI_PHY_860_PHY_RPTR_UPDATE_3_SHIFT (16U)
#define LPDDR_DENALI_PHY_860_PHY_RPTR_UPDATE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_860_PHY_RPTR_UPDATE_3_SHIFT)) & LPDDR_DENALI_PHY_860_PHY_RPTR_UPDATE_3_MASK)

#define LPDDR_DENALI_PHY_860_PHY_WRLVL_DLY_STEP_3_MASK (0xFF000000U)
#define LPDDR_DENALI_PHY_860_PHY_WRLVL_DLY_STEP_3_SHIFT (24U)
#define LPDDR_DENALI_PHY_860_PHY_WRLVL_DLY_STEP_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_860_PHY_WRLVL_DLY_STEP_3_SHIFT)) & LPDDR_DENALI_PHY_860_PHY_WRLVL_DLY_STEP_3_MASK)
/*! @} */

/*! @name DENALI_PHY_861 - DENALI_PHY_861 */
/*! @{ */

#define LPDDR_DENALI_PHY_861_PHY_WRLVL_DLY_FINE_STEP_3_MASK (0xFU)
#define LPDDR_DENALI_PHY_861_PHY_WRLVL_DLY_FINE_STEP_3_SHIFT (0U)
#define LPDDR_DENALI_PHY_861_PHY_WRLVL_DLY_FINE_STEP_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_861_PHY_WRLVL_DLY_FINE_STEP_3_SHIFT)) & LPDDR_DENALI_PHY_861_PHY_WRLVL_DLY_FINE_STEP_3_MASK)

#define LPDDR_DENALI_PHY_861_PHY_WRLVL_RESP_WAIT_CNT_3_MASK (0x3F00U)
#define LPDDR_DENALI_PHY_861_PHY_WRLVL_RESP_WAIT_CNT_3_SHIFT (8U)
/*! PHY_WRLVL_RESP_WAIT_CNT_3 - Defines the number of cycles to wait between dfi_wrlvl_strobe and
 *    the sampling of the DQs during write leveling for slice 3.
 */
#define LPDDR_DENALI_PHY_861_PHY_WRLVL_RESP_WAIT_CNT_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_861_PHY_WRLVL_RESP_WAIT_CNT_3_SHIFT)) & LPDDR_DENALI_PHY_861_PHY_WRLVL_RESP_WAIT_CNT_3_MASK)

#define LPDDR_DENALI_PHY_861_PHY_GTLVL_DLY_STEP_3_MASK (0xF0000U)
#define LPDDR_DENALI_PHY_861_PHY_GTLVL_DLY_STEP_3_SHIFT (16U)
#define LPDDR_DENALI_PHY_861_PHY_GTLVL_DLY_STEP_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_861_PHY_GTLVL_DLY_STEP_3_SHIFT)) & LPDDR_DENALI_PHY_861_PHY_GTLVL_DLY_STEP_3_MASK)

#define LPDDR_DENALI_PHY_861_PHY_GTLVL_RESP_WAIT_CNT_3_MASK (0x1F000000U)
#define LPDDR_DENALI_PHY_861_PHY_GTLVL_RESP_WAIT_CNT_3_SHIFT (24U)
#define LPDDR_DENALI_PHY_861_PHY_GTLVL_RESP_WAIT_CNT_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_861_PHY_GTLVL_RESP_WAIT_CNT_3_SHIFT)) & LPDDR_DENALI_PHY_861_PHY_GTLVL_RESP_WAIT_CNT_3_MASK)
/*! @} */

/*! @name DENALI_PHY_863 - DENALI_PHY_863 */
/*! @{ */

#define LPDDR_DENALI_PHY_863_PHY_WDQLVL_DLY_STEP_3_MASK (0xFFU)
#define LPDDR_DENALI_PHY_863_PHY_WDQLVL_DLY_STEP_3_SHIFT (0U)
#define LPDDR_DENALI_PHY_863_PHY_WDQLVL_DLY_STEP_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_863_PHY_WDQLVL_DLY_STEP_3_SHIFT)) & LPDDR_DENALI_PHY_863_PHY_WDQLVL_DLY_STEP_3_MASK)

#define LPDDR_DENALI_PHY_863_PHY_WDQLVL_QTR_DLY_STEP_3_MASK (0xF00U)
#define LPDDR_DENALI_PHY_863_PHY_WDQLVL_QTR_DLY_STEP_3_SHIFT (8U)
#define LPDDR_DENALI_PHY_863_PHY_WDQLVL_QTR_DLY_STEP_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_863_PHY_WDQLVL_QTR_DLY_STEP_3_SHIFT)) & LPDDR_DENALI_PHY_863_PHY_WDQLVL_QTR_DLY_STEP_3_MASK)

#define LPDDR_DENALI_PHY_863_PHY_TOGGLE_PRE_SUPPORT_3_MASK (0x10000U)
#define LPDDR_DENALI_PHY_863_PHY_TOGGLE_PRE_SUPPORT_3_SHIFT (16U)
/*! PHY_TOGGLE_PRE_SUPPORT_3 - Support the toggle read preamble for LPDDR4 for slice 3.
 *  0b0..Static read preamble
 *  0b1..Toggling read preamble
 */
#define LPDDR_DENALI_PHY_863_PHY_TOGGLE_PRE_SUPPORT_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_863_PHY_TOGGLE_PRE_SUPPORT_3_SHIFT)) & LPDDR_DENALI_PHY_863_PHY_TOGGLE_PRE_SUPPORT_3_MASK)

#define LPDDR_DENALI_PHY_863_PHY_RDLVL_DLY_STEP_3_MASK (0xF000000U)
#define LPDDR_DENALI_PHY_863_PHY_RDLVL_DLY_STEP_3_SHIFT (24U)
#define LPDDR_DENALI_PHY_863_PHY_RDLVL_DLY_STEP_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_863_PHY_RDLVL_DLY_STEP_3_SHIFT)) & LPDDR_DENALI_PHY_863_PHY_RDLVL_DLY_STEP_3_MASK)
/*! @} */

/*! @name DENALI_PHY_864 - DENALI_PHY_864 */
/*! @{ */

#define LPDDR_DENALI_PHY_864_PHY_RDLVL_MAX_EDGE_3_MASK (0x3FFU)
#define LPDDR_DENALI_PHY_864_PHY_RDLVL_MAX_EDGE_3_SHIFT (0U)
/*! PHY_RDLVL_MAX_EDGE_3 - Provides the maximun rdlvl slave delay search window for read eye training for slice 3. */
#define LPDDR_DENALI_PHY_864_PHY_RDLVL_MAX_EDGE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_864_PHY_RDLVL_MAX_EDGE_3_SHIFT)) & LPDDR_DENALI_PHY_864_PHY_RDLVL_MAX_EDGE_3_MASK)
/*! @} */

/*! @name DENALI_PHY_865 - DENALI_PHY_865 */
/*! @{ */

#define LPDDR_DENALI_PHY_865_PHY_WRPATH_GATE_DISABLE_3_MASK (0x3U)
#define LPDDR_DENALI_PHY_865_PHY_WRPATH_GATE_DISABLE_3_SHIFT (0U)
#define LPDDR_DENALI_PHY_865_PHY_WRPATH_GATE_DISABLE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_865_PHY_WRPATH_GATE_DISABLE_3_SHIFT)) & LPDDR_DENALI_PHY_865_PHY_WRPATH_GATE_DISABLE_3_MASK)

#define LPDDR_DENALI_PHY_865_PHY_WRPATH_GATE_TIMING_3_MASK (0x700U)
#define LPDDR_DENALI_PHY_865_PHY_WRPATH_GATE_TIMING_3_SHIFT (8U)
#define LPDDR_DENALI_PHY_865_PHY_WRPATH_GATE_TIMING_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_865_PHY_WRPATH_GATE_TIMING_3_SHIFT)) & LPDDR_DENALI_PHY_865_PHY_WRPATH_GATE_TIMING_3_MASK)

#define LPDDR_DENALI_PHY_865_PHY_MEAS_DLY_STEP_ENABLE_3_MASK (0x3F0000U)
#define LPDDR_DENALI_PHY_865_PHY_MEAS_DLY_STEP_ENABLE_3_SHIFT (16U)
/*! PHY_MEAS_DLY_STEP_ENABLE_3 - Data slice training step definition using phy_meas_dly_step_value for slice 3. */
#define LPDDR_DENALI_PHY_865_PHY_MEAS_DLY_STEP_ENABLE_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_865_PHY_MEAS_DLY_STEP_ENABLE_3_SHIFT)) & LPDDR_DENALI_PHY_865_PHY_MEAS_DLY_STEP_ENABLE_3_MASK)

#define LPDDR_DENALI_PHY_865_PHY_RDDATA_EN_DLY_3_MASK (0x1F000000U)
#define LPDDR_DENALI_PHY_865_PHY_RDDATA_EN_DLY_3_SHIFT (24U)
#define LPDDR_DENALI_PHY_865_PHY_RDDATA_EN_DLY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_865_PHY_RDDATA_EN_DLY_3_SHIFT)) & LPDDR_DENALI_PHY_865_PHY_RDDATA_EN_DLY_3_MASK)
/*! @} */

/*! @name DENALI_PHY_866 - DENALI_PHY_866 */
/*! @{ */

#define LPDDR_DENALI_PHY_866_PHY_DQ_DM_SWIZZLE0_3_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_PHY_866_PHY_DQ_DM_SWIZZLE0_3_SHIFT (0U)
#define LPDDR_DENALI_PHY_866_PHY_DQ_DM_SWIZZLE0_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_866_PHY_DQ_DM_SWIZZLE0_3_SHIFT)) & LPDDR_DENALI_PHY_866_PHY_DQ_DM_SWIZZLE0_3_MASK)
/*! @} */

/*! @name DENALI_PHY_868 - DENALI_PHY_868 */
/*! @{ */

#define LPDDR_DENALI_PHY_868_PHY_CLK_WRDQ0_SLAVE_DELAY_3_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_868_PHY_CLK_WRDQ0_SLAVE_DELAY_3_SHIFT (0U)
/*! PHY_CLK_WRDQ0_SLAVE_DELAY_3 - Write clock slave delay setting for DQ0 for slice 3. */
#define LPDDR_DENALI_PHY_868_PHY_CLK_WRDQ0_SLAVE_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_868_PHY_CLK_WRDQ0_SLAVE_DELAY_3_SHIFT)) & LPDDR_DENALI_PHY_868_PHY_CLK_WRDQ0_SLAVE_DELAY_3_MASK)

#define LPDDR_DENALI_PHY_868_PHY_CLK_WRDQ1_SLAVE_DELAY_3_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_868_PHY_CLK_WRDQ1_SLAVE_DELAY_3_SHIFT (16U)
#define LPDDR_DENALI_PHY_868_PHY_CLK_WRDQ1_SLAVE_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_868_PHY_CLK_WRDQ1_SLAVE_DELAY_3_SHIFT)) & LPDDR_DENALI_PHY_868_PHY_CLK_WRDQ1_SLAVE_DELAY_3_MASK)
/*! @} */

/*! @name DENALI_PHY_869 - DENALI_PHY_869 */
/*! @{ */

#define LPDDR_DENALI_PHY_869_PHY_CLK_WRDQ2_SLAVE_DELAY_3_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_869_PHY_CLK_WRDQ2_SLAVE_DELAY_3_SHIFT (0U)
/*! PHY_CLK_WRDQ2_SLAVE_DELAY_3 - Write clock slave delay setting for DQ2 for slice 3. */
#define LPDDR_DENALI_PHY_869_PHY_CLK_WRDQ2_SLAVE_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_869_PHY_CLK_WRDQ2_SLAVE_DELAY_3_SHIFT)) & LPDDR_DENALI_PHY_869_PHY_CLK_WRDQ2_SLAVE_DELAY_3_MASK)

#define LPDDR_DENALI_PHY_869_PHY_CLK_WRDQ3_SLAVE_DELAY_3_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_869_PHY_CLK_WRDQ3_SLAVE_DELAY_3_SHIFT (16U)
/*! PHY_CLK_WRDQ3_SLAVE_DELAY_3 - Write clock slave delay setting for DQ3 for slice 3. */
#define LPDDR_DENALI_PHY_869_PHY_CLK_WRDQ3_SLAVE_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_869_PHY_CLK_WRDQ3_SLAVE_DELAY_3_SHIFT)) & LPDDR_DENALI_PHY_869_PHY_CLK_WRDQ3_SLAVE_DELAY_3_MASK)
/*! @} */

/*! @name DENALI_PHY_870 - DENALI_PHY_870 */
/*! @{ */

#define LPDDR_DENALI_PHY_870_PHY_CLK_WRDQ4_SLAVE_DELAY_3_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_870_PHY_CLK_WRDQ4_SLAVE_DELAY_3_SHIFT (0U)
/*! PHY_CLK_WRDQ4_SLAVE_DELAY_3 - Write clock slave delay setting for DQ4 for slice 3. */
#define LPDDR_DENALI_PHY_870_PHY_CLK_WRDQ4_SLAVE_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_870_PHY_CLK_WRDQ4_SLAVE_DELAY_3_SHIFT)) & LPDDR_DENALI_PHY_870_PHY_CLK_WRDQ4_SLAVE_DELAY_3_MASK)

#define LPDDR_DENALI_PHY_870_PHY_CLK_WRDQ5_SLAVE_DELAY_3_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_870_PHY_CLK_WRDQ5_SLAVE_DELAY_3_SHIFT (16U)
/*! PHY_CLK_WRDQ5_SLAVE_DELAY_3 - Write clock slave delay setting for DQ5 for slice 3. */
#define LPDDR_DENALI_PHY_870_PHY_CLK_WRDQ5_SLAVE_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_870_PHY_CLK_WRDQ5_SLAVE_DELAY_3_SHIFT)) & LPDDR_DENALI_PHY_870_PHY_CLK_WRDQ5_SLAVE_DELAY_3_MASK)
/*! @} */

/*! @name DENALI_PHY_871 - DENALI_PHY_871 */
/*! @{ */

#define LPDDR_DENALI_PHY_871_PHY_CLK_WRDQ6_SLAVE_DELAY_3_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_871_PHY_CLK_WRDQ6_SLAVE_DELAY_3_SHIFT (0U)
/*! PHY_CLK_WRDQ6_SLAVE_DELAY_3 - Write clock slave delay setting for DQ6 for slice 3. */
#define LPDDR_DENALI_PHY_871_PHY_CLK_WRDQ6_SLAVE_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_871_PHY_CLK_WRDQ6_SLAVE_DELAY_3_SHIFT)) & LPDDR_DENALI_PHY_871_PHY_CLK_WRDQ6_SLAVE_DELAY_3_MASK)

#define LPDDR_DENALI_PHY_871_PHY_CLK_WRDQ7_SLAVE_DELAY_3_MASK (0x7FF0000U)
#define LPDDR_DENALI_PHY_871_PHY_CLK_WRDQ7_SLAVE_DELAY_3_SHIFT (16U)
/*! PHY_CLK_WRDQ7_SLAVE_DELAY_3 - Write clock slave delay setting for DQ7 for slice 3. */
#define LPDDR_DENALI_PHY_871_PHY_CLK_WRDQ7_SLAVE_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_871_PHY_CLK_WRDQ7_SLAVE_DELAY_3_SHIFT)) & LPDDR_DENALI_PHY_871_PHY_CLK_WRDQ7_SLAVE_DELAY_3_MASK)
/*! @} */

/*! @name DENALI_PHY_872 - DENALI_PHY_872 */
/*! @{ */

#define LPDDR_DENALI_PHY_872_PHY_CLK_WRDM_SLAVE_DELAY_3_MASK (0x7FFU)
#define LPDDR_DENALI_PHY_872_PHY_CLK_WRDM_SLAVE_DELAY_3_SHIFT (0U)
/*! PHY_CLK_WRDM_SLAVE_DELAY_3 - Write clock slave delay setting for DM for slice 3. */
#define LPDDR_DENALI_PHY_872_PHY_CLK_WRDM_SLAVE_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_872_PHY_CLK_WRDM_SLAVE_DELAY_3_SHIFT)) & LPDDR_DENALI_PHY_872_PHY_CLK_WRDM_SLAVE_DELAY_3_MASK)

#define LPDDR_DENALI_PHY_872_PHY_CLK_WRDQS_SLAVE_DELAY_3_MASK (0x3FF0000U)
#define LPDDR_DENALI_PHY_872_PHY_CLK_WRDQS_SLAVE_DELAY_3_SHIFT (16U)
/*! PHY_CLK_WRDQS_SLAVE_DELAY_3 - Write clock slave delay setting for DQS for slice 3. */
#define LPDDR_DENALI_PHY_872_PHY_CLK_WRDQS_SLAVE_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_872_PHY_CLK_WRDQS_SLAVE_DELAY_3_SHIFT)) & LPDDR_DENALI_PHY_872_PHY_CLK_WRDQS_SLAVE_DELAY_3_MASK)
/*! @} */

/*! @name DENALI_PHY_882 - DENALI_PHY_882 */
/*! @{ */

#define LPDDR_DENALI_PHY_882_PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_MASK (0x3FFU)
#define LPDDR_DENALI_PHY_882_PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_SHIFT (0U)
/*! PHY_RDDQS_DM_FALL_SLAVE_DELAY_3 - Falling edge read DQS slave delay setting for DM for slice 3. */
#define LPDDR_DENALI_PHY_882_PHY_RDDQS_DM_FALL_SLAVE_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_882_PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_SHIFT)) & LPDDR_DENALI_PHY_882_PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_MASK)

#define LPDDR_DENALI_PHY_882_PHY_RDDQS_GATE_SLAVE_DELAY_3_MASK (0x3FF0000U)
#define LPDDR_DENALI_PHY_882_PHY_RDDQS_GATE_SLAVE_DELAY_3_SHIFT (16U)
/*! PHY_RDDQS_GATE_SLAVE_DELAY_3 - Read DQS slave delay setting for slice 3. */
#define LPDDR_DENALI_PHY_882_PHY_RDDQS_GATE_SLAVE_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_882_PHY_RDDQS_GATE_SLAVE_DELAY_3_SHIFT)) & LPDDR_DENALI_PHY_882_PHY_RDDQS_GATE_SLAVE_DELAY_3_MASK)
/*! @} */

/*! @name DENALI_PHY_1030 - DENALI_PHY_1030 */
/*! @{ */

#define LPDDR_DENALI_PHY_1030_PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK (0x1U)
#define LPDDR_DENALI_PHY_1030_PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT (0U)
/*! PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0 - Power reduction slv_dly_control block gate disable for address slice 0. */
#define LPDDR_DENALI_PHY_1030_PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1030_PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT)) & LPDDR_DENALI_PHY_1030_PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK)

#define LPDDR_DENALI_PHY_1030_PHY_ADR_TYPE_0_MASK (0x300U)
#define LPDDR_DENALI_PHY_1030_PHY_ADR_TYPE_0_SHIFT (8U)
#define LPDDR_DENALI_PHY_1030_PHY_ADR_TYPE_0(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1030_PHY_ADR_TYPE_0_SHIFT)) & LPDDR_DENALI_PHY_1030_PHY_ADR_TYPE_0_MASK)

#define LPDDR_DENALI_PHY_1030_PHY_ADR_IE_MODE_0_MASK (0x1000000U)
#define LPDDR_DENALI_PHY_1030_PHY_ADR_IE_MODE_0_SHIFT (24U)
/*! PHY_ADR_IE_MODE_0
 *  0b0..Input enables off
 *  0b1..Input enables on
 */
#define LPDDR_DENALI_PHY_1030_PHY_ADR_IE_MODE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1030_PHY_ADR_IE_MODE_0_SHIFT)) & LPDDR_DENALI_PHY_1030_PHY_ADR_IE_MODE_0_MASK)
/*! @} */

/*! @name DENALI_PHY_1055 - DENALI_PHY_1055 */
/*! @{ */

#define LPDDR_DENALI_PHY_1055_PHY_ADR_TSEL_SELECT_0_MASK (0xFFU)
#define LPDDR_DENALI_PHY_1055_PHY_ADR_TSEL_SELECT_0_SHIFT (0U)
/*! PHY_ADR_TSEL_SELECT_0 - Tsel select values for address slice 0. */
#define LPDDR_DENALI_PHY_1055_PHY_ADR_TSEL_SELECT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1055_PHY_ADR_TSEL_SELECT_0_SHIFT)) & LPDDR_DENALI_PHY_1055_PHY_ADR_TSEL_SELECT_0_MASK)

#define LPDDR_DENALI_PHY_1055_PHY_PAD_ADR_IO_CFG_0_MASK (0x7FF00U)
#define LPDDR_DENALI_PHY_1055_PHY_PAD_ADR_IO_CFG_0_SHIFT (8U)
#define LPDDR_DENALI_PHY_1055_PHY_PAD_ADR_IO_CFG_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1055_PHY_PAD_ADR_IO_CFG_0_SHIFT)) & LPDDR_DENALI_PHY_1055_PHY_PAD_ADR_IO_CFG_0_MASK)
/*! @} */

/*! @name DENALI_PHY_1063 - DENALI_PHY_1063 */
/*! @{ */

#define LPDDR_DENALI_PHY_1063_PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK (0xFFU)
#define LPDDR_DENALI_PHY_1063_PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT (0U)
/*! PHY_ADR_MASTER_DELAY_HALF_MEASURE_0 - Defines the number of delay line elements to be considered
 *    in determing whether to lock to a half clock cycle for the master in address slice 0.
 */
#define LPDDR_DENALI_PHY_1063_PHY_ADR_MASTER_DELAY_HALF_MEASURE_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1063_PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT)) & LPDDR_DENALI_PHY_1063_PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK)

#define LPDDR_DENALI_PHY_1063_PHY_ADR_CALVL_DLY_STEP_0_MASK (0xF00U)
#define LPDDR_DENALI_PHY_1063_PHY_ADR_CALVL_DLY_STEP_0_SHIFT (8U)
/*! PHY_ADR_CALVL_DLY_STEP_0 - Sets the delay step size plus 1 during CA training for address slice 0. */
#define LPDDR_DENALI_PHY_1063_PHY_ADR_CALVL_DLY_STEP_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1063_PHY_ADR_CALVL_DLY_STEP_0_SHIFT)) & LPDDR_DENALI_PHY_1063_PHY_ADR_CALVL_DLY_STEP_0_MASK)
/*! @} */

/*! @name DENALI_PHY_1286 - DENALI_PHY_1286 */
/*! @{ */

#define LPDDR_DENALI_PHY_1286_PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_MASK (0x1U)
#define LPDDR_DENALI_PHY_1286_PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT (0U)
/*! PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1 - Power reduction slv_dly_control block gate disable for address slice 1. */
#define LPDDR_DENALI_PHY_1286_PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1286_PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT)) & LPDDR_DENALI_PHY_1286_PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_MASK)

#define LPDDR_DENALI_PHY_1286_PHY_ADR_TYPE_1_MASK (0x300U)
#define LPDDR_DENALI_PHY_1286_PHY_ADR_TYPE_1_SHIFT (8U)
#define LPDDR_DENALI_PHY_1286_PHY_ADR_TYPE_1(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1286_PHY_ADR_TYPE_1_SHIFT)) & LPDDR_DENALI_PHY_1286_PHY_ADR_TYPE_1_MASK)

#define LPDDR_DENALI_PHY_1286_PHY_ADR_IE_MODE_1_MASK (0x1000000U)
#define LPDDR_DENALI_PHY_1286_PHY_ADR_IE_MODE_1_SHIFT (24U)
/*! PHY_ADR_IE_MODE_1
 *  0b0..Input enables off
 *  0b1..Input enables on
 */
#define LPDDR_DENALI_PHY_1286_PHY_ADR_IE_MODE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1286_PHY_ADR_IE_MODE_1_SHIFT)) & LPDDR_DENALI_PHY_1286_PHY_ADR_IE_MODE_1_MASK)
/*! @} */

/*! @name DENALI_PHY_1311 - DENALI_PHY_1311 */
/*! @{ */

#define LPDDR_DENALI_PHY_1311_PHY_ADR_TSEL_SELECT_1_MASK (0xFFU)
#define LPDDR_DENALI_PHY_1311_PHY_ADR_TSEL_SELECT_1_SHIFT (0U)
/*! PHY_ADR_TSEL_SELECT_1 - Tsel select values for address slice 1. */
#define LPDDR_DENALI_PHY_1311_PHY_ADR_TSEL_SELECT_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1311_PHY_ADR_TSEL_SELECT_1_SHIFT)) & LPDDR_DENALI_PHY_1311_PHY_ADR_TSEL_SELECT_1_MASK)

#define LPDDR_DENALI_PHY_1311_PHY_PAD_ADR_IO_CFG_1_MASK (0x7FF00U)
#define LPDDR_DENALI_PHY_1311_PHY_PAD_ADR_IO_CFG_1_SHIFT (8U)
#define LPDDR_DENALI_PHY_1311_PHY_PAD_ADR_IO_CFG_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1311_PHY_PAD_ADR_IO_CFG_1_SHIFT)) & LPDDR_DENALI_PHY_1311_PHY_PAD_ADR_IO_CFG_1_MASK)
/*! @} */

/*! @name DENALI_PHY_1319 - DENALI_PHY_1319 */
/*! @{ */

#define LPDDR_DENALI_PHY_1319_PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_MASK (0xFFU)
#define LPDDR_DENALI_PHY_1319_PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_SHIFT (0U)
/*! PHY_ADR_MASTER_DELAY_HALF_MEASURE_1 - Defines the number of delay line elements to be considered
 *    in determing whether to lock to a half clock cycle for the master in address slice 1.
 */
#define LPDDR_DENALI_PHY_1319_PHY_ADR_MASTER_DELAY_HALF_MEASURE_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1319_PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_SHIFT)) & LPDDR_DENALI_PHY_1319_PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_MASK)

#define LPDDR_DENALI_PHY_1319_PHY_ADR_CALVL_DLY_STEP_1_MASK (0xF00U)
#define LPDDR_DENALI_PHY_1319_PHY_ADR_CALVL_DLY_STEP_1_SHIFT (8U)
/*! PHY_ADR_CALVL_DLY_STEP_1 - Sets the delay step size plus 1 during CA training for address slice 1. */
#define LPDDR_DENALI_PHY_1319_PHY_ADR_CALVL_DLY_STEP_1(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1319_PHY_ADR_CALVL_DLY_STEP_1_SHIFT)) & LPDDR_DENALI_PHY_1319_PHY_ADR_CALVL_DLY_STEP_1_MASK)
/*! @} */

/*! @name DENALI_PHY_1536 - DENALI_PHY_1536 */
/*! @{ */

#define LPDDR_DENALI_PHY_1536_PHY_FREQ_SEL_MASK  (0x3U)
#define LPDDR_DENALI_PHY_1536_PHY_FREQ_SEL_SHIFT (0U)
/*! PHY_FREQ_SEL - Specifies which set of the frequency-dependent timing bit will be used by the PHY. */
#define LPDDR_DENALI_PHY_1536_PHY_FREQ_SEL(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1536_PHY_FREQ_SEL_SHIFT)) & LPDDR_DENALI_PHY_1536_PHY_FREQ_SEL_MASK)
/*! @} */

/*! @name DENALI_PHY_1537 - DENALI_PHY_1537 */
/*! @{ */

#define LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_FROM_REGIF_MASK (0x1U)
#define LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_FROM_REGIF_SHIFT (0U)
#define LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_FROM_REGIF(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_FROM_REGIF_SHIFT)) & LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_FROM_REGIF_MASK)

#define LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_MULTICAST_EN_MASK (0x100U)
#define LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_MULTICAST_EN_SHIFT (8U)
#define LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_MULTICAST_EN(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_MULTICAST_EN_SHIFT)) & LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_MULTICAST_EN_MASK)

#define LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_INDEX_MASK (0x30000U)
#define LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_INDEX_SHIFT (16U)
/*! PHY_FREQ_SEL_INDEX - Selects which frequency set to update when PHY_FREQ_SEL_MULTICAST_EN is not set. */
#define LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_INDEX(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_INDEX_SHIFT)) & LPDDR_DENALI_PHY_1537_PHY_FREQ_SEL_INDEX_MASK)

#define LPDDR_DENALI_PHY_1537_PHY_SW_GRP0_SHIFT_0_MASK (0x1F000000U)
#define LPDDR_DENALI_PHY_1537_PHY_SW_GRP0_SHIFT_0_SHIFT (24U)
/*! PHY_SW_GRP0_SHIFT_0 - Address slice slave delay setting for address slice 4. */
#define LPDDR_DENALI_PHY_1537_PHY_SW_GRP0_SHIFT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1537_PHY_SW_GRP0_SHIFT_0_SHIFT)) & LPDDR_DENALI_PHY_1537_PHY_SW_GRP0_SHIFT_0_MASK)
/*! @} */

/*! @name DENALI_PHY_1547 - DENALI_PHY_1547 */
/*! @{ */

#define LPDDR_DENALI_PHY_1547_PHY_CSLVL_ENABLE_MASK (0x1U)
#define LPDDR_DENALI_PHY_1547_PHY_CSLVL_ENABLE_SHIFT (0U)
/*! PHY_CSLVL_ENABLE - CS Training Enable */
#define LPDDR_DENALI_PHY_1547_PHY_CSLVL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1547_PHY_CSLVL_ENABLE_SHIFT)) & LPDDR_DENALI_PHY_1547_PHY_CSLVL_ENABLE_MASK)

#define LPDDR_DENALI_PHY_1547_PHY_LP4_BOOT_DISABLE_MASK (0x100U)
#define LPDDR_DENALI_PHY_1547_PHY_LP4_BOOT_DISABLE_SHIFT (8U)
#define LPDDR_DENALI_PHY_1547_PHY_LP4_BOOT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1547_PHY_LP4_BOOT_DISABLE_SHIFT)) & LPDDR_DENALI_PHY_1547_PHY_LP4_BOOT_DISABLE_MASK)
/*! @} */

/*! @name DENALI_PHY_1555 - DENALI_PHY_1555 */
/*! @{ */

#define LPDDR_DENALI_PHY_1555_PHY_LP4_BOOT_PLL_BYPASS_MASK (0x1U)
#define LPDDR_DENALI_PHY_1555_PHY_LP4_BOOT_PLL_BYPASS_SHIFT (0U)
/*! PHY_LP4_BOOT_PLL_BYPASS - PHY clock PLL bypass select. */
#define LPDDR_DENALI_PHY_1555_PHY_LP4_BOOT_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1555_PHY_LP4_BOOT_PLL_BYPASS_SHIFT)) & LPDDR_DENALI_PHY_1555_PHY_LP4_BOOT_PLL_BYPASS_MASK)
/*! @} */

/*! @name DENALI_PHY_1564 - DENALI_PHY_1564 */
/*! @{ */

#define LPDDR_DENALI_PHY_1564_PHY_PLL_OBS_0_MASK (0xFFFFU)
#define LPDDR_DENALI_PHY_1564_PHY_PLL_OBS_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_1564_PHY_PLL_OBS_0(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1564_PHY_PLL_OBS_0_SHIFT)) & LPDDR_DENALI_PHY_1564_PHY_PLL_OBS_0_MASK)

#define LPDDR_DENALI_PHY_1564_PHY_PLL_OBS_1_MASK (0xFFFF0000U)
#define LPDDR_DENALI_PHY_1564_PHY_PLL_OBS_1_SHIFT (16U)
#define LPDDR_DENALI_PHY_1564_PHY_PLL_OBS_1(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1564_PHY_PLL_OBS_1_SHIFT)) & LPDDR_DENALI_PHY_1564_PHY_PLL_OBS_1_MASK)
/*! @} */

/*! @name DENALI_PHY_1565 - DENALI_PHY_1565 */
/*! @{ */

#define LPDDR_DENALI_PHY_1565_PHY_PLL_OBS_2_MASK (0xFFFFU)
#define LPDDR_DENALI_PHY_1565_PHY_PLL_OBS_2_SHIFT (0U)
#define LPDDR_DENALI_PHY_1565_PHY_PLL_OBS_2(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1565_PHY_PLL_OBS_2_SHIFT)) & LPDDR_DENALI_PHY_1565_PHY_PLL_OBS_2_MASK)

#define LPDDR_DENALI_PHY_1565_PHY_PLL_TESTOUT_SEL_MASK (0x30000U)
#define LPDDR_DENALI_PHY_1565_PHY_PLL_TESTOUT_SEL_SHIFT (16U)
/*! PHY_PLL_TESTOUT_SEL - PHY PLL Testout Select */
#define LPDDR_DENALI_PHY_1565_PHY_PLL_TESTOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1565_PHY_PLL_TESTOUT_SEL_SHIFT)) & LPDDR_DENALI_PHY_1565_PHY_PLL_TESTOUT_SEL_MASK)

#define LPDDR_DENALI_PHY_1565_PHY_LP4_BOOT_LOW_FREQ_SEL_MASK (0x1000000U)
#define LPDDR_DENALI_PHY_1565_PHY_LP4_BOOT_LOW_FREQ_SEL_SHIFT (24U)
/*! PHY_LP4_BOOT_LOW_FREQ_SEL - Control the PLL domain enter/exit from the negative clock edge for LPDDR4 boot frequency. */
#define LPDDR_DENALI_PHY_1565_PHY_LP4_BOOT_LOW_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1565_PHY_LP4_BOOT_LOW_FREQ_SEL_SHIFT)) & LPDDR_DENALI_PHY_1565_PHY_LP4_BOOT_LOW_FREQ_SEL_MASK)
/*! @} */

/*! @name DENALI_PHY_1566 - DENALI_PHY_1566 */
/*! @{ */

#define LPDDR_DENALI_PHY_1566_PHY_TCKSRE_WAIT_MASK (0xFU)
#define LPDDR_DENALI_PHY_1566_PHY_TCKSRE_WAIT_SHIFT (0U)
/*! PHY_TCKSRE_WAIT - Specifies the number of cycles the PHY should wait before turning off the PLL for a deep sleep or DFS event. */
#define LPDDR_DENALI_PHY_1566_PHY_TCKSRE_WAIT(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1566_PHY_TCKSRE_WAIT_SHIFT)) & LPDDR_DENALI_PHY_1566_PHY_TCKSRE_WAIT_MASK)

#define LPDDR_DENALI_PHY_1566_PHY_LP_WAKEUP_MASK (0xFF00U)
#define LPDDR_DENALI_PHY_1566_PHY_LP_WAKEUP_SHIFT (8U)
/*! PHY_LP_WAKEUP - Specifies the number of cycles the PHY takes to wakeup in low power mode. */
#define LPDDR_DENALI_PHY_1566_PHY_LP_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1566_PHY_LP_WAKEUP_SHIFT)) & LPDDR_DENALI_PHY_1566_PHY_LP_WAKEUP_MASK)

#define LPDDR_DENALI_PHY_1566_PHY_LS_IDLE_EN_MASK (0x10000U)
#define LPDDR_DENALI_PHY_1566_PHY_LS_IDLE_EN_SHIFT (16U)
/*! PHY_LS_IDLE_EN - Indicates the Reduced Idle Power State is enabled in low power mode. */
#define LPDDR_DENALI_PHY_1566_PHY_LS_IDLE_EN(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1566_PHY_LS_IDLE_EN_SHIFT)) & LPDDR_DENALI_PHY_1566_PHY_LS_IDLE_EN_MASK)
/*! @} */

/*! @name DENALI_PHY_1569 - DENALI_PHY_1569 */
/*! @{ */

#define LPDDR_DENALI_PHY_1569_PHY_PAD_FDBK_TERM_MASK (0x3FFFFU)
#define LPDDR_DENALI_PHY_1569_PHY_PAD_FDBK_TERM_SHIFT (0U)
/*! PHY_PAD_FDBK_TERM - Controls term settings for gate feedback pads. */
#define LPDDR_DENALI_PHY_1569_PHY_PAD_FDBK_TERM(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1569_PHY_PAD_FDBK_TERM_SHIFT)) & LPDDR_DENALI_PHY_1569_PHY_PAD_FDBK_TERM_MASK)
/*! @} */

/*! @name DENALI_PHY_1580 - DENALI_PHY_1580 */
/*! @{ */

#define LPDDR_DENALI_PHY_1580_PHY_TST_CLK_PAD_CTRL3_MASK (0x7FFFFFU)
#define LPDDR_DENALI_PHY_1580_PHY_TST_CLK_PAD_CTRL3_SHIFT (0U)
/*! PHY_TST_CLK_PAD_CTRL3 - PHY test clock pad additional controls. */
#define LPDDR_DENALI_PHY_1580_PHY_TST_CLK_PAD_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1580_PHY_TST_CLK_PAD_CTRL3_SHIFT)) & LPDDR_DENALI_PHY_1580_PHY_TST_CLK_PAD_CTRL3_MASK)
/*! @} */

/*! @name DENALI_PHY_1594 - DENALI_PHY_1594 */
/*! @{ */

#define LPDDR_DENALI_PHY_1594_PHY_ADRCTL_PVT_MAP_0_MASK (0xFFU)
#define LPDDR_DENALI_PHY_1594_PHY_ADRCTL_PVT_MAP_0_SHIFT (0U)
/*! PHY_ADRCTL_PVT_MAP_0
 *  0b00000000..Use pass 1 results
 *  0b00000001..Use pass 2 results
 */
#define LPDDR_DENALI_PHY_1594_PHY_ADRCTL_PVT_MAP_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1594_PHY_ADRCTL_PVT_MAP_0_SHIFT)) & LPDDR_DENALI_PHY_1594_PHY_ADRCTL_PVT_MAP_0_MASK)

#define LPDDR_DENALI_PHY_1594_PHY_CAL_SLOPE_ADJ_0_MASK (0xFFFFF00U)
#define LPDDR_DENALI_PHY_1594_PHY_CAL_SLOPE_ADJ_0_SHIFT (8U)
#define LPDDR_DENALI_PHY_1594_PHY_CAL_SLOPE_ADJ_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1594_PHY_CAL_SLOPE_ADJ_0_SHIFT)) & LPDDR_DENALI_PHY_1594_PHY_CAL_SLOPE_ADJ_0_MASK)
/*! @} */

/*! @name DENALI_PHY_1607 - DENALI_PHY_1607 */
/*! @{ */

#define LPDDR_DENALI_PHY_1607_PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK (0x1U)
#define LPDDR_DENALI_PHY_1607_PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT (0U)
/*! PHY_AC_SLV_DLY_CTRL_GATE_DISABLE
 *  0b0..Slave delay control clock gating is enabled.
 *  0b1..Slave delay control clock gating is disabled.
 */
#define LPDDR_DENALI_PHY_1607_PHY_AC_SLV_DLY_CTRL_GATE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1607_PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT)) & LPDDR_DENALI_PHY_1607_PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK)
/*! @} */

/*! @name DENALI_PHY_1624 - DENALI_PHY_1624 */
/*! @{ */

#define LPDDR_DENALI_PHY_1624_PHY_PLL_BYPASS_MASK (0x1U)
#define LPDDR_DENALI_PHY_1624_PHY_PLL_BYPASS_SHIFT (0U)
/*! PHY_PLL_BYPASS - PHY clock PLL bypass select.
 *  0b0..No bypass
 *  0b1..Bypass
 */
#define LPDDR_DENALI_PHY_1624_PHY_PLL_BYPASS(x)  (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1624_PHY_PLL_BYPASS_SHIFT)) & LPDDR_DENALI_PHY_1624_PHY_PLL_BYPASS_MASK)
/*! @} */

/*! @name DENALI_PHY_1625 - DENALI_PHY_1625 */
/*! @{ */

#define LPDDR_DENALI_PHY_1625_PHY_PLL_CTRL_MASK  (0x1FFFU)
#define LPDDR_DENALI_PHY_1625_PHY_PLL_CTRL_SHIFT (0U)
/*! PHY_PLL_CTRL - PHY clock PLL controls. */
#define LPDDR_DENALI_PHY_1625_PHY_PLL_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1625_PHY_PLL_CTRL_SHIFT)) & LPDDR_DENALI_PHY_1625_PHY_PLL_CTRL_MASK)

#define LPDDR_DENALI_PHY_1625_PHY_LOW_FREQ_SEL_MASK (0x10000U)
#define LPDDR_DENALI_PHY_1625_PHY_LOW_FREQ_SEL_SHIFT (16U)
#define LPDDR_DENALI_PHY_1625_PHY_LOW_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1625_PHY_LOW_FREQ_SEL_SHIFT)) & LPDDR_DENALI_PHY_1625_PHY_LOW_FREQ_SEL_MASK)
/*! @} */

/*! @name DENALI_PHY_1626 - DENALI_PHY_1626 */
/*! @{ */

#define LPDDR_DENALI_PHY_1626_PHY_PAD_VREF_CTRL_AC_MASK (0xFFFU)
#define LPDDR_DENALI_PHY_1626_PHY_PAD_VREF_CTRL_AC_SHIFT (0U)
/*! PHY_PAD_VREF_CTRL_AC - Defines the pad VREF control settings for the address/control. */
#define LPDDR_DENALI_PHY_1626_PHY_PAD_VREF_CTRL_AC(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1626_PHY_PAD_VREF_CTRL_AC_SHIFT)) & LPDDR_DENALI_PHY_1626_PHY_PAD_VREF_CTRL_AC_MASK)

#define LPDDR_DENALI_PHY_1626_PHY_CSLVL_CAPTURE_CNT_MASK (0xF0000U)
#define LPDDR_DENALI_PHY_1626_PHY_CSLVL_CAPTURE_CNT_SHIFT (16U)
/*! PHY_CSLVL_CAPTURE_CNT - Defines the number of samples to take at each GRP slave delay setting during CS training. */
#define LPDDR_DENALI_PHY_1626_PHY_CSLVL_CAPTURE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1626_PHY_CSLVL_CAPTURE_CNT_SHIFT)) & LPDDR_DENALI_PHY_1626_PHY_CSLVL_CAPTURE_CNT_MASK)

#define LPDDR_DENALI_PHY_1626_PHY_CSLVL_DLY_STEP_MASK (0xF000000U)
#define LPDDR_DENALI_PHY_1626_PHY_CSLVL_DLY_STEP_SHIFT (24U)
/*! PHY_CSLVL_DLY_STEP - Sets the delay step size plus 1 during CS training. */
#define LPDDR_DENALI_PHY_1626_PHY_CSLVL_DLY_STEP(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1626_PHY_CSLVL_DLY_STEP_SHIFT)) & LPDDR_DENALI_PHY_1626_PHY_CSLVL_DLY_STEP_MASK)
/*! @} */

/*! @name DENALI_PHY_1635 - DENALI_PHY_1635 */
/*! @{ */

#define LPDDR_DENALI_PHY_1635_PHY_PAD_FDBK_DRIVE_MASK (0x3FFFFFFFU)
#define LPDDR_DENALI_PHY_1635_PHY_PAD_FDBK_DRIVE_SHIFT (0U)
#define LPDDR_DENALI_PHY_1635_PHY_PAD_FDBK_DRIVE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1635_PHY_PAD_FDBK_DRIVE_SHIFT)) & LPDDR_DENALI_PHY_1635_PHY_PAD_FDBK_DRIVE_MASK)
/*! @} */

/*! @name DENALI_PHY_1637 - DENALI_PHY_1637 */
/*! @{ */

#define LPDDR_DENALI_PHY_1637_PHY_PAD_DATA_DRIVE_MASK (0x7FFFFFFFU)
#define LPDDR_DENALI_PHY_1637_PHY_PAD_DATA_DRIVE_SHIFT (0U)
#define LPDDR_DENALI_PHY_1637_PHY_PAD_DATA_DRIVE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1637_PHY_PAD_DATA_DRIVE_SHIFT)) & LPDDR_DENALI_PHY_1637_PHY_PAD_DATA_DRIVE_MASK)
/*! @} */

/*! @name DENALI_PHY_1639 - DENALI_PHY_1639 */
/*! @{ */

#define LPDDR_DENALI_PHY_1639_PHY_PAD_DQS_DRIVE_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_PHY_1639_PHY_PAD_DQS_DRIVE_SHIFT (0U)
#define LPDDR_DENALI_PHY_1639_PHY_PAD_DQS_DRIVE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1639_PHY_PAD_DQS_DRIVE_SHIFT)) & LPDDR_DENALI_PHY_1639_PHY_PAD_DQS_DRIVE_MASK)
/*! @} */

/*! @name DENALI_PHY_1641 - DENALI_PHY_1641 */
/*! @{ */

#define LPDDR_DENALI_PHY_1641_PHY_PAD_ADDR_DRIVE_MASK (0x3FFFFFFFU)
#define LPDDR_DENALI_PHY_1641_PHY_PAD_ADDR_DRIVE_SHIFT (0U)
#define LPDDR_DENALI_PHY_1641_PHY_PAD_ADDR_DRIVE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1641_PHY_PAD_ADDR_DRIVE_SHIFT)) & LPDDR_DENALI_PHY_1641_PHY_PAD_ADDR_DRIVE_MASK)
/*! @} */

/*! @name DENALI_PHY_1643 - DENALI_PHY_1643 */
/*! @{ */

#define LPDDR_DENALI_PHY_1643_PHY_PAD_CLK_DRIVE_MASK (0xFFFFFFFFU)
#define LPDDR_DENALI_PHY_1643_PHY_PAD_CLK_DRIVE_SHIFT (0U)
#define LPDDR_DENALI_PHY_1643_PHY_PAD_CLK_DRIVE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1643_PHY_PAD_CLK_DRIVE_SHIFT)) & LPDDR_DENALI_PHY_1643_PHY_PAD_CLK_DRIVE_MASK)
/*! @} */

/*! @name DENALI_PHY_1645 - DENALI_PHY_1645 */
/*! @{ */

#define LPDDR_DENALI_PHY_1645_PHY_PAD_CKE_DRIVE_MASK (0x3FFFFFFFU)
#define LPDDR_DENALI_PHY_1645_PHY_PAD_CKE_DRIVE_SHIFT (0U)
#define LPDDR_DENALI_PHY_1645_PHY_PAD_CKE_DRIVE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1645_PHY_PAD_CKE_DRIVE_SHIFT)) & LPDDR_DENALI_PHY_1645_PHY_PAD_CKE_DRIVE_MASK)
/*! @} */

/*! @name DENALI_PHY_1647 - DENALI_PHY_1647 */
/*! @{ */

#define LPDDR_DENALI_PHY_1647_PHY_PAD_RST_DRIVE_MASK (0x3FFFFFFFU)
#define LPDDR_DENALI_PHY_1647_PHY_PAD_RST_DRIVE_SHIFT (0U)
#define LPDDR_DENALI_PHY_1647_PHY_PAD_RST_DRIVE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1647_PHY_PAD_RST_DRIVE_SHIFT)) & LPDDR_DENALI_PHY_1647_PHY_PAD_RST_DRIVE_MASK)
/*! @} */

/*! @name DENALI_PHY_1649 - DENALI_PHY_1649 */
/*! @{ */

#define LPDDR_DENALI_PHY_1649_PHY_PAD_CS_DRIVE_MASK (0x3FFFFFFFU)
#define LPDDR_DENALI_PHY_1649_PHY_PAD_CS_DRIVE_SHIFT (0U)
#define LPDDR_DENALI_PHY_1649_PHY_PAD_CS_DRIVE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1649_PHY_PAD_CS_DRIVE_SHIFT)) & LPDDR_DENALI_PHY_1649_PHY_PAD_CS_DRIVE_MASK)
/*! @} */

/*! @name DENALI_PHY_1651 - DENALI_PHY_1651 */
/*! @{ */

#define LPDDR_DENALI_PHY_1651_PHY_PAD_ODT_DRIVE_MASK (0x3FFFFFFFU)
#define LPDDR_DENALI_PHY_1651_PHY_PAD_ODT_DRIVE_SHIFT (0U)
#define LPDDR_DENALI_PHY_1651_PHY_PAD_ODT_DRIVE(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1651_PHY_PAD_ODT_DRIVE_SHIFT)) & LPDDR_DENALI_PHY_1651_PHY_PAD_ODT_DRIVE_MASK)
/*! @} */

/*! @name DENALI_PHY_1653 - DENALI_PHY_1653 */
/*! @{ */

#define LPDDR_DENALI_PHY_1653_PHY_CAL_CLK_SELECT_0_MASK (0x7U)
#define LPDDR_DENALI_PHY_1653_PHY_CAL_CLK_SELECT_0_SHIFT (0U)
#define LPDDR_DENALI_PHY_1653_PHY_CAL_CLK_SELECT_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1653_PHY_CAL_CLK_SELECT_0_SHIFT)) & LPDDR_DENALI_PHY_1653_PHY_CAL_CLK_SELECT_0_MASK)

#define LPDDR_DENALI_PHY_1653_PHY_CAL_VREF_SWITCH_TIMER_0_MASK (0xFFFF00U)
#define LPDDR_DENALI_PHY_1653_PHY_CAL_VREF_SWITCH_TIMER_0_SHIFT (8U)
/*! PHY_CAL_VREF_SWITCH_TIMER_0 - The settling time for a switch in VREF during IO pad calibration. */
#define LPDDR_DENALI_PHY_1653_PHY_CAL_VREF_SWITCH_TIMER_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1653_PHY_CAL_VREF_SWITCH_TIMER_0_SHIFT)) & LPDDR_DENALI_PHY_1653_PHY_CAL_VREF_SWITCH_TIMER_0_MASK)

#define LPDDR_DENALI_PHY_1653_PHY_CAL_SETTLING_PRD_0_MASK (0x7F000000U)
#define LPDDR_DENALI_PHY_1653_PHY_CAL_SETTLING_PRD_0_SHIFT (24U)
/*! PHY_CAL_SETTLING_PRD_0 - Number of clock cycles to extend dfi_phyupd_req after the dfi_phyupd_ack is received for settling of final values. */
#define LPDDR_DENALI_PHY_1653_PHY_CAL_SETTLING_PRD_0(x) (((uint32_t)(((uint32_t)(x)) << LPDDR_DENALI_PHY_1653_PHY_CAL_SETTLING_PRD_0_SHIFT)) & LPDDR_DENALI_PHY_1653_PHY_CAL_SETTLING_PRD_0_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LPDDR_Register_Masks */


/* LPDDR - Peripheral instance base addresses */
/** Peripheral LPDDR base address */
#define LPDDR_BASE                               (0x2E060000u)
/** Peripheral LPDDR base pointer */
#define LPDDR                                    ((LPDDR_Type *)LPDDR_BASE)
/** Array initializer of LPDDR peripheral base addresses */
#define LPDDR_BASE_ADDRS                         { LPDDR_BASE }
/** Array initializer of LPDDR peripheral base pointers */
#define LPDDR_BASE_PTRS                          { LPDDR }

/*!
 * @}
 */ /* end of group LPDDR_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPI2C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
 * @{
 */

/** LPI2C - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t MCR;                               /**< Master Control, offset: 0x10 */
  __IO uint32_t MSR;                               /**< Master Status, offset: 0x14 */
  __IO uint32_t MIER;                              /**< Master Interrupt Enable, offset: 0x18 */
  __IO uint32_t MDER;                              /**< Master DMA Enable, offset: 0x1C */
  __IO uint32_t MCFGR0;                            /**< Master Configuration 0, offset: 0x20 */
  __IO uint32_t MCFGR1;                            /**< Master Configuration 1, offset: 0x24 */
  __IO uint32_t MCFGR2;                            /**< Master Configuration 2, offset: 0x28 */
  __IO uint32_t MCFGR3;                            /**< Master Configuration 3, offset: 0x2C */
       uint8_t RESERVED_1[16];
  __IO uint32_t MDMR;                              /**< Master Data Match, offset: 0x40 */
       uint8_t RESERVED_2[4];
  __IO uint32_t MCCR0;                             /**< Master Clock Configuration 0, offset: 0x48 */
       uint8_t RESERVED_3[4];
  __IO uint32_t MCCR1;                             /**< Master Clock Configuration 1, offset: 0x50 */
       uint8_t RESERVED_4[4];
  __IO uint32_t MFCR;                              /**< Master FIFO Control, offset: 0x58 */
  __I  uint32_t MFSR;                              /**< Master FIFO Status, offset: 0x5C */
  __O  uint32_t MTDR;                              /**< Master Transmit Data, offset: 0x60 */
       uint8_t RESERVED_5[12];
  __I  uint32_t MRDR;                              /**< Master Receive Data, offset: 0x70 */
       uint8_t RESERVED_6[156];
  __IO uint32_t SCR;                               /**< Slave Control, offset: 0x110 */
  __IO uint32_t SSR;                               /**< Slave Status, offset: 0x114 */
  __IO uint32_t SIER;                              /**< Slave Interrupt Enable, offset: 0x118 */
  __IO uint32_t SDER;                              /**< Slave DMA Enable, offset: 0x11C */
       uint8_t RESERVED_7[4];
  __IO uint32_t SCFGR1;                            /**< Slave Configuration 1, offset: 0x124 */
  __IO uint32_t SCFGR2;                            /**< Slave Configuration 2, offset: 0x128 */
       uint8_t RESERVED_8[20];
  __IO uint32_t SAMR;                              /**< Slave Address Match, offset: 0x140 */
       uint8_t RESERVED_9[12];
  __I  uint32_t SASR;                              /**< Slave Address Status, offset: 0x150 */
  __IO uint32_t STAR;                              /**< Slave Transmit ACK, offset: 0x154 */
       uint8_t RESERVED_10[8];
  __O  uint32_t STDR;                              /**< Slave Transmit Data, offset: 0x160 */
       uint8_t RESERVED_11[12];
  __I  uint32_t SRDR;                              /**< Slave Receive Data, offset: 0x170 */
} LPI2C_Type;

/* ----------------------------------------------------------------------------
   -- LPI2C Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
#define LPI2C_VERID_FEATURE_SHIFT                (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000010..Master only, with standard feature set
 *  0b0000000000000011..Master and slave, with standard feature set
 */
#define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)

#define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
#define LPI2C_VERID_MINOR_SHIFT                  (16U)
/*! MINOR - Minor Version Number */
#define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)

#define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
#define LPI2C_VERID_MAJOR_SHIFT                  (24U)
/*! MAJOR - Major Version Number */
#define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
#define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
/*! MTXFIFO - Master Transmit FIFO Size */
#define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)

#define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
#define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
/*! MRXFIFO - Master Receive FIFO Size */
#define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
/*! @} */

/*! @name MCR - Master Control */
/*! @{ */

#define LPI2C_MCR_MEN_MASK                       (0x1U)
#define LPI2C_MCR_MEN_SHIFT                      (0U)
/*! MEN - Master Enable
 *  0b0..Master logic is disabled
 *  0b1..Master logic is enabled
 */
#define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)

#define LPI2C_MCR_RST_MASK                       (0x2U)
#define LPI2C_MCR_RST_SHIFT                      (1U)
/*! RST - Software Reset
 *  0b0..Master logic is not reset
 *  0b1..Master logic is reset
 */
#define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)

#define LPI2C_MCR_DOZEN_MASK                     (0x4U)
#define LPI2C_MCR_DOZEN_SHIFT                    (2U)
/*! DOZEN - Doze mode enable
 *  0b0..Master is enabled in Doze mode
 *  0b1..Master is disabled in Doze mode
 */
#define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)

#define LPI2C_MCR_DBGEN_MASK                     (0x8U)
#define LPI2C_MCR_DBGEN_SHIFT                    (3U)
/*! DBGEN - Debug Enable
 *  0b0..Master is disabled in debug mode
 *  0b1..Master is enabled in debug mode
 */
#define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)

#define LPI2C_MCR_RTF_MASK                       (0x100U)
#define LPI2C_MCR_RTF_SHIFT                      (8U)
/*! RTF - Reset Transmit FIFO
 *  0b0..No effect
 *  0b1..Transmit FIFO is reset
 */
#define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)

#define LPI2C_MCR_RRF_MASK                       (0x200U)
#define LPI2C_MCR_RRF_SHIFT                      (9U)
/*! RRF - Reset Receive FIFO
 *  0b0..No effect
 *  0b1..Receive FIFO is reset
 */
#define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
/*! @} */

/*! @name MSR - Master Status */
/*! @{ */

#define LPI2C_MSR_TDF_MASK                       (0x1U)
#define LPI2C_MSR_TDF_SHIFT                      (0U)
/*! TDF - Transmit Data Flag
 *  0b0..Transmit data is not requested
 *  0b1..Transmit data is requested
 */
#define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)

#define LPI2C_MSR_RDF_MASK                       (0x2U)
#define LPI2C_MSR_RDF_SHIFT                      (1U)
/*! RDF - Receive Data Flag
 *  0b0..Receive Data is not ready
 *  0b1..Receive data is ready
 */
#define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)

#define LPI2C_MSR_EPF_MASK                       (0x100U)
#define LPI2C_MSR_EPF_SHIFT                      (8U)
/*! EPF - End Packet Flag
 *  0b0..Master has not generated a STOP or Repeated START condition
 *  0b1..Master has generated a STOP or Repeated START condition
 */
#define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)

#define LPI2C_MSR_SDF_MASK                       (0x200U)
#define LPI2C_MSR_SDF_SHIFT                      (9U)
/*! SDF - STOP Detect Flag
 *  0b0..Master has not generated a STOP condition
 *  0b1..Master has generated a STOP condition
 */
#define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)

#define LPI2C_MSR_NDF_MASK                       (0x400U)
#define LPI2C_MSR_NDF_SHIFT                      (10U)
/*! NDF - NACK Detect Flag
 *  0b0..Unexpected NACK was not detected
 *  0b1..Unexpected NACK was detected
 */
#define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)

#define LPI2C_MSR_ALF_MASK                       (0x800U)
#define LPI2C_MSR_ALF_SHIFT                      (11U)
/*! ALF - Arbitration Lost Flag
 *  0b0..Master has not lost arbitration
 *  0b1..Master has lost arbitration
 */
#define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)

#define LPI2C_MSR_FEF_MASK                       (0x1000U)
#define LPI2C_MSR_FEF_SHIFT                      (12U)
/*! FEF - FIFO Error Flag
 *  0b0..No error
 *  0b1..Master sending or receiving data without a START condition
 */
#define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)

#define LPI2C_MSR_PLTF_MASK                      (0x2000U)
#define LPI2C_MSR_PLTF_SHIFT                     (13U)
/*! PLTF - Pin Low Timeout Flag
 *  0b0..Pin low timeout has not occurred or is disabled
 *  0b1..Pin low timeout has occurred
 */
#define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)

#define LPI2C_MSR_DMF_MASK                       (0x4000U)
#define LPI2C_MSR_DMF_SHIFT                      (14U)
/*! DMF - Data Match Flag
 *  0b0..Have not received matching data
 *  0b1..Have received matching data
 */
#define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)

#define LPI2C_MSR_MBF_MASK                       (0x1000000U)
#define LPI2C_MSR_MBF_SHIFT                      (24U)
/*! MBF - Master Busy Flag
 *  0b0..I2C Master is idle
 *  0b1..I2C Master is busy
 */
#define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)

#define LPI2C_MSR_BBF_MASK                       (0x2000000U)
#define LPI2C_MSR_BBF_SHIFT                      (25U)
/*! BBF - Bus Busy Flag
 *  0b0..I2C Bus is idle
 *  0b1..I2C Bus is busy
 */
#define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
/*! @} */

/*! @name MIER - Master Interrupt Enable */
/*! @{ */

#define LPI2C_MIER_TDIE_MASK                     (0x1U)
#define LPI2C_MIER_TDIE_SHIFT                    (0U)
/*! TDIE - Transmit Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)

#define LPI2C_MIER_RDIE_MASK                     (0x2U)
#define LPI2C_MIER_RDIE_SHIFT                    (1U)
/*! RDIE - Receive Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)

#define LPI2C_MIER_EPIE_MASK                     (0x100U)
#define LPI2C_MIER_EPIE_SHIFT                    (8U)
/*! EPIE - End Packet Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)

#define LPI2C_MIER_SDIE_MASK                     (0x200U)
#define LPI2C_MIER_SDIE_SHIFT                    (9U)
/*! SDIE - STOP Detect Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)

#define LPI2C_MIER_NDIE_MASK                     (0x400U)
#define LPI2C_MIER_NDIE_SHIFT                    (10U)
/*! NDIE - NACK Detect Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)

#define LPI2C_MIER_ALIE_MASK                     (0x800U)
#define LPI2C_MIER_ALIE_SHIFT                    (11U)
/*! ALIE - Arbitration Lost Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)

#define LPI2C_MIER_FEIE_MASK                     (0x1000U)
#define LPI2C_MIER_FEIE_SHIFT                    (12U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)

#define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
#define LPI2C_MIER_PLTIE_SHIFT                   (13U)
/*! PLTIE - Pin Low Timeout Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)

#define LPI2C_MIER_DMIE_MASK                     (0x4000U)
#define LPI2C_MIER_DMIE_SHIFT                    (14U)
/*! DMIE - Data Match Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
/*! @} */

/*! @name MDER - Master DMA Enable */
/*! @{ */

#define LPI2C_MDER_TDDE_MASK                     (0x1U)
#define LPI2C_MDER_TDDE_SHIFT                    (0U)
/*! TDDE - Transmit Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)

#define LPI2C_MDER_RDDE_MASK                     (0x2U)
#define LPI2C_MDER_RDDE_SHIFT                    (1U)
/*! RDDE - Receive Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
/*! @} */

/*! @name MCFGR0 - Master Configuration 0 */
/*! @{ */

#define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
#define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
/*! HREN - Host Request Enable
 *  0b0..Host request input is disabled
 *  0b1..Host request input is enabled
 */
#define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)

#define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
#define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
/*! HRPOL - Host Request Polarity
 *  0b0..Active low
 *  0b1..Active high
 */
#define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)

#define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
#define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
/*! HRSEL - Host Request Select
 *  0b0..Host request input is pin HREQ
 *  0b1..Host request input is input trigger
 */
#define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)

#define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
#define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
/*! CIRFIFO - Circular FIFO Enable
 *  0b0..Circular FIFO is disabled
 *  0b1..Circular FIFO is enabled
 */
#define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)

#define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
#define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
/*! RDMO - Receive Data Match Only
 *  0b0..Received data is stored in the receive FIFO
 *  0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
 */
#define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
/*! @} */

/*! @name MCFGR1 - Master Configuration 1 */
/*! @{ */

#define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
#define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
/*! PRESCALE - Prescaler
 *  0b000..Divide by 1
 *  0b001..Divide by 2
 *  0b010..Divide by 4
 *  0b011..Divide by 8
 *  0b100..Divide by 16
 *  0b101..Divide by 32
 *  0b110..Divide by 64
 *  0b111..Divide by 128
 */
#define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)

#define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
#define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
/*! AUTOSTOP - Automatic STOP Generation
 *  0b0..No effect
 *  0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
 */
#define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)

#define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
#define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
/*! IGNACK - IGNACK
 *  0b0..LPI2C Master receives ACK and NACK normally
 *  0b1..LPI2C Master treats a received NACK as if it (NACK) was an ACK
 */
#define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)

#define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
#define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
/*! TIMECFG - Timeout Configuration
 *  0b0..MSR[PLTF] sets if SCL is low for longer than the configured timeout
 *  0b1..MSR[PLTF] sets if either SCL or SDA is low for longer than the configured timeout
 */
#define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)

#define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
#define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
/*! MATCFG - Match Configuration
 *  0b000..Match is disabled
 *  0b001..Reserved
 *  0b010..Match is enabled (1st data word equals MDMR[MATCH0] OR MDMR[MATCH1])
 *  0b011..Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1])
 *  0b100..Match is enabled (1st data word equals MDMR[MATCH0] AND 2nd data word equals MDMR[MATCH1)
 *  0b101..Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1)
 *  0b110..Match is enabled (1st data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])
 *  0b111..Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])
 */
#define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)

#define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
#define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
/*! PINCFG - Pin Configuration
 *  0b000..2-pin open drain mode
 *  0b001..2-pin output only mode (ultra-fast mode)
 *  0b010..2-pin push-pull mode
 *  0b011..4-pin push-pull mode
 *  0b100..2-pin open drain mode with separate LPI2C slave
 *  0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
 *  0b110..2-pin push-pull mode with separate LPI2C slave
 *  0b111..4-pin push-pull mode (inverted outputs)
 */
#define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)

#define LPI2C_MCFGR1_FRCHS_MASK                  (0x8000000U)
#define LPI2C_MCFGR1_FRCHS_SHIFT                 (27U)
/*! FRCHS - Force HS-mode
 *  0b0..No effect
 *  0b1..LPI2C pin state forced into HS-mode.
 */
#define LPI2C_MCFGR1_FRCHS(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_FRCHS_SHIFT)) & LPI2C_MCFGR1_FRCHS_MASK)
/*! @} */

/*! @name MCFGR2 - Master Configuration 2 */
/*! @{ */

#define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
#define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
/*! BUSIDLE - Bus Idle Timeout */
#define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)

#define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
#define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
/*! FILTSCL - Glitch Filter SCL */
#define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)

#define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
#define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
/*! FILTSDA - Glitch Filter SDA */
#define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
/*! @} */

/*! @name MCFGR3 - Master Configuration 3 */
/*! @{ */

#define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
#define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
/*! PINLOW - Pin Low Timeout */
#define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
/*! @} */

/*! @name MDMR - Master Data Match */
/*! @{ */

#define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
#define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
/*! MATCH0 - Match 0 Value */
#define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)

#define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
#define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
/*! MATCH1 - Match 1 Value */
#define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
/*! @} */

/*! @name MCCR0 - Master Clock Configuration 0 */
/*! @{ */

#define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
#define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
/*! CLKLO - Clock Low Period */
#define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)

#define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
#define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
/*! CLKHI - Clock High Period */
#define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)

#define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
#define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
/*! SETHOLD - Setup Hold Delay */
#define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)

#define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
#define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
/*! DATAVD - Data Valid Delay */
#define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
/*! @} */

/*! @name MCCR1 - Master Clock Configuration 1 */
/*! @{ */

#define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
#define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
/*! CLKLO - Clock Low Period */
#define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)

#define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
#define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
/*! CLKHI - Clock High Period */
#define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)

#define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
#define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
/*! SETHOLD - Setup Hold Delay */
#define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)

#define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
#define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
/*! DATAVD - Data Valid Delay */
#define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
/*! @} */

/*! @name MFCR - Master FIFO Control */
/*! @{ */

#define LPI2C_MFCR_TXWATER_MASK                  (0x3U)
#define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
/*! TXWATER - Transmit FIFO Watermark */
#define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)

#define LPI2C_MFCR_RXWATER_MASK                  (0x30000U)
#define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
/*! RXWATER - Receive FIFO Watermark */
#define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
/*! @} */

/*! @name MFSR - Master FIFO Status */
/*! @{ */

#define LPI2C_MFSR_TXCOUNT_MASK                  (0x7U)
#define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
/*! TXCOUNT - Transmit FIFO Count */
#define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)

#define LPI2C_MFSR_RXCOUNT_MASK                  (0x70000U)
#define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
/*! RXCOUNT - Receive FIFO Count */
#define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
/*! @} */

/*! @name MTDR - Master Transmit Data */
/*! @{ */

#define LPI2C_MTDR_DATA_MASK                     (0xFFU)
#define LPI2C_MTDR_DATA_SHIFT                    (0U)
/*! DATA - Transmit Data */
#define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)

#define LPI2C_MTDR_CMD_MASK                      (0x700U)
#define LPI2C_MTDR_CMD_SHIFT                     (8U)
/*! CMD - Command Data
 *  0b000..Transmit DATA[7:0]
 *  0b001..Receive (DATA[7:0] + 1) bytes
 *  0b010..Generate STOP condition
 *  0b011..Receive and discard (DATA[7:0] + 1) bytes
 *  0b100..Generate (repeated) START and transmit address in DATA[7:0]
 *  0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
 *  0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
 *  0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
 */
#define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
/*! @} */

/*! @name MRDR - Master Receive Data */
/*! @{ */

#define LPI2C_MRDR_DATA_MASK                     (0xFFU)
#define LPI2C_MRDR_DATA_SHIFT                    (0U)
/*! DATA - Receive Data */
#define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)

#define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
#define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
/*! RXEMPTY - Receive Empty
 *  0b0..Receive FIFO is not empty
 *  0b1..Receive FIFO is empty
 */
#define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
/*! @} */

/*! @name SCR - Slave Control */
/*! @{ */

#define LPI2C_SCR_SEN_MASK                       (0x1U)
#define LPI2C_SCR_SEN_SHIFT                      (0U)
/*! SEN - Slave Enable
 *  0b0..I2C Slave mode is disabled
 *  0b1..I2C Slave mode is enabled
 */
#define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)

#define LPI2C_SCR_RST_MASK                       (0x2U)
#define LPI2C_SCR_RST_SHIFT                      (1U)
/*! RST - Software Reset
 *  0b0..Slave mode logic is not reset
 *  0b1..Slave mode logic is reset
 */
#define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)

#define LPI2C_SCR_FILTEN_MASK                    (0x10U)
#define LPI2C_SCR_FILTEN_SHIFT                   (4U)
/*! FILTEN - Filter Enable
 *  0b0..Disable digital filter and output delay counter for slave mode
 *  0b1..Enable digital filter and output delay counter for slave mode
 */
#define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)

#define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
#define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
/*! FILTDZ - Filter Doze Enable
 *  0b0..Filter remains enabled in Doze mode
 *  0b1..Filter is disabled in Doze mode
 */
#define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)

#define LPI2C_SCR_RTF_MASK                       (0x100U)
#define LPI2C_SCR_RTF_SHIFT                      (8U)
/*! RTF - Reset Transmit FIFO
 *  0b0..No effect
 *  0b1..Transmit Data Register is now empty
 */
#define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)

#define LPI2C_SCR_RRF_MASK                       (0x200U)
#define LPI2C_SCR_RRF_SHIFT                      (9U)
/*! RRF - Reset Receive FIFO
 *  0b0..No effect
 *  0b1..Receive Data Register is now empty
 */
#define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
/*! @} */

/*! @name SSR - Slave Status */
/*! @{ */

#define LPI2C_SSR_TDF_MASK                       (0x1U)
#define LPI2C_SSR_TDF_SHIFT                      (0U)
/*! TDF - Transmit Data Flag
 *  0b0..Transmit data not requested
 *  0b1..Transmit data is requested
 */
#define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)

#define LPI2C_SSR_RDF_MASK                       (0x2U)
#define LPI2C_SSR_RDF_SHIFT                      (1U)
/*! RDF - Receive Data Flag
 *  0b0..Receive data is not ready
 *  0b1..Receive data is ready
 */
#define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)

#define LPI2C_SSR_AVF_MASK                       (0x4U)
#define LPI2C_SSR_AVF_SHIFT                      (2U)
/*! AVF - Address Valid Flag
 *  0b0..Address Status Register is not valid
 *  0b1..Address Status Register is valid
 */
#define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)

#define LPI2C_SSR_TAF_MASK                       (0x8U)
#define LPI2C_SSR_TAF_SHIFT                      (3U)
/*! TAF - Transmit ACK Flag
 *  0b0..Transmit ACK/NACK is not required
 *  0b1..Transmit ACK/NACK is required
 */
#define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)

#define LPI2C_SSR_RSF_MASK                       (0x100U)
#define LPI2C_SSR_RSF_SHIFT                      (8U)
/*! RSF - Repeated Start Flag
 *  0b0..Slave has not detected a Repeated START condition
 *  0b1..Slave has detected a Repeated START condition
 */
#define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)

#define LPI2C_SSR_SDF_MASK                       (0x200U)
#define LPI2C_SSR_SDF_SHIFT                      (9U)
/*! SDF - STOP Detect Flag
 *  0b0..Slave has not detected a STOP condition
 *  0b1..Slave has detected a STOP condition
 */
#define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)

#define LPI2C_SSR_BEF_MASK                       (0x400U)
#define LPI2C_SSR_BEF_SHIFT                      (10U)
/*! BEF - Bit Error Flag
 *  0b0..Slave has not detected a bit error
 *  0b1..Slave has detected a bit error
 */
#define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)

#define LPI2C_SSR_FEF_MASK                       (0x800U)
#define LPI2C_SSR_FEF_SHIFT                      (11U)
/*! FEF - FIFO Error Flag
 *  0b0..FIFO underflow or overflow was not detected
 *  0b1..FIFO underflow or overflow was detected
 */
#define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)

#define LPI2C_SSR_AM0F_MASK                      (0x1000U)
#define LPI2C_SSR_AM0F_SHIFT                     (12U)
/*! AM0F - Address Match 0 Flag
 *  0b0..Have not received an ADDR0 matching address
 *  0b1..Have received an ADDR0 matching address
 */
#define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)

#define LPI2C_SSR_AM1F_MASK                      (0x2000U)
#define LPI2C_SSR_AM1F_SHIFT                     (13U)
/*! AM1F - Address Match 1 Flag
 *  0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
 *  0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
 */
#define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)

#define LPI2C_SSR_GCF_MASK                       (0x4000U)
#define LPI2C_SSR_GCF_SHIFT                      (14U)
/*! GCF - General Call Flag
 *  0b0..Slave has not detected the General Call Address or the General Call Address is disabled
 *  0b1..Slave has detected the General Call Address
 */
#define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)

#define LPI2C_SSR_SARF_MASK                      (0x8000U)
#define LPI2C_SSR_SARF_SHIFT                     (15U)
/*! SARF - SMBus Alert Response Flag
 *  0b0..SMBus Alert Response is disabled or not detected
 *  0b1..SMBus Alert Response is enabled and detected
 */
#define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)

#define LPI2C_SSR_SBF_MASK                       (0x1000000U)
#define LPI2C_SSR_SBF_SHIFT                      (24U)
/*! SBF - Slave Busy Flag
 *  0b0..I2C Slave is idle
 *  0b1..I2C Slave is busy
 */
#define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)

#define LPI2C_SSR_BBF_MASK                       (0x2000000U)
#define LPI2C_SSR_BBF_SHIFT                      (25U)
/*! BBF - Bus Busy Flag
 *  0b0..I2C Bus is idle
 *  0b1..I2C Bus is busy
 */
#define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
/*! @} */

/*! @name SIER - Slave Interrupt Enable */
/*! @{ */

#define LPI2C_SIER_TDIE_MASK                     (0x1U)
#define LPI2C_SIER_TDIE_SHIFT                    (0U)
/*! TDIE - Transmit Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)

#define LPI2C_SIER_RDIE_MASK                     (0x2U)
#define LPI2C_SIER_RDIE_SHIFT                    (1U)
/*! RDIE - Receive Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)

#define LPI2C_SIER_AVIE_MASK                     (0x4U)
#define LPI2C_SIER_AVIE_SHIFT                    (2U)
/*! AVIE - Address Valid Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)

#define LPI2C_SIER_TAIE_MASK                     (0x8U)
#define LPI2C_SIER_TAIE_SHIFT                    (3U)
/*! TAIE - Transmit ACK Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)

#define LPI2C_SIER_RSIE_MASK                     (0x100U)
#define LPI2C_SIER_RSIE_SHIFT                    (8U)
/*! RSIE - Repeated Start Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)

#define LPI2C_SIER_SDIE_MASK                     (0x200U)
#define LPI2C_SIER_SDIE_SHIFT                    (9U)
/*! SDIE - STOP Detect Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)

#define LPI2C_SIER_BEIE_MASK                     (0x400U)
#define LPI2C_SIER_BEIE_SHIFT                    (10U)
/*! BEIE - Bit Error Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)

#define LPI2C_SIER_FEIE_MASK                     (0x800U)
#define LPI2C_SIER_FEIE_SHIFT                    (11U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)

#define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
#define LPI2C_SIER_AM0IE_SHIFT                   (12U)
/*! AM0IE - Address Match 0 Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)

#define LPI2C_SIER_AM1IE_MASK                    (0x2000U)
#define LPI2C_SIER_AM1IE_SHIFT                   (13U)
/*! AM1IE - Address Match 1 Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_AM1IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)

#define LPI2C_SIER_GCIE_MASK                     (0x4000U)
#define LPI2C_SIER_GCIE_SHIFT                    (14U)
/*! GCIE - General Call Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)

#define LPI2C_SIER_SARIE_MASK                    (0x8000U)
#define LPI2C_SIER_SARIE_SHIFT                   (15U)
/*! SARIE - SMBus Alert Response Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
/*! @} */

/*! @name SDER - Slave DMA Enable */
/*! @{ */

#define LPI2C_SDER_TDDE_MASK                     (0x1U)
#define LPI2C_SDER_TDDE_SHIFT                    (0U)
/*! TDDE - Transmit Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)

#define LPI2C_SDER_RDDE_MASK                     (0x2U)
#define LPI2C_SDER_RDDE_SHIFT                    (1U)
/*! RDDE - Receive Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)

#define LPI2C_SDER_AVDE_MASK                     (0x4U)
#define LPI2C_SDER_AVDE_SHIFT                    (2U)
/*! AVDE - Address Valid DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)

#define LPI2C_SDER_RSDE_MASK                     (0x100U)
#define LPI2C_SDER_RSDE_SHIFT                    (8U)
/*! RSDE - Repeated Start DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_RSDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK)

#define LPI2C_SDER_SDDE_MASK                     (0x200U)
#define LPI2C_SDER_SDDE_SHIFT                    (9U)
/*! SDDE - Stop Detect DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_SDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK)
/*! @} */

/*! @name SCFGR1 - Slave Configuration 1 */
/*! @{ */

#define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
#define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
/*! ADRSTALL - Address SCL Stall
 *  0b0..Clock stretching is disabled
 *  0b1..Clock stretching is enabled
 */
#define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)

#define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
#define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
/*! RXSTALL - RX SCL Stall
 *  0b0..Clock stretching is disabled
 *  0b1..Clock stretching is enabled
 */
#define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)

#define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
#define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
/*! TXDSTALL - TX Data SCL Stall
 *  0b0..Clock stretching is disabled
 *  0b1..Clock stretching is enabled
 */
#define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)

#define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
#define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
/*! ACKSTALL - ACK SCL Stall
 *  0b0..Clock stretching is disabled
 *  0b1..Clock stretching is enabled
 */
#define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)

#define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
#define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
/*! GCEN - General Call Enable
 *  0b0..General Call address is disabled
 *  0b1..General Call address is enabled
 */
#define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)

#define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
#define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
/*! SAEN - SMBus Alert Enable
 *  0b0..Disables match on SMBus Alert
 *  0b1..Enables match on SMBus Alert
 */
#define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)

#define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
#define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
/*! TXCFG - Transmit Flag Configuration
 *  0b0..Transmit Data Flag only asserts during a slave-transmit transfer when the Transmit Data register is empty
 *  0b1..Transmit Data Flag asserts whenever the Transmit Data register is empty
 */
#define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)

#define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
#define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
/*! RXCFG - Receive Data Configuration
 *  0b0..Reading the Receive Data register returns received data and clears the Receive Data flag.
 *  0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF]) is set, returns the Address
 *       Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid
 *       flag is clear, returns received data and clears the Receive Data flag (MSR[RDF]).
 */
#define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)

#define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
#define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
/*! IGNACK - Ignore NACK
 *  0b0..Slave ends transfer when NACK is detected
 *  0b1..Slave does not end transfer when NACK detected
 */
#define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)

#define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
#define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
/*! HSMEN - High Speed Mode Enable
 *  0b0..Disables detection of HS-mode master code
 *  0b1..Enables detection of HS-mode master code
 */
#define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)

#define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
#define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
/*! ADDRCFG - Address Configuration
 *  0b000..Address match 0 (7-bit)
 *  0b001..Address match 0 (10-bit)
 *  0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
 *  0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
 *  0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
 *  0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
 *  0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
 *  0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
 */
#define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
/*! @} */

/*! @name SCFGR2 - Slave Configuration 2 */
/*! @{ */

#define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
#define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
/*! CLKHOLD - Clock Hold Time */
#define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)

#define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
#define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
/*! DATAVD - Data Valid Delay */
#define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)

#define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
#define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
/*! FILTSCL - Glitch Filter SCL */
#define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)

#define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
#define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
/*! FILTSDA - Glitch Filter SDA */
#define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
/*! @} */

/*! @name SAMR - Slave Address Match */
/*! @{ */

#define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
#define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
/*! ADDR0 - Address 0 Value */
#define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)

#define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
#define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
/*! ADDR1 - Address 1 Value */
#define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
/*! @} */

/*! @name SASR - Slave Address Status */
/*! @{ */

#define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
#define LPI2C_SASR_RADDR_SHIFT                   (0U)
/*! RADDR - Received Address */
#define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)

#define LPI2C_SASR_ANV_MASK                      (0x4000U)
#define LPI2C_SASR_ANV_SHIFT                     (14U)
/*! ANV - Address Not Valid
 *  0b0..Received Address (RADDR) is valid
 *  0b1..Received Address (RADDR) is not valid
 */
#define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
/*! @} */

/*! @name STAR - Slave Transmit ACK */
/*! @{ */

#define LPI2C_STAR_TXNACK_MASK                   (0x1U)
#define LPI2C_STAR_TXNACK_SHIFT                  (0U)
/*! TXNACK - Transmit NACK
 *  0b0..Write a Transmit ACK for each received word
 *  0b1..Write a Transmit NACK for each received word
 */
#define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
/*! @} */

/*! @name STDR - Slave Transmit Data */
/*! @{ */

#define LPI2C_STDR_DATA_MASK                     (0xFFU)
#define LPI2C_STDR_DATA_SHIFT                    (0U)
/*! DATA - Transmit Data */
#define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
/*! @} */

/*! @name SRDR - Slave Receive Data */
/*! @{ */

#define LPI2C_SRDR_DATA_MASK                     (0xFFU)
#define LPI2C_SRDR_DATA_SHIFT                    (0U)
/*! DATA - Receive Data */
#define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)

#define LPI2C_SRDR_RADDR_MASK                    (0x700U)
#define LPI2C_SRDR_RADDR_SHIFT                   (8U)
/*! RADDR - Received Address */
#define LPI2C_SRDR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK)

#define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
#define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
/*! RXEMPTY - Receive Empty
 *  0b0..The Receive Data Register is not empty
 *  0b1..The Receive Data Register is empty
 */
#define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)

#define LPI2C_SRDR_SOF_MASK                      (0x8000U)
#define LPI2C_SRDR_SOF_SHIFT                     (15U)
/*! SOF - Start Of Frame
 *  0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
 *  0b1..Indicates this is the first data word since a (repeated) START or STOP condition
 */
#define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LPI2C_Register_Masks */


/* LPI2C - Peripheral instance base addresses */
/** Peripheral LPI2C0 base address */
#define LPI2C0_BASE                              (0x28098000u)
/** Peripheral LPI2C0 base pointer */
#define LPI2C0                                   ((LPI2C_Type *)LPI2C0_BASE)
/** Peripheral LPI2C1 base address */
#define LPI2C1_BASE                              (0x28099000u)
/** Peripheral LPI2C1 base pointer */
#define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
/** Peripheral LPI2C2 base address */
#define LPI2C2_BASE                              (0x28108000u)
/** Peripheral LPI2C2 base pointer */
#define LPI2C2                                   ((LPI2C_Type *)LPI2C2_BASE)
/** Peripheral LPI2C3 base address */
#define LPI2C3_BASE                              (0x28109000u)
/** Peripheral LPI2C3 base pointer */
#define LPI2C3                                   ((LPI2C_Type *)LPI2C3_BASE)
/** Peripheral LPI2C4 base address */
#define LPI2C4_BASE                              (0x29370000u)
/** Peripheral LPI2C4 base pointer */
#define LPI2C4                                   ((LPI2C_Type *)LPI2C4_BASE)
/** Peripheral LPI2C5 base address */
#define LPI2C5_BASE                              (0x29380000u)
/** Peripheral LPI2C5 base pointer */
#define LPI2C5                                   ((LPI2C_Type *)LPI2C5_BASE)
/** Peripheral LPI2C6 base address */
#define LPI2C6_BASE                              (0x29840000u)
/** Peripheral LPI2C6 base pointer */
#define LPI2C6                                   ((LPI2C_Type *)LPI2C6_BASE)
/** Peripheral LPI2C7 base address */
#define LPI2C7_BASE                              (0x29850000u)
/** Peripheral LPI2C7 base pointer */
#define LPI2C7                                   ((LPI2C_Type *)LPI2C7_BASE)
/** Array initializer of LPI2C peripheral base addresses */
#define LPI2C_BASE_ADDRS                         { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE }
/** Array initializer of LPI2C peripheral base pointers */
#define LPI2C_BASE_PTRS                          { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7 }

/*!
 * @}
 */ /* end of group LPI2C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPIT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer
 * @{
 */

/** LPIT - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
  __IO uint32_t MCR;                               /**< Module Control, offset: 0x8 */
  __IO uint32_t MSR;                               /**< Module Status, offset: 0xC */
  __IO uint32_t MIER;                              /**< Module Interrupt Enable, offset: 0x10 */
  __IO uint32_t SETTEN;                            /**< Set Timer Enable, offset: 0x14 */
  __O  uint32_t CLRTEN;                            /**< Clear Timer Enable, offset: 0x18 */
       uint8_t RESERVED_0[4];
  struct {                                         /* offset: 0x20, array step: 0x10 */
    __IO uint32_t TVAL;                              /**< Timer Value, array offset: 0x20, array step: 0x10 */
    __I  uint32_t CVAL;                              /**< Current Timer Value, array offset: 0x24, array step: 0x10 */
    __IO uint32_t TCTRL;                             /**< Timer Control, array offset: 0x28, array step: 0x10 */
         uint8_t RESERVED_0[4];
  } CHANNEL[4];
} LPIT_Type;

/* ----------------------------------------------------------------------------
   -- LPIT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPIT_Register_Masks LPIT Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define LPIT_VERID_FEATURE_MASK                  (0xFFFFU)
#define LPIT_VERID_FEATURE_SHIFT                 (0U)
/*! FEATURE - Feature Number */
#define LPIT_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK)

#define LPIT_VERID_MINOR_MASK                    (0xFF0000U)
#define LPIT_VERID_MINOR_SHIFT                   (16U)
/*! MINOR - Minor Version Number */
#define LPIT_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK)

#define LPIT_VERID_MAJOR_MASK                    (0xFF000000U)
#define LPIT_VERID_MAJOR_SHIFT                   (24U)
/*! MAJOR - Major Version Number */
#define LPIT_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define LPIT_PARAM_CHANNEL_MASK                  (0xFFU)
#define LPIT_PARAM_CHANNEL_SHIFT                 (0U)
/*! CHANNEL - Number of Timer Channels */
#define LPIT_PARAM_CHANNEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK)

#define LPIT_PARAM_EXT_TRIG_MASK                 (0xFF00U)
#define LPIT_PARAM_EXT_TRIG_SHIFT                (8U)
/*! EXT_TRIG - Number of External Trigger Inputs */
#define LPIT_PARAM_EXT_TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK)
/*! @} */

/*! @name MCR - Module Control */
/*! @{ */

#define LPIT_MCR_M_CEN_MASK                      (0x1U)
#define LPIT_MCR_M_CEN_SHIFT                     (0U)
/*! M_CEN - Module Clock Enable
 *  0b0..Disable peripheral clock to timers
 *  0b1..Enable peripheral clock to timers
 */
#define LPIT_MCR_M_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK)

#define LPIT_MCR_SW_RST_MASK                     (0x2U)
#define LPIT_MCR_SW_RST_SHIFT                    (1U)
/*! SW_RST - Software Reset
 *  0b0..Timer channels and registers are not reset
 *  0b1..Reset timer channels and registers
 */
#define LPIT_MCR_SW_RST(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK)

#define LPIT_MCR_DOZE_EN_MASK                    (0x4U)
#define LPIT_MCR_DOZE_EN_SHIFT                   (2U)
/*! DOZE_EN - DOZE Mode Enable
 *  0b0..Stop timer channels in DOZE mode
 *  0b1..Allow timer channels to continue to run in DOZE mode
 */
#define LPIT_MCR_DOZE_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK)

#define LPIT_MCR_DBG_EN_MASK                     (0x8U)
#define LPIT_MCR_DBG_EN_SHIFT                    (3U)
/*! DBG_EN - Debug Mode Enable
 *  0b0..Stop timer channels in Debug mode
 *  0b1..Allow timer channels to continue to run in Debug mode
 */
#define LPIT_MCR_DBG_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK)
/*! @} */

/*! @name MSR - Module Status */
/*! @{ */

#define LPIT_MSR_TIF0_MASK                       (0x1U)
#define LPIT_MSR_TIF0_SHIFT                      (0U)
/*! TIF0 - Channel 0 Timer Interrupt Flag
 *  0b0..Timer has not timed out
 *  0b1..Timeout has occurred (timer has timed out)
 */
#define LPIT_MSR_TIF0(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK)

#define LPIT_MSR_TIF1_MASK                       (0x2U)
#define LPIT_MSR_TIF1_SHIFT                      (1U)
/*! TIF1 - Channel 1 Timer Interrupt Flag
 *  0b0..Timer has not timed out
 *  0b1..Timeout has occurred (timer has timed out)
 */
#define LPIT_MSR_TIF1(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK)

#define LPIT_MSR_TIF2_MASK                       (0x4U)
#define LPIT_MSR_TIF2_SHIFT                      (2U)
/*! TIF2 - Channel 2 Timer Interrupt Flag
 *  0b0..Timer has not timed out
 *  0b1..Timeout has occurred (timer has timed out)
 */
#define LPIT_MSR_TIF2(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK)

#define LPIT_MSR_TIF3_MASK                       (0x8U)
#define LPIT_MSR_TIF3_SHIFT                      (3U)
/*! TIF3 - Channel 3 Timer Interrupt Flag
 *  0b0..Timer has not timed out
 *  0b1..Timeout has occurred (timer has timed out)
 */
#define LPIT_MSR_TIF3(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK)
/*! @} */

/*! @name MIER - Module Interrupt Enable */
/*! @{ */

#define LPIT_MIER_TIE0_MASK                      (0x1U)
#define LPIT_MIER_TIE0_SHIFT                     (0U)
/*! TIE0 - Channel 0 Timer Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPIT_MIER_TIE0(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK)

#define LPIT_MIER_TIE1_MASK                      (0x2U)
#define LPIT_MIER_TIE1_SHIFT                     (1U)
/*! TIE1 - Channel 1 Timer Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPIT_MIER_TIE1(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK)

#define LPIT_MIER_TIE2_MASK                      (0x4U)
#define LPIT_MIER_TIE2_SHIFT                     (2U)
/*! TIE2 - Channel 2 Timer Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPIT_MIER_TIE2(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK)

#define LPIT_MIER_TIE3_MASK                      (0x8U)
#define LPIT_MIER_TIE3_SHIFT                     (3U)
/*! TIE3 - Channel 3 Timer Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPIT_MIER_TIE3(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK)
/*! @} */

/*! @name SETTEN - Set Timer Enable */
/*! @{ */

#define LPIT_SETTEN_SET_T_EN_0_MASK              (0x1U)
#define LPIT_SETTEN_SET_T_EN_0_SHIFT             (0U)
/*! SET_T_EN_0 - Set Timer 0 Enable
 *  0b0..No effect
 *  0b1..Enables Timer Channel 0
 */
#define LPIT_SETTEN_SET_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK)

#define LPIT_SETTEN_SET_T_EN_1_MASK              (0x2U)
#define LPIT_SETTEN_SET_T_EN_1_SHIFT             (1U)
/*! SET_T_EN_1 - Set Timer 1 Enable
 *  0b0..No Effect
 *  0b1..Enables Timer Channel 1
 */
#define LPIT_SETTEN_SET_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK)

#define LPIT_SETTEN_SET_T_EN_2_MASK              (0x4U)
#define LPIT_SETTEN_SET_T_EN_2_SHIFT             (2U)
/*! SET_T_EN_2 - Set Timer 2 Enable
 *  0b0..No Effect
 *  0b1..Enables Timer Channel 2
 */
#define LPIT_SETTEN_SET_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK)

#define LPIT_SETTEN_SET_T_EN_3_MASK              (0x8U)
#define LPIT_SETTEN_SET_T_EN_3_SHIFT             (3U)
/*! SET_T_EN_3 - Set Timer 3 Enable
 *  0b0..No effect
 *  0b1..Enables Timer Channel 3
 */
#define LPIT_SETTEN_SET_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK)
/*! @} */

/*! @name CLRTEN - Clear Timer Enable */
/*! @{ */

#define LPIT_CLRTEN_CLR_T_EN_0_MASK              (0x1U)
#define LPIT_CLRTEN_CLR_T_EN_0_SHIFT             (0U)
/*! CLR_T_EN_0 - Clear Timer 0 Enable
 *  0b0..No action
 *  0b1..Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0
 */
#define LPIT_CLRTEN_CLR_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK)

#define LPIT_CLRTEN_CLR_T_EN_1_MASK              (0x2U)
#define LPIT_CLRTEN_CLR_T_EN_1_SHIFT             (1U)
/*! CLR_T_EN_1 - Clear Timer 1 Enable
 *  0b0..No Action
 *  0b1..Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1
 */
#define LPIT_CLRTEN_CLR_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK)

#define LPIT_CLRTEN_CLR_T_EN_2_MASK              (0x4U)
#define LPIT_CLRTEN_CLR_T_EN_2_SHIFT             (2U)
/*! CLR_T_EN_2 - Clear Timer 2 Enable
 *  0b0..No Action
 *  0b1..Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2
 */
#define LPIT_CLRTEN_CLR_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK)

#define LPIT_CLRTEN_CLR_T_EN_3_MASK              (0x8U)
#define LPIT_CLRTEN_CLR_T_EN_3_SHIFT             (3U)
/*! CLR_T_EN_3 - Clear Timer 3 Enable
 *  0b0..No Action
 *  0b1..Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3
 */
#define LPIT_CLRTEN_CLR_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK)
/*! @} */

/*! @name TVAL - Timer Value */
/*! @{ */

#define LPIT_TVAL_TMR_VAL_MASK                   (0xFFFFFFFFU)
#define LPIT_TVAL_TMR_VAL_SHIFT                  (0U)
/*! TMR_VAL - Timer Value
 *  0b00000000000000000000000000000000, 0b00000000000000000000000000000001..Invalid load value in compare mode
 *  0b00000000000000000000000000000010-0b11111111111111111111111111111111..In compare mode: the value to be loaded; in capture mode, the value of the timer
 */
#define LPIT_TVAL_TMR_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK)
/*! @} */

/* The count of LPIT_TVAL */
#define LPIT_TVAL_COUNT                          (4U)

/*! @name CVAL - Current Timer Value */
/*! @{ */

#define LPIT_CVAL_TMR_CUR_VAL_MASK               (0xFFFFFFFFU)
#define LPIT_CVAL_TMR_CUR_VAL_SHIFT              (0U)
/*! TMR_CUR_VAL - Current Timer Value */
#define LPIT_CVAL_TMR_CUR_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/*! @} */

/* The count of LPIT_CVAL */
#define LPIT_CVAL_COUNT                          (4U)

/*! @name TCTRL - Timer Control */
/*! @{ */

#define LPIT_TCTRL_T_EN_MASK                     (0x1U)
#define LPIT_TCTRL_T_EN_SHIFT                    (0U)
/*! T_EN - Timer Enable
 *  0b0..Timer Channel is disabled
 *  0b1..Timer Channel is enabled
 */
#define LPIT_TCTRL_T_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK)

#define LPIT_TCTRL_CHAIN_MASK                    (0x2U)
#define LPIT_TCTRL_CHAIN_SHIFT                   (1U)
/*! CHAIN - Chain Channel
 *  0b0..Channel Chaining is disabled. The channel timer runs independently.
 *  0b1..Channel Chaining is enabled. The timer decrements on the previous channel's timeout.
 */
#define LPIT_TCTRL_CHAIN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK)

#define LPIT_TCTRL_MODE_MASK                     (0xCU)
#define LPIT_TCTRL_MODE_SHIFT                    (2U)
/*! MODE - Timer Operation Mode
 *  0b00..32-bit Periodic Counter
 *  0b01..Dual 16-bit Periodic Counter
 *  0b10..32-bit Trigger Accumulator
 *  0b11..32-bit Trigger Input Capture
 */
#define LPIT_TCTRL_MODE(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK)

#define LPIT_TCTRL_TSOT_MASK                     (0x10000U)
#define LPIT_TCTRL_TSOT_SHIFT                    (16U)
/*! TSOT - Timer Start On Trigger
 *  0b0..Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI))
 *  0b1..Timer starts to decrement when a rising edge on a selected trigger is detected
 */
#define LPIT_TCTRL_TSOT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK)

#define LPIT_TCTRL_TSOI_MASK                     (0x20000U)
#define LPIT_TCTRL_TSOI_SHIFT                    (17U)
/*! TSOI - Timer Stop On Interrupt
 *  0b0..The channel timer does not stop after timeout
 *  0b1..The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On
 *       Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable
 *       bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1,
 *       the channel timer will restart after a rising edge on the selected trigger is detected.
 */
#define LPIT_TCTRL_TSOI(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK)

#define LPIT_TCTRL_TROT_MASK                     (0x40000U)
#define LPIT_TCTRL_TROT_SHIFT                    (18U)
/*! TROT - Timer Reload On Trigger
 *  0b0..Timer will not reload on the selected trigger
 *  0b1..Timer will reload on the selected trigger
 */
#define LPIT_TCTRL_TROT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK)

#define LPIT_TCTRL_TRG_SRC_MASK                  (0x800000U)
#define LPIT_TCTRL_TRG_SRC_SHIFT                 (23U)
/*! TRG_SRC - Trigger Source
 *  0b0..Selects external triggers
 *  0b1..Selects internal triggers
 */
#define LPIT_TCTRL_TRG_SRC(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK)

#define LPIT_TCTRL_TRG_SEL_MASK                  (0xF000000U)
#define LPIT_TCTRL_TRG_SEL_SHIFT                 (24U)
/*! TRG_SEL - Trigger Select
 *  0b0000-0b0011..Timer channel 0 - 3 trigger source is selected
 *  0b0100-0b1111..Reserved
 */
#define LPIT_TCTRL_TRG_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK)
/*! @} */

/* The count of LPIT_TCTRL */
#define LPIT_TCTRL_COUNT                         (4U)


/*!
 * @}
 */ /* end of group LPIT_Register_Masks */


/* LPIT - Peripheral instance base addresses */
/** Peripheral LPIT0 base address */
#define LPIT0_BASE                               (0x2803B000u)
/** Peripheral LPIT0 base pointer */
#define LPIT0                                    ((LPIT_Type *)LPIT0_BASE)
/** Peripheral LPIT1 base address */
#define LPIT1_BASE                               (0x29320000u)
/** Peripheral LPIT1 base pointer */
#define LPIT1                                    ((LPIT_Type *)LPIT1_BASE)
/** Array initializer of LPIT peripheral base addresses */
#define LPIT_BASE_ADDRS                          { LPIT0_BASE, LPIT1_BASE }
/** Array initializer of LPIT peripheral base pointers */
#define LPIT_BASE_PTRS                           { LPIT0, LPIT1 }

/*!
 * @}
 */ /* end of group LPIT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPSPI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
 * @{
 */

/** LPSPI - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t CR;                                /**< Control, offset: 0x10 */
  __IO uint32_t SR;                                /**< Status, offset: 0x14 */
  __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x18 */
  __IO uint32_t DER;                               /**< DMA Enable, offset: 0x1C */
  __IO uint32_t CFGR0;                             /**< Configuration 0, offset: 0x20 */
  __IO uint32_t CFGR1;                             /**< Configuration 1, offset: 0x24 */
       uint8_t RESERVED_1[8];
  __IO uint32_t DMR0;                              /**< Data Match 0, offset: 0x30 */
  __IO uint32_t DMR1;                              /**< Data Match 1, offset: 0x34 */
       uint8_t RESERVED_2[8];
  __IO uint32_t CCR;                               /**< Clock Configuration, offset: 0x40 */
  __IO uint32_t CCR1;                              /**< Clock Configuration 1, offset: 0x44 */
       uint8_t RESERVED_3[16];
  __IO uint32_t FCR;                               /**< FIFO Control, offset: 0x58 */
  __I  uint32_t FSR;                               /**< FIFO Status, offset: 0x5C */
  __IO uint32_t TCR;                               /**< Transmit Command, offset: 0x60 */
  __O  uint32_t TDR;                               /**< Transmit Data, offset: 0x64 */
       uint8_t RESERVED_4[8];
  __I  uint32_t RSR;                               /**< Receive Status, offset: 0x70 */
  __I  uint32_t RDR;                               /**< Receive Data, offset: 0x74 */
  __I  uint32_t RDROR;                             /**< Receive Data Read Only, offset: 0x78 */
       uint8_t RESERVED_5[896];
  __O  uint32_t TCBR;                              /**< Transmit Command Burst, offset: 0x3FC */
  __O  uint32_t TDBR[128];                         /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */
  __I  uint32_t RDBR[128];                         /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */
} LPSPI_Type;

/* ----------------------------------------------------------------------------
   -- LPSPI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
#define LPSPI_VERID_FEATURE_SHIFT                (0U)
/*! FEATURE - Module Identification Number
 *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
 */
#define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)

#define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
#define LPSPI_VERID_MINOR_SHIFT                  (16U)
/*! MINOR - Minor Version Number */
#define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)

#define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
#define LPSPI_VERID_MAJOR_SHIFT                  (24U)
/*! MAJOR - Major Version Number */
#define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
#define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
/*! TXFIFO - Transmit FIFO Size */
#define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)

#define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
#define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
/*! RXFIFO - Receive FIFO Size */
#define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)

#define LPSPI_PARAM_PCSNUM_MASK                  (0xFF0000U)
#define LPSPI_PARAM_PCSNUM_SHIFT                 (16U)
/*! PCSNUM - PCS Number */
#define LPSPI_PARAM_PCSNUM(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
/*! @} */

/*! @name CR - Control */
/*! @{ */

#define LPSPI_CR_MEN_MASK                        (0x1U)
#define LPSPI_CR_MEN_SHIFT                       (0U)
/*! MEN - Module Enable
 *  0b0..Module is disabled
 *  0b1..Module is enabled
 */
#define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)

#define LPSPI_CR_RST_MASK                        (0x2U)
#define LPSPI_CR_RST_SHIFT                       (1U)
/*! RST - Software Reset
 *  0b0..Module is not reset
 *  0b1..Module is reset
 */
#define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)

#define LPSPI_CR_DOZEN_MASK                      (0x4U)
#define LPSPI_CR_DOZEN_SHIFT                     (2U)
/*! DOZEN - Doze Mode Enable
 *  0b0..LPSPI module is enabled in Doze mode
 *  0b1..LPSPI module is disabled in Doze mode
 */
#define LPSPI_CR_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)

#define LPSPI_CR_DBGEN_MASK                      (0x8U)
#define LPSPI_CR_DBGEN_SHIFT                     (3U)
/*! DBGEN - Debug Enable
 *  0b0..LPSPI module is disabled when the CPU is halted. When LPSPI is disabled, the PCS will be negated once the
 *       transmit FIFO is empty regardless of the state of TCR register.
 *  0b1..LPSPI module is enabled in debug mode
 */
#define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)

#define LPSPI_CR_RTF_MASK                        (0x100U)
#define LPSPI_CR_RTF_SHIFT                       (8U)
/*! RTF - Reset Transmit FIFO
 *  0b0..No effect
 *  0b1..Reset the Transmit FIFO. The register bit always reads zero.
 */
#define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)

#define LPSPI_CR_RRF_MASK                        (0x200U)
#define LPSPI_CR_RRF_SHIFT                       (9U)
/*! RRF - Reset Receive FIFO
 *  0b0..No effect
 *  0b1..Reset the Receive FIFO. The register bit always reads zero.
 */
#define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
/*! @} */

/*! @name SR - Status */
/*! @{ */

#define LPSPI_SR_TDF_MASK                        (0x1U)
#define LPSPI_SR_TDF_SHIFT                       (0U)
/*! TDF - Transmit Data Flag
 *  0b0..Transmit data not requested
 *  0b1..Transmit data is requested
 */
#define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)

#define LPSPI_SR_RDF_MASK                        (0x2U)
#define LPSPI_SR_RDF_SHIFT                       (1U)
/*! RDF - Receive Data Flag
 *  0b0..Receive Data is not ready
 *  0b1..Receive data is ready
 */
#define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)

#define LPSPI_SR_WCF_MASK                        (0x100U)
#define LPSPI_SR_WCF_SHIFT                       (8U)
/*! WCF - Word Complete Flag
 *  0b0..Transfer of a received word has not yet completed
 *  0b1..Transfer of a received word has completed
 */
#define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)

#define LPSPI_SR_FCF_MASK                        (0x200U)
#define LPSPI_SR_FCF_SHIFT                       (9U)
/*! FCF - Frame Complete Flag
 *  0b0..Frame transfer has not completed
 *  0b1..Frame transfer has completed
 */
#define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)

#define LPSPI_SR_TCF_MASK                        (0x400U)
#define LPSPI_SR_TCF_SHIFT                       (10U)
/*! TCF - Transfer Complete Flag
 *  0b0..All transfers have not completed
 *  0b1..All transfers have completed
 */
#define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)

#define LPSPI_SR_TEF_MASK                        (0x800U)
#define LPSPI_SR_TEF_SHIFT                       (11U)
/*! TEF - Transmit Error Flag
 *  0b0..Transmit FIFO underrun has not occurred
 *  0b1..Transmit FIFO underrun has occurred
 */
#define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)

#define LPSPI_SR_REF_MASK                        (0x1000U)
#define LPSPI_SR_REF_SHIFT                       (12U)
/*! REF - Receive Error Flag
 *  0b0..Receive FIFO has not overflowed
 *  0b1..Receive FIFO has overflowed
 */
#define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)

#define LPSPI_SR_DMF_MASK                        (0x2000U)
#define LPSPI_SR_DMF_SHIFT                       (13U)
/*! DMF - Data Match Flag
 *  0b0..Have not received matching data
 *  0b1..Have received matching data
 */
#define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)

#define LPSPI_SR_MBF_MASK                        (0x1000000U)
#define LPSPI_SR_MBF_SHIFT                       (24U)
/*! MBF - Module Busy Flag
 *  0b0..LPSPI is idle
 *  0b1..LPSPI is busy
 */
#define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
/*! @} */

/*! @name IER - Interrupt Enable */
/*! @{ */

#define LPSPI_IER_TDIE_MASK                      (0x1U)
#define LPSPI_IER_TDIE_SHIFT                     (0U)
/*! TDIE - Transmit Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)

#define LPSPI_IER_RDIE_MASK                      (0x2U)
#define LPSPI_IER_RDIE_SHIFT                     (1U)
/*! RDIE - Receive Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)

#define LPSPI_IER_WCIE_MASK                      (0x100U)
#define LPSPI_IER_WCIE_SHIFT                     (8U)
/*! WCIE - Word Complete Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)

#define LPSPI_IER_FCIE_MASK                      (0x200U)
#define LPSPI_IER_FCIE_SHIFT                     (9U)
/*! FCIE - Frame Complete Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)

#define LPSPI_IER_TCIE_MASK                      (0x400U)
#define LPSPI_IER_TCIE_SHIFT                     (10U)
/*! TCIE - Transfer Complete Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)

#define LPSPI_IER_TEIE_MASK                      (0x800U)
#define LPSPI_IER_TEIE_SHIFT                     (11U)
/*! TEIE - Transmit Error Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)

#define LPSPI_IER_REIE_MASK                      (0x1000U)
#define LPSPI_IER_REIE_SHIFT                     (12U)
/*! REIE - Receive Error Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)

#define LPSPI_IER_DMIE_MASK                      (0x2000U)
#define LPSPI_IER_DMIE_SHIFT                     (13U)
/*! DMIE - Data Match Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
/*! @} */

/*! @name DER - DMA Enable */
/*! @{ */

#define LPSPI_DER_TDDE_MASK                      (0x1U)
#define LPSPI_DER_TDDE_SHIFT                     (0U)
/*! TDDE - Transmit Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)

#define LPSPI_DER_RDDE_MASK                      (0x2U)
#define LPSPI_DER_RDDE_SHIFT                     (1U)
/*! RDDE - Receive Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)

#define LPSPI_DER_FCDE_MASK                      (0x200U)
#define LPSPI_DER_FCDE_SHIFT                     (9U)
/*! FCDE - Frame Complete DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPSPI_DER_FCDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK)
/*! @} */

/*! @name CFGR0 - Configuration 0 */
/*! @{ */

#define LPSPI_CFGR0_HREN_MASK                    (0x1U)
#define LPSPI_CFGR0_HREN_SHIFT                   (0U)
/*! HREN - Host Request Enable
 *  0b0..Host request is disabled
 *  0b1..Host request is enabled
 */
#define LPSPI_CFGR0_HREN(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)

#define LPSPI_CFGR0_HRPOL_MASK                   (0x2U)
#define LPSPI_CFGR0_HRPOL_SHIFT                  (1U)
/*! HRPOL - Host Request Polarity
 *  0b0..HREQ pin or input trigger is active high
 *  0b1..HREQ pin or input trigger is active low
 */
#define LPSPI_CFGR0_HRPOL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)

#define LPSPI_CFGR0_HRSEL_MASK                   (0x4U)
#define LPSPI_CFGR0_HRSEL_SHIFT                  (2U)
/*! HRSEL - Host Request Select
 *  0b0..Host request input is the HREQ pin
 *  0b1..Host request input is the input trigger
 */
#define LPSPI_CFGR0_HRSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)

#define LPSPI_CFGR0_HRDIR_MASK                   (0x8U)
#define LPSPI_CFGR0_HRDIR_SHIFT                  (3U)
/*! HRDIR - Host Request Direction
 *  0b0..HREQ pin is configured as input
 *  0b1..HREQ pin is configured as output
 */
#define LPSPI_CFGR0_HRDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK)

#define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
#define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
/*! CIRFIFO - Circular FIFO Enable
 *  0b0..Circular FIFO is disabled
 *  0b1..Circular FIFO is enabled
 */
#define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)

#define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
#define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
/*! RDMO - Receive Data Match Only
 *  0b0..Received data is stored in the receive FIFO as in normal operations
 *  0b1..Received data is discarded unless the SR[DMF] = 1
 */
#define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
/*! @} */

/*! @name CFGR1 - Configuration 1 */
/*! @{ */

#define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
#define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
/*! MASTER - Master Mode
 *  0b0..Slave mode
 *  0b1..Master mode
 */
#define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)

#define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
#define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
/*! SAMPLE - Sample Point
 *  0b0..Input data is sampled on SCK edge
 *  0b1..Input data is sampled on delayed SCK edge
 */
#define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)

#define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
#define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
/*! AUTOPCS - Automatic PCS
 *  0b0..Automatic PCS generation is disabled
 *  0b1..Automatic PCS generation is enabled
 */
#define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)

#define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
#define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
/*! NOSTALL - No Stall
 *  0b0..Transfers stall when the transmit FIFO is empty or the receive FIFO is full
 *  0b1..Transfers do not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur
 */
#define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)

#define LPSPI_CFGR1_PARTIAL_MASK                 (0x10U)
#define LPSPI_CFGR1_PARTIAL_SHIFT                (4U)
/*! PARTIAL - Partial Enable
 *  0b0..Partial words in the receive shift register when PCS negates are discarded.
 *  0b1..Partial words in the receive shift register when PCS negates are stored in the receive FIFO.
 */
#define LPSPI_CFGR1_PARTIAL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK)

#define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
#define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
/*! PCSPOL - Peripheral Chip Select Polarity */
#define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)

#define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
#define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
/*! MATCFG - Match Configuration
 *  0b000..Match is disabled
 *  0b001..Reserved
 *  0b010..Match is enabled is 1st data word is MATCH0 or MATCH1
 *  0b011..Match is enabled on any data word equal MATCH0 or MATCH1
 *  0b100..Match is enabled on data match sequence
 *  0b101..Match is enabled on data match sequence
 *  0b110..Match is enabled
 *  0b111..Match is enabled
 */
#define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)

#define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
#define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
/*! PINCFG - Pin Configuration
 *  0b00..SIN is used for input data and SOUT is used for output data
 *  0b01..SIN is used for both input and output data, only half-duplex serial transfers are supported
 *  0b10..SOUT is used for both input and output data, only half-duplex serial transfers are supported
 *  0b11..SOUT is used for input data and SIN is used for output data
 */
#define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)

#define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
#define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
/*! OUTCFG - Output Configuration
 *  0b0..Output data retains last value when chip select is negated
 *  0b1..Output data is tristated when chip select is negated
 */
#define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)

#define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
#define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
/*! PCSCFG - Peripheral Chip Select Configuration
 *  0b0..PCS[3:2] are configured for chip select function
 *  0b1..PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
 */
#define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
/*! @} */

/*! @name DMR0 - Data Match 0 */
/*! @{ */

#define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
#define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
/*! MATCH0 - Match 0 Value */
#define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
/*! @} */

/*! @name DMR1 - Data Match 1 */
/*! @{ */

#define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
#define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
/*! MATCH1 - Match 1 Value */
#define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
/*! @} */

/*! @name CCR - Clock Configuration */
/*! @{ */

#define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
#define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
/*! SCKDIV - SCK Divider */
#define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)

#define LPSPI_CCR_DBT_MASK                       (0xFF00U)
#define LPSPI_CCR_DBT_SHIFT                      (8U)
/*! DBT - Delay Between Transfers */
#define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)

#define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
#define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
/*! PCSSCK - PCS-to-SCK Delay */
#define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)

#define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
#define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
/*! SCKPCS - SCK-to-PCS Delay */
#define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
/*! @} */

/*! @name CCR1 - Clock Configuration 1 */
/*! @{ */

#define LPSPI_CCR1_SCKSET_MASK                   (0xFFU)
#define LPSPI_CCR1_SCKSET_SHIFT                  (0U)
/*! SCKSET - SCK Setup */
#define LPSPI_CCR1_SCKSET(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK)

#define LPSPI_CCR1_SCKHLD_MASK                   (0xFF00U)
#define LPSPI_CCR1_SCKHLD_SHIFT                  (8U)
/*! SCKHLD - SCK Hold */
#define LPSPI_CCR1_SCKHLD(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK)

#define LPSPI_CCR1_PCSPCS_MASK                   (0xFF0000U)
#define LPSPI_CCR1_PCSPCS_SHIFT                  (16U)
/*! PCSPCS - PCS to PCS delay */
#define LPSPI_CCR1_PCSPCS(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK)

#define LPSPI_CCR1_SCKSCK_MASK                   (0xFF000000U)
#define LPSPI_CCR1_SCKSCK_SHIFT                  (24U)
/*! SCKSCK - SCK Inter-Frame Delay */
#define LPSPI_CCR1_SCKSCK(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK)
/*! @} */

/*! @name FCR - FIFO Control */
/*! @{ */

#define LPSPI_FCR_TXWATER_MASK                   (0xFU)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
#define LPSPI_FCR_TXWATER_SHIFT                  (0U)
/*! TXWATER - Transmit FIFO Watermark */
#define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */

#define LPSPI_FCR_RXWATER_MASK                   (0xF0000U)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
#define LPSPI_FCR_RXWATER_SHIFT                  (16U)
/*! RXWATER - Receive FIFO Watermark */
#define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
/*! @} */

/*! @name FSR - FIFO Status */
/*! @{ */

#define LPSPI_FSR_TXCOUNT_MASK                   (0x1FU)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
/*! TXCOUNT - Transmit FIFO Count */
#define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */

#define LPSPI_FSR_RXCOUNT_MASK                   (0x1F0000U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
/*! RXCOUNT - Receive FIFO Count */
#define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
/*! @} */

/*! @name TCR - Transmit Command */
/*! @{ */

#define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
#define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
/*! FRAMESZ - Frame Size */
#define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)

#define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
#define LPSPI_TCR_WIDTH_SHIFT                    (16U)
/*! WIDTH - Transfer Width
 *  0b00..1-bit transfer
 *  0b01..2-bit transfer
 *  0b10..4-bit transfer
 *  0b11..Reserved
 */
#define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)

#define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
#define LPSPI_TCR_TXMSK_SHIFT                    (18U)
/*! TXMSK - Transmit Data Mask
 *  0b0..Normal transfer
 *  0b1..Mask transmit data
 */
#define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)

#define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
#define LPSPI_TCR_RXMSK_SHIFT                    (19U)
/*! RXMSK - Receive Data Mask
 *  0b0..Normal transfer
 *  0b1..Receive data is masked
 */
#define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)

#define LPSPI_TCR_CONTC_MASK                     (0x100000U)
#define LPSPI_TCR_CONTC_SHIFT                    (20U)
/*! CONTC - Continuing Command
 *  0b0..Command word for start of new transfer
 *  0b1..Command word for continuing transfer
 */
#define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)

#define LPSPI_TCR_CONT_MASK                      (0x200000U)
#define LPSPI_TCR_CONT_SHIFT                     (21U)
/*! CONT - Continuous Transfer
 *  0b0..Continuous transfer is disabled
 *  0b1..Continuous transfer is enabled
 */
#define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)

#define LPSPI_TCR_BYSW_MASK                      (0x400000U)
#define LPSPI_TCR_BYSW_SHIFT                     (22U)
/*! BYSW - Byte Swap
 *  0b0..Byte swap is disabled
 *  0b1..Byte swap is enabled
 */
#define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)

#define LPSPI_TCR_LSBF_MASK                      (0x800000U)
#define LPSPI_TCR_LSBF_SHIFT                     (23U)
/*! LSBF - LSB First
 *  0b0..Data is transferred MSB first
 *  0b1..Data is transferred LSB first
 */
#define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)

#define LPSPI_TCR_PCS_MASK                       (0x3000000U)
#define LPSPI_TCR_PCS_SHIFT                      (24U)
/*! PCS - Peripheral Chip Select
 *  0b00..Transfer using PCS[0]
 *  0b01..Transfer using PCS[1]
 *  0b10..Transfer using PCS[2]
 *  0b11..Transfer using PCS[3]
 */
#define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)

#define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
#define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
/*! PRESCALE - Prescaler Value
 *  0b000..Divide by 1
 *  0b001..Divide by 2
 *  0b010..Divide by 4
 *  0b011..Divide by 8
 *  0b100..Divide by 16
 *  0b101..Divide by 32
 *  0b110..Divide by 64
 *  0b111..Divide by 128
 */
#define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)

#define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
#define LPSPI_TCR_CPHA_SHIFT                     (30U)
/*! CPHA - Clock Phase
 *  0b0..Captured
 *  0b1..Changed
 */
#define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)

#define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
#define LPSPI_TCR_CPOL_SHIFT                     (31U)
/*! CPOL - Clock Polarity
 *  0b0..The inactive state value of SCK is low
 *  0b1..The inactive state value of SCK is high
 */
#define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
/*! @} */

/*! @name TDR - Transmit Data */
/*! @{ */

#define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
#define LPSPI_TDR_DATA_SHIFT                     (0U)
/*! DATA - Transmit Data */
#define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
/*! @} */

/*! @name RSR - Receive Status */
/*! @{ */

#define LPSPI_RSR_SOF_MASK                       (0x1U)
#define LPSPI_RSR_SOF_SHIFT                      (0U)
/*! SOF - Start Of Frame
 *  0b0..Subsequent data word received after PCS assertion
 *  0b1..First data word received after PCS assertion
 */
#define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)

#define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
#define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
/*! RXEMPTY - RX FIFO Empty
 *  0b0..RX FIFO is not empty
 *  0b1..RX FIFO is empty
 */
#define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
/*! @} */

/*! @name RDR - Receive Data */
/*! @{ */

#define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
#define LPSPI_RDR_DATA_SHIFT                     (0U)
/*! DATA - Receive Data */
#define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
/*! @} */

/*! @name RDROR - Receive Data Read Only */
/*! @{ */

#define LPSPI_RDROR_DATA_MASK                    (0xFFFFFFFFU)
#define LPSPI_RDROR_DATA_SHIFT                   (0U)
/*! DATA - Receive Data */
#define LPSPI_RDROR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK)
/*! @} */

/*! @name TCBR - Transmit Command Burst */
/*! @{ */

#define LPSPI_TCBR_DATA_MASK                     (0xFFFFFFFFU)
#define LPSPI_TCBR_DATA_SHIFT                    (0U)
/*! DATA - Command Data */
#define LPSPI_TCBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK)
/*! @} */

/*! @name TDBR - Transmit Data Burst */
/*! @{ */

#define LPSPI_TDBR_DATA_MASK                     (0xFFFFFFFFU)
#define LPSPI_TDBR_DATA_SHIFT                    (0U)
/*! DATA - Data */
#define LPSPI_TDBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK)
/*! @} */

/* The count of LPSPI_TDBR */
#define LPSPI_TDBR_COUNT                         (128U)

/*! @name RDBR - Receive Data Burst */
/*! @{ */

#define LPSPI_RDBR_DATA_MASK                     (0xFFFFFFFFU)
#define LPSPI_RDBR_DATA_SHIFT                    (0U)
/*! DATA - Data */
#define LPSPI_RDBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK)
/*! @} */

/* The count of LPSPI_RDBR */
#define LPSPI_RDBR_COUNT                         (128U)


/*!
 * @}
 */ /* end of group LPSPI_Register_Masks */


/* LPSPI - Peripheral instance base addresses */
/** Peripheral LPSPI0 base address */
#define LPSPI0_BASE                              (0x2803E000u)
/** Peripheral LPSPI0 base pointer */
#define LPSPI0                                   ((LPSPI_Type *)LPSPI0_BASE)
/** Peripheral LPSPI1 base address */
#define LPSPI1_BASE                              (0x2803F000u)
/** Peripheral LPSPI1 base pointer */
#define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
/** Peripheral LPSPI2 base address */
#define LPSPI2_BASE                              (0x2810D000u)
/** Peripheral LPSPI2 base pointer */
#define LPSPI2                                   ((LPSPI_Type *)LPSPI2_BASE)
/** Peripheral LPSPI3 base address */
#define LPSPI3_BASE                              (0x2810E000u)
/** Peripheral LPSPI3 base pointer */
#define LPSPI3                                   ((LPSPI_Type *)LPSPI3_BASE)
/** Peripheral LPSPI4 base address */
#define LPSPI4_BASE                              (0x293B0000u)
/** Peripheral LPSPI4 base pointer */
#define LPSPI4                                   ((LPSPI_Type *)LPSPI4_BASE)
/** Peripheral LPSPI5 base address */
#define LPSPI5_BASE                              (0x293C0000u)
/** Peripheral LPSPI5 base pointer */
#define LPSPI5                                   ((LPSPI_Type *)LPSPI5_BASE)
/** Array initializer of LPSPI peripheral base addresses */
#define LPSPI_BASE_ADDRS                         { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE }
/** Array initializer of LPSPI peripheral base pointers */
#define LPSPI_BASE_PTRS                          { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5 }

/*!
 * @}
 */ /* end of group LPSPI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPTMR Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
 * @{
 */

/** LPTMR - Register Layout Typedef */
typedef struct {
  __IO uint32_t CSR;                               /**< Control Status Register, offset: 0x0 */
  __IO uint32_t PSR;                               /**< Prescale and Glitch Filter Register, offset: 0x4 */
  __IO uint32_t CMR;                               /**< Compare Register, offset: 0x8 */
  __IO uint32_t CNR;                               /**< Counter Register, offset: 0xC */
} LPTMR_Type;

/* ----------------------------------------------------------------------------
   -- LPTMR Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
 * @{
 */

/*! @name CSR - Control Status Register */
/*! @{ */

#define LPTMR_CSR_TEN_MASK                       (0x1U)
#define LPTMR_CSR_TEN_SHIFT                      (0U)
/*! TEN - Timer Enable
 *  0b0..LPTMR is disabled and internal logic is reset.
 *  0b1..LPTMR is enabled.
 */
#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)

#define LPTMR_CSR_TMS_MASK                       (0x2U)
#define LPTMR_CSR_TMS_SHIFT                      (1U)
/*! TMS - Timer Mode Select
 *  0b0..Time Counter mode.
 *  0b1..Pulse Counter mode.
 */
#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)

#define LPTMR_CSR_TFC_MASK                       (0x4U)
#define LPTMR_CSR_TFC_SHIFT                      (2U)
/*! TFC - Timer Free-Running Counter
 *  0b0..CNR is reset whenever TCF is set.
 *  0b1..CNR is reset on overflow.
 */
#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)

#define LPTMR_CSR_TPP_MASK                       (0x8U)
#define LPTMR_CSR_TPP_SHIFT                      (3U)
/*! TPP - Timer Pin Polarity
 *  0b0..Pulse Counter input source is active-high, and the CNR increments on the rising-edge.
 *  0b1..Pulse Counter input source is active-low, and the CNR increments on the falling-edge.
 */
#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)

#define LPTMR_CSR_TPS_MASK                       (0x30U)
#define LPTMR_CSR_TPS_SHIFT                      (4U)
/*! TPS - Timer Pin Select
 *  0b00..Pulse counter input 0 is selected.
 *  0b01..Pulse counter input 1 is selected.
 *  0b10..Pulse counter input 2 is selected.
 *  0b11..Pulse counter input 3 is selected.
 */
#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)

#define LPTMR_CSR_TIE_MASK                       (0x40U)
#define LPTMR_CSR_TIE_SHIFT                      (6U)
/*! TIE - Timer Interrupt Enable
 *  0b0..Timer interrupt disabled.
 *  0b1..Timer interrupt enabled.
 */
#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)

#define LPTMR_CSR_TCF_MASK                       (0x80U)
#define LPTMR_CSR_TCF_SHIFT                      (7U)
/*! TCF - Timer Compare Flag
 *  0b0..The value of CNR is not equal to CMR + 1.
 *  0b1..The value of CNR is equal to CMR + 1.
 */
#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)

#define LPTMR_CSR_TDRE_MASK                      (0x100U)
#define LPTMR_CSR_TDRE_SHIFT                     (8U)
/*! TDRE - Timer DMA Request Enable
 *  0b0..Timer DMA Request disabled.
 *  0b1..Timer DMA Request enabled.
 */
#define LPTMR_CSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK)
/*! @} */

/*! @name PSR - Prescale and Glitch Filter Register */
/*! @{ */

#define LPTMR_PSR_PCS_MASK                       (0x3U)
#define LPTMR_PSR_PCS_SHIFT                      (0U)
/*! PCS - Prescaler/Glitch Filter Clock Select
 *  0b00..Prescaler/glitch filter clock 0 selected.
 *  0b01..Prescaler/glitch filter clock 1 selected.
 *  0b10..Prescaler/glitch filter clock 2 selected.
 *  0b11..Prescaler/glitch filter clock 3 selected.
 */
#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)

#define LPTMR_PSR_PBYP_MASK                      (0x4U)
#define LPTMR_PSR_PBYP_SHIFT                     (2U)
/*! PBYP - Prescaler/Glitch Filter Bypass
 *  0b0..Prescaler/glitch filter is enabled.
 *  0b1..Prescaler/glitch filter is bypassed.
 */
#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)

#define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
#define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
/*! PRESCALE - Prescale/Glitch Filter Value
 *  0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
 *  0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
 *  0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
 *  0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
 *  0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
 *  0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
 *  0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
 *  0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
 *  0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
 *  0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
 *  0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
 *  0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
 *  0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
 *  0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
 *  0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
 *  0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
 */
#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
/*! @} */

/*! @name CMR - Compare Register */
/*! @{ */

#define LPTMR_CMR_COMPARE_MASK                   (0xFFFFU)
#define LPTMR_CMR_COMPARE_SHIFT                  (0U)
/*! COMPARE - Compare Value */
#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
/*! @} */

/*! @name CNR - Counter Register */
/*! @{ */

#define LPTMR_CNR_COUNTER_MASK                   (0xFFFFU)
#define LPTMR_CNR_COUNTER_SHIFT                  (0U)
/*! COUNTER - Counter Value */
#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LPTMR_Register_Masks */


/* LPTMR - Peripheral instance base addresses */
/** Peripheral LPTMR0 base address */
#define LPTMR0_BASE                              (0x28093000u)
/** Peripheral LPTMR0 base pointer */
#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
/** Peripheral LPTMR1 base address */
#define LPTMR1_BASE                              (0x28094000u)
/** Peripheral LPTMR1 base pointer */
#define LPTMR1                                   ((LPTMR_Type *)LPTMR1_BASE)
/** Array initializer of LPTMR peripheral base addresses */
#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE, LPTMR1_BASE }
/** Array initializer of LPTMR peripheral base pointers */
#define LPTMR_BASE_PTRS                          { LPTMR0, LPTMR1 }

/*!
 * @}
 */ /* end of group LPTMR_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPUART Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
 * @{
 */

/** LPUART - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __IO uint32_t GLOBAL;                            /**< LPUART Global Register, offset: 0x8 */
  __IO uint32_t PINCFG;                            /**< LPUART Pin Configuration Register, offset: 0xC */
  __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x10 */
  __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x14 */
  __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x18 */
  __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0x1C */
  __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x20 */
  __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x24 */
  __IO uint32_t FIFO;                              /**< LPUART FIFO Register, offset: 0x28 */
  __IO uint32_t WATER;                             /**< LPUART Watermark Register, offset: 0x2C */
} LPUART_Type;

/* ----------------------------------------------------------------------------
   -- LPUART Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPUART_Register_Masks LPUART Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
#define LPUART_VERID_FEATURE_SHIFT               (0U)
/*! FEATURE - Feature Identification Number
 *  0b0000000000000001..Standard feature set.
 *  0b0000000000000011..Standard feature set with MODEM/IrDA support.
 */
#define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)

#define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
#define LPUART_VERID_MINOR_SHIFT                 (16U)
/*! MINOR - Minor Version Number */
#define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)

#define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
#define LPUART_VERID_MAJOR_SHIFT                 (24U)
/*! MAJOR - Major Version Number */
#define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
#define LPUART_PARAM_TXFIFO_SHIFT                (0U)
/*! TXFIFO - Transmit FIFO Size */
#define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)

#define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
#define LPUART_PARAM_RXFIFO_SHIFT                (8U)
/*! RXFIFO - Receive FIFO Size */
#define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
/*! @} */

/*! @name GLOBAL - LPUART Global Register */
/*! @{ */

#define LPUART_GLOBAL_RST_MASK                   (0x2U)
#define LPUART_GLOBAL_RST_SHIFT                  (1U)
/*! RST - Software Reset
 *  0b0..Module is not reset.
 *  0b1..Module is reset.
 */
#define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
/*! @} */

/*! @name PINCFG - LPUART Pin Configuration Register */
/*! @{ */

#define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
#define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
/*! TRGSEL - Trigger Select
 *  0b00..Input trigger is disabled.
 *  0b01..Input trigger is used instead of RXD pin input.
 *  0b10..Input trigger is used instead of CTS_B pin input.
 *  0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is
 *        internally ANDed with the input trigger.
 */
#define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
/*! @} */

/*! @name BAUD - LPUART Baud Rate Register */
/*! @{ */

#define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
#define LPUART_BAUD_SBR_SHIFT                    (0U)
/*! SBR - Baud Rate Modulo Divisor. */
#define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)

#define LPUART_BAUD_SBNS_MASK                    (0x2000U)
#define LPUART_BAUD_SBNS_SHIFT                   (13U)
/*! SBNS - Stop Bit Number Select
 *  0b0..One stop bit.
 *  0b1..Two stop bits.
 */
#define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)

#define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
#define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
/*! RXEDGIE - RX Input Active Edge Interrupt Enable
 *  0b0..Hardware interrupts from STAT[RXEDGIF] are disabled.
 *  0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.
 */
#define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)

#define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
#define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
/*! LBKDIE - LIN Break Detect Interrupt Enable
 *  0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).
 *  0b1..Hardware interrupt is requested when STAT[LBKDIF] flag is 1.
 */
#define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)

#define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
#define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
/*! RESYNCDIS - Resynchronization Disable
 *  0b0..Resynchronization during received data word is supported.
 *  0b1..Resynchronization during received data word is disabled.
 */
#define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)

#define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
#define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
/*! BOTHEDGE - Both Edge Sampling
 *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
 *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
 */
#define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)

#define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
#define LPUART_BAUD_MATCFG_SHIFT                 (18U)
/*! MATCFG - Match Configuration
 *  0b00..Address Match Wakeup
 *  0b01..Idle Match Wakeup
 *  0b10..Match On and Match Off
 *  0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
 */
#define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)

#define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
#define LPUART_BAUD_RDMAE_SHIFT                  (21U)
/*! RDMAE - Receiver Full DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)

#define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
#define LPUART_BAUD_TDMAE_SHIFT                  (23U)
/*! TDMAE - Transmitter DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)

#define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
#define LPUART_BAUD_OSR_SHIFT                    (24U)
/*! OSR - Oversampling Ratio
 *  0b00000..Writing 0 to this field results in an oversampling ratio of 16
 *  0b00001..Reserved
 *  0b00010..Reserved
 *  0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
 *  0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
 *  0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
 *  0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
 *  0b00111..Oversampling ratio of 8.
 *  0b01000..Oversampling ratio of 9.
 *  0b01001..Oversampling ratio of 10.
 *  0b01010..Oversampling ratio of 11.
 *  0b01011..Oversampling ratio of 12.
 *  0b01100..Oversampling ratio of 13.
 *  0b01101..Oversampling ratio of 14.
 *  0b01110..Oversampling ratio of 15.
 *  0b01111..Oversampling ratio of 16.
 *  0b10000..Oversampling ratio of 17.
 *  0b10001..Oversampling ratio of 18.
 *  0b10010..Oversampling ratio of 19.
 *  0b10011..Oversampling ratio of 20.
 *  0b10100..Oversampling ratio of 21.
 *  0b10101..Oversampling ratio of 22.
 *  0b10110..Oversampling ratio of 23.
 *  0b10111..Oversampling ratio of 24.
 *  0b11000..Oversampling ratio of 25.
 *  0b11001..Oversampling ratio of 26.
 *  0b11010..Oversampling ratio of 27.
 *  0b11011..Oversampling ratio of 28.
 *  0b11100..Oversampling ratio of 29.
 *  0b11101..Oversampling ratio of 30.
 *  0b11110..Oversampling ratio of 31.
 *  0b11111..Oversampling ratio of 32.
 */
#define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)

#define LPUART_BAUD_M10_MASK                     (0x20000000U)
#define LPUART_BAUD_M10_SHIFT                    (29U)
/*! M10 - 10-bit Mode select
 *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
 *  0b1..Receiver and transmitter use 10-bit data characters.
 */
#define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)

#define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
#define LPUART_BAUD_MAEN2_SHIFT                  (30U)
/*! MAEN2 - Match Address Mode Enable 2
 *  0b0..Normal operation.
 *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
 */
#define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)

#define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
#define LPUART_BAUD_MAEN1_SHIFT                  (31U)
/*! MAEN1 - Match Address Mode Enable 1
 *  0b0..Normal operation.
 *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
 */
#define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
/*! @} */

/*! @name STAT - LPUART Status Register */
/*! @{ */

#define LPUART_STAT_MA2F_MASK                    (0x4000U)
#define LPUART_STAT_MA2F_SHIFT                   (14U)
/*! MA2F - Match 2 Flag
 *  0b0..Received data is not equal to MA2
 *  0b1..Received data is equal to MA2
 */
#define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)

#define LPUART_STAT_MA1F_MASK                    (0x8000U)
#define LPUART_STAT_MA1F_SHIFT                   (15U)
/*! MA1F - Match 1 Flag
 *  0b0..Received data is not equal to MA1
 *  0b1..Received data is equal to MA1
 */
#define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)

#define LPUART_STAT_PF_MASK                      (0x10000U)
#define LPUART_STAT_PF_SHIFT                     (16U)
/*! PF - Parity Error Flag
 *  0b0..No parity error.
 *  0b1..Parity error.
 */
#define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)

#define LPUART_STAT_FE_MASK                      (0x20000U)
#define LPUART_STAT_FE_SHIFT                     (17U)
/*! FE - Framing Error Flag
 *  0b0..No framing error detected. This does not guarantee the framing is correct.
 *  0b1..Framing error.
 */
#define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)

#define LPUART_STAT_NF_MASK                      (0x40000U)
#define LPUART_STAT_NF_SHIFT                     (18U)
/*! NF - Noise Flag
 *  0b0..No noise detected.
 *  0b1..Noise detected in the received character in the DATA register.
 */
#define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)

#define LPUART_STAT_OR_MASK                      (0x80000U)
#define LPUART_STAT_OR_SHIFT                     (19U)
/*! OR - Receiver Overrun Flag
 *  0b0..No overrun.
 *  0b1..Receive overrun (new LPUART data lost).
 */
#define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)

#define LPUART_STAT_IDLE_MASK                    (0x100000U)
#define LPUART_STAT_IDLE_SHIFT                   (20U)
/*! IDLE - Idle Line Flag
 *  0b0..No idle line detected.
 *  0b1..Idle line is detected.
 */
#define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)

#define LPUART_STAT_RDRF_MASK                    (0x200000U)
#define LPUART_STAT_RDRF_SHIFT                   (21U)
/*! RDRF - Receive Data Register Full Flag
 *  0b0..Receive FIFO level is less than watermark.
 *  0b1..Receive FIFO level is equal or greater than watermark.
 */
#define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)

#define LPUART_STAT_TC_MASK                      (0x400000U)
#define LPUART_STAT_TC_SHIFT                     (22U)
/*! TC - Transmission Complete Flag
 *  0b0..Transmitter active (sending data, a preamble, or a break).
 *  0b1..Transmitter idle (transmission activity complete).
 */
#define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)

#define LPUART_STAT_TDRE_MASK                    (0x800000U)
#define LPUART_STAT_TDRE_SHIFT                   (23U)
/*! TDRE - Transmit Data Register Empty Flag
 *  0b0..Transmit FIFO level is greater than watermark.
 *  0b1..Transmit FIFO level is equal or less than watermark.
 */
#define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)

#define LPUART_STAT_RAF_MASK                     (0x1000000U)
#define LPUART_STAT_RAF_SHIFT                    (24U)
/*! RAF - Receiver Active Flag
 *  0b0..LPUART receiver idle waiting for a start bit.
 *  0b1..LPUART receiver active (RXD input not idle).
 */
#define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)

#define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
#define LPUART_STAT_LBKDE_SHIFT                  (25U)
/*! LBKDE - LIN Break Detection Enable
 *  0b0..LIN break detect is disabled, normal break character can be detected.
 *  0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
 */
#define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)

#define LPUART_STAT_BRK13_MASK                   (0x4000000U)
#define LPUART_STAT_BRK13_SHIFT                  (26U)
/*! BRK13 - Break Character Generation Length
 *  0b0..Break character is transmitted with length of 9 to 13 bit times.
 *  0b1..Break character is transmitted with length of 12 to 15 bit times.
 */
#define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)

#define LPUART_STAT_RWUID_MASK                   (0x8000000U)
#define LPUART_STAT_RWUID_SHIFT                  (27U)
/*! RWUID - Receive Wake Up Idle Detect
 *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
 *       character. During address match wakeup, the IDLE bit does not set when an address does not match.
 *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During
 *       address match wakeup, the IDLE bit does set when an address does not match.
 */
#define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)

#define LPUART_STAT_RXINV_MASK                   (0x10000000U)
#define LPUART_STAT_RXINV_SHIFT                  (28U)
/*! RXINV - Receive Data Inversion
 *  0b0..Receive data not inverted.
 *  0b1..Receive data inverted.
 */
#define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)

#define LPUART_STAT_MSBF_MASK                    (0x20000000U)
#define LPUART_STAT_MSBF_SHIFT                   (29U)
/*! MSBF - MSB First
 *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received
 *       after the start bit is identified as bit0.
 *  0b1..MSB (identified as bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit
 *       depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. .
 */
#define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)

#define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
#define LPUART_STAT_RXEDGIF_SHIFT                (30U)
/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
 *  0b0..No active edge on the receive pin has occurred.
 *  0b1..An active edge on the receive pin has occurred.
 */
#define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)

#define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
#define LPUART_STAT_LBKDIF_SHIFT                 (31U)
/*! LBKDIF - LIN Break Detect Interrupt Flag
 *  0b0..No LIN break character has been detected.
 *  0b1..LIN break character has been detected.
 */
#define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
/*! @} */

/*! @name CTRL - LPUART Control Register */
/*! @{ */

#define LPUART_CTRL_PT_MASK                      (0x1U)
#define LPUART_CTRL_PT_SHIFT                     (0U)
/*! PT - Parity Type
 *  0b0..Even parity.
 *  0b1..Odd parity.
 */
#define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)

#define LPUART_CTRL_PE_MASK                      (0x2U)
#define LPUART_CTRL_PE_SHIFT                     (1U)
/*! PE - Parity Enable
 *  0b0..No hardware parity generation or checking.
 *  0b1..Parity enabled.
 */
#define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)

#define LPUART_CTRL_ILT_MASK                     (0x4U)
#define LPUART_CTRL_ILT_SHIFT                    (2U)
/*! ILT - Idle Line Type Select
 *  0b0..Idle character bit count starts after start bit.
 *  0b1..Idle character bit count starts after stop bit.
 */
#define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)

#define LPUART_CTRL_WAKE_MASK                    (0x8U)
#define LPUART_CTRL_WAKE_SHIFT                   (3U)
/*! WAKE - Receiver Wakeup Method Select
 *  0b0..Configures RWU for idle-line wakeup.
 *  0b1..Configures RWU with address-mark wakeup.
 */
#define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)

#define LPUART_CTRL_M_MASK                       (0x10U)
#define LPUART_CTRL_M_SHIFT                      (4U)
/*! M - 9-Bit or 8-Bit Mode Select
 *  0b0..Receiver and transmitter use 8-bit data characters.
 *  0b1..Receiver and transmitter use 9-bit data characters.
 */
#define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)

#define LPUART_CTRL_RSRC_MASK                    (0x20U)
#define LPUART_CTRL_RSRC_SHIFT                   (5U)
/*! RSRC - Receiver Source Select
 *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
 *  0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
 */
#define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)

#define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
#define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
/*! DOZEEN - Doze Enable
 *  0b0..LPUART is enabled in Doze mode.
 *  0b1..LPUART is disabled in Doze mode , but remains active when not in Doze mode .
 */
#define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)

#define LPUART_CTRL_LOOPS_MASK                   (0x80U)
#define LPUART_CTRL_LOOPS_SHIFT                  (7U)
/*! LOOPS - Loop Mode Select
 *  0b0..Normal operation - RXD and TXD use separate pins.
 *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
 */
#define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)

#define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
#define LPUART_CTRL_IDLECFG_SHIFT                (8U)
/*! IDLECFG - Idle Configuration
 *  0b000..1 idle character
 *  0b001..2 idle characters
 *  0b010..4 idle characters
 *  0b011..8 idle characters
 *  0b100..16 idle characters
 *  0b101..32 idle characters
 *  0b110..64 idle characters
 *  0b111..128 idle characters
 */
#define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)

#define LPUART_CTRL_M7_MASK                      (0x800U)
#define LPUART_CTRL_M7_SHIFT                     (11U)
/*! M7 - 7-Bit Mode Select
 *  0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
 *  0b1..Receiver and transmitter use 7-bit data characters.
 */
#define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)

#define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
#define LPUART_CTRL_MA2IE_SHIFT                  (14U)
/*! MA2IE - Match 2 Interrupt Enable
 *  0b0..MA2F interrupt disabled
 *  0b1..MA2F interrupt enabled
 */
#define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)

#define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
#define LPUART_CTRL_MA1IE_SHIFT                  (15U)
/*! MA1IE - Match 1 Interrupt Enable
 *  0b0..MA1F interrupt disabled
 *  0b1..MA1F interrupt enabled
 */
#define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)

#define LPUART_CTRL_SBK_MASK                     (0x10000U)
#define LPUART_CTRL_SBK_SHIFT                    (16U)
/*! SBK - Send Break
 *  0b0..Normal transmitter operation.
 *  0b1..Queue break character(s) to be sent.
 */
#define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)

#define LPUART_CTRL_RWU_MASK                     (0x20000U)
#define LPUART_CTRL_RWU_SHIFT                    (17U)
/*! RWU - Receiver Wakeup Control
 *  0b0..Normal receiver operation.
 *  0b1..LPUART receiver in standby waiting for wakeup condition.
 */
#define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)

#define LPUART_CTRL_RE_MASK                      (0x40000U)
#define LPUART_CTRL_RE_SHIFT                     (18U)
/*! RE - Receiver Enable
 *  0b0..Receiver disabled.
 *  0b1..Receiver enabled.
 */
#define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)

#define LPUART_CTRL_TE_MASK                      (0x80000U)
#define LPUART_CTRL_TE_SHIFT                     (19U)
/*! TE - Transmitter Enable
 *  0b0..Transmitter disabled.
 *  0b1..Transmitter enabled.
 */
#define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)

#define LPUART_CTRL_ILIE_MASK                    (0x100000U)
#define LPUART_CTRL_ILIE_SHIFT                   (20U)
/*! ILIE - Idle Line Interrupt Enable
 *  0b0..Hardware interrupts from IDLE disabled; use polling.
 *  0b1..Hardware interrupt is requested when IDLE flag is 1.
 */
#define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)

#define LPUART_CTRL_RIE_MASK                     (0x200000U)
#define LPUART_CTRL_RIE_SHIFT                    (21U)
/*! RIE - Receiver Interrupt Enable
 *  0b0..Hardware interrupts from RDRF disabled.
 *  0b1..Hardware interrupt is requested when RDRF flag is 1.
 */
#define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)

#define LPUART_CTRL_TCIE_MASK                    (0x400000U)
#define LPUART_CTRL_TCIE_SHIFT                   (22U)
/*! TCIE - Transmission Complete Interrupt Enable for
 *  0b0..Hardware interrupts from TC disabled.
 *  0b1..Hardware interrupt is requested when TC flag is 1.
 */
#define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)

#define LPUART_CTRL_TIE_MASK                     (0x800000U)
#define LPUART_CTRL_TIE_SHIFT                    (23U)
/*! TIE - Transmit Interrupt Enable
 *  0b0..Hardware interrupts from TDRE disabled.
 *  0b1..Hardware interrupt is requested when TDRE flag is 1.
 */
#define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)

#define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
#define LPUART_CTRL_PEIE_SHIFT                   (24U)
/*! PEIE - Parity Error Interrupt Enable
 *  0b0..PF interrupts disabled; use polling).
 *  0b1..Hardware interrupt is requested when PF is set.
 */
#define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)

#define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
#define LPUART_CTRL_FEIE_SHIFT                   (25U)
/*! FEIE - Framing Error Interrupt Enable
 *  0b0..FE interrupts disabled; use polling.
 *  0b1..Hardware interrupt is requested when FE is set.
 */
#define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)

#define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
#define LPUART_CTRL_NEIE_SHIFT                   (26U)
/*! NEIE - Noise Error Interrupt Enable
 *  0b0..NF interrupts disabled; use polling.
 *  0b1..Hardware interrupt is requested when NF is set.
 */
#define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)

#define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
#define LPUART_CTRL_ORIE_SHIFT                   (27U)
/*! ORIE - Overrun Interrupt Enable
 *  0b0..OR interrupts disabled; use polling.
 *  0b1..Hardware interrupt is requested when OR is set.
 */
#define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)

#define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
#define LPUART_CTRL_TXINV_SHIFT                  (28U)
/*! TXINV - Transmit Data Inversion
 *  0b0..Transmit data not inverted.
 *  0b1..Transmit data inverted.
 */
#define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)

#define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
#define LPUART_CTRL_TXDIR_SHIFT                  (29U)
/*! TXDIR - TXD Pin Direction in Single-Wire Mode
 *  0b0..TXD pin is an input in single-wire mode.
 *  0b1..TXD pin is an output in single-wire mode.
 */
#define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)

#define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
#define LPUART_CTRL_R9T8_SHIFT                   (30U)
/*! R9T8 - Receive Bit 9 / Transmit Bit 8 */
#define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)

#define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
#define LPUART_CTRL_R8T9_SHIFT                   (31U)
/*! R8T9 - Receive Bit 8 / Transmit Bit 9 */
#define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
/*! @} */

/*! @name DATA - LPUART Data Register */
/*! @{ */

#define LPUART_DATA_R0T0_MASK                    (0x1U)
#define LPUART_DATA_R0T0_SHIFT                   (0U)
/*! R0T0 - R0T0 */
#define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)

#define LPUART_DATA_R1T1_MASK                    (0x2U)
#define LPUART_DATA_R1T1_SHIFT                   (1U)
/*! R1T1 - R1T1 */
#define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)

#define LPUART_DATA_R2T2_MASK                    (0x4U)
#define LPUART_DATA_R2T2_SHIFT                   (2U)
/*! R2T2 - R2T2 */
#define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)

#define LPUART_DATA_R3T3_MASK                    (0x8U)
#define LPUART_DATA_R3T3_SHIFT                   (3U)
/*! R3T3 - R3T3 */
#define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)

#define LPUART_DATA_R4T4_MASK                    (0x10U)
#define LPUART_DATA_R4T4_SHIFT                   (4U)
/*! R4T4 - R4T4 */
#define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)

#define LPUART_DATA_R5T5_MASK                    (0x20U)
#define LPUART_DATA_R5T5_SHIFT                   (5U)
/*! R5T5 - R5T5 */
#define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)

#define LPUART_DATA_R6T6_MASK                    (0x40U)
#define LPUART_DATA_R6T6_SHIFT                   (6U)
/*! R6T6 - R6T6 */
#define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)

#define LPUART_DATA_R7T7_MASK                    (0x80U)
#define LPUART_DATA_R7T7_SHIFT                   (7U)
/*! R7T7 - R7T7 */
#define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)

#define LPUART_DATA_R8T8_MASK                    (0x100U)
#define LPUART_DATA_R8T8_SHIFT                   (8U)
/*! R8T8 - R8T8 */
#define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)

#define LPUART_DATA_R9T9_MASK                    (0x200U)
#define LPUART_DATA_R9T9_SHIFT                   (9U)
/*! R9T9 - R9T9 */
#define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)

#define LPUART_DATA_IDLINE_MASK                  (0x800U)
#define LPUART_DATA_IDLINE_SHIFT                 (11U)
/*! IDLINE - Idle Line
 *  0b0..Receiver was not idle before receiving this character.
 *  0b1..Receiver was idle before receiving this character.
 */
#define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)

#define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
#define LPUART_DATA_RXEMPT_SHIFT                 (12U)
/*! RXEMPT - Receive Buffer Empty
 *  0b0..Receive buffer contains valid data.
 *  0b1..Receive buffer is empty, data returned on read is not valid.
 */
#define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)

#define LPUART_DATA_FRETSC_MASK                  (0x2000U)
#define LPUART_DATA_FRETSC_SHIFT                 (13U)
/*! FRETSC - Frame Error / Transmit Special Character
 *  0b0..The dataword is received without a frame error on read, or transmit a normal character on write.
 *  0b1..The dataword is received with a frame error, or transmit an idle or break character on transmit.
 */
#define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)

#define LPUART_DATA_PARITYE_MASK                 (0x4000U)
#define LPUART_DATA_PARITYE_SHIFT                (14U)
/*! PARITYE - Parity Error
 *  0b0..The dataword is received without a parity error.
 *  0b1..The dataword is received with a parity error.
 */
#define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)

#define LPUART_DATA_NOISY_MASK                   (0x8000U)
#define LPUART_DATA_NOISY_SHIFT                  (15U)
/*! NOISY - Noisy Data Received
 *  0b0..The dataword is received without noise.
 *  0b1..The data is received with noise.
 */
#define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
/*! @} */

/*! @name MATCH - LPUART Match Address Register */
/*! @{ */

#define LPUART_MATCH_MA1_MASK                    (0x3FFU)
#define LPUART_MATCH_MA1_SHIFT                   (0U)
/*! MA1 - Match Address 1 */
#define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)

#define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
#define LPUART_MATCH_MA2_SHIFT                   (16U)
/*! MA2 - Match Address 2 */
#define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
/*! @} */

/*! @name MODIR - LPUART Modem IrDA Register */
/*! @{ */

#define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
#define LPUART_MODIR_TXCTSE_SHIFT                (0U)
/*! TXCTSE - Transmitter clear-to-send enable
 *  0b0..CTS has no effect on the transmitter.
 *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a
 *       character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the
 *       mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent
 *       do not affect its transmission.
 */
#define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)

#define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
#define LPUART_MODIR_TXRTSE_SHIFT                (1U)
/*! TXRTSE - Transmitter request-to-send enable
 *  0b0..The transmitter has no effect on RTS.
 *  0b1..When a character is placed into an empty transmit shift register, RTS asserts one bit time before the
 *       start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter FIFO and shift
 *       register are completely sent, including the last stop bit.
 */
#define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)

#define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
#define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
/*! TXRTSPOL - Transmitter request-to-send polarity
 *  0b0..Transmitter RTS is active low.
 *  0b1..Transmitter RTS is active high.
 */
#define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)

#define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
#define LPUART_MODIR_RXRTSE_SHIFT                (3U)
/*! RXRTSE - Receiver request-to-send enable
 *  0b0..The receiver has no effect on RTS.
 *  0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause
 *       the receiver data register to become full. RTS is asserted if the receiver data register is not full and
 *       has not detected a start bit that would cause the receiver data register to become full.
 */
#define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)

#define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
#define LPUART_MODIR_TXCTSC_SHIFT                (4U)
/*! TXCTSC - Transmit CTS Configuration
 *  0b0..CTS input is sampled at the start of each character.
 *  0b1..CTS input is sampled when the transmitter is idle.
 */
#define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)

#define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
#define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
/*! TXCTSSRC - Transmit CTS Source
 *  0b0..CTS input is the CTS_B pin.
 *  0b1..CTS input is an internal connection to the receiver address match result.
 */
#define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)

#define LPUART_MODIR_RTSWATER_MASK               (0x700U)
#define LPUART_MODIR_RTSWATER_SHIFT              (8U)
/*! RTSWATER - Receive RTS Configuration */
#define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)

#define LPUART_MODIR_TNP_MASK                    (0x30000U)
#define LPUART_MODIR_TNP_SHIFT                   (16U)
/*! TNP - Transmitter narrow pulse
 *  0b00..1/OSR.
 *  0b01..2/OSR.
 *  0b10..3/OSR.
 *  0b11..4/OSR.
 */
#define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)

#define LPUART_MODIR_IREN_MASK                   (0x40000U)
#define LPUART_MODIR_IREN_SHIFT                  (18U)
/*! IREN - Infrared enable
 *  0b0..IR disabled.
 *  0b1..IR enabled.
 */
#define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
/*! @} */

/*! @name FIFO - LPUART FIFO Register */
/*! @{ */

#define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
#define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
/*! RXFIFOSIZE - Receive FIFO Buffer Depth
 *  0b000..Receive FIFO/Buffer depth = 1 dataword.
 *  0b001..Receive FIFO/Buffer depth = 4 datawords.
 *  0b010..Receive FIFO/Buffer depth = 8 datawords.
 *  0b011..Receive FIFO/Buffer depth = 16 datawords.
 *  0b100..Receive FIFO/Buffer depth = 32 datawords.
 *  0b101..Receive FIFO/Buffer depth = 64 datawords.
 *  0b110..Receive FIFO/Buffer depth = 128 datawords.
 *  0b111..Receive FIFO/Buffer depth = 256 datawords.
 */
#define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)

#define LPUART_FIFO_RXFE_MASK                    (0x8U)
#define LPUART_FIFO_RXFE_SHIFT                   (3U)
/*! RXFE - Receive FIFO Enable
 *  0b0..Receive FIFO is not enabled. Buffer depth is 1.
 *  0b1..Receive FIFO is enabled. Buffer depth is indicted by RXFIFOSIZE.
 */
#define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)

#define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
#define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
/*! TXFIFOSIZE - Transmit FIFO Buffer Depth
 *  0b000..Transmit FIFO/Buffer depth = 1 dataword.
 *  0b001..Transmit FIFO/Buffer depth = 4 datawords.
 *  0b010..Transmit FIFO/Buffer depth = 8 datawords.
 *  0b011..Transmit FIFO/Buffer depth = 16 datawords.
 *  0b100..Transmit FIFO/Buffer depth = 32 datawords.
 *  0b101..Transmit FIFO/Buffer depth = 64 datawords.
 *  0b110..Transmit FIFO/Buffer depth = 128 datawords.
 *  0b111..Transmit FIFO/Buffer depth = 256 datawords
 */
#define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)

#define LPUART_FIFO_TXFE_MASK                    (0x80U)
#define LPUART_FIFO_TXFE_SHIFT                   (7U)
/*! TXFE - Transmit FIFO Enable
 *  0b0..Transmit FIFO is not enabled. Buffer depth is 1.
 *  0b1..Transmit FIFO is enabled. Buffer depth is indicated by TXFIFOSIZE.
 */
#define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)

#define LPUART_FIFO_RXUFE_MASK                   (0x100U)
#define LPUART_FIFO_RXUFE_SHIFT                  (8U)
/*! RXUFE - Receive FIFO Underflow Interrupt Enable
 *  0b0..RXUF flag does not generate an interrupt to the host.
 *  0b1..RXUF flag generates an interrupt to the host.
 */
#define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)

#define LPUART_FIFO_TXOFE_MASK                   (0x200U)
#define LPUART_FIFO_TXOFE_SHIFT                  (9U)
/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
 *  0b0..TXOF flag does not generate an interrupt to the host.
 *  0b1..TXOF flag generates an interrupt to the host.
 */
#define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)

#define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
#define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
/*! RXIDEN - Receiver Idle Empty Enable
 *  0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
 *  0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
 *  0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
 *  0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
 *  0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
 *  0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
 *  0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
 *  0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
 */
#define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)

#define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
#define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
/*! RXFLUSH - Receive FIFO Flush
 *  0b0..No flush operation occurs.
 *  0b1..All data in the receive FIFO/buffer is cleared out.
 */
#define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)

#define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
#define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
/*! TXFLUSH - Transmit FIFO Flush
 *  0b0..No flush operation occurs.
 *  0b1..All data in the transmit FIFO is cleared out.
 */
#define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)

#define LPUART_FIFO_RXUF_MASK                    (0x10000U)
#define LPUART_FIFO_RXUF_SHIFT                   (16U)
/*! RXUF - Receiver FIFO Underflow Flag
 *  0b0..No receive FIFO underflow has occurred since the last time the flag was cleared.
 *  0b1..At least one receive FIFO underflow has occurred since the last time the flag was cleared.
 */
#define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)

#define LPUART_FIFO_TXOF_MASK                    (0x20000U)
#define LPUART_FIFO_TXOF_SHIFT                   (17U)
/*! TXOF - Transmitter FIFO Overflow Flag
 *  0b0..No transmit FIFO overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one transmit FIFO overflow has occurred since the last time the flag was cleared.
 */
#define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)

#define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
#define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
/*! RXEMPT - Receive FIFO/Buffer Empty
 *  0b0..Receive buffer is not empty.
 *  0b1..Receive buffer is empty.
 */
#define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)

#define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
#define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
/*! TXEMPT - Transmit FIFO/Buffer Empty
 *  0b0..Transmit buffer is not empty.
 *  0b1..Transmit buffer is empty.
 */
#define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
/*! @} */

/*! @name WATER - LPUART Watermark Register */
/*! @{ */

#define LPUART_WATER_TXWATER_MASK                (0x7U)
#define LPUART_WATER_TXWATER_SHIFT               (0U)
/*! TXWATER - Transmit Watermark */
#define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)

#define LPUART_WATER_TXCOUNT_MASK                (0xF00U)
#define LPUART_WATER_TXCOUNT_SHIFT               (8U)
/*! TXCOUNT - Transmit Counter */
#define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)

#define LPUART_WATER_RXWATER_MASK                (0x70000U)
#define LPUART_WATER_RXWATER_SHIFT               (16U)
/*! RXWATER - Receive Watermark */
#define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)

#define LPUART_WATER_RXCOUNT_MASK                (0xF000000U)
#define LPUART_WATER_RXCOUNT_SHIFT               (24U)
/*! RXCOUNT - Receive Counter */
#define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LPUART_Register_Masks */


/* LPUART - Peripheral instance base addresses */
/** Peripheral LPUART0 base address */
#define LPUART0_BASE                             (0x2809A000u)
/** Peripheral LPUART0 base pointer */
#define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
/** Peripheral LPUART1 base address */
#define LPUART1_BASE                             (0x2809B000u)
/** Peripheral LPUART1 base pointer */
#define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
/** Peripheral LPUART2 base address */
#define LPUART2_BASE                             (0x2810B000u)
/** Peripheral LPUART2 base pointer */
#define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
/** Peripheral LPUART3 base address */
#define LPUART3_BASE                             (0x2810C000u)
/** Peripheral LPUART3 base pointer */
#define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
/** Peripheral LPUART4 base address */
#define LPUART4_BASE                             (0x29390000u)
/** Peripheral LPUART4 base pointer */
#define LPUART4                                  ((LPUART_Type *)LPUART4_BASE)
/** Peripheral LPUART5 base address */
#define LPUART5_BASE                             (0x293A0000u)
/** Peripheral LPUART5 base pointer */
#define LPUART5                                  ((LPUART_Type *)LPUART5_BASE)
/** Peripheral LPUART6 base address */
#define LPUART6_BASE                             (0x29860000u)
/** Peripheral LPUART6 base pointer */
#define LPUART6                                  ((LPUART_Type *)LPUART6_BASE)
/** Peripheral LPUART7 base address */
#define LPUART7_BASE                             (0x29870000u)
/** Peripheral LPUART7 base pointer */
#define LPUART7                                  ((LPUART_Type *)LPUART7_BASE)
/** Array initializer of LPUART peripheral base addresses */
#define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE }
/** Array initializer of LPUART peripheral base pointers */
#define LPUART_BASE_PTRS                         { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7 }
/** Interrupt vectors for the LPUART peripheral type */
#define LPUART_RX_TX_IRQS                        { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }

/*!
 * @}
 */ /* end of group LPUART_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MCM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
 * @{
 */

/** MCM - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[12];
  __IO uint32_t CPCR;                              /**< Core Platform Control, offset: 0xC */
       uint8_t RESERVED_1[36];
  __I  uint32_t CPCR2;                             /**< Core Platform Control 2, offset: 0x34 */
       uint8_t RESERVED_2[968];
  __IO uint32_t LMDR0;                             /**< Local Memory Descriptor 0, offset: 0x400 */
  __IO uint32_t LMDR1;                             /**< Local Memory Descriptor 1, offset: 0x404 */
  __IO uint32_t LMDR2;                             /**< Local Memory Descriptor 2, offset: 0x408 */
  __IO uint32_t LMDR3;                             /**< Local Memory Descriptor 3, offset: 0x40C */
} MCM_Type;

/* ----------------------------------------------------------------------------
   -- MCM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MCM_Register_Masks MCM Register Masks
 * @{
 */

/*! @name CPCR - Core Platform Control */
/*! @{ */

#define MCM_CPCR_CBRR_MASK                       (0x200U)
#define MCM_CPCR_CBRR_SHIFT                      (9U)
/*! CBRR - Crossbar Round-robin Arbitration Enable
 *  0b0..Fixed-priority arbitration
 *  0b1..Round-robin arbitration
 */
#define MCM_CPCR_CBRR(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_CBRR_SHIFT)) & MCM_CPCR_CBRR_MASK)
/*! @} */

/*! @name CPCR2 - Core Platform Control 2 */
/*! @{ */

#define MCM_CPCR2_CBCS_MASK                      (0xF0U)
#define MCM_CPCR2_CBCS_SHIFT                     (4U)
/*! CBCS - Code Bus Cache Size
 *  0b0000..0 KB
 *  0b0001..1 KB
 *  0b0010..2 KB
 *  0b0011..4 KB
 *  0b0100..8 KB
 *  0b0101..16 KB
 *  0b0110..32 KB
 */
#define MCM_CPCR2_CBCS(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_CBCS_SHIFT)) & MCM_CPCR2_CBCS_MASK)

#define MCM_CPCR2_SBCS_MASK                      (0xF000U)
#define MCM_CPCR2_SBCS_SHIFT                     (12U)
/*! SBCS - System Bus Cache Size
 *  0b0000..0 KB
 *  0b0001..1 KB
 *  0b0010..2 KB
 *  0b0011..4 KB
 *  0b0100..8 KB
 *  0b0101..16 KB
 *  0b0110..32 KB
 */
#define MCM_CPCR2_SBCS(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_SBCS_SHIFT)) & MCM_CPCR2_SBCS_MASK)
/*! @} */

/*! @name LMDR0 - Local Memory Descriptor 0 */
/*! @{ */

#define MCM_LMDR0_MT_MASK                        (0xE000U)
#define MCM_LMDR0_MT_SHIFT                       (13U)
/*! MT - Memory Type
 *  0b000..SRAM_L
 *  0b001..SRAM_U
 *  0b010..PC Cache
 *  0b011..PS Cache
 */
#define MCM_LMDR0_MT(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_MT_SHIFT)) & MCM_LMDR0_MT_MASK)

#define MCM_LMDR0_RO_MASK                        (0x10000U)
#define MCM_LMDR0_RO_SHIFT                       (16U)
/*! RO - Read-Only
 *  0b0..Writes to the corresponding LMDRn[7:0] are allowed.
 *  0b1..Writes to the corresponding LMDRn[7:0] are ignored.
 */
#define MCM_LMDR0_RO(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_RO_SHIFT)) & MCM_LMDR0_RO_MASK)

#define MCM_LMDR0_DPW_MASK                       (0xE0000U)
#define MCM_LMDR0_DPW_SHIFT                      (17U)
/*! DPW - LMEM Data Path Width
 *  0b000-0b001..Reserved
 *  0b010..LMEMn 32-bit wide
 *  0b011..LMEMn 64-bit wide
 *  0b100-0b111..Reserved
 */
#define MCM_LMDR0_DPW(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_DPW_SHIFT)) & MCM_LMDR0_DPW_MASK)

#define MCM_LMDR0_LMSZ_MASK                      (0xF000000U)
#define MCM_LMDR0_LMSZ_SHIFT                     (24U)
/*! LMSZ - LMEM Size
 *  0b0000..no LMEMn (0 KB)
 *  0b0001..1 KB LMEMn
 *  0b0010..2 KB LMEMn
 *  0b0011..4 KB LMEMn
 *  0b0100..8 KB LMEMn
 *  0b0101..16 KB LMEMn
 *  0b0110..32 KB LMEMn
 *  0b0111..64 KB LMEMn
 *  0b1000..128 KB LMEMn
 *  0b1001..256 KB LMEMn
 *  0b1010..512 KB LMEMn
 *  0b1011..1024 KB LMEMn
 *  0b1100..2048 KB LMEMn
 *  0b1101..4096 KB LMEMn
 *  0b1110..8192 KB LMEMn
 *  0b1111..16384 KB LMEMn
 */
#define MCM_LMDR0_LMSZ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_LMSZ_SHIFT)) & MCM_LMDR0_LMSZ_MASK)

#define MCM_LMDR0_LMSZH_MASK                     (0x10000000U)
#define MCM_LMDR0_LMSZH_SHIFT                    (28U)
/*! LMSZH - LMEM Size Hole
 *  0b0..LMEMn is a power-of-2 capacity.
 *  0b1..LMEMn is a capacity of 0.75 * LMSZ.
 */
#define MCM_LMDR0_LMSZH(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_LMSZH_SHIFT)) & MCM_LMDR0_LMSZH_MASK)

#define MCM_LMDR0_V_MASK                         (0x80000000U)
#define MCM_LMDR0_V_SHIFT                        (31U)
/*! V - Valid
 *  0b0..LMEMn is not present.
 *  0b1..LMEMn is present.
 */
#define MCM_LMDR0_V(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_V_SHIFT)) & MCM_LMDR0_V_MASK)
/*! @} */

/*! @name LMDR1 - Local Memory Descriptor 1 */
/*! @{ */

#define MCM_LMDR1_MT_MASK                        (0xE000U)
#define MCM_LMDR1_MT_SHIFT                       (13U)
/*! MT - Memory Type
 *  0b000..SRAM_L
 *  0b001..SRAM_U
 *  0b010..PC Cache
 *  0b011..PS Cache
 */
#define MCM_LMDR1_MT(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_MT_SHIFT)) & MCM_LMDR1_MT_MASK)

#define MCM_LMDR1_RO_MASK                        (0x10000U)
#define MCM_LMDR1_RO_SHIFT                       (16U)
/*! RO - Read-Only
 *  0b0..Writes to the corresponding LMDRn[7:0] are allowed.
 *  0b1..Writes to the corresponding LMDRn[7:0] are ignored.
 */
#define MCM_LMDR1_RO(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_RO_SHIFT)) & MCM_LMDR1_RO_MASK)

#define MCM_LMDR1_DPW_MASK                       (0xE0000U)
#define MCM_LMDR1_DPW_SHIFT                      (17U)
/*! DPW - LMEM Data Path Width
 *  0b000-0b001..Reserved
 *  0b010..LMEMn 32-bit wide
 *  0b011..LMEMn 64-bit wide
 *  0b100-0b111..Reserved
 */
#define MCM_LMDR1_DPW(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_DPW_SHIFT)) & MCM_LMDR1_DPW_MASK)

#define MCM_LMDR1_LMSZ_MASK                      (0xF000000U)
#define MCM_LMDR1_LMSZ_SHIFT                     (24U)
/*! LMSZ - LMEM Size
 *  0b0000..no LMEMn (0 KB)
 *  0b0001..1 KB LMEMn
 *  0b0010..2 KB LMEMn
 *  0b0011..4 KB LMEMn
 *  0b0100..8 KB LMEMn
 *  0b0101..16 KB LMEMn
 *  0b0110..32 KB LMEMn
 *  0b0111..64 KB LMEMn
 *  0b1000..128 KB LMEMn
 *  0b1001..256 KB LMEMn
 *  0b1010..512 KB LMEMn
 *  0b1011..1024 KB LMEMn
 *  0b1100..2048 KB LMEMn
 *  0b1101..4096 KB LMEMn
 *  0b1110..8192 KB LMEMn
 *  0b1111..16384 KB LMEMn
 */
#define MCM_LMDR1_LMSZ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_LMSZ_SHIFT)) & MCM_LMDR1_LMSZ_MASK)

#define MCM_LMDR1_LMSZH_MASK                     (0x10000000U)
#define MCM_LMDR1_LMSZH_SHIFT                    (28U)
/*! LMSZH - LMEM Size Hole
 *  0b0..LMEMn is a power-of-2 capacity.
 *  0b1..LMEMn is a capacity of 0.75 * LMSZ.
 */
#define MCM_LMDR1_LMSZH(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_LMSZH_SHIFT)) & MCM_LMDR1_LMSZH_MASK)

#define MCM_LMDR1_V_MASK                         (0x80000000U)
#define MCM_LMDR1_V_SHIFT                        (31U)
/*! V - Valid
 *  0b0..LMEMn is not present.
 *  0b1..LMEMn is present.
 */
#define MCM_LMDR1_V(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_V_SHIFT)) & MCM_LMDR1_V_MASK)
/*! @} */

/*! @name LMDR2 - Local Memory Descriptor 2 */
/*! @{ */

#define MCM_LMDR2_MT_MASK                        (0xE000U)
#define MCM_LMDR2_MT_SHIFT                       (13U)
/*! MT - Memory Type
 *  0b000..SRAM_L
 *  0b001..SRAM_U
 *  0b010..PC Cache
 *  0b011..PS Cache
 */
#define MCM_LMDR2_MT(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_MT_SHIFT)) & MCM_LMDR2_MT_MASK)

#define MCM_LMDR2_RO_MASK                        (0x10000U)
#define MCM_LMDR2_RO_SHIFT                       (16U)
/*! RO - Read-Only
 *  0b0..Writes to the corresponding LMDRn[7:0] are allowed.
 *  0b1..Writes to the corresponding LMDRn[7:0] are ignored.
 */
#define MCM_LMDR2_RO(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_RO_SHIFT)) & MCM_LMDR2_RO_MASK)

#define MCM_LMDR2_DPW_MASK                       (0xE0000U)
#define MCM_LMDR2_DPW_SHIFT                      (17U)
/*! DPW - LMEM Data Path Width
 *  0b000-0b001..Reserved
 *  0b010..LMEMn 32-bit wide
 *  0b011..LMEMn 64-bit wide
 *  0b100-0b111..Reserved
 */
#define MCM_LMDR2_DPW(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_DPW_SHIFT)) & MCM_LMDR2_DPW_MASK)

#define MCM_LMDR2_WY_MASK                        (0xF00000U)
#define MCM_LMDR2_WY_SHIFT                       (20U)
/*! WY - Level 1 Cache Ways
 *  0b0000..No Cache
 *  0b0010..2-Way Set Associative
 *  0b0100..4-Way Set Associative
 *  0b1000..8-Way Set Associative
 */
#define MCM_LMDR2_WY(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_WY_SHIFT)) & MCM_LMDR2_WY_MASK)

#define MCM_LMDR2_LMSZ_MASK                      (0xF000000U)
#define MCM_LMDR2_LMSZ_SHIFT                     (24U)
/*! LMSZ - LMEM Size
 *  0b0000..no LMEMn (0 KB)
 *  0b0001..1 KB LMEMn
 *  0b0010..2 KB LMEMn
 *  0b0011..4 KB LMEMn
 *  0b0100..8 KB LMEMn
 *  0b0101..16 KB LMEMn
 *  0b0110..32 KB LMEMn
 *  0b0111..64 KB LMEMn
 *  0b1000..128 KB LMEMn
 *  0b1001..256 KB LMEMn
 *  0b1010..512 KB LMEMn
 *  0b1011..1024 KB LMEMn
 *  0b1100..2048 KB LMEMn
 *  0b1101..4096 KB LMEMn
 *  0b1110..8192 KB LMEMn
 *  0b1111..16384 KB LMEMn
 */
#define MCM_LMDR2_LMSZ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_LMSZ_SHIFT)) & MCM_LMDR2_LMSZ_MASK)

#define MCM_LMDR2_LMSZH_MASK                     (0x10000000U)
#define MCM_LMDR2_LMSZH_SHIFT                    (28U)
/*! LMSZH - LMEM Size Hole
 *  0b0..LMEMn is a power-of-2 capacity.
 *  0b1..LMEMn is a capacity of 0.75 * LMSZ.
 */
#define MCM_LMDR2_LMSZH(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_LMSZH_SHIFT)) & MCM_LMDR2_LMSZH_MASK)

#define MCM_LMDR2_V_MASK                         (0x80000000U)
#define MCM_LMDR2_V_SHIFT                        (31U)
/*! V - Valid
 *  0b0..LMEMn is not present.
 *  0b1..LMEMn is present.
 */
#define MCM_LMDR2_V(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_V_SHIFT)) & MCM_LMDR2_V_MASK)
/*! @} */

/*! @name LMDR3 - Local Memory Descriptor 3 */
/*! @{ */

#define MCM_LMDR3_MT_MASK                        (0xE000U)
#define MCM_LMDR3_MT_SHIFT                       (13U)
/*! MT - Memory Type
 *  0b000..SRAM_L
 *  0b001..SRAM_U
 *  0b010..PC Cache
 *  0b011..PS Cache
 */
#define MCM_LMDR3_MT(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR3_MT_SHIFT)) & MCM_LMDR3_MT_MASK)

#define MCM_LMDR3_RO_MASK                        (0x10000U)
#define MCM_LMDR3_RO_SHIFT                       (16U)
/*! RO - Read-Only
 *  0b0..Writes to the corresponding LMDRn[7:0] are allowed.
 *  0b1..Writes to the corresponding LMDRn[7:0] are ignored.
 */
#define MCM_LMDR3_RO(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR3_RO_SHIFT)) & MCM_LMDR3_RO_MASK)

#define MCM_LMDR3_DPW_MASK                       (0xE0000U)
#define MCM_LMDR3_DPW_SHIFT                      (17U)
/*! DPW - LMEM Data Path Width
 *  0b000-0b001..Reserved
 *  0b010..LMEMn 32-bit wide
 *  0b011..LMEMn 64-bit wide
 *  0b100-0b111..Reserved
 */
#define MCM_LMDR3_DPW(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_LMDR3_DPW_SHIFT)) & MCM_LMDR3_DPW_MASK)

#define MCM_LMDR3_WY_MASK                        (0xF00000U)
#define MCM_LMDR3_WY_SHIFT                       (20U)
/*! WY - Level 1 Cache Ways
 *  0b0000..No Cache
 *  0b0010..2-Way Set Associative
 *  0b0100..4-Way Set Associative
 *  0b1000..8-Way Set Associative
 */
#define MCM_LMDR3_WY(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR3_WY_SHIFT)) & MCM_LMDR3_WY_MASK)

#define MCM_LMDR3_LMSZ_MASK                      (0xF000000U)
#define MCM_LMDR3_LMSZ_SHIFT                     (24U)
/*! LMSZ - LMEM Size
 *  0b0000..no LMEMn (0 KB)
 *  0b0001..1 KB LMEMn
 *  0b0010..2 KB LMEMn
 *  0b0011..4 KB LMEMn
 *  0b0100..8 KB LMEMn
 *  0b0101..16 KB LMEMn
 *  0b0110..32 KB LMEMn
 *  0b0111..64 KB LMEMn
 *  0b1000..128 KB LMEMn
 *  0b1001..256 KB LMEMn
 *  0b1010..512 KB LMEMn
 *  0b1011..1024 KB LMEMn
 *  0b1100..2048 KB LMEMn
 *  0b1101..4096 KB LMEMn
 *  0b1110..8192 KB LMEMn
 *  0b1111..16384 KB LMEMn
 */
#define MCM_LMDR3_LMSZ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_LMDR3_LMSZ_SHIFT)) & MCM_LMDR3_LMSZ_MASK)

#define MCM_LMDR3_LMSZH_MASK                     (0x10000000U)
#define MCM_LMDR3_LMSZH_SHIFT                    (28U)
/*! LMSZH - LMEM Size Hole
 *  0b0..LMEMn is a power-of-2 capacity.
 *  0b1..LMEMn is a capacity of 0.75 * LMSZ.
 */
#define MCM_LMDR3_LMSZH(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMDR3_LMSZH_SHIFT)) & MCM_LMDR3_LMSZH_MASK)

#define MCM_LMDR3_V_MASK                         (0x80000000U)
#define MCM_LMDR3_V_SHIFT                        (31U)
/*! V - Valid
 *  0b0..LMEMn is not present.
 *  0b1..LMEMn is present.
 */
#define MCM_LMDR3_V(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_LMDR3_V_SHIFT)) & MCM_LMDR3_V_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MCM_Register_Masks */


/* MCM - Peripheral instance base addresses */
/** Peripheral MCM base address */
#define MCM_BASE                                 (0xE0080000u)
/** Peripheral MCM base pointer */
#define MCM                                      ((MCM_Type *)MCM_BASE)
/** Array initializer of MCM peripheral base addresses */
#define MCM_BASE_ADDRS                           { MCM_BASE }
/** Array initializer of MCM peripheral base pointers */
#define MCM_BASE_PTRS                            { MCM }

/*!
 * @}
 */ /* end of group MCM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MIPI_CSI2RX Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_CSI2RX_Peripheral_Access_Layer MIPI_CSI2RX Peripheral Access Layer
 * @{
 */

/** MIPI_CSI2RX - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[256];
  __IO uint32_t CSI2RX_CFG_NUM_LANES;              /**< Lane Configuration Register, offset: 0x100 */
  __IO uint32_t CSI2RX_CFG_DISABLE_DATA_LANES;     /**< Disable Data Lane Register, offset: 0x104 */
  __I  uint32_t CSI2RX_BIT_ERR;                    /**< ECC and CRC Error Status Register, offset: 0x108 */
  __I  uint32_t CSI2RX_IRQ_STATUS;                 /**< IRQ Status Register, offset: 0x10C */
  __IO uint32_t CSI2RX_IRQ_MASK;                   /**< IRQ Mask Setting Register, offset: 0x110 */
  __I  uint32_t CSI2RX_ULPS_STATUS;                /**< Ultra Low Power State (ULPS) Status Register, offset: 0x114 */
  __I  uint32_t CSI2RX_PPI_ERRSOT_HS;              /**< ERRSot HS Status Register, offset: 0x118 */
  __I  uint32_t CSI2RX_PPI_ERRSOTSYNC_HS;          /**< ErrSotSync HS Status Register, offset: 0x11C */
  __I  uint32_t CSI2RX_PPI_ERRESC;                 /**< ErrEsc Status Register, offset: 0x120 */
  __I  uint32_t CSI2RX_PPI_ERRSYNCESC;             /**< ErrSyncEsc Status Register, offset: 0x124 */
  __I  uint32_t CSI2RX_PPI_ERRCONTROL;             /**< ErrControl Status Register, offset: 0x128 */
  __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_0;      /**< Disable Payload 0 Register, offset: 0x12C */
  __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_1;      /**< Disable Payload 1 Register, offset: 0x130 */
} MIPI_CSI2RX_Type;

/* ----------------------------------------------------------------------------
   -- MIPI_CSI2RX Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_CSI2RX_Register_Masks MIPI_CSI2RX Register Masks
 * @{
 */

/*! @name CSI2RX_CFG_NUM_LANES - Lane Configuration Register */
/*! @{ */

#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK (0x3U)
#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT (0U)
/*! CFG_NUM_LANES - Sets the number of active lanes that are to be used for receiving data. */
#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK)
/*! @} */

/*! @name CSI2RX_CFG_DISABLE_DATA_LANES - Disable Data Lane Register */
/*! @{ */

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK (0xFU)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT (0U)
/*! CFG_DISABLE_DATA_LANES - Forces DPHY Enable_n signals to 1'b0 when register is set to 1.
 *  0b0000..Data Lane 0
 *  0b0001..Data Lane 1.
 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK)
/*! @} */

/*! @name CSI2RX_BIT_ERR - ECC and CRC Error Status Register */
/*! @{ */

#define MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_MASK  (0x3FFU)
#define MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_SHIFT (0U)
/*! BIT_ERR - Captures the first Error event when either a one or two bit error occurs, with only
 *    the one bit error providing position information.
 */
#define MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_SHIFT)) & MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_MASK)
/*! @} */

/*! @name CSI2RX_IRQ_STATUS - IRQ Status Register */
/*! @{ */

#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK (0x1FFU)
#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT (0U)
/*! IRQ_STATUS - Status of IRQ. Rx Controller irq_out output is the result of anding these bits with
 *    IRQ_MASK and then ORing the individual resultant bits together. The status bits get cleared
 *    when read.
 */
#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK)
/*! @} */

/*! @name CSI2RX_IRQ_MASK - IRQ Mask Setting Register */
/*! @{ */

#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_MASK (0x1FFU)
#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT (0U)
/*! IRQ_MASK - This field shows the IRQ Mask setting. */
#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_MASK)
/*! @} */

/*! @name CSI2RX_ULPS_STATUS - Ultra Low Power State (ULPS) Status Register */
/*! @{ */

#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_ULPS_STATUS_MASK (0x3FFU)
#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_ULPS_STATUS_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_ULPS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_ULPS_STATUS_ULPS_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_ULPS_STATUS_ULPS_STATUS_MASK)
/*! @} */

/*! @name CSI2RX_PPI_ERRSOT_HS - ERRSot HS Status Register */
/*! @{ */

#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_PPI_ERRSOT_HS_MASK (0xFU)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_PPI_ERRSOT_HS_SHIFT (0U)
/*! PPI_ERRSOT_HS - This field indicates PPI ErrSotHS captured status from DPHY. */
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_PPI_ERRSOT_HS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_PPI_ERRSOT_HS_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_PPI_ERRSOT_HS_MASK)
/*! @} */

/*! @name CSI2RX_PPI_ERRSOTSYNC_HS - ErrSotSync HS Status Register */
/*! @{ */

#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_PPI_ERRSOTSYNC_HS_MASK (0xFU)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_PPI_ERRSOTSYNC_HS_SHIFT (0U)
/*! PPI_ERRSOTSYNC_HS - This field indicates PPI ErrSotSync_HS captured status from DPHY. */
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_PPI_ERRSOTSYNC_HS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_PPI_ERRSOTSYNC_HS_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_PPI_ERRSOTSYNC_HS_MASK)
/*! @} */

/*! @name CSI2RX_PPI_ERRESC - ErrEsc Status Register */
/*! @{ */

#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_PPI_ERRESC_MASK (0xFU)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_PPI_ERRESC_SHIFT (0U)
/*! PPI_ERRESC - This field indicates PPI ErrEsc captured status from DPHY. */
#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_PPI_ERRESC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRESC_PPI_ERRESC_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRESC_PPI_ERRESC_MASK)
/*! @} */

/*! @name CSI2RX_PPI_ERRSYNCESC - ErrSyncEsc Status Register */
/*! @{ */

#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_PPI_ERRSYNCESC_MASK (0xFU)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_PPI_ERRSYNCESC_SHIFT (0U)
/*! PPI_ERRSYNCESC - CSI2 RX DPHY PPI ErrSyncEsc captured status from the DPHY. */
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_PPI_ERRSYNCESC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_PPI_ERRSYNCESC_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_PPI_ERRSYNCESC_MASK)
/*! @} */

/*! @name CSI2RX_PPI_ERRCONTROL - ErrControl Status Register */
/*! @{ */

#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_PPI_ERRCONTROL_MASK (0xFU)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_PPI_ERRCONTROL_SHIFT (0U)
/*! PPI_ERRCONTROL - This field indicates PPI ErrControl captured status from DPHY. */
#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_PPI_ERRCONTROL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_PPI_ERRCONTROL_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_PPI_ERRCONTROL_MASK)
/*! @} */

/*! @name CSI2RX_CFG_DISABLE_PAYLOAD_0 - Disable Payload 0 Register */
/*! @{ */

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK (0x1U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT (0U)
/*! DIS_PAYLOAD_NULL - Null */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK (0x2U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT (1U)
/*! DIS_PAYLOAD_BLANK - Blank */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK (0x4U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT (2U)
/*! DIS_PAYLOAD_EMBEDDED - Embedded */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK (0x400U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT (10U)
/*! DIS_PAYLOAD_YUV420 - Legacy YUV 420 8 bit */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK (0x4000U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT (14U)
/*! DIS_PAYLOAD_YUV422_8BIT - YUV422 8 bit */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT_MASK (0x8000U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT_SHIFT (15U)
/*! DIS_PAYLOAD_YUV422_10BIT - YUV422 10 bit */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK (0x10000U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT (16U)
/*! DIS_PAYLOAD_RGB444 - RGB444 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK (0x20000U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT (17U)
/*! DIS_PAYLOAD_RGB555 - RGB555 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK (0x40000U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT (18U)
/*! DIS_PAYLOAD_RGB565 - RGB565 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK (0x80000U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT (19U)
/*! DIS_PAYLOAD_RGB666 - RGB666 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK (0x100000U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT (20U)
/*! DIS_PAYLOAD_RGB888 - RGB888 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6_MASK (0x1000000U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6_SHIFT (24U)
/*! DIS_PAYLOAD_RAW6 - RAW6 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8_MASK (0x4000000U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8_SHIFT (26U)
/*! DIS_PAYLOAD_RAW8 - RAW8 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10_MASK (0x8000000U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10_SHIFT (27U)
/*! DIS_PAYLOAD_RAW10 - RAW10 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12_MASK (0x10000000U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12_SHIFT (28U)
/*! DIS_PAYLOAD_RAW12 - RAW12 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12_MASK)
/*! @} */

/*! @name CSI2RX_CFG_DISABLE_PAYLOAD_1 - Disable Payload 1 Register */
/*! @{ */

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK (0x1U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT (0U)
/*! DIS_PAYLOAD_UDEF_30 - User defined type 0x30 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK (0x2U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT (1U)
/*! DIS_PAYLOAD_UDEF_31 - User defined type 0x31 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK (0x4U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT (2U)
/*! DIS_PAYLOAD_UDEF_32 - User defined type 0x32 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK (0x8U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT (3U)
/*! DIS_PAYLOAD_UDEF_33 - User defined type 0x33 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK (0x10U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT (4U)
/*! DIS_PAYLOAD_UDEF_34 - User defined type 0x34 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK (0x20U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT (5U)
/*! DIS_PAYLOAD_UDEF_35 - User defined type 0x35 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK (0x40U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT (6U)
/*! DIS_PAYLOAD_UDEF_36 - User defined type 0x36 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK (0x80U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT (7U)
/*! DIS_PAYLOAD_UDEF_37 - User defined type 0x37 */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK)

#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK (0x10000U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT (16U)
/*! DIS_PAYLOAD_UNSUPPORTED - Unsupported Data Types */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MIPI_CSI2RX_Register_Masks */


/* MIPI_CSI2RX - Peripheral instance base addresses */
/** Peripheral MIPI_CSI2RX base address */
#define MIPI_CSI2RX_BASE                         (0x2DAD0000u)
/** Peripheral MIPI_CSI2RX base pointer */
#define MIPI_CSI2RX                              ((MIPI_CSI2RX_Type *)MIPI_CSI2RX_BASE)
/** Array initializer of MIPI_CSI2RX peripheral base addresses */
#define MIPI_CSI2RX_BASE_ADDRS                   { MIPI_CSI2RX_BASE }
/** Array initializer of MIPI_CSI2RX peripheral base pointers */
#define MIPI_CSI2RX_BASE_PTRS                    { MIPI_CSI2RX }

/*!
 * @}
 */ /* end of group MIPI_CSI2RX_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MIPI_CSI_CSR Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_CSI_CSR_Peripheral_Access_Layer MIPI_CSI_CSR Peripheral Access Layer
 * @{
 */

/** MIPI_CSI_CSR - Register Layout Typedef */
typedef struct {
  __IO uint32_t PLM_CTRL;                          /**< Pixel Link Master (PLM) Control, offset: 0x0 */
  __IO uint32_t PHY_CTRL;                          /**< PHY_CTRL are outputs from CSR to the PHY or Controller., offset: 0x4 */
  __I  uint32_t PHY_STATUS;                        /**< offset: 0x8 */
       uint8_t RESERVED_0[36];
  __IO uint32_t VC_INTERLACED;                     /**< offset: 0x30 */
       uint8_t RESERVED_1[4];
  __IO uint32_t DATA_TYPE_DISABLE_BF;              /**< offset: 0x38 */
       uint8_t RESERVED_2[4];
  __IO uint32_t YUV420_FIRST_LINE_DATA_TYPE;       /**< offset: 0x40 */
  __IO uint32_t CONTROLLER_CLOCK_RESET_CONTROL;    /**< offset: 0x44 */
  __IO uint32_t STREAM_FENCING_CONTROL;            /**< Stream Fencing Control (RW - to Pixel Reformatter), offset: 0x48 */
  __I  uint32_t STREAM_FENCING_STATUS;             /**< Stream Fencing Status (RO - from Pixel Reformatter), offset: 0x4C */
} MIPI_CSI_CSR_Type;

/* ----------------------------------------------------------------------------
   -- MIPI_CSI_CSR Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_CSI_CSR_Register_Masks MIPI_CSI_CSR Register Masks
 * @{
 */

/*! @name PLM_CTRL - Pixel Link Master (PLM) Control */
/*! @{ */

#define MIPI_CSI_CSR_PLM_CTRL_ENABLE_MASK        (0x1U)
#define MIPI_CSI_CSR_PLM_CTRL_ENABLE_SHIFT       (0U)
/*! ENABLE - Enable - for pixel link */
#define MIPI_CSI_CSR_PLM_CTRL_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_ENABLE_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_ENABLE_MASK)

#define MIPI_CSI_CSR_PLM_CTRL_ADDR_MASK          (0x6U)
#define MIPI_CSI_CSR_PLM_CTRL_ADDR_SHIFT         (1U)
/*! ADDR - For selecting the destination module that receives the data. Can be defaulted to 0. */
#define MIPI_CSI_CSR_PLM_CTRL_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_ADDR_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_ADDR_MASK)

#define MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE_MASK (0x200U)
#define MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE_SHIFT (9U)
/*! VSYNC_OVERIDE - Used to force the Pixel Link Master VSYNC input to be active */
#define MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE_MASK)

#define MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE_MASK (0x400U)
#define MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE_SHIFT (10U)
/*! HSYNC_OVERIDE - Used to force the Pixel Link Master HSYNC input to be active */
#define MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE_MASK)

#define MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_MASK (0x800U)
#define MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_SHIFT (11U)
/*! VALID_OVERRIDE - Used to drive valid on the Pixel Link */
#define MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_MASK)

#define MIPI_CSI_CSR_PLM_CTRL_POLARITY_MASK      (0x1000U)
#define MIPI_CSI_CSR_PLM_CTRL_POLARITY_SHIFT     (12U)
/*! POLARITY - POLARITY
 *  0b1..HSYNC and VSYNC signals should be active high
 *  0b0..HSYNC and VSYNC signals should be active low. Also a reset value (active low).
 */
#define MIPI_CSI_CSR_PLM_CTRL_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_POLARITY_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_POLARITY_MASK)
/*! @} */

/*! @name PHY_CTRL - PHY_CTRL are outputs from CSR to the PHY or Controller. */
/*! @{ */

#define MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_MASK     (0x1U)
#define MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_SHIFT    (0U)
/*! RX_ENABLE - Receive Enable */
#define MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_MASK)

#define MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_MASK    (0x2U)
#define MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_SHIFT   (1U)
/*! AUTO_PD_EN - Powers down inactive lanes reported by CFG_NUM_LANES input bus.
 *  0b0..Inactive lanes are powered up.
 *  0b1..Inactive lanes are powered down.
 */
#define MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_MASK)

#define MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_MASK     (0x4U)
#define MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_SHIFT    (2U)
/*! DDRCLK_EN - DDR Clock Enable. When set, enables received DDR clock on CLK_DRXHS. */
#define MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_MASK)

#define MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE_MASK (0x8U)
#define MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE_SHIFT (3U)
/*! CONT_CLK_MODE - Enables the slave clock lane feature to maintain HS reception state during
 *    continuous clock mode operation, despite line glitches.
 *  0b0..Feature disabled.
 *  0b1..Feature enabled.
 */
#define MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE_MASK)

#define MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE_MASK (0x3F0U)
#define MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE_SHIFT (4U)
/*! S_PRG_RXHS_SETTLE - Bits used to program T_HS_SETTLE. HS-RX waits for Time-out T_HS_SETTLE in order to neglect transition effects. */
#define MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE_MASK)

#define MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_MASK     (0x200000U)
#define MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_SHIFT    (21U)
/*! RTERM_SEL - Selects voltage levels that enable HS termination.
 *  0b0..LPCD levels enable HS termination (VIL-CD).
 *  0b1..LPRX levels enable HS termination (VIL-LP).
 */
#define MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_MASK)

#define MIPI_CSI_CSR_PHY_CTRL_PD_MASK            (0x400000U)
#define MIPI_CSI_CSR_PHY_CTRL_PD_SHIFT           (22U)
/*! PD - Power Down input for D-PHY. When high, all blocks are powered down. */
#define MIPI_CSI_CSR_PHY_CTRL_PD(x)              (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_PD_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_PD_MASK)
/*! @} */

/*! @name PHY_STATUS -  */
/*! @{ */

#define MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED_MASK (0x1U)
#define MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED_SHIFT (0U)
/*! LANES_STOPPED - LANES_STOPPED (csi_controller.ulps_active[4:0] = 5'b0) */
#define MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED_SHIFT)) & MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED_MASK)
/*! @} */

/*! @name VC_INTERLACED -  */
/*! @{ */

#define MIPI_CSI_CSR_VC_INTERLACED_VC0_MASK      (0x1U)
#define MIPI_CSI_CSR_VC_INTERLACED_VC0_SHIFT     (0U)
/*! VC0
 *  0b1..VC0 is interlaced
 *  0b0..Default
 */
#define MIPI_CSI_CSR_VC_INTERLACED_VC0(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_VC_INTERLACED_VC0_SHIFT)) & MIPI_CSI_CSR_VC_INTERLACED_VC0_MASK)

#define MIPI_CSI_CSR_VC_INTERLACED_VC1_MASK      (0x2U)
#define MIPI_CSI_CSR_VC_INTERLACED_VC1_SHIFT     (1U)
/*! VC1
 *  0b1..VC1 is interlaced
 *  0b0..Default
 */
#define MIPI_CSI_CSR_VC_INTERLACED_VC1(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_VC_INTERLACED_VC1_SHIFT)) & MIPI_CSI_CSR_VC_INTERLACED_VC1_MASK)

#define MIPI_CSI_CSR_VC_INTERLACED_VC2_MASK      (0x4U)
#define MIPI_CSI_CSR_VC_INTERLACED_VC2_SHIFT     (2U)
/*! VC2
 *  0b1..VC2 is interlaced
 *  0b0..Default
 */
#define MIPI_CSI_CSR_VC_INTERLACED_VC2(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_VC_INTERLACED_VC2_SHIFT)) & MIPI_CSI_CSR_VC_INTERLACED_VC2_MASK)

#define MIPI_CSI_CSR_VC_INTERLACED_VC3_MASK      (0x8U)
#define MIPI_CSI_CSR_VC_INTERLACED_VC3_SHIFT     (3U)
/*! VC3
 *  0b1..VC3 is interlaced
 *  0b0..Default
 */
#define MIPI_CSI_CSR_VC_INTERLACED_VC3(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_VC_INTERLACED_VC3_SHIFT)) & MIPI_CSI_CSR_VC_INTERLACED_VC3_MASK)
/*! @} */

/*! @name DATA_TYPE_DISABLE_BF -  */
/*! @{ */

#define MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE_MASK (0xFFFFFFU)
#define MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE_SHIFT (0U)
/*! DATA_TYPE_DISABLE - Data Type Disable */
#define MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE_SHIFT)) & MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE_MASK)

#define MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_NO_RAW_SHIFTING_MASK (0x80000000U)
#define MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_NO_RAW_SHIFTING_SHIFT (31U)
/*! NO_RAW_SHIFTING - When set, prevents shifting of RAW8 to RAW14 pixel format inside pixel reformatting module.
 *  0b0..RAW8 is changed to RAW14 (default).
 *  0b1..Prevents shitfing of RAW8 to RAW14 format.
 */
#define MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_NO_RAW_SHIFTING(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_NO_RAW_SHIFTING_SHIFT)) & MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_NO_RAW_SHIFTING_MASK)
/*! @} */

/*! @name YUV420_FIRST_LINE_DATA_TYPE -  */
/*! @{ */

#define MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE_MASK (0x1U)
#define MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE_SHIFT (0U)
/*! YUV420_FIRST_LINE_DATA_TYPE - YUV420_FIRST_LINE_DATA_TYPE
 *  0b0..Odd (reset value)
 *  0b1..Even
 */
#define MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE_SHIFT)) & MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE_MASK)
/*! @} */

/*! @name CONTROLLER_CLOCK_RESET_CONTROL -  */
/*! @{ */

#define MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL_MASK (0x3U)
#define MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL_SHIFT (0U)
/*! CONTROLLER_CLOCK_RESET_CONTROL - CONTROLLER_CLOCK_RESET_CONTROL
 *  0b00..SW_RESETN (reset value is 0)
 *  0b01..CTL_CLK_OFF (connect to LPCG) (reset value is 1)
 */
#define MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL_SHIFT)) & MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL_MASK)
/*! @} */

/*! @name STREAM_FENCING_CONTROL - Stream Fencing Control (RW - to Pixel Reformatter) */
/*! @{ */

#define MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL_MASK (0xFU)
#define MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL_SHIFT (0U)
/*! STREAM_FENCING_CONTROL
 *  0b0001..Fence VC0
 *  0b0010..Fence VC1
 *  0b0100..Fence VC2
 *  0b1000..Fence VC3
 */
#define MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL_SHIFT)) & MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL_MASK)
/*! @} */

/*! @name STREAM_FENCING_STATUS - Stream Fencing Status (RO - from Pixel Reformatter) */
/*! @{ */

#define MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS_MASK (0xFU)
#define MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS_SHIFT (0U)
/*! STREAM_FENCING_STATUS
 *  0b0001..VC0 is fenced
 *  0b0010..VC1 is fenced
 *  0b0100..VC2 is fenced
 *  0b1000..VC3 is fenced
 */
#define MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS_SHIFT)) & MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MIPI_CSI_CSR_Register_Masks */


/* MIPI_CSI_CSR - Peripheral instance base addresses */
/** Peripheral MIPI_CSI_CSR base address */
#define MIPI_CSI_CSR_BASE                        (0x2DAF0000u)
/** Peripheral MIPI_CSI_CSR base pointer */
#define MIPI_CSI_CSR                             ((MIPI_CSI_CSR_Type *)MIPI_CSI_CSR_BASE)
/** Array initializer of MIPI_CSI_CSR peripheral base addresses */
#define MIPI_CSI_CSR_BASE_ADDRS                  { MIPI_CSI_CSR_BASE }
/** Array initializer of MIPI_CSI_CSR peripheral base pointers */
#define MIPI_CSI_CSR_BASE_PTRS                   { MIPI_CSI_CSR }

/*!
 * @}
 */ /* end of group MIPI_CSI_CSR_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MIPI_DSI_HOST Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_DSI_HOST_Peripheral_Access_Layer MIPI_DSI_HOST Peripheral Access Layer
 * @{
 */

/** MIPI_DSI_HOST - Register Layout Typedef */
typedef struct {
  __IO uint32_t CFG_NUM_LANES;                     /**< offset: 0x0 */
  __IO uint32_t CFG_NONCONTINUOUS_CLK;             /**< offset: 0x4 */
  __IO uint32_t CFG_T_PRE;                         /**< offset: 0x8 */
  __IO uint32_t CFG_T_POST;                        /**< offset: 0xC */
  __IO uint32_t CFG_TX_GAP;                        /**< offset: 0x10 */
  __IO uint32_t CFG_AUTOINSERT_EOTP;               /**< offset: 0x14 */
  __IO uint32_t CFG_EXTRA_CMDS_AFTER_EOTP;         /**< offset: 0x18 */
  __IO uint32_t CFG_HTX_TO_COUNT;                  /**< offset: 0x1C */
  __IO uint32_t CFG_LRX_H_TO_COUNT;                /**< offset: 0x20 */
  __IO uint32_t CFG_BTA_H_TO_COUNT;                /**< offset: 0x24 */
  __IO uint32_t CFG_TWAKEUP;                       /**< offset: 0x28 */
  __I  uint32_t CFG_STATUS_OUT;                    /**< offset: 0x2C */
  __I  uint32_t RX_ERROR_STATUS;                   /**< offset: 0x30 */
       uint8_t RESERVED_0[204];
  __IO uint32_t CFG_DBI_PIXEL_PAYLOAD_SIZE;        /**< offset: 0x100 */
  __IO uint32_t CFG_DBI_PIXEL_FIFO_SEND_LEVEL;     /**< offset: 0x104 */
       uint8_t RESERVED_1[248];
  __IO uint32_t CFG_DPI_PIXEL_PAYLOAD_SIZE;        /**< offset: 0x200 */
  __IO uint32_t CFG_DPI_PIXEL_FIFO_SEND_LEVEL;     /**< offset: 0x204 */
  __IO uint32_t CFG_DPI_INTERFACE_COLOR_CODING;    /**< offset: 0x208 */
  __IO uint32_t CFG_DPI_PIXEL_FORMAT;              /**< offset: 0x20C */
  __IO uint32_t CFG_DPI_VSYNC_POLARITY;            /**< offset: 0x210 */
  __IO uint32_t CFG_DPI_HSYNC_POLARITY;            /**< offset: 0x214 */
  __IO uint32_t CFG_DPI_VIDEO_MODE;                /**< offset: 0x218 */
  __IO uint32_t CFG_DPI_HFP;                       /**< offset: 0x21C */
  __IO uint32_t CFG_DPI_HBP;                       /**< offset: 0x220 */
  __IO uint32_t CFG_DPI_HSA;                       /**< offset: 0x224 */
  __IO uint32_t CFG_DPI_ENABLE_MULT_PKTS;          /**< offset: 0x228 */
  __IO uint32_t CFG_DPI_VBP;                       /**< offset: 0x22C */
  __IO uint32_t CFG_DPI_VFP;                       /**< offset: 0x230 */
  __IO uint32_t CFG_DPI_BLLP_MODE;                 /**< offset: 0x234 */
  __IO uint32_t CFG_DPI_USE_NULL_PKT_BLLP;         /**< offset: 0x238 */
  __IO uint32_t CFG_DPI_VACTIVE;                   /**< offset: 0x23C */
  __IO uint32_t CFG_DPI_VC;                        /**< offset: 0x240 */
       uint8_t RESERVED_2[60];
  __IO uint32_t TX_PAYLOAD;                        /**< offset: 0x280 */
  __IO uint32_t PKT_CONTROL;                       /**< offset: 0x284 */
  __IO uint32_t SEND_PACKET;                       /**< offset: 0x288 */
  __I  uint32_t PKT_STATUS;                        /**< offset: 0x28C */
  __I  uint32_t PKT_FIFO_WR_LEVEL;                 /**< offset: 0x290 */
  __I  uint32_t PKT_FIFO_RD_LEVEL;                 /**< offset: 0x294 */
  __I  uint32_t PKT_RX_PAYLOAD;                    /**< offset: 0x298 */
  __I  uint32_t PKT_RX_PKT_HEADER;                 /**< offset: 0x29C */
  __I  uint32_t IRQ_STATUS;                        /**< offset: 0x2A0 */
  __I  uint32_t IRQ_STATUS2;                       /**< offset: 0x2A4 */
  __IO uint32_t IRQ_MASK;                          /**< offset: 0x2A8 */
  __IO uint32_t IRQ_MASK2;                         /**< offset: 0x2AC */
       uint8_t RESERVED_3[80];
  __IO uint32_t PD_DPHY;                           /**< offset: 0x300 */
  __IO uint32_t M_PRG_HS_PREPARE;                  /**< offset: 0x304 */
  __IO uint32_t MC_PRG_HS_PREPARE;                 /**< offset: 0x308 */
  __IO uint32_t M_PRG_HS_ZERO;                     /**< offset: 0x30C */
  __IO uint32_t MC_PRG_HS_ZERO;                    /**< offset: 0x310 */
  __IO uint32_t M_PRG_HS_TRAIL;                    /**< offset: 0x314 */
  __IO uint32_t MC_PRG_HS_TRAIL;                   /**< offset: 0x318 */
  __IO uint32_t MC_PRG_RXHS_SETTLE;                /**< offset: 0x31C */
  __IO uint32_t M_PRG_RXHS_SETTLE;                 /**< offset: 0x320 */
  __IO uint32_t PD_PLL;                            /**< offset: 0x324 */
  __IO uint32_t TST;                               /**< offset: 0x328 */
  __IO uint32_t CN;                                /**< offset: 0x32C */
  __IO uint32_t CM;                                /**< offset: 0x330 */
  __IO uint32_t CO;                                /**< offset: 0x334 */
  __I  uint32_t LOCK;                              /**< offset: 0x338 */
  __IO uint32_t LOCK_BYP;                          /**< offset: 0x33C */
  __IO uint32_t AUTO_PD_EN;                        /**< offset: 0x340 */
  __IO uint32_t RXLPRP;                            /**< offset: 0x344 */
  __IO uint32_t RXCDRP;                            /**< offset: 0x348 */
} MIPI_DSI_HOST_Type;

/* ----------------------------------------------------------------------------
   -- MIPI_DSI_HOST Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_DSI_HOST_Register_Masks MIPI_DSI_HOST Register Masks
 * @{
 */

/*! @name CFG_NUM_LANES -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK (0x3U)
#define MIPI_DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT (0U)
/*! NUM_LANES - Sets the number of active lanes that are to be used for transmitting data. */
#define MIPI_DSI_HOST_CFG_NUM_LANES_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT)) & MIPI_DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK)
/*! @} */

/*! @name CFG_NONCONTINUOUS_CLK -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK (0x1U)
#define MIPI_DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT (0U)
/*! CLK_MODE - Sets the Host Controller into non-continuous MIPI clock mode. */
#define MIPI_DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT)) & MIPI_DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK)
/*! @} */

/*! @name CFG_T_PRE -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK (0x7FU)
#define MIPI_DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT (0U)
#define MIPI_DSI_HOST_CFG_T_PRE_NUM_PERIODS(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT)) & MIPI_DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK)
/*! @} */

/*! @name CFG_T_POST -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK (0x7FU)
#define MIPI_DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT (0U)
#define MIPI_DSI_HOST_CFG_T_POST_NUM_PERIODS(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT)) & MIPI_DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK)
/*! @} */

/*! @name CFG_TX_GAP -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK (0x7FU)
#define MIPI_DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT (0U)
#define MIPI_DSI_HOST_CFG_TX_GAP_NUM_PERIODS(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT)) & MIPI_DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK)
/*! @} */

/*! @name CFG_AUTOINSERT_EOTP -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK (0x1U)
#define MIPI_DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT (0U)
#define MIPI_DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT)) & MIPI_DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK)
/*! @} */

/*! @name CFG_EXTRA_CMDS_AFTER_EOTP -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK (0xFFU)
#define MIPI_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT (0U)
/*! EXTRA_EOTP - Configures the DSI Host Controller to send extra End Of Transmission Packets after the end of a packet. */
#define MIPI_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT)) & MIPI_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK)
/*! @} */

/*! @name CFG_HTX_TO_COUNT -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT (0U)
#define MIPI_DSI_HOST_CFG_HTX_TO_COUNT_COUNT(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT)) & MIPI_DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK)
/*! @} */

/*! @name CFG_LRX_H_TO_COUNT -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT (0U)
#define MIPI_DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT)) & MIPI_DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK)
/*! @} */

/*! @name CFG_BTA_H_TO_COUNT -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT (0U)
/*! COUNT - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in clk_byte clock periods
 *    that once reached will initiate a timeout error.
 */
#define MIPI_DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT)) & MIPI_DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK)
/*! @} */

/*! @name CFG_TWAKEUP -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK (0x7FFFFU)
#define MIPI_DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT (0U)
/*! NUM_PERIODS - DPHY Twakeup timing parameter. */
#define MIPI_DSI_HOST_CFG_TWAKEUP_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT)) & MIPI_DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK)
/*! @} */

/*! @name CFG_STATUS_OUT -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_STATUS_OUT_STATUS_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT (0U)
/*! STATUS - Status Register */
#define MIPI_DSI_HOST_CFG_STATUS_OUT_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT)) & MIPI_DSI_HOST_CFG_STATUS_OUT_STATUS_MASK)
/*! @} */

/*! @name RX_ERROR_STATUS -  */
/*! @{ */

#define MIPI_DSI_HOST_RX_ERROR_STATUS_STATUS_MASK (0x7FFU)
#define MIPI_DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT (0U)
/*! STATUS - Status Register for Host receive error detection, ECC errors, CRC errors and for timeout indicators */
#define MIPI_DSI_HOST_RX_ERROR_STATUS_STATUS(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT)) & MIPI_DSI_HOST_RX_ERROR_STATUS_STATUS_MASK)
/*! @} */

/*! @name CFG_DBI_PIXEL_PAYLOAD_SIZE -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT (0U)
/*! PAYLOAD_SIZE - Maximum number of pixels that should be sent as one DSI packet. */
#define MIPI_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT)) & MIPI_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK)
/*! @} */

/*! @name CFG_DBI_PIXEL_FIFO_SEND_LEVEL -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT (0U)
/*! FIFO_SEND_LEVEL - In order to optimize DSI utility, the DBI bridge buffers a certain number of DBI pixels before initiating a DSI packet. */
#define MIPI_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT)) & MIPI_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK)
/*! @} */

/*! @name CFG_DPI_PIXEL_PAYLOAD_SIZE -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT (0U)
/*! PAYLOAD_SIZE - Maximum number of pixels that should be sent as one DSI packet. */
#define MIPI_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK)
/*! @} */

/*! @name CFG_DPI_PIXEL_FIFO_SEND_LEVEL -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT (0U)
/*! FIFO_SEND_LEVEL - In order to optimize DSI utility, the DPI bridge buffers a cerntain number of DPI pixels before initiating a DSI packet. */
#define MIPI_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK)
/*! @} */

/*! @name CFG_DPI_INTERFACE_COLOR_CODING -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK (0x7U)
#define MIPI_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT (0U)
/*! RGB_CONFIG - Sets the distribution of RGB bits within the 24-bit d bus, as specified by the DPI specification.
 *  0b000..16-bit Configuration 1
 *  0b001..16-bit Configuration 2
 *  0b010..16-bit Configuration 3
 *  0b011..18-bit Configuration 1
 *  0b100..18-bit Configuration 2
 *  0b101..24-bit
 */
#define MIPI_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_RGB_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK)
/*! @} */

/*! @name CFG_DPI_PIXEL_FORMAT -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_PIXEL_FORMAT_PIXEL_FORMAT_MASK (0x3U)
#define MIPI_DSI_HOST_CFG_DPI_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT (0U)
/*! PIXEL_FORMAT - Sets the DSI packet type of the pixels.
 *  0b00..16 bit
 *  0b01..18 bit
 *  0b10..18 bit loosely packed
 *  0b11..24 bit
 */
#define MIPI_DSI_HOST_CFG_DPI_PIXEL_FORMAT_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_PIXEL_FORMAT_PIXEL_FORMAT_MASK)
/*! @} */

/*! @name CFG_DPI_VSYNC_POLARITY -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_VSYNC_POLARITY_VSYNC_POLARITY_MASK (0x1U)
#define MIPI_DSI_HOST_CFG_DPI_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT (0U)
/*! VSYNC_POLARITY - Sets polarity of dpi_vsync_input
 *  0b0..active low
 *  0b1..active high
 */
#define MIPI_DSI_HOST_CFG_DPI_VSYNC_POLARITY_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_VSYNC_POLARITY_VSYNC_POLARITY_MASK)
/*! @} */

/*! @name CFG_DPI_HSYNC_POLARITY -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_HSYNC_POLARITY_HSYNC_POLARITY_MASK (0x1U)
#define MIPI_DSI_HOST_CFG_DPI_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT (0U)
/*! HSYNC_POLARITY - Sets polarity of dpi_hsync_input
 *  0b0..active low
 *  0b1..active high
 */
#define MIPI_DSI_HOST_CFG_DPI_HSYNC_POLARITY_HSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_HSYNC_POLARITY_HSYNC_POLARITY_MASK)
/*! @} */

/*! @name CFG_DPI_VIDEO_MODE -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_VIDEO_MODE_VIDEO_MODE_MASK (0x3U)
#define MIPI_DSI_HOST_CFG_DPI_VIDEO_MODE_VIDEO_MODE_SHIFT (0U)
/*! VIDEO_MODE - Select DSI video mode that the host DPI module should generate packets for.
 *  0b00..Non-Burst mode with Sync Pulses
 *  0b01..Non-Burst mode with Sync Events
 *  0b10..Burst mode
 *  0b11..Reserved, not valid
 */
#define MIPI_DSI_HOST_CFG_DPI_VIDEO_MODE_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_VIDEO_MODE_VIDEO_MODE_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_VIDEO_MODE_VIDEO_MODE_MASK)
/*! @} */

/*! @name CFG_DPI_HFP -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_HFP_PAYLOAD_SIZE_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DPI_HFP_PAYLOAD_SIZE_SHIFT (0U)
/*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet. */
#define MIPI_DSI_HOST_CFG_DPI_HFP_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_HFP_PAYLOAD_SIZE_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_HFP_PAYLOAD_SIZE_MASK)
/*! @} */

/*! @name CFG_DPI_HBP -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_HBP_PAYLOAD_SIZE_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DPI_HBP_PAYLOAD_SIZE_SHIFT (0U)
/*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet. */
#define MIPI_DSI_HOST_CFG_DPI_HBP_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_HBP_PAYLOAD_SIZE_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_HBP_PAYLOAD_SIZE_MASK)
/*! @} */

/*! @name CFG_DPI_HSA -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_HSA_PAYLOAD_SIZE_MASK (0xFFFFU)
#define MIPI_DSI_HOST_CFG_DPI_HSA_PAYLOAD_SIZE_SHIFT (0U)
/*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet. */
#define MIPI_DSI_HOST_CFG_DPI_HSA_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_HSA_PAYLOAD_SIZE_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_HSA_PAYLOAD_SIZE_MASK)
/*! @} */

/*! @name CFG_DPI_ENABLE_MULT_PKTS -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK (0x1U)
#define MIPI_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT (0U)
/*! ENABLE_MULT_PKTS - Enable Multiple packets per video line.
 *  0b0..Video Line is sent in a single packet
 *  0b1..Video Line is sent in two packets
 */
#define MIPI_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK)
/*! @} */

/*! @name CFG_DPI_VBP -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_VBP_NUM_LINES_MASK (0xFFU)
#define MIPI_DSI_HOST_CFG_DPI_VBP_NUM_LINES_SHIFT (0U)
/*! NUM_LINES - Sets the number of lines in the vertical back porch. */
#define MIPI_DSI_HOST_CFG_DPI_VBP_NUM_LINES(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_VBP_NUM_LINES_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_VBP_NUM_LINES_MASK)
/*! @} */

/*! @name CFG_DPI_VFP -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_VFP_NUM_LINES_MASK (0xFFU)
#define MIPI_DSI_HOST_CFG_DPI_VFP_NUM_LINES_SHIFT (0U)
/*! NUM_LINES - Sets the number of lines in the vertical front porch. */
#define MIPI_DSI_HOST_CFG_DPI_VFP_NUM_LINES(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_VFP_NUM_LINES_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_VFP_NUM_LINES_MASK)
/*! @} */

/*! @name CFG_DPI_BLLP_MODE -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_BLLP_MODE_LP_MASK  (0x1U)
#define MIPI_DSI_HOST_CFG_DPI_BLLP_MODE_LP_SHIFT (0U)
/*! LP - Optimize bllp periods to Low Power mode when possible
 *  0b0..Blanking packets are sent during BLLP periods
 *  0b1..LP mode is used for BLLP periods
 */
#define MIPI_DSI_HOST_CFG_DPI_BLLP_MODE_LP(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_BLLP_MODE_LP_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_BLLP_MODE_LP_MASK)
/*! @} */

/*! @name CFG_DPI_USE_NULL_PKT_BLLP -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_NULL_MASK (0x1U)
#define MIPI_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_NULL_SHIFT (0U)
/*! NULL - Selects type of blanking packet to be sent during bllp region
 *  0b0..Blanking packet used in bllp region
 *  0b1..Null packet used in bllp region
 */
#define MIPI_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_NULL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_NULL_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_NULL_MASK)
/*! @} */

/*! @name CFG_DPI_VACTIVE -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_VACTIVE_NUM_LINES_MASK (0x3FFFU)
#define MIPI_DSI_HOST_CFG_DPI_VACTIVE_NUM_LINES_SHIFT (0U)
/*! NUM_LINES - Sets the number of lines in the vertical active aread. */
#define MIPI_DSI_HOST_CFG_DPI_VACTIVE_NUM_LINES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_VACTIVE_NUM_LINES_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_VACTIVE_NUM_LINES_MASK)
/*! @} */

/*! @name CFG_DPI_VC -  */
/*! @{ */

#define MIPI_DSI_HOST_CFG_DPI_VC_SET_VC_MASK     (0x3U)
#define MIPI_DSI_HOST_CFG_DPI_VC_SET_VC_SHIFT    (0U)
/*! SET_VC - Sets the Virtual Channel (VC) of packets that will be sent to the receive packet interface. */
#define MIPI_DSI_HOST_CFG_DPI_VC_SET_VC(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CFG_DPI_VC_SET_VC_SHIFT)) & MIPI_DSI_HOST_CFG_DPI_VC_SET_VC_MASK)
/*! @} */

/*! @name TX_PAYLOAD -  */
/*! @{ */

#define MIPI_DSI_HOST_TX_PAYLOAD_PAYLOAD_MASK    (0xFFFFFFFFU)
#define MIPI_DSI_HOST_TX_PAYLOAD_PAYLOAD_SHIFT   (0U)
/*! PAYLOAD - Tx Payload data write register. */
#define MIPI_DSI_HOST_TX_PAYLOAD_PAYLOAD(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_TX_PAYLOAD_PAYLOAD_SHIFT)) & MIPI_DSI_HOST_TX_PAYLOAD_PAYLOAD_MASK)
/*! @} */

/*! @name PKT_CONTROL -  */
/*! @{ */

#define MIPI_DSI_HOST_PKT_CONTROL_CTRL_MASK      (0x7FFFFFFU)
#define MIPI_DSI_HOST_PKT_CONTROL_CTRL_SHIFT     (0U)
/*! CTRL - Tx packet control register. */
#define MIPI_DSI_HOST_PKT_CONTROL_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PKT_CONTROL_CTRL_SHIFT)) & MIPI_DSI_HOST_PKT_CONTROL_CTRL_MASK)
/*! @} */

/*! @name SEND_PACKET -  */
/*! @{ */

#define MIPI_DSI_HOST_SEND_PACKET_TX_SEND_MASK   (0x1U)
#define MIPI_DSI_HOST_SEND_PACKET_TX_SEND_SHIFT  (0U)
/*! TX_SEND - Tx send packet, writing to this register causes the packet described in dsi_host_pkt_control to be sent. */
#define MIPI_DSI_HOST_SEND_PACKET_TX_SEND(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_SEND_PACKET_TX_SEND_SHIFT)) & MIPI_DSI_HOST_SEND_PACKET_TX_SEND_MASK)
/*! @} */

/*! @name PKT_STATUS -  */
/*! @{ */

#define MIPI_DSI_HOST_PKT_STATUS_STATUS_MASK     (0x1FFU)
#define MIPI_DSI_HOST_PKT_STATUS_STATUS_SHIFT    (0U)
/*! STATUS - Status of APB to packet interface */
#define MIPI_DSI_HOST_PKT_STATUS_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PKT_STATUS_STATUS_SHIFT)) & MIPI_DSI_HOST_PKT_STATUS_STATUS_MASK)
/*! @} */

/*! @name PKT_FIFO_WR_LEVEL -  */
/*! @{ */

#define MIPI_DSI_HOST_PKT_FIFO_WR_LEVEL_WR_MASK  (0xFFFFU)
#define MIPI_DSI_HOST_PKT_FIFO_WR_LEVEL_WR_SHIFT (0U)
/*! WR - Write level of APB to pkt interface fifo */
#define MIPI_DSI_HOST_PKT_FIFO_WR_LEVEL_WR(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PKT_FIFO_WR_LEVEL_WR_SHIFT)) & MIPI_DSI_HOST_PKT_FIFO_WR_LEVEL_WR_MASK)
/*! @} */

/*! @name PKT_FIFO_RD_LEVEL -  */
/*! @{ */

#define MIPI_DSI_HOST_PKT_FIFO_RD_LEVEL_RD_MASK  (0xFFFFU)
#define MIPI_DSI_HOST_PKT_FIFO_RD_LEVEL_RD_SHIFT (0U)
/*! RD - Read level of APB to pkt interface fifo */
#define MIPI_DSI_HOST_PKT_FIFO_RD_LEVEL_RD(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PKT_FIFO_RD_LEVEL_RD_SHIFT)) & MIPI_DSI_HOST_PKT_FIFO_RD_LEVEL_RD_MASK)
/*! @} */

/*! @name PKT_RX_PAYLOAD -  */
/*! @{ */

#define MIPI_DSI_HOST_PKT_RX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_PKT_RX_PAYLOAD_PAYLOAD_SHIFT (0U)
/*! PAYLOAD - APB to pkt interface rx payload read */
#define MIPI_DSI_HOST_PKT_RX_PAYLOAD_PAYLOAD(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PKT_RX_PAYLOAD_PAYLOAD_SHIFT)) & MIPI_DSI_HOST_PKT_RX_PAYLOAD_PAYLOAD_MASK)
/*! @} */

/*! @name PKT_RX_PKT_HEADER -  */
/*! @{ */

#define MIPI_DSI_HOST_PKT_RX_PKT_HEADER_HEADER_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_PKT_RX_PKT_HEADER_HEADER_SHIFT (0U)
/*! HEADER - APB to pkt interface rx packet header [15:0] word count [21:16] data type [23:22] Virtual Channel */
#define MIPI_DSI_HOST_PKT_RX_PKT_HEADER_HEADER(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PKT_RX_PKT_HEADER_HEADER_SHIFT)) & MIPI_DSI_HOST_PKT_RX_PKT_HEADER_HEADER_MASK)
/*! @} */

/*! @name IRQ_STATUS -  */
/*! @{ */

#define MIPI_DSI_HOST_IRQ_STATUS_STATUS_MASK     (0xFFFFFFFFU)
#define MIPI_DSI_HOST_IRQ_STATUS_STATUS_SHIFT    (0U)
#define MIPI_DSI_HOST_IRQ_STATUS_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_IRQ_STATUS_STATUS_SHIFT)) & MIPI_DSI_HOST_IRQ_STATUS_STATUS_MASK)
/*! @} */

/*! @name IRQ_STATUS2 -  */
/*! @{ */

#define MIPI_DSI_HOST_IRQ_STATUS2_STATUS2_MASK   (0x7U)
#define MIPI_DSI_HOST_IRQ_STATUS2_STATUS2_SHIFT  (0U)
/*! STATUS2 - Status of APB to packet interface part 2, read part 2 first then dsi_host_irq_status. */
#define MIPI_DSI_HOST_IRQ_STATUS2_STATUS2(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_IRQ_STATUS2_STATUS2_SHIFT)) & MIPI_DSI_HOST_IRQ_STATUS2_STATUS2_MASK)
/*! @} */

/*! @name IRQ_MASK -  */
/*! @{ */

#define MIPI_DSI_HOST_IRQ_MASK_MASK_MASK         (0xFFFFFFFFU)
#define MIPI_DSI_HOST_IRQ_MASK_MASK_SHIFT        (0U)
/*! MASK - IRQ Mask */
#define MIPI_DSI_HOST_IRQ_MASK_MASK(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_IRQ_MASK_MASK_SHIFT)) & MIPI_DSI_HOST_IRQ_MASK_MASK_MASK)
/*! @} */

/*! @name IRQ_MASK2 -  */
/*! @{ */

#define MIPI_DSI_HOST_IRQ_MASK2_MASK2_MASK       (0x7U)
#define MIPI_DSI_HOST_IRQ_MASK2_MASK2_SHIFT      (0U)
/*! MASK2 - IRQ Mask 2 */
#define MIPI_DSI_HOST_IRQ_MASK2_MASK2(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_IRQ_MASK2_MASK2_SHIFT)) & MIPI_DSI_HOST_IRQ_MASK2_MASK2_MASK)
/*! @} */

/*! @name PD_DPHY -  */
/*! @{ */

#define MIPI_DSI_HOST_PD_DPHY_PD_DPHY_MASK       (0x1U)
#define MIPI_DSI_HOST_PD_DPHY_PD_DPHY_SHIFT      (0U)
/*! PD_DPHY - Power Down input for PHY. When high, all PHY blocks are powered down. */
#define MIPI_DSI_HOST_PD_DPHY_PD_DPHY(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PD_DPHY_PD_DPHY_SHIFT)) & MIPI_DSI_HOST_PD_DPHY_PD_DPHY_MASK)
/*! @} */

/*! @name M_PRG_HS_PREPARE -  */
/*! @{ */

#define MIPI_DSI_HOST_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK (0x3U)
#define MIPI_DSI_HOST_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT (0U)
#define MIPI_DSI_HOST_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT)) & MIPI_DSI_HOST_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK)
/*! @} */

/*! @name MC_PRG_HS_PREPARE -  */
/*! @{ */

#define MIPI_DSI_HOST_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK (0x1U)
#define MIPI_DSI_HOST_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT (0U)
#define MIPI_DSI_HOST_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT)) & MIPI_DSI_HOST_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK)
/*! @} */

/*! @name M_PRG_HS_ZERO -  */
/*! @{ */

#define MIPI_DSI_HOST_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK (0x3FU)
#define MIPI_DSI_HOST_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT (0U)
#define MIPI_DSI_HOST_M_PRG_HS_ZERO_M_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT)) & MIPI_DSI_HOST_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK)
/*! @} */

/*! @name MC_PRG_HS_ZERO -  */
/*! @{ */

#define MIPI_DSI_HOST_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK (0x7FU)
#define MIPI_DSI_HOST_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT (0U)
#define MIPI_DSI_HOST_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT)) & MIPI_DSI_HOST_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK)
/*! @} */

/*! @name M_PRG_HS_TRAIL -  */
/*! @{ */

#define MIPI_DSI_HOST_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK (0x1FU)
#define MIPI_DSI_HOST_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT (0U)
#define MIPI_DSI_HOST_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT)) & MIPI_DSI_HOST_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK)
/*! @} */

/*! @name MC_PRG_HS_TRAIL -  */
/*! @{ */

#define MIPI_DSI_HOST_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK (0x1FU)
#define MIPI_DSI_HOST_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT (0U)
#define MIPI_DSI_HOST_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT)) & MIPI_DSI_HOST_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK)
/*! @} */

/*! @name MC_PRG_RXHS_SETTLE -  */
/*! @{ */

#define MIPI_DSI_HOST_MC_PRG_RXHS_SETTLE_MC_PRG_RXHS_SETTLE_MASK (0x3FU)
#define MIPI_DSI_HOST_MC_PRG_RXHS_SETTLE_MC_PRG_RXHS_SETTLE_SHIFT (0U)
#define MIPI_DSI_HOST_MC_PRG_RXHS_SETTLE_MC_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_MC_PRG_RXHS_SETTLE_MC_PRG_RXHS_SETTLE_SHIFT)) & MIPI_DSI_HOST_MC_PRG_RXHS_SETTLE_MC_PRG_RXHS_SETTLE_MASK)
/*! @} */

/*! @name M_PRG_RXHS_SETTLE -  */
/*! @{ */

#define MIPI_DSI_HOST_M_PRG_RXHS_SETTLE_M_PRG_RXHS_SETTLE_MASK (0x3FU)
#define MIPI_DSI_HOST_M_PRG_RXHS_SETTLE_M_PRG_RXHS_SETTLE_SHIFT (0U)
#define MIPI_DSI_HOST_M_PRG_RXHS_SETTLE_M_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_M_PRG_RXHS_SETTLE_M_PRG_RXHS_SETTLE_SHIFT)) & MIPI_DSI_HOST_M_PRG_RXHS_SETTLE_M_PRG_RXHS_SETTLE_MASK)
/*! @} */

/*! @name PD_PLL -  */
/*! @{ */

#define MIPI_DSI_HOST_PD_PLL_PD_PLL_MASK         (0x1U)
#define MIPI_DSI_HOST_PD_PLL_PD_PLL_SHIFT        (0U)
/*! PD_PLL - Power-down signal. When high, the PLL is powered down. */
#define MIPI_DSI_HOST_PD_PLL_PD_PLL(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_PD_PLL_PD_PLL_SHIFT)) & MIPI_DSI_HOST_PD_PLL_PD_PLL_MASK)
/*! @} */

/*! @name TST -  */
/*! @{ */

#define MIPI_DSI_HOST_TST_TST_MASK               (0x3FU)
#define MIPI_DSI_HOST_TST_TST_SHIFT              (0U)
/*! TST - Test Pins */
#define MIPI_DSI_HOST_TST_TST(x)                 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_TST_TST_SHIFT)) & MIPI_DSI_HOST_TST_TST_MASK)
/*! @} */

/*! @name CN -  */
/*! @{ */

#define MIPI_DSI_HOST_CN_CN_MASK                 (0x1FU)
#define MIPI_DSI_HOST_CN_CN_SHIFT                (0U)
/*! CN - Control N divider */
#define MIPI_DSI_HOST_CN_CN(x)                   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CN_CN_SHIFT)) & MIPI_DSI_HOST_CN_CN_MASK)
/*! @} */

/*! @name CM -  */
/*! @{ */

#define MIPI_DSI_HOST_CM_CM_MASK                 (0xFFU)
#define MIPI_DSI_HOST_CM_CM_SHIFT                (0U)
/*! CM - Control M divider */
#define MIPI_DSI_HOST_CM_CM(x)                   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CM_CM_SHIFT)) & MIPI_DSI_HOST_CM_CM_MASK)
/*! @} */

/*! @name CO -  */
/*! @{ */

#define MIPI_DSI_HOST_CO_CO_MASK                 (0x3U)
#define MIPI_DSI_HOST_CO_CO_SHIFT                (0U)
/*! CO - Control O divider
 *  0b00..Divide by 1
 *  0b01..Divide by 2
 *  0b10..Divide by 4
 *  0b11..Divide by 8
 */
#define MIPI_DSI_HOST_CO_CO(x)                   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_CO_CO_SHIFT)) & MIPI_DSI_HOST_CO_CO_MASK)
/*! @} */

/*! @name LOCK -  */
/*! @{ */

#define MIPI_DSI_HOST_LOCK_LOCK_MASK             (0x1U)
#define MIPI_DSI_HOST_LOCK_LOCK_SHIFT            (0U)
/*! LOCK - Lock Detect output. Asserted when the PLL has achieved frequency lock. */
#define MIPI_DSI_HOST_LOCK_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_LOCK_LOCK_SHIFT)) & MIPI_DSI_HOST_LOCK_LOCK_MASK)
/*! @} */

/*! @name LOCK_BYP -  */
/*! @{ */

#define MIPI_DSI_HOST_LOCK_BYP_LOCK_BYP_MASK     (0x1U)
#define MIPI_DSI_HOST_LOCK_BYP_LOCK_BYP_SHIFT    (0U)
/*! LOCK_BYP - When clock lane exits from ULPS, this input determines if the PLL LOCK signal will be used to gate the TxByteClkHS
 *  0b0..PLL LOCK signal will gate TxByteClkHS clock [Default]
 *  0b1..PLL LOCK signal will not gate TxByteClkHS clock, CIL based counter will be used to gate the TxByteClkHS.
 */
#define MIPI_DSI_HOST_LOCK_BYP_LOCK_BYP(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_LOCK_BYP_LOCK_BYP_SHIFT)) & MIPI_DSI_HOST_LOCK_BYP_LOCK_BYP_MASK)
/*! @} */

/*! @name AUTO_PD_EN -  */
/*! @{ */

#define MIPI_DSI_HOST_AUTO_PD_EN_AUTO_PD_EN_MASK (0x1U)
#define MIPI_DSI_HOST_AUTO_PD_EN_AUTO_PD_EN_SHIFT (0U)
/*! AUTO_PD_EN - Powers down inactive lanes reported by CFG_NUM_LANES input bus
 *  0b0..Inactive lanes are powered up and driving LP11.
 *  0b1..Inactive lanes are powered down [Default].
 */
#define MIPI_DSI_HOST_AUTO_PD_EN_AUTO_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_AUTO_PD_EN_AUTO_PD_EN_SHIFT)) & MIPI_DSI_HOST_AUTO_PD_EN_AUTO_PD_EN_MASK)
/*! @} */

/*! @name RXLPRP -  */
/*! @{ */

#define MIPI_DSI_HOST_RXLPRP_RXLPRP_MASK         (0x3U)
#define MIPI_DSI_HOST_RXLPRP_RXLPRP_SHIFT        (0U)
/*! RXLPRP - This field adjusts the threshold voltage and hysteresis of LP-RX. Default value 2'b01. */
#define MIPI_DSI_HOST_RXLPRP_RXLPRP(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_RXLPRP_RXLPRP_SHIFT)) & MIPI_DSI_HOST_RXLPRP_RXLPRP_MASK)
/*! @} */

/*! @name RXCDRP -  */
/*! @{ */

#define MIPI_DSI_HOST_RXCDRP_RXCDRP_MASK         (0x3U)
#define MIPI_DSI_HOST_RXCDRP_RXCDRP_SHIFT        (0U)
/*! RXCDRP - This field adjusts the threshold voltage of LP-CD. Default value 2'b01. */
#define MIPI_DSI_HOST_RXCDRP_RXCDRP(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_RXCDRP_RXCDRP_SHIFT)) & MIPI_DSI_HOST_RXCDRP_RXCDRP_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MIPI_DSI_HOST_Register_Masks */


/* MIPI_DSI_HOST - Peripheral instance base addresses */
/** Peripheral MIPI_DSI base address */
#define MIPI_DSI_BASE                            (0x2DB00000u)
/** Peripheral MIPI_DSI base pointer */
#define MIPI_DSI                                 ((MIPI_DSI_HOST_Type *)MIPI_DSI_BASE)
/** Array initializer of MIPI_DSI_HOST peripheral base addresses */
#define MIPI_DSI_HOST_BASE_ADDRS                 { MIPI_DSI_BASE }
/** Array initializer of MIPI_DSI_HOST peripheral base pointers */
#define MIPI_DSI_HOST_BASE_PTRS                  { MIPI_DSI }

/*!
 * @}
 */ /* end of group MIPI_DSI_HOST_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MRT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
 * @{
 */

/** MRT - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0x10 */
    __IO uint32_t INTVAL;                            /**< Time Interval Value, array offset: 0x0, array step: 0x10 */
    __I  uint32_t TIMER;                             /**< Timer, array offset: 0x4, array step: 0x10 */
    __IO uint32_t CTRL;                              /**< Control, array offset: 0x8, array step: 0x10 */
    __IO uint32_t STAT;                              /**< Status, array offset: 0xC, array step: 0x10 */
  } CHANNEL[4];
       uint8_t RESERVED_0[176];
  __IO uint32_t MODCFG;                            /**< Module Configuration, offset: 0xF0 */
  __I  uint32_t IDLE_CH;                           /**< Idle Channel, offset: 0xF4 */
  __IO uint32_t IRQ_FLAG;                          /**< Global Interrupt Flag, offset: 0xF8 */
} MRT_Type;

/* ----------------------------------------------------------------------------
   -- MRT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MRT_Register_Masks MRT Register Masks
 * @{
 */

/*! @name CHANNEL_INTVAL - Time Interval Value */
/*! @{ */

#define MRT_CHANNEL_INTVAL_IVALUE_MASK           (0xFFFFFFU)
#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT          (0U)
/*! IVALUE - Time interval load value. */
#define MRT_CHANNEL_INTVAL_IVALUE(x)             (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)

#define MRT_CHANNEL_INTVAL_LOAD_MASK             (0x80000000U)
#define MRT_CHANNEL_INTVAL_LOAD_SHIFT            (31U)
/*! LOAD - Determines how the timer interval value (IVALUE -1) is loaded into the TIMER n register.
 *  0b0..No force load.
 *  0b1..Force load. T
 */
#define MRT_CHANNEL_INTVAL_LOAD(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
/*! @} */

/* The count of MRT_CHANNEL_INTVAL */
#define MRT_CHANNEL_INTVAL_COUNT                 (4U)

/*! @name CHANNEL_TIMER - Timer */
/*! @{ */

#define MRT_CHANNEL_TIMER_VALUE_MASK             (0xFFFFFFU)
#define MRT_CHANNEL_TIMER_VALUE_SHIFT            (0U)
/*! VALUE - Holds the current timer value of the down-counter. */
#define MRT_CHANNEL_TIMER_VALUE(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
/*! @} */

/* The count of MRT_CHANNEL_TIMER */
#define MRT_CHANNEL_TIMER_COUNT                  (4U)

/*! @name CHANNEL_CTRL - Control */
/*! @{ */

#define MRT_CHANNEL_CTRL_INTEN_MASK              (0x1U)
#define MRT_CHANNEL_CTRL_INTEN_SHIFT             (0U)
/*! INTEN - Enable the TIMER n interrupt.
 *  0b0..Disabled. TIMER n interrupt is disabled.
 *  0b1..Enabled. TIMER n interrupt is enabled.
 */
#define MRT_CHANNEL_CTRL_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)

#define MRT_CHANNEL_CTRL_MODE_MASK               (0x6U)
#define MRT_CHANNEL_CTRL_MODE_SHIFT              (1U)
/*! MODE - Selects the timer mode
 *  0b00..Repeat interrupt mode
 *  0b01..One-shot interrupt mode
 *  0b10..One-shot stall mode
 *  0b11..Reserved
 */
#define MRT_CHANNEL_CTRL_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
/*! @} */

/* The count of MRT_CHANNEL_CTRL */
#define MRT_CHANNEL_CTRL_COUNT                   (4U)

/*! @name CHANNEL_STAT - Status */
/*! @{ */

#define MRT_CHANNEL_STAT_INTFLAG_MASK            (0x1U)
#define MRT_CHANNEL_STAT_INTFLAG_SHIFT           (0U)
/*! INTFLAG - Monitors the interrupt flag
 *  0b0..No pending interrupt. Writing a zero is equivalent to no operation.
 *  0b1..Pending interrupt.
 */
#define MRT_CHANNEL_STAT_INTFLAG(x)              (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)

#define MRT_CHANNEL_STAT_RUN_MASK                (0x2U)
#define MRT_CHANNEL_STAT_RUN_SHIFT               (1U)
/*! RUN - Indicates the state of TIMER n. RUN bit is read-only.
 *  0b0..Idle state. TIMER n has stopped.
 *  0b1..Running. TIMER n is running.
 */
#define MRT_CHANNEL_STAT_RUN(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)

#define MRT_CHANNEL_STAT_INUSE_MASK              (0x4U)
#define MRT_CHANNEL_STAT_INUSE_SHIFT             (2U)
/*! INUSE - Channel-In-Use flag
 *  0b0..This timer channel is not in use.
 *  0b1..This timer channel is in use. Writing a 1 to this bit clears the status.
 */
#define MRT_CHANNEL_STAT_INUSE(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
/*! @} */

/* The count of MRT_CHANNEL_STAT */
#define MRT_CHANNEL_STAT_COUNT                   (4U)

/*! @name MODCFG - Module Configuration */
/*! @{ */

#define MRT_MODCFG_NOC_MASK                      (0xFU)
#define MRT_MODCFG_NOC_SHIFT                     (0U)
/*! NOC - Number Of Channels: identifies the number of channels in this MRT. (Minus 1 encoded) */
#define MRT_MODCFG_NOC(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)

#define MRT_MODCFG_NOB_MASK                      (0x1F0U)
#define MRT_MODCFG_NOB_SHIFT                     (4U)
/*! NOB - Number Of Bits: identifies the number of timer bits in this MRT. (24 bits on this device) */
#define MRT_MODCFG_NOB(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)

#define MRT_MODCFG_MULTITASK_MASK                (0x80000000U)
#define MRT_MODCFG_MULTITASK_SHIFT               (31U)
/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register.
 *  0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.
 *  0b1..Multi-task mode
 */
#define MRT_MODCFG_MULTITASK(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
/*! @} */

/*! @name IDLE_CH - Idle Channel */
/*! @{ */

#define MRT_IDLE_CH_CHAN_MASK                    (0xF0U)
#define MRT_IDLE_CH_CHAN_SHIFT                   (4U)
/*! CHAN - Idle channel. */
#define MRT_IDLE_CH_CHAN(x)                      (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
/*! @} */

/*! @name IRQ_FLAG - Global Interrupt Flag */
/*! @{ */

#define MRT_IRQ_FLAG_GFLAG0_MASK                 (0x1U)
#define MRT_IRQ_FLAG_GFLAG0_SHIFT                (0U)
/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
 *  0b0..No pending interrupt. Writing a zero is equivalent to no operation.
 *  0b1..Pending interrupt
 */
#define MRT_IRQ_FLAG_GFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)

#define MRT_IRQ_FLAG_GFLAG1_MASK                 (0x2U)
#define MRT_IRQ_FLAG_GFLAG1_SHIFT                (1U)
/*! GFLAG1 - Monitors the interrupt flag of TIMER1, and acts similarly to channel 0. */
#define MRT_IRQ_FLAG_GFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)

#define MRT_IRQ_FLAG_GFLAG2_MASK                 (0x4U)
#define MRT_IRQ_FLAG_GFLAG2_SHIFT                (2U)
/*! GFLAG2 - Monitors the interrupt flag of TIMER2, and acts similarly to channel 0. */
#define MRT_IRQ_FLAG_GFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)

#define MRT_IRQ_FLAG_GFLAG3_MASK                 (0x8U)
#define MRT_IRQ_FLAG_GFLAG3_SHIFT                (3U)
/*! GFLAG3 - Monitors the interrupt flag of TIMER3, and acts similarly to channel 0. */
#define MRT_IRQ_FLAG_GFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MRT_Register_Masks */


/* MRT - Peripheral instance base addresses */
/** Peripheral MRT0 base address */
#define MRT0_BASE                                (0x28107000u)
/** Peripheral MRT0 base pointer */
#define MRT0                                     ((MRT_Type *)MRT0_BASE)
/** Array initializer of MRT peripheral base addresses */
#define MRT_BASE_ADDRS                           { MRT0_BASE }
/** Array initializer of MRT peripheral base pointers */
#define MRT_BASE_PTRS                            { MRT0 }

/*!
 * @}
 */ /* end of group MRT_Peripheral_Access_Layer */

/*!
 * @brief Core boot mode.
 */
typedef enum _mu_core_boot_mode
{
    kMU_CoreBootFromAddr0 = 0x00U, /*!< Boot from 0x00.      */
    kMU_CoreBootFromFlash = 0x01U, /*!< Boot from Flash base. */
    kMU_CoreBootFromItcm  = 0x02U, /*!< Boot from ITCM base. */
} mu_core_boot_mode_t;


/* ----------------------------------------------------------------------------
   -- MU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
 * @{
 */

/** MU - Register Layout Typedef */
typedef struct {
  __I  uint32_t VER;                               /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PAR;                               /**< Parameter Register, offset: 0x4 */
  __IO uint32_t CR;                                /**< Control Register, offset: 0x8 */
  __IO uint32_t SR;                                /**< Status Register, offset: 0xC */
  __IO uint32_t CCR0;                              /**< Core Control Register 0, offset: 0x10 */
  __IO uint32_t CIER0;                             /**< Core Interrupt Enable Register 0, offset: 0x14 */
  __IO uint32_t CSSR0;                             /**< Core Sticky Status Register 0, offset: 0x18 */
  __I  uint32_t CSR0;                              /**< Core Status Register 0, offset: 0x1C */
       uint8_t RESERVED_0[224];
  __IO uint32_t FCR;                               /**< Flag Control Register, offset: 0x100 */
  __I  uint32_t FSR;                               /**< Flag Status Register, offset: 0x104 */
       uint8_t RESERVED_1[8];
  __IO uint32_t GIER;                              /**< General Interrupt Enable Register, offset: 0x110 */
  __IO uint32_t GCR;                               /**< General Control Register, offset: 0x114 */
  __IO uint32_t GSR;                               /**< General Status Register, offset: 0x118 */
       uint8_t RESERVED_2[4];
  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0x120 */
  __I  uint32_t TSR;                               /**< Transmit Status Register, offset: 0x124 */
  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x128 */
  __I  uint32_t RSR;                               /**< Receive Status Register, offset: 0x12C */
       uint8_t RESERVED_3[208];
  __IO uint32_t TR[4];                             /**< Transmit Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_4[112];
  __I  uint32_t RR[4];                             /**< Receive Register, array offset: 0x280, array step: 0x4 */
} MU_Type;

/* ----------------------------------------------------------------------------
   -- MU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MU_Register_Masks MU Register Masks
 * @{
 */

/*! @name VER - Version ID Register */
/*! @{ */

#define MU_VER_FEATURE_MASK                      (0xFFFFU)
#define MU_VER_FEATURE_SHIFT                     (0U)
/*! FEATURE - Feature Set Number */
#define MU_VER_FEATURE(x)                        (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK)

#define MU_VER_MINOR_MASK                        (0xFF0000U)
#define MU_VER_MINOR_SHIFT                       (16U)
/*! MINOR - Minor Version Number */
#define MU_VER_MINOR(x)                          (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK)

#define MU_VER_MAJOR_MASK                        (0xFF000000U)
#define MU_VER_MAJOR_SHIFT                       (24U)
/*! MAJOR - Major Version Number */
#define MU_VER_MAJOR(x)                          (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK)
/*! @} */

/*! @name PAR - Parameter Register */
/*! @{ */

#define MU_PAR_TR_NUM_MASK                       (0xFFU)
#define MU_PAR_TR_NUM_SHIFT                      (0U)
/*! TR_NUM - Transmit Register Number */
#define MU_PAR_TR_NUM(x)                         (((uint32_t)(((uint32_t)(x)) << MU_PAR_TR_NUM_SHIFT)) & MU_PAR_TR_NUM_MASK)

#define MU_PAR_RR_NUM_MASK                       (0xFF00U)
#define MU_PAR_RR_NUM_SHIFT                      (8U)
/*! RR_NUM - RR Number */
#define MU_PAR_RR_NUM(x)                         (((uint32_t)(((uint32_t)(x)) << MU_PAR_RR_NUM_SHIFT)) & MU_PAR_RR_NUM_MASK)

#define MU_PAR_GIR_NUM_MASK                      (0xFF0000U)
#define MU_PAR_GIR_NUM_SHIFT                     (16U)
/*! GIR_NUM - General Interrupt Request Number */
#define MU_PAR_GIR_NUM(x)                        (((uint32_t)(((uint32_t)(x)) << MU_PAR_GIR_NUM_SHIFT)) & MU_PAR_GIR_NUM_MASK)

#define MU_PAR_FLAG_WIDTH_MASK                   (0xFF000000U)
#define MU_PAR_FLAG_WIDTH_SHIFT                  (24U)
/*! FLAG_WIDTH - Flag Width */
#define MU_PAR_FLAG_WIDTH(x)                     (((uint32_t)(((uint32_t)(x)) << MU_PAR_FLAG_WIDTH_SHIFT)) & MU_PAR_FLAG_WIDTH_MASK)
/*! @} */

/*! @name CR - Control Register */
/*! @{ */

#define MU_CR_MUR_MASK                           (0x1U)
#define MU_CR_MUR_SHIFT                          (0U)
/*! MUR - MU Reset
 *  0b0..Self clearing bit.
 *  0b1..Asserts the MU reset.
 */
#define MU_CR_MUR(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)

#define MU_CR_MURIE_MASK                         (0x2U)
#define MU_CR_MURIE_SHIFT                        (1U)
/*! MURIE - MUB Reset Interrupt Enable
 *  0b0..Disables Processor B-side MU Reset Interrupt request due to MU reset issued by MUA.
 *  0b1..Enables Processor B-side MU Reset Interrupt request due to MU reset issued by MUA.
 */
#define MU_CR_MURIE(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CR_MURIE_SHIFT)) & MU_CR_MURIE_MASK)
/*! @} */

/*! @name SR - Status Register */
/*! @{ */

#define MU_SR_MURS_MASK                          (0x1U)
#define MU_SR_MURS_SHIFT                         (0U)
/*! MURS - MUA and MUB Reset State
 *  0b0..MUA and MUB are out of reset.
 *  0b1..MUA or MUB is in reset state.
 */
#define MU_SR_MURS(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_MURS_SHIFT)) & MU_SR_MURS_MASK)

#define MU_SR_MURIP_MASK                         (0x2U)
#define MU_SR_MURIP_SHIFT                        (1U)
/*! MURIP - MU Reset Interrupt Pending
 *  0b0..Processor A did not issue MU reset.
 *  0b1..Processor A issued MU reset.
 */
#define MU_SR_MURIP(x)                           (((uint32_t)(((uint32_t)(x)) << MU_SR_MURIP_SHIFT)) & MU_SR_MURIP_MASK)

#define MU_SR_EP_MASK                            (0x4U)
#define MU_SR_EP_SHIFT                           (2U)
/*! EP - MUB Side Event Pending
 *  0b0..The MUB side event is not pending.
 *  0b1..The MUB side event is pending.
 */
#define MU_SR_EP(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)

#define MU_SR_FUP_MASK                           (0x8U)
#define MU_SR_FUP_SHIFT                          (3U)
/*! FUP - MUB Flags Update Pending
 *  0b0..No pending update flags(initiated by MUB) are in process
 *  0b1..Pending update flags(initiated by MUB) are in process
 */
#define MU_SR_FUP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)

#define MU_SR_GIRP_MASK                          (0x10U)
#define MU_SR_GIRP_SHIFT                         (4U)
/*! GIRP - MUB General Interrupt Pending
 *  0b0..No general interrupt request is sent from MUA.
 *  0b1..Any general interrupt request is sent from MUA.
 */
#define MU_SR_GIRP(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_GIRP_SHIFT)) & MU_SR_GIRP_MASK)

#define MU_SR_TEP_MASK                           (0x20U)
#define MU_SR_TEP_SHIFT                          (5U)
/*! TEP - MUB Transmit Empty Pending
 *  0b0..RRn register is not read by MUA.
 *  0b1..Any RRn register is read by MUA.
 */
#define MU_SR_TEP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_TEP_SHIFT)) & MU_SR_TEP_MASK)

#define MU_SR_RFP_MASK                           (0x40U)
#define MU_SR_RFP_SHIFT                          (6U)
/*! RFP - MUB Receive Full Pending Flag
 *  0b0..No TRn register is written by MUA.
 *  0b1..Any TRn register is written by MUA.
 */
#define MU_SR_RFP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_RFP_SHIFT)) & MU_SR_RFP_MASK)

#define MU_SR_CEP_MASK                           (0x80U)
#define MU_SR_CEP_SHIFT                          (7U)
/*! CEP - Processor A Event Pending Flag
 *  0b0..No core operation mode entry event pending.
 *  0b1..Any core operation mode entry event pending.
 */
#define MU_SR_CEP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_CEP_SHIFT)) & MU_SR_CEP_MASK)
/*! @} */

/*! @name CCR0 - Core Control Register 0 */
/*! @{ */

#define MU_CCR0_NMI_MASK                         (0x1U)
#define MU_CCR0_NMI_SHIFT                        (0U)
/*! NMI - MUA Non-maskable Interrupt Request
 *  0b0..Non-maskable interrupt is not issued to the Processor A by the Processor B.
 *  0b1..Non-maskable interrupt is issued to the Processor A by the Processor B.
 */
#define MU_CCR0_NMI(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CCR0_NMI_SHIFT)) & MU_CCR0_NMI_MASK)

#define MU_CCR0_HR_MASK                          (0x2U)
#define MU_CCR0_HR_SHIFT                         (1U)
/*! HR - Processor A Hardware Reset
 *  0b0..De-assert Hardware reset to the Processor A.
 *  0b1..Assert Hardware reset to the Processor A.
 */
#define MU_CCR0_HR(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CCR0_HR_SHIFT)) & MU_CCR0_HR_MASK)

#define MU_CCR0_HRM_MASK                         (0x4U)
#define MU_CCR0_HRM_SHIFT                        (2U)
/*! HRM - Processor B Hardware Reset Mask
 *  0b0..The MUA_CCR0[HR] bit is not masked, and the hardware reset to the Processor B is enabled.
 *  0b1..The MUA_CCR0[HR] bit is masked, and the hardware reset request to the Processor B is disabled.
 */
#define MU_CCR0_HRM(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CCR0_HRM_SHIFT)) & MU_CCR0_HRM_MASK)

#define MU_CCR0_CLKE_MASK                        (0x8U)
#define MU_CCR0_CLKE_SHIFT                       (3U)
/*! CLKE - Processor A clock enable
 *  0b0..Processor A platform clock is gated when Processor A enters a stop mode.
 *  0b1..Processor A platform clock is kept running after Processor A enters a stop mode, until Processor B also enters a stop mode.
 */
#define MU_CCR0_CLKE(x)                          (((uint32_t)(((uint32_t)(x)) << MU_CCR0_CLKE_SHIFT)) & MU_CCR0_CLKE_MASK)

#define MU_CCR0_RSTH_MASK                        (0x10U)
#define MU_CCR0_RSTH_SHIFT                       (4U)
/*! RSTH - Processor A Reset Hold
 *  0b0..Release Processor A from reset
 *  0b1..Hold Processor A in reset
 */
#define MU_CCR0_RSTH(x)                          (((uint32_t)(((uint32_t)(x)) << MU_CCR0_RSTH_SHIFT)) & MU_CCR0_RSTH_MASK)

#define MU_CCR0_BOOT_MASK                        (0x60U)
#define MU_CCR0_BOOT_SHIFT                       (5U)
/*! BOOT - Slave Processor A Boot Config.
 *  0b00..Processor Boot option 0
 *  0b01..Processor Boot option 1
 *  0b10..Processor Boot option 2
 *  0b11..Processor Boot option 3
 */
#define MU_CCR0_BOOT(x)                          (((uint32_t)(((uint32_t)(x)) << MU_CCR0_BOOT_SHIFT)) & MU_CCR0_BOOT_MASK)
/*! @} */

/*! @name CIER0 - Core Interrupt Enable Register 0 */
/*! @{ */

#define MU_CIER0_HRIE_MASK                       (0x2U)
#define MU_CIER0_HRIE_SHIFT                      (1U)
/*! HRIE - Processor B Hardware Reset Interrupt Enable
 *  0b0..Disables Processor B Hardware Reset Interrupt request due to Processor A issues HR to Processor B.
 *  0b1..Enables Processor B Hardware Reset Interrupt request due to Processor A issues HR to Processor B.
 */
#define MU_CIER0_HRIE(x)                         (((uint32_t)(((uint32_t)(x)) << MU_CIER0_HRIE_SHIFT)) & MU_CIER0_HRIE_MASK)

#define MU_CIER0_RUNIE_MASK                      (0x4U)
#define MU_CIER0_RUNIE_SHIFT                     (2U)
/*! RUNIE - Processor A Run Mode Entry Interrupt Enable
 *  0b0..Disables Processor B Run Mode Entry Interrupt request due to Processor A Run Mode Entry.
 *  0b1..Enables Processor B Run Mode Entry Interrupt request due to Processor A Run Mode Entry.
 */
#define MU_CIER0_RUNIE(x)                        (((uint32_t)(((uint32_t)(x)) << MU_CIER0_RUNIE_SHIFT)) & MU_CIER0_RUNIE_MASK)

#define MU_CIER0_RAIE_MASK                       (0x8U)
#define MU_CIER0_RAIE_SHIFT                      (3U)
/*! RAIE - Processor A Reset Assertion Interrupt Enable
 *  0b0..Disables Processor B Reset Assertion Interrupt request due to Processor A reset assertion.
 *  0b1..Enables Processor B Reset Assertion Interrupt request due to Processor A reset assertion.
 */
#define MU_CIER0_RAIE(x)                         (((uint32_t)(((uint32_t)(x)) << MU_CIER0_RAIE_SHIFT)) & MU_CIER0_RAIE_MASK)

#define MU_CIER0_HALTIE_MASK                     (0x10U)
#define MU_CIER0_HALTIE_SHIFT                    (4U)
/*! HALTIE - Processor A Halt Mode Entry Interrupt Enable
 *  0b0..Disables Processor B Halt Mode Entry Interrupt request due to Processor A Halt Mode Entry.
 *  0b1..Enables Processor B Halt Mode Entry Interrupt request due to Processor A Halt Mode Entry.
 */
#define MU_CIER0_HALTIE(x)                       (((uint32_t)(((uint32_t)(x)) << MU_CIER0_HALTIE_SHIFT)) & MU_CIER0_HALTIE_MASK)

#define MU_CIER0_WAITIE_MASK                     (0x20U)
#define MU_CIER0_WAITIE_SHIFT                    (5U)
/*! WAITIE - Processor A Wait Mode Entry Interrupt Enable
 *  0b0..Disables Processor B Wait Mode Entry Interrupt request due to Processor A Wait Mode Entry.
 *  0b1..Enables Processor B Wait Mode Entry Interrupt request due to Processor A Wait Mode Entry.
 */
#define MU_CIER0_WAITIE(x)                       (((uint32_t)(((uint32_t)(x)) << MU_CIER0_WAITIE_SHIFT)) & MU_CIER0_WAITIE_MASK)

#define MU_CIER0_STOPIE_MASK                     (0x40U)
#define MU_CIER0_STOPIE_SHIFT                    (6U)
/*! STOPIE - Processor A Stop Mode Entry Interrupt Enable
 *  0b0..Disables Processor B Stop Mode Entry Interrupt request due to Processor A Stop Mode Entry.
 *  0b1..Enables Processor B Stop Mode Entry Interrupt request due to Processor A Stop Mode Entry.
 */
#define MU_CIER0_STOPIE(x)                       (((uint32_t)(((uint32_t)(x)) << MU_CIER0_STOPIE_SHIFT)) & MU_CIER0_STOPIE_MASK)

#define MU_CIER0_PDIE_MASK                       (0x80U)
#define MU_CIER0_PDIE_SHIFT                      (7U)
/*! PDIE - Processor A Power-Down Mode Entry Interrupt Enable
 *  0b0..Disables Processor B Power-Down Mode Entry Interrupt request due to Processor A Power-Down Mode Entry.
 *  0b1..Enables Processor B Power-Down Mode Entry Interrupt request due to Processor A Power-Down Mode Entry.
 */
#define MU_CIER0_PDIE(x)                         (((uint32_t)(((uint32_t)(x)) << MU_CIER0_PDIE_SHIFT)) & MU_CIER0_PDIE_MASK)
/*! @} */

/*! @name CSSR0 - Core Sticky Status Register 0 */
/*! @{ */

#define MU_CSSR0_NMIC_MASK                       (0x1U)
#define MU_CSSR0_NMIC_SHIFT                      (0U)
/*! NMIC - Processor B Non-Maskable-Interrupt Clear
 *  0b0..Default
 *  0b1..Writing "1" clears the MUA_CCR0[NMI] bit.
 */
#define MU_CSSR0_NMIC(x)                         (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_NMIC_SHIFT)) & MU_CSSR0_NMIC_MASK)

#define MU_CSSR0_HRIP_MASK                       (0x2U)
#define MU_CSSR0_HRIP_SHIFT                      (1U)
/*! HRIP - Processor B Hardware Reset Interrupt Pending
 *  0b0..MUA didn't issue hardware reset to Processor B
 *  0b1..MUA had initiated a hardware reset to Processor B through HR bit.
 */
#define MU_CSSR0_HRIP(x)                         (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_HRIP_SHIFT)) & MU_CSSR0_HRIP_MASK)

#define MU_CSSR0_RUN_MASK                        (0x4U)
#define MU_CSSR0_RUN_SHIFT                       (2U)
/*! RUN - Processor A Run Mode Entry Interrupt Pending
 *  0b0..Processor A did not enter Run Mode.
 *  0b1..Processor A entered Run Mode
 */
#define MU_CSSR0_RUN(x)                          (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_RUN_SHIFT)) & MU_CSSR0_RUN_MASK)

#define MU_CSSR0_RAIP_MASK                       (0x8U)
#define MU_CSSR0_RAIP_SHIFT                      (3U)
/*! RAIP - Processor A Reset Asserted Interrupt Pending
 *  0b0..Processor A did not enter reset
 *  0b1..Processor A entered reset
 */
#define MU_CSSR0_RAIP(x)                         (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_RAIP_SHIFT)) & MU_CSSR0_RAIP_MASK)

#define MU_CSSR0_HALT_MASK                       (0x10U)
#define MU_CSSR0_HALT_SHIFT                      (4U)
/*! HALT - Processor A Halt Mode Entry Interrupt Pending
 *  0b0..Processor A did not enter Halt Mode.
 *  0b1..Processor A entered Halt Mode
 */
#define MU_CSSR0_HALT(x)                         (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_HALT_SHIFT)) & MU_CSSR0_HALT_MASK)

#define MU_CSSR0_WAIT_MASK                       (0x20U)
#define MU_CSSR0_WAIT_SHIFT                      (5U)
/*! WAIT - Processor A Wait Mode Entry Interrupt Pending
 *  0b0..Processor A did not enter Wait Mode.
 *  0b1..Processor A entered Wait Mode
 */
#define MU_CSSR0_WAIT(x)                         (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_WAIT_SHIFT)) & MU_CSSR0_WAIT_MASK)

#define MU_CSSR0_STOP_MASK                       (0x40U)
#define MU_CSSR0_STOP_SHIFT                      (6U)
/*! STOP - Processor A Stop Mode Entry Interrupt Pending
 *  0b0..Processor A did not enter Stop Mode.
 *  0b1..Processor A entered Stop Mode
 */
#define MU_CSSR0_STOP(x)                         (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_STOP_SHIFT)) & MU_CSSR0_STOP_MASK)

#define MU_CSSR0_PD_MASK                         (0x80U)
#define MU_CSSR0_PD_SHIFT                        (7U)
/*! PD - Processor A Power-Down Mode Entry Interrupt Pending
 *  0b0..Processor A did not enter Power-Down Mode.
 *  0b1..Processor A entered Power-Down Mode
 */
#define MU_CSSR0_PD(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_PD_SHIFT)) & MU_CSSR0_PD_MASK)
/*! @} */

/*! @name CSR0 - Core Status Register 0 */
/*! @{ */

#define MU_CSR0_HRIP_MASK                        (0x2U)
#define MU_CSR0_HRIP_SHIFT                       (1U)
/*! HRIP - Processor B Hardware Reset Interrupt Pending
 *  0b0..MUA didn't issue hardware reset to Processor B.
 *  0b1..MUA had initiated a hardware reset to Processor B through HR bit.
 */
#define MU_CSR0_HRIP(x)                          (((uint32_t)(((uint32_t)(x)) << MU_CSR0_HRIP_SHIFT)) & MU_CSR0_HRIP_MASK)

#define MU_CSR0_RUN_MASK                         (0x4U)
#define MU_CSR0_RUN_SHIFT                        (2U)
/*! RUN - Processor A Run Mode Entry
 *  0b0..Processor A did not enter Run Mode.
 *  0b1..Processor A entered Run Mode.
 */
#define MU_CSR0_RUN(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CSR0_RUN_SHIFT)) & MU_CSR0_RUN_MASK)

#define MU_CSR0_RAIP_MASK                        (0x8U)
#define MU_CSR0_RAIP_SHIFT                       (3U)
/*! RAIP - Processor A Reset Asserted Interrupt Pending
 *  0b0..Processor A did not enter reset.
 *  0b1..Processor A entered reset.
 */
#define MU_CSR0_RAIP(x)                          (((uint32_t)(((uint32_t)(x)) << MU_CSR0_RAIP_SHIFT)) & MU_CSR0_RAIP_MASK)

#define MU_CSR0_HALT_MASK                        (0x10U)
#define MU_CSR0_HALT_SHIFT                       (4U)
/*! HALT - Processor A Halt Mode Entry
 *  0b0..Processor A did not enter Halt Mode.
 *  0b1..Processor A entered Halt Mode.
 */
#define MU_CSR0_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << MU_CSR0_HALT_SHIFT)) & MU_CSR0_HALT_MASK)

#define MU_CSR0_WAIT_MASK                        (0x20U)
#define MU_CSR0_WAIT_SHIFT                       (5U)
/*! WAIT - Processor A Wait Mode Entry
 *  0b0..Processor A did not enter Wait Mode.
 *  0b1..Processor A entered Wait Mode.
 */
#define MU_CSR0_WAIT(x)                          (((uint32_t)(((uint32_t)(x)) << MU_CSR0_WAIT_SHIFT)) & MU_CSR0_WAIT_MASK)

#define MU_CSR0_STOP_MASK                        (0x40U)
#define MU_CSR0_STOP_SHIFT                       (6U)
/*! STOP - Processor A Stop Mode Entry
 *  0b0..Processor A did not enter Stop Mode.
 *  0b1..Processor A entered Stop Mode.
 */
#define MU_CSR0_STOP(x)                          (((uint32_t)(((uint32_t)(x)) << MU_CSR0_STOP_SHIFT)) & MU_CSR0_STOP_MASK)

#define MU_CSR0_PD_MASK                          (0x80U)
#define MU_CSR0_PD_SHIFT                         (7U)
/*! PD - Processor A Power-Down Mode Entry
 *  0b0..Processor A did not enter Power-Down Mode.
 *  0b1..Processor A entered Power-Down Mode.
 */
#define MU_CSR0_PD(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CSR0_PD_SHIFT)) & MU_CSR0_PD_MASK)
/*! @} */

/*! @name FCR - Flag Control Register */
/*! @{ */

#define MU_FCR_F0_MASK                           (0x1U)
#define MU_FCR_F0_SHIFT                          (0U)
/*! F0 - MUB to MUA Flag n
 *  0b0..Clears the Fn bit in the FSR register.
 *  0b1..Sets the Fn bit in the FSR register.
 */
#define MU_FCR_F0(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FCR_F0_SHIFT)) & MU_FCR_F0_MASK)

#define MU_FCR_F1_MASK                           (0x2U)
#define MU_FCR_F1_SHIFT                          (1U)
/*! F1 - MUB to MUA Flag n
 *  0b0..Clears the Fn bit in the FSR register.
 *  0b1..Sets the Fn bit in the FSR register.
 */
#define MU_FCR_F1(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FCR_F1_SHIFT)) & MU_FCR_F1_MASK)

#define MU_FCR_F2_MASK                           (0x4U)
#define MU_FCR_F2_SHIFT                          (2U)
/*! F2 - MUB to MUA Flag n
 *  0b0..Clears the Fn bit in the FSR register.
 *  0b1..Sets the Fn bit in the FSR register.
 */
#define MU_FCR_F2(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FCR_F2_SHIFT)) & MU_FCR_F2_MASK)
/*! @} */

/*! @name FSR - Flag Status Register */
/*! @{ */

#define MU_FSR_F0_MASK                           (0x1U)
#define MU_FSR_F0_SHIFT                          (0U)
/*! F0 - MUA to MUB Side Flag n
 *  0b0..Fn bit in the MUA FCR register is written 0.
 *  0b1..Fn bit in the MUA FCR register is written 1.
 */
#define MU_FSR_F0(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FSR_F0_SHIFT)) & MU_FSR_F0_MASK)

#define MU_FSR_F1_MASK                           (0x2U)
#define MU_FSR_F1_SHIFT                          (1U)
/*! F1 - MUA to MUB Side Flag n
 *  0b0..Fn bit in the MUA FCR register is written 0.
 *  0b1..Fn bit in the MUA FCR register is written 1.
 */
#define MU_FSR_F1(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FSR_F1_SHIFT)) & MU_FSR_F1_MASK)

#define MU_FSR_F2_MASK                           (0x4U)
#define MU_FSR_F2_SHIFT                          (2U)
/*! F2 - MUA to MUB Side Flag n
 *  0b0..Fn bit in the MUA FCR register is written 0.
 *  0b1..Fn bit in the MUA FCR register is written 1.
 */
#define MU_FSR_F2(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FSR_F2_SHIFT)) & MU_FSR_F2_MASK)
/*! @} */

/*! @name GIER - General Interrupt Enable Register */
/*! @{ */

#define MU_GIER_GIE0_MASK                        (0x1U)
#define MU_GIER_GIE0_SHIFT                       (0U)
/*! GIE0 - MUB General Purpose Interrupt Enable n
 *  0b0..Disables MUB General Interrupt n.
 *  0b1..Enables MUB General Interrupt n.
 */
#define MU_GIER_GIE0(x)                          (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE0_SHIFT)) & MU_GIER_GIE0_MASK)

#define MU_GIER_GIE1_MASK                        (0x2U)
#define MU_GIER_GIE1_SHIFT                       (1U)
/*! GIE1 - MUB General Purpose Interrupt Enable n
 *  0b0..Disables MUB General Interrupt n.
 *  0b1..Enables MUB General Interrupt n.
 */
#define MU_GIER_GIE1(x)                          (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE1_SHIFT)) & MU_GIER_GIE1_MASK)

#define MU_GIER_GIE2_MASK                        (0x4U)
#define MU_GIER_GIE2_SHIFT                       (2U)
/*! GIE2 - MUB General Purpose Interrupt Enable n
 *  0b0..Disables MUB General Interrupt n.
 *  0b1..Enables MUB General Interrupt n.
 */
#define MU_GIER_GIE2(x)                          (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE2_SHIFT)) & MU_GIER_GIE2_MASK)

#define MU_GIER_GIE3_MASK                        (0x8U)
#define MU_GIER_GIE3_SHIFT                       (3U)
/*! GIE3 - MUB General Purpose Interrupt Enable n
 *  0b0..Disables MUB General Interrupt n.
 *  0b1..Enables MUB General Interrupt n.
 */
#define MU_GIER_GIE3(x)                          (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE3_SHIFT)) & MU_GIER_GIE3_MASK)
/*! @} */

/*! @name GCR - General Control Register */
/*! @{ */

#define MU_GCR_GIR0_MASK                         (0x1U)
#define MU_GCR_GIR0_SHIFT                        (0U)
/*! GIR0 - MUB General Purpose Interrupt Request n
 *  0b0..MUB General Interrupt n is not requested to the MUA.
 *  0b1..MUB General Interrupt n is requested to the MUA.
 */
#define MU_GCR_GIR0(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR0_SHIFT)) & MU_GCR_GIR0_MASK)

#define MU_GCR_GIR1_MASK                         (0x2U)
#define MU_GCR_GIR1_SHIFT                        (1U)
/*! GIR1 - MUB General Purpose Interrupt Request n
 *  0b0..MUB General Interrupt n is not requested to the MUA.
 *  0b1..MUB General Interrupt n is requested to the MUA.
 */
#define MU_GCR_GIR1(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR1_SHIFT)) & MU_GCR_GIR1_MASK)

#define MU_GCR_GIR2_MASK                         (0x4U)
#define MU_GCR_GIR2_SHIFT                        (2U)
/*! GIR2 - MUB General Purpose Interrupt Request n
 *  0b0..MUB General Interrupt n is not requested to the MUA.
 *  0b1..MUB General Interrupt n is requested to the MUA.
 */
#define MU_GCR_GIR2(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR2_SHIFT)) & MU_GCR_GIR2_MASK)

#define MU_GCR_GIR3_MASK                         (0x8U)
#define MU_GCR_GIR3_SHIFT                        (3U)
/*! GIR3 - MUB General Purpose Interrupt Request n
 *  0b0..MUB General Interrupt n is not requested to the MUA.
 *  0b1..MUB General Interrupt n is requested to the MUA.
 */
#define MU_GCR_GIR3(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR3_SHIFT)) & MU_GCR_GIR3_MASK)
/*! @} */

/*! @name GSR - General Status Register */
/*! @{ */

#define MU_GSR_GIP0_MASK                         (0x1U)
#define MU_GSR_GIP0_SHIFT                        (0U)
/*! GIP0 - MUB General Interrupt Request Pending n
 *  0b0..MUB general purpose interrupt n is not pending.
 *  0b1..MUB general purpose interrupt n is pending.
 */
#define MU_GSR_GIP0(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP0_SHIFT)) & MU_GSR_GIP0_MASK)

#define MU_GSR_GIP1_MASK                         (0x2U)
#define MU_GSR_GIP1_SHIFT                        (1U)
/*! GIP1 - MUB General Interrupt Request Pending n
 *  0b0..MUB general purpose interrupt n is not pending.
 *  0b1..MUB general purpose interrupt n is pending.
 */
#define MU_GSR_GIP1(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP1_SHIFT)) & MU_GSR_GIP1_MASK)

#define MU_GSR_GIP2_MASK                         (0x4U)
#define MU_GSR_GIP2_SHIFT                        (2U)
/*! GIP2 - MUB General Interrupt Request Pending n
 *  0b0..MUB general purpose interrupt n is not pending.
 *  0b1..MUB general purpose interrupt n is pending.
 */
#define MU_GSR_GIP2(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP2_SHIFT)) & MU_GSR_GIP2_MASK)

#define MU_GSR_GIP3_MASK                         (0x8U)
#define MU_GSR_GIP3_SHIFT                        (3U)
/*! GIP3 - MUB General Interrupt Request Pending n
 *  0b0..MUB general purpose interrupt n is not pending.
 *  0b1..MUB general purpose interrupt n is pending.
 */
#define MU_GSR_GIP3(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP3_SHIFT)) & MU_GSR_GIP3_MASK)
/*! @} */

/*! @name TCR - Transmit Control Register */
/*! @{ */

#define MU_TCR_TIE0_MASK                         (0x1U)
#define MU_TCR_TIE0_SHIFT                        (0U)
/*! TIE0 - MUB Transmit Interrupt Enable n
 *  0b0..Disables MUB Transmit Interrupt n. (default)
 *  0b1..Enables MUB Transmit Interrupt n.
 */
#define MU_TCR_TIE0(x)                           (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE0_SHIFT)) & MU_TCR_TIE0_MASK)

#define MU_TCR_TIE1_MASK                         (0x2U)
#define MU_TCR_TIE1_SHIFT                        (1U)
/*! TIE1 - MUB Transmit Interrupt Enable n
 *  0b0..Disables MUB Transmit Interrupt n. (default)
 *  0b1..Enables MUB Transmit Interrupt n.
 */
#define MU_TCR_TIE1(x)                           (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE1_SHIFT)) & MU_TCR_TIE1_MASK)

#define MU_TCR_TIE2_MASK                         (0x4U)
#define MU_TCR_TIE2_SHIFT                        (2U)
/*! TIE2 - MUB Transmit Interrupt Enable n
 *  0b0..Disables MUB Transmit Interrupt n. (default)
 *  0b1..Enables MUB Transmit Interrupt n.
 */
#define MU_TCR_TIE2(x)                           (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE2_SHIFT)) & MU_TCR_TIE2_MASK)

#define MU_TCR_TIE3_MASK                         (0x8U)
#define MU_TCR_TIE3_SHIFT                        (3U)
/*! TIE3 - MUB Transmit Interrupt Enable n
 *  0b0..Disables MUB Transmit Interrupt n. (default)
 *  0b1..Enables MUB Transmit Interrupt n.
 */
#define MU_TCR_TIE3(x)                           (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE3_SHIFT)) & MU_TCR_TIE3_MASK)
/*! @} */

/*! @name TSR - Transmit Status Register */
/*! @{ */

#define MU_TSR_TE0_MASK                          (0x1U)
#define MU_TSR_TE0_SHIFT                         (0U)
/*! TE0 - MUB Transmit Register n Empty
 *  0b0..MUB TRn register is not empty.
 *  0b1..MUB TRn register is empty.
 */
#define MU_TSR_TE0(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE0_SHIFT)) & MU_TSR_TE0_MASK)

#define MU_TSR_TE1_MASK                          (0x2U)
#define MU_TSR_TE1_SHIFT                         (1U)
/*! TE1 - MUB Transmit Register n Empty
 *  0b0..MUB TRn register is not empty.
 *  0b1..MUB TRn register is empty.
 */
#define MU_TSR_TE1(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE1_SHIFT)) & MU_TSR_TE1_MASK)

#define MU_TSR_TE2_MASK                          (0x4U)
#define MU_TSR_TE2_SHIFT                         (2U)
/*! TE2 - MUB Transmit Register n Empty
 *  0b0..MUB TRn register is not empty.
 *  0b1..MUB TRn register is empty.
 */
#define MU_TSR_TE2(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE2_SHIFT)) & MU_TSR_TE2_MASK)

#define MU_TSR_TE3_MASK                          (0x8U)
#define MU_TSR_TE3_SHIFT                         (3U)
/*! TE3 - MUB Transmit Register n Empty
 *  0b0..MUB TRn register is not empty.
 *  0b1..MUB TRn register is empty.
 */
#define MU_TSR_TE3(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE3_SHIFT)) & MU_TSR_TE3_MASK)
/*! @} */

/*! @name RCR - Receive Control Register */
/*! @{ */

#define MU_RCR_RIE0_MASK                         (0x1U)
#define MU_RCR_RIE0_SHIFT                        (0U)
/*! RIE0 - MUB Receive Interrupt Enable n
 *  0b0..Disables MUB Receive Interrupt n.
 *  0b1..Enables MUB Receive Interrupt n.
 */
#define MU_RCR_RIE0(x)                           (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE0_SHIFT)) & MU_RCR_RIE0_MASK)

#define MU_RCR_RIE1_MASK                         (0x2U)
#define MU_RCR_RIE1_SHIFT                        (1U)
/*! RIE1 - MUB Receive Interrupt Enable n
 *  0b0..Disables MUB Receive Interrupt n.
 *  0b1..Enables MUB Receive Interrupt n.
 */
#define MU_RCR_RIE1(x)                           (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE1_SHIFT)) & MU_RCR_RIE1_MASK)

#define MU_RCR_RIE2_MASK                         (0x4U)
#define MU_RCR_RIE2_SHIFT                        (2U)
/*! RIE2 - MUB Receive Interrupt Enable n
 *  0b0..Disables MUB Receive Interrupt n.
 *  0b1..Enables MUB Receive Interrupt n.
 */
#define MU_RCR_RIE2(x)                           (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE2_SHIFT)) & MU_RCR_RIE2_MASK)

#define MU_RCR_RIE3_MASK                         (0x8U)
#define MU_RCR_RIE3_SHIFT                        (3U)
/*! RIE3 - MUB Receive Interrupt Enable n
 *  0b0..Disables MUB Receive Interrupt n.
 *  0b1..Enables MUB Receive Interrupt n.
 */
#define MU_RCR_RIE3(x)                           (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE3_SHIFT)) & MU_RCR_RIE3_MASK)
/*! @} */

/*! @name RSR - Receive Status Register */
/*! @{ */

#define MU_RSR_RF0_MASK                          (0x1U)
#define MU_RSR_RF0_SHIFT                         (0U)
/*! RF0 - MUB Receive Register n Full
 *  0b0..MUB RRn register is not full.
 *  0b1..MUB RRn register has received data from MUA TRn register and is ready to be read by the MUB.
 */
#define MU_RSR_RF0(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF0_SHIFT)) & MU_RSR_RF0_MASK)

#define MU_RSR_RF1_MASK                          (0x2U)
#define MU_RSR_RF1_SHIFT                         (1U)
/*! RF1 - MUB Receive Register n Full
 *  0b0..MUB RRn register is not full.
 *  0b1..MUB RRn register has received data from MUA TRn register and is ready to be read by the MUB.
 */
#define MU_RSR_RF1(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF1_SHIFT)) & MU_RSR_RF1_MASK)

#define MU_RSR_RF2_MASK                          (0x4U)
#define MU_RSR_RF2_SHIFT                         (2U)
/*! RF2 - MUB Receive Register n Full
 *  0b0..MUB RRn register is not full.
 *  0b1..MUB RRn register has received data from MUA TRn register and is ready to be read by the MUB.
 */
#define MU_RSR_RF2(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF2_SHIFT)) & MU_RSR_RF2_MASK)

#define MU_RSR_RF3_MASK                          (0x8U)
#define MU_RSR_RF3_SHIFT                         (3U)
/*! RF3 - MUB Receive Register n Full
 *  0b0..MUB RRn register is not full.
 *  0b1..MUB RRn register has received data from MUA TRn register and is ready to be read by the MUB.
 */
#define MU_RSR_RF3(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF3_SHIFT)) & MU_RSR_RF3_MASK)
/*! @} */

/*! @name TR - Transmit Register */
/*! @{ */

#define MU_TR_TR_DATA_MASK                       (0xFFFFFFFFU)
#define MU_TR_TR_DATA_SHIFT                      (0U)
/*! TR_DATA - MUB Transmit Data */
#define MU_TR_TR_DATA(x)                         (((uint32_t)(((uint32_t)(x)) << MU_TR_TR_DATA_SHIFT)) & MU_TR_TR_DATA_MASK)
/*! @} */

/* The count of MU_TR */
#define MU_TR_COUNT                              (4U)

/*! @name RR - Receive Register */
/*! @{ */

#define MU_RR_RR_DATA_MASK                       (0xFFFFFFFFU)
#define MU_RR_RR_DATA_SHIFT                      (0U)
/*! RR_DATA - MUB Receive Data */
#define MU_RR_RR_DATA(x)                         (((uint32_t)(((uint32_t)(x)) << MU_RR_RR_DATA_SHIFT)) & MU_RR_RR_DATA_MASK)
/*! @} */

/* The count of MU_RR */
#define MU_RR_COUNT                              (4U)


/*!
 * @}
 */ /* end of group MU_Register_Masks */


/* MU - Peripheral instance base addresses */
/** Peripheral MU2_MUB base address */
#define MU2_MUB_BASE                             (0x2DA10000u)
/** Peripheral MU2_MUB base pointer */
#define MU2_MUB                                  ((MU_Type *)MU2_MUB_BASE)
/** Peripheral MU3_MUB base address */
#define MU3_MUB_BASE                             (0x2DA20000u)
/** Peripheral MU3_MUB base pointer */
#define MU3_MUB                                  ((MU_Type *)MU3_MUB_BASE)
/** Array initializer of MU peripheral base addresses */
#define MU_BASE_ADDRS                            { MU2_MUB_BASE, MU3_MUB_BASE }
/** Array initializer of MU peripheral base pointers */
#define MU_BASE_PTRS                             { MU2_MUB, MU3_MUB }
/** Interrupt vectors for the MU peripheral type */
#define MU_IRQS                                  { MU2_B_IRQn, MU3_B_IRQn }

/*!
 * @}
 */ /* end of group MU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PCC0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PCC0_Peripheral_Access_Layer PCC0 Peripheral Access Layer
 * @{
 */

/** PCC0 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[4];
  __IO uint32_t PCC_DMA0_MP;                       /**< PCC DMA0_MP Register, offset: 0x4 */
  __IO uint32_t PCC_DMA0_CH0;                      /**< PCC DMA0_CH0 Register, offset: 0x8 */
  __IO uint32_t PCC_DMA0_CH1;                      /**< PCC DMA0_CH1 Register, offset: 0xC */
  __IO uint32_t PCC_DMA0_CH2;                      /**< PCC DMA0_CH2 Register, offset: 0x10 */
  __IO uint32_t PCC_DMA0_CH3;                      /**< PCC DMA0_CH3 Register, offset: 0x14 */
  __IO uint32_t PCC_DMA0_CH4;                      /**< PCC DMA0_CH4 Register, offset: 0x18 */
  __IO uint32_t PCC_DMA0_CH5;                      /**< PCC DMA0_CH5 Register, offset: 0x1C */
  __IO uint32_t PCC_DMA0_CH6;                      /**< PCC DMA0_CH6 Register, offset: 0x20 */
  __IO uint32_t PCC_DMA0_CH7;                      /**< PCC DMA0_CH7 Register, offset: 0x24 */
  __IO uint32_t PCC_DMA0_CH8;                      /**< PCC DMA0_CH8 Register, offset: 0x28 */
  __IO uint32_t PCC_DMA0_CH9;                      /**< PCC DMA0_CH9 Register, offset: 0x2C */
  __IO uint32_t PCC_DMA0_CH10;                     /**< PCC DMA0_CH10 Register, offset: 0x30 */
  __IO uint32_t PCC_DMA0_CH11;                     /**< PCC DMA0_CH11 Register, offset: 0x34 */
  __IO uint32_t PCC_DMA0_CH12;                     /**< PCC DMA0_CH12 Register, offset: 0x38 */
  __IO uint32_t PCC_DMA0_CH13;                     /**< PCC DMA0_CH13 Register, offset: 0x3C */
  __IO uint32_t PCC_DMA0_CH14;                     /**< PCC DMA0_CH14 Register, offset: 0x40 */
  __IO uint32_t PCC_DMA0_CH15;                     /**< PCC DMA0_CH15 Register, offset: 0x44 */
  __IO uint32_t PCC_DMA0_CH16;                     /**< PCC DMA0_CH16 Register, offset: 0x48 */
  __IO uint32_t PCC_DMA0_CH17;                     /**< PCC DMA0_CH17 Register, offset: 0x4C */
  __IO uint32_t PCC_DMA0_CH18;                     /**< PCC DMA0_CH18 Register, offset: 0x50 */
  __IO uint32_t PCC_DMA0_CH19;                     /**< PCC DMA0_CH19 Register, offset: 0x54 */
  __IO uint32_t PCC_DMA0_CH20;                     /**< PCC DMA0_CH20 Register, offset: 0x58 */
  __IO uint32_t PCC_DMA0_CH21;                     /**< PCC DMA0_CH21 Register, offset: 0x5C */
  __IO uint32_t PCC_DMA0_CH22;                     /**< PCC DMA0_CH22 Register, offset: 0x60 */
  __IO uint32_t PCC_DMA0_CH23;                     /**< PCC DMA0_CH23 Register, offset: 0x64 */
  __IO uint32_t PCC_DMA0_CH24;                     /**< PCC DMA0_CH24 Register, offset: 0x68 */
  __IO uint32_t PCC_DMA0_CH25;                     /**< PCC DMA0_CH25 Register, offset: 0x6C */
  __IO uint32_t PCC_DMA0_CH26;                     /**< PCC DMA0_CH26 Register, offset: 0x70 */
  __IO uint32_t PCC_DMA0_CH27;                     /**< PCC DMA0_CH27 Register, offset: 0x74 */
  __IO uint32_t PCC_DMA0_CH28;                     /**< PCC DMA0_CH28 Register, offset: 0x78 */
  __IO uint32_t PCC_DMA0_CH29;                     /**< PCC DMA0_CH29 Register, offset: 0x7C */
  __IO uint32_t PCC_DMA0_CH30;                     /**< PCC DMA0_CH30 Register, offset: 0x80 */
  __IO uint32_t PCC_DMA0_CH31;                     /**< PCC DMA0_CH31 Register, offset: 0x84 */
  __IO uint32_t PCC_MU0_A;                         /**< PCC MU0_A Register, offset: 0x88 */
  __IO uint32_t PCC_MU1_A;                         /**< PCC MU1_A Register, offset: 0x8C */
  __IO uint32_t PCC_MU2_A;                         /**< PCC MU2_A Register, offset: 0x90 */
       uint8_t RESERVED_1[4];
  __IO uint32_t PCC_SYSPM0;                        /**< PCC SYSPM0 Register, offset: 0x98 */
       uint8_t RESERVED_2[4];
  __IO uint32_t PCC_WUU0;                          /**< PCC WUU0 Register, offset: 0xA0 */
  __IO uint32_t PCC_UPOWER_MUA_RTD;                /**< PCC uPower_MUA_RTD Register, offset: 0xA4 */
       uint8_t RESERVED_3[8];
  __IO uint32_t PCC_WDOG0;                         /**< PCC WDOG0 Register, offset: 0xB0 */
  __IO uint32_t PCC_WDOG1;                         /**< PCC WDOG1 Register, offset: 0xB4 */
       uint8_t RESERVED_4[12];
  __IO uint32_t PCC_TRDC_MGR;                      /**< PCC TRDC_MGR Register, offset: 0xC4 */
  __IO uint32_t PCC_TRDC_MBC0;                     /**< PCC TRDC_MBC0 Register, offset: 0xC8 */
  __IO uint32_t PCC_TRDC_MBC1;                     /**< PCC TRDC_MBC1 Register, offset: 0xCC */
  __IO uint32_t PCC_TRDC_MBC2;                     /**< PCC TRDC_MBC2 Register, offset: 0xD0 */
  __IO uint32_t PCC_TRDC_MBC3;                     /**< PCC TRDC_MBC3 Register, offset: 0xD4 */
  __IO uint32_t PCC_TRDC_MRC;                      /**< PCC TRDC_MRC Register, offset: 0xD8 */
  __IO uint32_t PCC_SEMA42_0;                      /**< PCC SEMA42_0 Register, offset: 0xDC */
  __IO uint32_t PCC_BBNSM;                         /**< PCC BBNSM Register, offset: 0xE0 */
  __IO uint32_t PCC_FLEXSPI0;                      /**< PCC FlexSPI0 Register, offset: 0xE4 */
  __IO uint32_t PCC_ROMCP0;                        /**< PCC ROMCP0 Register, offset: 0xE8 */
  __IO uint32_t PCC_LPIT0;                         /**< PCC LPIT0 Register, offset: 0xEC */
  __IO uint32_t PCC_FLEXIO0;                       /**< PCC FlexIO0 Register, offset: 0xF0 */
  __IO uint32_t PCC_I3C0;                          /**< PCC I3C0 Register, offset: 0xF4 */
  __IO uint32_t PCC_LPSPI0;                        /**< PCC LPSPI0 Register, offset: 0xF8 */
  __IO uint32_t PCC_LPSPI1;                        /**< PCC LPSPI1 Register, offset: 0xFC */
  __IO uint32_t PCC_ADC0;                          /**< PCC ADC0 Register, offset: 0x100 */
  __IO uint32_t PCC_CMP0;                          /**< PCC CMP0 Register, offset: 0x104 */
  __IO uint32_t PCC_CMP1;                          /**< PCC CMP1 Register, offset: 0x108 */
  __IO uint32_t PCC_DAC0;                          /**< PCC DAC0 Register, offset: 0x10C */
  __IO uint32_t PCC_DAC1;                          /**< PCC DAC1 Register, offset: 0x110 */
       uint8_t RESERVED_5[4];
  __IO uint32_t PCC_CM33_CACHE_CONTROLLER;         /**< PCC CM33_Cache_Controller Register, offset: 0x118 */
       uint8_t RESERVED_6[20];
  __IO uint32_t PCC_S400_LPUART;                   /**< PCC S400_LPUART Register, offset: 0x130 */
       uint8_t RESERVED_7[4];
  __IO uint32_t PCC_POWERSYS_WDOG;                 /**< PCC Powersys_WDOG Register, offset: 0x138 */
  __IO uint32_t PCC_OCOTP;                         /**< PCC OCOTP Register, offset: 0x13C */
} PCC0_Type;

/* ----------------------------------------------------------------------------
   -- PCC0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PCC0_Register_Masks PCC0 Register Masks
 * @{
 */

/*! @name PCC_DMA0_MP - PCC DMA0_MP Register */
/*! @{ */

#define PCC0_PCC_DMA0_MP_SSADO_MASK              (0xC00000U)
#define PCC0_PCC_DMA0_MP_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_MP_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_MP_SSADO_SHIFT)) & PCC0_PCC_DMA0_MP_SSADO_MASK)

#define PCC0_PCC_DMA0_MP_CGC_MASK                (0x40000000U)
#define PCC0_PCC_DMA0_MP_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_MP_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_MP_CGC_SHIFT)) & PCC0_PCC_DMA0_MP_CGC_MASK)

#define PCC0_PCC_DMA0_MP_PR_MASK                 (0x80000000U)
#define PCC0_PCC_DMA0_MP_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_MP_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_MP_PR_SHIFT)) & PCC0_PCC_DMA0_MP_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH0 - PCC DMA0_CH0 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH0_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_DMA0_CH0_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH0_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH0_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH0_SSADO_MASK)

#define PCC0_PCC_DMA0_CH0_CGC_MASK               (0x40000000U)
#define PCC0_PCC_DMA0_CH0_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH0_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH0_CGC_SHIFT)) & PCC0_PCC_DMA0_CH0_CGC_MASK)

#define PCC0_PCC_DMA0_CH0_PR_MASK                (0x80000000U)
#define PCC0_PCC_DMA0_CH0_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH0_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH0_PR_SHIFT)) & PCC0_PCC_DMA0_CH0_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH1 - PCC DMA0_CH1 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH1_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_DMA0_CH1_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH1_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH1_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH1_SSADO_MASK)

#define PCC0_PCC_DMA0_CH1_CGC_MASK               (0x40000000U)
#define PCC0_PCC_DMA0_CH1_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH1_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH1_CGC_SHIFT)) & PCC0_PCC_DMA0_CH1_CGC_MASK)

#define PCC0_PCC_DMA0_CH1_PR_MASK                (0x80000000U)
#define PCC0_PCC_DMA0_CH1_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH1_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH1_PR_SHIFT)) & PCC0_PCC_DMA0_CH1_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH2 - PCC DMA0_CH2 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH2_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_DMA0_CH2_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH2_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH2_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH2_SSADO_MASK)

#define PCC0_PCC_DMA0_CH2_CGC_MASK               (0x40000000U)
#define PCC0_PCC_DMA0_CH2_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH2_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH2_CGC_SHIFT)) & PCC0_PCC_DMA0_CH2_CGC_MASK)

#define PCC0_PCC_DMA0_CH2_PR_MASK                (0x80000000U)
#define PCC0_PCC_DMA0_CH2_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH2_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH2_PR_SHIFT)) & PCC0_PCC_DMA0_CH2_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH3 - PCC DMA0_CH3 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH3_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_DMA0_CH3_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH3_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH3_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH3_SSADO_MASK)

#define PCC0_PCC_DMA0_CH3_CGC_MASK               (0x40000000U)
#define PCC0_PCC_DMA0_CH3_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH3_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH3_CGC_SHIFT)) & PCC0_PCC_DMA0_CH3_CGC_MASK)

#define PCC0_PCC_DMA0_CH3_PR_MASK                (0x80000000U)
#define PCC0_PCC_DMA0_CH3_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH3_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH3_PR_SHIFT)) & PCC0_PCC_DMA0_CH3_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH4 - PCC DMA0_CH4 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH4_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_DMA0_CH4_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH4_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH4_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH4_SSADO_MASK)

#define PCC0_PCC_DMA0_CH4_CGC_MASK               (0x40000000U)
#define PCC0_PCC_DMA0_CH4_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH4_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH4_CGC_SHIFT)) & PCC0_PCC_DMA0_CH4_CGC_MASK)

#define PCC0_PCC_DMA0_CH4_PR_MASK                (0x80000000U)
#define PCC0_PCC_DMA0_CH4_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH4_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH4_PR_SHIFT)) & PCC0_PCC_DMA0_CH4_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH5 - PCC DMA0_CH5 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH5_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_DMA0_CH5_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH5_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH5_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH5_SSADO_MASK)

#define PCC0_PCC_DMA0_CH5_CGC_MASK               (0x40000000U)
#define PCC0_PCC_DMA0_CH5_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH5_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH5_CGC_SHIFT)) & PCC0_PCC_DMA0_CH5_CGC_MASK)

#define PCC0_PCC_DMA0_CH5_PR_MASK                (0x80000000U)
#define PCC0_PCC_DMA0_CH5_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH5_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH5_PR_SHIFT)) & PCC0_PCC_DMA0_CH5_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH6 - PCC DMA0_CH6 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH6_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_DMA0_CH6_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH6_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH6_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH6_SSADO_MASK)

#define PCC0_PCC_DMA0_CH6_CGC_MASK               (0x40000000U)
#define PCC0_PCC_DMA0_CH6_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH6_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH6_CGC_SHIFT)) & PCC0_PCC_DMA0_CH6_CGC_MASK)

#define PCC0_PCC_DMA0_CH6_PR_MASK                (0x80000000U)
#define PCC0_PCC_DMA0_CH6_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH6_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH6_PR_SHIFT)) & PCC0_PCC_DMA0_CH6_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH7 - PCC DMA0_CH7 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH7_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_DMA0_CH7_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH7_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH7_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH7_SSADO_MASK)

#define PCC0_PCC_DMA0_CH7_CGC_MASK               (0x40000000U)
#define PCC0_PCC_DMA0_CH7_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH7_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH7_CGC_SHIFT)) & PCC0_PCC_DMA0_CH7_CGC_MASK)

#define PCC0_PCC_DMA0_CH7_PR_MASK                (0x80000000U)
#define PCC0_PCC_DMA0_CH7_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH7_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH7_PR_SHIFT)) & PCC0_PCC_DMA0_CH7_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH8 - PCC DMA0_CH8 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH8_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_DMA0_CH8_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH8_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH8_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH8_SSADO_MASK)

#define PCC0_PCC_DMA0_CH8_CGC_MASK               (0x40000000U)
#define PCC0_PCC_DMA0_CH8_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH8_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH8_CGC_SHIFT)) & PCC0_PCC_DMA0_CH8_CGC_MASK)

#define PCC0_PCC_DMA0_CH8_PR_MASK                (0x80000000U)
#define PCC0_PCC_DMA0_CH8_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH8_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH8_PR_SHIFT)) & PCC0_PCC_DMA0_CH8_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH9 - PCC DMA0_CH9 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH9_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_DMA0_CH9_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH9_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH9_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH9_SSADO_MASK)

#define PCC0_PCC_DMA0_CH9_CGC_MASK               (0x40000000U)
#define PCC0_PCC_DMA0_CH9_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH9_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH9_CGC_SHIFT)) & PCC0_PCC_DMA0_CH9_CGC_MASK)

#define PCC0_PCC_DMA0_CH9_PR_MASK                (0x80000000U)
#define PCC0_PCC_DMA0_CH9_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH9_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH9_PR_SHIFT)) & PCC0_PCC_DMA0_CH9_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH10 - PCC DMA0_CH10 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH10_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH10_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH10_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH10_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH10_SSADO_MASK)

#define PCC0_PCC_DMA0_CH10_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH10_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH10_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH10_CGC_SHIFT)) & PCC0_PCC_DMA0_CH10_CGC_MASK)

#define PCC0_PCC_DMA0_CH10_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH10_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH10_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH10_PR_SHIFT)) & PCC0_PCC_DMA0_CH10_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH11 - PCC DMA0_CH11 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH11_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH11_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH11_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH11_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH11_SSADO_MASK)

#define PCC0_PCC_DMA0_CH11_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH11_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH11_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH11_CGC_SHIFT)) & PCC0_PCC_DMA0_CH11_CGC_MASK)

#define PCC0_PCC_DMA0_CH11_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH11_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH11_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH11_PR_SHIFT)) & PCC0_PCC_DMA0_CH11_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH12 - PCC DMA0_CH12 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH12_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH12_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH12_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH12_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH12_SSADO_MASK)

#define PCC0_PCC_DMA0_CH12_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH12_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH12_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH12_CGC_SHIFT)) & PCC0_PCC_DMA0_CH12_CGC_MASK)

#define PCC0_PCC_DMA0_CH12_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH12_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH12_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH12_PR_SHIFT)) & PCC0_PCC_DMA0_CH12_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH13 - PCC DMA0_CH13 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH13_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH13_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH13_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH13_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH13_SSADO_MASK)

#define PCC0_PCC_DMA0_CH13_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH13_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH13_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH13_CGC_SHIFT)) & PCC0_PCC_DMA0_CH13_CGC_MASK)

#define PCC0_PCC_DMA0_CH13_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH13_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH13_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH13_PR_SHIFT)) & PCC0_PCC_DMA0_CH13_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH14 - PCC DMA0_CH14 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH14_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH14_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH14_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH14_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH14_SSADO_MASK)

#define PCC0_PCC_DMA0_CH14_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH14_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH14_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH14_CGC_SHIFT)) & PCC0_PCC_DMA0_CH14_CGC_MASK)

#define PCC0_PCC_DMA0_CH14_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH14_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH14_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH14_PR_SHIFT)) & PCC0_PCC_DMA0_CH14_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH15 - PCC DMA0_CH15 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH15_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH15_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH15_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH15_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH15_SSADO_MASK)

#define PCC0_PCC_DMA0_CH15_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH15_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH15_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH15_CGC_SHIFT)) & PCC0_PCC_DMA0_CH15_CGC_MASK)

#define PCC0_PCC_DMA0_CH15_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH15_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH15_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH15_PR_SHIFT)) & PCC0_PCC_DMA0_CH15_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH16 - PCC DMA0_CH16 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH16_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH16_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH16_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH16_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH16_SSADO_MASK)

#define PCC0_PCC_DMA0_CH16_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH16_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH16_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH16_CGC_SHIFT)) & PCC0_PCC_DMA0_CH16_CGC_MASK)

#define PCC0_PCC_DMA0_CH16_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH16_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH16_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH16_PR_SHIFT)) & PCC0_PCC_DMA0_CH16_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH17 - PCC DMA0_CH17 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH17_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH17_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH17_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH17_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH17_SSADO_MASK)

#define PCC0_PCC_DMA0_CH17_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH17_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH17_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH17_CGC_SHIFT)) & PCC0_PCC_DMA0_CH17_CGC_MASK)

#define PCC0_PCC_DMA0_CH17_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH17_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH17_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH17_PR_SHIFT)) & PCC0_PCC_DMA0_CH17_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH18 - PCC DMA0_CH18 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH18_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH18_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH18_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH18_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH18_SSADO_MASK)

#define PCC0_PCC_DMA0_CH18_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH18_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH18_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH18_CGC_SHIFT)) & PCC0_PCC_DMA0_CH18_CGC_MASK)

#define PCC0_PCC_DMA0_CH18_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH18_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH18_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH18_PR_SHIFT)) & PCC0_PCC_DMA0_CH18_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH19 - PCC DMA0_CH19 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH19_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH19_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH19_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH19_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH19_SSADO_MASK)

#define PCC0_PCC_DMA0_CH19_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH19_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH19_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH19_CGC_SHIFT)) & PCC0_PCC_DMA0_CH19_CGC_MASK)

#define PCC0_PCC_DMA0_CH19_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH19_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH19_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH19_PR_SHIFT)) & PCC0_PCC_DMA0_CH19_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH20 - PCC DMA0_CH20 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH20_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH20_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH20_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH20_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH20_SSADO_MASK)

#define PCC0_PCC_DMA0_CH20_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH20_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH20_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH20_CGC_SHIFT)) & PCC0_PCC_DMA0_CH20_CGC_MASK)

#define PCC0_PCC_DMA0_CH20_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH20_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH20_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH20_PR_SHIFT)) & PCC0_PCC_DMA0_CH20_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH21 - PCC DMA0_CH21 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH21_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH21_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH21_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH21_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH21_SSADO_MASK)

#define PCC0_PCC_DMA0_CH21_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH21_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH21_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH21_CGC_SHIFT)) & PCC0_PCC_DMA0_CH21_CGC_MASK)

#define PCC0_PCC_DMA0_CH21_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH21_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH21_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH21_PR_SHIFT)) & PCC0_PCC_DMA0_CH21_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH22 - PCC DMA0_CH22 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH22_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH22_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH22_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH22_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH22_SSADO_MASK)

#define PCC0_PCC_DMA0_CH22_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH22_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH22_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH22_CGC_SHIFT)) & PCC0_PCC_DMA0_CH22_CGC_MASK)

#define PCC0_PCC_DMA0_CH22_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH22_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH22_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH22_PR_SHIFT)) & PCC0_PCC_DMA0_CH22_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH23 - PCC DMA0_CH23 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH23_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH23_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH23_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH23_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH23_SSADO_MASK)

#define PCC0_PCC_DMA0_CH23_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH23_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH23_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH23_CGC_SHIFT)) & PCC0_PCC_DMA0_CH23_CGC_MASK)

#define PCC0_PCC_DMA0_CH23_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH23_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH23_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH23_PR_SHIFT)) & PCC0_PCC_DMA0_CH23_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH24 - PCC DMA0_CH24 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH24_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH24_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH24_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH24_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH24_SSADO_MASK)

#define PCC0_PCC_DMA0_CH24_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH24_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH24_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH24_CGC_SHIFT)) & PCC0_PCC_DMA0_CH24_CGC_MASK)

#define PCC0_PCC_DMA0_CH24_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH24_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH24_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH24_PR_SHIFT)) & PCC0_PCC_DMA0_CH24_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH25 - PCC DMA0_CH25 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH25_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH25_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH25_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH25_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH25_SSADO_MASK)

#define PCC0_PCC_DMA0_CH25_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH25_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH25_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH25_CGC_SHIFT)) & PCC0_PCC_DMA0_CH25_CGC_MASK)

#define PCC0_PCC_DMA0_CH25_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH25_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH25_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH25_PR_SHIFT)) & PCC0_PCC_DMA0_CH25_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH26 - PCC DMA0_CH26 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH26_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH26_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH26_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH26_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH26_SSADO_MASK)

#define PCC0_PCC_DMA0_CH26_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH26_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH26_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH26_CGC_SHIFT)) & PCC0_PCC_DMA0_CH26_CGC_MASK)

#define PCC0_PCC_DMA0_CH26_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH26_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH26_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH26_PR_SHIFT)) & PCC0_PCC_DMA0_CH26_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH27 - PCC DMA0_CH27 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH27_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH27_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH27_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH27_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH27_SSADO_MASK)

#define PCC0_PCC_DMA0_CH27_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH27_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH27_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH27_CGC_SHIFT)) & PCC0_PCC_DMA0_CH27_CGC_MASK)

#define PCC0_PCC_DMA0_CH27_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH27_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH27_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH27_PR_SHIFT)) & PCC0_PCC_DMA0_CH27_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH28 - PCC DMA0_CH28 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH28_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH28_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH28_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH28_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH28_SSADO_MASK)

#define PCC0_PCC_DMA0_CH28_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH28_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH28_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH28_CGC_SHIFT)) & PCC0_PCC_DMA0_CH28_CGC_MASK)

#define PCC0_PCC_DMA0_CH28_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH28_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH28_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH28_PR_SHIFT)) & PCC0_PCC_DMA0_CH28_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH29 - PCC DMA0_CH29 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH29_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH29_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH29_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH29_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH29_SSADO_MASK)

#define PCC0_PCC_DMA0_CH29_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH29_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH29_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH29_CGC_SHIFT)) & PCC0_PCC_DMA0_CH29_CGC_MASK)

#define PCC0_PCC_DMA0_CH29_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH29_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH29_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH29_PR_SHIFT)) & PCC0_PCC_DMA0_CH29_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH30 - PCC DMA0_CH30 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH30_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH30_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH30_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH30_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH30_SSADO_MASK)

#define PCC0_PCC_DMA0_CH30_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH30_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH30_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH30_CGC_SHIFT)) & PCC0_PCC_DMA0_CH30_CGC_MASK)

#define PCC0_PCC_DMA0_CH30_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH30_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH30_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH30_PR_SHIFT)) & PCC0_PCC_DMA0_CH30_PR_MASK)
/*! @} */

/*! @name PCC_DMA0_CH31 - PCC DMA0_CH31 Register */
/*! @{ */

#define PCC0_PCC_DMA0_CH31_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_DMA0_CH31_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DMA0_CH31_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH31_SSADO_SHIFT)) & PCC0_PCC_DMA0_CH31_SSADO_MASK)

#define PCC0_PCC_DMA0_CH31_CGC_MASK              (0x40000000U)
#define PCC0_PCC_DMA0_CH31_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DMA0_CH31_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH31_CGC_SHIFT)) & PCC0_PCC_DMA0_CH31_CGC_MASK)

#define PCC0_PCC_DMA0_CH31_PR_MASK               (0x80000000U)
#define PCC0_PCC_DMA0_CH31_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DMA0_CH31_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CH31_PR_SHIFT)) & PCC0_PCC_DMA0_CH31_PR_MASK)
/*! @} */

/*! @name PCC_MU0_A - PCC MU0_A Register */
/*! @{ */

#define PCC0_PCC_MU0_A_SSADO_MASK                (0xC00000U)
#define PCC0_PCC_MU0_A_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_MU0_A_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_MU0_A_SSADO_SHIFT)) & PCC0_PCC_MU0_A_SSADO_MASK)

#define PCC0_PCC_MU0_A_CGC_MASK                  (0x40000000U)
#define PCC0_PCC_MU0_A_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_MU0_A_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_MU0_A_CGC_SHIFT)) & PCC0_PCC_MU0_A_CGC_MASK)

#define PCC0_PCC_MU0_A_PR_MASK                   (0x80000000U)
#define PCC0_PCC_MU0_A_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_MU0_A_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_MU0_A_PR_SHIFT)) & PCC0_PCC_MU0_A_PR_MASK)
/*! @} */

/*! @name PCC_MU1_A - PCC MU1_A Register */
/*! @{ */

#define PCC0_PCC_MU1_A_SSADO_MASK                (0xC00000U)
#define PCC0_PCC_MU1_A_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_MU1_A_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_MU1_A_SSADO_SHIFT)) & PCC0_PCC_MU1_A_SSADO_MASK)

#define PCC0_PCC_MU1_A_CGC_MASK                  (0x40000000U)
#define PCC0_PCC_MU1_A_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_MU1_A_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_MU1_A_CGC_SHIFT)) & PCC0_PCC_MU1_A_CGC_MASK)

#define PCC0_PCC_MU1_A_PR_MASK                   (0x80000000U)
#define PCC0_PCC_MU1_A_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_MU1_A_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_MU1_A_PR_SHIFT)) & PCC0_PCC_MU1_A_PR_MASK)
/*! @} */

/*! @name PCC_MU2_A - PCC MU2_A Register */
/*! @{ */

#define PCC0_PCC_MU2_A_SSADO_MASK                (0xC00000U)
#define PCC0_PCC_MU2_A_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_MU2_A_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_MU2_A_SSADO_SHIFT)) & PCC0_PCC_MU2_A_SSADO_MASK)

#define PCC0_PCC_MU2_A_CGC_MASK                  (0x40000000U)
#define PCC0_PCC_MU2_A_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_MU2_A_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_MU2_A_CGC_SHIFT)) & PCC0_PCC_MU2_A_CGC_MASK)

#define PCC0_PCC_MU2_A_PR_MASK                   (0x80000000U)
#define PCC0_PCC_MU2_A_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_MU2_A_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_MU2_A_PR_SHIFT)) & PCC0_PCC_MU2_A_PR_MASK)
/*! @} */

/*! @name PCC_SYSPM0 - PCC SYSPM0 Register */
/*! @{ */

#define PCC0_PCC_SYSPM0_SSADO_MASK               (0xC00000U)
#define PCC0_PCC_SYSPM0_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_SYSPM0_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SYSPM0_SSADO_SHIFT)) & PCC0_PCC_SYSPM0_SSADO_MASK)

#define PCC0_PCC_SYSPM0_CGC_MASK                 (0x40000000U)
#define PCC0_PCC_SYSPM0_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_SYSPM0_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SYSPM0_CGC_SHIFT)) & PCC0_PCC_SYSPM0_CGC_MASK)

#define PCC0_PCC_SYSPM0_PR_MASK                  (0x80000000U)
#define PCC0_PCC_SYSPM0_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_SYSPM0_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SYSPM0_PR_SHIFT)) & PCC0_PCC_SYSPM0_PR_MASK)
/*! @} */

/*! @name PCC_WUU0 - PCC WUU0 Register */
/*! @{ */

#define PCC0_PCC_WUU0_SSADO_MASK                 (0xC00000U)
#define PCC0_PCC_WUU0_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_WUU0_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WUU0_SSADO_SHIFT)) & PCC0_PCC_WUU0_SSADO_MASK)

#define PCC0_PCC_WUU0_CGC_MASK                   (0x40000000U)
#define PCC0_PCC_WUU0_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_WUU0_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WUU0_CGC_SHIFT)) & PCC0_PCC_WUU0_CGC_MASK)

#define PCC0_PCC_WUU0_PR_MASK                    (0x80000000U)
#define PCC0_PCC_WUU0_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_WUU0_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WUU0_PR_SHIFT)) & PCC0_PCC_WUU0_PR_MASK)
/*! @} */

/*! @name PCC_UPOWER_MUA_RTD - PCC uPower_MUA_RTD Register */
/*! @{ */

#define PCC0_PCC_UPOWER_MUA_RTD_SSADO_MASK       (0xC00000U)
#define PCC0_PCC_UPOWER_MUA_RTD_SSADO_SHIFT      (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_UPOWER_MUA_RTD_SSADO(x)         (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_UPOWER_MUA_RTD_SSADO_SHIFT)) & PCC0_PCC_UPOWER_MUA_RTD_SSADO_MASK)

#define PCC0_PCC_UPOWER_MUA_RTD_CGC_MASK         (0x40000000U)
#define PCC0_PCC_UPOWER_MUA_RTD_CGC_SHIFT        (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_UPOWER_MUA_RTD_CGC(x)           (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_UPOWER_MUA_RTD_CGC_SHIFT)) & PCC0_PCC_UPOWER_MUA_RTD_CGC_MASK)

#define PCC0_PCC_UPOWER_MUA_RTD_PR_MASK          (0x80000000U)
#define PCC0_PCC_UPOWER_MUA_RTD_PR_SHIFT         (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_UPOWER_MUA_RTD_PR(x)            (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_UPOWER_MUA_RTD_PR_SHIFT)) & PCC0_PCC_UPOWER_MUA_RTD_PR_MASK)
/*! @} */

/*! @name PCC_WDOG0 - PCC WDOG0 Register */
/*! @{ */

#define PCC0_PCC_WDOG0_PCD_MASK                  (0x7U)
#define PCC0_PCC_WDOG0_PCD_SHIFT                 (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC0_PCC_WDOG0_PCD(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG0_PCD_SHIFT)) & PCC0_PCC_WDOG0_PCD_MASK)

#define PCC0_PCC_WDOG0_FRAC_MASK                 (0x8U)
#define PCC0_PCC_WDOG0_FRAC_SHIFT                (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC0_PCC_WDOG0_FRAC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG0_FRAC_SHIFT)) & PCC0_PCC_WDOG0_FRAC_MASK)

#define PCC0_PCC_WDOG0_SSADO_MASK                (0xC00000U)
#define PCC0_PCC_WDOG0_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_WDOG0_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG0_SSADO_SHIFT)) & PCC0_PCC_WDOG0_SSADO_MASK)

#define PCC0_PCC_WDOG0_PCS_MASK                  (0x7000000U)
#define PCC0_PCC_WDOG0_PCS_SHIFT                 (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC0_PCC_WDOG0_PCS(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG0_PCS_SHIFT)) & PCC0_PCC_WDOG0_PCS_MASK)

#define PCC0_PCC_WDOG0_SWRST_MASK                (0x10000000U)
#define PCC0_PCC_WDOG0_SWRST_SHIFT               (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC0_PCC_WDOG0_SWRST(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG0_SWRST_SHIFT)) & PCC0_PCC_WDOG0_SWRST_MASK)

#define PCC0_PCC_WDOG0_CGC_MASK                  (0x40000000U)
#define PCC0_PCC_WDOG0_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_WDOG0_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG0_CGC_SHIFT)) & PCC0_PCC_WDOG0_CGC_MASK)

#define PCC0_PCC_WDOG0_PR_MASK                   (0x80000000U)
#define PCC0_PCC_WDOG0_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_WDOG0_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG0_PR_SHIFT)) & PCC0_PCC_WDOG0_PR_MASK)
/*! @} */

/*! @name PCC_WDOG1 - PCC WDOG1 Register */
/*! @{ */

#define PCC0_PCC_WDOG1_PCD_MASK                  (0x7U)
#define PCC0_PCC_WDOG1_PCD_SHIFT                 (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC0_PCC_WDOG1_PCD(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG1_PCD_SHIFT)) & PCC0_PCC_WDOG1_PCD_MASK)

#define PCC0_PCC_WDOG1_FRAC_MASK                 (0x8U)
#define PCC0_PCC_WDOG1_FRAC_SHIFT                (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC0_PCC_WDOG1_FRAC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG1_FRAC_SHIFT)) & PCC0_PCC_WDOG1_FRAC_MASK)

#define PCC0_PCC_WDOG1_SSADO_MASK                (0xC00000U)
#define PCC0_PCC_WDOG1_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_WDOG1_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG1_SSADO_SHIFT)) & PCC0_PCC_WDOG1_SSADO_MASK)

#define PCC0_PCC_WDOG1_PCS_MASK                  (0x7000000U)
#define PCC0_PCC_WDOG1_PCS_SHIFT                 (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC0_PCC_WDOG1_PCS(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG1_PCS_SHIFT)) & PCC0_PCC_WDOG1_PCS_MASK)

#define PCC0_PCC_WDOG1_SWRST_MASK                (0x10000000U)
#define PCC0_PCC_WDOG1_SWRST_SHIFT               (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC0_PCC_WDOG1_SWRST(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG1_SWRST_SHIFT)) & PCC0_PCC_WDOG1_SWRST_MASK)

#define PCC0_PCC_WDOG1_CGC_MASK                  (0x40000000U)
#define PCC0_PCC_WDOG1_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_WDOG1_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG1_CGC_SHIFT)) & PCC0_PCC_WDOG1_CGC_MASK)

#define PCC0_PCC_WDOG1_PR_MASK                   (0x80000000U)
#define PCC0_PCC_WDOG1_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_WDOG1_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG1_PR_SHIFT)) & PCC0_PCC_WDOG1_PR_MASK)
/*! @} */

/*! @name PCC_TRDC_MGR - PCC TRDC_MGR Register */
/*! @{ */

#define PCC0_PCC_TRDC_MGR_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_TRDC_MGR_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_TRDC_MGR_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MGR_SSADO_SHIFT)) & PCC0_PCC_TRDC_MGR_SSADO_MASK)

#define PCC0_PCC_TRDC_MGR_CGC_MASK               (0x40000000U)
#define PCC0_PCC_TRDC_MGR_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_TRDC_MGR_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MGR_CGC_SHIFT)) & PCC0_PCC_TRDC_MGR_CGC_MASK)

#define PCC0_PCC_TRDC_MGR_PR_MASK                (0x80000000U)
#define PCC0_PCC_TRDC_MGR_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_TRDC_MGR_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MGR_PR_SHIFT)) & PCC0_PCC_TRDC_MGR_PR_MASK)
/*! @} */

/*! @name PCC_TRDC_MBC0 - PCC TRDC_MBC0 Register */
/*! @{ */

#define PCC0_PCC_TRDC_MBC0_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_TRDC_MBC0_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_TRDC_MBC0_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MBC0_SSADO_SHIFT)) & PCC0_PCC_TRDC_MBC0_SSADO_MASK)

#define PCC0_PCC_TRDC_MBC0_CGC_MASK              (0x40000000U)
#define PCC0_PCC_TRDC_MBC0_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_TRDC_MBC0_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MBC0_CGC_SHIFT)) & PCC0_PCC_TRDC_MBC0_CGC_MASK)

#define PCC0_PCC_TRDC_MBC0_PR_MASK               (0x80000000U)
#define PCC0_PCC_TRDC_MBC0_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_TRDC_MBC0_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MBC0_PR_SHIFT)) & PCC0_PCC_TRDC_MBC0_PR_MASK)
/*! @} */

/*! @name PCC_TRDC_MBC1 - PCC TRDC_MBC1 Register */
/*! @{ */

#define PCC0_PCC_TRDC_MBC1_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_TRDC_MBC1_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_TRDC_MBC1_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MBC1_SSADO_SHIFT)) & PCC0_PCC_TRDC_MBC1_SSADO_MASK)

#define PCC0_PCC_TRDC_MBC1_CGC_MASK              (0x40000000U)
#define PCC0_PCC_TRDC_MBC1_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_TRDC_MBC1_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MBC1_CGC_SHIFT)) & PCC0_PCC_TRDC_MBC1_CGC_MASK)

#define PCC0_PCC_TRDC_MBC1_PR_MASK               (0x80000000U)
#define PCC0_PCC_TRDC_MBC1_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_TRDC_MBC1_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MBC1_PR_SHIFT)) & PCC0_PCC_TRDC_MBC1_PR_MASK)
/*! @} */

/*! @name PCC_TRDC_MBC2 - PCC TRDC_MBC2 Register */
/*! @{ */

#define PCC0_PCC_TRDC_MBC2_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_TRDC_MBC2_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_TRDC_MBC2_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MBC2_SSADO_SHIFT)) & PCC0_PCC_TRDC_MBC2_SSADO_MASK)

#define PCC0_PCC_TRDC_MBC2_CGC_MASK              (0x40000000U)
#define PCC0_PCC_TRDC_MBC2_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_TRDC_MBC2_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MBC2_CGC_SHIFT)) & PCC0_PCC_TRDC_MBC2_CGC_MASK)

#define PCC0_PCC_TRDC_MBC2_PR_MASK               (0x80000000U)
#define PCC0_PCC_TRDC_MBC2_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_TRDC_MBC2_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MBC2_PR_SHIFT)) & PCC0_PCC_TRDC_MBC2_PR_MASK)
/*! @} */

/*! @name PCC_TRDC_MBC3 - PCC TRDC_MBC3 Register */
/*! @{ */

#define PCC0_PCC_TRDC_MBC3_SSADO_MASK            (0xC00000U)
#define PCC0_PCC_TRDC_MBC3_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_TRDC_MBC3_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MBC3_SSADO_SHIFT)) & PCC0_PCC_TRDC_MBC3_SSADO_MASK)

#define PCC0_PCC_TRDC_MBC3_CGC_MASK              (0x40000000U)
#define PCC0_PCC_TRDC_MBC3_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_TRDC_MBC3_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MBC3_CGC_SHIFT)) & PCC0_PCC_TRDC_MBC3_CGC_MASK)

#define PCC0_PCC_TRDC_MBC3_PR_MASK               (0x80000000U)
#define PCC0_PCC_TRDC_MBC3_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_TRDC_MBC3_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MBC3_PR_SHIFT)) & PCC0_PCC_TRDC_MBC3_PR_MASK)
/*! @} */

/*! @name PCC_TRDC_MRC - PCC TRDC_MRC Register */
/*! @{ */

#define PCC0_PCC_TRDC_MRC_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_TRDC_MRC_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_TRDC_MRC_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MRC_SSADO_SHIFT)) & PCC0_PCC_TRDC_MRC_SSADO_MASK)

#define PCC0_PCC_TRDC_MRC_CGC_MASK               (0x40000000U)
#define PCC0_PCC_TRDC_MRC_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_TRDC_MRC_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MRC_CGC_SHIFT)) & PCC0_PCC_TRDC_MRC_CGC_MASK)

#define PCC0_PCC_TRDC_MRC_PR_MASK                (0x80000000U)
#define PCC0_PCC_TRDC_MRC_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_TRDC_MRC_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRDC_MRC_PR_SHIFT)) & PCC0_PCC_TRDC_MRC_PR_MASK)
/*! @} */

/*! @name PCC_SEMA42_0 - PCC SEMA42_0 Register */
/*! @{ */

#define PCC0_PCC_SEMA42_0_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_SEMA42_0_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_SEMA42_0_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SEMA42_0_SSADO_SHIFT)) & PCC0_PCC_SEMA42_0_SSADO_MASK)

#define PCC0_PCC_SEMA42_0_CGC_MASK               (0x40000000U)
#define PCC0_PCC_SEMA42_0_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_SEMA42_0_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SEMA42_0_CGC_SHIFT)) & PCC0_PCC_SEMA42_0_CGC_MASK)

#define PCC0_PCC_SEMA42_0_PR_MASK                (0x80000000U)
#define PCC0_PCC_SEMA42_0_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_SEMA42_0_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SEMA42_0_PR_SHIFT)) & PCC0_PCC_SEMA42_0_PR_MASK)
/*! @} */

/*! @name PCC_BBNSM - PCC BBNSM Register */
/*! @{ */

#define PCC0_PCC_BBNSM_SSADO_MASK                (0xC00000U)
#define PCC0_PCC_BBNSM_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_BBNSM_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_BBNSM_SSADO_SHIFT)) & PCC0_PCC_BBNSM_SSADO_MASK)

#define PCC0_PCC_BBNSM_CGC_MASK                  (0x40000000U)
#define PCC0_PCC_BBNSM_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_BBNSM_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_BBNSM_CGC_SHIFT)) & PCC0_PCC_BBNSM_CGC_MASK)

#define PCC0_PCC_BBNSM_PR_MASK                   (0x80000000U)
#define PCC0_PCC_BBNSM_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_BBNSM_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_BBNSM_PR_SHIFT)) & PCC0_PCC_BBNSM_PR_MASK)
/*! @} */

/*! @name PCC_FLEXSPI0 - PCC FlexSPI0 Register */
/*! @{ */

#define PCC0_PCC_FLEXSPI0_PCD_MASK               (0x7U)
#define PCC0_PCC_FLEXSPI0_PCD_SHIFT              (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC0_PCC_FLEXSPI0_PCD(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXSPI0_PCD_SHIFT)) & PCC0_PCC_FLEXSPI0_PCD_MASK)

#define PCC0_PCC_FLEXSPI0_FRAC_MASK              (0x8U)
#define PCC0_PCC_FLEXSPI0_FRAC_SHIFT             (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC0_PCC_FLEXSPI0_FRAC(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXSPI0_FRAC_SHIFT)) & PCC0_PCC_FLEXSPI0_FRAC_MASK)

#define PCC0_PCC_FLEXSPI0_SSADO_MASK             (0xC00000U)
#define PCC0_PCC_FLEXSPI0_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_FLEXSPI0_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXSPI0_SSADO_SHIFT)) & PCC0_PCC_FLEXSPI0_SSADO_MASK)

#define PCC0_PCC_FLEXSPI0_PCS_MASK               (0x7000000U)
#define PCC0_PCC_FLEXSPI0_PCS_SHIFT              (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC0_PCC_FLEXSPI0_PCS(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXSPI0_PCS_SHIFT)) & PCC0_PCC_FLEXSPI0_PCS_MASK)

#define PCC0_PCC_FLEXSPI0_SWRST_MASK             (0x10000000U)
#define PCC0_PCC_FLEXSPI0_SWRST_SHIFT            (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC0_PCC_FLEXSPI0_SWRST(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXSPI0_SWRST_SHIFT)) & PCC0_PCC_FLEXSPI0_SWRST_MASK)

#define PCC0_PCC_FLEXSPI0_CGC_MASK               (0x40000000U)
#define PCC0_PCC_FLEXSPI0_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_FLEXSPI0_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXSPI0_CGC_SHIFT)) & PCC0_PCC_FLEXSPI0_CGC_MASK)

#define PCC0_PCC_FLEXSPI0_PR_MASK                (0x80000000U)
#define PCC0_PCC_FLEXSPI0_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_FLEXSPI0_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXSPI0_PR_SHIFT)) & PCC0_PCC_FLEXSPI0_PR_MASK)
/*! @} */

/*! @name PCC_ROMCP0 - PCC ROMCP0 Register */
/*! @{ */

#define PCC0_PCC_ROMCP0_SSADO_MASK               (0xC00000U)
#define PCC0_PCC_ROMCP0_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_ROMCP0_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ROMCP0_SSADO_SHIFT)) & PCC0_PCC_ROMCP0_SSADO_MASK)

#define PCC0_PCC_ROMCP0_CGC_MASK                 (0x40000000U)
#define PCC0_PCC_ROMCP0_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_ROMCP0_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ROMCP0_CGC_SHIFT)) & PCC0_PCC_ROMCP0_CGC_MASK)

#define PCC0_PCC_ROMCP0_PR_MASK                  (0x80000000U)
#define PCC0_PCC_ROMCP0_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_ROMCP0_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ROMCP0_PR_SHIFT)) & PCC0_PCC_ROMCP0_PR_MASK)
/*! @} */

/*! @name PCC_LPIT0 - PCC LPIT0 Register */
/*! @{ */

#define PCC0_PCC_LPIT0_PCD_MASK                  (0x7U)
#define PCC0_PCC_LPIT0_PCD_SHIFT                 (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC0_PCC_LPIT0_PCD(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPIT0_PCD_SHIFT)) & PCC0_PCC_LPIT0_PCD_MASK)

#define PCC0_PCC_LPIT0_FRAC_MASK                 (0x8U)
#define PCC0_PCC_LPIT0_FRAC_SHIFT                (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC0_PCC_LPIT0_FRAC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPIT0_FRAC_SHIFT)) & PCC0_PCC_LPIT0_FRAC_MASK)

#define PCC0_PCC_LPIT0_SSADO_MASK                (0xC00000U)
#define PCC0_PCC_LPIT0_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_LPIT0_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPIT0_SSADO_SHIFT)) & PCC0_PCC_LPIT0_SSADO_MASK)

#define PCC0_PCC_LPIT0_PCS_MASK                  (0x7000000U)
#define PCC0_PCC_LPIT0_PCS_SHIFT                 (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC0_PCC_LPIT0_PCS(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPIT0_PCS_SHIFT)) & PCC0_PCC_LPIT0_PCS_MASK)

#define PCC0_PCC_LPIT0_SWRST_MASK                (0x10000000U)
#define PCC0_PCC_LPIT0_SWRST_SHIFT               (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC0_PCC_LPIT0_SWRST(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPIT0_SWRST_SHIFT)) & PCC0_PCC_LPIT0_SWRST_MASK)

#define PCC0_PCC_LPIT0_CGC_MASK                  (0x40000000U)
#define PCC0_PCC_LPIT0_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_LPIT0_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPIT0_CGC_SHIFT)) & PCC0_PCC_LPIT0_CGC_MASK)

#define PCC0_PCC_LPIT0_PR_MASK                   (0x80000000U)
#define PCC0_PCC_LPIT0_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_LPIT0_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPIT0_PR_SHIFT)) & PCC0_PCC_LPIT0_PR_MASK)
/*! @} */

/*! @name PCC_FLEXIO0 - PCC FlexIO0 Register */
/*! @{ */

#define PCC0_PCC_FLEXIO0_PCD_MASK                (0x7U)
#define PCC0_PCC_FLEXIO0_PCD_SHIFT               (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC0_PCC_FLEXIO0_PCD(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXIO0_PCD_SHIFT)) & PCC0_PCC_FLEXIO0_PCD_MASK)

#define PCC0_PCC_FLEXIO0_FRAC_MASK               (0x8U)
#define PCC0_PCC_FLEXIO0_FRAC_SHIFT              (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC0_PCC_FLEXIO0_FRAC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXIO0_FRAC_SHIFT)) & PCC0_PCC_FLEXIO0_FRAC_MASK)

#define PCC0_PCC_FLEXIO0_SSADO_MASK              (0xC00000U)
#define PCC0_PCC_FLEXIO0_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_FLEXIO0_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXIO0_SSADO_SHIFT)) & PCC0_PCC_FLEXIO0_SSADO_MASK)

#define PCC0_PCC_FLEXIO0_PCS_MASK                (0x7000000U)
#define PCC0_PCC_FLEXIO0_PCS_SHIFT               (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC0_PCC_FLEXIO0_PCS(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXIO0_PCS_SHIFT)) & PCC0_PCC_FLEXIO0_PCS_MASK)

#define PCC0_PCC_FLEXIO0_SWRST_MASK              (0x10000000U)
#define PCC0_PCC_FLEXIO0_SWRST_SHIFT             (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC0_PCC_FLEXIO0_SWRST(x)                (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXIO0_SWRST_SHIFT)) & PCC0_PCC_FLEXIO0_SWRST_MASK)

#define PCC0_PCC_FLEXIO0_CGC_MASK                (0x40000000U)
#define PCC0_PCC_FLEXIO0_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_FLEXIO0_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXIO0_CGC_SHIFT)) & PCC0_PCC_FLEXIO0_CGC_MASK)

#define PCC0_PCC_FLEXIO0_PR_MASK                 (0x80000000U)
#define PCC0_PCC_FLEXIO0_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_FLEXIO0_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXIO0_PR_SHIFT)) & PCC0_PCC_FLEXIO0_PR_MASK)
/*! @} */

/*! @name PCC_I3C0 - PCC I3C0 Register */
/*! @{ */

#define PCC0_PCC_I3C0_PCD_MASK                   (0x7U)
#define PCC0_PCC_I3C0_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC0_PCC_I3C0_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_I3C0_PCD_SHIFT)) & PCC0_PCC_I3C0_PCD_MASK)

#define PCC0_PCC_I3C0_FRAC_MASK                  (0x8U)
#define PCC0_PCC_I3C0_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC0_PCC_I3C0_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_I3C0_FRAC_SHIFT)) & PCC0_PCC_I3C0_FRAC_MASK)

#define PCC0_PCC_I3C0_SSADO_MASK                 (0xC00000U)
#define PCC0_PCC_I3C0_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_I3C0_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_I3C0_SSADO_SHIFT)) & PCC0_PCC_I3C0_SSADO_MASK)

#define PCC0_PCC_I3C0_PCS_MASK                   (0x7000000U)
#define PCC0_PCC_I3C0_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC0_PCC_I3C0_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_I3C0_PCS_SHIFT)) & PCC0_PCC_I3C0_PCS_MASK)

#define PCC0_PCC_I3C0_SWRST_MASK                 (0x10000000U)
#define PCC0_PCC_I3C0_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC0_PCC_I3C0_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_I3C0_SWRST_SHIFT)) & PCC0_PCC_I3C0_SWRST_MASK)

#define PCC0_PCC_I3C0_CGC_MASK                   (0x40000000U)
#define PCC0_PCC_I3C0_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_I3C0_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_I3C0_CGC_SHIFT)) & PCC0_PCC_I3C0_CGC_MASK)

#define PCC0_PCC_I3C0_PR_MASK                    (0x80000000U)
#define PCC0_PCC_I3C0_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_I3C0_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_I3C0_PR_SHIFT)) & PCC0_PCC_I3C0_PR_MASK)
/*! @} */

/*! @name PCC_LPSPI0 - PCC LPSPI0 Register */
/*! @{ */

#define PCC0_PCC_LPSPI0_PCD_MASK                 (0x7U)
#define PCC0_PCC_LPSPI0_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC0_PCC_LPSPI0_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI0_PCD_SHIFT)) & PCC0_PCC_LPSPI0_PCD_MASK)

#define PCC0_PCC_LPSPI0_FRAC_MASK                (0x8U)
#define PCC0_PCC_LPSPI0_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC0_PCC_LPSPI0_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI0_FRAC_SHIFT)) & PCC0_PCC_LPSPI0_FRAC_MASK)

#define PCC0_PCC_LPSPI0_SSADO_MASK               (0xC00000U)
#define PCC0_PCC_LPSPI0_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_LPSPI0_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI0_SSADO_SHIFT)) & PCC0_PCC_LPSPI0_SSADO_MASK)

#define PCC0_PCC_LPSPI0_PCS_MASK                 (0x7000000U)
#define PCC0_PCC_LPSPI0_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC0_PCC_LPSPI0_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI0_PCS_SHIFT)) & PCC0_PCC_LPSPI0_PCS_MASK)

#define PCC0_PCC_LPSPI0_SWRST_MASK               (0x10000000U)
#define PCC0_PCC_LPSPI0_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC0_PCC_LPSPI0_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI0_SWRST_SHIFT)) & PCC0_PCC_LPSPI0_SWRST_MASK)

#define PCC0_PCC_LPSPI0_CGC_MASK                 (0x40000000U)
#define PCC0_PCC_LPSPI0_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_LPSPI0_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI0_CGC_SHIFT)) & PCC0_PCC_LPSPI0_CGC_MASK)

#define PCC0_PCC_LPSPI0_PR_MASK                  (0x80000000U)
#define PCC0_PCC_LPSPI0_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_LPSPI0_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI0_PR_SHIFT)) & PCC0_PCC_LPSPI0_PR_MASK)
/*! @} */

/*! @name PCC_LPSPI1 - PCC LPSPI1 Register */
/*! @{ */

#define PCC0_PCC_LPSPI1_PCD_MASK                 (0x7U)
#define PCC0_PCC_LPSPI1_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC0_PCC_LPSPI1_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI1_PCD_SHIFT)) & PCC0_PCC_LPSPI1_PCD_MASK)

#define PCC0_PCC_LPSPI1_FRAC_MASK                (0x8U)
#define PCC0_PCC_LPSPI1_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC0_PCC_LPSPI1_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI1_FRAC_SHIFT)) & PCC0_PCC_LPSPI1_FRAC_MASK)

#define PCC0_PCC_LPSPI1_SSADO_MASK               (0xC00000U)
#define PCC0_PCC_LPSPI1_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_LPSPI1_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI1_SSADO_SHIFT)) & PCC0_PCC_LPSPI1_SSADO_MASK)

#define PCC0_PCC_LPSPI1_PCS_MASK                 (0x7000000U)
#define PCC0_PCC_LPSPI1_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC0_PCC_LPSPI1_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI1_PCS_SHIFT)) & PCC0_PCC_LPSPI1_PCS_MASK)

#define PCC0_PCC_LPSPI1_SWRST_MASK               (0x10000000U)
#define PCC0_PCC_LPSPI1_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC0_PCC_LPSPI1_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI1_SWRST_SHIFT)) & PCC0_PCC_LPSPI1_SWRST_MASK)

#define PCC0_PCC_LPSPI1_CGC_MASK                 (0x40000000U)
#define PCC0_PCC_LPSPI1_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_LPSPI1_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI1_CGC_SHIFT)) & PCC0_PCC_LPSPI1_CGC_MASK)

#define PCC0_PCC_LPSPI1_PR_MASK                  (0x80000000U)
#define PCC0_PCC_LPSPI1_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_LPSPI1_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI1_PR_SHIFT)) & PCC0_PCC_LPSPI1_PR_MASK)
/*! @} */

/*! @name PCC_ADC0 - PCC ADC0 Register */
/*! @{ */

#define PCC0_PCC_ADC0_PCD_MASK                   (0x7U)
#define PCC0_PCC_ADC0_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC0_PCC_ADC0_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ADC0_PCD_SHIFT)) & PCC0_PCC_ADC0_PCD_MASK)

#define PCC0_PCC_ADC0_FRAC_MASK                  (0x8U)
#define PCC0_PCC_ADC0_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC0_PCC_ADC0_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ADC0_FRAC_SHIFT)) & PCC0_PCC_ADC0_FRAC_MASK)

#define PCC0_PCC_ADC0_SSADO_MASK                 (0xC00000U)
#define PCC0_PCC_ADC0_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_ADC0_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ADC0_SSADO_SHIFT)) & PCC0_PCC_ADC0_SSADO_MASK)

#define PCC0_PCC_ADC0_PCS_MASK                   (0x7000000U)
#define PCC0_PCC_ADC0_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC0_PCC_ADC0_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ADC0_PCS_SHIFT)) & PCC0_PCC_ADC0_PCS_MASK)

#define PCC0_PCC_ADC0_SWRST_MASK                 (0x10000000U)
#define PCC0_PCC_ADC0_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC0_PCC_ADC0_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ADC0_SWRST_SHIFT)) & PCC0_PCC_ADC0_SWRST_MASK)

#define PCC0_PCC_ADC0_CGC_MASK                   (0x40000000U)
#define PCC0_PCC_ADC0_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_ADC0_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ADC0_CGC_SHIFT)) & PCC0_PCC_ADC0_CGC_MASK)

#define PCC0_PCC_ADC0_PR_MASK                    (0x80000000U)
#define PCC0_PCC_ADC0_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_ADC0_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ADC0_PR_SHIFT)) & PCC0_PCC_ADC0_PR_MASK)
/*! @} */

/*! @name PCC_CMP0 - PCC CMP0 Register */
/*! @{ */

#define PCC0_PCC_CMP0_SSADO_MASK                 (0xC00000U)
#define PCC0_PCC_CMP0_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_CMP0_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CMP0_SSADO_SHIFT)) & PCC0_PCC_CMP0_SSADO_MASK)

#define PCC0_PCC_CMP0_CGC_MASK                   (0x40000000U)
#define PCC0_PCC_CMP0_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_CMP0_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CMP0_CGC_SHIFT)) & PCC0_PCC_CMP0_CGC_MASK)

#define PCC0_PCC_CMP0_PR_MASK                    (0x80000000U)
#define PCC0_PCC_CMP0_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_CMP0_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CMP0_PR_SHIFT)) & PCC0_PCC_CMP0_PR_MASK)
/*! @} */

/*! @name PCC_CMP1 - PCC CMP1 Register */
/*! @{ */

#define PCC0_PCC_CMP1_SSADO_MASK                 (0xC00000U)
#define PCC0_PCC_CMP1_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_CMP1_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CMP1_SSADO_SHIFT)) & PCC0_PCC_CMP1_SSADO_MASK)

#define PCC0_PCC_CMP1_CGC_MASK                   (0x40000000U)
#define PCC0_PCC_CMP1_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_CMP1_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CMP1_CGC_SHIFT)) & PCC0_PCC_CMP1_CGC_MASK)

#define PCC0_PCC_CMP1_PR_MASK                    (0x80000000U)
#define PCC0_PCC_CMP1_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_CMP1_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CMP1_PR_SHIFT)) & PCC0_PCC_CMP1_PR_MASK)
/*! @} */

/*! @name PCC_DAC0 - PCC DAC0 Register */
/*! @{ */

#define PCC0_PCC_DAC0_PCD_MASK                   (0x7U)
#define PCC0_PCC_DAC0_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC0_PCC_DAC0_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC0_PCD_SHIFT)) & PCC0_PCC_DAC0_PCD_MASK)

#define PCC0_PCC_DAC0_FRAC_MASK                  (0x8U)
#define PCC0_PCC_DAC0_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC0_PCC_DAC0_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC0_FRAC_SHIFT)) & PCC0_PCC_DAC0_FRAC_MASK)

#define PCC0_PCC_DAC0_SSADO_MASK                 (0xC00000U)
#define PCC0_PCC_DAC0_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DAC0_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC0_SSADO_SHIFT)) & PCC0_PCC_DAC0_SSADO_MASK)

#define PCC0_PCC_DAC0_PCS_MASK                   (0x7000000U)
#define PCC0_PCC_DAC0_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC0_PCC_DAC0_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC0_PCS_SHIFT)) & PCC0_PCC_DAC0_PCS_MASK)

#define PCC0_PCC_DAC0_SWRST_MASK                 (0x10000000U)
#define PCC0_PCC_DAC0_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC0_PCC_DAC0_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC0_SWRST_SHIFT)) & PCC0_PCC_DAC0_SWRST_MASK)

#define PCC0_PCC_DAC0_CGC_MASK                   (0x40000000U)
#define PCC0_PCC_DAC0_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DAC0_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC0_CGC_SHIFT)) & PCC0_PCC_DAC0_CGC_MASK)

#define PCC0_PCC_DAC0_PR_MASK                    (0x80000000U)
#define PCC0_PCC_DAC0_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DAC0_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC0_PR_SHIFT)) & PCC0_PCC_DAC0_PR_MASK)
/*! @} */

/*! @name PCC_DAC1 - PCC DAC1 Register */
/*! @{ */

#define PCC0_PCC_DAC1_PCD_MASK                   (0x7U)
#define PCC0_PCC_DAC1_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC0_PCC_DAC1_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC1_PCD_SHIFT)) & PCC0_PCC_DAC1_PCD_MASK)

#define PCC0_PCC_DAC1_FRAC_MASK                  (0x8U)
#define PCC0_PCC_DAC1_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC0_PCC_DAC1_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC1_FRAC_SHIFT)) & PCC0_PCC_DAC1_FRAC_MASK)

#define PCC0_PCC_DAC1_SSADO_MASK                 (0xC00000U)
#define PCC0_PCC_DAC1_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_DAC1_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC1_SSADO_SHIFT)) & PCC0_PCC_DAC1_SSADO_MASK)

#define PCC0_PCC_DAC1_PCS_MASK                   (0x7000000U)
#define PCC0_PCC_DAC1_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC0_PCC_DAC1_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC1_PCS_SHIFT)) & PCC0_PCC_DAC1_PCS_MASK)

#define PCC0_PCC_DAC1_SWRST_MASK                 (0x10000000U)
#define PCC0_PCC_DAC1_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC0_PCC_DAC1_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC1_SWRST_SHIFT)) & PCC0_PCC_DAC1_SWRST_MASK)

#define PCC0_PCC_DAC1_CGC_MASK                   (0x40000000U)
#define PCC0_PCC_DAC1_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_DAC1_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC1_CGC_SHIFT)) & PCC0_PCC_DAC1_CGC_MASK)

#define PCC0_PCC_DAC1_PR_MASK                    (0x80000000U)
#define PCC0_PCC_DAC1_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_DAC1_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC1_PR_SHIFT)) & PCC0_PCC_DAC1_PR_MASK)
/*! @} */

/*! @name PCC_CM33_CACHE_CONTROLLER - PCC CM33_Cache_Controller Register */
/*! @{ */

#define PCC0_PCC_CM33_CACHE_CONTROLLER_SSADO_MASK (0xC00000U)
#define PCC0_PCC_CM33_CACHE_CONTROLLER_SSADO_SHIFT (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_CM33_CACHE_CONTROLLER_SSADO(x)  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CM33_CACHE_CONTROLLER_SSADO_SHIFT)) & PCC0_PCC_CM33_CACHE_CONTROLLER_SSADO_MASK)

#define PCC0_PCC_CM33_CACHE_CONTROLLER_CGC_MASK  (0x40000000U)
#define PCC0_PCC_CM33_CACHE_CONTROLLER_CGC_SHIFT (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_CM33_CACHE_CONTROLLER_CGC(x)    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CM33_CACHE_CONTROLLER_CGC_SHIFT)) & PCC0_PCC_CM33_CACHE_CONTROLLER_CGC_MASK)

#define PCC0_PCC_CM33_CACHE_CONTROLLER_PR_MASK   (0x80000000U)
#define PCC0_PCC_CM33_CACHE_CONTROLLER_PR_SHIFT  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_CM33_CACHE_CONTROLLER_PR(x)     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CM33_CACHE_CONTROLLER_PR_SHIFT)) & PCC0_PCC_CM33_CACHE_CONTROLLER_PR_MASK)
/*! @} */

/*! @name PCC_S400_LPUART - PCC S400_LPUART Register */
/*! @{ */

#define PCC0_PCC_S400_LPUART_PCD_MASK            (0x7U)
#define PCC0_PCC_S400_LPUART_PCD_SHIFT           (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC0_PCC_S400_LPUART_PCD(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_S400_LPUART_PCD_SHIFT)) & PCC0_PCC_S400_LPUART_PCD_MASK)

#define PCC0_PCC_S400_LPUART_FRAC_MASK           (0x8U)
#define PCC0_PCC_S400_LPUART_FRAC_SHIFT          (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC0_PCC_S400_LPUART_FRAC(x)             (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_S400_LPUART_FRAC_SHIFT)) & PCC0_PCC_S400_LPUART_FRAC_MASK)

#define PCC0_PCC_S400_LPUART_SSADO_MASK          (0xC00000U)
#define PCC0_PCC_S400_LPUART_SSADO_SHIFT         (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_S400_LPUART_SSADO(x)            (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_S400_LPUART_SSADO_SHIFT)) & PCC0_PCC_S400_LPUART_SSADO_MASK)

#define PCC0_PCC_S400_LPUART_PCS_MASK            (0x7000000U)
#define PCC0_PCC_S400_LPUART_PCS_SHIFT           (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC0_PCC_S400_LPUART_PCS(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_S400_LPUART_PCS_SHIFT)) & PCC0_PCC_S400_LPUART_PCS_MASK)

#define PCC0_PCC_S400_LPUART_CGC_MASK            (0x40000000U)
#define PCC0_PCC_S400_LPUART_CGC_SHIFT           (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_S400_LPUART_CGC(x)              (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_S400_LPUART_CGC_SHIFT)) & PCC0_PCC_S400_LPUART_CGC_MASK)

#define PCC0_PCC_S400_LPUART_PR_MASK             (0x80000000U)
#define PCC0_PCC_S400_LPUART_PR_SHIFT            (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_S400_LPUART_PR(x)               (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_S400_LPUART_PR_SHIFT)) & PCC0_PCC_S400_LPUART_PR_MASK)
/*! @} */

/*! @name PCC_POWERSYS_WDOG - PCC Powersys_WDOG Register */
/*! @{ */

#define PCC0_PCC_POWERSYS_WDOG_PCD_MASK          (0x7U)
#define PCC0_PCC_POWERSYS_WDOG_PCD_SHIFT         (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC0_PCC_POWERSYS_WDOG_PCD(x)            (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_POWERSYS_WDOG_PCD_SHIFT)) & PCC0_PCC_POWERSYS_WDOG_PCD_MASK)

#define PCC0_PCC_POWERSYS_WDOG_FRAC_MASK         (0x8U)
#define PCC0_PCC_POWERSYS_WDOG_FRAC_SHIFT        (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC0_PCC_POWERSYS_WDOG_FRAC(x)           (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_POWERSYS_WDOG_FRAC_SHIFT)) & PCC0_PCC_POWERSYS_WDOG_FRAC_MASK)

#define PCC0_PCC_POWERSYS_WDOG_SSADO_MASK        (0xC00000U)
#define PCC0_PCC_POWERSYS_WDOG_SSADO_SHIFT       (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_POWERSYS_WDOG_SSADO(x)          (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_POWERSYS_WDOG_SSADO_SHIFT)) & PCC0_PCC_POWERSYS_WDOG_SSADO_MASK)

#define PCC0_PCC_POWERSYS_WDOG_PCS_MASK          (0x7000000U)
#define PCC0_PCC_POWERSYS_WDOG_PCS_SHIFT         (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC0_PCC_POWERSYS_WDOG_PCS(x)            (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_POWERSYS_WDOG_PCS_SHIFT)) & PCC0_PCC_POWERSYS_WDOG_PCS_MASK)

#define PCC0_PCC_POWERSYS_WDOG_CGC_MASK          (0x40000000U)
#define PCC0_PCC_POWERSYS_WDOG_CGC_SHIFT         (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_POWERSYS_WDOG_CGC(x)            (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_POWERSYS_WDOG_CGC_SHIFT)) & PCC0_PCC_POWERSYS_WDOG_CGC_MASK)

#define PCC0_PCC_POWERSYS_WDOG_PR_MASK           (0x80000000U)
#define PCC0_PCC_POWERSYS_WDOG_PR_SHIFT          (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_POWERSYS_WDOG_PR(x)             (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_POWERSYS_WDOG_PR_SHIFT)) & PCC0_PCC_POWERSYS_WDOG_PR_MASK)
/*! @} */

/*! @name PCC_OCOTP - PCC OCOTP Register */
/*! @{ */

#define PCC0_PCC_OCOTP_SSADO_MASK                (0xC00000U)
#define PCC0_PCC_OCOTP_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC0_PCC_OCOTP_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_OCOTP_SSADO_SHIFT)) & PCC0_PCC_OCOTP_SSADO_MASK)

#define PCC0_PCC_OCOTP_CGC_MASK                  (0x40000000U)
#define PCC0_PCC_OCOTP_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC0_PCC_OCOTP_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_OCOTP_CGC_SHIFT)) & PCC0_PCC_OCOTP_CGC_MASK)

#define PCC0_PCC_OCOTP_PR_MASK                   (0x80000000U)
#define PCC0_PCC_OCOTP_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC0_PCC_OCOTP_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_OCOTP_PR_SHIFT)) & PCC0_PCC_OCOTP_PR_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PCC0_Register_Masks */


/* PCC0 - Peripheral instance base addresses */
/** Peripheral PCC0 base address */
#define PCC0_BASE                                (0x28030000u)
/** Peripheral PCC0 base pointer */
#define PCC0                                     ((PCC0_Type *)PCC0_BASE)
/** Array initializer of PCC0 peripheral base addresses */
#define PCC0_BASE_ADDRS                          { PCC0_BASE }
/** Array initializer of PCC0 peripheral base pointers */
#define PCC0_BASE_PTRS                           { PCC0 }

/*!
 * @}
 */ /* end of group PCC0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PCC1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PCC1_Peripheral_Access_Layer PCC1 Peripheral Access Layer
 * @{
 */

/** PCC1 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[12];
  __IO uint32_t PCC_TPIU;                          /**< PCC TPIU Register, offset: 0xC */
       uint8_t RESERVED_1[8];
  __IO uint32_t PCC_SWO;                           /**< PCC SWO Register, offset: 0x18 */
       uint8_t RESERVED_2[44];
  __IO uint32_t PCC_FLEXSPI1;                      /**< PCC FlexSPI1 Register, offset: 0x48 */
  __IO uint32_t PCC_LPTMR0;                        /**< PCC LPTMR0 Register, offset: 0x4C */
  __IO uint32_t PCC_LPTMR1;                        /**< PCC LPTMR1 Register, offset: 0x50 */
  __IO uint32_t PCC_TPM0;                          /**< PCC TPM0 Register, offset: 0x54 */
  __IO uint32_t PCC_TPM1;                          /**< PCC TPM1 Register, offset: 0x58 */
       uint8_t RESERVED_3[4];
  __IO uint32_t PCC_LPI2C0;                        /**< PCC LPI2C0 Register, offset: 0x60 */
  __IO uint32_t PCC_LPI2C1;                        /**< PCC LPI2C1 Register, offset: 0x64 */
  __IO uint32_t PCC_LPUART0;                       /**< PCC LPUART0 Register, offset: 0x68 */
  __IO uint32_t PCC_LPUART1;                       /**< PCC LPUART1 Register, offset: 0x6C */
  __IO uint32_t PCC_SAI0;                          /**< PCC SAI0 Register, offset: 0x70 */
  __IO uint32_t PCC_SAI1;                          /**< PCC SAI1 Register, offset: 0x74 */
  __IO uint32_t PCC_DIGITAL_FILTER_A;              /**< PCC DIGITAL_FILTER_A Register, offset: 0x78 */
  __IO uint32_t PCC_DIGITAL_FILTER_B;              /**< PCC DIGITAL_FILTER_B Register, offset: 0x7C */
       uint8_t RESERVED_4[8];
  __IO uint32_t PCC_ADC1;                          /**< PCC ADC1 Register, offset: 0x88 */
       uint8_t RESERVED_5[20];
  __IO uint32_t PCC_FLEXCAN;                       /**< PCC Flexcan Register, offset: 0xA0 */
       uint8_t RESERVED_6[16];
  __IO uint32_t PCC_RGPIOA;                        /**< PCC RGPIOA Register, offset: 0xB4 */
  __IO uint32_t PCC_RGPIOB;                        /**< PCC RGPIOB Register, offset: 0xB8 */
  __IO uint32_t PCC_RGPIOC;                        /**< PCC RGPIOC Register, offset: 0xBC */
} PCC1_Type;

/* ----------------------------------------------------------------------------
   -- PCC1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PCC1_Register_Masks PCC1 Register Masks
 * @{
 */

/*! @name PCC_TPIU - PCC TPIU Register */
/*! @{ */

#define PCC1_PCC_TPIU_PCD_MASK                   (0x7U)
#define PCC1_PCC_TPIU_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC1_PCC_TPIU_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPIU_PCD_SHIFT)) & PCC1_PCC_TPIU_PCD_MASK)

#define PCC1_PCC_TPIU_FRAC_MASK                  (0x8U)
#define PCC1_PCC_TPIU_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC1_PCC_TPIU_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPIU_FRAC_SHIFT)) & PCC1_PCC_TPIU_FRAC_MASK)

#define PCC1_PCC_TPIU_SSADO_MASK                 (0xC00000U)
#define PCC1_PCC_TPIU_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_TPIU_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPIU_SSADO_SHIFT)) & PCC1_PCC_TPIU_SSADO_MASK)

#define PCC1_PCC_TPIU_PCS_MASK                   (0x7000000U)
#define PCC1_PCC_TPIU_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC1_PCC_TPIU_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPIU_PCS_SHIFT)) & PCC1_PCC_TPIU_PCS_MASK)

#define PCC1_PCC_TPIU_CGC_MASK                   (0x40000000U)
#define PCC1_PCC_TPIU_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_TPIU_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPIU_CGC_SHIFT)) & PCC1_PCC_TPIU_CGC_MASK)

#define PCC1_PCC_TPIU_PR_MASK                    (0x80000000U)
#define PCC1_PCC_TPIU_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_TPIU_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPIU_PR_SHIFT)) & PCC1_PCC_TPIU_PR_MASK)
/*! @} */

/*! @name PCC_SWO - PCC SWO Register */
/*! @{ */

#define PCC1_PCC_SWO_PCD_MASK                    (0x7U)
#define PCC1_PCC_SWO_PCD_SHIFT                   (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC1_PCC_SWO_PCD(x)                      (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SWO_PCD_SHIFT)) & PCC1_PCC_SWO_PCD_MASK)

#define PCC1_PCC_SWO_FRAC_MASK                   (0x8U)
#define PCC1_PCC_SWO_FRAC_SHIFT                  (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC1_PCC_SWO_FRAC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SWO_FRAC_SHIFT)) & PCC1_PCC_SWO_FRAC_MASK)

#define PCC1_PCC_SWO_SSADO_MASK                  (0xC00000U)
#define PCC1_PCC_SWO_SSADO_SHIFT                 (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_SWO_SSADO(x)                    (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SWO_SSADO_SHIFT)) & PCC1_PCC_SWO_SSADO_MASK)

#define PCC1_PCC_SWO_PCS_MASK                    (0x7000000U)
#define PCC1_PCC_SWO_PCS_SHIFT                   (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC1_PCC_SWO_PCS(x)                      (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SWO_PCS_SHIFT)) & PCC1_PCC_SWO_PCS_MASK)

#define PCC1_PCC_SWO_CGC_MASK                    (0x40000000U)
#define PCC1_PCC_SWO_CGC_SHIFT                   (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_SWO_CGC(x)                      (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SWO_CGC_SHIFT)) & PCC1_PCC_SWO_CGC_MASK)

#define PCC1_PCC_SWO_PR_MASK                     (0x80000000U)
#define PCC1_PCC_SWO_PR_SHIFT                    (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_SWO_PR(x)                       (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SWO_PR_SHIFT)) & PCC1_PCC_SWO_PR_MASK)
/*! @} */

/*! @name PCC_FLEXSPI1 - PCC FlexSPI1 Register */
/*! @{ */

#define PCC1_PCC_FLEXSPI1_PCD_MASK               (0x7U)
#define PCC1_PCC_FLEXSPI1_PCD_SHIFT              (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC1_PCC_FLEXSPI1_PCD(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXSPI1_PCD_SHIFT)) & PCC1_PCC_FLEXSPI1_PCD_MASK)

#define PCC1_PCC_FLEXSPI1_FRAC_MASK              (0x8U)
#define PCC1_PCC_FLEXSPI1_FRAC_SHIFT             (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC1_PCC_FLEXSPI1_FRAC(x)                (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXSPI1_FRAC_SHIFT)) & PCC1_PCC_FLEXSPI1_FRAC_MASK)

#define PCC1_PCC_FLEXSPI1_SSADO_MASK             (0xC00000U)
#define PCC1_PCC_FLEXSPI1_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_FLEXSPI1_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXSPI1_SSADO_SHIFT)) & PCC1_PCC_FLEXSPI1_SSADO_MASK)

#define PCC1_PCC_FLEXSPI1_PCS_MASK               (0x7000000U)
#define PCC1_PCC_FLEXSPI1_PCS_SHIFT              (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC1_PCC_FLEXSPI1_PCS(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXSPI1_PCS_SHIFT)) & PCC1_PCC_FLEXSPI1_PCS_MASK)

#define PCC1_PCC_FLEXSPI1_SWRST_MASK             (0x10000000U)
#define PCC1_PCC_FLEXSPI1_SWRST_SHIFT            (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC1_PCC_FLEXSPI1_SWRST(x)               (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXSPI1_SWRST_SHIFT)) & PCC1_PCC_FLEXSPI1_SWRST_MASK)

#define PCC1_PCC_FLEXSPI1_CGC_MASK               (0x40000000U)
#define PCC1_PCC_FLEXSPI1_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_FLEXSPI1_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXSPI1_CGC_SHIFT)) & PCC1_PCC_FLEXSPI1_CGC_MASK)

#define PCC1_PCC_FLEXSPI1_PR_MASK                (0x80000000U)
#define PCC1_PCC_FLEXSPI1_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_FLEXSPI1_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXSPI1_PR_SHIFT)) & PCC1_PCC_FLEXSPI1_PR_MASK)
/*! @} */

/*! @name PCC_LPTMR0 - PCC LPTMR0 Register */
/*! @{ */

#define PCC1_PCC_LPTMR0_SSADO_MASK               (0xC00000U)
#define PCC1_PCC_LPTMR0_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_LPTMR0_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPTMR0_SSADO_SHIFT)) & PCC1_PCC_LPTMR0_SSADO_MASK)

#define PCC1_PCC_LPTMR0_CGC_MASK                 (0x40000000U)
#define PCC1_PCC_LPTMR0_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_LPTMR0_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPTMR0_CGC_SHIFT)) & PCC1_PCC_LPTMR0_CGC_MASK)

#define PCC1_PCC_LPTMR0_PR_MASK                  (0x80000000U)
#define PCC1_PCC_LPTMR0_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_LPTMR0_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPTMR0_PR_SHIFT)) & PCC1_PCC_LPTMR0_PR_MASK)
/*! @} */

/*! @name PCC_LPTMR1 - PCC LPTMR1 Register */
/*! @{ */

#define PCC1_PCC_LPTMR1_SSADO_MASK               (0xC00000U)
#define PCC1_PCC_LPTMR1_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_LPTMR1_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPTMR1_SSADO_SHIFT)) & PCC1_PCC_LPTMR1_SSADO_MASK)

#define PCC1_PCC_LPTMR1_CGC_MASK                 (0x40000000U)
#define PCC1_PCC_LPTMR1_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_LPTMR1_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPTMR1_CGC_SHIFT)) & PCC1_PCC_LPTMR1_CGC_MASK)

#define PCC1_PCC_LPTMR1_PR_MASK                  (0x80000000U)
#define PCC1_PCC_LPTMR1_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_LPTMR1_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPTMR1_PR_SHIFT)) & PCC1_PCC_LPTMR1_PR_MASK)
/*! @} */

/*! @name PCC_TPM0 - PCC TPM0 Register */
/*! @{ */

#define PCC1_PCC_TPM0_PCD_MASK                   (0x7U)
#define PCC1_PCC_TPM0_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC1_PCC_TPM0_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM0_PCD_SHIFT)) & PCC1_PCC_TPM0_PCD_MASK)

#define PCC1_PCC_TPM0_FRAC_MASK                  (0x8U)
#define PCC1_PCC_TPM0_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC1_PCC_TPM0_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM0_FRAC_SHIFT)) & PCC1_PCC_TPM0_FRAC_MASK)

#define PCC1_PCC_TPM0_SSADO_MASK                 (0xC00000U)
#define PCC1_PCC_TPM0_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_TPM0_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM0_SSADO_SHIFT)) & PCC1_PCC_TPM0_SSADO_MASK)

#define PCC1_PCC_TPM0_PCS_MASK                   (0x7000000U)
#define PCC1_PCC_TPM0_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC1_PCC_TPM0_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM0_PCS_SHIFT)) & PCC1_PCC_TPM0_PCS_MASK)

#define PCC1_PCC_TPM0_SWRST_MASK                 (0x10000000U)
#define PCC1_PCC_TPM0_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC1_PCC_TPM0_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM0_SWRST_SHIFT)) & PCC1_PCC_TPM0_SWRST_MASK)

#define PCC1_PCC_TPM0_CGC_MASK                   (0x40000000U)
#define PCC1_PCC_TPM0_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_TPM0_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM0_CGC_SHIFT)) & PCC1_PCC_TPM0_CGC_MASK)

#define PCC1_PCC_TPM0_PR_MASK                    (0x80000000U)
#define PCC1_PCC_TPM0_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_TPM0_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM0_PR_SHIFT)) & PCC1_PCC_TPM0_PR_MASK)
/*! @} */

/*! @name PCC_TPM1 - PCC TPM1 Register */
/*! @{ */

#define PCC1_PCC_TPM1_PCD_MASK                   (0x7U)
#define PCC1_PCC_TPM1_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC1_PCC_TPM1_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM1_PCD_SHIFT)) & PCC1_PCC_TPM1_PCD_MASK)

#define PCC1_PCC_TPM1_FRAC_MASK                  (0x8U)
#define PCC1_PCC_TPM1_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC1_PCC_TPM1_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM1_FRAC_SHIFT)) & PCC1_PCC_TPM1_FRAC_MASK)

#define PCC1_PCC_TPM1_SSADO_MASK                 (0xC00000U)
#define PCC1_PCC_TPM1_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_TPM1_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM1_SSADO_SHIFT)) & PCC1_PCC_TPM1_SSADO_MASK)

#define PCC1_PCC_TPM1_PCS_MASK                   (0x7000000U)
#define PCC1_PCC_TPM1_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC1_PCC_TPM1_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM1_PCS_SHIFT)) & PCC1_PCC_TPM1_PCS_MASK)

#define PCC1_PCC_TPM1_SWRST_MASK                 (0x10000000U)
#define PCC1_PCC_TPM1_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC1_PCC_TPM1_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM1_SWRST_SHIFT)) & PCC1_PCC_TPM1_SWRST_MASK)

#define PCC1_PCC_TPM1_CGC_MASK                   (0x40000000U)
#define PCC1_PCC_TPM1_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_TPM1_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM1_CGC_SHIFT)) & PCC1_PCC_TPM1_CGC_MASK)

#define PCC1_PCC_TPM1_PR_MASK                    (0x80000000U)
#define PCC1_PCC_TPM1_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_TPM1_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM1_PR_SHIFT)) & PCC1_PCC_TPM1_PR_MASK)
/*! @} */

/*! @name PCC_LPI2C0 - PCC LPI2C0 Register */
/*! @{ */

#define PCC1_PCC_LPI2C0_PCD_MASK                 (0x7U)
#define PCC1_PCC_LPI2C0_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC1_PCC_LPI2C0_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C0_PCD_SHIFT)) & PCC1_PCC_LPI2C0_PCD_MASK)

#define PCC1_PCC_LPI2C0_FRAC_MASK                (0x8U)
#define PCC1_PCC_LPI2C0_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC1_PCC_LPI2C0_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C0_FRAC_SHIFT)) & PCC1_PCC_LPI2C0_FRAC_MASK)

#define PCC1_PCC_LPI2C0_SSADO_MASK               (0xC00000U)
#define PCC1_PCC_LPI2C0_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_LPI2C0_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C0_SSADO_SHIFT)) & PCC1_PCC_LPI2C0_SSADO_MASK)

#define PCC1_PCC_LPI2C0_PCS_MASK                 (0x7000000U)
#define PCC1_PCC_LPI2C0_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC1_PCC_LPI2C0_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C0_PCS_SHIFT)) & PCC1_PCC_LPI2C0_PCS_MASK)

#define PCC1_PCC_LPI2C0_SWRST_MASK               (0x10000000U)
#define PCC1_PCC_LPI2C0_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC1_PCC_LPI2C0_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C0_SWRST_SHIFT)) & PCC1_PCC_LPI2C0_SWRST_MASK)

#define PCC1_PCC_LPI2C0_CGC_MASK                 (0x40000000U)
#define PCC1_PCC_LPI2C0_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_LPI2C0_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C0_CGC_SHIFT)) & PCC1_PCC_LPI2C0_CGC_MASK)

#define PCC1_PCC_LPI2C0_PR_MASK                  (0x80000000U)
#define PCC1_PCC_LPI2C0_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_LPI2C0_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C0_PR_SHIFT)) & PCC1_PCC_LPI2C0_PR_MASK)
/*! @} */

/*! @name PCC_LPI2C1 - PCC LPI2C1 Register */
/*! @{ */

#define PCC1_PCC_LPI2C1_PCD_MASK                 (0x7U)
#define PCC1_PCC_LPI2C1_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC1_PCC_LPI2C1_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C1_PCD_SHIFT)) & PCC1_PCC_LPI2C1_PCD_MASK)

#define PCC1_PCC_LPI2C1_FRAC_MASK                (0x8U)
#define PCC1_PCC_LPI2C1_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC1_PCC_LPI2C1_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C1_FRAC_SHIFT)) & PCC1_PCC_LPI2C1_FRAC_MASK)

#define PCC1_PCC_LPI2C1_SSADO_MASK               (0xC00000U)
#define PCC1_PCC_LPI2C1_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_LPI2C1_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C1_SSADO_SHIFT)) & PCC1_PCC_LPI2C1_SSADO_MASK)

#define PCC1_PCC_LPI2C1_PCS_MASK                 (0x7000000U)
#define PCC1_PCC_LPI2C1_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC1_PCC_LPI2C1_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C1_PCS_SHIFT)) & PCC1_PCC_LPI2C1_PCS_MASK)

#define PCC1_PCC_LPI2C1_SWRST_MASK               (0x10000000U)
#define PCC1_PCC_LPI2C1_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC1_PCC_LPI2C1_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C1_SWRST_SHIFT)) & PCC1_PCC_LPI2C1_SWRST_MASK)

#define PCC1_PCC_LPI2C1_CGC_MASK                 (0x40000000U)
#define PCC1_PCC_LPI2C1_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_LPI2C1_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C1_CGC_SHIFT)) & PCC1_PCC_LPI2C1_CGC_MASK)

#define PCC1_PCC_LPI2C1_PR_MASK                  (0x80000000U)
#define PCC1_PCC_LPI2C1_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_LPI2C1_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPI2C1_PR_SHIFT)) & PCC1_PCC_LPI2C1_PR_MASK)
/*! @} */

/*! @name PCC_LPUART0 - PCC LPUART0 Register */
/*! @{ */

#define PCC1_PCC_LPUART0_PCD_MASK                (0x7U)
#define PCC1_PCC_LPUART0_PCD_SHIFT               (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC1_PCC_LPUART0_PCD(x)                  (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART0_PCD_SHIFT)) & PCC1_PCC_LPUART0_PCD_MASK)

#define PCC1_PCC_LPUART0_FRAC_MASK               (0x8U)
#define PCC1_PCC_LPUART0_FRAC_SHIFT              (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC1_PCC_LPUART0_FRAC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART0_FRAC_SHIFT)) & PCC1_PCC_LPUART0_FRAC_MASK)

#define PCC1_PCC_LPUART0_SSADO_MASK              (0xC00000U)
#define PCC1_PCC_LPUART0_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_LPUART0_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART0_SSADO_SHIFT)) & PCC1_PCC_LPUART0_SSADO_MASK)

#define PCC1_PCC_LPUART0_PCS_MASK                (0x7000000U)
#define PCC1_PCC_LPUART0_PCS_SHIFT               (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC1_PCC_LPUART0_PCS(x)                  (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART0_PCS_SHIFT)) & PCC1_PCC_LPUART0_PCS_MASK)

#define PCC1_PCC_LPUART0_SWRST_MASK              (0x10000000U)
#define PCC1_PCC_LPUART0_SWRST_SHIFT             (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC1_PCC_LPUART0_SWRST(x)                (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART0_SWRST_SHIFT)) & PCC1_PCC_LPUART0_SWRST_MASK)

#define PCC1_PCC_LPUART0_CGC_MASK                (0x40000000U)
#define PCC1_PCC_LPUART0_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_LPUART0_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART0_CGC_SHIFT)) & PCC1_PCC_LPUART0_CGC_MASK)

#define PCC1_PCC_LPUART0_PR_MASK                 (0x80000000U)
#define PCC1_PCC_LPUART0_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_LPUART0_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART0_PR_SHIFT)) & PCC1_PCC_LPUART0_PR_MASK)
/*! @} */

/*! @name PCC_LPUART1 - PCC LPUART1 Register */
/*! @{ */

#define PCC1_PCC_LPUART1_PCD_MASK                (0x7U)
#define PCC1_PCC_LPUART1_PCD_SHIFT               (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC1_PCC_LPUART1_PCD(x)                  (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART1_PCD_SHIFT)) & PCC1_PCC_LPUART1_PCD_MASK)

#define PCC1_PCC_LPUART1_FRAC_MASK               (0x8U)
#define PCC1_PCC_LPUART1_FRAC_SHIFT              (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC1_PCC_LPUART1_FRAC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART1_FRAC_SHIFT)) & PCC1_PCC_LPUART1_FRAC_MASK)

#define PCC1_PCC_LPUART1_SSADO_MASK              (0xC00000U)
#define PCC1_PCC_LPUART1_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_LPUART1_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART1_SSADO_SHIFT)) & PCC1_PCC_LPUART1_SSADO_MASK)

#define PCC1_PCC_LPUART1_PCS_MASK                (0x7000000U)
#define PCC1_PCC_LPUART1_PCS_SHIFT               (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC1_PCC_LPUART1_PCS(x)                  (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART1_PCS_SHIFT)) & PCC1_PCC_LPUART1_PCS_MASK)

#define PCC1_PCC_LPUART1_SWRST_MASK              (0x10000000U)
#define PCC1_PCC_LPUART1_SWRST_SHIFT             (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC1_PCC_LPUART1_SWRST(x)                (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART1_SWRST_SHIFT)) & PCC1_PCC_LPUART1_SWRST_MASK)

#define PCC1_PCC_LPUART1_CGC_MASK                (0x40000000U)
#define PCC1_PCC_LPUART1_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_LPUART1_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART1_CGC_SHIFT)) & PCC1_PCC_LPUART1_CGC_MASK)

#define PCC1_PCC_LPUART1_PR_MASK                 (0x80000000U)
#define PCC1_PCC_LPUART1_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_LPUART1_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART1_PR_SHIFT)) & PCC1_PCC_LPUART1_PR_MASK)
/*! @} */

/*! @name PCC_SAI0 - PCC SAI0 Register */
/*! @{ */

#define PCC1_PCC_SAI0_SSADO_MASK                 (0xC00000U)
#define PCC1_PCC_SAI0_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_SAI0_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI0_SSADO_SHIFT)) & PCC1_PCC_SAI0_SSADO_MASK)

#define PCC1_PCC_SAI0_SWRST_MASK                 (0x10000000U)
#define PCC1_PCC_SAI0_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC1_PCC_SAI0_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI0_SWRST_SHIFT)) & PCC1_PCC_SAI0_SWRST_MASK)

#define PCC1_PCC_SAI0_CGC_MASK                   (0x40000000U)
#define PCC1_PCC_SAI0_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_SAI0_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI0_CGC_SHIFT)) & PCC1_PCC_SAI0_CGC_MASK)

#define PCC1_PCC_SAI0_PR_MASK                    (0x80000000U)
#define PCC1_PCC_SAI0_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_SAI0_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI0_PR_SHIFT)) & PCC1_PCC_SAI0_PR_MASK)
/*! @} */

/*! @name PCC_SAI1 - PCC SAI1 Register */
/*! @{ */

#define PCC1_PCC_SAI1_SSADO_MASK                 (0xC00000U)
#define PCC1_PCC_SAI1_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_SAI1_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI1_SSADO_SHIFT)) & PCC1_PCC_SAI1_SSADO_MASK)

#define PCC1_PCC_SAI1_SWRST_MASK                 (0x10000000U)
#define PCC1_PCC_SAI1_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC1_PCC_SAI1_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI1_SWRST_SHIFT)) & PCC1_PCC_SAI1_SWRST_MASK)

#define PCC1_PCC_SAI1_CGC_MASK                   (0x40000000U)
#define PCC1_PCC_SAI1_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_SAI1_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI1_CGC_SHIFT)) & PCC1_PCC_SAI1_CGC_MASK)

#define PCC1_PCC_SAI1_PR_MASK                    (0x80000000U)
#define PCC1_PCC_SAI1_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_SAI1_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI1_PR_SHIFT)) & PCC1_PCC_SAI1_PR_MASK)
/*! @} */

/*! @name PCC_DIGITAL_FILTER_A - PCC DIGITAL_FILTER_A Register */
/*! @{ */

#define PCC1_PCC_DIGITAL_FILTER_A_SSADO_MASK     (0xC00000U)
#define PCC1_PCC_DIGITAL_FILTER_A_SSADO_SHIFT    (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_DIGITAL_FILTER_A_SSADO(x)       (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_DIGITAL_FILTER_A_SSADO_SHIFT)) & PCC1_PCC_DIGITAL_FILTER_A_SSADO_MASK)

#define PCC1_PCC_DIGITAL_FILTER_A_CGC_MASK       (0x40000000U)
#define PCC1_PCC_DIGITAL_FILTER_A_CGC_SHIFT      (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_DIGITAL_FILTER_A_CGC(x)         (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_DIGITAL_FILTER_A_CGC_SHIFT)) & PCC1_PCC_DIGITAL_FILTER_A_CGC_MASK)

#define PCC1_PCC_DIGITAL_FILTER_A_PR_MASK        (0x80000000U)
#define PCC1_PCC_DIGITAL_FILTER_A_PR_SHIFT       (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_DIGITAL_FILTER_A_PR(x)          (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_DIGITAL_FILTER_A_PR_SHIFT)) & PCC1_PCC_DIGITAL_FILTER_A_PR_MASK)
/*! @} */

/*! @name PCC_DIGITAL_FILTER_B - PCC DIGITAL_FILTER_B Register */
/*! @{ */

#define PCC1_PCC_DIGITAL_FILTER_B_SSADO_MASK     (0xC00000U)
#define PCC1_PCC_DIGITAL_FILTER_B_SSADO_SHIFT    (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_DIGITAL_FILTER_B_SSADO(x)       (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_DIGITAL_FILTER_B_SSADO_SHIFT)) & PCC1_PCC_DIGITAL_FILTER_B_SSADO_MASK)

#define PCC1_PCC_DIGITAL_FILTER_B_CGC_MASK       (0x40000000U)
#define PCC1_PCC_DIGITAL_FILTER_B_CGC_SHIFT      (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_DIGITAL_FILTER_B_CGC(x)         (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_DIGITAL_FILTER_B_CGC_SHIFT)) & PCC1_PCC_DIGITAL_FILTER_B_CGC_MASK)

#define PCC1_PCC_DIGITAL_FILTER_B_PR_MASK        (0x80000000U)
#define PCC1_PCC_DIGITAL_FILTER_B_PR_SHIFT       (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_DIGITAL_FILTER_B_PR(x)          (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_DIGITAL_FILTER_B_PR_SHIFT)) & PCC1_PCC_DIGITAL_FILTER_B_PR_MASK)
/*! @} */

/*! @name PCC_ADC1 - PCC ADC1 Register */
/*! @{ */

#define PCC1_PCC_ADC1_PCD_MASK                   (0x7U)
#define PCC1_PCC_ADC1_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC1_PCC_ADC1_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_ADC1_PCD_SHIFT)) & PCC1_PCC_ADC1_PCD_MASK)

#define PCC1_PCC_ADC1_FRAC_MASK                  (0x8U)
#define PCC1_PCC_ADC1_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC1_PCC_ADC1_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_ADC1_FRAC_SHIFT)) & PCC1_PCC_ADC1_FRAC_MASK)

#define PCC1_PCC_ADC1_SSADO_MASK                 (0xC00000U)
#define PCC1_PCC_ADC1_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_ADC1_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_ADC1_SSADO_SHIFT)) & PCC1_PCC_ADC1_SSADO_MASK)

#define PCC1_PCC_ADC1_PCS_MASK                   (0x7000000U)
#define PCC1_PCC_ADC1_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC1_PCC_ADC1_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_ADC1_PCS_SHIFT)) & PCC1_PCC_ADC1_PCS_MASK)

#define PCC1_PCC_ADC1_SWRST_MASK                 (0x10000000U)
#define PCC1_PCC_ADC1_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC1_PCC_ADC1_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_ADC1_SWRST_SHIFT)) & PCC1_PCC_ADC1_SWRST_MASK)

#define PCC1_PCC_ADC1_CGC_MASK                   (0x40000000U)
#define PCC1_PCC_ADC1_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_ADC1_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_ADC1_CGC_SHIFT)) & PCC1_PCC_ADC1_CGC_MASK)

#define PCC1_PCC_ADC1_PR_MASK                    (0x80000000U)
#define PCC1_PCC_ADC1_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_ADC1_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_ADC1_PR_SHIFT)) & PCC1_PCC_ADC1_PR_MASK)
/*! @} */

/*! @name PCC_FLEXCAN - PCC Flexcan Register */
/*! @{ */

#define PCC1_PCC_FLEXCAN_PCD_MASK                (0x7U)
#define PCC1_PCC_FLEXCAN_PCD_SHIFT               (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC1_PCC_FLEXCAN_PCD(x)                  (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXCAN_PCD_SHIFT)) & PCC1_PCC_FLEXCAN_PCD_MASK)

#define PCC1_PCC_FLEXCAN_FRAC_MASK               (0x8U)
#define PCC1_PCC_FLEXCAN_FRAC_SHIFT              (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC1_PCC_FLEXCAN_FRAC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXCAN_FRAC_SHIFT)) & PCC1_PCC_FLEXCAN_FRAC_MASK)

#define PCC1_PCC_FLEXCAN_SSADO_MASK              (0xC00000U)
#define PCC1_PCC_FLEXCAN_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_FLEXCAN_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXCAN_SSADO_SHIFT)) & PCC1_PCC_FLEXCAN_SSADO_MASK)

#define PCC1_PCC_FLEXCAN_PCS_MASK                (0x7000000U)
#define PCC1_PCC_FLEXCAN_PCS_SHIFT               (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC1_PCC_FLEXCAN_PCS(x)                  (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXCAN_PCS_SHIFT)) & PCC1_PCC_FLEXCAN_PCS_MASK)

#define PCC1_PCC_FLEXCAN_SWRST_MASK              (0x10000000U)
#define PCC1_PCC_FLEXCAN_SWRST_SHIFT             (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC1_PCC_FLEXCAN_SWRST(x)                (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXCAN_SWRST_SHIFT)) & PCC1_PCC_FLEXCAN_SWRST_MASK)

#define PCC1_PCC_FLEXCAN_CGC_MASK                (0x40000000U)
#define PCC1_PCC_FLEXCAN_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_FLEXCAN_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXCAN_CGC_SHIFT)) & PCC1_PCC_FLEXCAN_CGC_MASK)

#define PCC1_PCC_FLEXCAN_PR_MASK                 (0x80000000U)
#define PCC1_PCC_FLEXCAN_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_FLEXCAN_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_FLEXCAN_PR_SHIFT)) & PCC1_PCC_FLEXCAN_PR_MASK)
/*! @} */

/*! @name PCC_RGPIOA - PCC RGPIOA Register */
/*! @{ */

#define PCC1_PCC_RGPIOA_SSADO_MASK               (0xC00000U)
#define PCC1_PCC_RGPIOA_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_RGPIOA_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_RGPIOA_SSADO_SHIFT)) & PCC1_PCC_RGPIOA_SSADO_MASK)

#define PCC1_PCC_RGPIOA_CGC_MASK                 (0x40000000U)
#define PCC1_PCC_RGPIOA_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_RGPIOA_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_RGPIOA_CGC_SHIFT)) & PCC1_PCC_RGPIOA_CGC_MASK)

#define PCC1_PCC_RGPIOA_PR_MASK                  (0x80000000U)
#define PCC1_PCC_RGPIOA_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_RGPIOA_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_RGPIOA_PR_SHIFT)) & PCC1_PCC_RGPIOA_PR_MASK)
/*! @} */

/*! @name PCC_RGPIOB - PCC RGPIOB Register */
/*! @{ */

#define PCC1_PCC_RGPIOB_SSADO_MASK               (0xC00000U)
#define PCC1_PCC_RGPIOB_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_RGPIOB_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_RGPIOB_SSADO_SHIFT)) & PCC1_PCC_RGPIOB_SSADO_MASK)

#define PCC1_PCC_RGPIOB_CGC_MASK                 (0x40000000U)
#define PCC1_PCC_RGPIOB_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_RGPIOB_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_RGPIOB_CGC_SHIFT)) & PCC1_PCC_RGPIOB_CGC_MASK)

#define PCC1_PCC_RGPIOB_PR_MASK                  (0x80000000U)
#define PCC1_PCC_RGPIOB_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_RGPIOB_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_RGPIOB_PR_SHIFT)) & PCC1_PCC_RGPIOB_PR_MASK)
/*! @} */

/*! @name PCC_RGPIOC - PCC RGPIOC Register */
/*! @{ */

#define PCC1_PCC_RGPIOC_SSADO_MASK               (0xC00000U)
#define PCC1_PCC_RGPIOC_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC1_PCC_RGPIOC_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_RGPIOC_SSADO_SHIFT)) & PCC1_PCC_RGPIOC_SSADO_MASK)

#define PCC1_PCC_RGPIOC_CGC_MASK                 (0x40000000U)
#define PCC1_PCC_RGPIOC_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC1_PCC_RGPIOC_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_RGPIOC_CGC_SHIFT)) & PCC1_PCC_RGPIOC_CGC_MASK)

#define PCC1_PCC_RGPIOC_PR_MASK                  (0x80000000U)
#define PCC1_PCC_RGPIOC_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC1_PCC_RGPIOC_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_RGPIOC_PR_SHIFT)) & PCC1_PCC_RGPIOC_PR_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PCC1_Register_Masks */


/* PCC1 - Peripheral instance base addresses */
/** Peripheral PCC1 base address */
#define PCC1_BASE                                (0x28091000u)
/** Peripheral PCC1 base pointer */
#define PCC1                                     ((PCC1_Type *)PCC1_BASE)
/** Array initializer of PCC1 peripheral base addresses */
#define PCC1_BASE_ADDRS                          { PCC1_BASE }
/** Array initializer of PCC1 peripheral base pointers */
#define PCC1_BASE_PTRS                           { PCC1 }

/*!
 * @}
 */ /* end of group PCC1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PCC2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PCC2_Peripheral_Access_Layer PCC2 Peripheral Access Layer
 * @{
 */

/** PCC2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t PCC_MU1_B;                         /**< PCC MU1_B Register, offset: 0x0 */
  __IO uint32_t PCC_WDOG2;                         /**< PCC WDOG2 Register, offset: 0x4 */
       uint8_t RESERVED_0[12];
  __IO uint32_t PCC_TPM2;                          /**< PCC TPM2 Register, offset: 0x14 */
  __IO uint32_t PCC_TPM3;                          /**< PCC TPM3 Register, offset: 0x18 */
  __IO uint32_t PCC_MRT;                           /**< PCC MRT Register, offset: 0x1C */
  __IO uint32_t PCC_LPI2C2;                        /**< PCC LPI2C2 Register, offset: 0x20 */
  __IO uint32_t PCC_LPI2C3;                        /**< PCC LPI2C3 Register, offset: 0x24 */
  __IO uint32_t PCC_I3C1;                          /**< PCC I3C1 Register, offset: 0x28 */
  __IO uint32_t PCC_LPUART2;                       /**< PCC LPUART2 Register, offset: 0x2C */
  __IO uint32_t PCC_LPUART3;                       /**< PCC LPUART3 Register, offset: 0x30 */
  __IO uint32_t PCC_LPSPI2;                        /**< PCC LPSPI2 Register, offset: 0x34 */
  __IO uint32_t PCC_LPSPI3;                        /**< PCC LPSPI3 Register, offset: 0x38 */
  __IO uint32_t PCC_SAI2;                          /**< PCC SAI2 Register, offset: 0x3C */
  __IO uint32_t PCC_SAI3;                          /**< PCC SAI3 Register, offset: 0x40 */
  __IO uint32_t PCC_MICFIL;                        /**< PCC MICFIL Register, offset: 0x44 */
} PCC2_Type;

/* ----------------------------------------------------------------------------
   -- PCC2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PCC2_Register_Masks PCC2 Register Masks
 * @{
 */

/*! @name PCC_MU1_B - PCC MU1_B Register */
/*! @{ */

#define PCC2_PCC_MU1_B_SSADO_MASK                (0xC00000U)
#define PCC2_PCC_MU1_B_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_MU1_B_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_MU1_B_SSADO_SHIFT)) & PCC2_PCC_MU1_B_SSADO_MASK)

#define PCC2_PCC_MU1_B_CGC_MASK                  (0x40000000U)
#define PCC2_PCC_MU1_B_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_MU1_B_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_MU1_B_CGC_SHIFT)) & PCC2_PCC_MU1_B_CGC_MASK)

#define PCC2_PCC_MU1_B_PR_MASK                   (0x80000000U)
#define PCC2_PCC_MU1_B_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_MU1_B_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_MU1_B_PR_SHIFT)) & PCC2_PCC_MU1_B_PR_MASK)
/*! @} */

/*! @name PCC_WDOG2 - PCC WDOG2 Register */
/*! @{ */

#define PCC2_PCC_WDOG2_PCD_MASK                  (0x7U)
#define PCC2_PCC_WDOG2_PCD_SHIFT                 (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC2_PCC_WDOG2_PCD(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG2_PCD_SHIFT)) & PCC2_PCC_WDOG2_PCD_MASK)

#define PCC2_PCC_WDOG2_FRAC_MASK                 (0x8U)
#define PCC2_PCC_WDOG2_FRAC_SHIFT                (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC2_PCC_WDOG2_FRAC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG2_FRAC_SHIFT)) & PCC2_PCC_WDOG2_FRAC_MASK)

#define PCC2_PCC_WDOG2_SSADO_MASK                (0xC00000U)
#define PCC2_PCC_WDOG2_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_WDOG2_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG2_SSADO_SHIFT)) & PCC2_PCC_WDOG2_SSADO_MASK)

#define PCC2_PCC_WDOG2_PCS_MASK                  (0x7000000U)
#define PCC2_PCC_WDOG2_PCS_SHIFT                 (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC2_PCC_WDOG2_PCS(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG2_PCS_SHIFT)) & PCC2_PCC_WDOG2_PCS_MASK)

#define PCC2_PCC_WDOG2_SWRST_MASK                (0x10000000U)
#define PCC2_PCC_WDOG2_SWRST_SHIFT               (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_WDOG2_SWRST(x)                  (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG2_SWRST_SHIFT)) & PCC2_PCC_WDOG2_SWRST_MASK)

#define PCC2_PCC_WDOG2_CGC_MASK                  (0x40000000U)
#define PCC2_PCC_WDOG2_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_WDOG2_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG2_CGC_SHIFT)) & PCC2_PCC_WDOG2_CGC_MASK)

#define PCC2_PCC_WDOG2_PR_MASK                   (0x80000000U)
#define PCC2_PCC_WDOG2_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_WDOG2_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG2_PR_SHIFT)) & PCC2_PCC_WDOG2_PR_MASK)
/*! @} */

/*! @name PCC_TPM2 - PCC TPM2 Register */
/*! @{ */

#define PCC2_PCC_TPM2_PCD_MASK                   (0x7U)
#define PCC2_PCC_TPM2_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC2_PCC_TPM2_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM2_PCD_SHIFT)) & PCC2_PCC_TPM2_PCD_MASK)

#define PCC2_PCC_TPM2_FRAC_MASK                  (0x8U)
#define PCC2_PCC_TPM2_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC2_PCC_TPM2_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM2_FRAC_SHIFT)) & PCC2_PCC_TPM2_FRAC_MASK)

#define PCC2_PCC_TPM2_SSADO_MASK                 (0xC00000U)
#define PCC2_PCC_TPM2_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_TPM2_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM2_SSADO_SHIFT)) & PCC2_PCC_TPM2_SSADO_MASK)

#define PCC2_PCC_TPM2_PCS_MASK                   (0x7000000U)
#define PCC2_PCC_TPM2_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC2_PCC_TPM2_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM2_PCS_SHIFT)) & PCC2_PCC_TPM2_PCS_MASK)

#define PCC2_PCC_TPM2_SWRST_MASK                 (0x10000000U)
#define PCC2_PCC_TPM2_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_TPM2_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM2_SWRST_SHIFT)) & PCC2_PCC_TPM2_SWRST_MASK)

#define PCC2_PCC_TPM2_CGC_MASK                   (0x40000000U)
#define PCC2_PCC_TPM2_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_TPM2_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM2_CGC_SHIFT)) & PCC2_PCC_TPM2_CGC_MASK)

#define PCC2_PCC_TPM2_PR_MASK                    (0x80000000U)
#define PCC2_PCC_TPM2_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_TPM2_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM2_PR_SHIFT)) & PCC2_PCC_TPM2_PR_MASK)
/*! @} */

/*! @name PCC_TPM3 - PCC TPM3 Register */
/*! @{ */

#define PCC2_PCC_TPM3_PCD_MASK                   (0x7U)
#define PCC2_PCC_TPM3_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC2_PCC_TPM3_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM3_PCD_SHIFT)) & PCC2_PCC_TPM3_PCD_MASK)

#define PCC2_PCC_TPM3_FRAC_MASK                  (0x8U)
#define PCC2_PCC_TPM3_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC2_PCC_TPM3_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM3_FRAC_SHIFT)) & PCC2_PCC_TPM3_FRAC_MASK)

#define PCC2_PCC_TPM3_SSADO_MASK                 (0xC00000U)
#define PCC2_PCC_TPM3_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_TPM3_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM3_SSADO_SHIFT)) & PCC2_PCC_TPM3_SSADO_MASK)

#define PCC2_PCC_TPM3_PCS_MASK                   (0x7000000U)
#define PCC2_PCC_TPM3_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC2_PCC_TPM3_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM3_PCS_SHIFT)) & PCC2_PCC_TPM3_PCS_MASK)

#define PCC2_PCC_TPM3_SWRST_MASK                 (0x10000000U)
#define PCC2_PCC_TPM3_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_TPM3_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM3_SWRST_SHIFT)) & PCC2_PCC_TPM3_SWRST_MASK)

#define PCC2_PCC_TPM3_CGC_MASK                   (0x40000000U)
#define PCC2_PCC_TPM3_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_TPM3_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM3_CGC_SHIFT)) & PCC2_PCC_TPM3_CGC_MASK)

#define PCC2_PCC_TPM3_PR_MASK                    (0x80000000U)
#define PCC2_PCC_TPM3_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_TPM3_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM3_PR_SHIFT)) & PCC2_PCC_TPM3_PR_MASK)
/*! @} */

/*! @name PCC_MRT - PCC MRT Register */
/*! @{ */

#define PCC2_PCC_MRT_SSADO_MASK                  (0xC00000U)
#define PCC2_PCC_MRT_SSADO_SHIFT                 (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_MRT_SSADO(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_MRT_SSADO_SHIFT)) & PCC2_PCC_MRT_SSADO_MASK)

#define PCC2_PCC_MRT_SWRST_MASK                  (0x10000000U)
#define PCC2_PCC_MRT_SWRST_SHIFT                 (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_MRT_SWRST(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_MRT_SWRST_SHIFT)) & PCC2_PCC_MRT_SWRST_MASK)

#define PCC2_PCC_MRT_CGC_MASK                    (0x40000000U)
#define PCC2_PCC_MRT_CGC_SHIFT                   (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_MRT_CGC(x)                      (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_MRT_CGC_SHIFT)) & PCC2_PCC_MRT_CGC_MASK)

#define PCC2_PCC_MRT_PR_MASK                     (0x80000000U)
#define PCC2_PCC_MRT_PR_SHIFT                    (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_MRT_PR(x)                       (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_MRT_PR_SHIFT)) & PCC2_PCC_MRT_PR_MASK)
/*! @} */

/*! @name PCC_LPI2C2 - PCC LPI2C2 Register */
/*! @{ */

#define PCC2_PCC_LPI2C2_PCD_MASK                 (0x7U)
#define PCC2_PCC_LPI2C2_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC2_PCC_LPI2C2_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C2_PCD_SHIFT)) & PCC2_PCC_LPI2C2_PCD_MASK)

#define PCC2_PCC_LPI2C2_FRAC_MASK                (0x8U)
#define PCC2_PCC_LPI2C2_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC2_PCC_LPI2C2_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C2_FRAC_SHIFT)) & PCC2_PCC_LPI2C2_FRAC_MASK)

#define PCC2_PCC_LPI2C2_SSADO_MASK               (0xC00000U)
#define PCC2_PCC_LPI2C2_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_LPI2C2_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C2_SSADO_SHIFT)) & PCC2_PCC_LPI2C2_SSADO_MASK)

#define PCC2_PCC_LPI2C2_PCS_MASK                 (0x7000000U)
#define PCC2_PCC_LPI2C2_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC2_PCC_LPI2C2_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C2_PCS_SHIFT)) & PCC2_PCC_LPI2C2_PCS_MASK)

#define PCC2_PCC_LPI2C2_SWRST_MASK               (0x10000000U)
#define PCC2_PCC_LPI2C2_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_LPI2C2_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C2_SWRST_SHIFT)) & PCC2_PCC_LPI2C2_SWRST_MASK)

#define PCC2_PCC_LPI2C2_CGC_MASK                 (0x40000000U)
#define PCC2_PCC_LPI2C2_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_LPI2C2_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C2_CGC_SHIFT)) & PCC2_PCC_LPI2C2_CGC_MASK)

#define PCC2_PCC_LPI2C2_PR_MASK                  (0x80000000U)
#define PCC2_PCC_LPI2C2_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_LPI2C2_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C2_PR_SHIFT)) & PCC2_PCC_LPI2C2_PR_MASK)
/*! @} */

/*! @name PCC_LPI2C3 - PCC LPI2C3 Register */
/*! @{ */

#define PCC2_PCC_LPI2C3_PCD_MASK                 (0x7U)
#define PCC2_PCC_LPI2C3_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC2_PCC_LPI2C3_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C3_PCD_SHIFT)) & PCC2_PCC_LPI2C3_PCD_MASK)

#define PCC2_PCC_LPI2C3_FRAC_MASK                (0x8U)
#define PCC2_PCC_LPI2C3_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC2_PCC_LPI2C3_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C3_FRAC_SHIFT)) & PCC2_PCC_LPI2C3_FRAC_MASK)

#define PCC2_PCC_LPI2C3_SSADO_MASK               (0xC00000U)
#define PCC2_PCC_LPI2C3_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_LPI2C3_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C3_SSADO_SHIFT)) & PCC2_PCC_LPI2C3_SSADO_MASK)

#define PCC2_PCC_LPI2C3_PCS_MASK                 (0x7000000U)
#define PCC2_PCC_LPI2C3_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC2_PCC_LPI2C3_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C3_PCS_SHIFT)) & PCC2_PCC_LPI2C3_PCS_MASK)

#define PCC2_PCC_LPI2C3_SWRST_MASK               (0x10000000U)
#define PCC2_PCC_LPI2C3_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_LPI2C3_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C3_SWRST_SHIFT)) & PCC2_PCC_LPI2C3_SWRST_MASK)

#define PCC2_PCC_LPI2C3_CGC_MASK                 (0x40000000U)
#define PCC2_PCC_LPI2C3_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_LPI2C3_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C3_CGC_SHIFT)) & PCC2_PCC_LPI2C3_CGC_MASK)

#define PCC2_PCC_LPI2C3_PR_MASK                  (0x80000000U)
#define PCC2_PCC_LPI2C3_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_LPI2C3_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C3_PR_SHIFT)) & PCC2_PCC_LPI2C3_PR_MASK)
/*! @} */

/*! @name PCC_I3C1 - PCC I3C1 Register */
/*! @{ */

#define PCC2_PCC_I3C1_PCD_MASK                   (0x7U)
#define PCC2_PCC_I3C1_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC2_PCC_I3C1_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_I3C1_PCD_SHIFT)) & PCC2_PCC_I3C1_PCD_MASK)

#define PCC2_PCC_I3C1_FRAC_MASK                  (0x8U)
#define PCC2_PCC_I3C1_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC2_PCC_I3C1_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_I3C1_FRAC_SHIFT)) & PCC2_PCC_I3C1_FRAC_MASK)

#define PCC2_PCC_I3C1_SSADO_MASK                 (0xC00000U)
#define PCC2_PCC_I3C1_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_I3C1_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_I3C1_SSADO_SHIFT)) & PCC2_PCC_I3C1_SSADO_MASK)

#define PCC2_PCC_I3C1_PCS_MASK                   (0x7000000U)
#define PCC2_PCC_I3C1_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC2_PCC_I3C1_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_I3C1_PCS_SHIFT)) & PCC2_PCC_I3C1_PCS_MASK)

#define PCC2_PCC_I3C1_SWRST_MASK                 (0x10000000U)
#define PCC2_PCC_I3C1_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_I3C1_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_I3C1_SWRST_SHIFT)) & PCC2_PCC_I3C1_SWRST_MASK)

#define PCC2_PCC_I3C1_CGC_MASK                   (0x40000000U)
#define PCC2_PCC_I3C1_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_I3C1_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_I3C1_CGC_SHIFT)) & PCC2_PCC_I3C1_CGC_MASK)

#define PCC2_PCC_I3C1_PR_MASK                    (0x80000000U)
#define PCC2_PCC_I3C1_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_I3C1_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_I3C1_PR_SHIFT)) & PCC2_PCC_I3C1_PR_MASK)
/*! @} */

/*! @name PCC_LPUART2 - PCC LPUART2 Register */
/*! @{ */

#define PCC2_PCC_LPUART2_PCD_MASK                (0x7U)
#define PCC2_PCC_LPUART2_PCD_SHIFT               (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC2_PCC_LPUART2_PCD(x)                  (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART2_PCD_SHIFT)) & PCC2_PCC_LPUART2_PCD_MASK)

#define PCC2_PCC_LPUART2_FRAC_MASK               (0x8U)
#define PCC2_PCC_LPUART2_FRAC_SHIFT              (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC2_PCC_LPUART2_FRAC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART2_FRAC_SHIFT)) & PCC2_PCC_LPUART2_FRAC_MASK)

#define PCC2_PCC_LPUART2_SSADO_MASK              (0xC00000U)
#define PCC2_PCC_LPUART2_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_LPUART2_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART2_SSADO_SHIFT)) & PCC2_PCC_LPUART2_SSADO_MASK)

#define PCC2_PCC_LPUART2_PCS_MASK                (0x7000000U)
#define PCC2_PCC_LPUART2_PCS_SHIFT               (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC2_PCC_LPUART2_PCS(x)                  (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART2_PCS_SHIFT)) & PCC2_PCC_LPUART2_PCS_MASK)

#define PCC2_PCC_LPUART2_SWRST_MASK              (0x10000000U)
#define PCC2_PCC_LPUART2_SWRST_SHIFT             (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_LPUART2_SWRST(x)                (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART2_SWRST_SHIFT)) & PCC2_PCC_LPUART2_SWRST_MASK)

#define PCC2_PCC_LPUART2_CGC_MASK                (0x40000000U)
#define PCC2_PCC_LPUART2_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_LPUART2_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART2_CGC_SHIFT)) & PCC2_PCC_LPUART2_CGC_MASK)

#define PCC2_PCC_LPUART2_PR_MASK                 (0x80000000U)
#define PCC2_PCC_LPUART2_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_LPUART2_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART2_PR_SHIFT)) & PCC2_PCC_LPUART2_PR_MASK)
/*! @} */

/*! @name PCC_LPUART3 - PCC LPUART3 Register */
/*! @{ */

#define PCC2_PCC_LPUART3_PCD_MASK                (0x7U)
#define PCC2_PCC_LPUART3_PCD_SHIFT               (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC2_PCC_LPUART3_PCD(x)                  (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART3_PCD_SHIFT)) & PCC2_PCC_LPUART3_PCD_MASK)

#define PCC2_PCC_LPUART3_FRAC_MASK               (0x8U)
#define PCC2_PCC_LPUART3_FRAC_SHIFT              (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC2_PCC_LPUART3_FRAC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART3_FRAC_SHIFT)) & PCC2_PCC_LPUART3_FRAC_MASK)

#define PCC2_PCC_LPUART3_SSADO_MASK              (0xC00000U)
#define PCC2_PCC_LPUART3_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_LPUART3_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART3_SSADO_SHIFT)) & PCC2_PCC_LPUART3_SSADO_MASK)

#define PCC2_PCC_LPUART3_PCS_MASK                (0x7000000U)
#define PCC2_PCC_LPUART3_PCS_SHIFT               (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC2_PCC_LPUART3_PCS(x)                  (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART3_PCS_SHIFT)) & PCC2_PCC_LPUART3_PCS_MASK)

#define PCC2_PCC_LPUART3_SWRST_MASK              (0x10000000U)
#define PCC2_PCC_LPUART3_SWRST_SHIFT             (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_LPUART3_SWRST(x)                (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART3_SWRST_SHIFT)) & PCC2_PCC_LPUART3_SWRST_MASK)

#define PCC2_PCC_LPUART3_CGC_MASK                (0x40000000U)
#define PCC2_PCC_LPUART3_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_LPUART3_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART3_CGC_SHIFT)) & PCC2_PCC_LPUART3_CGC_MASK)

#define PCC2_PCC_LPUART3_PR_MASK                 (0x80000000U)
#define PCC2_PCC_LPUART3_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_LPUART3_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART3_PR_SHIFT)) & PCC2_PCC_LPUART3_PR_MASK)
/*! @} */

/*! @name PCC_LPSPI2 - PCC LPSPI2 Register */
/*! @{ */

#define PCC2_PCC_LPSPI2_PCD_MASK                 (0x7U)
#define PCC2_PCC_LPSPI2_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC2_PCC_LPSPI2_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI2_PCD_SHIFT)) & PCC2_PCC_LPSPI2_PCD_MASK)

#define PCC2_PCC_LPSPI2_FRAC_MASK                (0x8U)
#define PCC2_PCC_LPSPI2_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC2_PCC_LPSPI2_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI2_FRAC_SHIFT)) & PCC2_PCC_LPSPI2_FRAC_MASK)

#define PCC2_PCC_LPSPI2_SSADO_MASK               (0xC00000U)
#define PCC2_PCC_LPSPI2_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_LPSPI2_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI2_SSADO_SHIFT)) & PCC2_PCC_LPSPI2_SSADO_MASK)

#define PCC2_PCC_LPSPI2_PCS_MASK                 (0x7000000U)
#define PCC2_PCC_LPSPI2_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC2_PCC_LPSPI2_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI2_PCS_SHIFT)) & PCC2_PCC_LPSPI2_PCS_MASK)

#define PCC2_PCC_LPSPI2_SWRST_MASK               (0x10000000U)
#define PCC2_PCC_LPSPI2_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_LPSPI2_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI2_SWRST_SHIFT)) & PCC2_PCC_LPSPI2_SWRST_MASK)

#define PCC2_PCC_LPSPI2_CGC_MASK                 (0x40000000U)
#define PCC2_PCC_LPSPI2_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_LPSPI2_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI2_CGC_SHIFT)) & PCC2_PCC_LPSPI2_CGC_MASK)

#define PCC2_PCC_LPSPI2_PR_MASK                  (0x80000000U)
#define PCC2_PCC_LPSPI2_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_LPSPI2_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI2_PR_SHIFT)) & PCC2_PCC_LPSPI2_PR_MASK)
/*! @} */

/*! @name PCC_LPSPI3 - PCC LPSPI3 Register */
/*! @{ */

#define PCC2_PCC_LPSPI3_PCD_MASK                 (0x7U)
#define PCC2_PCC_LPSPI3_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC2_PCC_LPSPI3_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI3_PCD_SHIFT)) & PCC2_PCC_LPSPI3_PCD_MASK)

#define PCC2_PCC_LPSPI3_FRAC_MASK                (0x8U)
#define PCC2_PCC_LPSPI3_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC2_PCC_LPSPI3_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI3_FRAC_SHIFT)) & PCC2_PCC_LPSPI3_FRAC_MASK)

#define PCC2_PCC_LPSPI3_SSADO_MASK               (0xC00000U)
#define PCC2_PCC_LPSPI3_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_LPSPI3_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI3_SSADO_SHIFT)) & PCC2_PCC_LPSPI3_SSADO_MASK)

#define PCC2_PCC_LPSPI3_PCS_MASK                 (0x7000000U)
#define PCC2_PCC_LPSPI3_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC2_PCC_LPSPI3_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI3_PCS_SHIFT)) & PCC2_PCC_LPSPI3_PCS_MASK)

#define PCC2_PCC_LPSPI3_SWRST_MASK               (0x10000000U)
#define PCC2_PCC_LPSPI3_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_LPSPI3_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI3_SWRST_SHIFT)) & PCC2_PCC_LPSPI3_SWRST_MASK)

#define PCC2_PCC_LPSPI3_CGC_MASK                 (0x40000000U)
#define PCC2_PCC_LPSPI3_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_LPSPI3_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI3_CGC_SHIFT)) & PCC2_PCC_LPSPI3_CGC_MASK)

#define PCC2_PCC_LPSPI3_PR_MASK                  (0x80000000U)
#define PCC2_PCC_LPSPI3_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_LPSPI3_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI3_PR_SHIFT)) & PCC2_PCC_LPSPI3_PR_MASK)
/*! @} */

/*! @name PCC_SAI2 - PCC SAI2 Register */
/*! @{ */

#define PCC2_PCC_SAI2_SSADO_MASK                 (0xC00000U)
#define PCC2_PCC_SAI2_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_SAI2_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_SAI2_SSADO_SHIFT)) & PCC2_PCC_SAI2_SSADO_MASK)

#define PCC2_PCC_SAI2_SWRST_MASK                 (0x10000000U)
#define PCC2_PCC_SAI2_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_SAI2_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_SAI2_SWRST_SHIFT)) & PCC2_PCC_SAI2_SWRST_MASK)

#define PCC2_PCC_SAI2_CGC_MASK                   (0x40000000U)
#define PCC2_PCC_SAI2_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_SAI2_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_SAI2_CGC_SHIFT)) & PCC2_PCC_SAI2_CGC_MASK)

#define PCC2_PCC_SAI2_PR_MASK                    (0x80000000U)
#define PCC2_PCC_SAI2_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_SAI2_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_SAI2_PR_SHIFT)) & PCC2_PCC_SAI2_PR_MASK)
/*! @} */

/*! @name PCC_SAI3 - PCC SAI3 Register */
/*! @{ */

#define PCC2_PCC_SAI3_SSADO_MASK                 (0xC00000U)
#define PCC2_PCC_SAI3_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_SAI3_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_SAI3_SSADO_SHIFT)) & PCC2_PCC_SAI3_SSADO_MASK)

#define PCC2_PCC_SAI3_SWRST_MASK                 (0x10000000U)
#define PCC2_PCC_SAI3_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_SAI3_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_SAI3_SWRST_SHIFT)) & PCC2_PCC_SAI3_SWRST_MASK)

#define PCC2_PCC_SAI3_CGC_MASK                   (0x40000000U)
#define PCC2_PCC_SAI3_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_SAI3_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_SAI3_CGC_SHIFT)) & PCC2_PCC_SAI3_CGC_MASK)

#define PCC2_PCC_SAI3_PR_MASK                    (0x80000000U)
#define PCC2_PCC_SAI3_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_SAI3_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_SAI3_PR_SHIFT)) & PCC2_PCC_SAI3_PR_MASK)
/*! @} */

/*! @name PCC_MICFIL - PCC MICFIL Register */
/*! @{ */

#define PCC2_PCC_MICFIL_SSADO_MASK               (0xC00000U)
#define PCC2_PCC_MICFIL_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC2_PCC_MICFIL_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_MICFIL_SSADO_SHIFT)) & PCC2_PCC_MICFIL_SSADO_MASK)

#define PCC2_PCC_MICFIL_SWRST_MASK               (0x10000000U)
#define PCC2_PCC_MICFIL_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC2_PCC_MICFIL_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_MICFIL_SWRST_SHIFT)) & PCC2_PCC_MICFIL_SWRST_MASK)

#define PCC2_PCC_MICFIL_CGC_MASK                 (0x40000000U)
#define PCC2_PCC_MICFIL_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC2_PCC_MICFIL_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_MICFIL_CGC_SHIFT)) & PCC2_PCC_MICFIL_CGC_MASK)

#define PCC2_PCC_MICFIL_PR_MASK                  (0x80000000U)
#define PCC2_PCC_MICFIL_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC2_PCC_MICFIL_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_MICFIL_PR_SHIFT)) & PCC2_PCC_MICFIL_PR_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PCC2_Register_Masks */


/* PCC2 - Peripheral instance base addresses */
/** Peripheral PCC2 base address */
#define PCC2_BASE                                (0x28102000u)
/** Peripheral PCC2 base pointer */
#define PCC2                                     ((PCC2_Type *)PCC2_BASE)
/** Array initializer of PCC2 peripheral base addresses */
#define PCC2_BASE_ADDRS                          { PCC2_BASE }
/** Array initializer of PCC2 peripheral base pointers */
#define PCC2_BASE_PTRS                           { PCC2 }

/*!
 * @}
 */ /* end of group PCC2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PCC3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PCC3_Peripheral_Access_Layer PCC3 Peripheral Access Layer
 * @{
 */

/** PCC3 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[4];
  __IO uint32_t PCC_DMA1_MP;                       /**< PCC DMA1_MP Register, offset: 0x4 */
  __IO uint32_t PCC_DMA1_CH0;                      /**< PCC DMA1_CH0 Register, offset: 0x8 */
  __IO uint32_t PCC_DMA1_CH1;                      /**< PCC DMA1_CH1 Register, offset: 0xC */
  __IO uint32_t PCC_DMA1_CH2;                      /**< PCC DMA1_CH2 Register, offset: 0x10 */
  __IO uint32_t PCC_DMA1_CH3;                      /**< PCC DMA1_CH3 Register, offset: 0x14 */
  __IO uint32_t PCC_DMA1_CH4;                      /**< PCC DMA1_CH4 Register, offset: 0x18 */
  __IO uint32_t PCC_DMA1_CH5;                      /**< PCC DMA1_CH5 Register, offset: 0x1C */
  __IO uint32_t PCC_DMA1_CH6;                      /**< PCC DMA1_CH6 Register, offset: 0x20 */
  __IO uint32_t PCC_DMA1_CH7;                      /**< PCC DMA1_CH7 Register, offset: 0x24 */
  __IO uint32_t PCC_DMA1_CH8;                      /**< PCC DMA1_CH8 Register, offset: 0x28 */
  __IO uint32_t PCC_DMA1_CH9;                      /**< PCC DMA1_CH9 Register, offset: 0x2C */
  __IO uint32_t PCC_DMA1_CH10;                     /**< PCC DMA1_CH10 Register, offset: 0x30 */
  __IO uint32_t PCC_DMA1_CH11;                     /**< PCC DMA1_CH11 Register, offset: 0x34 */
  __IO uint32_t PCC_DMA1_CH12;                     /**< PCC DMA1_CH12 Register, offset: 0x38 */
  __IO uint32_t PCC_DMA1_CH13;                     /**< PCC DMA1_CH13 Register, offset: 0x3C */
  __IO uint32_t PCC_DMA1_CH14;                     /**< PCC DMA1_CH14 Register, offset: 0x40 */
  __IO uint32_t PCC_DMA1_CH15;                     /**< PCC DMA1_CH15 Register, offset: 0x44 */
  __IO uint32_t PCC_DMA1_CH16;                     /**< PCC DMA1_CH16 Register, offset: 0x48 */
  __IO uint32_t PCC_DMA1_CH17;                     /**< PCC DMA1_CH17 Register, offset: 0x4C */
  __IO uint32_t PCC_DMA1_CH18;                     /**< PCC DMA1_CH18 Register, offset: 0x50 */
  __IO uint32_t PCC_DMA1_CH19;                     /**< PCC DMA1_CH19 Register, offset: 0x54 */
  __IO uint32_t PCC_DMA1_CH20;                     /**< PCC DMA1_CH20 Register, offset: 0x58 */
  __IO uint32_t PCC_DMA1_CH21;                     /**< PCC DMA1_CH21 Register, offset: 0x5C */
  __IO uint32_t PCC_DMA1_CH22;                     /**< PCC DMA1_CH22 Register, offset: 0x60 */
  __IO uint32_t PCC_DMA1_CH23;                     /**< PCC DMA1_CH23 Register, offset: 0x64 */
  __IO uint32_t PCC_DMA1_CH24;                     /**< PCC DMA1_CH24 Register, offset: 0x68 */
  __IO uint32_t PCC_DMA1_CH25;                     /**< PCC DMA1_CH25 Register, offset: 0x6C */
  __IO uint32_t PCC_DMA1_CH26;                     /**< PCC DMA1_CH26 Register, offset: 0x70 */
  __IO uint32_t PCC_DMA1_CH27;                     /**< PCC DMA1_CH27 Register, offset: 0x74 */
  __IO uint32_t PCC_DMA1_CH28;                     /**< PCC DMA1_CH28 Register, offset: 0x78 */
  __IO uint32_t PCC_DMA1_CH29;                     /**< PCC DMA1_CH29 Register, offset: 0x7C */
  __IO uint32_t PCC_DMA1_CH30;                     /**< PCC DMA1_CH30 Register, offset: 0x80 */
  __IO uint32_t PCC_DMA1_CH31;                     /**< PCC DMA1_CH31 Register, offset: 0x84 */
  __IO uint32_t PCC_MU0_B;                         /**< PCC MU0_B Register, offset: 0x88 */
  __IO uint32_t PCC_MU3_A;                         /**< PCC MU3_A Register, offset: 0x8C */
       uint8_t RESERVED_1[8];
  __IO uint32_t PCC_WUU1;                          /**< PCC WUU1 Register, offset: 0x98 */
  __IO uint32_t PCC_SYSPM1;                        /**< PCC SYSPM1 Register, offset: 0x9C */
  __IO uint32_t PCC_UPOWER_MUA_APD;                /**< PCC uPower_MUA_APD Register, offset: 0xA0 */
       uint8_t RESERVED_2[4];
  __IO uint32_t PCC_WDOG3;                         /**< PCC WDOG3 Register, offset: 0xA8 */
  __IO uint32_t PCC_WDOG4;                         /**< PCC WDOG4 Register, offset: 0xAC */
       uint8_t RESERVED_3[8];
  __IO uint32_t PCC_CAAM;                          /**< PCC CAAM Register, offset: 0xB8 */
  __IO uint32_t PCC_XRDC_MGR;                      /**< PCC XRDC_MGR Register, offset: 0xBC */
  __IO uint32_t PCC_SEMA42_1;                      /**< PCC SEMA42_1 Register, offset: 0xC0 */
  __IO uint32_t PCC_ROMCP1;                        /**< PCC ROMCP1 Register, offset: 0xC4 */
  __IO uint32_t PCC_LPIT1;                         /**< PCC LPIT1 Register, offset: 0xC8 */
  __IO uint32_t PCC_TPM4;                          /**< PCC TPM4 Register, offset: 0xCC */
  __IO uint32_t PCC_TPM5;                          /**< PCC TPM5 Register, offset: 0xD0 */
  __IO uint32_t PCC_FLEXIO1;                       /**< PCC FlexIO1 Register, offset: 0xD4 */
  __IO uint32_t PCC_I3C2;                          /**< PCC I3C2 Register, offset: 0xD8 */
  __IO uint32_t PCC_LPI2C4;                        /**< PCC LPI2C4 Register, offset: 0xDC */
  __IO uint32_t PCC_LPI2C5;                        /**< PCC LPI2C5 Register, offset: 0xE0 */
  __IO uint32_t PCC_LPUART4;                       /**< PCC LPUART4 Register, offset: 0xE4 */
  __IO uint32_t PCC_LPUART5;                       /**< PCC LPUART5 Register, offset: 0xE8 */
  __IO uint32_t PCC_LPSPI4;                        /**< PCC LPSPI4 Register, offset: 0xEC */
  __IO uint32_t PCC_LPSPI5;                        /**< PCC LPSPI5 Register, offset: 0xF0 */
} PCC3_Type;

/* ----------------------------------------------------------------------------
   -- PCC3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PCC3_Register_Masks PCC3 Register Masks
 * @{
 */

/*! @name PCC_DMA1_MP - PCC DMA1_MP Register */
/*! @{ */

#define PCC3_PCC_DMA1_MP_SSADO_MASK              (0xC00000U)
#define PCC3_PCC_DMA1_MP_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_MP_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_MP_SSADO_SHIFT)) & PCC3_PCC_DMA1_MP_SSADO_MASK)

#define PCC3_PCC_DMA1_MP_CGC_MASK                (0x40000000U)
#define PCC3_PCC_DMA1_MP_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_MP_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_MP_CGC_SHIFT)) & PCC3_PCC_DMA1_MP_CGC_MASK)

#define PCC3_PCC_DMA1_MP_PR_MASK                 (0x80000000U)
#define PCC3_PCC_DMA1_MP_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_MP_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_MP_PR_SHIFT)) & PCC3_PCC_DMA1_MP_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH0 - PCC DMA1_CH0 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH0_SSADO_MASK             (0xC00000U)
#define PCC3_PCC_DMA1_CH0_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH0_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH0_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH0_SSADO_MASK)

#define PCC3_PCC_DMA1_CH0_CGC_MASK               (0x40000000U)
#define PCC3_PCC_DMA1_CH0_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH0_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH0_CGC_SHIFT)) & PCC3_PCC_DMA1_CH0_CGC_MASK)

#define PCC3_PCC_DMA1_CH0_PR_MASK                (0x80000000U)
#define PCC3_PCC_DMA1_CH0_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH0_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH0_PR_SHIFT)) & PCC3_PCC_DMA1_CH0_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH1 - PCC DMA1_CH1 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH1_SSADO_MASK             (0xC00000U)
#define PCC3_PCC_DMA1_CH1_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH1_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH1_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH1_SSADO_MASK)

#define PCC3_PCC_DMA1_CH1_CGC_MASK               (0x40000000U)
#define PCC3_PCC_DMA1_CH1_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH1_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH1_CGC_SHIFT)) & PCC3_PCC_DMA1_CH1_CGC_MASK)

#define PCC3_PCC_DMA1_CH1_PR_MASK                (0x80000000U)
#define PCC3_PCC_DMA1_CH1_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH1_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH1_PR_SHIFT)) & PCC3_PCC_DMA1_CH1_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH2 - PCC DMA1_CH2 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH2_SSADO_MASK             (0xC00000U)
#define PCC3_PCC_DMA1_CH2_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH2_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH2_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH2_SSADO_MASK)

#define PCC3_PCC_DMA1_CH2_CGC_MASK               (0x40000000U)
#define PCC3_PCC_DMA1_CH2_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH2_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH2_CGC_SHIFT)) & PCC3_PCC_DMA1_CH2_CGC_MASK)

#define PCC3_PCC_DMA1_CH2_PR_MASK                (0x80000000U)
#define PCC3_PCC_DMA1_CH2_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH2_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH2_PR_SHIFT)) & PCC3_PCC_DMA1_CH2_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH3 - PCC DMA1_CH3 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH3_SSADO_MASK             (0xC00000U)
#define PCC3_PCC_DMA1_CH3_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH3_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH3_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH3_SSADO_MASK)

#define PCC3_PCC_DMA1_CH3_CGC_MASK               (0x40000000U)
#define PCC3_PCC_DMA1_CH3_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH3_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH3_CGC_SHIFT)) & PCC3_PCC_DMA1_CH3_CGC_MASK)

#define PCC3_PCC_DMA1_CH3_PR_MASK                (0x80000000U)
#define PCC3_PCC_DMA1_CH3_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH3_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH3_PR_SHIFT)) & PCC3_PCC_DMA1_CH3_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH4 - PCC DMA1_CH4 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH4_SSADO_MASK             (0xC00000U)
#define PCC3_PCC_DMA1_CH4_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH4_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH4_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH4_SSADO_MASK)

#define PCC3_PCC_DMA1_CH4_CGC_MASK               (0x40000000U)
#define PCC3_PCC_DMA1_CH4_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH4_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH4_CGC_SHIFT)) & PCC3_PCC_DMA1_CH4_CGC_MASK)

#define PCC3_PCC_DMA1_CH4_PR_MASK                (0x80000000U)
#define PCC3_PCC_DMA1_CH4_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH4_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH4_PR_SHIFT)) & PCC3_PCC_DMA1_CH4_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH5 - PCC DMA1_CH5 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH5_SSADO_MASK             (0xC00000U)
#define PCC3_PCC_DMA1_CH5_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH5_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH5_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH5_SSADO_MASK)

#define PCC3_PCC_DMA1_CH5_CGC_MASK               (0x40000000U)
#define PCC3_PCC_DMA1_CH5_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH5_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH5_CGC_SHIFT)) & PCC3_PCC_DMA1_CH5_CGC_MASK)

#define PCC3_PCC_DMA1_CH5_PR_MASK                (0x80000000U)
#define PCC3_PCC_DMA1_CH5_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH5_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH5_PR_SHIFT)) & PCC3_PCC_DMA1_CH5_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH6 - PCC DMA1_CH6 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH6_SSADO_MASK             (0xC00000U)
#define PCC3_PCC_DMA1_CH6_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH6_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH6_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH6_SSADO_MASK)

#define PCC3_PCC_DMA1_CH6_CGC_MASK               (0x40000000U)
#define PCC3_PCC_DMA1_CH6_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH6_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH6_CGC_SHIFT)) & PCC3_PCC_DMA1_CH6_CGC_MASK)

#define PCC3_PCC_DMA1_CH6_PR_MASK                (0x80000000U)
#define PCC3_PCC_DMA1_CH6_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH6_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH6_PR_SHIFT)) & PCC3_PCC_DMA1_CH6_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH7 - PCC DMA1_CH7 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH7_SSADO_MASK             (0xC00000U)
#define PCC3_PCC_DMA1_CH7_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH7_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH7_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH7_SSADO_MASK)

#define PCC3_PCC_DMA1_CH7_CGC_MASK               (0x40000000U)
#define PCC3_PCC_DMA1_CH7_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH7_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH7_CGC_SHIFT)) & PCC3_PCC_DMA1_CH7_CGC_MASK)

#define PCC3_PCC_DMA1_CH7_PR_MASK                (0x80000000U)
#define PCC3_PCC_DMA1_CH7_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH7_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH7_PR_SHIFT)) & PCC3_PCC_DMA1_CH7_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH8 - PCC DMA1_CH8 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH8_SSADO_MASK             (0xC00000U)
#define PCC3_PCC_DMA1_CH8_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH8_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH8_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH8_SSADO_MASK)

#define PCC3_PCC_DMA1_CH8_CGC_MASK               (0x40000000U)
#define PCC3_PCC_DMA1_CH8_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH8_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH8_CGC_SHIFT)) & PCC3_PCC_DMA1_CH8_CGC_MASK)

#define PCC3_PCC_DMA1_CH8_PR_MASK                (0x80000000U)
#define PCC3_PCC_DMA1_CH8_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH8_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH8_PR_SHIFT)) & PCC3_PCC_DMA1_CH8_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH9 - PCC DMA1_CH9 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH9_SSADO_MASK             (0xC00000U)
#define PCC3_PCC_DMA1_CH9_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH9_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH9_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH9_SSADO_MASK)

#define PCC3_PCC_DMA1_CH9_CGC_MASK               (0x40000000U)
#define PCC3_PCC_DMA1_CH9_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH9_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH9_CGC_SHIFT)) & PCC3_PCC_DMA1_CH9_CGC_MASK)

#define PCC3_PCC_DMA1_CH9_PR_MASK                (0x80000000U)
#define PCC3_PCC_DMA1_CH9_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH9_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH9_PR_SHIFT)) & PCC3_PCC_DMA1_CH9_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH10 - PCC DMA1_CH10 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH10_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH10_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH10_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH10_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH10_SSADO_MASK)

#define PCC3_PCC_DMA1_CH10_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH10_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH10_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH10_CGC_SHIFT)) & PCC3_PCC_DMA1_CH10_CGC_MASK)

#define PCC3_PCC_DMA1_CH10_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH10_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH10_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH10_PR_SHIFT)) & PCC3_PCC_DMA1_CH10_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH11 - PCC DMA1_CH11 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH11_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH11_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH11_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH11_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH11_SSADO_MASK)

#define PCC3_PCC_DMA1_CH11_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH11_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH11_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH11_CGC_SHIFT)) & PCC3_PCC_DMA1_CH11_CGC_MASK)

#define PCC3_PCC_DMA1_CH11_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH11_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH11_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH11_PR_SHIFT)) & PCC3_PCC_DMA1_CH11_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH12 - PCC DMA1_CH12 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH12_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH12_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH12_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH12_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH12_SSADO_MASK)

#define PCC3_PCC_DMA1_CH12_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH12_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH12_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH12_CGC_SHIFT)) & PCC3_PCC_DMA1_CH12_CGC_MASK)

#define PCC3_PCC_DMA1_CH12_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH12_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH12_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH12_PR_SHIFT)) & PCC3_PCC_DMA1_CH12_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH13 - PCC DMA1_CH13 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH13_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH13_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH13_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH13_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH13_SSADO_MASK)

#define PCC3_PCC_DMA1_CH13_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH13_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH13_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH13_CGC_SHIFT)) & PCC3_PCC_DMA1_CH13_CGC_MASK)

#define PCC3_PCC_DMA1_CH13_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH13_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH13_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH13_PR_SHIFT)) & PCC3_PCC_DMA1_CH13_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH14 - PCC DMA1_CH14 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH14_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH14_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH14_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH14_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH14_SSADO_MASK)

#define PCC3_PCC_DMA1_CH14_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH14_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH14_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH14_CGC_SHIFT)) & PCC3_PCC_DMA1_CH14_CGC_MASK)

#define PCC3_PCC_DMA1_CH14_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH14_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH14_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH14_PR_SHIFT)) & PCC3_PCC_DMA1_CH14_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH15 - PCC DMA1_CH15 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH15_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH15_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH15_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH15_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH15_SSADO_MASK)

#define PCC3_PCC_DMA1_CH15_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH15_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH15_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH15_CGC_SHIFT)) & PCC3_PCC_DMA1_CH15_CGC_MASK)

#define PCC3_PCC_DMA1_CH15_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH15_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH15_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH15_PR_SHIFT)) & PCC3_PCC_DMA1_CH15_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH16 - PCC DMA1_CH16 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH16_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH16_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH16_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH16_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH16_SSADO_MASK)

#define PCC3_PCC_DMA1_CH16_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH16_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH16_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH16_CGC_SHIFT)) & PCC3_PCC_DMA1_CH16_CGC_MASK)

#define PCC3_PCC_DMA1_CH16_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH16_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH16_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH16_PR_SHIFT)) & PCC3_PCC_DMA1_CH16_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH17 - PCC DMA1_CH17 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH17_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH17_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH17_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH17_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH17_SSADO_MASK)

#define PCC3_PCC_DMA1_CH17_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH17_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH17_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH17_CGC_SHIFT)) & PCC3_PCC_DMA1_CH17_CGC_MASK)

#define PCC3_PCC_DMA1_CH17_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH17_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH17_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH17_PR_SHIFT)) & PCC3_PCC_DMA1_CH17_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH18 - PCC DMA1_CH18 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH18_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH18_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH18_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH18_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH18_SSADO_MASK)

#define PCC3_PCC_DMA1_CH18_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH18_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH18_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH18_CGC_SHIFT)) & PCC3_PCC_DMA1_CH18_CGC_MASK)

#define PCC3_PCC_DMA1_CH18_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH18_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH18_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH18_PR_SHIFT)) & PCC3_PCC_DMA1_CH18_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH19 - PCC DMA1_CH19 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH19_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH19_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH19_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH19_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH19_SSADO_MASK)

#define PCC3_PCC_DMA1_CH19_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH19_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH19_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH19_CGC_SHIFT)) & PCC3_PCC_DMA1_CH19_CGC_MASK)

#define PCC3_PCC_DMA1_CH19_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH19_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH19_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH19_PR_SHIFT)) & PCC3_PCC_DMA1_CH19_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH20 - PCC DMA1_CH20 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH20_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH20_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH20_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH20_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH20_SSADO_MASK)

#define PCC3_PCC_DMA1_CH20_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH20_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH20_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH20_CGC_SHIFT)) & PCC3_PCC_DMA1_CH20_CGC_MASK)

#define PCC3_PCC_DMA1_CH20_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH20_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH20_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH20_PR_SHIFT)) & PCC3_PCC_DMA1_CH20_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH21 - PCC DMA1_CH21 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH21_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH21_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH21_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH21_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH21_SSADO_MASK)

#define PCC3_PCC_DMA1_CH21_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH21_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH21_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH21_CGC_SHIFT)) & PCC3_PCC_DMA1_CH21_CGC_MASK)

#define PCC3_PCC_DMA1_CH21_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH21_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH21_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH21_PR_SHIFT)) & PCC3_PCC_DMA1_CH21_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH22 - PCC DMA1_CH22 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH22_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH22_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH22_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH22_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH22_SSADO_MASK)

#define PCC3_PCC_DMA1_CH22_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH22_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH22_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH22_CGC_SHIFT)) & PCC3_PCC_DMA1_CH22_CGC_MASK)

#define PCC3_PCC_DMA1_CH22_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH22_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH22_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH22_PR_SHIFT)) & PCC3_PCC_DMA1_CH22_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH23 - PCC DMA1_CH23 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH23_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH23_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH23_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH23_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH23_SSADO_MASK)

#define PCC3_PCC_DMA1_CH23_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH23_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH23_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH23_CGC_SHIFT)) & PCC3_PCC_DMA1_CH23_CGC_MASK)

#define PCC3_PCC_DMA1_CH23_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH23_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH23_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH23_PR_SHIFT)) & PCC3_PCC_DMA1_CH23_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH24 - PCC DMA1_CH24 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH24_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH24_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH24_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH24_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH24_SSADO_MASK)

#define PCC3_PCC_DMA1_CH24_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH24_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH24_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH24_CGC_SHIFT)) & PCC3_PCC_DMA1_CH24_CGC_MASK)

#define PCC3_PCC_DMA1_CH24_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH24_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH24_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH24_PR_SHIFT)) & PCC3_PCC_DMA1_CH24_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH25 - PCC DMA1_CH25 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH25_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH25_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH25_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH25_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH25_SSADO_MASK)

#define PCC3_PCC_DMA1_CH25_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH25_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH25_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH25_CGC_SHIFT)) & PCC3_PCC_DMA1_CH25_CGC_MASK)

#define PCC3_PCC_DMA1_CH25_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH25_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH25_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH25_PR_SHIFT)) & PCC3_PCC_DMA1_CH25_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH26 - PCC DMA1_CH26 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH26_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH26_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH26_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH26_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH26_SSADO_MASK)

#define PCC3_PCC_DMA1_CH26_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH26_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH26_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH26_CGC_SHIFT)) & PCC3_PCC_DMA1_CH26_CGC_MASK)

#define PCC3_PCC_DMA1_CH26_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH26_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH26_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH26_PR_SHIFT)) & PCC3_PCC_DMA1_CH26_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH27 - PCC DMA1_CH27 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH27_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH27_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH27_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH27_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH27_SSADO_MASK)

#define PCC3_PCC_DMA1_CH27_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH27_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH27_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH27_CGC_SHIFT)) & PCC3_PCC_DMA1_CH27_CGC_MASK)

#define PCC3_PCC_DMA1_CH27_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH27_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH27_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH27_PR_SHIFT)) & PCC3_PCC_DMA1_CH27_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH28 - PCC DMA1_CH28 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH28_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH28_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH28_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH28_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH28_SSADO_MASK)

#define PCC3_PCC_DMA1_CH28_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH28_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH28_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH28_CGC_SHIFT)) & PCC3_PCC_DMA1_CH28_CGC_MASK)

#define PCC3_PCC_DMA1_CH28_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH28_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH28_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH28_PR_SHIFT)) & PCC3_PCC_DMA1_CH28_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH29 - PCC DMA1_CH29 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH29_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH29_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH29_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH29_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH29_SSADO_MASK)

#define PCC3_PCC_DMA1_CH29_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH29_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH29_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH29_CGC_SHIFT)) & PCC3_PCC_DMA1_CH29_CGC_MASK)

#define PCC3_PCC_DMA1_CH29_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH29_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH29_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH29_PR_SHIFT)) & PCC3_PCC_DMA1_CH29_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH30 - PCC DMA1_CH30 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH30_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH30_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH30_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH30_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH30_SSADO_MASK)

#define PCC3_PCC_DMA1_CH30_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH30_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH30_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH30_CGC_SHIFT)) & PCC3_PCC_DMA1_CH30_CGC_MASK)

#define PCC3_PCC_DMA1_CH30_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH30_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH30_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH30_PR_SHIFT)) & PCC3_PCC_DMA1_CH30_PR_MASK)
/*! @} */

/*! @name PCC_DMA1_CH31 - PCC DMA1_CH31 Register */
/*! @{ */

#define PCC3_PCC_DMA1_CH31_SSADO_MASK            (0xC00000U)
#define PCC3_PCC_DMA1_CH31_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_DMA1_CH31_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH31_SSADO_SHIFT)) & PCC3_PCC_DMA1_CH31_SSADO_MASK)

#define PCC3_PCC_DMA1_CH31_CGC_MASK              (0x40000000U)
#define PCC3_PCC_DMA1_CH31_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_DMA1_CH31_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH31_CGC_SHIFT)) & PCC3_PCC_DMA1_CH31_CGC_MASK)

#define PCC3_PCC_DMA1_CH31_PR_MASK               (0x80000000U)
#define PCC3_PCC_DMA1_CH31_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_DMA1_CH31_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DMA1_CH31_PR_SHIFT)) & PCC3_PCC_DMA1_CH31_PR_MASK)
/*! @} */

/*! @name PCC_MU0_B - PCC MU0_B Register */
/*! @{ */

#define PCC3_PCC_MU0_B_SSADO_MASK                (0xC00000U)
#define PCC3_PCC_MU0_B_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_MU0_B_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_MU0_B_SSADO_SHIFT)) & PCC3_PCC_MU0_B_SSADO_MASK)

#define PCC3_PCC_MU0_B_CGC_MASK                  (0x40000000U)
#define PCC3_PCC_MU0_B_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_MU0_B_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_MU0_B_CGC_SHIFT)) & PCC3_PCC_MU0_B_CGC_MASK)

#define PCC3_PCC_MU0_B_PR_MASK                   (0x80000000U)
#define PCC3_PCC_MU0_B_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_MU0_B_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_MU0_B_PR_SHIFT)) & PCC3_PCC_MU0_B_PR_MASK)
/*! @} */

/*! @name PCC_MU3_A - PCC MU3_A Register */
/*! @{ */

#define PCC3_PCC_MU3_A_SSADO_MASK                (0xC00000U)
#define PCC3_PCC_MU3_A_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_MU3_A_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_MU3_A_SSADO_SHIFT)) & PCC3_PCC_MU3_A_SSADO_MASK)

#define PCC3_PCC_MU3_A_CGC_MASK                  (0x40000000U)
#define PCC3_PCC_MU3_A_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_MU3_A_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_MU3_A_CGC_SHIFT)) & PCC3_PCC_MU3_A_CGC_MASK)

#define PCC3_PCC_MU3_A_PR_MASK                   (0x80000000U)
#define PCC3_PCC_MU3_A_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_MU3_A_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_MU3_A_PR_SHIFT)) & PCC3_PCC_MU3_A_PR_MASK)
/*! @} */

/*! @name PCC_WUU1 - PCC WUU1 Register */
/*! @{ */

#define PCC3_PCC_WUU1_SSADO_MASK                 (0xC00000U)
#define PCC3_PCC_WUU1_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_WUU1_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WUU1_SSADO_SHIFT)) & PCC3_PCC_WUU1_SSADO_MASK)

#define PCC3_PCC_WUU1_CGC_MASK                   (0x40000000U)
#define PCC3_PCC_WUU1_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_WUU1_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WUU1_CGC_SHIFT)) & PCC3_PCC_WUU1_CGC_MASK)

#define PCC3_PCC_WUU1_PR_MASK                    (0x80000000U)
#define PCC3_PCC_WUU1_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_WUU1_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WUU1_PR_SHIFT)) & PCC3_PCC_WUU1_PR_MASK)
/*! @} */

/*! @name PCC_SYSPM1 - PCC SYSPM1 Register */
/*! @{ */

#define PCC3_PCC_SYSPM1_SSADO_MASK               (0xC00000U)
#define PCC3_PCC_SYSPM1_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_SYSPM1_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_SYSPM1_SSADO_SHIFT)) & PCC3_PCC_SYSPM1_SSADO_MASK)

#define PCC3_PCC_SYSPM1_CGC_MASK                 (0x40000000U)
#define PCC3_PCC_SYSPM1_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_SYSPM1_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_SYSPM1_CGC_SHIFT)) & PCC3_PCC_SYSPM1_CGC_MASK)

#define PCC3_PCC_SYSPM1_PR_MASK                  (0x80000000U)
#define PCC3_PCC_SYSPM1_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_SYSPM1_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_SYSPM1_PR_SHIFT)) & PCC3_PCC_SYSPM1_PR_MASK)
/*! @} */

/*! @name PCC_UPOWER_MUA_APD - PCC uPower_MUA_APD Register */
/*! @{ */

#define PCC3_PCC_UPOWER_MUA_APD_SSADO_MASK       (0xC00000U)
#define PCC3_PCC_UPOWER_MUA_APD_SSADO_SHIFT      (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_UPOWER_MUA_APD_SSADO(x)         (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_UPOWER_MUA_APD_SSADO_SHIFT)) & PCC3_PCC_UPOWER_MUA_APD_SSADO_MASK)

#define PCC3_PCC_UPOWER_MUA_APD_CGC_MASK         (0x40000000U)
#define PCC3_PCC_UPOWER_MUA_APD_CGC_SHIFT        (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_UPOWER_MUA_APD_CGC(x)           (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_UPOWER_MUA_APD_CGC_SHIFT)) & PCC3_PCC_UPOWER_MUA_APD_CGC_MASK)

#define PCC3_PCC_UPOWER_MUA_APD_PR_MASK          (0x80000000U)
#define PCC3_PCC_UPOWER_MUA_APD_PR_SHIFT         (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_UPOWER_MUA_APD_PR(x)            (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_UPOWER_MUA_APD_PR_SHIFT)) & PCC3_PCC_UPOWER_MUA_APD_PR_MASK)
/*! @} */

/*! @name PCC_WDOG3 - PCC WDOG3 Register */
/*! @{ */

#define PCC3_PCC_WDOG3_PCD_MASK                  (0x7U)
#define PCC3_PCC_WDOG3_PCD_SHIFT                 (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC3_PCC_WDOG3_PCD(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG3_PCD_SHIFT)) & PCC3_PCC_WDOG3_PCD_MASK)

#define PCC3_PCC_WDOG3_FRAC_MASK                 (0x8U)
#define PCC3_PCC_WDOG3_FRAC_SHIFT                (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC3_PCC_WDOG3_FRAC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG3_FRAC_SHIFT)) & PCC3_PCC_WDOG3_FRAC_MASK)

#define PCC3_PCC_WDOG3_SSADO_MASK                (0xC00000U)
#define PCC3_PCC_WDOG3_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_WDOG3_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG3_SSADO_SHIFT)) & PCC3_PCC_WDOG3_SSADO_MASK)

#define PCC3_PCC_WDOG3_PCS_MASK                  (0x7000000U)
#define PCC3_PCC_WDOG3_PCS_SHIFT                 (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC3_PCC_WDOG3_PCS(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG3_PCS_SHIFT)) & PCC3_PCC_WDOG3_PCS_MASK)

#define PCC3_PCC_WDOG3_SWRST_MASK                (0x10000000U)
#define PCC3_PCC_WDOG3_SWRST_SHIFT               (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC3_PCC_WDOG3_SWRST(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG3_SWRST_SHIFT)) & PCC3_PCC_WDOG3_SWRST_MASK)

#define PCC3_PCC_WDOG3_CGC_MASK                  (0x40000000U)
#define PCC3_PCC_WDOG3_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_WDOG3_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG3_CGC_SHIFT)) & PCC3_PCC_WDOG3_CGC_MASK)

#define PCC3_PCC_WDOG3_PR_MASK                   (0x80000000U)
#define PCC3_PCC_WDOG3_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_WDOG3_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG3_PR_SHIFT)) & PCC3_PCC_WDOG3_PR_MASK)
/*! @} */

/*! @name PCC_WDOG4 - PCC WDOG4 Register */
/*! @{ */

#define PCC3_PCC_WDOG4_PCD_MASK                  (0x7U)
#define PCC3_PCC_WDOG4_PCD_SHIFT                 (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC3_PCC_WDOG4_PCD(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG4_PCD_SHIFT)) & PCC3_PCC_WDOG4_PCD_MASK)

#define PCC3_PCC_WDOG4_FRAC_MASK                 (0x8U)
#define PCC3_PCC_WDOG4_FRAC_SHIFT                (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC3_PCC_WDOG4_FRAC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG4_FRAC_SHIFT)) & PCC3_PCC_WDOG4_FRAC_MASK)

#define PCC3_PCC_WDOG4_SSADO_MASK                (0xC00000U)
#define PCC3_PCC_WDOG4_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_WDOG4_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG4_SSADO_SHIFT)) & PCC3_PCC_WDOG4_SSADO_MASK)

#define PCC3_PCC_WDOG4_PCS_MASK                  (0x7000000U)
#define PCC3_PCC_WDOG4_PCS_SHIFT                 (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC3_PCC_WDOG4_PCS(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG4_PCS_SHIFT)) & PCC3_PCC_WDOG4_PCS_MASK)

#define PCC3_PCC_WDOG4_SWRST_MASK                (0x10000000U)
#define PCC3_PCC_WDOG4_SWRST_SHIFT               (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC3_PCC_WDOG4_SWRST(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG4_SWRST_SHIFT)) & PCC3_PCC_WDOG4_SWRST_MASK)

#define PCC3_PCC_WDOG4_CGC_MASK                  (0x40000000U)
#define PCC3_PCC_WDOG4_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_WDOG4_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG4_CGC_SHIFT)) & PCC3_PCC_WDOG4_CGC_MASK)

#define PCC3_PCC_WDOG4_PR_MASK                   (0x80000000U)
#define PCC3_PCC_WDOG4_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_WDOG4_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_WDOG4_PR_SHIFT)) & PCC3_PCC_WDOG4_PR_MASK)
/*! @} */

/*! @name PCC_CAAM - PCC CAAM Register */
/*! @{ */

#define PCC3_PCC_CAAM_SSADO_MASK                 (0xC00000U)
#define PCC3_PCC_CAAM_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_CAAM_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_CAAM_SSADO_SHIFT)) & PCC3_PCC_CAAM_SSADO_MASK)

#define PCC3_PCC_CAAM_CGC_MASK                   (0x40000000U)
#define PCC3_PCC_CAAM_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_CAAM_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_CAAM_CGC_SHIFT)) & PCC3_PCC_CAAM_CGC_MASK)

#define PCC3_PCC_CAAM_PR_MASK                    (0x80000000U)
#define PCC3_PCC_CAAM_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_CAAM_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_CAAM_PR_SHIFT)) & PCC3_PCC_CAAM_PR_MASK)
/*! @} */

/*! @name PCC_XRDC_MGR - PCC XRDC_MGR Register */
/*! @{ */

#define PCC3_PCC_XRDC_MGR_SSADO_MASK             (0xC00000U)
#define PCC3_PCC_XRDC_MGR_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_XRDC_MGR_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_XRDC_MGR_SSADO_SHIFT)) & PCC3_PCC_XRDC_MGR_SSADO_MASK)

#define PCC3_PCC_XRDC_MGR_CGC_MASK               (0x40000000U)
#define PCC3_PCC_XRDC_MGR_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_XRDC_MGR_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_XRDC_MGR_CGC_SHIFT)) & PCC3_PCC_XRDC_MGR_CGC_MASK)

#define PCC3_PCC_XRDC_MGR_PR_MASK                (0x80000000U)
#define PCC3_PCC_XRDC_MGR_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_XRDC_MGR_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_XRDC_MGR_PR_SHIFT)) & PCC3_PCC_XRDC_MGR_PR_MASK)
/*! @} */

/*! @name PCC_SEMA42_1 - PCC SEMA42_1 Register */
/*! @{ */

#define PCC3_PCC_SEMA42_1_SSADO_MASK             (0xC00000U)
#define PCC3_PCC_SEMA42_1_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_SEMA42_1_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_SEMA42_1_SSADO_SHIFT)) & PCC3_PCC_SEMA42_1_SSADO_MASK)

#define PCC3_PCC_SEMA42_1_CGC_MASK               (0x40000000U)
#define PCC3_PCC_SEMA42_1_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_SEMA42_1_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_SEMA42_1_CGC_SHIFT)) & PCC3_PCC_SEMA42_1_CGC_MASK)

#define PCC3_PCC_SEMA42_1_PR_MASK                (0x80000000U)
#define PCC3_PCC_SEMA42_1_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_SEMA42_1_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_SEMA42_1_PR_SHIFT)) & PCC3_PCC_SEMA42_1_PR_MASK)
/*! @} */

/*! @name PCC_ROMCP1 - PCC ROMCP1 Register */
/*! @{ */

#define PCC3_PCC_ROMCP1_SSADO_MASK               (0xC00000U)
#define PCC3_PCC_ROMCP1_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_ROMCP1_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_ROMCP1_SSADO_SHIFT)) & PCC3_PCC_ROMCP1_SSADO_MASK)

#define PCC3_PCC_ROMCP1_CGC_MASK                 (0x40000000U)
#define PCC3_PCC_ROMCP1_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_ROMCP1_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_ROMCP1_CGC_SHIFT)) & PCC3_PCC_ROMCP1_CGC_MASK)

#define PCC3_PCC_ROMCP1_PR_MASK                  (0x80000000U)
#define PCC3_PCC_ROMCP1_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_ROMCP1_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_ROMCP1_PR_SHIFT)) & PCC3_PCC_ROMCP1_PR_MASK)
/*! @} */

/*! @name PCC_LPIT1 - PCC LPIT1 Register */
/*! @{ */

#define PCC3_PCC_LPIT1_PCD_MASK                  (0x7U)
#define PCC3_PCC_LPIT1_PCD_SHIFT                 (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC3_PCC_LPIT1_PCD(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPIT1_PCD_SHIFT)) & PCC3_PCC_LPIT1_PCD_MASK)

#define PCC3_PCC_LPIT1_FRAC_MASK                 (0x8U)
#define PCC3_PCC_LPIT1_FRAC_SHIFT                (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC3_PCC_LPIT1_FRAC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPIT1_FRAC_SHIFT)) & PCC3_PCC_LPIT1_FRAC_MASK)

#define PCC3_PCC_LPIT1_SSADO_MASK                (0xC00000U)
#define PCC3_PCC_LPIT1_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_LPIT1_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPIT1_SSADO_SHIFT)) & PCC3_PCC_LPIT1_SSADO_MASK)

#define PCC3_PCC_LPIT1_PCS_MASK                  (0x7000000U)
#define PCC3_PCC_LPIT1_PCS_SHIFT                 (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC3_PCC_LPIT1_PCS(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPIT1_PCS_SHIFT)) & PCC3_PCC_LPIT1_PCS_MASK)

#define PCC3_PCC_LPIT1_SWRST_MASK                (0x10000000U)
#define PCC3_PCC_LPIT1_SWRST_SHIFT               (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC3_PCC_LPIT1_SWRST(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPIT1_SWRST_SHIFT)) & PCC3_PCC_LPIT1_SWRST_MASK)

#define PCC3_PCC_LPIT1_CGC_MASK                  (0x40000000U)
#define PCC3_PCC_LPIT1_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_LPIT1_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPIT1_CGC_SHIFT)) & PCC3_PCC_LPIT1_CGC_MASK)

#define PCC3_PCC_LPIT1_PR_MASK                   (0x80000000U)
#define PCC3_PCC_LPIT1_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_LPIT1_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPIT1_PR_SHIFT)) & PCC3_PCC_LPIT1_PR_MASK)
/*! @} */

/*! @name PCC_TPM4 - PCC TPM4 Register */
/*! @{ */

#define PCC3_PCC_TPM4_PCD_MASK                   (0x7U)
#define PCC3_PCC_TPM4_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC3_PCC_TPM4_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM4_PCD_SHIFT)) & PCC3_PCC_TPM4_PCD_MASK)

#define PCC3_PCC_TPM4_FRAC_MASK                  (0x8U)
#define PCC3_PCC_TPM4_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC3_PCC_TPM4_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM4_FRAC_SHIFT)) & PCC3_PCC_TPM4_FRAC_MASK)

#define PCC3_PCC_TPM4_SSADO_MASK                 (0xC00000U)
#define PCC3_PCC_TPM4_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_TPM4_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM4_SSADO_SHIFT)) & PCC3_PCC_TPM4_SSADO_MASK)

#define PCC3_PCC_TPM4_PCS_MASK                   (0x7000000U)
#define PCC3_PCC_TPM4_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC3_PCC_TPM4_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM4_PCS_SHIFT)) & PCC3_PCC_TPM4_PCS_MASK)

#define PCC3_PCC_TPM4_SWRST_MASK                 (0x10000000U)
#define PCC3_PCC_TPM4_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC3_PCC_TPM4_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM4_SWRST_SHIFT)) & PCC3_PCC_TPM4_SWRST_MASK)

#define PCC3_PCC_TPM4_CGC_MASK                   (0x40000000U)
#define PCC3_PCC_TPM4_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_TPM4_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM4_CGC_SHIFT)) & PCC3_PCC_TPM4_CGC_MASK)

#define PCC3_PCC_TPM4_PR_MASK                    (0x80000000U)
#define PCC3_PCC_TPM4_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_TPM4_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM4_PR_SHIFT)) & PCC3_PCC_TPM4_PR_MASK)
/*! @} */

/*! @name PCC_TPM5 - PCC TPM5 Register */
/*! @{ */

#define PCC3_PCC_TPM5_PCD_MASK                   (0x7U)
#define PCC3_PCC_TPM5_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC3_PCC_TPM5_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM5_PCD_SHIFT)) & PCC3_PCC_TPM5_PCD_MASK)

#define PCC3_PCC_TPM5_FRAC_MASK                  (0x8U)
#define PCC3_PCC_TPM5_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC3_PCC_TPM5_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM5_FRAC_SHIFT)) & PCC3_PCC_TPM5_FRAC_MASK)

#define PCC3_PCC_TPM5_SSADO_MASK                 (0xC00000U)
#define PCC3_PCC_TPM5_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_TPM5_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM5_SSADO_SHIFT)) & PCC3_PCC_TPM5_SSADO_MASK)

#define PCC3_PCC_TPM5_PCS_MASK                   (0x7000000U)
#define PCC3_PCC_TPM5_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC3_PCC_TPM5_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM5_PCS_SHIFT)) & PCC3_PCC_TPM5_PCS_MASK)

#define PCC3_PCC_TPM5_SWRST_MASK                 (0x10000000U)
#define PCC3_PCC_TPM5_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC3_PCC_TPM5_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM5_SWRST_SHIFT)) & PCC3_PCC_TPM5_SWRST_MASK)

#define PCC3_PCC_TPM5_CGC_MASK                   (0x40000000U)
#define PCC3_PCC_TPM5_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_TPM5_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM5_CGC_SHIFT)) & PCC3_PCC_TPM5_CGC_MASK)

#define PCC3_PCC_TPM5_PR_MASK                    (0x80000000U)
#define PCC3_PCC_TPM5_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_TPM5_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM5_PR_SHIFT)) & PCC3_PCC_TPM5_PR_MASK)
/*! @} */

/*! @name PCC_FLEXIO1 - PCC FlexIO1 Register */
/*! @{ */

#define PCC3_PCC_FLEXIO1_PCD_MASK                (0x7U)
#define PCC3_PCC_FLEXIO1_PCD_SHIFT               (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC3_PCC_FLEXIO1_PCD(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_FLEXIO1_PCD_SHIFT)) & PCC3_PCC_FLEXIO1_PCD_MASK)

#define PCC3_PCC_FLEXIO1_FRAC_MASK               (0x8U)
#define PCC3_PCC_FLEXIO1_FRAC_SHIFT              (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC3_PCC_FLEXIO1_FRAC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_FLEXIO1_FRAC_SHIFT)) & PCC3_PCC_FLEXIO1_FRAC_MASK)

#define PCC3_PCC_FLEXIO1_SSADO_MASK              (0xC00000U)
#define PCC3_PCC_FLEXIO1_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_FLEXIO1_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_FLEXIO1_SSADO_SHIFT)) & PCC3_PCC_FLEXIO1_SSADO_MASK)

#define PCC3_PCC_FLEXIO1_PCS_MASK                (0x7000000U)
#define PCC3_PCC_FLEXIO1_PCS_SHIFT               (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC3_PCC_FLEXIO1_PCS(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_FLEXIO1_PCS_SHIFT)) & PCC3_PCC_FLEXIO1_PCS_MASK)

#define PCC3_PCC_FLEXIO1_SWRST_MASK              (0x10000000U)
#define PCC3_PCC_FLEXIO1_SWRST_SHIFT             (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC3_PCC_FLEXIO1_SWRST(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_FLEXIO1_SWRST_SHIFT)) & PCC3_PCC_FLEXIO1_SWRST_MASK)

#define PCC3_PCC_FLEXIO1_CGC_MASK                (0x40000000U)
#define PCC3_PCC_FLEXIO1_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_FLEXIO1_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_FLEXIO1_CGC_SHIFT)) & PCC3_PCC_FLEXIO1_CGC_MASK)

#define PCC3_PCC_FLEXIO1_PR_MASK                 (0x80000000U)
#define PCC3_PCC_FLEXIO1_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_FLEXIO1_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_FLEXIO1_PR_SHIFT)) & PCC3_PCC_FLEXIO1_PR_MASK)
/*! @} */

/*! @name PCC_I3C2 - PCC I3C2 Register */
/*! @{ */

#define PCC3_PCC_I3C2_PCD_MASK                   (0x7U)
#define PCC3_PCC_I3C2_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC3_PCC_I3C2_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_I3C2_PCD_SHIFT)) & PCC3_PCC_I3C2_PCD_MASK)

#define PCC3_PCC_I3C2_FRAC_MASK                  (0x8U)
#define PCC3_PCC_I3C2_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC3_PCC_I3C2_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_I3C2_FRAC_SHIFT)) & PCC3_PCC_I3C2_FRAC_MASK)

#define PCC3_PCC_I3C2_SSADO_MASK                 (0xC00000U)
#define PCC3_PCC_I3C2_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_I3C2_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_I3C2_SSADO_SHIFT)) & PCC3_PCC_I3C2_SSADO_MASK)

#define PCC3_PCC_I3C2_PCS_MASK                   (0x7000000U)
#define PCC3_PCC_I3C2_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC3_PCC_I3C2_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_I3C2_PCS_SHIFT)) & PCC3_PCC_I3C2_PCS_MASK)

#define PCC3_PCC_I3C2_SWRST_MASK                 (0x10000000U)
#define PCC3_PCC_I3C2_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC3_PCC_I3C2_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_I3C2_SWRST_SHIFT)) & PCC3_PCC_I3C2_SWRST_MASK)

#define PCC3_PCC_I3C2_CGC_MASK                   (0x40000000U)
#define PCC3_PCC_I3C2_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_I3C2_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_I3C2_CGC_SHIFT)) & PCC3_PCC_I3C2_CGC_MASK)

#define PCC3_PCC_I3C2_PR_MASK                    (0x80000000U)
#define PCC3_PCC_I3C2_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_I3C2_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_I3C2_PR_SHIFT)) & PCC3_PCC_I3C2_PR_MASK)
/*! @} */

/*! @name PCC_LPI2C4 - PCC LPI2C4 Register */
/*! @{ */

#define PCC3_PCC_LPI2C4_PCD_MASK                 (0x7U)
#define PCC3_PCC_LPI2C4_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC3_PCC_LPI2C4_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C4_PCD_SHIFT)) & PCC3_PCC_LPI2C4_PCD_MASK)

#define PCC3_PCC_LPI2C4_FRAC_MASK                (0x8U)
#define PCC3_PCC_LPI2C4_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC3_PCC_LPI2C4_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C4_FRAC_SHIFT)) & PCC3_PCC_LPI2C4_FRAC_MASK)

#define PCC3_PCC_LPI2C4_SSADO_MASK               (0xC00000U)
#define PCC3_PCC_LPI2C4_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_LPI2C4_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C4_SSADO_SHIFT)) & PCC3_PCC_LPI2C4_SSADO_MASK)

#define PCC3_PCC_LPI2C4_PCS_MASK                 (0x7000000U)
#define PCC3_PCC_LPI2C4_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC3_PCC_LPI2C4_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C4_PCS_SHIFT)) & PCC3_PCC_LPI2C4_PCS_MASK)

#define PCC3_PCC_LPI2C4_SWRST_MASK               (0x10000000U)
#define PCC3_PCC_LPI2C4_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC3_PCC_LPI2C4_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C4_SWRST_SHIFT)) & PCC3_PCC_LPI2C4_SWRST_MASK)

#define PCC3_PCC_LPI2C4_CGC_MASK                 (0x40000000U)
#define PCC3_PCC_LPI2C4_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_LPI2C4_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C4_CGC_SHIFT)) & PCC3_PCC_LPI2C4_CGC_MASK)

#define PCC3_PCC_LPI2C4_PR_MASK                  (0x80000000U)
#define PCC3_PCC_LPI2C4_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_LPI2C4_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C4_PR_SHIFT)) & PCC3_PCC_LPI2C4_PR_MASK)
/*! @} */

/*! @name PCC_LPI2C5 - PCC LPI2C5 Register */
/*! @{ */

#define PCC3_PCC_LPI2C5_PCD_MASK                 (0x7U)
#define PCC3_PCC_LPI2C5_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC3_PCC_LPI2C5_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C5_PCD_SHIFT)) & PCC3_PCC_LPI2C5_PCD_MASK)

#define PCC3_PCC_LPI2C5_FRAC_MASK                (0x8U)
#define PCC3_PCC_LPI2C5_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC3_PCC_LPI2C5_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C5_FRAC_SHIFT)) & PCC3_PCC_LPI2C5_FRAC_MASK)

#define PCC3_PCC_LPI2C5_SSADO_MASK               (0xC00000U)
#define PCC3_PCC_LPI2C5_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_LPI2C5_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C5_SSADO_SHIFT)) & PCC3_PCC_LPI2C5_SSADO_MASK)

#define PCC3_PCC_LPI2C5_PCS_MASK                 (0x7000000U)
#define PCC3_PCC_LPI2C5_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC3_PCC_LPI2C5_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C5_PCS_SHIFT)) & PCC3_PCC_LPI2C5_PCS_MASK)

#define PCC3_PCC_LPI2C5_SWRST_MASK               (0x10000000U)
#define PCC3_PCC_LPI2C5_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC3_PCC_LPI2C5_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C5_SWRST_SHIFT)) & PCC3_PCC_LPI2C5_SWRST_MASK)

#define PCC3_PCC_LPI2C5_CGC_MASK                 (0x40000000U)
#define PCC3_PCC_LPI2C5_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_LPI2C5_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C5_CGC_SHIFT)) & PCC3_PCC_LPI2C5_CGC_MASK)

#define PCC3_PCC_LPI2C5_PR_MASK                  (0x80000000U)
#define PCC3_PCC_LPI2C5_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_LPI2C5_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C5_PR_SHIFT)) & PCC3_PCC_LPI2C5_PR_MASK)
/*! @} */

/*! @name PCC_LPUART4 - PCC LPUART4 Register */
/*! @{ */

#define PCC3_PCC_LPUART4_PCD_MASK                (0x7U)
#define PCC3_PCC_LPUART4_PCD_SHIFT               (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC3_PCC_LPUART4_PCD(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART4_PCD_SHIFT)) & PCC3_PCC_LPUART4_PCD_MASK)

#define PCC3_PCC_LPUART4_FRAC_MASK               (0x8U)
#define PCC3_PCC_LPUART4_FRAC_SHIFT              (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC3_PCC_LPUART4_FRAC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART4_FRAC_SHIFT)) & PCC3_PCC_LPUART4_FRAC_MASK)

#define PCC3_PCC_LPUART4_SSADO_MASK              (0xC00000U)
#define PCC3_PCC_LPUART4_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_LPUART4_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART4_SSADO_SHIFT)) & PCC3_PCC_LPUART4_SSADO_MASK)

#define PCC3_PCC_LPUART4_PCS_MASK                (0x7000000U)
#define PCC3_PCC_LPUART4_PCS_SHIFT               (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC3_PCC_LPUART4_PCS(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART4_PCS_SHIFT)) & PCC3_PCC_LPUART4_PCS_MASK)

#define PCC3_PCC_LPUART4_SWRST_MASK              (0x10000000U)
#define PCC3_PCC_LPUART4_SWRST_SHIFT             (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC3_PCC_LPUART4_SWRST(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART4_SWRST_SHIFT)) & PCC3_PCC_LPUART4_SWRST_MASK)

#define PCC3_PCC_LPUART4_CGC_MASK                (0x40000000U)
#define PCC3_PCC_LPUART4_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_LPUART4_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART4_CGC_SHIFT)) & PCC3_PCC_LPUART4_CGC_MASK)

#define PCC3_PCC_LPUART4_PR_MASK                 (0x80000000U)
#define PCC3_PCC_LPUART4_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_LPUART4_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART4_PR_SHIFT)) & PCC3_PCC_LPUART4_PR_MASK)
/*! @} */

/*! @name PCC_LPUART5 - PCC LPUART5 Register */
/*! @{ */

#define PCC3_PCC_LPUART5_PCD_MASK                (0x7U)
#define PCC3_PCC_LPUART5_PCD_SHIFT               (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC3_PCC_LPUART5_PCD(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART5_PCD_SHIFT)) & PCC3_PCC_LPUART5_PCD_MASK)

#define PCC3_PCC_LPUART5_FRAC_MASK               (0x8U)
#define PCC3_PCC_LPUART5_FRAC_SHIFT              (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC3_PCC_LPUART5_FRAC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART5_FRAC_SHIFT)) & PCC3_PCC_LPUART5_FRAC_MASK)

#define PCC3_PCC_LPUART5_SSADO_MASK              (0xC00000U)
#define PCC3_PCC_LPUART5_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_LPUART5_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART5_SSADO_SHIFT)) & PCC3_PCC_LPUART5_SSADO_MASK)

#define PCC3_PCC_LPUART5_PCS_MASK                (0x7000000U)
#define PCC3_PCC_LPUART5_PCS_SHIFT               (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC3_PCC_LPUART5_PCS(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART5_PCS_SHIFT)) & PCC3_PCC_LPUART5_PCS_MASK)

#define PCC3_PCC_LPUART5_SWRST_MASK              (0x10000000U)
#define PCC3_PCC_LPUART5_SWRST_SHIFT             (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC3_PCC_LPUART5_SWRST(x)                (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART5_SWRST_SHIFT)) & PCC3_PCC_LPUART5_SWRST_MASK)

#define PCC3_PCC_LPUART5_CGC_MASK                (0x40000000U)
#define PCC3_PCC_LPUART5_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_LPUART5_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART5_CGC_SHIFT)) & PCC3_PCC_LPUART5_CGC_MASK)

#define PCC3_PCC_LPUART5_PR_MASK                 (0x80000000U)
#define PCC3_PCC_LPUART5_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_LPUART5_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART5_PR_SHIFT)) & PCC3_PCC_LPUART5_PR_MASK)
/*! @} */

/*! @name PCC_LPSPI4 - PCC LPSPI4 Register */
/*! @{ */

#define PCC3_PCC_LPSPI4_PCD_MASK                 (0x7U)
#define PCC3_PCC_LPSPI4_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC3_PCC_LPSPI4_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI4_PCD_SHIFT)) & PCC3_PCC_LPSPI4_PCD_MASK)

#define PCC3_PCC_LPSPI4_FRAC_MASK                (0x8U)
#define PCC3_PCC_LPSPI4_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC3_PCC_LPSPI4_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI4_FRAC_SHIFT)) & PCC3_PCC_LPSPI4_FRAC_MASK)

#define PCC3_PCC_LPSPI4_SSADO_MASK               (0xC00000U)
#define PCC3_PCC_LPSPI4_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_LPSPI4_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI4_SSADO_SHIFT)) & PCC3_PCC_LPSPI4_SSADO_MASK)

#define PCC3_PCC_LPSPI4_PCS_MASK                 (0x7000000U)
#define PCC3_PCC_LPSPI4_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC3_PCC_LPSPI4_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI4_PCS_SHIFT)) & PCC3_PCC_LPSPI4_PCS_MASK)

#define PCC3_PCC_LPSPI4_SWRST_MASK               (0x10000000U)
#define PCC3_PCC_LPSPI4_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC3_PCC_LPSPI4_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI4_SWRST_SHIFT)) & PCC3_PCC_LPSPI4_SWRST_MASK)

#define PCC3_PCC_LPSPI4_CGC_MASK                 (0x40000000U)
#define PCC3_PCC_LPSPI4_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_LPSPI4_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI4_CGC_SHIFT)) & PCC3_PCC_LPSPI4_CGC_MASK)

#define PCC3_PCC_LPSPI4_PR_MASK                  (0x80000000U)
#define PCC3_PCC_LPSPI4_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_LPSPI4_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI4_PR_SHIFT)) & PCC3_PCC_LPSPI4_PR_MASK)
/*! @} */

/*! @name PCC_LPSPI5 - PCC LPSPI5 Register */
/*! @{ */

#define PCC3_PCC_LPSPI5_PCD_MASK                 (0x7U)
#define PCC3_PCC_LPSPI5_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC3_PCC_LPSPI5_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI5_PCD_SHIFT)) & PCC3_PCC_LPSPI5_PCD_MASK)

#define PCC3_PCC_LPSPI5_FRAC_MASK                (0x8U)
#define PCC3_PCC_LPSPI5_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC3_PCC_LPSPI5_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI5_FRAC_SHIFT)) & PCC3_PCC_LPSPI5_FRAC_MASK)

#define PCC3_PCC_LPSPI5_SSADO_MASK               (0xC00000U)
#define PCC3_PCC_LPSPI5_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC3_PCC_LPSPI5_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI5_SSADO_SHIFT)) & PCC3_PCC_LPSPI5_SSADO_MASK)

#define PCC3_PCC_LPSPI5_PCS_MASK                 (0x7000000U)
#define PCC3_PCC_LPSPI5_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC3_PCC_LPSPI5_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI5_PCS_SHIFT)) & PCC3_PCC_LPSPI5_PCS_MASK)

#define PCC3_PCC_LPSPI5_SWRST_MASK               (0x10000000U)
#define PCC3_PCC_LPSPI5_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC3_PCC_LPSPI5_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI5_SWRST_SHIFT)) & PCC3_PCC_LPSPI5_SWRST_MASK)

#define PCC3_PCC_LPSPI5_CGC_MASK                 (0x40000000U)
#define PCC3_PCC_LPSPI5_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC3_PCC_LPSPI5_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI5_CGC_SHIFT)) & PCC3_PCC_LPSPI5_CGC_MASK)

#define PCC3_PCC_LPSPI5_PR_MASK                  (0x80000000U)
#define PCC3_PCC_LPSPI5_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC3_PCC_LPSPI5_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPSPI5_PR_SHIFT)) & PCC3_PCC_LPSPI5_PR_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PCC3_Register_Masks */


/* PCC3 - Peripheral instance base addresses */
/** Peripheral PCC3 base address */
#define PCC3_BASE                                (0x292D0000u)
/** Peripheral PCC3 base pointer */
#define PCC3                                     ((PCC3_Type *)PCC3_BASE)
/** Array initializer of PCC3 peripheral base addresses */
#define PCC3_BASE_ADDRS                          { PCC3_BASE }
/** Array initializer of PCC3 peripheral base pointers */
#define PCC3_BASE_PTRS                           { PCC3 }

/*!
 * @}
 */ /* end of group PCC3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PCC4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PCC4_Peripheral_Access_Layer PCC4 Peripheral Access Layer
 * @{
 */

/** PCC4 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[4];
  __IO uint32_t PCC_FLEXSPI2;                      /**< PCC FlexSPI2 Register, offset: 0x4 */
  __IO uint32_t PCC_TPM6;                          /**< PCC TPM6 Register, offset: 0x8 */
  __IO uint32_t PCC_TPM7;                          /**< PCC TPM7 Register, offset: 0xC */
  __IO uint32_t PCC_LPI2C6;                        /**< PCC LPI2C6 Register, offset: 0x10 */
  __IO uint32_t PCC_LPI2C7;                        /**< PCC LPI2C7 Register, offset: 0x14 */
  __IO uint32_t PCC_LPUART6;                       /**< PCC LPUART6 Register, offset: 0x18 */
  __IO uint32_t PCC_LPUART7;                       /**< PCC LPUART7 Register, offset: 0x1C */
  __IO uint32_t PCC_SAI4;                          /**< PCC SAI4 Register, offset: 0x20 */
  __IO uint32_t PCC_SAI5;                          /**< PCC SAI5 Register, offset: 0x24 */
  __IO uint32_t PCC_DIGITAL_FILTER_E;              /**< PCC DIGITAL_FILTER_E Register, offset: 0x28 */
  __IO uint32_t PCC_DIGITAL_FILTER_F;              /**< PCC DIGITAL_FILTER_F Register, offset: 0x2C */
       uint8_t RESERVED_1[4];
  __IO uint32_t PCC_USDHC0;                        /**< PCC uSDHC0 Register, offset: 0x34 */
  __IO uint32_t PCC_USDHC1;                        /**< PCC uSDHC1 Register, offset: 0x38 */
  __IO uint32_t PCC_USDHC2;                        /**< PCC uSDHC2 Register, offset: 0x3C */
  __IO uint32_t PCC_USB0;                          /**< PCC USB0 Register, offset: 0x40 */
  __IO uint32_t PCC_USB0_PHY;                      /**< PCC USB0_PHY Register, offset: 0x44 */
  __IO uint32_t PCC_USB1;                          /**< PCC USB1 Register, offset: 0x48 */
  __IO uint32_t PCC_USB1_PHY;                      /**< PCC USB1_PHY Register, offset: 0x4C */
  __IO uint32_t PCC_USB_XBAR;                      /**< PCC USB_XBAR Register, offset: 0x50 */
  __IO uint32_t PCC_ENET;                          /**< PCC ENET Register, offset: 0x54 */
       uint8_t RESERVED_2[32];
  __IO uint32_t PCC_RGPIOE;                        /**< PCC RGPIOE Register, offset: 0x78 */
  __IO uint32_t PCC_RGPIOF;                        /**< PCC RGPIOF Register, offset: 0x7C */
} PCC4_Type;

/* ----------------------------------------------------------------------------
   -- PCC4 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PCC4_Register_Masks PCC4 Register Masks
 * @{
 */

/*! @name PCC_FLEXSPI2 - PCC FlexSPI2 Register */
/*! @{ */

#define PCC4_PCC_FLEXSPI2_PCD_MASK               (0x7U)
#define PCC4_PCC_FLEXSPI2_PCD_SHIFT              (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC4_PCC_FLEXSPI2_PCD(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_FLEXSPI2_PCD_SHIFT)) & PCC4_PCC_FLEXSPI2_PCD_MASK)

#define PCC4_PCC_FLEXSPI2_FRAC_MASK              (0x8U)
#define PCC4_PCC_FLEXSPI2_FRAC_SHIFT             (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC4_PCC_FLEXSPI2_FRAC(x)                (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_FLEXSPI2_FRAC_SHIFT)) & PCC4_PCC_FLEXSPI2_FRAC_MASK)

#define PCC4_PCC_FLEXSPI2_SSADO_MASK             (0xC00000U)
#define PCC4_PCC_FLEXSPI2_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_FLEXSPI2_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_FLEXSPI2_SSADO_SHIFT)) & PCC4_PCC_FLEXSPI2_SSADO_MASK)

#define PCC4_PCC_FLEXSPI2_PCS_MASK               (0x7000000U)
#define PCC4_PCC_FLEXSPI2_PCS_SHIFT              (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC4_PCC_FLEXSPI2_PCS(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_FLEXSPI2_PCS_SHIFT)) & PCC4_PCC_FLEXSPI2_PCS_MASK)

#define PCC4_PCC_FLEXSPI2_SWRST_MASK             (0x10000000U)
#define PCC4_PCC_FLEXSPI2_SWRST_SHIFT            (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_FLEXSPI2_SWRST(x)               (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_FLEXSPI2_SWRST_SHIFT)) & PCC4_PCC_FLEXSPI2_SWRST_MASK)

#define PCC4_PCC_FLEXSPI2_CGC_MASK               (0x40000000U)
#define PCC4_PCC_FLEXSPI2_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_FLEXSPI2_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_FLEXSPI2_CGC_SHIFT)) & PCC4_PCC_FLEXSPI2_CGC_MASK)

#define PCC4_PCC_FLEXSPI2_PR_MASK                (0x80000000U)
#define PCC4_PCC_FLEXSPI2_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_FLEXSPI2_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_FLEXSPI2_PR_SHIFT)) & PCC4_PCC_FLEXSPI2_PR_MASK)
/*! @} */

/*! @name PCC_TPM6 - PCC TPM6 Register */
/*! @{ */

#define PCC4_PCC_TPM6_PCD_MASK                   (0x7U)
#define PCC4_PCC_TPM6_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC4_PCC_TPM6_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM6_PCD_SHIFT)) & PCC4_PCC_TPM6_PCD_MASK)

#define PCC4_PCC_TPM6_FRAC_MASK                  (0x8U)
#define PCC4_PCC_TPM6_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC4_PCC_TPM6_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM6_FRAC_SHIFT)) & PCC4_PCC_TPM6_FRAC_MASK)

#define PCC4_PCC_TPM6_SSADO_MASK                 (0xC00000U)
#define PCC4_PCC_TPM6_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_TPM6_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM6_SSADO_SHIFT)) & PCC4_PCC_TPM6_SSADO_MASK)

#define PCC4_PCC_TPM6_PCS_MASK                   (0x7000000U)
#define PCC4_PCC_TPM6_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC4_PCC_TPM6_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM6_PCS_SHIFT)) & PCC4_PCC_TPM6_PCS_MASK)

#define PCC4_PCC_TPM6_SWRST_MASK                 (0x10000000U)
#define PCC4_PCC_TPM6_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_TPM6_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM6_SWRST_SHIFT)) & PCC4_PCC_TPM6_SWRST_MASK)

#define PCC4_PCC_TPM6_CGC_MASK                   (0x40000000U)
#define PCC4_PCC_TPM6_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_TPM6_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM6_CGC_SHIFT)) & PCC4_PCC_TPM6_CGC_MASK)

#define PCC4_PCC_TPM6_PR_MASK                    (0x80000000U)
#define PCC4_PCC_TPM6_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_TPM6_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM6_PR_SHIFT)) & PCC4_PCC_TPM6_PR_MASK)
/*! @} */

/*! @name PCC_TPM7 - PCC TPM7 Register */
/*! @{ */

#define PCC4_PCC_TPM7_PCD_MASK                   (0x7U)
#define PCC4_PCC_TPM7_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC4_PCC_TPM7_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM7_PCD_SHIFT)) & PCC4_PCC_TPM7_PCD_MASK)

#define PCC4_PCC_TPM7_FRAC_MASK                  (0x8U)
#define PCC4_PCC_TPM7_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC4_PCC_TPM7_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM7_FRAC_SHIFT)) & PCC4_PCC_TPM7_FRAC_MASK)

#define PCC4_PCC_TPM7_SSADO_MASK                 (0xC00000U)
#define PCC4_PCC_TPM7_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_TPM7_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM7_SSADO_SHIFT)) & PCC4_PCC_TPM7_SSADO_MASK)

#define PCC4_PCC_TPM7_PCS_MASK                   (0x7000000U)
#define PCC4_PCC_TPM7_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC4_PCC_TPM7_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM7_PCS_SHIFT)) & PCC4_PCC_TPM7_PCS_MASK)

#define PCC4_PCC_TPM7_SWRST_MASK                 (0x10000000U)
#define PCC4_PCC_TPM7_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_TPM7_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM7_SWRST_SHIFT)) & PCC4_PCC_TPM7_SWRST_MASK)

#define PCC4_PCC_TPM7_CGC_MASK                   (0x40000000U)
#define PCC4_PCC_TPM7_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_TPM7_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM7_CGC_SHIFT)) & PCC4_PCC_TPM7_CGC_MASK)

#define PCC4_PCC_TPM7_PR_MASK                    (0x80000000U)
#define PCC4_PCC_TPM7_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_TPM7_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_TPM7_PR_SHIFT)) & PCC4_PCC_TPM7_PR_MASK)
/*! @} */

/*! @name PCC_LPI2C6 - PCC LPI2C6 Register */
/*! @{ */

#define PCC4_PCC_LPI2C6_PCD_MASK                 (0x7U)
#define PCC4_PCC_LPI2C6_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC4_PCC_LPI2C6_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C6_PCD_SHIFT)) & PCC4_PCC_LPI2C6_PCD_MASK)

#define PCC4_PCC_LPI2C6_FRAC_MASK                (0x8U)
#define PCC4_PCC_LPI2C6_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC4_PCC_LPI2C6_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C6_FRAC_SHIFT)) & PCC4_PCC_LPI2C6_FRAC_MASK)

#define PCC4_PCC_LPI2C6_SSADO_MASK               (0xC00000U)
#define PCC4_PCC_LPI2C6_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_LPI2C6_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C6_SSADO_SHIFT)) & PCC4_PCC_LPI2C6_SSADO_MASK)

#define PCC4_PCC_LPI2C6_PCS_MASK                 (0x7000000U)
#define PCC4_PCC_LPI2C6_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC4_PCC_LPI2C6_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C6_PCS_SHIFT)) & PCC4_PCC_LPI2C6_PCS_MASK)

#define PCC4_PCC_LPI2C6_SWRST_MASK               (0x10000000U)
#define PCC4_PCC_LPI2C6_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_LPI2C6_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C6_SWRST_SHIFT)) & PCC4_PCC_LPI2C6_SWRST_MASK)

#define PCC4_PCC_LPI2C6_CGC_MASK                 (0x40000000U)
#define PCC4_PCC_LPI2C6_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_LPI2C6_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C6_CGC_SHIFT)) & PCC4_PCC_LPI2C6_CGC_MASK)

#define PCC4_PCC_LPI2C6_PR_MASK                  (0x80000000U)
#define PCC4_PCC_LPI2C6_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_LPI2C6_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C6_PR_SHIFT)) & PCC4_PCC_LPI2C6_PR_MASK)
/*! @} */

/*! @name PCC_LPI2C7 - PCC LPI2C7 Register */
/*! @{ */

#define PCC4_PCC_LPI2C7_PCD_MASK                 (0x7U)
#define PCC4_PCC_LPI2C7_PCD_SHIFT                (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC4_PCC_LPI2C7_PCD(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C7_PCD_SHIFT)) & PCC4_PCC_LPI2C7_PCD_MASK)

#define PCC4_PCC_LPI2C7_FRAC_MASK                (0x8U)
#define PCC4_PCC_LPI2C7_FRAC_SHIFT               (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC4_PCC_LPI2C7_FRAC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C7_FRAC_SHIFT)) & PCC4_PCC_LPI2C7_FRAC_MASK)

#define PCC4_PCC_LPI2C7_SSADO_MASK               (0xC00000U)
#define PCC4_PCC_LPI2C7_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_LPI2C7_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C7_SSADO_SHIFT)) & PCC4_PCC_LPI2C7_SSADO_MASK)

#define PCC4_PCC_LPI2C7_PCS_MASK                 (0x7000000U)
#define PCC4_PCC_LPI2C7_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC4_PCC_LPI2C7_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C7_PCS_SHIFT)) & PCC4_PCC_LPI2C7_PCS_MASK)

#define PCC4_PCC_LPI2C7_SWRST_MASK               (0x10000000U)
#define PCC4_PCC_LPI2C7_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_LPI2C7_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C7_SWRST_SHIFT)) & PCC4_PCC_LPI2C7_SWRST_MASK)

#define PCC4_PCC_LPI2C7_CGC_MASK                 (0x40000000U)
#define PCC4_PCC_LPI2C7_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_LPI2C7_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C7_CGC_SHIFT)) & PCC4_PCC_LPI2C7_CGC_MASK)

#define PCC4_PCC_LPI2C7_PR_MASK                  (0x80000000U)
#define PCC4_PCC_LPI2C7_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_LPI2C7_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPI2C7_PR_SHIFT)) & PCC4_PCC_LPI2C7_PR_MASK)
/*! @} */

/*! @name PCC_LPUART6 - PCC LPUART6 Register */
/*! @{ */

#define PCC4_PCC_LPUART6_PCD_MASK                (0x7U)
#define PCC4_PCC_LPUART6_PCD_SHIFT               (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC4_PCC_LPUART6_PCD(x)                  (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART6_PCD_SHIFT)) & PCC4_PCC_LPUART6_PCD_MASK)

#define PCC4_PCC_LPUART6_FRAC_MASK               (0x8U)
#define PCC4_PCC_LPUART6_FRAC_SHIFT              (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC4_PCC_LPUART6_FRAC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART6_FRAC_SHIFT)) & PCC4_PCC_LPUART6_FRAC_MASK)

#define PCC4_PCC_LPUART6_SSADO_MASK              (0xC00000U)
#define PCC4_PCC_LPUART6_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_LPUART6_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART6_SSADO_SHIFT)) & PCC4_PCC_LPUART6_SSADO_MASK)

#define PCC4_PCC_LPUART6_PCS_MASK                (0x7000000U)
#define PCC4_PCC_LPUART6_PCS_SHIFT               (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC4_PCC_LPUART6_PCS(x)                  (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART6_PCS_SHIFT)) & PCC4_PCC_LPUART6_PCS_MASK)

#define PCC4_PCC_LPUART6_SWRST_MASK              (0x10000000U)
#define PCC4_PCC_LPUART6_SWRST_SHIFT             (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_LPUART6_SWRST(x)                (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART6_SWRST_SHIFT)) & PCC4_PCC_LPUART6_SWRST_MASK)

#define PCC4_PCC_LPUART6_CGC_MASK                (0x40000000U)
#define PCC4_PCC_LPUART6_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_LPUART6_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART6_CGC_SHIFT)) & PCC4_PCC_LPUART6_CGC_MASK)

#define PCC4_PCC_LPUART6_PR_MASK                 (0x80000000U)
#define PCC4_PCC_LPUART6_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_LPUART6_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART6_PR_SHIFT)) & PCC4_PCC_LPUART6_PR_MASK)
/*! @} */

/*! @name PCC_LPUART7 - PCC LPUART7 Register */
/*! @{ */

#define PCC4_PCC_LPUART7_PCD_MASK                (0x7U)
#define PCC4_PCC_LPUART7_PCD_SHIFT               (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC4_PCC_LPUART7_PCD(x)                  (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART7_PCD_SHIFT)) & PCC4_PCC_LPUART7_PCD_MASK)

#define PCC4_PCC_LPUART7_FRAC_MASK               (0x8U)
#define PCC4_PCC_LPUART7_FRAC_SHIFT              (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC4_PCC_LPUART7_FRAC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART7_FRAC_SHIFT)) & PCC4_PCC_LPUART7_FRAC_MASK)

#define PCC4_PCC_LPUART7_SSADO_MASK              (0xC00000U)
#define PCC4_PCC_LPUART7_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_LPUART7_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART7_SSADO_SHIFT)) & PCC4_PCC_LPUART7_SSADO_MASK)

#define PCC4_PCC_LPUART7_PCS_MASK                (0x7000000U)
#define PCC4_PCC_LPUART7_PCS_SHIFT               (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC4_PCC_LPUART7_PCS(x)                  (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART7_PCS_SHIFT)) & PCC4_PCC_LPUART7_PCS_MASK)

#define PCC4_PCC_LPUART7_SWRST_MASK              (0x10000000U)
#define PCC4_PCC_LPUART7_SWRST_SHIFT             (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_LPUART7_SWRST(x)                (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART7_SWRST_SHIFT)) & PCC4_PCC_LPUART7_SWRST_MASK)

#define PCC4_PCC_LPUART7_CGC_MASK                (0x40000000U)
#define PCC4_PCC_LPUART7_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_LPUART7_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART7_CGC_SHIFT)) & PCC4_PCC_LPUART7_CGC_MASK)

#define PCC4_PCC_LPUART7_PR_MASK                 (0x80000000U)
#define PCC4_PCC_LPUART7_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_LPUART7_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_LPUART7_PR_SHIFT)) & PCC4_PCC_LPUART7_PR_MASK)
/*! @} */

/*! @name PCC_SAI4 - PCC SAI4 Register */
/*! @{ */

#define PCC4_PCC_SAI4_SSADO_MASK                 (0xC00000U)
#define PCC4_PCC_SAI4_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_SAI4_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_SAI4_SSADO_SHIFT)) & PCC4_PCC_SAI4_SSADO_MASK)

#define PCC4_PCC_SAI4_SWRST_MASK                 (0x10000000U)
#define PCC4_PCC_SAI4_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_SAI4_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_SAI4_SWRST_SHIFT)) & PCC4_PCC_SAI4_SWRST_MASK)

#define PCC4_PCC_SAI4_CGC_MASK                   (0x40000000U)
#define PCC4_PCC_SAI4_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_SAI4_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_SAI4_CGC_SHIFT)) & PCC4_PCC_SAI4_CGC_MASK)

#define PCC4_PCC_SAI4_PR_MASK                    (0x80000000U)
#define PCC4_PCC_SAI4_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_SAI4_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_SAI4_PR_SHIFT)) & PCC4_PCC_SAI4_PR_MASK)
/*! @} */

/*! @name PCC_SAI5 - PCC SAI5 Register */
/*! @{ */

#define PCC4_PCC_SAI5_SSADO_MASK                 (0xC00000U)
#define PCC4_PCC_SAI5_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_SAI5_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_SAI5_SSADO_SHIFT)) & PCC4_PCC_SAI5_SSADO_MASK)

#define PCC4_PCC_SAI5_SWRST_MASK                 (0x10000000U)
#define PCC4_PCC_SAI5_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_SAI5_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_SAI5_SWRST_SHIFT)) & PCC4_PCC_SAI5_SWRST_MASK)

#define PCC4_PCC_SAI5_CGC_MASK                   (0x40000000U)
#define PCC4_PCC_SAI5_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_SAI5_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_SAI5_CGC_SHIFT)) & PCC4_PCC_SAI5_CGC_MASK)

#define PCC4_PCC_SAI5_PR_MASK                    (0x80000000U)
#define PCC4_PCC_SAI5_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_SAI5_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_SAI5_PR_SHIFT)) & PCC4_PCC_SAI5_PR_MASK)
/*! @} */

/*! @name PCC_DIGITAL_FILTER_E - PCC DIGITAL_FILTER_E Register */
/*! @{ */

#define PCC4_PCC_DIGITAL_FILTER_E_SSADO_MASK     (0xC00000U)
#define PCC4_PCC_DIGITAL_FILTER_E_SSADO_SHIFT    (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_DIGITAL_FILTER_E_SSADO(x)       (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_DIGITAL_FILTER_E_SSADO_SHIFT)) & PCC4_PCC_DIGITAL_FILTER_E_SSADO_MASK)

#define PCC4_PCC_DIGITAL_FILTER_E_CGC_MASK       (0x40000000U)
#define PCC4_PCC_DIGITAL_FILTER_E_CGC_SHIFT      (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_DIGITAL_FILTER_E_CGC(x)         (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_DIGITAL_FILTER_E_CGC_SHIFT)) & PCC4_PCC_DIGITAL_FILTER_E_CGC_MASK)

#define PCC4_PCC_DIGITAL_FILTER_E_PR_MASK        (0x80000000U)
#define PCC4_PCC_DIGITAL_FILTER_E_PR_SHIFT       (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_DIGITAL_FILTER_E_PR(x)          (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_DIGITAL_FILTER_E_PR_SHIFT)) & PCC4_PCC_DIGITAL_FILTER_E_PR_MASK)
/*! @} */

/*! @name PCC_DIGITAL_FILTER_F - PCC DIGITAL_FILTER_F Register */
/*! @{ */

#define PCC4_PCC_DIGITAL_FILTER_F_SSADO_MASK     (0xC00000U)
#define PCC4_PCC_DIGITAL_FILTER_F_SSADO_SHIFT    (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_DIGITAL_FILTER_F_SSADO(x)       (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_DIGITAL_FILTER_F_SSADO_SHIFT)) & PCC4_PCC_DIGITAL_FILTER_F_SSADO_MASK)

#define PCC4_PCC_DIGITAL_FILTER_F_CGC_MASK       (0x40000000U)
#define PCC4_PCC_DIGITAL_FILTER_F_CGC_SHIFT      (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_DIGITAL_FILTER_F_CGC(x)         (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_DIGITAL_FILTER_F_CGC_SHIFT)) & PCC4_PCC_DIGITAL_FILTER_F_CGC_MASK)

#define PCC4_PCC_DIGITAL_FILTER_F_PR_MASK        (0x80000000U)
#define PCC4_PCC_DIGITAL_FILTER_F_PR_SHIFT       (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_DIGITAL_FILTER_F_PR(x)          (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_DIGITAL_FILTER_F_PR_SHIFT)) & PCC4_PCC_DIGITAL_FILTER_F_PR_MASK)
/*! @} */

/*! @name PCC_USDHC0 - PCC uSDHC0 Register */
/*! @{ */

#define PCC4_PCC_USDHC0_SSADO_MASK               (0xC00000U)
#define PCC4_PCC_USDHC0_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_USDHC0_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC0_SSADO_SHIFT)) & PCC4_PCC_USDHC0_SSADO_MASK)

#define PCC4_PCC_USDHC0_PCS_MASK                 (0x7000000U)
#define PCC4_PCC_USDHC0_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC4_PCC_USDHC0_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC0_PCS_SHIFT)) & PCC4_PCC_USDHC0_PCS_MASK)

#define PCC4_PCC_USDHC0_SWRST_MASK               (0x10000000U)
#define PCC4_PCC_USDHC0_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_USDHC0_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC0_SWRST_SHIFT)) & PCC4_PCC_USDHC0_SWRST_MASK)

#define PCC4_PCC_USDHC0_CGC_MASK                 (0x40000000U)
#define PCC4_PCC_USDHC0_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_USDHC0_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC0_CGC_SHIFT)) & PCC4_PCC_USDHC0_CGC_MASK)

#define PCC4_PCC_USDHC0_PR_MASK                  (0x80000000U)
#define PCC4_PCC_USDHC0_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_USDHC0_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC0_PR_SHIFT)) & PCC4_PCC_USDHC0_PR_MASK)
/*! @} */

/*! @name PCC_USDHC1 - PCC uSDHC1 Register */
/*! @{ */

#define PCC4_PCC_USDHC1_SSADO_MASK               (0xC00000U)
#define PCC4_PCC_USDHC1_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_USDHC1_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC1_SSADO_SHIFT)) & PCC4_PCC_USDHC1_SSADO_MASK)

#define PCC4_PCC_USDHC1_PCS_MASK                 (0x7000000U)
#define PCC4_PCC_USDHC1_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC4_PCC_USDHC1_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC1_PCS_SHIFT)) & PCC4_PCC_USDHC1_PCS_MASK)

#define PCC4_PCC_USDHC1_SWRST_MASK               (0x10000000U)
#define PCC4_PCC_USDHC1_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_USDHC1_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC1_SWRST_SHIFT)) & PCC4_PCC_USDHC1_SWRST_MASK)

#define PCC4_PCC_USDHC1_CGC_MASK                 (0x40000000U)
#define PCC4_PCC_USDHC1_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_USDHC1_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC1_CGC_SHIFT)) & PCC4_PCC_USDHC1_CGC_MASK)

#define PCC4_PCC_USDHC1_PR_MASK                  (0x80000000U)
#define PCC4_PCC_USDHC1_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_USDHC1_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC1_PR_SHIFT)) & PCC4_PCC_USDHC1_PR_MASK)
/*! @} */

/*! @name PCC_USDHC2 - PCC uSDHC2 Register */
/*! @{ */

#define PCC4_PCC_USDHC2_SSADO_MASK               (0xC00000U)
#define PCC4_PCC_USDHC2_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_USDHC2_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC2_SSADO_SHIFT)) & PCC4_PCC_USDHC2_SSADO_MASK)

#define PCC4_PCC_USDHC2_PCS_MASK                 (0x7000000U)
#define PCC4_PCC_USDHC2_PCS_SHIFT                (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC4_PCC_USDHC2_PCS(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC2_PCS_SHIFT)) & PCC4_PCC_USDHC2_PCS_MASK)

#define PCC4_PCC_USDHC2_SWRST_MASK               (0x10000000U)
#define PCC4_PCC_USDHC2_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_USDHC2_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC2_SWRST_SHIFT)) & PCC4_PCC_USDHC2_SWRST_MASK)

#define PCC4_PCC_USDHC2_CGC_MASK                 (0x40000000U)
#define PCC4_PCC_USDHC2_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_USDHC2_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC2_CGC_SHIFT)) & PCC4_PCC_USDHC2_CGC_MASK)

#define PCC4_PCC_USDHC2_PR_MASK                  (0x80000000U)
#define PCC4_PCC_USDHC2_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_USDHC2_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USDHC2_PR_SHIFT)) & PCC4_PCC_USDHC2_PR_MASK)
/*! @} */

/*! @name PCC_USB0 - PCC USB0 Register */
/*! @{ */

#define PCC4_PCC_USB0_SSADO_MASK                 (0xC00000U)
#define PCC4_PCC_USB0_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_USB0_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB0_SSADO_SHIFT)) & PCC4_PCC_USB0_SSADO_MASK)

#define PCC4_PCC_USB0_SWRST_MASK                 (0x10000000U)
#define PCC4_PCC_USB0_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_USB0_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB0_SWRST_SHIFT)) & PCC4_PCC_USB0_SWRST_MASK)

#define PCC4_PCC_USB0_CGC_MASK                   (0x40000000U)
#define PCC4_PCC_USB0_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_USB0_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB0_CGC_SHIFT)) & PCC4_PCC_USB0_CGC_MASK)

#define PCC4_PCC_USB0_PR_MASK                    (0x80000000U)
#define PCC4_PCC_USB0_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_USB0_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB0_PR_SHIFT)) & PCC4_PCC_USB0_PR_MASK)
/*! @} */

/*! @name PCC_USB0_PHY - PCC USB0_PHY Register */
/*! @{ */

#define PCC4_PCC_USB0_PHY_SSADO_MASK             (0xC00000U)
#define PCC4_PCC_USB0_PHY_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_USB0_PHY_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB0_PHY_SSADO_SHIFT)) & PCC4_PCC_USB0_PHY_SSADO_MASK)

#define PCC4_PCC_USB0_PHY_SWRST_MASK             (0x10000000U)
#define PCC4_PCC_USB0_PHY_SWRST_SHIFT            (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_USB0_PHY_SWRST(x)               (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB0_PHY_SWRST_SHIFT)) & PCC4_PCC_USB0_PHY_SWRST_MASK)

#define PCC4_PCC_USB0_PHY_CGC_MASK               (0x40000000U)
#define PCC4_PCC_USB0_PHY_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_USB0_PHY_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB0_PHY_CGC_SHIFT)) & PCC4_PCC_USB0_PHY_CGC_MASK)

#define PCC4_PCC_USB0_PHY_PR_MASK                (0x80000000U)
#define PCC4_PCC_USB0_PHY_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_USB0_PHY_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB0_PHY_PR_SHIFT)) & PCC4_PCC_USB0_PHY_PR_MASK)
/*! @} */

/*! @name PCC_USB1 - PCC USB1 Register */
/*! @{ */

#define PCC4_PCC_USB1_SSADO_MASK                 (0xC00000U)
#define PCC4_PCC_USB1_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_USB1_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB1_SSADO_SHIFT)) & PCC4_PCC_USB1_SSADO_MASK)

#define PCC4_PCC_USB1_SWRST_MASK                 (0x10000000U)
#define PCC4_PCC_USB1_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_USB1_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB1_SWRST_SHIFT)) & PCC4_PCC_USB1_SWRST_MASK)

#define PCC4_PCC_USB1_CGC_MASK                   (0x40000000U)
#define PCC4_PCC_USB1_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_USB1_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB1_CGC_SHIFT)) & PCC4_PCC_USB1_CGC_MASK)

#define PCC4_PCC_USB1_PR_MASK                    (0x80000000U)
#define PCC4_PCC_USB1_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_USB1_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB1_PR_SHIFT)) & PCC4_PCC_USB1_PR_MASK)
/*! @} */

/*! @name PCC_USB1_PHY - PCC USB1_PHY Register */
/*! @{ */

#define PCC4_PCC_USB1_PHY_SSADO_MASK             (0xC00000U)
#define PCC4_PCC_USB1_PHY_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_USB1_PHY_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB1_PHY_SSADO_SHIFT)) & PCC4_PCC_USB1_PHY_SSADO_MASK)

#define PCC4_PCC_USB1_PHY_SWRST_MASK             (0x10000000U)
#define PCC4_PCC_USB1_PHY_SWRST_SHIFT            (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_USB1_PHY_SWRST(x)               (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB1_PHY_SWRST_SHIFT)) & PCC4_PCC_USB1_PHY_SWRST_MASK)

#define PCC4_PCC_USB1_PHY_CGC_MASK               (0x40000000U)
#define PCC4_PCC_USB1_PHY_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_USB1_PHY_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB1_PHY_CGC_SHIFT)) & PCC4_PCC_USB1_PHY_CGC_MASK)

#define PCC4_PCC_USB1_PHY_PR_MASK                (0x80000000U)
#define PCC4_PCC_USB1_PHY_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_USB1_PHY_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB1_PHY_PR_SHIFT)) & PCC4_PCC_USB1_PHY_PR_MASK)
/*! @} */

/*! @name PCC_USB_XBAR - PCC USB_XBAR Register */
/*! @{ */

#define PCC4_PCC_USB_XBAR_SSADO_MASK             (0xC00000U)
#define PCC4_PCC_USB_XBAR_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_USB_XBAR_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB_XBAR_SSADO_SHIFT)) & PCC4_PCC_USB_XBAR_SSADO_MASK)

#define PCC4_PCC_USB_XBAR_CGC_MASK               (0x40000000U)
#define PCC4_PCC_USB_XBAR_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_USB_XBAR_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB_XBAR_CGC_SHIFT)) & PCC4_PCC_USB_XBAR_CGC_MASK)

#define PCC4_PCC_USB_XBAR_PR_MASK                (0x80000000U)
#define PCC4_PCC_USB_XBAR_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_USB_XBAR_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_USB_XBAR_PR_SHIFT)) & PCC4_PCC_USB_XBAR_PR_MASK)
/*! @} */

/*! @name PCC_ENET - PCC ENET Register */
/*! @{ */

#define PCC4_PCC_ENET_SSADO_MASK                 (0xC00000U)
#define PCC4_PCC_ENET_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_ENET_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_ENET_SSADO_SHIFT)) & PCC4_PCC_ENET_SSADO_MASK)

#define PCC4_PCC_ENET_SWRST_MASK                 (0x10000000U)
#define PCC4_PCC_ENET_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC4_PCC_ENET_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_ENET_SWRST_SHIFT)) & PCC4_PCC_ENET_SWRST_MASK)

#define PCC4_PCC_ENET_CGC_MASK                   (0x40000000U)
#define PCC4_PCC_ENET_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_ENET_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_ENET_CGC_SHIFT)) & PCC4_PCC_ENET_CGC_MASK)

#define PCC4_PCC_ENET_PR_MASK                    (0x80000000U)
#define PCC4_PCC_ENET_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_ENET_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_ENET_PR_SHIFT)) & PCC4_PCC_ENET_PR_MASK)
/*! @} */

/*! @name PCC_RGPIOE - PCC RGPIOE Register */
/*! @{ */

#define PCC4_PCC_RGPIOE_SSADO_MASK               (0xC00000U)
#define PCC4_PCC_RGPIOE_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_RGPIOE_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_RGPIOE_SSADO_SHIFT)) & PCC4_PCC_RGPIOE_SSADO_MASK)

#define PCC4_PCC_RGPIOE_CGC_MASK                 (0x40000000U)
#define PCC4_PCC_RGPIOE_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_RGPIOE_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_RGPIOE_CGC_SHIFT)) & PCC4_PCC_RGPIOE_CGC_MASK)

#define PCC4_PCC_RGPIOE_PR_MASK                  (0x80000000U)
#define PCC4_PCC_RGPIOE_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_RGPIOE_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_RGPIOE_PR_SHIFT)) & PCC4_PCC_RGPIOE_PR_MASK)
/*! @} */

/*! @name PCC_RGPIOF - PCC RGPIOF Register */
/*! @{ */

#define PCC4_PCC_RGPIOF_SSADO_MASK               (0xC00000U)
#define PCC4_PCC_RGPIOF_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC4_PCC_RGPIOF_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_RGPIOF_SSADO_SHIFT)) & PCC4_PCC_RGPIOF_SSADO_MASK)

#define PCC4_PCC_RGPIOF_CGC_MASK                 (0x40000000U)
#define PCC4_PCC_RGPIOF_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC4_PCC_RGPIOF_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_RGPIOF_CGC_SHIFT)) & PCC4_PCC_RGPIOF_CGC_MASK)

#define PCC4_PCC_RGPIOF_PR_MASK                  (0x80000000U)
#define PCC4_PCC_RGPIOF_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC4_PCC_RGPIOF_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC4_PCC_RGPIOF_PR_SHIFT)) & PCC4_PCC_RGPIOF_PR_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PCC4_Register_Masks */


/* PCC4 - Peripheral instance base addresses */
/** Peripheral PCC4 base address */
#define PCC4_BASE                                (0x29800000u)
/** Peripheral PCC4 base pointer */
#define PCC4                                     ((PCC4_Type *)PCC4_BASE)
/** Array initializer of PCC4 peripheral base addresses */
#define PCC4_BASE_ADDRS                          { PCC4_BASE }
/** Array initializer of PCC4 peripheral base pointers */
#define PCC4_BASE_PTRS                           { PCC4 }

/*!
 * @}
 */ /* end of group PCC4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PCC5 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PCC5_Peripheral_Access_Layer PCC5 Peripheral Access Layer
 * @{
 */

/** PCC5 - Register Layout Typedef */
typedef struct {
  __IO uint32_t PCC_DMA2_MP;                       /**< PCC DMA2_MP Register, offset: 0x0 */
  __IO uint32_t PCC_DMA2_CH0;                      /**< PCC DMA2_CH0 Register, offset: 0x4 */
  __IO uint32_t PCC_DMA2_CH1;                      /**< PCC DMA2_CH1 Register, offset: 0x8 */
  __IO uint32_t PCC_DMA2_CH2;                      /**< PCC DMA2_CH2 Register, offset: 0xC */
  __IO uint32_t PCC_DMA2_CH3;                      /**< PCC DMA2_CH3 Register, offset: 0x10 */
  __IO uint32_t PCC_DMA2_CH4;                      /**< PCC DMA2_CH4 Register, offset: 0x14 */
  __IO uint32_t PCC_DMA2_CH5;                      /**< PCC DMA2_CH5 Register, offset: 0x18 */
  __IO uint32_t PCC_DMA2_CH6;                      /**< PCC DMA2_CH6 Register, offset: 0x1C */
  __IO uint32_t PCC_DMA2_CH7;                      /**< PCC DMA2_CH7 Register, offset: 0x20 */
  __IO uint32_t PCC_DMA2_CH8;                      /**< PCC DMA2_CH8 Register, offset: 0x24 */
  __IO uint32_t PCC_DMA2_CH9;                      /**< PCC DMA2_CH9 Register, offset: 0x28 */
  __IO uint32_t PCC_DMA2_CH10;                     /**< PCC DMA2_CH10 Register, offset: 0x2C */
  __IO uint32_t PCC_DMA2_CH11;                     /**< PCC DMA2_CH11 Register, offset: 0x30 */
  __IO uint32_t PCC_DMA2_CH12;                     /**< PCC DMA2_CH12 Register, offset: 0x34 */
  __IO uint32_t PCC_DMA2_CH13;                     /**< PCC DMA2_CH13 Register, offset: 0x38 */
  __IO uint32_t PCC_DMA2_CH14;                     /**< PCC DMA2_CH14 Register, offset: 0x3C */
  __IO uint32_t PCC_DMA2_CH15;                     /**< PCC DMA2_CH15 Register, offset: 0x40 */
  __IO uint32_t PCC_DMA2_CH16;                     /**< PCC DMA2_CH16 Register, offset: 0x44 */
  __IO uint32_t PCC_DMA2_CH17;                     /**< PCC DMA2_CH17 Register, offset: 0x48 */
  __IO uint32_t PCC_DMA2_CH18;                     /**< PCC DMA2_CH18 Register, offset: 0x4C */
  __IO uint32_t PCC_DMA2_CH19;                     /**< PCC DMA2_CH19 Register, offset: 0x50 */
  __IO uint32_t PCC_DMA2_CH20;                     /**< PCC DMA2_CH20 Register, offset: 0x54 */
  __IO uint32_t PCC_DMA2_CH21;                     /**< PCC DMA2_CH21 Register, offset: 0x58 */
  __IO uint32_t PCC_DMA2_CH22;                     /**< PCC DMA2_CH22 Register, offset: 0x5C */
  __IO uint32_t PCC_DMA2_CH23;                     /**< PCC DMA2_CH23 Register, offset: 0x60 */
  __IO uint32_t PCC_DMA2_CH24;                     /**< PCC DMA2_CH24 Register, offset: 0x64 */
  __IO uint32_t PCC_DMA2_CH25;                     /**< PCC DMA2_CH25 Register, offset: 0x68 */
  __IO uint32_t PCC_DMA2_CH26;                     /**< PCC DMA2_CH26 Register, offset: 0x6C */
  __IO uint32_t PCC_DMA2_CH27;                     /**< PCC DMA2_CH27 Register, offset: 0x70 */
  __IO uint32_t PCC_DMA2_CH28;                     /**< PCC DMA2_CH28 Register, offset: 0x74 */
  __IO uint32_t PCC_DMA2_CH29;                     /**< PCC DMA2_CH29 Register, offset: 0x78 */
  __IO uint32_t PCC_DMA2_CH30;                     /**< PCC DMA2_CH30 Register, offset: 0x7C */
  __IO uint32_t PCC_DMA2_CH31;                     /**< PCC DMA2_CH31 Register, offset: 0x80 */
  __IO uint32_t PCC_MU2_B;                         /**< PCC MU2_B Register, offset: 0x84 */
  __IO uint32_t PCC_MU3_B;                         /**< PCC MU3_B Register, offset: 0x88 */
  __IO uint32_t PCC_SEMA42_2;                      /**< PCC SEMA42_2 Register, offset: 0x8C */
       uint8_t RESERVED_0[16];
  __IO uint32_t PCC_TPM8;                          /**< PCC TPM8 Register, offset: 0xA0 */
  __IO uint32_t PCC_SAI6;                          /**< PCC SAI6 Register, offset: 0xA4 */
  __IO uint32_t PCC_SAI7;                          /**< PCC SAI7 Register, offset: 0xA8 */
  __IO uint32_t PCC_SPDIF;                         /**< PCC SPDIF Register, offset: 0xAC */
  __IO uint32_t PCC_ISI;                           /**< PCC ISI Register, offset: 0xB0 */
  __IO uint32_t PCC_CSI_REGS;                      /**< PCC CSI_REGS Register, offset: 0xB4 */
       uint8_t RESERVED_1[4];
  __IO uint32_t PCC_CSI;                           /**< PCC CSI Register, offset: 0xBC */
  __IO uint32_t PCC_DSI;                           /**< PCC DSI Register, offset: 0xC0 */
       uint8_t RESERVED_2[4];
  __IO uint32_t PCC_WDOG5;                         /**< PCC WDOG5 Register, offset: 0xC8 */
  __IO uint32_t PCC_EPDC;                          /**< PCC EPDC Register, offset: 0xCC */
  __IO uint32_t PCC_PXP;                           /**< PCC PXP Register, offset: 0xD0 */
       uint8_t RESERVED_3[28];
  __IO uint32_t PCC_GPU2D;                         /**< PCC GPU2D Register, offset: 0xF0 */
  __IO uint32_t PCC_GPU3D;                         /**< PCC GPU3D Register, offset: 0xF4 */
  __IO uint32_t PCC_DC_NANO;                       /**< PCC DC_Nano Register, offset: 0xF8 */
       uint8_t RESERVED_4[12];
  __IO uint32_t PCC_LPDDR4;                        /**< PCC LPDDR4 Register, offset: 0x108 */
  __IO uint32_t PCC_CSI_CLK_UI;                    /**< PCC CSI_clk_ui Register, offset: 0x10C */
  __IO uint32_t PCC_CSI_CLK_ESC;                   /**< PCC CSI_clk_esc Register, offset: 0x110 */
  __IO uint32_t PCC_RGPIOD;                        /**< PCC RGPIOD Register, offset: 0x114 */
} PCC5_Type;

/* ----------------------------------------------------------------------------
   -- PCC5 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PCC5_Register_Masks PCC5 Register Masks
 * @{
 */

/*! @name PCC_DMA2_MP - PCC DMA2_MP Register */
/*! @{ */

#define PCC5_PCC_DMA2_MP_SSADO_MASK              (0xC00000U)
#define PCC5_PCC_DMA2_MP_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_MP_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_MP_SSADO_SHIFT)) & PCC5_PCC_DMA2_MP_SSADO_MASK)

#define PCC5_PCC_DMA2_MP_CGC_MASK                (0x40000000U)
#define PCC5_PCC_DMA2_MP_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_MP_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_MP_CGC_SHIFT)) & PCC5_PCC_DMA2_MP_CGC_MASK)

#define PCC5_PCC_DMA2_MP_PR_MASK                 (0x80000000U)
#define PCC5_PCC_DMA2_MP_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_MP_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_MP_PR_SHIFT)) & PCC5_PCC_DMA2_MP_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH0 - PCC DMA2_CH0 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH0_SSADO_MASK             (0xC00000U)
#define PCC5_PCC_DMA2_CH0_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH0_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH0_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH0_SSADO_MASK)

#define PCC5_PCC_DMA2_CH0_CGC_MASK               (0x40000000U)
#define PCC5_PCC_DMA2_CH0_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH0_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH0_CGC_SHIFT)) & PCC5_PCC_DMA2_CH0_CGC_MASK)

#define PCC5_PCC_DMA2_CH0_PR_MASK                (0x80000000U)
#define PCC5_PCC_DMA2_CH0_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH0_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH0_PR_SHIFT)) & PCC5_PCC_DMA2_CH0_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH1 - PCC DMA2_CH1 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH1_SSADO_MASK             (0xC00000U)
#define PCC5_PCC_DMA2_CH1_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH1_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH1_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH1_SSADO_MASK)

#define PCC5_PCC_DMA2_CH1_CGC_MASK               (0x40000000U)
#define PCC5_PCC_DMA2_CH1_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH1_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH1_CGC_SHIFT)) & PCC5_PCC_DMA2_CH1_CGC_MASK)

#define PCC5_PCC_DMA2_CH1_PR_MASK                (0x80000000U)
#define PCC5_PCC_DMA2_CH1_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH1_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH1_PR_SHIFT)) & PCC5_PCC_DMA2_CH1_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH2 - PCC DMA2_CH2 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH2_SSADO_MASK             (0xC00000U)
#define PCC5_PCC_DMA2_CH2_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH2_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH2_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH2_SSADO_MASK)

#define PCC5_PCC_DMA2_CH2_CGC_MASK               (0x40000000U)
#define PCC5_PCC_DMA2_CH2_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH2_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH2_CGC_SHIFT)) & PCC5_PCC_DMA2_CH2_CGC_MASK)

#define PCC5_PCC_DMA2_CH2_PR_MASK                (0x80000000U)
#define PCC5_PCC_DMA2_CH2_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH2_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH2_PR_SHIFT)) & PCC5_PCC_DMA2_CH2_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH3 - PCC DMA2_CH3 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH3_SSADO_MASK             (0xC00000U)
#define PCC5_PCC_DMA2_CH3_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH3_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH3_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH3_SSADO_MASK)

#define PCC5_PCC_DMA2_CH3_CGC_MASK               (0x40000000U)
#define PCC5_PCC_DMA2_CH3_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH3_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH3_CGC_SHIFT)) & PCC5_PCC_DMA2_CH3_CGC_MASK)

#define PCC5_PCC_DMA2_CH3_PR_MASK                (0x80000000U)
#define PCC5_PCC_DMA2_CH3_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH3_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH3_PR_SHIFT)) & PCC5_PCC_DMA2_CH3_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH4 - PCC DMA2_CH4 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH4_SSADO_MASK             (0xC00000U)
#define PCC5_PCC_DMA2_CH4_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH4_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH4_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH4_SSADO_MASK)

#define PCC5_PCC_DMA2_CH4_CGC_MASK               (0x40000000U)
#define PCC5_PCC_DMA2_CH4_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH4_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH4_CGC_SHIFT)) & PCC5_PCC_DMA2_CH4_CGC_MASK)

#define PCC5_PCC_DMA2_CH4_PR_MASK                (0x80000000U)
#define PCC5_PCC_DMA2_CH4_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH4_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH4_PR_SHIFT)) & PCC5_PCC_DMA2_CH4_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH5 - PCC DMA2_CH5 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH5_SSADO_MASK             (0xC00000U)
#define PCC5_PCC_DMA2_CH5_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH5_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH5_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH5_SSADO_MASK)

#define PCC5_PCC_DMA2_CH5_CGC_MASK               (0x40000000U)
#define PCC5_PCC_DMA2_CH5_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH5_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH5_CGC_SHIFT)) & PCC5_PCC_DMA2_CH5_CGC_MASK)

#define PCC5_PCC_DMA2_CH5_PR_MASK                (0x80000000U)
#define PCC5_PCC_DMA2_CH5_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH5_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH5_PR_SHIFT)) & PCC5_PCC_DMA2_CH5_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH6 - PCC DMA2_CH6 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH6_SSADO_MASK             (0xC00000U)
#define PCC5_PCC_DMA2_CH6_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH6_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH6_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH6_SSADO_MASK)

#define PCC5_PCC_DMA2_CH6_CGC_MASK               (0x40000000U)
#define PCC5_PCC_DMA2_CH6_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH6_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH6_CGC_SHIFT)) & PCC5_PCC_DMA2_CH6_CGC_MASK)

#define PCC5_PCC_DMA2_CH6_PR_MASK                (0x80000000U)
#define PCC5_PCC_DMA2_CH6_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH6_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH6_PR_SHIFT)) & PCC5_PCC_DMA2_CH6_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH7 - PCC DMA2_CH7 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH7_SSADO_MASK             (0xC00000U)
#define PCC5_PCC_DMA2_CH7_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH7_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH7_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH7_SSADO_MASK)

#define PCC5_PCC_DMA2_CH7_CGC_MASK               (0x40000000U)
#define PCC5_PCC_DMA2_CH7_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH7_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH7_CGC_SHIFT)) & PCC5_PCC_DMA2_CH7_CGC_MASK)

#define PCC5_PCC_DMA2_CH7_PR_MASK                (0x80000000U)
#define PCC5_PCC_DMA2_CH7_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH7_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH7_PR_SHIFT)) & PCC5_PCC_DMA2_CH7_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH8 - PCC DMA2_CH8 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH8_SSADO_MASK             (0xC00000U)
#define PCC5_PCC_DMA2_CH8_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH8_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH8_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH8_SSADO_MASK)

#define PCC5_PCC_DMA2_CH8_CGC_MASK               (0x40000000U)
#define PCC5_PCC_DMA2_CH8_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH8_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH8_CGC_SHIFT)) & PCC5_PCC_DMA2_CH8_CGC_MASK)

#define PCC5_PCC_DMA2_CH8_PR_MASK                (0x80000000U)
#define PCC5_PCC_DMA2_CH8_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH8_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH8_PR_SHIFT)) & PCC5_PCC_DMA2_CH8_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH9 - PCC DMA2_CH9 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH9_SSADO_MASK             (0xC00000U)
#define PCC5_PCC_DMA2_CH9_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH9_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH9_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH9_SSADO_MASK)

#define PCC5_PCC_DMA2_CH9_CGC_MASK               (0x40000000U)
#define PCC5_PCC_DMA2_CH9_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH9_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH9_CGC_SHIFT)) & PCC5_PCC_DMA2_CH9_CGC_MASK)

#define PCC5_PCC_DMA2_CH9_PR_MASK                (0x80000000U)
#define PCC5_PCC_DMA2_CH9_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH9_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH9_PR_SHIFT)) & PCC5_PCC_DMA2_CH9_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH10 - PCC DMA2_CH10 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH10_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH10_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH10_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH10_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH10_SSADO_MASK)

#define PCC5_PCC_DMA2_CH10_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH10_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH10_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH10_CGC_SHIFT)) & PCC5_PCC_DMA2_CH10_CGC_MASK)

#define PCC5_PCC_DMA2_CH10_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH10_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH10_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH10_PR_SHIFT)) & PCC5_PCC_DMA2_CH10_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH11 - PCC DMA2_CH11 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH11_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH11_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH11_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH11_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH11_SSADO_MASK)

#define PCC5_PCC_DMA2_CH11_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH11_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH11_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH11_CGC_SHIFT)) & PCC5_PCC_DMA2_CH11_CGC_MASK)

#define PCC5_PCC_DMA2_CH11_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH11_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH11_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH11_PR_SHIFT)) & PCC5_PCC_DMA2_CH11_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH12 - PCC DMA2_CH12 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH12_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH12_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH12_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH12_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH12_SSADO_MASK)

#define PCC5_PCC_DMA2_CH12_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH12_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH12_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH12_CGC_SHIFT)) & PCC5_PCC_DMA2_CH12_CGC_MASK)

#define PCC5_PCC_DMA2_CH12_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH12_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH12_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH12_PR_SHIFT)) & PCC5_PCC_DMA2_CH12_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH13 - PCC DMA2_CH13 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH13_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH13_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH13_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH13_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH13_SSADO_MASK)

#define PCC5_PCC_DMA2_CH13_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH13_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH13_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH13_CGC_SHIFT)) & PCC5_PCC_DMA2_CH13_CGC_MASK)

#define PCC5_PCC_DMA2_CH13_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH13_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH13_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH13_PR_SHIFT)) & PCC5_PCC_DMA2_CH13_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH14 - PCC DMA2_CH14 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH14_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH14_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH14_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH14_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH14_SSADO_MASK)

#define PCC5_PCC_DMA2_CH14_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH14_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH14_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH14_CGC_SHIFT)) & PCC5_PCC_DMA2_CH14_CGC_MASK)

#define PCC5_PCC_DMA2_CH14_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH14_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH14_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH14_PR_SHIFT)) & PCC5_PCC_DMA2_CH14_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH15 - PCC DMA2_CH15 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH15_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH15_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH15_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH15_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH15_SSADO_MASK)

#define PCC5_PCC_DMA2_CH15_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH15_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH15_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH15_CGC_SHIFT)) & PCC5_PCC_DMA2_CH15_CGC_MASK)

#define PCC5_PCC_DMA2_CH15_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH15_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH15_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH15_PR_SHIFT)) & PCC5_PCC_DMA2_CH15_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH16 - PCC DMA2_CH16 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH16_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH16_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH16_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH16_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH16_SSADO_MASK)

#define PCC5_PCC_DMA2_CH16_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH16_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH16_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH16_CGC_SHIFT)) & PCC5_PCC_DMA2_CH16_CGC_MASK)

#define PCC5_PCC_DMA2_CH16_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH16_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH16_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH16_PR_SHIFT)) & PCC5_PCC_DMA2_CH16_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH17 - PCC DMA2_CH17 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH17_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH17_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH17_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH17_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH17_SSADO_MASK)

#define PCC5_PCC_DMA2_CH17_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH17_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH17_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH17_CGC_SHIFT)) & PCC5_PCC_DMA2_CH17_CGC_MASK)

#define PCC5_PCC_DMA2_CH17_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH17_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH17_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH17_PR_SHIFT)) & PCC5_PCC_DMA2_CH17_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH18 - PCC DMA2_CH18 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH18_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH18_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH18_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH18_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH18_SSADO_MASK)

#define PCC5_PCC_DMA2_CH18_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH18_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH18_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH18_CGC_SHIFT)) & PCC5_PCC_DMA2_CH18_CGC_MASK)

#define PCC5_PCC_DMA2_CH18_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH18_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH18_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH18_PR_SHIFT)) & PCC5_PCC_DMA2_CH18_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH19 - PCC DMA2_CH19 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH19_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH19_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH19_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH19_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH19_SSADO_MASK)

#define PCC5_PCC_DMA2_CH19_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH19_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH19_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH19_CGC_SHIFT)) & PCC5_PCC_DMA2_CH19_CGC_MASK)

#define PCC5_PCC_DMA2_CH19_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH19_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH19_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH19_PR_SHIFT)) & PCC5_PCC_DMA2_CH19_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH20 - PCC DMA2_CH20 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH20_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH20_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH20_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH20_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH20_SSADO_MASK)

#define PCC5_PCC_DMA2_CH20_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH20_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH20_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH20_CGC_SHIFT)) & PCC5_PCC_DMA2_CH20_CGC_MASK)

#define PCC5_PCC_DMA2_CH20_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH20_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH20_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH20_PR_SHIFT)) & PCC5_PCC_DMA2_CH20_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH21 - PCC DMA2_CH21 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH21_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH21_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH21_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH21_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH21_SSADO_MASK)

#define PCC5_PCC_DMA2_CH21_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH21_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH21_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH21_CGC_SHIFT)) & PCC5_PCC_DMA2_CH21_CGC_MASK)

#define PCC5_PCC_DMA2_CH21_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH21_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH21_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH21_PR_SHIFT)) & PCC5_PCC_DMA2_CH21_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH22 - PCC DMA2_CH22 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH22_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH22_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH22_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH22_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH22_SSADO_MASK)

#define PCC5_PCC_DMA2_CH22_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH22_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH22_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH22_CGC_SHIFT)) & PCC5_PCC_DMA2_CH22_CGC_MASK)

#define PCC5_PCC_DMA2_CH22_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH22_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH22_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH22_PR_SHIFT)) & PCC5_PCC_DMA2_CH22_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH23 - PCC DMA2_CH23 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH23_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH23_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH23_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH23_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH23_SSADO_MASK)

#define PCC5_PCC_DMA2_CH23_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH23_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH23_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH23_CGC_SHIFT)) & PCC5_PCC_DMA2_CH23_CGC_MASK)

#define PCC5_PCC_DMA2_CH23_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH23_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH23_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH23_PR_SHIFT)) & PCC5_PCC_DMA2_CH23_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH24 - PCC DMA2_CH24 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH24_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH24_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH24_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH24_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH24_SSADO_MASK)

#define PCC5_PCC_DMA2_CH24_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH24_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH24_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH24_CGC_SHIFT)) & PCC5_PCC_DMA2_CH24_CGC_MASK)

#define PCC5_PCC_DMA2_CH24_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH24_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH24_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH24_PR_SHIFT)) & PCC5_PCC_DMA2_CH24_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH25 - PCC DMA2_CH25 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH25_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH25_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH25_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH25_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH25_SSADO_MASK)

#define PCC5_PCC_DMA2_CH25_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH25_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH25_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH25_CGC_SHIFT)) & PCC5_PCC_DMA2_CH25_CGC_MASK)

#define PCC5_PCC_DMA2_CH25_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH25_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH25_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH25_PR_SHIFT)) & PCC5_PCC_DMA2_CH25_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH26 - PCC DMA2_CH26 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH26_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH26_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH26_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH26_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH26_SSADO_MASK)

#define PCC5_PCC_DMA2_CH26_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH26_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH26_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH26_CGC_SHIFT)) & PCC5_PCC_DMA2_CH26_CGC_MASK)

#define PCC5_PCC_DMA2_CH26_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH26_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH26_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH26_PR_SHIFT)) & PCC5_PCC_DMA2_CH26_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH27 - PCC DMA2_CH27 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH27_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH27_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH27_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH27_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH27_SSADO_MASK)

#define PCC5_PCC_DMA2_CH27_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH27_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH27_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH27_CGC_SHIFT)) & PCC5_PCC_DMA2_CH27_CGC_MASK)

#define PCC5_PCC_DMA2_CH27_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH27_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH27_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH27_PR_SHIFT)) & PCC5_PCC_DMA2_CH27_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH28 - PCC DMA2_CH28 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH28_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH28_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH28_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH28_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH28_SSADO_MASK)

#define PCC5_PCC_DMA2_CH28_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH28_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH28_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH28_CGC_SHIFT)) & PCC5_PCC_DMA2_CH28_CGC_MASK)

#define PCC5_PCC_DMA2_CH28_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH28_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH28_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH28_PR_SHIFT)) & PCC5_PCC_DMA2_CH28_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH29 - PCC DMA2_CH29 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH29_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH29_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH29_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH29_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH29_SSADO_MASK)

#define PCC5_PCC_DMA2_CH29_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH29_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH29_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH29_CGC_SHIFT)) & PCC5_PCC_DMA2_CH29_CGC_MASK)

#define PCC5_PCC_DMA2_CH29_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH29_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH29_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH29_PR_SHIFT)) & PCC5_PCC_DMA2_CH29_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH30 - PCC DMA2_CH30 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH30_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH30_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH30_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH30_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH30_SSADO_MASK)

#define PCC5_PCC_DMA2_CH30_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH30_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH30_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH30_CGC_SHIFT)) & PCC5_PCC_DMA2_CH30_CGC_MASK)

#define PCC5_PCC_DMA2_CH30_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH30_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH30_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH30_PR_SHIFT)) & PCC5_PCC_DMA2_CH30_PR_MASK)
/*! @} */

/*! @name PCC_DMA2_CH31 - PCC DMA2_CH31 Register */
/*! @{ */

#define PCC5_PCC_DMA2_CH31_SSADO_MASK            (0xC00000U)
#define PCC5_PCC_DMA2_CH31_SSADO_SHIFT           (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DMA2_CH31_SSADO(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH31_SSADO_SHIFT)) & PCC5_PCC_DMA2_CH31_SSADO_MASK)

#define PCC5_PCC_DMA2_CH31_CGC_MASK              (0x40000000U)
#define PCC5_PCC_DMA2_CH31_CGC_SHIFT             (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DMA2_CH31_CGC(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH31_CGC_SHIFT)) & PCC5_PCC_DMA2_CH31_CGC_MASK)

#define PCC5_PCC_DMA2_CH31_PR_MASK               (0x80000000U)
#define PCC5_PCC_DMA2_CH31_PR_SHIFT              (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DMA2_CH31_PR(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DMA2_CH31_PR_SHIFT)) & PCC5_PCC_DMA2_CH31_PR_MASK)
/*! @} */

/*! @name PCC_MU2_B - PCC MU2_B Register */
/*! @{ */

#define PCC5_PCC_MU2_B_SSADO_MASK                (0xC00000U)
#define PCC5_PCC_MU2_B_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_MU2_B_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_MU2_B_SSADO_SHIFT)) & PCC5_PCC_MU2_B_SSADO_MASK)

#define PCC5_PCC_MU2_B_CGC_MASK                  (0x40000000U)
#define PCC5_PCC_MU2_B_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_MU2_B_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_MU2_B_CGC_SHIFT)) & PCC5_PCC_MU2_B_CGC_MASK)

#define PCC5_PCC_MU2_B_PR_MASK                   (0x80000000U)
#define PCC5_PCC_MU2_B_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_MU2_B_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_MU2_B_PR_SHIFT)) & PCC5_PCC_MU2_B_PR_MASK)
/*! @} */

/*! @name PCC_MU3_B - PCC MU3_B Register */
/*! @{ */

#define PCC5_PCC_MU3_B_SSADO_MASK                (0xC00000U)
#define PCC5_PCC_MU3_B_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_MU3_B_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_MU3_B_SSADO_SHIFT)) & PCC5_PCC_MU3_B_SSADO_MASK)

#define PCC5_PCC_MU3_B_CGC_MASK                  (0x40000000U)
#define PCC5_PCC_MU3_B_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_MU3_B_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_MU3_B_CGC_SHIFT)) & PCC5_PCC_MU3_B_CGC_MASK)

#define PCC5_PCC_MU3_B_PR_MASK                   (0x80000000U)
#define PCC5_PCC_MU3_B_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_MU3_B_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_MU3_B_PR_SHIFT)) & PCC5_PCC_MU3_B_PR_MASK)
/*! @} */

/*! @name PCC_SEMA42_2 - PCC SEMA42_2 Register */
/*! @{ */

#define PCC5_PCC_SEMA42_2_SSADO_MASK             (0xC00000U)
#define PCC5_PCC_SEMA42_2_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_SEMA42_2_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SEMA42_2_SSADO_SHIFT)) & PCC5_PCC_SEMA42_2_SSADO_MASK)

#define PCC5_PCC_SEMA42_2_CGC_MASK               (0x40000000U)
#define PCC5_PCC_SEMA42_2_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_SEMA42_2_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SEMA42_2_CGC_SHIFT)) & PCC5_PCC_SEMA42_2_CGC_MASK)

#define PCC5_PCC_SEMA42_2_PR_MASK                (0x80000000U)
#define PCC5_PCC_SEMA42_2_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_SEMA42_2_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SEMA42_2_PR_SHIFT)) & PCC5_PCC_SEMA42_2_PR_MASK)
/*! @} */

/*! @name PCC_TPM8 - PCC TPM8 Register */
/*! @{ */

#define PCC5_PCC_TPM8_PCD_MASK                   (0x7U)
#define PCC5_PCC_TPM8_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC5_PCC_TPM8_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_TPM8_PCD_SHIFT)) & PCC5_PCC_TPM8_PCD_MASK)

#define PCC5_PCC_TPM8_FRAC_MASK                  (0x8U)
#define PCC5_PCC_TPM8_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC5_PCC_TPM8_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_TPM8_FRAC_SHIFT)) & PCC5_PCC_TPM8_FRAC_MASK)

#define PCC5_PCC_TPM8_SSADO_MASK                 (0xC00000U)
#define PCC5_PCC_TPM8_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_TPM8_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_TPM8_SSADO_SHIFT)) & PCC5_PCC_TPM8_SSADO_MASK)

#define PCC5_PCC_TPM8_PCS_MASK                   (0x7000000U)
#define PCC5_PCC_TPM8_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC5_PCC_TPM8_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_TPM8_PCS_SHIFT)) & PCC5_PCC_TPM8_PCS_MASK)

#define PCC5_PCC_TPM8_SWRST_MASK                 (0x10000000U)
#define PCC5_PCC_TPM8_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_TPM8_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_TPM8_SWRST_SHIFT)) & PCC5_PCC_TPM8_SWRST_MASK)

#define PCC5_PCC_TPM8_CGC_MASK                   (0x40000000U)
#define PCC5_PCC_TPM8_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_TPM8_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_TPM8_CGC_SHIFT)) & PCC5_PCC_TPM8_CGC_MASK)

#define PCC5_PCC_TPM8_PR_MASK                    (0x80000000U)
#define PCC5_PCC_TPM8_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_TPM8_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_TPM8_PR_SHIFT)) & PCC5_PCC_TPM8_PR_MASK)
/*! @} */

/*! @name PCC_SAI6 - PCC SAI6 Register */
/*! @{ */

#define PCC5_PCC_SAI6_SSADO_MASK                 (0xC00000U)
#define PCC5_PCC_SAI6_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_SAI6_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SAI6_SSADO_SHIFT)) & PCC5_PCC_SAI6_SSADO_MASK)

#define PCC5_PCC_SAI6_SWRST_MASK                 (0x10000000U)
#define PCC5_PCC_SAI6_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_SAI6_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SAI6_SWRST_SHIFT)) & PCC5_PCC_SAI6_SWRST_MASK)

#define PCC5_PCC_SAI6_CGC_MASK                   (0x40000000U)
#define PCC5_PCC_SAI6_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_SAI6_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SAI6_CGC_SHIFT)) & PCC5_PCC_SAI6_CGC_MASK)

#define PCC5_PCC_SAI6_PR_MASK                    (0x80000000U)
#define PCC5_PCC_SAI6_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_SAI6_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SAI6_PR_SHIFT)) & PCC5_PCC_SAI6_PR_MASK)
/*! @} */

/*! @name PCC_SAI7 - PCC SAI7 Register */
/*! @{ */

#define PCC5_PCC_SAI7_SSADO_MASK                 (0xC00000U)
#define PCC5_PCC_SAI7_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_SAI7_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SAI7_SSADO_SHIFT)) & PCC5_PCC_SAI7_SSADO_MASK)

#define PCC5_PCC_SAI7_SWRST_MASK                 (0x10000000U)
#define PCC5_PCC_SAI7_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_SAI7_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SAI7_SWRST_SHIFT)) & PCC5_PCC_SAI7_SWRST_MASK)

#define PCC5_PCC_SAI7_CGC_MASK                   (0x40000000U)
#define PCC5_PCC_SAI7_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_SAI7_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SAI7_CGC_SHIFT)) & PCC5_PCC_SAI7_CGC_MASK)

#define PCC5_PCC_SAI7_PR_MASK                    (0x80000000U)
#define PCC5_PCC_SAI7_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_SAI7_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SAI7_PR_SHIFT)) & PCC5_PCC_SAI7_PR_MASK)
/*! @} */

/*! @name PCC_SPDIF - PCC SPDIF Register */
/*! @{ */

#define PCC5_PCC_SPDIF_SSADO_MASK                (0xC00000U)
#define PCC5_PCC_SPDIF_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_SPDIF_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SPDIF_SSADO_SHIFT)) & PCC5_PCC_SPDIF_SSADO_MASK)

#define PCC5_PCC_SPDIF_SWRST_MASK                (0x10000000U)
#define PCC5_PCC_SPDIF_SWRST_SHIFT               (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_SPDIF_SWRST(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SPDIF_SWRST_SHIFT)) & PCC5_PCC_SPDIF_SWRST_MASK)

#define PCC5_PCC_SPDIF_CGC_MASK                  (0x40000000U)
#define PCC5_PCC_SPDIF_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_SPDIF_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SPDIF_CGC_SHIFT)) & PCC5_PCC_SPDIF_CGC_MASK)

#define PCC5_PCC_SPDIF_PR_MASK                   (0x80000000U)
#define PCC5_PCC_SPDIF_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_SPDIF_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_SPDIF_PR_SHIFT)) & PCC5_PCC_SPDIF_PR_MASK)
/*! @} */

/*! @name PCC_ISI - PCC ISI Register */
/*! @{ */

#define PCC5_PCC_ISI_SSADO_MASK                  (0xC00000U)
#define PCC5_PCC_ISI_SSADO_SHIFT                 (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_ISI_SSADO(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_ISI_SSADO_SHIFT)) & PCC5_PCC_ISI_SSADO_MASK)

#define PCC5_PCC_ISI_SWRST_MASK                  (0x10000000U)
#define PCC5_PCC_ISI_SWRST_SHIFT                 (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_ISI_SWRST(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_ISI_SWRST_SHIFT)) & PCC5_PCC_ISI_SWRST_MASK)

#define PCC5_PCC_ISI_CGC_MASK                    (0x40000000U)
#define PCC5_PCC_ISI_CGC_SHIFT                   (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_ISI_CGC(x)                      (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_ISI_CGC_SHIFT)) & PCC5_PCC_ISI_CGC_MASK)

#define PCC5_PCC_ISI_PR_MASK                     (0x80000000U)
#define PCC5_PCC_ISI_PR_SHIFT                    (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_ISI_PR(x)                       (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_ISI_PR_SHIFT)) & PCC5_PCC_ISI_PR_MASK)
/*! @} */

/*! @name PCC_CSI_REGS - PCC CSI_REGS Register */
/*! @{ */

#define PCC5_PCC_CSI_REGS_SSADO_MASK             (0xC00000U)
#define PCC5_PCC_CSI_REGS_SSADO_SHIFT            (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_CSI_REGS_SSADO(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_REGS_SSADO_SHIFT)) & PCC5_PCC_CSI_REGS_SSADO_MASK)

#define PCC5_PCC_CSI_REGS_SWRST_MASK             (0x10000000U)
#define PCC5_PCC_CSI_REGS_SWRST_SHIFT            (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_CSI_REGS_SWRST(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_REGS_SWRST_SHIFT)) & PCC5_PCC_CSI_REGS_SWRST_MASK)

#define PCC5_PCC_CSI_REGS_CGC_MASK               (0x40000000U)
#define PCC5_PCC_CSI_REGS_CGC_SHIFT              (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_CSI_REGS_CGC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_REGS_CGC_SHIFT)) & PCC5_PCC_CSI_REGS_CGC_MASK)

#define PCC5_PCC_CSI_REGS_PR_MASK                (0x80000000U)
#define PCC5_PCC_CSI_REGS_PR_SHIFT               (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_CSI_REGS_PR(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_REGS_PR_SHIFT)) & PCC5_PCC_CSI_REGS_PR_MASK)
/*! @} */

/*! @name PCC_CSI - PCC CSI Register */
/*! @{ */

#define PCC5_PCC_CSI_PCD_MASK                    (0x7U)
#define PCC5_PCC_CSI_PCD_SHIFT                   (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC5_PCC_CSI_PCD(x)                      (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_PCD_SHIFT)) & PCC5_PCC_CSI_PCD_MASK)

#define PCC5_PCC_CSI_FRAC_MASK                   (0x8U)
#define PCC5_PCC_CSI_FRAC_SHIFT                  (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC5_PCC_CSI_FRAC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_FRAC_SHIFT)) & PCC5_PCC_CSI_FRAC_MASK)

#define PCC5_PCC_CSI_SSADO_MASK                  (0xC00000U)
#define PCC5_PCC_CSI_SSADO_SHIFT                 (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_CSI_SSADO(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_SSADO_SHIFT)) & PCC5_PCC_CSI_SSADO_MASK)

#define PCC5_PCC_CSI_PCS_MASK                    (0x7000000U)
#define PCC5_PCC_CSI_PCS_SHIFT                   (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC5_PCC_CSI_PCS(x)                      (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_PCS_SHIFT)) & PCC5_PCC_CSI_PCS_MASK)

#define PCC5_PCC_CSI_SWRST_MASK                  (0x10000000U)
#define PCC5_PCC_CSI_SWRST_SHIFT                 (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_CSI_SWRST(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_SWRST_SHIFT)) & PCC5_PCC_CSI_SWRST_MASK)

#define PCC5_PCC_CSI_CGC_MASK                    (0x40000000U)
#define PCC5_PCC_CSI_CGC_SHIFT                   (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_CSI_CGC(x)                      (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_CGC_SHIFT)) & PCC5_PCC_CSI_CGC_MASK)

#define PCC5_PCC_CSI_PR_MASK                     (0x80000000U)
#define PCC5_PCC_CSI_PR_SHIFT                    (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_CSI_PR(x)                       (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_PR_SHIFT)) & PCC5_PCC_CSI_PR_MASK)
/*! @} */

/*! @name PCC_DSI - PCC DSI Register */
/*! @{ */

#define PCC5_PCC_DSI_PCD_MASK                    (0x7U)
#define PCC5_PCC_DSI_PCD_SHIFT                   (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC5_PCC_DSI_PCD(x)                      (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DSI_PCD_SHIFT)) & PCC5_PCC_DSI_PCD_MASK)

#define PCC5_PCC_DSI_FRAC_MASK                   (0x8U)
#define PCC5_PCC_DSI_FRAC_SHIFT                  (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC5_PCC_DSI_FRAC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DSI_FRAC_SHIFT)) & PCC5_PCC_DSI_FRAC_MASK)

#define PCC5_PCC_DSI_SSADO_MASK                  (0xC00000U)
#define PCC5_PCC_DSI_SSADO_SHIFT                 (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DSI_SSADO(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DSI_SSADO_SHIFT)) & PCC5_PCC_DSI_SSADO_MASK)

#define PCC5_PCC_DSI_PCS_MASK                    (0x7000000U)
#define PCC5_PCC_DSI_PCS_SHIFT                   (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC5_PCC_DSI_PCS(x)                      (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DSI_PCS_SHIFT)) & PCC5_PCC_DSI_PCS_MASK)

#define PCC5_PCC_DSI_SWRST_MASK                  (0x10000000U)
#define PCC5_PCC_DSI_SWRST_SHIFT                 (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_DSI_SWRST(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DSI_SWRST_SHIFT)) & PCC5_PCC_DSI_SWRST_MASK)

#define PCC5_PCC_DSI_CGC_MASK                    (0x40000000U)
#define PCC5_PCC_DSI_CGC_SHIFT                   (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DSI_CGC(x)                      (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DSI_CGC_SHIFT)) & PCC5_PCC_DSI_CGC_MASK)

#define PCC5_PCC_DSI_PR_MASK                     (0x80000000U)
#define PCC5_PCC_DSI_PR_SHIFT                    (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DSI_PR(x)                       (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DSI_PR_SHIFT)) & PCC5_PCC_DSI_PR_MASK)
/*! @} */

/*! @name PCC_WDOG5 - PCC WDOG5 Register */
/*! @{ */

#define PCC5_PCC_WDOG5_PCD_MASK                  (0x7U)
#define PCC5_PCC_WDOG5_PCD_SHIFT                 (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC5_PCC_WDOG5_PCD(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_WDOG5_PCD_SHIFT)) & PCC5_PCC_WDOG5_PCD_MASK)

#define PCC5_PCC_WDOG5_FRAC_MASK                 (0x8U)
#define PCC5_PCC_WDOG5_FRAC_SHIFT                (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC5_PCC_WDOG5_FRAC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_WDOG5_FRAC_SHIFT)) & PCC5_PCC_WDOG5_FRAC_MASK)

#define PCC5_PCC_WDOG5_SSADO_MASK                (0xC00000U)
#define PCC5_PCC_WDOG5_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_WDOG5_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_WDOG5_SSADO_SHIFT)) & PCC5_PCC_WDOG5_SSADO_MASK)

#define PCC5_PCC_WDOG5_PCS_MASK                  (0x7000000U)
#define PCC5_PCC_WDOG5_PCS_SHIFT                 (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC5_PCC_WDOG5_PCS(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_WDOG5_PCS_SHIFT)) & PCC5_PCC_WDOG5_PCS_MASK)

#define PCC5_PCC_WDOG5_SWRST_MASK                (0x10000000U)
#define PCC5_PCC_WDOG5_SWRST_SHIFT               (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_WDOG5_SWRST(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_WDOG5_SWRST_SHIFT)) & PCC5_PCC_WDOG5_SWRST_MASK)

#define PCC5_PCC_WDOG5_CGC_MASK                  (0x40000000U)
#define PCC5_PCC_WDOG5_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_WDOG5_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_WDOG5_CGC_SHIFT)) & PCC5_PCC_WDOG5_CGC_MASK)

#define PCC5_PCC_WDOG5_PR_MASK                   (0x80000000U)
#define PCC5_PCC_WDOG5_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_WDOG5_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_WDOG5_PR_SHIFT)) & PCC5_PCC_WDOG5_PR_MASK)
/*! @} */

/*! @name PCC_EPDC - PCC EPDC Register */
/*! @{ */

#define PCC5_PCC_EPDC_PCD_MASK                   (0x7U)
#define PCC5_PCC_EPDC_PCD_SHIFT                  (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC5_PCC_EPDC_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_EPDC_PCD_SHIFT)) & PCC5_PCC_EPDC_PCD_MASK)

#define PCC5_PCC_EPDC_FRAC_MASK                  (0x8U)
#define PCC5_PCC_EPDC_FRAC_SHIFT                 (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC5_PCC_EPDC_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_EPDC_FRAC_SHIFT)) & PCC5_PCC_EPDC_FRAC_MASK)

#define PCC5_PCC_EPDC_SSADO_MASK                 (0xC00000U)
#define PCC5_PCC_EPDC_SSADO_SHIFT                (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_EPDC_SSADO(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_EPDC_SSADO_SHIFT)) & PCC5_PCC_EPDC_SSADO_MASK)

#define PCC5_PCC_EPDC_PCS_MASK                   (0x7000000U)
#define PCC5_PCC_EPDC_PCS_SHIFT                  (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC5_PCC_EPDC_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_EPDC_PCS_SHIFT)) & PCC5_PCC_EPDC_PCS_MASK)

#define PCC5_PCC_EPDC_SWRST_MASK                 (0x10000000U)
#define PCC5_PCC_EPDC_SWRST_SHIFT                (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_EPDC_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_EPDC_SWRST_SHIFT)) & PCC5_PCC_EPDC_SWRST_MASK)

#define PCC5_PCC_EPDC_CGC_MASK                   (0x40000000U)
#define PCC5_PCC_EPDC_CGC_SHIFT                  (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_EPDC_CGC(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_EPDC_CGC_SHIFT)) & PCC5_PCC_EPDC_CGC_MASK)

#define PCC5_PCC_EPDC_PR_MASK                    (0x80000000U)
#define PCC5_PCC_EPDC_PR_SHIFT                   (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_EPDC_PR(x)                      (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_EPDC_PR_SHIFT)) & PCC5_PCC_EPDC_PR_MASK)
/*! @} */

/*! @name PCC_PXP - PCC PXP Register */
/*! @{ */

#define PCC5_PCC_PXP_SSADO_MASK                  (0xC00000U)
#define PCC5_PCC_PXP_SSADO_SHIFT                 (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_PXP_SSADO(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_PXP_SSADO_SHIFT)) & PCC5_PCC_PXP_SSADO_MASK)

#define PCC5_PCC_PXP_SWRST_MASK                  (0x10000000U)
#define PCC5_PCC_PXP_SWRST_SHIFT                 (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_PXP_SWRST(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_PXP_SWRST_SHIFT)) & PCC5_PCC_PXP_SWRST_MASK)

#define PCC5_PCC_PXP_CGC_MASK                    (0x40000000U)
#define PCC5_PCC_PXP_CGC_SHIFT                   (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_PXP_CGC(x)                      (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_PXP_CGC_SHIFT)) & PCC5_PCC_PXP_CGC_MASK)

#define PCC5_PCC_PXP_PR_MASK                     (0x80000000U)
#define PCC5_PCC_PXP_PR_SHIFT                    (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_PXP_PR(x)                       (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_PXP_PR_SHIFT)) & PCC5_PCC_PXP_PR_MASK)
/*! @} */

/*! @name PCC_GPU2D - PCC GPU2D Register */
/*! @{ */

#define PCC5_PCC_GPU2D_PCD_MASK                  (0x7U)
#define PCC5_PCC_GPU2D_PCD_SHIFT                 (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC5_PCC_GPU2D_PCD(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU2D_PCD_SHIFT)) & PCC5_PCC_GPU2D_PCD_MASK)

#define PCC5_PCC_GPU2D_FRAC_MASK                 (0x8U)
#define PCC5_PCC_GPU2D_FRAC_SHIFT                (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC5_PCC_GPU2D_FRAC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU2D_FRAC_SHIFT)) & PCC5_PCC_GPU2D_FRAC_MASK)

#define PCC5_PCC_GPU2D_SSADO_MASK                (0xC00000U)
#define PCC5_PCC_GPU2D_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_GPU2D_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU2D_SSADO_SHIFT)) & PCC5_PCC_GPU2D_SSADO_MASK)

#define PCC5_PCC_GPU2D_PCS_MASK                  (0x7000000U)
#define PCC5_PCC_GPU2D_PCS_SHIFT                 (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC5_PCC_GPU2D_PCS(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU2D_PCS_SHIFT)) & PCC5_PCC_GPU2D_PCS_MASK)

#define PCC5_PCC_GPU2D_SWRST_MASK                (0x10000000U)
#define PCC5_PCC_GPU2D_SWRST_SHIFT               (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_GPU2D_SWRST(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU2D_SWRST_SHIFT)) & PCC5_PCC_GPU2D_SWRST_MASK)

#define PCC5_PCC_GPU2D_CGC_MASK                  (0x40000000U)
#define PCC5_PCC_GPU2D_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_GPU2D_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU2D_CGC_SHIFT)) & PCC5_PCC_GPU2D_CGC_MASK)

#define PCC5_PCC_GPU2D_PR_MASK                   (0x80000000U)
#define PCC5_PCC_GPU2D_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_GPU2D_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU2D_PR_SHIFT)) & PCC5_PCC_GPU2D_PR_MASK)
/*! @} */

/*! @name PCC_GPU3D - PCC GPU3D Register */
/*! @{ */

#define PCC5_PCC_GPU3D_PCD_MASK                  (0x7U)
#define PCC5_PCC_GPU3D_PCD_SHIFT                 (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC5_PCC_GPU3D_PCD(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU3D_PCD_SHIFT)) & PCC5_PCC_GPU3D_PCD_MASK)

#define PCC5_PCC_GPU3D_FRAC_MASK                 (0x8U)
#define PCC5_PCC_GPU3D_FRAC_SHIFT                (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC5_PCC_GPU3D_FRAC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU3D_FRAC_SHIFT)) & PCC5_PCC_GPU3D_FRAC_MASK)

#define PCC5_PCC_GPU3D_SSADO_MASK                (0xC00000U)
#define PCC5_PCC_GPU3D_SSADO_SHIFT               (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_GPU3D_SSADO(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU3D_SSADO_SHIFT)) & PCC5_PCC_GPU3D_SSADO_MASK)

#define PCC5_PCC_GPU3D_PCS_MASK                  (0x7000000U)
#define PCC5_PCC_GPU3D_PCS_SHIFT                 (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC5_PCC_GPU3D_PCS(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU3D_PCS_SHIFT)) & PCC5_PCC_GPU3D_PCS_MASK)

#define PCC5_PCC_GPU3D_SWRST_MASK                (0x10000000U)
#define PCC5_PCC_GPU3D_SWRST_SHIFT               (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_GPU3D_SWRST(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU3D_SWRST_SHIFT)) & PCC5_PCC_GPU3D_SWRST_MASK)

#define PCC5_PCC_GPU3D_CGC_MASK                  (0x40000000U)
#define PCC5_PCC_GPU3D_CGC_SHIFT                 (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_GPU3D_CGC(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU3D_CGC_SHIFT)) & PCC5_PCC_GPU3D_CGC_MASK)

#define PCC5_PCC_GPU3D_PR_MASK                   (0x80000000U)
#define PCC5_PCC_GPU3D_PR_SHIFT                  (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_GPU3D_PR(x)                     (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_GPU3D_PR_SHIFT)) & PCC5_PCC_GPU3D_PR_MASK)
/*! @} */

/*! @name PCC_DC_NANO - PCC DC_Nano Register */
/*! @{ */

#define PCC5_PCC_DC_NANO_PCD_MASK                (0x7U)
#define PCC5_PCC_DC_NANO_PCD_SHIFT               (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC5_PCC_DC_NANO_PCD(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DC_NANO_PCD_SHIFT)) & PCC5_PCC_DC_NANO_PCD_MASK)

#define PCC5_PCC_DC_NANO_FRAC_MASK               (0x8U)
#define PCC5_PCC_DC_NANO_FRAC_SHIFT              (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC5_PCC_DC_NANO_FRAC(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DC_NANO_FRAC_SHIFT)) & PCC5_PCC_DC_NANO_FRAC_MASK)

#define PCC5_PCC_DC_NANO_SSADO_MASK              (0xC00000U)
#define PCC5_PCC_DC_NANO_SSADO_SHIFT             (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_DC_NANO_SSADO(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DC_NANO_SSADO_SHIFT)) & PCC5_PCC_DC_NANO_SSADO_MASK)

#define PCC5_PCC_DC_NANO_PCS_MASK                (0x7000000U)
#define PCC5_PCC_DC_NANO_PCS_SHIFT               (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC5_PCC_DC_NANO_PCS(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DC_NANO_PCS_SHIFT)) & PCC5_PCC_DC_NANO_PCS_MASK)

#define PCC5_PCC_DC_NANO_SWRST_MASK              (0x10000000U)
#define PCC5_PCC_DC_NANO_SWRST_SHIFT             (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_DC_NANO_SWRST(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DC_NANO_SWRST_SHIFT)) & PCC5_PCC_DC_NANO_SWRST_MASK)

#define PCC5_PCC_DC_NANO_CGC_MASK                (0x40000000U)
#define PCC5_PCC_DC_NANO_CGC_SHIFT               (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_DC_NANO_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DC_NANO_CGC_SHIFT)) & PCC5_PCC_DC_NANO_CGC_MASK)

#define PCC5_PCC_DC_NANO_PR_MASK                 (0x80000000U)
#define PCC5_PCC_DC_NANO_PR_SHIFT                (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_DC_NANO_PR(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_DC_NANO_PR_SHIFT)) & PCC5_PCC_DC_NANO_PR_MASK)
/*! @} */

/*! @name PCC_LPDDR4 - PCC LPDDR4 Register */
/*! @{ */

#define PCC5_PCC_LPDDR4_SSADO_MASK               (0xC00000U)
#define PCC5_PCC_LPDDR4_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_LPDDR4_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_LPDDR4_SSADO_SHIFT)) & PCC5_PCC_LPDDR4_SSADO_MASK)

#define PCC5_PCC_LPDDR4_SWRST_MASK               (0x10000000U)
#define PCC5_PCC_LPDDR4_SWRST_SHIFT              (28U)
/*! SWRST - Software Reset Control
 *  0b1..No SoftWare Reset.
 *  0b0..Software Reset.
 */
#define PCC5_PCC_LPDDR4_SWRST(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_LPDDR4_SWRST_SHIFT)) & PCC5_PCC_LPDDR4_SWRST_MASK)

#define PCC5_PCC_LPDDR4_CGC_MASK                 (0x40000000U)
#define PCC5_PCC_LPDDR4_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_LPDDR4_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_LPDDR4_CGC_SHIFT)) & PCC5_PCC_LPDDR4_CGC_MASK)

#define PCC5_PCC_LPDDR4_PR_MASK                  (0x80000000U)
#define PCC5_PCC_LPDDR4_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_LPDDR4_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_LPDDR4_PR_SHIFT)) & PCC5_PCC_LPDDR4_PR_MASK)
/*! @} */

/*! @name PCC_CSI_CLK_UI - PCC CSI_clk_ui Register */
/*! @{ */

#define PCC5_PCC_CSI_CLK_UI_PCD_MASK             (0x7U)
#define PCC5_PCC_CSI_CLK_UI_PCD_SHIFT            (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC5_PCC_CSI_CLK_UI_PCD(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_CLK_UI_PCD_SHIFT)) & PCC5_PCC_CSI_CLK_UI_PCD_MASK)

#define PCC5_PCC_CSI_CLK_UI_FRAC_MASK            (0x8U)
#define PCC5_PCC_CSI_CLK_UI_FRAC_SHIFT           (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC5_PCC_CSI_CLK_UI_FRAC(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_CLK_UI_FRAC_SHIFT)) & PCC5_PCC_CSI_CLK_UI_FRAC_MASK)

#define PCC5_PCC_CSI_CLK_UI_SSADO_MASK           (0xC00000U)
#define PCC5_PCC_CSI_CLK_UI_SSADO_SHIFT          (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_CSI_CLK_UI_SSADO(x)             (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_CLK_UI_SSADO_SHIFT)) & PCC5_PCC_CSI_CLK_UI_SSADO_MASK)

#define PCC5_PCC_CSI_CLK_UI_PCS_MASK             (0x7000000U)
#define PCC5_PCC_CSI_CLK_UI_PCS_SHIFT            (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC5_PCC_CSI_CLK_UI_PCS(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_CLK_UI_PCS_SHIFT)) & PCC5_PCC_CSI_CLK_UI_PCS_MASK)

#define PCC5_PCC_CSI_CLK_UI_CGC_MASK             (0x40000000U)
#define PCC5_PCC_CSI_CLK_UI_CGC_SHIFT            (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_CSI_CLK_UI_CGC(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_CLK_UI_CGC_SHIFT)) & PCC5_PCC_CSI_CLK_UI_CGC_MASK)

#define PCC5_PCC_CSI_CLK_UI_PR_MASK              (0x80000000U)
#define PCC5_PCC_CSI_CLK_UI_PR_SHIFT             (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_CSI_CLK_UI_PR(x)                (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_CLK_UI_PR_SHIFT)) & PCC5_PCC_CSI_CLK_UI_PR_MASK)
/*! @} */

/*! @name PCC_CSI_CLK_ESC - PCC CSI_clk_esc Register */
/*! @{ */

#define PCC5_PCC_CSI_CLK_ESC_PCD_MASK            (0x7U)
#define PCC5_PCC_CSI_CLK_ESC_PCD_SHIFT           (0U)
/*! PCD - Peripheral Clock Divider Select
 *  0b000..Divide by 1.
 *  0b001..Divide by 2.
 *  0b010..Divide by 3.
 *  0b011..Divide by 4.
 *  0b100..Divide by 5.
 *  0b101..Divide by 6.
 *  0b110..Divide by 7.
 *  0b111..Divide by 8.
 */
#define PCC5_PCC_CSI_CLK_ESC_PCD(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_CLK_ESC_PCD_SHIFT)) & PCC5_PCC_CSI_CLK_ESC_PCD_MASK)

#define PCC5_PCC_CSI_CLK_ESC_FRAC_MASK           (0x8U)
#define PCC5_PCC_CSI_CLK_ESC_FRAC_SHIFT          (3U)
/*! FRAC - Peripheral Clock Divider Fraction
 *  0b0..Fractional value is 0.
 *  0b1..Fractional value is 1.
 */
#define PCC5_PCC_CSI_CLK_ESC_FRAC(x)             (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_CLK_ESC_FRAC_SHIFT)) & PCC5_PCC_CSI_CLK_ESC_FRAC_MASK)

#define PCC5_PCC_CSI_CLK_ESC_SSADO_MASK          (0xC00000U)
#define PCC5_PCC_CSI_CLK_ESC_SSADO_SHIFT         (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_CSI_CLK_ESC_SSADO(x)            (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_CLK_ESC_SSADO_SHIFT)) & PCC5_PCC_CSI_CLK_ESC_SSADO_MASK)

#define PCC5_PCC_CSI_CLK_ESC_PCS_MASK            (0x7000000U)
#define PCC5_PCC_CSI_CLK_ESC_PCS_SHIFT           (24U)
/*! PCS - Peripheral Clock Source Select
 *  0b000..Clock is off (or test clock is enabled).
 *  0b001..Clock option 1
 *  0b010..Clock option 2
 *  0b011..Clock option 3
 *  0b100..Clock option 4
 *  0b101..Clock option 5
 *  0b110..Clock option 6
 *  0b111..Clock option 7
 */
#define PCC5_PCC_CSI_CLK_ESC_PCS(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_CLK_ESC_PCS_SHIFT)) & PCC5_PCC_CSI_CLK_ESC_PCS_MASK)

#define PCC5_PCC_CSI_CLK_ESC_CGC_MASK            (0x40000000U)
#define PCC5_PCC_CSI_CLK_ESC_CGC_SHIFT           (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_CSI_CLK_ESC_CGC(x)              (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_CLK_ESC_CGC_SHIFT)) & PCC5_PCC_CSI_CLK_ESC_CGC_MASK)

#define PCC5_PCC_CSI_CLK_ESC_PR_MASK             (0x80000000U)
#define PCC5_PCC_CSI_CLK_ESC_PR_SHIFT            (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_CSI_CLK_ESC_PR(x)               (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_CSI_CLK_ESC_PR_SHIFT)) & PCC5_PCC_CSI_CLK_ESC_PR_MASK)
/*! @} */

/*! @name PCC_RGPIOD - PCC RGPIOD Register */
/*! @{ */

#define PCC5_PCC_RGPIOD_SSADO_MASK               (0xC00000U)
#define PCC5_PCC_RGPIOD_SSADO_SHIFT              (22U)
/*! SSADO - Stop and "Stop ACK" Domain Owner
 *  0b01..PCC handles ACK from PERI for domain 0 stop, and ack to domain 1 stop is always 0.
 *  0b10..PCC handles ACK from PERI for domain 1 stop, and ack to domain 0 stop is always 0.
 *  0b11..PCC handles ACK from PERI for domain 0 stop Domain 1 stop.
 *  0b00..PCC ack to both domains' stop are always 0.
 */
#define PCC5_PCC_RGPIOD_SSADO(x)                 (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_RGPIOD_SSADO_SHIFT)) & PCC5_PCC_RGPIOD_SSADO_MASK)

#define PCC5_PCC_RGPIOD_CGC_MASK                 (0x40000000U)
#define PCC5_PCC_RGPIOD_CGC_SHIFT                (30U)
/*! CGC - Clock Gate Control
 *  0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified.
 *  0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified.
 */
#define PCC5_PCC_RGPIOD_CGC(x)                   (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_RGPIOD_CGC_SHIFT)) & PCC5_PCC_RGPIOD_CGC_MASK)

#define PCC5_PCC_RGPIOD_PR_MASK                  (0x80000000U)
#define PCC5_PCC_RGPIOD_PR_SHIFT                 (31U)
/*! PR - Present
 *  0b0..Peripheral is not present.
 *  0b1..Peripheral is present.
 */
#define PCC5_PCC_RGPIOD_PR(x)                    (((uint32_t)(((uint32_t)(x)) << PCC5_PCC_RGPIOD_PR_SHIFT)) & PCC5_PCC_RGPIOD_PR_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PCC5_Register_Masks */


/* PCC5 - Peripheral instance base addresses */
/** Peripheral PCC5 base address */
#define PCC5_BASE                                (0x2DA70000u)
/** Peripheral PCC5 base pointer */
#define PCC5                                     ((PCC5_Type *)PCC5_BASE)
/** Array initializer of PCC5 peripheral base addresses */
#define PCC5_BASE_ADDRS                          { PCC5_BASE }
/** Array initializer of PCC5 peripheral base pointers */
#define PCC5_BASE_PTRS                           { PCC5 }

/*!
 * @}
 */ /* end of group PCC5_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PDM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer
 * @{
 */

/** PDM - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL_1;                            /**< PDM Control register 1, offset: 0x0 */
  __IO uint32_t CTRL_2;                            /**< PDM Control register 2, offset: 0x4 */
  __IO uint32_t STAT;                              /**< PDM Status register, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t FIFO_CTRL;                         /**< PDM FIFO Control register, offset: 0x10 */
  __IO uint32_t FIFO_STAT;                         /**< PDM FIFO Status register, offset: 0x14 */
       uint8_t RESERVED_1[12];
  __I  uint32_t DATACH[8];                         /**< PDM Output Result Register, array offset: 0x24, array step: 0x4 */
       uint8_t RESERVED_2[32];
  __I  uint32_t DC_CTRL;                           /**< PDM DC Remover Control register, offset: 0x64 */
  __IO uint32_t DC_OUT_CTRL;                       /**< PDM Output DC Remover Control register, offset: 0x68 */
       uint8_t RESERVED_3[8];
  __IO uint32_t RANGE_CTRL;                        /**< PDM Range Control register, offset: 0x74 */
       uint8_t RESERVED_4[4];
  __IO uint32_t RANGE_STAT;                        /**< PDM Range Status register, offset: 0x7C */
  __IO uint32_t FSYNC_CTRL;                        /**< Frame Synchronization Control register, offset: 0x80 */
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x84 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x88 */
       uint8_t RESERVED_5[4];
  __IO uint32_t VAD0_CTRL_1;                       /**< Voice Activity Detector 0 Control register, offset: 0x90 */
  __IO uint32_t VAD0_CTRL_2;                       /**< Voice Activity Detector 0 Control register, offset: 0x94 */
  __IO uint32_t VAD0_STAT;                         /**< Voice Activity Detector 0 Status register, offset: 0x98 */
  __IO uint32_t VAD0_SCONFIG;                      /**< Voice Activity Detector 0 Signal Configuration, offset: 0x9C */
  __IO uint32_t VAD0_NCONFIG;                      /**< Voice Activity Detector 0 Noise Configuration, offset: 0xA0 */
  __I  uint32_t VAD0_NDATA;                        /**< Voice Activity Detector 0 Noise Data, offset: 0xA4 */
  __IO uint32_t VAD0_ZCD;                          /**< Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8 */
} PDM_Type;

/* ----------------------------------------------------------------------------
   -- PDM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PDM_Register_Masks PDM Register Masks
 * @{
 */

/*! @name CTRL_1 - PDM Control register 1 */
/*! @{ */

#define PDM_CTRL_1_CH0EN_MASK                    (0x1U)
#define PDM_CTRL_1_CH0EN_SHIFT                   (0U)
/*! CH0EN - Channel 0 Enable */
#define PDM_CTRL_1_CH0EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)

#define PDM_CTRL_1_CH1EN_MASK                    (0x2U)
#define PDM_CTRL_1_CH1EN_SHIFT                   (1U)
/*! CH1EN - Channel 1 Enable */
#define PDM_CTRL_1_CH1EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)

#define PDM_CTRL_1_CH2EN_MASK                    (0x4U)
#define PDM_CTRL_1_CH2EN_SHIFT                   (2U)
/*! CH2EN - Channel 2 Enable */
#define PDM_CTRL_1_CH2EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)

#define PDM_CTRL_1_CH3EN_MASK                    (0x8U)
#define PDM_CTRL_1_CH3EN_SHIFT                   (3U)
/*! CH3EN - Channel 3 Enable */
#define PDM_CTRL_1_CH3EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)

#define PDM_CTRL_1_CH4EN_MASK                    (0x10U)
#define PDM_CTRL_1_CH4EN_SHIFT                   (4U)
/*! CH4EN - Channel 4 Enable */
#define PDM_CTRL_1_CH4EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)

#define PDM_CTRL_1_CH5EN_MASK                    (0x20U)
#define PDM_CTRL_1_CH5EN_SHIFT                   (5U)
/*! CH5EN - Channel 5 Enable */
#define PDM_CTRL_1_CH5EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)

#define PDM_CTRL_1_CH6EN_MASK                    (0x40U)
#define PDM_CTRL_1_CH6EN_SHIFT                   (6U)
/*! CH6EN - Channel 6 Enable */
#define PDM_CTRL_1_CH6EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)

#define PDM_CTRL_1_CH7EN_MASK                    (0x80U)
#define PDM_CTRL_1_CH7EN_SHIFT                   (7U)
/*! CH7EN - Channel 7 Enable */
#define PDM_CTRL_1_CH7EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)

#define PDM_CTRL_1_FSYNCEN_MASK                  (0x10000U)
#define PDM_CTRL_1_FSYNCEN_SHIFT                 (16U)
/*! FSYNCEN - Frame Synchronization Enable
 *  0b0..Frame synchronization disable
 *  0b1..Frame synchronization enable
 */
#define PDM_CTRL_1_FSYNCEN(x)                    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_FSYNCEN_SHIFT)) & PDM_CTRL_1_FSYNCEN_MASK)

#define PDM_CTRL_1_DECFILS_MASK                  (0x100000U)
#define PDM_CTRL_1_DECFILS_SHIFT                 (20U)
/*! DECFILS - Decimation filter enable in stop
 *  0b0..Decimation filter is stopped in SoC stop mode
 *  0b1..Decimation filter is kept running in SoC stop mode
 */
#define PDM_CTRL_1_DECFILS(x)                    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DECFILS_SHIFT)) & PDM_CTRL_1_DECFILS_MASK)

#define PDM_CTRL_1_ERREN_MASK                    (0x800000U)
#define PDM_CTRL_1_ERREN_SHIFT                   (23U)
/*! ERREN - Error Interruption Enable
 *  0b0..Error Interrupts disabled
 *  0b1..Error Interrupts enabled
 */
#define PDM_CTRL_1_ERREN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)

#define PDM_CTRL_1_DISEL_MASK                    (0x3000000U)
#define PDM_CTRL_1_DISEL_SHIFT                   (24U)
/*! DISEL - DMA Interrupt Selection
 *  0b00..DMA and interrupt requests disabled
 *  0b01..DMA requests enabled
 *  0b10..Interrupt requests enabled
 *  0b11..Reserved
 */
#define PDM_CTRL_1_DISEL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)

#define PDM_CTRL_1_DBGE_MASK                     (0x4000000U)
#define PDM_CTRL_1_DBGE_SHIFT                    (26U)
/*! DBGE - Module Enable in Debug
 *  0b0..Disabled after completing the current frame
 *  0b1..Enabled
 */
#define PDM_CTRL_1_DBGE(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)

#define PDM_CTRL_1_SRES_MASK                     (0x8000000U)
#define PDM_CTRL_1_SRES_SHIFT                    (27U)
/*! SRES - Software-reset bit
 *  0b0..No action
 *  0b1..Software reset
 */
#define PDM_CTRL_1_SRES(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)

#define PDM_CTRL_1_DBG_MASK                      (0x10000000U)
#define PDM_CTRL_1_DBG_SHIFT                     (28U)
/*! DBG - Debug Mode
 *  0b0..Normal Mode
 *  0b1..Debug Mode
 */
#define PDM_CTRL_1_DBG(x)                        (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)

#define PDM_CTRL_1_PDMIEN_MASK                   (0x20000000U)
#define PDM_CTRL_1_PDMIEN_SHIFT                  (29U)
/*! PDMIEN - PDM Enable
 *  0b0..PDM stopped
 *  0b1..PDM operation started
 */
#define PDM_CTRL_1_PDMIEN(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)

#define PDM_CTRL_1_DOZEN_MASK                    (0x40000000U)
#define PDM_CTRL_1_DOZEN_SHIFT                   (30U)
/*! DOZEN - DOZE enable */
#define PDM_CTRL_1_DOZEN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)

#define PDM_CTRL_1_MDIS_MASK                     (0x80000000U)
#define PDM_CTRL_1_MDIS_SHIFT                    (31U)
/*! MDIS - Module Disable
 *  0b0..Normal Mode
 *  0b1..Disable/Low Leakage Mode
 */
#define PDM_CTRL_1_MDIS(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
/*! @} */

/*! @name CTRL_2 - PDM Control register 2 */
/*! @{ */

#define PDM_CTRL_2_CLKDIV_MASK                   (0xFFU)
#define PDM_CTRL_2_CLKDIV_SHIFT                  (0U)
/*! CLKDIV - Clock Divider */
#define PDM_CTRL_2_CLKDIV(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)

#define PDM_CTRL_2_CLKDIVDIS_MASK                (0x8000U)
#define PDM_CTRL_2_CLKDIVDIS_SHIFT               (15U)
/*! CLKDIVDIS - Clock Divider Disable
 *  0b0..Clock Divider enable
 *  0b1..Clock Divider disable
 */
#define PDM_CTRL_2_CLKDIVDIS(x)                  (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIVDIS_SHIFT)) & PDM_CTRL_2_CLKDIVDIS_MASK)

#define PDM_CTRL_2_CICOSR_MASK                   (0xF0000U)
#define PDM_CTRL_2_CICOSR_SHIFT                  (16U)
/*! CICOSR - CIC Decimation Rate */
#define PDM_CTRL_2_CICOSR(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)

#define PDM_CTRL_2_QSEL_MASK                     (0xE000000U)
#define PDM_CTRL_2_QSEL_SHIFT                    (25U)
/*! QSEL - Quality Mode
 *  0b001..High quality mode
 *  0b000..Medium quality mode
 *  0b111..Low quality mode
 *  0b110..Very low quality 0 mode
 *  0b101..Very low quality 1 mode
 *  0b100..Very low quality 2 mode
 */
#define PDM_CTRL_2_QSEL(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)
/*! @} */

/*! @name STAT - PDM Status register */
/*! @{ */

#define PDM_STAT_CH0F_MASK                       (0x1U)
#define PDM_STAT_CH0F_SHIFT                      (0U)
/*! CH0F - Channel 0 Output Data Flag
 *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
 *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
 */
#define PDM_STAT_CH0F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)

#define PDM_STAT_CH1F_MASK                       (0x2U)
#define PDM_STAT_CH1F_SHIFT                      (1U)
/*! CH1F - Channel 1 Output Data Flag
 *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
 *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
 */
#define PDM_STAT_CH1F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)

#define PDM_STAT_CH2F_MASK                       (0x4U)
#define PDM_STAT_CH2F_SHIFT                      (2U)
/*! CH2F - Channel 2 Output Data Flag
 *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
 *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
 */
#define PDM_STAT_CH2F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)

#define PDM_STAT_CH3F_MASK                       (0x8U)
#define PDM_STAT_CH3F_SHIFT                      (3U)
/*! CH3F - Channel 3 Output Data Flag
 *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
 *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
 */
#define PDM_STAT_CH3F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)

#define PDM_STAT_CH4F_MASK                       (0x10U)
#define PDM_STAT_CH4F_SHIFT                      (4U)
/*! CH4F - Channel 4 Output Data Flag
 *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
 *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
 */
#define PDM_STAT_CH4F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)

#define PDM_STAT_CH5F_MASK                       (0x20U)
#define PDM_STAT_CH5F_SHIFT                      (5U)
/*! CH5F - Channel 5 Output Data Flag
 *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
 *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
 */
#define PDM_STAT_CH5F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)

#define PDM_STAT_CH6F_MASK                       (0x40U)
#define PDM_STAT_CH6F_SHIFT                      (6U)
/*! CH6F - Channel 6 Output Data Flag
 *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
 *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
 */
#define PDM_STAT_CH6F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)

#define PDM_STAT_CH7F_MASK                       (0x80U)
#define PDM_STAT_CH7F_SHIFT                      (7U)
/*! CH7F - Channel 7 Output Data Flag
 *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
 *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
 */
#define PDM_STAT_CH7F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)

#define PDM_STAT_BSY_FIL_MASK                    (0x80000000U)
#define PDM_STAT_BSY_FIL_SHIFT                   (31U)
/*! BSY_FIL - Busy Flag
 *  0b1..PDM is running
 *  0b0..PDM is stopped
 */
#define PDM_STAT_BSY_FIL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
/*! @} */

/*! @name FIFO_CTRL - PDM FIFO Control register */
/*! @{ */

#define PDM_FIFO_CTRL_FIFOWMK_MASK               (0x7U)
#define PDM_FIFO_CTRL_FIFOWMK_SHIFT              (0U)
/*! FIFOWMK - FIFO Watermark Control */
#define PDM_FIFO_CTRL_FIFOWMK(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/*! @} */

/*! @name FIFO_STAT - PDM FIFO Status register */
/*! @{ */

#define PDM_FIFO_STAT_FIFOOVF0_MASK              (0x1U)
#define PDM_FIFO_STAT_FIFOOVF0_SHIFT             (0U)
/*! FIFOOVF0 - FIFO Overflow Exception flag for Channel 0
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)

#define PDM_FIFO_STAT_FIFOOVF1_MASK              (0x2U)
#define PDM_FIFO_STAT_FIFOOVF1_SHIFT             (1U)
/*! FIFOOVF1 - FIFO Overflow Exception flag for Channel 1
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)

#define PDM_FIFO_STAT_FIFOOVF2_MASK              (0x4U)
#define PDM_FIFO_STAT_FIFOOVF2_SHIFT             (2U)
/*! FIFOOVF2 - FIFO Overflow Exception flag for Channel 2
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)

#define PDM_FIFO_STAT_FIFOOVF3_MASK              (0x8U)
#define PDM_FIFO_STAT_FIFOOVF3_SHIFT             (3U)
/*! FIFOOVF3 - FIFO Overflow Exception flag for Channel 3
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)

#define PDM_FIFO_STAT_FIFOOVF4_MASK              (0x10U)
#define PDM_FIFO_STAT_FIFOOVF4_SHIFT             (4U)
/*! FIFOOVF4 - FIFO Overflow Exception flag for Channel 4
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)

#define PDM_FIFO_STAT_FIFOOVF5_MASK              (0x20U)
#define PDM_FIFO_STAT_FIFOOVF5_SHIFT             (5U)
/*! FIFOOVF5 - FIFO Overflow Exception flag for Channel 5
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)

#define PDM_FIFO_STAT_FIFOOVF6_MASK              (0x40U)
#define PDM_FIFO_STAT_FIFOOVF6_SHIFT             (6U)
/*! FIFOOVF6 - FIFO Overflow Exception flag for Channel 6
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)

#define PDM_FIFO_STAT_FIFOOVF7_MASK              (0x80U)
#define PDM_FIFO_STAT_FIFOOVF7_SHIFT             (7U)
/*! FIFOOVF7 - FIFO Overflow Exception flag for Channel 7
 *  0b0..No exception by FIFO overflow
 *  0b1..Exception by FIFO overflow
 */
#define PDM_FIFO_STAT_FIFOOVF7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)

#define PDM_FIFO_STAT_FIFOUND0_MASK              (0x100U)
#define PDM_FIFO_STAT_FIFOUND0_SHIFT             (8U)
/*! FIFOUND0 - FIFO Underflow Exception flag for Channel 0
 *  0b0..No exception by FIFO Underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)

#define PDM_FIFO_STAT_FIFOUND1_MASK              (0x200U)
#define PDM_FIFO_STAT_FIFOUND1_SHIFT             (9U)
/*! FIFOUND1 - FIFO Underflow Exception flag for Channel 1
 *  0b0..No exception by FIFO Underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)

#define PDM_FIFO_STAT_FIFOUND2_MASK              (0x400U)
#define PDM_FIFO_STAT_FIFOUND2_SHIFT             (10U)
/*! FIFOUND2 - FIFO Underflow Exception flag for Channel 2
 *  0b0..No exception by FIFO Underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)

#define PDM_FIFO_STAT_FIFOUND3_MASK              (0x800U)
#define PDM_FIFO_STAT_FIFOUND3_SHIFT             (11U)
/*! FIFOUND3 - FIFO Underflow Exception flag for Channel 3
 *  0b0..No exception by FIFO Underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)

#define PDM_FIFO_STAT_FIFOUND4_MASK              (0x1000U)
#define PDM_FIFO_STAT_FIFOUND4_SHIFT             (12U)
/*! FIFOUND4 - FIFO Underflow Exception flag for Channel 4
 *  0b0..No exception by FIFO Underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)

#define PDM_FIFO_STAT_FIFOUND5_MASK              (0x2000U)
#define PDM_FIFO_STAT_FIFOUND5_SHIFT             (13U)
/*! FIFOUND5 - FIFO Underflow Exception flag for Channel 5
 *  0b0..No exception by FIFO Underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)

#define PDM_FIFO_STAT_FIFOUND6_MASK              (0x4000U)
#define PDM_FIFO_STAT_FIFOUND6_SHIFT             (14U)
/*! FIFOUND6 - FIFO Underflow Exception flag for Channel 6
 *  0b0..No exception by FIFO Underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)

#define PDM_FIFO_STAT_FIFOUND7_MASK              (0x8000U)
#define PDM_FIFO_STAT_FIFOUND7_SHIFT             (15U)
/*! FIFOUND7 - FIFO Underflow Exception flag for Channel 7
 *  0b0..No exception by FIFO Underflow
 *  0b1..Exception by FIFO underflow
 */
#define PDM_FIFO_STAT_FIFOUND7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)
/*! @} */

/*! @name DATACH - PDM Output Result Register */
/*! @{ */

#define PDM_DATACH_DATA_MASK                     (0xFFFFFFFFU)
#define PDM_DATACH_DATA_SHIFT                    (0U)
/*! DATA - Channel n Data */
#define PDM_DATACH_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)
/*! @} */

/* The count of PDM_DATACH */
#define PDM_DATACH_COUNT                         (8U)

/*! @name DC_CTRL - PDM DC Remover Control register */
/*! @{ */

#define PDM_DC_CTRL_DCCONFIG0_MASK               (0x3U)
#define PDM_DC_CTRL_DCCONFIG0_SHIFT              (0U)
/*! DCCONFIG0 - Channel 0 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (PDM_CLK=3.072MHz)
 *  0b01..DC Remover cut-off at 13.3Hz (PDM_CLK=3.072MHz)
 *  0b10..DC Remover cut-off at 40Hz (PDM_CLK=3.072MHz)
 */
#define PDM_DC_CTRL_DCCONFIG0(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)

#define PDM_DC_CTRL_DCCONFIG1_MASK               (0xCU)
#define PDM_DC_CTRL_DCCONFIG1_SHIFT              (2U)
/*! DCCONFIG1 - Channel 1 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (PDM_CLK=3.072MHz)
 *  0b01..DC Remover cut-off at 13.3Hz (PDM_CLK=3.072MHz)
 *  0b10..DC Remover cut-off at 40Hz (PDM_CLK=3.072MHz)
 */
#define PDM_DC_CTRL_DCCONFIG1(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)

#define PDM_DC_CTRL_DCCONFIG2_MASK               (0x30U)
#define PDM_DC_CTRL_DCCONFIG2_SHIFT              (4U)
/*! DCCONFIG2 - Channel 2 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (PDM_CLK=3.072MHz)
 *  0b01..DC Remover cut-off at 13.3Hz (PDM_CLK=3.072MHz)
 *  0b10..DC Remover cut-off at 40Hz (PDM_CLK=3.072MHz)
 */
#define PDM_DC_CTRL_DCCONFIG2(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)

#define PDM_DC_CTRL_DCCONFIG3_MASK               (0xC0U)
#define PDM_DC_CTRL_DCCONFIG3_SHIFT              (6U)
/*! DCCONFIG3 - Channel 3 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (PDM_CLK=3.072MHz)
 *  0b01..DC Remover cut-off at 13.3Hz (PDM_CLK=3.072MHz)
 *  0b10..DC Remover cut-off at 40Hz (PDM_CLK=3.072MHz)
 */
#define PDM_DC_CTRL_DCCONFIG3(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)

#define PDM_DC_CTRL_DCCONFIG4_MASK               (0x300U)
#define PDM_DC_CTRL_DCCONFIG4_SHIFT              (8U)
/*! DCCONFIG4 - Channel 4 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (PDM_CLK=3.072MHz)
 *  0b01..DC Remover cut-off at 13.3Hz (PDM_CLK=3.072MHz)
 *  0b10..DC Remover cut-off at 40Hz (PDM_CLK=3.072MHz)
 */
#define PDM_DC_CTRL_DCCONFIG4(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)

#define PDM_DC_CTRL_DCCONFIG5_MASK               (0xC00U)
#define PDM_DC_CTRL_DCCONFIG5_SHIFT              (10U)
/*! DCCONFIG5 - Channel 5 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (PDM_CLK=3.072MHz)
 *  0b01..DC Remover cut-off at 13.3Hz (PDM_CLK=3.072MHz)
 *  0b10..DC Remover cut-off at 40Hz (PDM_CLK=3.072MHz)
 */
#define PDM_DC_CTRL_DCCONFIG5(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)

#define PDM_DC_CTRL_DCCONFIG6_MASK               (0x3000U)
#define PDM_DC_CTRL_DCCONFIG6_SHIFT              (12U)
/*! DCCONFIG6 - Channel 6 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (PDM_CLK=3.072MHz)
 *  0b01..DC Remover cut-off at 13.3Hz (PDM_CLK=3.072MHz)
 *  0b10..DC Remover cut-off at 40Hz (PDM_CLK=3.072MHz)
 */
#define PDM_DC_CTRL_DCCONFIG6(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)

#define PDM_DC_CTRL_DCCONFIG7_MASK               (0xC000U)
#define PDM_DC_CTRL_DCCONFIG7_SHIFT              (14U)
/*! DCCONFIG7 - Channel 7 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (PDM_CLK=3.072MHz)
 *  0b01..DC Remover cut-off at 13.3Hz (PDM_CLK=3.072MHz)
 *  0b10..DC Remover cut-off at 40Hz (PDM_CLK=3.072MHz)
 */
#define PDM_DC_CTRL_DCCONFIG7(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)
/*! @} */

/*! @name DC_OUT_CTRL - PDM Output DC Remover Control register */
/*! @{ */

#define PDM_DC_OUT_CTRL_DCCONFIG0_MASK           (0x3U)
#define PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT          (0U)
/*! DCCONFIG0 - Channel 0 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (FS=48kHz)
 *  0b01..DC Remover cut-off at 13.3Hz (FS=48kHz)
 *  0b10..DC Remover cut-off at 40Hz (FS=48kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG0(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG0_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG1_MASK           (0xCU)
#define PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT          (2U)
/*! DCCONFIG1 - Channel 1 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (FS=48kHz)
 *  0b01..DC Remover cut-off at 13.3Hz (FS=48kHz)
 *  0b10..DC Remover cut-off at 40Hz (FS=48kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG1(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG1_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG2_MASK           (0x30U)
#define PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT          (4U)
/*! DCCONFIG2 - Channel 2 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (FS=48kHz)
 *  0b01..DC Remover cut-off at 13.3Hz (FS=48kHz)
 *  0b10..DC Remover cut-off at 40Hz (FS=48kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG2(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG2_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG3_MASK           (0xC0U)
#define PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT          (6U)
/*! DCCONFIG3 - Channel 3 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (FS=48kHz)
 *  0b01..DC Remover cut-off at 13.3Hz (FS=48kHz)
 *  0b10..DC Remover cut-off at 40Hz (FS=48kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG3(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG3_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG4_MASK           (0x300U)
#define PDM_DC_OUT_CTRL_DCCONFIG4_SHIFT          (8U)
/*! DCCONFIG4 - Channel 4 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (FS=48kHz)
 *  0b01..DC Remover cut-off at 13.3Hz (FS=48kHz)
 *  0b10..DC Remover cut-off at 40Hz (FS=48kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG4(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG4_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG5_MASK           (0xC00U)
#define PDM_DC_OUT_CTRL_DCCONFIG5_SHIFT          (10U)
/*! DCCONFIG5 - Channel 5 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (FS=48kHz)
 *  0b01..DC Remover cut-off at 13.3Hz (FS=48kHz)
 *  0b10..DC Remover cut-off at 40Hz (FS=48kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG5(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG5_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG6_MASK           (0x3000U)
#define PDM_DC_OUT_CTRL_DCCONFIG6_SHIFT          (12U)
/*! DCCONFIG6 - Channel 6 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (FS=48kHz)
 *  0b01..DC Remover cut-off at 13.3Hz (FS=48kHz)
 *  0b10..DC Remover cut-off at 40Hz (FS=48kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG6(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG6_MASK)

#define PDM_DC_OUT_CTRL_DCCONFIG7_MASK           (0xC000U)
#define PDM_DC_OUT_CTRL_DCCONFIG7_SHIFT          (14U)
/*! DCCONFIG7 - Channel 7 DC Remover Configuration
 *  0b11..DC Remover is bypassed
 *  0b00..DC Remover cut-off at 20Hz (FS=48kHz)
 *  0b01..DC Remover cut-off at 13.3Hz (FS=48kHz)
 *  0b10..DC Remover cut-off at 40Hz (FS=48kHz)
 */
#define PDM_DC_OUT_CTRL_DCCONFIG7(x)             (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG7_MASK)
/*! @} */

/*! @name RANGE_CTRL - PDM Range Control register */
/*! @{ */

#define PDM_RANGE_CTRL_RANGEADJ0_MASK            (0xFU)
#define PDM_RANGE_CTRL_RANGEADJ0_SHIFT           (0U)
/*! RANGEADJ0 - Channel 0 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)

#define PDM_RANGE_CTRL_RANGEADJ1_MASK            (0xF0U)
#define PDM_RANGE_CTRL_RANGEADJ1_SHIFT           (4U)
/*! RANGEADJ1 - Channel 1 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)

#define PDM_RANGE_CTRL_RANGEADJ2_MASK            (0xF00U)
#define PDM_RANGE_CTRL_RANGEADJ2_SHIFT           (8U)
/*! RANGEADJ2 - Channel 2 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)

#define PDM_RANGE_CTRL_RANGEADJ3_MASK            (0xF000U)
#define PDM_RANGE_CTRL_RANGEADJ3_SHIFT           (12U)
/*! RANGEADJ3 - Channel 3 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)

#define PDM_RANGE_CTRL_RANGEADJ4_MASK            (0xF0000U)
#define PDM_RANGE_CTRL_RANGEADJ4_SHIFT           (16U)
/*! RANGEADJ4 - Channel 4 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)

#define PDM_RANGE_CTRL_RANGEADJ5_MASK            (0xF00000U)
#define PDM_RANGE_CTRL_RANGEADJ5_SHIFT           (20U)
/*! RANGEADJ5 - Channel 5 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)

#define PDM_RANGE_CTRL_RANGEADJ6_MASK            (0xF000000U)
#define PDM_RANGE_CTRL_RANGEADJ6_SHIFT           (24U)
/*! RANGEADJ6 - Channel 6 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)

#define PDM_RANGE_CTRL_RANGEADJ7_MASK            (0xF0000000U)
#define PDM_RANGE_CTRL_RANGEADJ7_SHIFT           (28U)
/*! RANGEADJ7 - Channel 7 Range Adjustment */
#define PDM_RANGE_CTRL_RANGEADJ7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)
/*! @} */

/*! @name RANGE_STAT - PDM Range Status register */
/*! @{ */

#define PDM_RANGE_STAT_RANGEOVF0_MASK            (0x1U)
#define PDM_RANGE_STAT_RANGEOVF0_SHIFT           (0U)
/*! RANGEOVF0 - Channel 0 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)

#define PDM_RANGE_STAT_RANGEOVF1_MASK            (0x2U)
#define PDM_RANGE_STAT_RANGEOVF1_SHIFT           (1U)
/*! RANGEOVF1 - Channel 1 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)

#define PDM_RANGE_STAT_RANGEOVF2_MASK            (0x4U)
#define PDM_RANGE_STAT_RANGEOVF2_SHIFT           (2U)
/*! RANGEOVF2 - Channel 2 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)

#define PDM_RANGE_STAT_RANGEOVF3_MASK            (0x8U)
#define PDM_RANGE_STAT_RANGEOVF3_SHIFT           (3U)
/*! RANGEOVF3 - Channel 3 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)

#define PDM_RANGE_STAT_RANGEOVF4_MASK            (0x10U)
#define PDM_RANGE_STAT_RANGEOVF4_SHIFT           (4U)
/*! RANGEOVF4 - Channel 4 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)

#define PDM_RANGE_STAT_RANGEOVF5_MASK            (0x20U)
#define PDM_RANGE_STAT_RANGEOVF5_SHIFT           (5U)
/*! RANGEOVF5 - Channel 5 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)

#define PDM_RANGE_STAT_RANGEOVF6_MASK            (0x40U)
#define PDM_RANGE_STAT_RANGEOVF6_SHIFT           (6U)
/*! RANGEOVF6 - Channel 6 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)

#define PDM_RANGE_STAT_RANGEOVF7_MASK            (0x80U)
#define PDM_RANGE_STAT_RANGEOVF7_SHIFT           (7U)
/*! RANGEOVF7 - Channel 7 Range Overflow Error Flag
 *  0b0..No exception by range overflow
 *  0b1..Exception by range overflow
 */
#define PDM_RANGE_STAT_RANGEOVF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)

#define PDM_RANGE_STAT_RANGEUNF0_MASK            (0x10000U)
#define PDM_RANGE_STAT_RANGEUNF0_SHIFT           (16U)
/*! RANGEUNF0 - Channel 0 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)

#define PDM_RANGE_STAT_RANGEUNF1_MASK            (0x20000U)
#define PDM_RANGE_STAT_RANGEUNF1_SHIFT           (17U)
/*! RANGEUNF1 - Channel 1 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)

#define PDM_RANGE_STAT_RANGEUNF2_MASK            (0x40000U)
#define PDM_RANGE_STAT_RANGEUNF2_SHIFT           (18U)
/*! RANGEUNF2 - Channel 2 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)

#define PDM_RANGE_STAT_RANGEUNF3_MASK            (0x80000U)
#define PDM_RANGE_STAT_RANGEUNF3_SHIFT           (19U)
/*! RANGEUNF3 - Channel 3 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)

#define PDM_RANGE_STAT_RANGEUNF4_MASK            (0x100000U)
#define PDM_RANGE_STAT_RANGEUNF4_SHIFT           (20U)
/*! RANGEUNF4 - Channel 4 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)

#define PDM_RANGE_STAT_RANGEUNF5_MASK            (0x200000U)
#define PDM_RANGE_STAT_RANGEUNF5_SHIFT           (21U)
/*! RANGEUNF5 - Channel 5 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)

#define PDM_RANGE_STAT_RANGEUNF6_MASK            (0x400000U)
#define PDM_RANGE_STAT_RANGEUNF6_SHIFT           (22U)
/*! RANGEUNF6 - Channel 6 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)

#define PDM_RANGE_STAT_RANGEUNF7_MASK            (0x800000U)
#define PDM_RANGE_STAT_RANGEUNF7_SHIFT           (23U)
/*! RANGEUNF7 - Channel 7 Range Underflow Error Flag
 *  0b0..No exception by range underflow
 *  0b1..Exception by range underflow
 */
#define PDM_RANGE_STAT_RANGEUNF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)
/*! @} */

/*! @name FSYNC_CTRL - Frame Synchronization Control register */
/*! @{ */

#define PDM_FSYNC_CTRL_FSYNCLEN_MASK             (0xFFFFFFFFU)
#define PDM_FSYNC_CTRL_FSYNCLEN_SHIFT            (0U)
/*! FSYNCLEN - Frame Synchronization Window Length */
#define PDM_FSYNC_CTRL_FSYNCLEN(x)               (((uint32_t)(((uint32_t)(x)) << PDM_FSYNC_CTRL_FSYNCLEN_SHIFT)) & PDM_FSYNC_CTRL_FSYNCLEN_MASK)
/*! @} */

/*! @name VERID - Version ID Register */
/*! @{ */

#define PDM_VERID_FEATURE_MASK                   (0xFFFFU)
#define PDM_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Specification Number */
#define PDM_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_VERID_FEATURE_SHIFT)) & PDM_VERID_FEATURE_MASK)

#define PDM_VERID_MINOR_MASK                     (0xFF0000U)
#define PDM_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number */
#define PDM_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MINOR_SHIFT)) & PDM_VERID_MINOR_MASK)

#define PDM_VERID_MAJOR_MASK                     (0xFF000000U)
#define PDM_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number */
#define PDM_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MAJOR_SHIFT)) & PDM_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define PDM_PARAM_NPAIR_MASK                     (0xFU)
#define PDM_PARAM_NPAIR_SHIFT                    (0U)
/*! NPAIR - Number of microphone pairs */
#define PDM_PARAM_NPAIR(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NPAIR_SHIFT)) & PDM_PARAM_NPAIR_MASK)

#define PDM_PARAM_FIFO_PTRWID_MASK               (0xF0U)
#define PDM_PARAM_FIFO_PTRWID_SHIFT              (4U)
/*! FIFO_PTRWID - FIFO Pointer Width */
#define PDM_PARAM_FIFO_PTRWID(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIFO_PTRWID_SHIFT)) & PDM_PARAM_FIFO_PTRWID_MASK)

#define PDM_PARAM_FIL_OUT_WIDTH_24B_MASK         (0x100U)
#define PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT        (8U)
/*! FIL_OUT_WIDTH_24B - Filter Output Width
 *  0b0..Filter output width is 16 bits
 *  0b1..Filter output width is 24 bits
 */
#define PDM_PARAM_FIL_OUT_WIDTH_24B(x)           (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT)) & PDM_PARAM_FIL_OUT_WIDTH_24B_MASK)

#define PDM_PARAM_LOW_POWER_MASK                 (0x200U)
#define PDM_PARAM_LOW_POWER_SHIFT                (9U)
/*! LOW_POWER - Low power decimation filter */
#define PDM_PARAM_LOW_POWER(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_LOW_POWER_SHIFT)) & PDM_PARAM_LOW_POWER_MASK)

#define PDM_PARAM_DC_BYPASS_MASK                 (0x400U)
#define PDM_PARAM_DC_BYPASS_SHIFT                (10U)
/*! DC_BYPASS - Input DC remover bypass
 *  0b0..DC remover active.
 *  0b1..DC remover disabled.
 */
#define PDM_PARAM_DC_BYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_BYPASS_SHIFT)) & PDM_PARAM_DC_BYPASS_MASK)

#define PDM_PARAM_DC_OUT_BYPASS_MASK             (0x800U)
#define PDM_PARAM_DC_OUT_BYPASS_SHIFT            (11U)
/*! DC_OUT_BYPASS - Output DC remover bypass
 *  0b0..DC remover active.
 *  0b1..DC remover disabled.
 */
#define PDM_PARAM_DC_OUT_BYPASS(x)               (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_OUT_BYPASS_SHIFT)) & PDM_PARAM_DC_OUT_BYPASS_MASK)

#define PDM_PARAM_HWVAD_MASK                     (0x10000U)
#define PDM_PARAM_HWVAD_SHIFT                    (16U)
/*! HWVAD - HWVAD active */
#define PDM_PARAM_HWVAD(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_SHIFT)) & PDM_PARAM_HWVAD_MASK)

#define PDM_PARAM_HWVAD_ENERGY_MODE_MASK         (0x20000U)
#define PDM_PARAM_HWVAD_ENERGY_MODE_SHIFT        (17U)
/*! HWVAD_ENERGY_MODE - HWVAD energy mode active */
#define PDM_PARAM_HWVAD_ENERGY_MODE(x)           (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_ENERGY_MODE_SHIFT)) & PDM_PARAM_HWVAD_ENERGY_MODE_MASK)

#define PDM_PARAM_HWVAD_ZCD_MASK                 (0x80000U)
#define PDM_PARAM_HWVAD_ZCD_SHIFT                (19U)
/*! HWVAD_ZCD - HWVAD zero-cross detector active */
#define PDM_PARAM_HWVAD_ZCD(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_ZCD_SHIFT)) & PDM_PARAM_HWVAD_ZCD_MASK)

#define PDM_PARAM_NUM_HWVAD_MASK                 (0xF000000U)
#define PDM_PARAM_NUM_HWVAD_SHIFT                (24U)
/*! NUM_HWVAD - Number of HWVADs */
#define PDM_PARAM_NUM_HWVAD(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NUM_HWVAD_SHIFT)) & PDM_PARAM_NUM_HWVAD_MASK)
/*! @} */

/*! @name VAD0_CTRL_1 - Voice Activity Detector 0 Control register */
/*! @{ */

#define PDM_VAD0_CTRL_1_VADEN_MASK               (0x1U)
#define PDM_VAD0_CTRL_1_VADEN_SHIFT              (0U)
/*! VADEN - Voice Activity Detector Enable
 *  0b0..The HWVAD is disabled
 *  0b1..The HWVAD is enabled
 */
#define PDM_VAD0_CTRL_1_VADEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)

#define PDM_VAD0_CTRL_1_VADRST_MASK              (0x2U)
#define PDM_VAD0_CTRL_1_VADRST_SHIFT             (1U)
/*! VADRST - Voice Activity Detector Reset */
#define PDM_VAD0_CTRL_1_VADRST(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)

#define PDM_VAD0_CTRL_1_VADIE_MASK               (0x4U)
#define PDM_VAD0_CTRL_1_VADIE_SHIFT              (2U)
/*! VADIE - Voice Activity Detector Interruption Enable
 *  0b0..HWVAD Interrupts disabled
 *  0b1..HWVAD Interrupts enabled
 */
#define PDM_VAD0_CTRL_1_VADIE(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)

#define PDM_VAD0_CTRL_1_VADERIE_MASK             (0x8U)
#define PDM_VAD0_CTRL_1_VADERIE_SHIFT            (3U)
/*! VADERIE - Voice Activity Detector Error Interruption Enable
 *  0b0..HWVAD Error Interrupts disabled
 *  0b1..HWVAD Error Interrupts enabled
 */
#define PDM_VAD0_CTRL_1_VADERIE(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)

#define PDM_VAD0_CTRL_1_VADST10_MASK             (0x10U)
#define PDM_VAD0_CTRL_1_VADST10_SHIFT            (4U)
/*! VADST10 - Voice Activity Detector Internal Filters Initialization
 *  0b0..Normal operation.
 *  0b1..Filters are initialized.
 */
#define PDM_VAD0_CTRL_1_VADST10(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)

#define PDM_VAD0_CTRL_1_VADINITT_MASK            (0x1F00U)
#define PDM_VAD0_CTRL_1_VADINITT_SHIFT           (8U)
/*! VADINITT - Voice Activity Detector Initialization Time */
#define PDM_VAD0_CTRL_1_VADINITT(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)

#define PDM_VAD0_CTRL_1_VADCICOSR_MASK           (0xF0000U)
#define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT          (16U)
/*! VADCICOSR - Voice Activity Detector CIC Oversampling Rate */
#define PDM_VAD0_CTRL_1_VADCICOSR(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)

#define PDM_VAD0_CTRL_1_VADCHSEL_MASK            (0x7000000U)
#define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT           (24U)
/*! VADCHSEL - Voice Activity Detector Channel Selector */
#define PDM_VAD0_CTRL_1_VADCHSEL(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)
/*! @} */

/*! @name VAD0_CTRL_2 - Voice Activity Detector 0 Control register */
/*! @{ */

#define PDM_VAD0_CTRL_2_VADHPF_MASK              (0x3U)
#define PDM_VAD0_CTRL_2_VADHPF_SHIFT             (0U)
/*! VADHPF - Voice Activity Detector High-Pass Filter
 *  0b00..Filter bypassed.
 *  0b01..Cut-off frequency at 1750Hz.
 *  0b10..Cut-off frequency at 215Hz.
 *  0b11..Cut-off frequency at 102Hz.
 */
#define PDM_VAD0_CTRL_2_VADHPF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)

#define PDM_VAD0_CTRL_2_VADINPGAIN_MASK          (0xF00U)
#define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT         (8U)
/*! VADINPGAIN - Voice Activity Detector Input Gain */
#define PDM_VAD0_CTRL_2_VADINPGAIN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)

#define PDM_VAD0_CTRL_2_VADFRAMET_MASK           (0x3F0000U)
#define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT          (16U)
/*! VADFRAMET - Voice Activity Detector Frame Time */
#define PDM_VAD0_CTRL_2_VADFRAMET(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)

#define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK          (0x10000000U)
#define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT         (28U)
/*! VADFOUTDIS - Voice Activity Detector Force Output Disable
 *  0b0..Output is enabled.
 *  0b1..Output is disabled.
 */
#define PDM_VAD0_CTRL_2_VADFOUTDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)

#define PDM_VAD0_CTRL_2_VADPREFEN_MASK           (0x40000000U)
#define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT          (30U)
/*! VADPREFEN - Voice Activity Detector Pre Filter Enable
 *  0b0..Pre-filter is bypassed.
 *  0b1..Pre-filter is enabled.
 */
#define PDM_VAD0_CTRL_2_VADPREFEN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)

#define PDM_VAD0_CTRL_2_VADFRENDIS_MASK          (0x80000000U)
#define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT         (31U)
/*! VADFRENDIS - Voice Activity Detector Frame Energy Disable
 *  0b1..Frame energy calculus disabled.
 *  0b0..Frame energy calculus enabled.
 */
#define PDM_VAD0_CTRL_2_VADFRENDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)
/*! @} */

/*! @name VAD0_STAT - Voice Activity Detector 0 Status register */
/*! @{ */

#define PDM_VAD0_STAT_VADIF_MASK                 (0x1U)
#define PDM_VAD0_STAT_VADIF_SHIFT                (0U)
/*! VADIF - Voice Activity Detector Interrupt Flag
 *  0b0..Voice activity not detected
 *  0b1..Voice activity detected
 */
#define PDM_VAD0_STAT_VADIF(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)

#define PDM_VAD0_STAT_VADINSATF_MASK             (0x10000U)
#define PDM_VAD0_STAT_VADINSATF_SHIFT            (16U)
/*! VADINSATF - Voice Activity Detector Input Saturation Flag
 *  0b0..No exception
 *  0b1..Exception
 */
#define PDM_VAD0_STAT_VADINSATF(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)

#define PDM_VAD0_STAT_VADINITF_MASK              (0x80000000U)
#define PDM_VAD0_STAT_VADINITF_SHIFT             (31U)
/*! VADINITF - Voice Activity Detector Initialization Flag
 *  0b0..HWVAD is not being initialized.
 *  0b1..HWVAD is being initialized.
 */
#define PDM_VAD0_STAT_VADINITF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)
/*! @} */

/*! @name VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration */
/*! @{ */

#define PDM_VAD0_SCONFIG_VADSGAIN_MASK           (0xFU)
#define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT          (0U)
/*! VADSGAIN - Voice Activity Detector Signal Gain */
#define PDM_VAD0_SCONFIG_VADSGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)

#define PDM_VAD0_SCONFIG_VADSMAXEN_MASK          (0x40000000U)
#define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT         (30U)
/*! VADSMAXEN - Voice Activity Detector Signal Maximum Enable
 *  0b0..Maximum block is bypassed.
 *  0b1..Maximum block is enabled.
 */
#define PDM_VAD0_SCONFIG_VADSMAXEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)

#define PDM_VAD0_SCONFIG_VADSFILEN_MASK          (0x80000000U)
#define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT         (31U)
/*! VADSFILEN - Voice Activity Detector Signal Filter Enable
 *  0b0..Signal filter is disabled.
 *  0b1..Signal filter is enabled.
 */
#define PDM_VAD0_SCONFIG_VADSFILEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/*! @} */

/*! @name VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration */
/*! @{ */

#define PDM_VAD0_NCONFIG_VADNGAIN_MASK           (0xFU)
#define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT          (0U)
/*! VADNGAIN - Voice Activity Detector Noise Gain */
#define PDM_VAD0_NCONFIG_VADNGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)

#define PDM_VAD0_NCONFIG_VADNFILADJ_MASK         (0x1F00U)
#define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT        (8U)
/*! VADNFILADJ - Voice Activity Detector Noise Filter Adjustment */
#define PDM_VAD0_NCONFIG_VADNFILADJ(x)           (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)

#define PDM_VAD0_NCONFIG_VADNOREN_MASK           (0x10000000U)
#define PDM_VAD0_NCONFIG_VADNOREN_SHIFT          (28U)
/*! VADNOREN - Voice Activity Detector Noise OR Enable
 *  0b0..Noise input is not decimated.
 *  0b1..Noise input is decimated.
 */
#define PDM_VAD0_NCONFIG_VADNOREN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)

#define PDM_VAD0_NCONFIG_VADNDECEN_MASK          (0x20000000U)
#define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT         (29U)
/*! VADNDECEN - Voice Activity Detector Noise Decimation Enable
 *  0b0..Noise input is not decimated.
 *  0b1..Noise input is decimated.
 */
#define PDM_VAD0_NCONFIG_VADNDECEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)

#define PDM_VAD0_NCONFIG_VADNMINEN_MASK          (0x40000000U)
#define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT         (30U)
/*! VADNMINEN - Voice Activity Detector Noise Minimum Enable
 *  0b0..Minimum block is bypassed.
 *  0b1..Minimum block is enabled.
 */
#define PDM_VAD0_NCONFIG_VADNMINEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)

#define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK        (0x80000000U)
#define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT       (31U)
/*! VADNFILAUTO - Voice Activity Detector Noise Filter Auto
 *  0b0..Noise filter is always enabled.
 *  0b1..Noise filter is enabled/disabled based on voice activity information.
 */
#define PDM_VAD0_NCONFIG_VADNFILAUTO(x)          (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)
/*! @} */

/*! @name VAD0_NDATA - Voice Activity Detector 0 Noise Data */
/*! @{ */

#define PDM_VAD0_NDATA_VADNDATA_MASK             (0xFFFFU)
#define PDM_VAD0_NDATA_VADNDATA_SHIFT            (0U)
/*! VADNDATA - Voice Activity Detector Noise Data */
#define PDM_VAD0_NDATA_VADNDATA(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)
/*! @} */

/*! @name VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector */
/*! @{ */

#define PDM_VAD0_ZCD_VADZCDEN_MASK               (0x1U)
#define PDM_VAD0_ZCD_VADZCDEN_SHIFT              (0U)
/*! VADZCDEN - Zero-Crossing Detector Enable
 *  0b0..The ZCD is disabled
 *  0b1..The ZCD is enabled
 */
#define PDM_VAD0_ZCD_VADZCDEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)

#define PDM_VAD0_ZCD_VADZCDAUTO_MASK             (0x4U)
#define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT            (2U)
/*! VADZCDAUTO - Zero-Crossing Detector Automatic Threshold
 *  0b0..The ZCD threshold is not estimated automatically
 *  0b1..The ZCD threshold is estimated automatically
 */
#define PDM_VAD0_ZCD_VADZCDAUTO(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)

#define PDM_VAD0_ZCD_VADZCDAND_MASK              (0x10U)
#define PDM_VAD0_ZCD_VADZCDAND_SHIFT             (4U)
/*! VADZCDAND - Zero-Crossing Detector AND Behavior
 *  0b0..The ZCD result is OR'ed with the energy-based detection.
 *  0b1..The ZCD result is AND'ed with the energy-based detection.
 */
#define PDM_VAD0_ZCD_VADZCDAND(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)

#define PDM_VAD0_ZCD_VADZCDADJ_MASK              (0xF00U)
#define PDM_VAD0_ZCD_VADZCDADJ_SHIFT             (8U)
/*! VADZCDADJ - Zero-Crossing Detector Adjustment */
#define PDM_VAD0_ZCD_VADZCDADJ(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)

#define PDM_VAD0_ZCD_VADZCDTH_MASK               (0x3FF0000U)
#define PDM_VAD0_ZCD_VADZCDTH_SHIFT              (16U)
/*! VADZCDTH - Zero-Crossing Detector Threshold */
#define PDM_VAD0_ZCD_VADZCDTH(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PDM_Register_Masks */


/* PDM - Peripheral instance base addresses */
/** Peripheral PDM base address */
#define PDM_BASE                                 (0x28111000u)
/** Peripheral PDM base pointer */
#define PDM                                      ((PDM_Type *)PDM_BASE)
/** Array initializer of PDM peripheral base addresses */
#define PDM_BASE_ADDRS                           { PDM_BASE }
/** Array initializer of PDM peripheral base pointers */
#define PDM_BASE_PTRS                            { PDM }

/*!
 * @}
 */ /* end of group PDM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- POWERQUAD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer
 * @{
 */

/** POWERQUAD - Register Layout Typedef */
typedef struct {
  __IO uint32_t OUTBASE;                           /**< Output Base, offset: 0x0 */
  __IO uint32_t OUTFORMAT;                         /**< Output Format, offset: 0x4 */
  __IO uint32_t TMPBASE;                           /**< Temporary Base, offset: 0x8 */
  __IO uint32_t TMPFORMAT;                         /**< Temporary Format, offset: 0xC */
  __IO uint32_t INABASE;                           /**< Input A Base, offset: 0x10 */
  __IO uint32_t INAFORMAT;                         /**< Input A Format, offset: 0x14 */
  __IO uint32_t INBBASE;                           /**< Input B Base, offset: 0x18 */
  __IO uint32_t INBFORMAT;                         /**< Input B Format, offset: 0x1C */
       uint8_t RESERVED_0[224];
  __IO uint32_t CONTROL;                           /**< Control, offset: 0x100 */
  __IO uint32_t LENGTH;                            /**< Length, offset: 0x104 */
  __IO uint32_t CPPRE;                             /**< Coprocessor Pre-scale, offset: 0x108 */
  __IO uint32_t MISC;                              /**< Miscellaneous, offset: 0x10C */
  __IO uint32_t CURSORY;                           /**< Cursory, offset: 0x110 */
       uint8_t RESERVED_1[108];
  __IO uint32_t CORDIC_X;                          /**< Cordic input X, offset: 0x180 */
  __IO uint32_t CORDIC_Y;                          /**< Cordic Input Y, offset: 0x184 */
  __IO uint32_t CORDIC_Z;                          /**< Cordic Input Z, offset: 0x188 */
  __IO uint32_t ERRSTAT;                           /**< Error Status, offset: 0x18C */
  __IO uint32_t INTREN;                            /**< Interrupt Enable, offset: 0x190 */
  __IO uint32_t EVENTEN;                           /**< Event Enable, offset: 0x194 */
  __IO uint32_t INTRSTAT;                          /**< Interrupt Status, offset: 0x198 */
       uint8_t RESERVED_2[100];
  __IO uint32_t GPREG[16];                         /**< General Purpose Register Bank n, array offset: 0x200, array step: 0x4 */
  __IO uint32_t COMPREG[8];                        /**< Compute Register Bank n, array offset: 0x240, array step: 0x4 */
} POWERQUAD_Type;

/* ----------------------------------------------------------------------------
   -- POWERQUAD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks
 * @{
 */

/*! @name OUTBASE - Output Base */
/*! @{ */

#define POWERQUAD_OUTBASE_OUTBASE_MASK           (0xFFFFFFFFU)
#define POWERQUAD_OUTBASE_OUTBASE_SHIFT          (0U)
/*! OUTBASE - Base address register for the output region */
#define POWERQUAD_OUTBASE_OUTBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK)
/*! @} */

/*! @name OUTFORMAT - Output Format */
/*! @{ */

#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK   (0x3U)
#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT  (0U)
/*! OUT_FORMATINT - Output Internal Format */
#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK)

#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK   (0x30U)
#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT  (4U)
/*! OUT_FORMATEXT - Output External Format */
#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK)

#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK      (0xFF00U)
#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT     (8U)
/*! OUT_SCALER - Output Scaler Value */
#define POWERQUAD_OUTFORMAT_OUT_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK)
/*! @} */

/*! @name TMPBASE - Temporary Base */
/*! @{ */

#define POWERQUAD_TMPBASE_TMPBASE_MASK           (0xFFFFFFFFU)
#define POWERQUAD_TMPBASE_TMPBASE_SHIFT          (0U)
/*! TMPBASE - Base address register for the temporary region */
#define POWERQUAD_TMPBASE_TMPBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK)
/*! @} */

/*! @name TMPFORMAT - Temporary Format */
/*! @{ */

#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK   (0x3U)
#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT  (0U)
/*! TMP_FORMATINT - Temporary Internal Format */
#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK)

#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK   (0x30U)
#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT  (4U)
/*! TMP_FORMATEXT - Temporary External Format */
#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK)

#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK      (0xFF00U)
#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT     (8U)
/*! TMP_SCALER - Temporary Scaler Value */
#define POWERQUAD_TMPFORMAT_TMP_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK)
/*! @} */

/*! @name INABASE - Input A Base */
/*! @{ */

#define POWERQUAD_INABASE_INABASE_MASK           (0xFFFFFFFFU)
#define POWERQUAD_INABASE_INABASE_SHIFT          (0U)
/*! INABASE - Input A Base */
#define POWERQUAD_INABASE_INABASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK)
/*! @} */

/*! @name INAFORMAT - Input A Format */
/*! @{ */

#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK   (0x3U)
#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT  (0U)
/*! INA_FORMATINT - Input A Internal Format */
#define POWERQUAD_INAFORMAT_INA_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK)

#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK   (0x30U)
#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT  (4U)
/*! INA_FORMATEXT - Input A External Format */
#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK)

#define POWERQUAD_INAFORMAT_INA_SCALER_MASK      (0xFF00U)
#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT     (8U)
/*! INA_SCALER - Input A Scaler Value */
#define POWERQUAD_INAFORMAT_INA_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK)
/*! @} */

/*! @name INBBASE - Input B Base */
/*! @{ */

#define POWERQUAD_INBBASE_INBBASE_MASK           (0xFFFFFFFFU)
#define POWERQUAD_INBBASE_INBBASE_SHIFT          (0U)
/*! INBBASE - Input B Base */
#define POWERQUAD_INBBASE_INBBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK)
/*! @} */

/*! @name INBFORMAT - Input B Format */
/*! @{ */

#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK   (0x3U)
#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT  (0U)
/*! INB_FORMATINT - Input B Internal Format */
#define POWERQUAD_INBFORMAT_INB_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK)

#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK   (0x30U)
#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT  (4U)
/*! INB_FORMATEXT - Input B External Format */
#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK)

#define POWERQUAD_INBFORMAT_INB_SCALER_MASK      (0xFF00U)
#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT     (8U)
/*! INB_SCALER - Input B Scaler Value */
#define POWERQUAD_INBFORMAT_INB_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK)
/*! @} */

/*! @name CONTROL - Control */
/*! @{ */

#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK     (0xFU)
#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT    (0U)
/*! DECODE_OPCODE - Decode Opcode */
#define POWERQUAD_CONTROL_DECODE_OPCODE(x)       (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK)

#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK    (0xF0U)
#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT   (4U)
/*! DECODE_MACHINE - Decode Machine */
#define POWERQUAD_CONTROL_DECODE_MACHINE(x)      (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK)

#define POWERQUAD_CONTROL_INST_BUSY_MASK         (0x80000000U)
#define POWERQUAD_CONTROL_INST_BUSY_SHIFT        (31U)
/*! INST_BUSY - Instruction Busy */
#define POWERQUAD_CONTROL_INST_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK)
/*! @} */

/*! @name LENGTH - Length */
/*! @{ */

#define POWERQUAD_LENGTH_INST_LENGTH_MASK        (0xFFFFFFFFU)
#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT       (0U)
/*! INST_LENGTH - Instruction Length */
#define POWERQUAD_LENGTH_INST_LENGTH(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK)
/*! @} */

/*! @name CPPRE - Coprocessor Pre-scale */
/*! @{ */

#define POWERQUAD_CPPRE_CPPRE_IN_MASK            (0xFFU)
#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT           (0U)
/*! CPPRE_IN - Input */
#define POWERQUAD_CPPRE_CPPRE_IN(x)              (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK)

#define POWERQUAD_CPPRE_CPPRE_OUT_MASK           (0xFF00U)
#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT          (8U)
/*! CPPRE_OUT - Output */
#define POWERQUAD_CPPRE_CPPRE_OUT(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK)

#define POWERQUAD_CPPRE_CPPRE_SAT_MASK           (0x10000U)
#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT          (16U)
/*! CPPRE_SAT - Saturation
 *  0b0..No saturation
 *  0b1..Forces sub-32 bit saturation
 */
#define POWERQUAD_CPPRE_CPPRE_SAT(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK)

#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK          (0x20000U)
#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT         (17U)
/*! CPPRE_SAT8 - Saturation 8
 *  0b0..8 bits
 *  0b1..16 bits
 */
#define POWERQUAD_CPPRE_CPPRE_SAT8(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK)
/*! @} */

/*! @name MISC - Miscellaneous */
/*! @{ */

#define POWERQUAD_MISC_INST_MISC_MASK            (0xFFFFFFFFU)
#define POWERQUAD_MISC_INST_MISC_SHIFT           (0U)
/*! INST_MISC - For Matrix : Used for scaling factor */
#define POWERQUAD_MISC_INST_MISC(x)              (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK)
/*! @} */

/*! @name CURSORY - Cursory */
/*! @{ */

#define POWERQUAD_CURSORY_CURSORY_MASK           (0x1U)
#define POWERQUAD_CURSORY_CURSORY_SHIFT          (0U)
/*! CURSORY - Cursory Mode
 *  0b0..Disable Cursory mode
 *  0b1..Enable Cursory Mode
 */
#define POWERQUAD_CURSORY_CURSORY(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK)
/*! @} */

/*! @name CORDIC_X - Cordic input X */
/*! @{ */

#define POWERQUAD_CORDIC_X_CORDIC_X_MASK         (0xFFFFFFFFU)
#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT        (0U)
/*! CORDIC_X - Cordic Input x */
#define POWERQUAD_CORDIC_X_CORDIC_X(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK)
/*! @} */

/*! @name CORDIC_Y - Cordic Input Y */
/*! @{ */

#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK         (0xFFFFFFFFU)
#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT        (0U)
/*! CORDIC_Y - Cordic Input y */
#define POWERQUAD_CORDIC_Y_CORDIC_Y(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK)
/*! @} */

/*! @name CORDIC_Z - Cordic Input Z */
/*! @{ */

#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK         (0xFFFFFFFFU)
#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT        (0U)
/*! CORDIC_Z - Cordic Input z */
#define POWERQUAD_CORDIC_Z_CORDIC_Z(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK)
/*! @} */

/*! @name ERRSTAT - Error Status */
/*! @{ */

#define POWERQUAD_ERRSTAT_OVERFLOW_MASK          (0x1U)
#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT         (0U)
/*! OVERFLOW - Floating Point Overflow
 *  0b0..No Error
 *  0b1..Error on Floating Point Overflow
 */
#define POWERQUAD_ERRSTAT_OVERFLOW(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK)

#define POWERQUAD_ERRSTAT_NAN_MASK               (0x2U)
#define POWERQUAD_ERRSTAT_NAN_SHIFT              (1U)
/*! NAN - Floating Point NaN
 *  0b0..No Error
 *  0b1..Error on Floating Point NaN
 */
#define POWERQUAD_ERRSTAT_NAN(x)                 (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK)

#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK     (0x4U)
#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT    (2U)
/*! FIXEDOVERFLOW - Fixed Point Overflow
 *  0b0..No Error
 *  0b1..Error on Fixed Point Overflow
 */
#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x)       (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK)

#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK         (0x8U)
#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT        (3U)
/*! UNDERFLOW - Underflow
 *  0b0..No Error
 *  0b1..Error on Underflow
 */
#define POWERQUAD_ERRSTAT_UNDERFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK)

#define POWERQUAD_ERRSTAT_BUSERROR_MASK          (0x10U)
#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT         (4U)
/*! BUSERROR - Bus Error
 *  0b0..No Error
 *  0b1..Error on Bus
 */
#define POWERQUAD_ERRSTAT_BUSERROR(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK)
/*! @} */

/*! @name INTREN - Interrupt Enable */
/*! @{ */

#define POWERQUAD_INTREN_INTR_OFLOW_MASK         (0x1U)
#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT        (0U)
/*! INTR_OFLOW - Interrupt Floating Point Overflow
 *  0b0..Disable
 *  0b1..Enable interrupt on floating point overflow
 */
#define POWERQUAD_INTREN_INTR_OFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK)

#define POWERQUAD_INTREN_INTR_NAN_MASK           (0x2U)
#define POWERQUAD_INTREN_INTR_NAN_SHIFT          (1U)
/*! INTR_NAN - Interrupt Floating Point NaN
 *  0b0..Disable
 *  0b1..Enable interrupt on floating point NaN
 */
#define POWERQUAD_INTREN_INTR_NAN(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK)

#define POWERQUAD_INTREN_INTR_FIXED_MASK         (0x4U)
#define POWERQUAD_INTREN_INTR_FIXED_SHIFT        (2U)
/*! INTR_FIXED - Interrupt on Fixed Point Overflow
 *  0b0..Disable
 *  0b1..Enable interrupt on fixed point overflow
 */
#define POWERQUAD_INTREN_INTR_FIXED(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK)

#define POWERQUAD_INTREN_INTR_UFLOW_MASK         (0x8U)
#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT        (3U)
/*! INTR_UFLOW - Interrupt on Subnormal Truncation
 *  0b0..Disable
 *  0b1..Enable interrupt on subnormal truncation
 */
#define POWERQUAD_INTREN_INTR_UFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK)

#define POWERQUAD_INTREN_INTR_BERR_MASK          (0x10U)
#define POWERQUAD_INTREN_INTR_BERR_SHIFT         (4U)
/*! INTR_BERR - Interrupt on AHBM Bus Error
 *  0b0..Disable
 *  0b1..Enable interrupt on AHBM Bus Error
 */
#define POWERQUAD_INTREN_INTR_BERR(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK)

#define POWERQUAD_INTREN_INTR_COMP_MASK          (0x80U)
#define POWERQUAD_INTREN_INTR_COMP_SHIFT         (7U)
/*! INTR_COMP - Interrupt on Instruction Completion
 *  0b0..Disable
 *  0b1..Enable interrupt on instruction completion
 */
#define POWERQUAD_INTREN_INTR_COMP(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK)
/*! @} */

/*! @name EVENTEN - Event Enable */
/*! @{ */

#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK       (0x1U)
#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT      (0U)
/*! EVENT_OFLOW - Event Trigger on Floating Point Overflow
 *  0b0..Disable
 *  0b1..Enable event trigger on Floating point overflow
 */
#define POWERQUAD_EVENTEN_EVENT_OFLOW(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK)

#define POWERQUAD_EVENTEN_EVENT_NAN_MASK         (0x2U)
#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT        (1U)
/*! EVENT_NAN - Event Trigger on Floating Point NaN
 *  0b0..Disable
 *  0b1..Enable event trigger on floating point NaN
 */
#define POWERQUAD_EVENTEN_EVENT_NAN(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK)

#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK       (0x4U)
#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT      (2U)
/*! EVENT_FIXED - Event Trigger on Fixed Point Overflow
 *  0b0..Disable
 *  0b1..Enable event trigger on fixed point overflow
 */
#define POWERQUAD_EVENTEN_EVENT_FIXED(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK)

#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK       (0x8U)
#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT      (3U)
/*! EVENT_UFLOW - Event Trigger on Subnormal Truncation
 *  0b0..Disable
 *  0b1..Enable event trigger on subnormal truncation
 */
#define POWERQUAD_EVENTEN_EVENT_UFLOW(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK)

#define POWERQUAD_EVENTEN_EVENT_BERR_MASK        (0x10U)
#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT       (4U)
/*! EVENT_BERR - Event Trigger on AHBM Bus Error
 *  0b0..Disable
 *  0b1..Enable event trigger on AHBM bus error
 */
#define POWERQUAD_EVENTEN_EVENT_BERR(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK)

#define POWERQUAD_EVENTEN_EVENT_COMP_MASK        (0x80U)
#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT       (7U)
/*! EVENT_COMP - Event Trigger on Instruction Completion
 *  0b0..Disable
 *  0b1..Enable event trigger on instruction completion
 */
#define POWERQUAD_EVENTEN_EVENT_COMP(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK)
/*! @} */

/*! @name INTRSTAT - Interrupt Status */
/*! @{ */

#define POWERQUAD_INTRSTAT_INTR_STAT_MASK        (0x1U)
#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT       (0U)
/*! INTR_STAT - Interrupt Status
 *  0b0..No new interrupt
 *  0b1..Interrupt captured
 */
#define POWERQUAD_INTRSTAT_INTR_STAT(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK)
/*! @} */

/*! @name GPREG - General Purpose Register Bank n */
/*! @{ */

#define POWERQUAD_GPREG_GPREG_MASK               (0xFFFFFFFFU)
#define POWERQUAD_GPREG_GPREG_SHIFT              (0U)
/*! GPREG - General Purpose Register Bank */
#define POWERQUAD_GPREG_GPREG(x)                 (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK)
/*! @} */

/* The count of POWERQUAD_GPREG */
#define POWERQUAD_GPREG_COUNT                    (16U)

/*! @name COMPREGS_COMPREG - Compute Register Bank n */
/*! @{ */

#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK  (0xFFFFFFFFU)
#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U)
/*! COMPREG - Compute Register Bank */
#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x)    (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK)
/*! @} */

/* The count of POWERQUAD_COMPREGS_COMPREG */
#define POWERQUAD_COMPREGS_COMPREG_COUNT         (8U)


/*!
 * @}
 */ /* end of group POWERQUAD_Register_Masks */


/* POWERQUAD - Peripheral instance base addresses */
/** Peripheral POWERQUAD base address */
#define POWERQUAD_BASE                           (0x28400000u)
/** Peripheral POWERQUAD base pointer */
#define POWERQUAD                                ((POWERQUAD_Type *)POWERQUAD_BASE)
/** Array initializer of POWERQUAD peripheral base addresses */
#define POWERQUAD_BASE_ADDRS                     { POWERQUAD_BASE }
/** Array initializer of POWERQUAD peripheral base pointers */
#define POWERQUAD_BASE_PTRS                      { POWERQUAD }

/*!
 * @}
 */ /* end of group POWERQUAD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PXP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer
 * @{
 */

/** PXP - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< Control Register 0, offset: 0x0 */
  __IO uint32_t CTRL_SET;                          /**< Control Register 0, offset: 0x4 */
  __IO uint32_t CTRL_CLR;                          /**< Control Register 0, offset: 0x8 */
  __IO uint32_t CTRL_TOG;                          /**< Control Register 0, offset: 0xC */
  __IO uint32_t STAT;                              /**< Status Register, offset: 0x10 */
  __IO uint32_t STAT_SET;                          /**< Status Register, offset: 0x14 */
  __IO uint32_t STAT_CLR;                          /**< Status Register, offset: 0x18 */
  __IO uint32_t STAT_TOG;                          /**< Status Register, offset: 0x1C */
  __IO uint32_t OUT_CTRL;                          /**< Output Buffer Control Register, offset: 0x20 */
  __IO uint32_t OUT_CTRL_SET;                      /**< Output Buffer Control Register, offset: 0x24 */
  __IO uint32_t OUT_CTRL_CLR;                      /**< Output Buffer Control Register, offset: 0x28 */
  __IO uint32_t OUT_CTRL_TOG;                      /**< Output Buffer Control Register, offset: 0x2C */
  __IO uint32_t OUT_BUF;                           /**< Output Frame Buffer Pointer, offset: 0x30 */
       uint8_t RESERVED_0[12];
  __IO uint32_t OUT_BUF2;                          /**< Output Frame Buffer Pointer #2, offset: 0x40 */
       uint8_t RESERVED_1[12];
  __IO uint32_t OUT_PITCH;                         /**< Output Buffer Pitch, offset: 0x50 */
       uint8_t RESERVED_2[12];
  __IO uint32_t OUT_LRC;                           /**< Output Surface Lower Right Coordinate, offset: 0x60 */
       uint8_t RESERVED_3[12];
  __IO uint32_t OUT_PS_ULC;                        /**< Processed Surface Upper Left Coordinate, offset: 0x70 */
       uint8_t RESERVED_4[12];
  __IO uint32_t OUT_PS_LRC;                        /**< Processed Surface Lower Right Coordinate, offset: 0x80 */
       uint8_t RESERVED_5[12];
  __IO uint32_t OUT_AS_ULC;                        /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */
       uint8_t RESERVED_6[12];
  __IO uint32_t OUT_AS_LRC;                        /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */
       uint8_t RESERVED_7[12];
  __IO uint32_t PS_CTRL;                           /**< Processed Surface (PS) Control Register, offset: 0xB0 */
  __IO uint32_t PS_CTRL_SET;                       /**< Processed Surface (PS) Control Register, offset: 0xB4 */
  __IO uint32_t PS_CTRL_CLR;                       /**< Processed Surface (PS) Control Register, offset: 0xB8 */
  __IO uint32_t PS_CTRL_TOG;                       /**< Processed Surface (PS) Control Register, offset: 0xBC */
  __IO uint32_t PS_BUF;                            /**< PS Input Buffer Address, offset: 0xC0 */
       uint8_t RESERVED_8[12];
  __IO uint32_t PS_UBUF;                           /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */
       uint8_t RESERVED_9[12];
  __IO uint32_t PS_VBUF;                           /**< PS V/Cr Input Buffer Address, offset: 0xE0 */
       uint8_t RESERVED_10[12];
  __IO uint32_t PS_PITCH;                          /**< Processed Surface Pitch, offset: 0xF0 */
       uint8_t RESERVED_11[12];
  __IO uint32_t PS_BACKGROUND_0;                   /**< PS Background Color, offset: 0x100 */
       uint8_t RESERVED_12[12];
  __IO uint32_t PS_SCALE;                          /**< PS Scale Factor Register, offset: 0x110 */
       uint8_t RESERVED_13[12];
  __IO uint32_t PS_OFFSET;                         /**< PS Scale Offset Register, offset: 0x120 */
       uint8_t RESERVED_14[12];
  __IO uint32_t PS_CLRKEYLOW_0;                    /**< PS Color Key Low, offset: 0x130 */
       uint8_t RESERVED_15[12];
  __IO uint32_t PS_CLRKEYHIGH_0;                   /**< PS Color Key High, offset: 0x140 */
       uint8_t RESERVED_16[12];
  __IO uint32_t AS_CTRL;                           /**< Alpha Surface Control, offset: 0x150 */
       uint8_t RESERVED_17[12];
  __IO uint32_t AS_BUF;                            /**< Alpha Surface Buffer Pointer, offset: 0x160 */
       uint8_t RESERVED_18[12];
  __IO uint32_t AS_PITCH;                          /**< Alpha Surface Pitch, offset: 0x170 */
       uint8_t RESERVED_19[12];
  __IO uint32_t AS_CLRKEYLOW_0;                    /**< Overlay Color Key Low, offset: 0x180 */
       uint8_t RESERVED_20[12];
  __IO uint32_t AS_CLRKEYHIGH_0;                   /**< Overlay Color Key High, offset: 0x190 */
       uint8_t RESERVED_21[12];
  __IO uint32_t CSC1_COEF0;                        /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */
       uint8_t RESERVED_22[12];
  __IO uint32_t CSC1_COEF1;                        /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */
       uint8_t RESERVED_23[12];
  __IO uint32_t CSC1_COEF2;                        /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */
       uint8_t RESERVED_24[12];
  __IO uint32_t CSC2_CTRL;                         /**< Color Space Conversion Control Register., offset: 0x1D0 */
       uint8_t RESERVED_25[12];
  __IO uint32_t CSC2_COEF0;                        /**< Color Space Conversion Coefficient Register 0, offset: 0x1E0 */
       uint8_t RESERVED_26[12];
  __IO uint32_t CSC2_COEF1;                        /**< Color Space Conversion Coefficient Register 1, offset: 0x1F0 */
       uint8_t RESERVED_27[12];
  __IO uint32_t CSC2_COEF2;                        /**< Color Space Conversion Coefficient Register 2, offset: 0x200 */
       uint8_t RESERVED_28[12];
  __IO uint32_t CSC2_COEF3;                        /**< Color Space Conversion Coefficient Register 3, offset: 0x210 */
       uint8_t RESERVED_29[12];
  __IO uint32_t CSC2_COEF4;                        /**< Color Space Conversion Coefficient Register 4, offset: 0x220 */
       uint8_t RESERVED_30[12];
  __IO uint32_t CSC2_COEF5;                        /**< Color Space Conversion Coefficient Register 5, offset: 0x230 */
       uint8_t RESERVED_31[12];
  __IO uint32_t LUT_CTRL;                          /**< Lookup Table Control Register., offset: 0x240 */
       uint8_t RESERVED_32[12];
  __IO uint32_t LUT_ADDR;                          /**< Lookup Table Control Register., offset: 0x250 */
       uint8_t RESERVED_33[12];
  __IO uint32_t LUT_DATA;                          /**< Lookup Table Data Register., offset: 0x260 */
       uint8_t RESERVED_34[12];
  __IO uint32_t LUT_EXTMEM;                        /**< Lookup Table External Memory Address Register., offset: 0x270 */
       uint8_t RESERVED_35[12];
  __IO uint32_t CFA;                               /**< Color Filter Array Register., offset: 0x280 */
       uint8_t RESERVED_36[12];
  __IO uint32_t ALPHA_A_CTRL;                      /**< PXP Alpha Engine A Control Register., offset: 0x290 */
       uint8_t RESERVED_37[12];
  __IO uint32_t ALPHA_B_CTRL;                      /**< PXP Alpha Engine B Control Register., offset: 0x2A0 */
       uint8_t RESERVED_38[12];
  __IO uint32_t ALPHA_B_CTRL_1;                    /**< offset: 0x2B0 */
       uint8_t RESERVED_39[12];
  __IO uint32_t PS_BACKGROUND_1;                   /**< PS Background Color 1, offset: 0x2C0 */
       uint8_t RESERVED_40[12];
  __IO uint32_t PS_CLRKEYLOW_1;                    /**< PS Color Key Low 1, offset: 0x2D0 */
       uint8_t RESERVED_41[12];
  __IO uint32_t PS_CLRKEYHIGH_1;                   /**< PS Color Key High 1, offset: 0x2E0 */
       uint8_t RESERVED_42[12];
  __IO uint32_t AS_CLRKEYLOW_1;                    /**< Overlay Color Key Low, offset: 0x2F0 */
       uint8_t RESERVED_43[12];
  __IO uint32_t AS_CLRKEYHIGH_1;                   /**< Overlay Color Key High, offset: 0x300 */
       uint8_t RESERVED_44[12];
  __IO uint32_t CTRL2;                             /**< Control Register 2, offset: 0x310 */
  __IO uint32_t CTRL2_SET;                         /**< Control Register 2, offset: 0x314 */
  __IO uint32_t CTRL2_CLR;                         /**< Control Register 2, offset: 0x318 */
  __IO uint32_t CTRL2_TOG;                         /**< Control Register 2, offset: 0x31C */
  __IO uint32_t POWER_REG0;                        /**< PXP Power Control Register., offset: 0x320 */
       uint8_t RESERVED_45[12];
  __IO uint32_t POWER_REG1;                        /**< PXP Power Control Register 1., offset: 0x330 */
       uint8_t RESERVED_46[12];
  __IO uint32_t DATA_PATH_CTRL0;                   /**< offset: 0x340 */
  __IO uint32_t DATA_PATH_CTRL0_SET;               /**< offset: 0x344 */
  __IO uint32_t DATA_PATH_CTRL0_CLR;               /**< offset: 0x348 */
  __IO uint32_t DATA_PATH_CTRL0_TOG;               /**< offset: 0x34C */
  __IO uint32_t DATA_PATH_CTRL1;                   /**< offset: 0x350 */
  __IO uint32_t DATA_PATH_CTRL1_SET;               /**< offset: 0x354 */
  __IO uint32_t DATA_PATH_CTRL1_CLR;               /**< offset: 0x358 */
  __IO uint32_t DATA_PATH_CTRL1_TOG;               /**< offset: 0x35C */
  __IO uint32_t INIT_MEM_CTRL;                     /**< Initialize memory buffer control Register, offset: 0x360 */
  __IO uint32_t INIT_MEM_CTRL_SET;                 /**< Initialize memory buffer control Register, offset: 0x364 */
  __IO uint32_t INIT_MEM_CTRL_CLR;                 /**< Initialize memory buffer control Register, offset: 0x368 */
  __IO uint32_t INIT_MEM_CTRL_TOG;                 /**< Initialize memory buffer control Register, offset: 0x36C */
  __IO uint32_t INIT_MEM_DATA;                     /**< Write data Register, offset: 0x370 */
       uint8_t RESERVED_47[12];
  __IO uint32_t INIT_MEM_DATA_HIGH;                /**< Write data Register, offset: 0x380 */
       uint8_t RESERVED_48[12];
  __IO uint32_t IRQ_MASK;                          /**< PXP IRQ Mask Register, offset: 0x390 */
  __IO uint32_t IRQ_MASK_SET;                      /**< PXP IRQ Mask Register, offset: 0x394 */
  __IO uint32_t IRQ_MASK_CLR;                      /**< PXP IRQ Mask Register, offset: 0x398 */
  __IO uint32_t IRQ_MASK_TOG;                      /**< PXP IRQ Mask Register, offset: 0x39C */
  __IO uint32_t IRQ;                               /**< PXP Interrupt Register, offset: 0x3A0 */
  __IO uint32_t IRQ_SET;                           /**< PXP Interrupt Register, offset: 0x3A4 */
  __IO uint32_t IRQ_CLR;                           /**< PXP Interrupt Register, offset: 0x3A8 */
  __IO uint32_t IRQ_TOG;                           /**< PXP Interrupt Register, offset: 0x3AC */
       uint8_t RESERVED_49[80];
  __IO uint32_t NEXT;                              /**< Next Frame Pointer, offset: 0x400 */
       uint8_t RESERVED_50[76];
  __IO uint32_t INPUT_FETCH_CTRL_CH0;              /**< Pre-fetch engine Control Channel 0 Register, offset: 0x450 */
  __IO uint32_t INPUT_FETCH_CTRL_CH0_SET;          /**< Pre-fetch engine Control Channel 0 Register, offset: 0x454 */
  __IO uint32_t INPUT_FETCH_CTRL_CH0_CLR;          /**< Pre-fetch engine Control Channel 0 Register, offset: 0x458 */
  __IO uint32_t INPUT_FETCH_CTRL_CH0_TOG;          /**< Pre-fetch engine Control Channel 0 Register, offset: 0x45C */
  __IO uint32_t INPUT_FETCH_CTRL_CH1;              /**< Pre-fetch engine Control Channel 1 Register, offset: 0x460 */
  __IO uint32_t INPUT_FETCH_CTRL_CH1_SET;          /**< Pre-fetch engine Control Channel 1 Register, offset: 0x464 */
  __IO uint32_t INPUT_FETCH_CTRL_CH1_CLR;          /**< Pre-fetch engine Control Channel 1 Register, offset: 0x468 */
  __IO uint32_t INPUT_FETCH_CTRL_CH1_TOG;          /**< Pre-fetch engine Control Channel 1 Register, offset: 0x46C */
  __I  uint32_t INPUT_FETCH_STATUS_CH0;            /**< Pre-fetch engine status Channel 0 Register, offset: 0x470 */
       uint8_t RESERVED_51[12];
  __I  uint32_t INPUT_FETCH_STATUS_CH1;            /**< Store engine status Channel 1 Register, offset: 0x480 */
       uint8_t RESERVED_52[12];
  __IO uint32_t INPUT_FETCH_ACTIVE_SIZE_ULC_CH0;   /**< offset: 0x490 */
       uint8_t RESERVED_53[12];
  __IO uint32_t INPUT_FETCH_ACTIVE_SIZE_LRC_CH0;   /**< offset: 0x4A0 */
       uint8_t RESERVED_54[12];
  __IO uint32_t INPUT_FETCH_ACTIVE_SIZE_ULC_CH1;   /**< offset: 0x4B0 */
       uint8_t RESERVED_55[12];
  __IO uint32_t INPUT_FETCH_ACTIVE_SIZE_LRC_CH1;   /**< offset: 0x4C0 */
       uint8_t RESERVED_56[12];
  __IO uint32_t INPUT_FETCH_SIZE_CH0;              /**< offset: 0x4D0 */
       uint8_t RESERVED_57[12];
  __IO uint32_t INPUT_FETCH_SIZE_CH1;              /**< offset: 0x4E0 */
       uint8_t RESERVED_58[12];
  __IO uint32_t INPUT_FETCH_BACKGROUND_COLOR_CH0;  /**< offset: 0x4F0 */
       uint8_t RESERVED_59[12];
  __IO uint32_t INPUT_FETCH_BACKGROUND_COLOR_CH1;  /**< offset: 0x500 */
       uint8_t RESERVED_60[12];
  __IO uint32_t INPUT_FETCH_PITCH;                 /**< offset: 0x510 */
       uint8_t RESERVED_61[12];
  __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH0;        /**< offset: 0x520 */
  __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH0_SET;    /**< offset: 0x524 */
  __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH0_CLR;    /**< offset: 0x528 */
  __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH0_TOG;    /**< offset: 0x52C */
  __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH1;        /**< offset: 0x530 */
  __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH1_SET;    /**< offset: 0x534 */
  __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH1_CLR;    /**< offset: 0x538 */
  __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH1_TOG;    /**< offset: 0x53C */
  __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH0;      /**< offset: 0x540 */
  __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH0_SET;  /**< offset: 0x544 */
  __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH0_CLR;  /**< offset: 0x548 */
  __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH0_TOG;  /**< offset: 0x54C */
  __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH1;      /**< offset: 0x550 */
  __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH1_SET;  /**< offset: 0x554 */
  __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH1_CLR;  /**< offset: 0x558 */
  __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH1_TOG;  /**< offset: 0x55C */
  __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH0;       /**< offset: 0x560 */
  __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH0_SET;   /**< offset: 0x564 */
  __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH0_CLR;   /**< offset: 0x568 */
  __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH0_TOG;   /**< offset: 0x56C */
  __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH1;       /**< offset: 0x570 */
  __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH1_SET;   /**< offset: 0x574 */
  __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH1_CLR;   /**< offset: 0x578 */
  __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH1_TOG;   /**< offset: 0x57C */
  __IO uint32_t INPUT_FETCH_ADDR_0_CH0;            /**< offset: 0x580 */
       uint8_t RESERVED_62[12];
  __IO uint32_t INPUT_FETCH_ADDR_1_CH0;            /**< offset: 0x590 */
       uint8_t RESERVED_63[12];
  __IO uint32_t INPUT_FETCH_ADDR_0_CH1;            /**< offset: 0x5A0 */
       uint8_t RESERVED_64[12];
  __IO uint32_t INPUT_FETCH_ADDR_1_CH1;            /**< offset: 0x5B0 */
       uint8_t RESERVED_65[12];
  __IO uint32_t INPUT_STORE_CTRL_CH0;              /**< Store engine Control Channel 0 Register, offset: 0x5C0 */
  __IO uint32_t INPUT_STORE_CTRL_CH0_SET;          /**< Store engine Control Channel 0 Register, offset: 0x5C4 */
  __IO uint32_t INPUT_STORE_CTRL_CH0_CLR;          /**< Store engine Control Channel 0 Register, offset: 0x5C8 */
  __IO uint32_t INPUT_STORE_CTRL_CH0_TOG;          /**< Store engine Control Channel 0 Register, offset: 0x5CC */
  __IO uint32_t INPUT_STORE_CTRL_CH1;              /**< Store engine Control Channel 1 Register, offset: 0x5D0 */
  __IO uint32_t INPUT_STORE_CTRL_CH1_SET;          /**< Store engine Control Channel 1 Register, offset: 0x5D4 */
  __IO uint32_t INPUT_STORE_CTRL_CH1_CLR;          /**< Store engine Control Channel 1 Register, offset: 0x5D8 */
  __IO uint32_t INPUT_STORE_CTRL_CH1_TOG;          /**< Store engine Control Channel 1 Register, offset: 0x5DC */
  __I  uint32_t INPUT_STORE_STATUS_CH0;            /**< Store engine status Channel 0 Register, offset: 0x5E0 */
       uint8_t RESERVED_66[12];
  __I  uint32_t INPUT_STORE_STATUS_CH1;            /**< Store engine status Channel 1 Register, offset: 0x5F0 */
       uint8_t RESERVED_67[12];
  __IO uint32_t INPUT_STORE_SIZE_CH0;              /**< offset: 0x600 */
       uint8_t RESERVED_68[12];
  __IO uint32_t INPUT_STORE_SIZE_CH1;              /**< offset: 0x610 */
       uint8_t RESERVED_69[12];
  __IO uint32_t INPUT_STORE_PITCH;                 /**< offset: 0x620 */
       uint8_t RESERVED_70[12];
  __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH0;        /**< offset: 0x630 */
  __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH0_SET;    /**< offset: 0x634 */
  __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH0_CLR;    /**< offset: 0x638 */
  __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH0_TOG;    /**< offset: 0x63C */
  __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH1;        /**< offset: 0x640 */
  __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH1_SET;    /**< offset: 0x644 */
  __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH1_CLR;    /**< offset: 0x648 */
  __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH1_TOG;    /**< offset: 0x64C */
       uint8_t RESERVED_71[64];
  __IO uint32_t INPUT_STORE_ADDR_0_CH0;            /**< offset: 0x690 */
       uint8_t RESERVED_72[12];
  __IO uint32_t INPUT_STORE_ADDR_1_CH0;            /**< offset: 0x6A0 */
       uint8_t RESERVED_73[12];
  __IO uint32_t INPUT_STORE_FILL_DATA_CH0;         /**< offset: 0x6B0 */
       uint8_t RESERVED_74[12];
  __IO uint32_t INPUT_STORE_ADDR_0_CH1;            /**< offset: 0x6C0 */
       uint8_t RESERVED_75[12];
  __IO uint32_t INPUT_STORE_ADDR_1_CH1;            /**< offset: 0x6D0 */
       uint8_t RESERVED_76[12];
  __IO uint32_t INPUT_STORE_D_MASK0_H_CH0;         /**< offset: 0x6E0 */
       uint8_t RESERVED_77[12];
  __IO uint32_t INPUT_STORE_D_MASK0_L_CH0;         /**< offset: 0x6F0 */
       uint8_t RESERVED_78[12];
  __IO uint32_t INPUT_STORE_D_MASK1_H_CH0;         /**< offset: 0x700 */
       uint8_t RESERVED_79[12];
  __IO uint32_t INPUT_STORE_D_MASK1_L_CH0;         /**< offset: 0x710 */
       uint8_t RESERVED_80[12];
  __IO uint32_t INPUT_STORE_D_MASK2_H_CH0;         /**< offset: 0x720 */
       uint8_t RESERVED_81[12];
  __IO uint32_t INPUT_STORE_D_MASK2_L_CH0;         /**< offset: 0x730 */
       uint8_t RESERVED_82[12];
  __IO uint32_t INPUT_STORE_D_MASK3_H_CH0;         /**< offset: 0x740 */
       uint8_t RESERVED_83[12];
  __IO uint32_t INPUT_STORE_D_MASK3_L_CH0;         /**< offset: 0x750 */
       uint8_t RESERVED_84[12];
  __IO uint32_t INPUT_STORE_D_MASK4_H_CH0;         /**< offset: 0x760 */
       uint8_t RESERVED_85[12];
  __IO uint32_t INPUT_STORE_D_MASK4_L_CH0;         /**< offset: 0x770 */
       uint8_t RESERVED_86[12];
  __IO uint32_t INPUT_STORE_D_MASK5_H_CH0;         /**< offset: 0x780 */
       uint8_t RESERVED_87[12];
  __IO uint32_t INPUT_STORE_D_MASK5_L_CH0;         /**< offset: 0x790 */
       uint8_t RESERVED_88[12];
  __IO uint32_t INPUT_STORE_D_MASK6_H_CH0;         /**< offset: 0x7A0 */
       uint8_t RESERVED_89[12];
  __IO uint32_t INPUT_STORE_D_MASK6_L_CH0;         /**< offset: 0x7B0 */
       uint8_t RESERVED_90[12];
  __IO uint32_t INPUT_STORE_D_MASK7_H_CH0;         /**< offset: 0x7C0 */
       uint8_t RESERVED_91[28];
  __IO uint32_t INPUT_STORE_D_MASK7_L_CH0;         /**< offset: 0x7E0 */
       uint8_t RESERVED_92[12];
  __IO uint32_t INPUT_STORE_D_SHIFT_L_CH0;         /**< offset: 0x7F0 */
       uint8_t RESERVED_93[12];
  __IO uint32_t INPUT_STORE_D_SHIFT_H_CH0;         /**< offset: 0x800 */
       uint8_t RESERVED_94[12];
  __IO uint32_t INPUT_STORE_F_SHIFT_L_CH0;         /**< offset: 0x810 */
       uint8_t RESERVED_95[12];
  __IO uint32_t INPUT_STORE_F_SHIFT_H_CH0;         /**< offset: 0x820 */
       uint8_t RESERVED_96[12];
  __IO uint32_t INPUT_STORE_F_MASK_L_CH0;          /**< offset: 0x830 */
       uint8_t RESERVED_97[12];
  __IO uint32_t INPUT_STORE_F_MASK_H_CH0;          /**< offset: 0x840 */
       uint8_t RESERVED_98[12];
  __IO uint32_t DITHER_FETCH_CTRL_CH0;             /**< Pre-fetch engine Control Channel 0 Register, offset: 0x850 */
  __IO uint32_t DITHER_FETCH_CTRL_CH0_SET;         /**< Pre-fetch engine Control Channel 0 Register, offset: 0x854 */
  __IO uint32_t DITHER_FETCH_CTRL_CH0_CLR;         /**< Pre-fetch engine Control Channel 0 Register, offset: 0x858 */
  __IO uint32_t DITHER_FETCH_CTRL_CH0_TOG;         /**< Pre-fetch engine Control Channel 0 Register, offset: 0x85C */
  __IO uint32_t DITHER_FETCH_CTRL_CH1;             /**< Pre-fetch engine Control Channel 1 Register, offset: 0x860 */
  __IO uint32_t DITHER_FETCH_CTRL_CH1_SET;         /**< Pre-fetch engine Control Channel 1 Register, offset: 0x864 */
  __IO uint32_t DITHER_FETCH_CTRL_CH1_CLR;         /**< Pre-fetch engine Control Channel 1 Register, offset: 0x868 */
  __IO uint32_t DITHER_FETCH_CTRL_CH1_TOG;         /**< Pre-fetch engine Control Channel 1 Register, offset: 0x86C */
  __I  uint32_t DITHER_FETCH_STATUS_CH0;           /**< Pre-fetch engine status Channel 0 Register, offset: 0x870 */
       uint8_t RESERVED_99[12];
  __I  uint32_t DITHER_FETCH_STATUS_CH1;           /**< Store engine status Channel 1 Register, offset: 0x880 */
       uint8_t RESERVED_100[12];
  __IO uint32_t DITHER_FETCH_ACTIVE_SIZE_ULC_CH0;  /**< offset: 0x890 */
       uint8_t RESERVED_101[12];
  __IO uint32_t DITHER_FETCH_ACTIVE_SIZE_LRC_CH0;  /**< offset: 0x8A0 */
       uint8_t RESERVED_102[12];
  __IO uint32_t DITHER_FETCH_ACTIVE_SIZE_ULC_CH1;  /**< offset: 0x8B0 */
       uint8_t RESERVED_103[12];
  __IO uint32_t DITHER_FETCH_ACTIVE_SIZE_LRC_CH1;  /**< offset: 0x8C0 */
       uint8_t RESERVED_104[12];
  __IO uint32_t DITHER_FETCH_SIZE_CH0;             /**< offset: 0x8D0 */
       uint8_t RESERVED_105[12];
  __IO uint32_t DITHER_FETCH_SIZE_CH1;             /**< offset: 0x8E0 */
       uint8_t RESERVED_106[12];
  __IO uint32_t DITHER_FETCH_BACKGROUND_COLOR_CH0; /**< offset: 0x8F0 */
       uint8_t RESERVED_107[12];
  __IO uint32_t DITHER_FETCH_BACKGROUND_COLOR_CH1; /**< offset: 0x900 */
       uint8_t RESERVED_108[12];
  __IO uint32_t DITHER_FETCH_PITCH;                /**< offset: 0x910 */
       uint8_t RESERVED_109[12];
  __IO uint32_t DITHER_FETCH_SHIFT_CTRL_CH0;       /**< offset: 0x920 */
  __IO uint32_t DITHER_FETCH_SHIFT_CTRL_CH0_SET;   /**< offset: 0x924 */
  __IO uint32_t DITHER_FETCH_SHIFT_CTRL_CH0_CLR;   /**< offset: 0x928 */
  __IO uint32_t DITHER_FETCH_SHIFT_CTRL_CH0_TOG;   /**< offset: 0x92C */
  __IO uint32_t DITHER_FETCH_SHIFT_CTRL_CH1;       /**< offset: 0x930 */
  __IO uint32_t DITHER_FETCH_SHIFT_CTRL_CH1_SET;   /**< offset: 0x934 */
  __IO uint32_t DITHER_FETCH_SHIFT_CTRL_CH1_CLR;   /**< offset: 0x938 */
  __IO uint32_t DITHER_FETCH_SHIFT_CTRL_CH1_TOG;   /**< offset: 0x93C */
  __IO uint32_t DITHER_FETCH_SHIFT_OFFSET_CH0;     /**< offset: 0x940 */
  __IO uint32_t DITHER_FETCH_SHIFT_OFFSET_CH0_SET; /**< offset: 0x944 */
  __IO uint32_t DITHER_FETCH_SHIFT_OFFSET_CH0_CLR; /**< offset: 0x948 */
  __IO uint32_t DITHER_FETCH_SHIFT_OFFSET_CH0_TOG; /**< offset: 0x94C */
  __IO uint32_t DITHER_FETCH_SHIFT_OFFSET_CH1;     /**< offset: 0x950 */
  __IO uint32_t DITHER_FETCH_SHIFT_OFFSET_CH1_SET; /**< offset: 0x954 */
  __IO uint32_t DITHER_FETCH_SHIFT_OFFSET_CH1_CLR; /**< offset: 0x958 */
  __IO uint32_t DITHER_FETCH_SHIFT_OFFSET_CH1_TOG; /**< offset: 0x95C */
  __IO uint32_t DITHER_FETCH_SHIFT_WIDTH_CH0;      /**< offset: 0x960 */
  __IO uint32_t DITHER_FETCH_SHIFT_WIDTH_CH0_SET;  /**< offset: 0x964 */
  __IO uint32_t DITHER_FETCH_SHIFT_WIDTH_CH0_CLR;  /**< offset: 0x968 */
  __IO uint32_t DITHER_FETCH_SHIFT_WIDTH_CH0_TOG;  /**< offset: 0x96C */
  __IO uint32_t DITHER_FETCH_SHIFT_WIDTH_CH1;      /**< offset: 0x970 */
  __IO uint32_t DITHER_FETCH_SHIFT_WIDTH_CH1_SET;  /**< offset: 0x974 */
  __IO uint32_t DITHER_FETCH_SHIFT_WIDTH_CH1_CLR;  /**< offset: 0x978 */
  __IO uint32_t DITHER_FETCH_SHIFT_WIDTH_CH1_TOG;  /**< offset: 0x97C */
  __IO uint32_t DITHER_FETCH_ADDR_0_CH0;           /**< offset: 0x980 */
       uint8_t RESERVED_110[12];
  __IO uint32_t DITHER_FETCH_ADDR_1_CH0;           /**< offset: 0x990 */
       uint8_t RESERVED_111[12];
  __IO uint32_t DITHER_FETCH_ADDR_0_CH1;           /**< offset: 0x9A0 */
       uint8_t RESERVED_112[12];
  __IO uint32_t DITHER_FETCH_ADDR_1_CH1;           /**< offset: 0x9B0 */
       uint8_t RESERVED_113[12];
  __IO uint32_t DITHER_STORE_CTRL_CH0;             /**< Store engine Control Channel 0 Register, offset: 0x9C0 */
  __IO uint32_t DITHER_STORE_CTRL_CH0_SET;         /**< Store engine Control Channel 0 Register, offset: 0x9C4 */
  __IO uint32_t DITHER_STORE_CTRL_CH0_CLR;         /**< Store engine Control Channel 0 Register, offset: 0x9C8 */
  __IO uint32_t DITHER_STORE_CTRL_CH0_TOG;         /**< Store engine Control Channel 0 Register, offset: 0x9CC */
  __IO uint32_t DITHER_STORE_CTRL_CH1;             /**< Store engine Control Channel 1 Register, offset: 0x9D0 */
  __IO uint32_t DITHER_STORE_CTRL_CH1_SET;         /**< Store engine Control Channel 1 Register, offset: 0x9D4 */
  __IO uint32_t DITHER_STORE_CTRL_CH1_CLR;         /**< Store engine Control Channel 1 Register, offset: 0x9D8 */
  __IO uint32_t DITHER_STORE_CTRL_CH1_TOG;         /**< Store engine Control Channel 1 Register, offset: 0x9DC */
  __I  uint32_t DITHER_STORE_STATUS_CH0;           /**< Store engine status Channel 0 Register, offset: 0x9E0 */
       uint8_t RESERVED_114[12];
  __I  uint32_t DITHER_STORE_STATUS_CH1;           /**< Store engine status Channel 1 Register, offset: 0x9F0 */
       uint8_t RESERVED_115[12];
  __IO uint32_t DITHER_STORE_SIZE_CH0;             /**< offset: 0xA00 */
       uint8_t RESERVED_116[12];
  __IO uint32_t DITHER_STORE_SIZE_CH1;             /**< offset: 0xA10 */
       uint8_t RESERVED_117[12];
  __IO uint32_t DITHER_STORE_PITCH;                /**< offset: 0xA20 */
       uint8_t RESERVED_118[12];
  __IO uint32_t DITHER_STORE_SHIFT_CTRL_CH0;       /**< offset: 0xA30 */
  __IO uint32_t DITHER_STORE_SHIFT_CTRL_CH0_SET;   /**< offset: 0xA34 */
  __IO uint32_t DITHER_STORE_SHIFT_CTRL_CH0_CLR;   /**< offset: 0xA38 */
  __IO uint32_t DITHER_STORE_SHIFT_CTRL_CH0_TOG;   /**< offset: 0xA3C */
  __IO uint32_t DITHER_STORE_SHIFT_CTRL_CH1;       /**< offset: 0xA40 */
  __IO uint32_t DITHER_STORE_SHIFT_CTRL_CH1_SET;   /**< offset: 0xA44 */
  __IO uint32_t DITHER_STORE_SHIFT_CTRL_CH1_CLR;   /**< offset: 0xA48 */
  __IO uint32_t DITHER_STORE_SHIFT_CTRL_CH1_TOG;   /**< offset: 0xA4C */
       uint8_t RESERVED_119[64];
  __IO uint32_t DITHER_STORE_ADDR_0_CH0;           /**< offset: 0xA90 */
       uint8_t RESERVED_120[12];
  __IO uint32_t DITHER_STORE_ADDR_1_CH0;           /**< offset: 0xAA0 */
       uint8_t RESERVED_121[12];
  __IO uint32_t DITHER_STORE_FILL_DATA_CH0;        /**< offset: 0xAB0 */
       uint8_t RESERVED_122[12];
  __IO uint32_t DITHER_STORE_ADDR_0_CH1;           /**< offset: 0xAC0 */
       uint8_t RESERVED_123[12];
  __IO uint32_t DITHER_STORE_ADDR_1_CH1;           /**< offset: 0xAD0 */
       uint8_t RESERVED_124[12];
  __IO uint32_t DITHER_STORE_D_MASK0_H_CH0;        /**< offset: 0xAE0 */
       uint8_t RESERVED_125[12];
  __IO uint32_t DITHER_STORE_D_MASK0_L_CH0;        /**< offset: 0xAF0 */
       uint8_t RESERVED_126[12];
  __IO uint32_t DITHER_STORE_D_MASK1_H_CH0;        /**< offset: 0xB00 */
       uint8_t RESERVED_127[12];
  __IO uint32_t DITHER_STORE_D_MASK1_L_CH0;        /**< offset: 0xB10 */
       uint8_t RESERVED_128[12];
  __IO uint32_t DITHER_STORE_D_MASK2_H_CH0;        /**< offset: 0xB20 */
       uint8_t RESERVED_129[12];
  __IO uint32_t DITHER_STORE_D_MASK2_L_CH0;        /**< offset: 0xB30 */
       uint8_t RESERVED_130[12];
  __IO uint32_t DITHER_STORE_D_MASK3_H_CH0;        /**< offset: 0xB40 */
       uint8_t RESERVED_131[12];
  __IO uint32_t DITHER_STORE_D_MASK3_L_CH0;        /**< offset: 0xB50 */
       uint8_t RESERVED_132[12];
  __IO uint32_t DITHER_STORE_D_MASK4_H_CH0;        /**< offset: 0xB60 */
       uint8_t RESERVED_133[12];
  __IO uint32_t DITHER_STORE_D_MASK4_L_CH0;        /**< offset: 0xB70 */
       uint8_t RESERVED_134[12];
  __IO uint32_t DITHER_STORE_D_MASK5_H_CH0;        /**< offset: 0xB80 */
       uint8_t RESERVED_135[12];
  __IO uint32_t DITHER_STORE_D_MASK5_L_CH0;        /**< offset: 0xB90 */
       uint8_t RESERVED_136[12];
  __IO uint32_t DITHER_STORE_D_MASK6_H_CH0;        /**< offset: 0xBA0 */
       uint8_t RESERVED_137[12];
  __IO uint32_t DITHER_STORE_D_MASK6_L_CH0;        /**< offset: 0xBB0 */
       uint8_t RESERVED_138[12];
  __IO uint32_t DITHER_STORE_D_MASK7_H_CH0;        /**< offset: 0xBC0 */
       uint8_t RESERVED_139[12];
  __IO uint32_t DITHER_STORE_D_MASK7_L_CH0;        /**< offset: 0xBD0 */
       uint8_t RESERVED_140[12];
  __IO uint32_t DITHER_STORE_D_SHIFT_L_CH0;        /**< offset: 0xBE0 */
       uint8_t RESERVED_141[12];
  __IO uint32_t DITHER_STORE_D_SHIFT_H_CH0;        /**< offset: 0xBF0 */
       uint8_t RESERVED_142[12];
  __IO uint32_t DITHER_STORE_F_SHIFT_L_CH0;        /**< offset: 0xC00 */
       uint8_t RESERVED_143[12];
  __IO uint32_t DITHER_STORE_F_SHIFT_H_CH0;        /**< offset: 0xC10 */
       uint8_t RESERVED_144[12];
  __IO uint32_t DITHER_STORE_F_MASK_L_CH0;         /**< offset: 0xC20 */
       uint8_t RESERVED_145[12];
  __IO uint32_t DITHER_STORE_F_MASK_H_CH0;         /**< offset: 0xC30 */
       uint8_t RESERVED_146[12];
  __IO uint32_t WFA_FETCH_CTRL;                    /**< Fetch engine Control for WFE A Register, offset: 0xC40 */
  __IO uint32_t WFA_FETCH_CTRL_SET;                /**< Fetch engine Control for WFE A Register, offset: 0xC44 */
  __IO uint32_t WFA_FETCH_CTRL_CLR;                /**< Fetch engine Control for WFE A Register, offset: 0xC48 */
  __IO uint32_t WFA_FETCH_CTRL_TOG;                /**< Fetch engine Control for WFE A Register, offset: 0xC4C */
  __IO uint32_t WFA_FETCH_BUF1_ADDR;               /**< offset: 0xC50 */
       uint8_t RESERVED_147[12];
  __IO uint32_t WFA_FETCH_BUF1_PITCH;              /**< offset: 0xC60 */
       uint8_t RESERVED_148[12];
  __IO uint32_t WFA_FETCH_BUF1_SIZE;               /**< offset: 0xC70 */
       uint8_t RESERVED_149[12];
  __IO uint32_t WFA_FETCH_BUF2_ADDR;               /**< offset: 0xC80 */
       uint8_t RESERVED_150[12];
  __IO uint32_t WFA_FETCH_BUF2_PITCH;              /**< offset: 0xC90 */
       uint8_t RESERVED_151[12];
  __IO uint32_t WFA_FETCH_BUF2_SIZE;               /**< offset: 0xCA0 */
       uint8_t RESERVED_152[12];
  __IO uint32_t WFA_ARRAY_PIXEL0_MASK;             /**< offset: 0xCB0 */
       uint8_t RESERVED_153[12];
  __IO uint32_t WFA_ARRAY_PIXEL1_MASK;             /**< offset: 0xCC0 */
       uint8_t RESERVED_154[12];
  __IO uint32_t WFA_ARRAY_PIXEL2_MASK;             /**< offset: 0xCD0 */
       uint8_t RESERVED_155[12];
  __IO uint32_t WFA_ARRAY_PIXEL3_MASK;             /**< offset: 0xCE0 */
       uint8_t RESERVED_156[12];
  __IO uint32_t WFA_ARRAY_PIXEL4_MASK;             /**< offset: 0xCF0 */
       uint8_t RESERVED_157[12];
  __IO uint32_t WFA_ARRAY_PIXEL5_MASK;             /**< offset: 0xD00 */
       uint8_t RESERVED_158[12];
  __IO uint32_t WFA_ARRAY_PIXEL6_MASK;             /**< offset: 0xD10 */
       uint8_t RESERVED_159[12];
  __IO uint32_t WFA_ARRAY_PIXEL7_MASK;             /**< offset: 0xD20 */
       uint8_t RESERVED_160[12];
  __IO uint32_t WFA_ARRAY_FLAG0_MASK;              /**< offset: 0xD30 */
       uint8_t RESERVED_161[12];
  __IO uint32_t WFA_ARRAY_FLAG1_MASK;              /**< offset: 0xD40 */
       uint8_t RESERVED_162[12];
  __IO uint32_t WFA_ARRAY_FLAG2_MASK;              /**< offset: 0xD50 */
       uint8_t RESERVED_163[12];
  __IO uint32_t WFA_ARRAY_FLAG3_MASK;              /**< offset: 0xD60 */
       uint8_t RESERVED_164[12];
  __IO uint32_t WFA_ARRAY_FLAG4_MASK;              /**< offset: 0xD70 */
       uint8_t RESERVED_165[12];
  __IO uint32_t WFA_ARRAY_FLAG5_MASK;              /**< offset: 0xD80 */
       uint8_t RESERVED_166[12];
  __IO uint32_t WFA_ARRAY_FLAG6_MASK;              /**< offset: 0xD90 */
       uint8_t RESERVED_167[12];
  __IO uint32_t WFA_ARRAY_FLAG7_MASK;              /**< offset: 0xDA0 */
       uint8_t RESERVED_168[12];
  __IO uint32_t WFA_FETCH_BUF1_CORD;               /**< offset: 0xDB0 */
       uint8_t RESERVED_169[12];
  __IO uint32_t WFA_FETCH_BUF2_CORD;               /**< offset: 0xDC0 */
       uint8_t RESERVED_170[12];
  __IO uint32_t WFA_ARRAY_FLAG8_MASK;              /**< offset: 0xDD0 */
       uint8_t RESERVED_171[12];
  __IO uint32_t WFA_ARRAY_FLAG9_MASK;              /**< offset: 0xDE0 */
       uint8_t RESERVED_172[12];
  __IO uint32_t WFA_ARRAY_FLAG10_MASK;             /**< offset: 0xDF0 */
       uint8_t RESERVED_173[12];
  __IO uint32_t WFA_ARRAY_FLAG11_MASK;             /**< offset: 0xE00 */
       uint8_t RESERVED_174[12];
  __IO uint32_t WFA_ARRAY_FLAG12_MASK;             /**< offset: 0xE10 */
       uint8_t RESERVED_175[12];
  __IO uint32_t WFA_ARRAY_FLAG13_MASK;             /**< offset: 0xE20 */
       uint8_t RESERVED_176[12];
  __IO uint32_t WFA_ARRAY_FLAG14_MASK;             /**< offset: 0xE30 */
       uint8_t RESERVED_177[12];
  __IO uint32_t WFA_ARRAY_FLAG15_MASK;             /**< offset: 0xE40 */
       uint8_t RESERVED_178[12];
  __IO uint32_t WFA_ARRAY_REG0;                    /**< offset: 0xE50 */
       uint8_t RESERVED_179[12];
  __IO uint32_t WFA_ARRAY_REG1;                    /**< offset: 0xE60 */
       uint8_t RESERVED_180[12];
  __IO uint32_t WFA_ARRAY_REG2;                    /**< offset: 0xE70 */
       uint8_t RESERVED_181[12];
  __IO uint32_t WFE_A_STORE_CTRL_CH0;              /**< Pre-fetch engine Control Channel 0 Register, offset: 0xE80 */
  __IO uint32_t WFE_A_STORE_CTRL_CH0_SET;          /**< Pre-fetch engine Control Channel 0 Register, offset: 0xE84 */
  __IO uint32_t WFE_A_STORE_CTRL_CH0_CLR;          /**< Pre-fetch engine Control Channel 0 Register, offset: 0xE88 */
  __IO uint32_t WFE_A_STORE_CTRL_CH0_TOG;          /**< Pre-fetch engine Control Channel 0 Register, offset: 0xE8C */
  __IO uint32_t WFE_A_STORE_CTRL_CH1;              /**< Pre-fetch engine Control Channel 1 Register, offset: 0xE90 */
  __IO uint32_t WFE_A_STORE_CTRL_CH1_SET;          /**< Pre-fetch engine Control Channel 1 Register, offset: 0xE94 */
  __IO uint32_t WFE_A_STORE_CTRL_CH1_CLR;          /**< Pre-fetch engine Control Channel 1 Register, offset: 0xE98 */
  __IO uint32_t WFE_A_STORE_CTRL_CH1_TOG;          /**< Pre-fetch engine Control Channel 1 Register, offset: 0xE9C */
  __I  uint32_t WFE_A_STORE_STATUS_CH0;            /**< Store engine status Channel 0 Register, offset: 0xEA0 */
       uint8_t RESERVED_182[12];
  __I  uint32_t WFE_A_STORE_STATUS_CH1;            /**< Store engine status Channel 1 Register, offset: 0xEB0 */
       uint8_t RESERVED_183[12];
  __IO uint32_t WFE_A_STORE_SIZE_CH0;              /**< offset: 0xEC0 */
       uint8_t RESERVED_184[12];
  __IO uint32_t WFE_A_STORE_SIZE_CH1;              /**< offset: 0xED0 */
       uint8_t RESERVED_185[12];
  __IO uint32_t WFE_A_STORE_PITCH;                 /**< offset: 0xEE0 */
       uint8_t RESERVED_186[12];
  __IO uint32_t WFE_A_STORE_SHIFT_CTRL_CH0;        /**< offset: 0xEF0 */
  __IO uint32_t WFE_A_STORE_SHIFT_CTRL_CH0_SET;    /**< offset: 0xEF4 */
  __IO uint32_t WFE_A_STORE_SHIFT_CTRL_CH0_CLR;    /**< offset: 0xEF8 */
  __IO uint32_t WFE_A_STORE_SHIFT_CTRL_CH0_TOG;    /**< offset: 0xEFC */
  __IO uint32_t WFE_A_STORE_SHIFT_CTRL_CH1;        /**< offset: 0xF00 */
  __IO uint32_t WFE_A_STORE_SHIFT_CTRL_CH1_SET;    /**< offset: 0xF04 */
  __IO uint32_t WFE_A_STORE_SHIFT_CTRL_CH1_CLR;    /**< offset: 0xF08 */
  __IO uint32_t WFE_A_STORE_SHIFT_CTRL_CH1_TOG;    /**< offset: 0xF0C */
       uint8_t RESERVED_187[64];
  __IO uint32_t WFE_A_STORE_ADDR_0_CH0;            /**< offset: 0xF50 */
       uint8_t RESERVED_188[12];
  __IO uint32_t WFE_A_STORE_ADDR_1_CH0;            /**< offset: 0xF60 */
       uint8_t RESERVED_189[12];
  __IO uint32_t WFE_A_STORE_FILL_DATA_CH0;         /**< offset: 0xF70 */
       uint8_t RESERVED_190[12];
  __IO uint32_t WFE_A_STORE_ADDR_0_CH1;            /**< offset: 0xF80 */
       uint8_t RESERVED_191[12];
  __IO uint32_t WFE_A_STORE_ADDR_1_CH1;            /**< offset: 0xF90 */
       uint8_t RESERVED_192[12];
  __IO uint32_t WFE_A_STORE_D_MASK0_H_CH0;         /**< offset: 0xFA0 */
       uint8_t RESERVED_193[12];
  __IO uint32_t WFE_A_STORE_D_MASK0_L_CH0;         /**< offset: 0xFB0 */
       uint8_t RESERVED_194[12];
  __IO uint32_t WFE_A_STORE_D_MASK1_H_CH0;         /**< offset: 0xFC0 */
       uint8_t RESERVED_195[12];
  __IO uint32_t WFE_A_STORE_D_MASK1_L_CH0;         /**< offset: 0xFD0 */
       uint8_t RESERVED_196[12];
  __IO uint32_t WFE_A_STORE_D_MASK2_H_CH0;         /**< offset: 0xFE0 */
       uint8_t RESERVED_197[12];
  __IO uint32_t WFE_A_STORE_D_MASK2_L_CH0;         /**< offset: 0xFF0 */
       uint8_t RESERVED_198[12];
  __IO uint32_t WFE_A_STORE_D_MASK3_H_CH0;         /**< offset: 0x1000 */
       uint8_t RESERVED_199[12];
  __IO uint32_t WFE_A_STORE_D_MASK3_L_CH0;         /**< offset: 0x1010 */
       uint8_t RESERVED_200[12];
  __IO uint32_t WFE_A_STORE_D_MASK4_H_CH0;         /**< offset: 0x1020 */
       uint8_t RESERVED_201[12];
  __IO uint32_t WFE_A_STORE_D_MASK4_L_CH0;         /**< offset: 0x1030 */
       uint8_t RESERVED_202[12];
  __IO uint32_t WFE_A_STORE_D_MASK5_H_CH0;         /**< offset: 0x1040 */
       uint8_t RESERVED_203[12];
  __IO uint32_t WFE_A_STORE_D_MASK5_L_CH0;         /**< offset: 0x1050 */
       uint8_t RESERVED_204[12];
  __IO uint32_t WFE_A_STORE_D_MASK6_H_CH0;         /**< offset: 0x1060 */
       uint8_t RESERVED_205[12];
  __IO uint32_t WFE_A_STORE_D_MASK6_L_CH0;         /**< offset: 0x1070 */
       uint8_t RESERVED_206[12];
  __IO uint32_t WFE_A_STORE_D_MASK7_H_CH0;         /**< offset: 0x1080 */
       uint8_t RESERVED_207[12];
  __IO uint32_t WFE_A_STORE_D_MASK7_L_CH0;         /**< offset: 0x1090 */
       uint8_t RESERVED_208[12];
  __IO uint32_t WFE_A_STORE_D_SHIFT_L_CH0;         /**< offset: 0x10A0 */
       uint8_t RESERVED_209[12];
  __IO uint32_t WFE_A_STORE_D_SHIFT_H_CH0;         /**< offset: 0x10B0 */
       uint8_t RESERVED_210[12];
  __IO uint32_t WFE_A_STORE_F_SHIFT_L_CH0;         /**< offset: 0x10C0 */
       uint8_t RESERVED_211[12];
  __IO uint32_t WFE_A_STORE_F_SHIFT_H_CH0;         /**< offset: 0x10D0 */
       uint8_t RESERVED_212[12];
  __IO uint32_t WFE_A_STORE_F_MASK_L_CH0;          /**< offset: 0x10E0 */
       uint8_t RESERVED_213[12];
  __IO uint32_t WFE_A_STORE_F_MASK_H_CH0;          /**< offset: 0x10F0 */
       uint8_t RESERVED_214[588];
  __IO uint32_t WFE_B_STORE_CTRL_CH0;              /**< Store engine Control Channel 0 Register, offset: 0x1340 */
  __IO uint32_t WFE_B_STORE_CTRL_CH0_SET;          /**< Store engine Control Channel 0 Register, offset: 0x1344 */
  __IO uint32_t WFE_B_STORE_CTRL_CH0_CLR;          /**< Store engine Control Channel 0 Register, offset: 0x1348 */
  __IO uint32_t WFE_B_STORE_CTRL_CH0_TOG;          /**< Store engine Control Channel 0 Register, offset: 0x134C */
  __IO uint32_t WFE_B_STORE_CTRL_CH1;              /**< Store engine Control Channel 1 Register, offset: 0x1350 */
  __IO uint32_t WFE_B_STORE_CTRL_CH1_SET;          /**< Store engine Control Channel 1 Register, offset: 0x1354 */
  __IO uint32_t WFE_B_STORE_CTRL_CH1_CLR;          /**< Store engine Control Channel 1 Register, offset: 0x1358 */
  __IO uint32_t WFE_B_STORE_CTRL_CH1_TOG;          /**< Store engine Control Channel 1 Register, offset: 0x135C */
  __I  uint32_t WFE_B_STORE_STATUS_CH0;            /**< Store engine status Channel 0 Register, offset: 0x1360 */
       uint8_t RESERVED_215[12];
  __I  uint32_t WFE_B_STORE_STATUS_CH1;            /**< Store engine status Channel 1 Register, offset: 0x1370 */
       uint8_t RESERVED_216[12];
  __IO uint32_t WFE_B_STORE_SIZE_CH0;              /**< offset: 0x1380 */
       uint8_t RESERVED_217[12];
  __IO uint32_t WFE_B_STORE_SIZE_CH1;              /**< offset: 0x1390 */
       uint8_t RESERVED_218[12];
  __IO uint32_t WFE_B_STORE_PITCH;                 /**< offset: 0x13A0 */
       uint8_t RESERVED_219[12];
  __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0;        /**< offset: 0x13B0 */
  __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_SET;    /**< offset: 0x13B4 */
  __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_CLR;    /**< offset: 0x13B8 */
  __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_TOG;    /**< offset: 0x13BC */
  __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1;        /**< offset: 0x13C0 */
  __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_SET;    /**< offset: 0x13C4 */
  __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_CLR;    /**< offset: 0x13C8 */
  __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_TOG;    /**< offset: 0x13CC */
       uint8_t RESERVED_220[64];
  __IO uint32_t WFE_B_STORE_ADDR_0_CH0;            /**< offset: 0x1410 */
       uint8_t RESERVED_221[12];
  __IO uint32_t WFE_B_STORE_ADDR_1_CH0;            /**< offset: 0x1420 */
       uint8_t RESERVED_222[12];
  __IO uint32_t WFE_B_STORE_FILL_DATA_CH0;         /**< offset: 0x1430 */
       uint8_t RESERVED_223[12];
  __IO uint32_t WFE_B_STORE_ADDR_0_CH1;            /**< offset: 0x1440 */
       uint8_t RESERVED_224[12];
  __IO uint32_t WFE_B_STORE_ADDR_1_CH1;            /**< offset: 0x1450 */
       uint8_t RESERVED_225[12];
  __IO uint32_t WFE_B_STORE_D_MASK0_H_CH0;         /**< offset: 0x1460 */
       uint8_t RESERVED_226[12];
  __IO uint32_t WFE_B_STORE_D_MASK0_L_CH0;         /**< offset: 0x1470 */
       uint8_t RESERVED_227[12];
  __IO uint32_t WFE_B_STORE_D_MASK1_H_CH0;         /**< offset: 0x1480 */
       uint8_t RESERVED_228[12];
  __IO uint32_t WFE_B_STORE_D_MASK1_L_CH0;         /**< offset: 0x1490 */
       uint8_t RESERVED_229[12];
  __IO uint32_t WFE_B_STORE_D_MASK2_H_CH0;         /**< offset: 0x14A0 */
       uint8_t RESERVED_230[12];
  __IO uint32_t WFE_B_STORE_D_MASK2_L_CH0;         /**< offset: 0x14B0 */
       uint8_t RESERVED_231[12];
  __IO uint32_t WFE_B_STORE_D_MASK3_H_CH0;         /**< offset: 0x14C0 */
       uint8_t RESERVED_232[12];
  __IO uint32_t WFE_B_STORE_D_MASK3_L_CH0;         /**< offset: 0x14D0 */
       uint8_t RESERVED_233[12];
  __IO uint32_t WFE_B_STORE_D_MASK4_H_CH0;         /**< offset: 0x14E0 */
       uint8_t RESERVED_234[12];
  __IO uint32_t WFE_B_STORE_D_MASK4_L_CH0;         /**< offset: 0x14F0 */
       uint8_t RESERVED_235[12];
  __IO uint32_t WFE_B_STORE_D_MASK5_H_CH0;         /**< offset: 0x1500 */
       uint8_t RESERVED_236[12];
  __IO uint32_t WFE_B_STORE_D_MASK5_L_CH0;         /**< offset: 0x1510 */
       uint8_t RESERVED_237[12];
  __IO uint32_t WFE_B_STORE_D_MASK6_H_CH0;         /**< offset: 0x1520 */
       uint8_t RESERVED_238[12];
  __IO uint32_t WFE_B_STORE_D_MASK6_L_CH0;         /**< offset: 0x1530 */
       uint8_t RESERVED_239[12];
  __IO uint32_t WFE_B_STORE_D_MASK7_H_CH0;         /**< offset: 0x1540 */
       uint8_t RESERVED_240[12];
  __IO uint32_t WFE_B_STORE_D_MASK7_L_CH0;         /**< offset: 0x1550 */
       uint8_t RESERVED_241[12];
  __IO uint32_t WFE_B_STORE_D_SHIFT_L_CH0;         /**< offset: 0x1560 */
       uint8_t RESERVED_242[12];
  __IO uint32_t WFE_B_STORE_D_SHIFT_H_CH0;         /**< offset: 0x1570 */
       uint8_t RESERVED_243[12];
  __IO uint32_t WFE_B_STORE_F_SHIFT_L_CH0;         /**< offset: 0x1580 */
       uint8_t RESERVED_244[12];
  __IO uint32_t WFE_B_STORE_F_SHIFT_H_CH0;         /**< offset: 0x1590 */
       uint8_t RESERVED_245[12];
  __IO uint32_t WFE_B_STORE_F_MASK_L_CH0;          /**< offset: 0x15A0 */
       uint8_t RESERVED_246[12];
  __IO uint32_t WFE_B_STORE_F_MASK_H_CH0;          /**< offset: 0x15B0 */
       uint8_t RESERVED_247[12];
  __IO uint32_t FETCH_WFE_A_DEBUG;                 /**< offset: 0x15C0 */
       uint8_t RESERVED_248[12];
  __IO uint32_t FETCH_WFE_B_DEBUG;                 /**< offset: 0x15D0 */
       uint8_t RESERVED_249[156];
  __IO uint32_t DITHER_CTRL;                       /**< Dither Control Register 0, offset: 0x1670 */
  __IO uint32_t DITHER_CTRL_SET;                   /**< Dither Control Register 0, offset: 0x1674 */
  __IO uint32_t DITHER_CTRL_CLR;                   /**< Dither Control Register 0, offset: 0x1678 */
  __IO uint32_t DITHER_CTRL_TOG;                   /**< Dither Control Register 0, offset: 0x167C */
  __IO uint32_t DITHER_FINAL_LUT_DATA0;            /**< Final stage lookup value Register, offset: 0x1680 */
  __IO uint32_t DITHER_FINAL_LUT_DATA0_SET;        /**< Final stage lookup value Register, offset: 0x1684 */
  __IO uint32_t DITHER_FINAL_LUT_DATA0_CLR;        /**< Final stage lookup value Register, offset: 0x1688 */
  __IO uint32_t DITHER_FINAL_LUT_DATA0_TOG;        /**< Final stage lookup value Register, offset: 0x168C */
  __IO uint32_t DITHER_FINAL_LUT_DATA1;            /**< Final stage lookup value Register, offset: 0x1690 */
  __IO uint32_t DITHER_FINAL_LUT_DATA1_SET;        /**< Final stage lookup value Register, offset: 0x1694 */
  __IO uint32_t DITHER_FINAL_LUT_DATA1_CLR;        /**< Final stage lookup value Register, offset: 0x1698 */
  __IO uint32_t DITHER_FINAL_LUT_DATA1_TOG;        /**< Final stage lookup value Register, offset: 0x169C */
  __IO uint32_t DITHER_FINAL_LUT_DATA2;            /**< Final stage lookup value Register, offset: 0x16A0 */
  __IO uint32_t DITHER_FINAL_LUT_DATA2_SET;        /**< Final stage lookup value Register, offset: 0x16A4 */
  __IO uint32_t DITHER_FINAL_LUT_DATA2_CLR;        /**< Final stage lookup value Register, offset: 0x16A8 */
  __IO uint32_t DITHER_FINAL_LUT_DATA2_TOG;        /**< Final stage lookup value Register, offset: 0x16AC */
  __IO uint32_t DITHER_FINAL_LUT_DATA3;            /**< Final stage lookup value Register, offset: 0x16B0 */
  __IO uint32_t DITHER_FINAL_LUT_DATA3_SET;        /**< Final stage lookup value Register, offset: 0x16B4 */
  __IO uint32_t DITHER_FINAL_LUT_DATA3_CLR;        /**< Final stage lookup value Register, offset: 0x16B8 */
  __IO uint32_t DITHER_FINAL_LUT_DATA3_TOG;        /**< Final stage lookup value Register, offset: 0x16BC */
  __IO uint32_t WFE_A_CTRL;                        /**< offset: 0x16C0 */
  __IO uint32_t WFE_A_CTRL_SET;                    /**< offset: 0x16C4 */
  __IO uint32_t WFE_A_CTRL_CLR;                    /**< offset: 0x16C8 */
  __IO uint32_t WFE_A_CTRL_TOG;                    /**< offset: 0x16CC */
  __IO uint32_t WFE_A_DIMENSIONS;                  /**< offset: 0x16D0 */
       uint8_t RESERVED_250[12];
  __IO uint32_t WFE_A_OFFSET;                      /**< offset: 0x16E0 */
       uint8_t RESERVED_251[12];
  __IO uint32_t WFE_A_SW_DATA_REGS;                /**< offset: 0x16F0 */
       uint8_t RESERVED_252[12];
  __IO uint32_t WFE_A_SW_FLAG_REGS;                /**< offset: 0x1700 */
       uint8_t RESERVED_253[12];
  __IO uint32_t WFE_A_STAGE1_MUX0;                 /**< offset: 0x1710 */
  __IO uint32_t WFE_A_STAGE1_MUX0_SET;             /**< offset: 0x1714 */
  __IO uint32_t WFE_A_STAGE1_MUX0_CLR;             /**< offset: 0x1718 */
  __IO uint32_t WFE_A_STAGE1_MUX0_TOG;             /**< offset: 0x171C */
  __IO uint32_t WFE_A_STAGE1_MUX1;                 /**< offset: 0x1720 */
  __IO uint32_t WFE_A_STAGE1_MUX1_SET;             /**< offset: 0x1724 */
  __IO uint32_t WFE_A_STAGE1_MUX1_CLR;             /**< offset: 0x1728 */
  __IO uint32_t WFE_A_STAGE1_MUX1_TOG;             /**< offset: 0x172C */
  __IO uint32_t WFE_A_STAGE1_MUX2;                 /**< offset: 0x1730 */
  __IO uint32_t WFE_A_STAGE1_MUX2_SET;             /**< offset: 0x1734 */
  __IO uint32_t WFE_A_STAGE1_MUX2_CLR;             /**< offset: 0x1738 */
  __IO uint32_t WFE_A_STAGE1_MUX2_TOG;             /**< offset: 0x173C */
  __IO uint32_t WFE_A_STAGE1_MUX3;                 /**< offset: 0x1740 */
  __IO uint32_t WFE_A_STAGE1_MUX3_SET;             /**< offset: 0x1744 */
  __IO uint32_t WFE_A_STAGE1_MUX3_CLR;             /**< offset: 0x1748 */
  __IO uint32_t WFE_A_STAGE1_MUX3_TOG;             /**< offset: 0x174C */
  __IO uint32_t WFE_A_STAGE1_MUX4;                 /**< offset: 0x1750 */
  __IO uint32_t WFE_A_STAGE1_MUX4_SET;             /**< offset: 0x1754 */
  __IO uint32_t WFE_A_STAGE1_MUX4_CLR;             /**< offset: 0x1758 */
  __IO uint32_t WFE_A_STAGE1_MUX4_TOG;             /**< offset: 0x175C */
  __IO uint32_t WFE_A_STAGE2_MUX0;                 /**< offset: 0x1760 */
  __IO uint32_t WFE_A_STAGE2_MUX0_SET;             /**< offset: 0x1764 */
  __IO uint32_t WFE_A_STAGE2_MUX0_CLR;             /**< offset: 0x1768 */
  __IO uint32_t WFE_A_STAGE2_MUX0_TOG;             /**< offset: 0x176C */
  __IO uint32_t WFE_A_STAGE2_MUX1;                 /**< offset: 0x1770 */
  __IO uint32_t WFE_A_STAGE2_MUX1_SET;             /**< offset: 0x1774 */
  __IO uint32_t WFE_A_STAGE2_MUX1_CLR;             /**< offset: 0x1778 */
  __IO uint32_t WFE_A_STAGE2_MUX1_TOG;             /**< offset: 0x177C */
  __IO uint32_t WFE_A_STAGE2_MUX2;                 /**< offset: 0x1780 */
  __IO uint32_t WFE_A_STAGE2_MUX2_SET;             /**< offset: 0x1784 */
  __IO uint32_t WFE_A_STAGE2_MUX2_CLR;             /**< offset: 0x1788 */
  __IO uint32_t WFE_A_STAGE2_MUX2_TOG;             /**< offset: 0x178C */
  __IO uint32_t WFE_A_STAGE2_MUX3;                 /**< offset: 0x1790 */
  __IO uint32_t WFE_A_STAGE2_MUX3_SET;             /**< offset: 0x1794 */
  __IO uint32_t WFE_A_STAGE2_MUX3_CLR;             /**< offset: 0x1798 */
  __IO uint32_t WFE_A_STAGE2_MUX3_TOG;             /**< offset: 0x179C */
  __IO uint32_t WFE_A_STAGE2_MUX4;                 /**< offset: 0x17A0 */
  __IO uint32_t WFE_A_STAGE2_MUX4_SET;             /**< offset: 0x17A4 */
  __IO uint32_t WFE_A_STAGE2_MUX4_CLR;             /**< offset: 0x17A8 */
  __IO uint32_t WFE_A_STAGE2_MUX4_TOG;             /**< offset: 0x17AC */
  __IO uint32_t WFE_A_STAGE2_MUX5;                 /**< offset: 0x17B0 */
  __IO uint32_t WFE_A_STAGE2_MUX5_SET;             /**< offset: 0x17B4 */
  __IO uint32_t WFE_A_STAGE2_MUX5_CLR;             /**< offset: 0x17B8 */
  __IO uint32_t WFE_A_STAGE2_MUX5_TOG;             /**< offset: 0x17BC */
  __IO uint32_t WFE_A_STAGE2_MUX6;                 /**< offset: 0x17C0 */
  __IO uint32_t WFE_A_STAGE2_MUX6_SET;             /**< offset: 0x17C4 */
  __IO uint32_t WFE_A_STAGE2_MUX6_CLR;             /**< offset: 0x17C8 */
  __IO uint32_t WFE_A_STAGE2_MUX6_TOG;             /**< offset: 0x17CC */
  __IO uint32_t WFE_A_STAGE2_MUX7;                 /**< offset: 0x17D0 */
  __IO uint32_t WFE_A_STAGE2_MUX7_SET;             /**< offset: 0x17D4 */
  __IO uint32_t WFE_A_STAGE2_MUX7_CLR;             /**< offset: 0x17D8 */
  __IO uint32_t WFE_A_STAGE2_MUX7_TOG;             /**< offset: 0x17DC */
  __IO uint32_t WFE_A_STAGE2_MUX8;                 /**< offset: 0x17E0 */
  __IO uint32_t WFE_A_STAGE2_MUX8_SET;             /**< offset: 0x17E4 */
  __IO uint32_t WFE_A_STAGE2_MUX8_CLR;             /**< offset: 0x17E8 */
  __IO uint32_t WFE_A_STAGE2_MUX8_TOG;             /**< offset: 0x17EC */
  __IO uint32_t WFE_A_STAGE2_MUX9;                 /**< offset: 0x17F0 */
  __IO uint32_t WFE_A_STAGE2_MUX9_SET;             /**< offset: 0x17F4 */
  __IO uint32_t WFE_A_STAGE2_MUX9_CLR;             /**< offset: 0x17F8 */
  __IO uint32_t WFE_A_STAGE2_MUX9_TOG;             /**< offset: 0x17FC */
  __IO uint32_t WFE_A_STAGE2_MUX10;                /**< offset: 0x1800 */
  __IO uint32_t WFE_A_STAGE2_MUX10_SET;            /**< offset: 0x1804 */
  __IO uint32_t WFE_A_STAGE2_MUX10_CLR;            /**< offset: 0x1808 */
  __IO uint32_t WFE_A_STAGE2_MUX10_TOG;            /**< offset: 0x180C */
  __IO uint32_t WFE_A_STAGE2_MUX11;                /**< offset: 0x1810 */
  __IO uint32_t WFE_A_STAGE2_MUX11_SET;            /**< offset: 0x1814 */
  __IO uint32_t WFE_A_STAGE2_MUX11_CLR;            /**< offset: 0x1818 */
  __IO uint32_t WFE_A_STAGE2_MUX11_TOG;            /**< offset: 0x181C */
  __IO uint32_t WFE_A_STAGE2_MUX12;                /**< offset: 0x1820 */
  __IO uint32_t WFE_A_STAGE2_MUX12_SET;            /**< offset: 0x1824 */
  __IO uint32_t WFE_A_STAGE2_MUX12_CLR;            /**< offset: 0x1828 */
  __IO uint32_t WFE_A_STAGE2_MUX12_TOG;            /**< offset: 0x182C */
  __IO uint32_t WFE_A_STAGE3_MUX0;                 /**< offset: 0x1830 */
  __IO uint32_t WFE_A_STAGE3_MUX0_SET;             /**< offset: 0x1834 */
  __IO uint32_t WFE_A_STAGE3_MUX0_CLR;             /**< offset: 0x1838 */
  __IO uint32_t WFE_A_STAGE3_MUX0_TOG;             /**< offset: 0x183C */
  __IO uint32_t WFE_A_STAGE3_MUX1;                 /**< offset: 0x1840 */
  __IO uint32_t WFE_A_STAGE3_MUX1_SET;             /**< offset: 0x1844 */
  __IO uint32_t WFE_A_STAGE3_MUX1_CLR;             /**< offset: 0x1848 */
  __IO uint32_t WFE_A_STAGE3_MUX1_TOG;             /**< offset: 0x184C */
  __IO uint32_t WFE_A_STAGE3_MUX2;                 /**< offset: 0x1850 */
  __IO uint32_t WFE_A_STAGE3_MUX2_SET;             /**< offset: 0x1854 */
  __IO uint32_t WFE_A_STAGE3_MUX2_CLR;             /**< offset: 0x1858 */
  __IO uint32_t WFE_A_STAGE3_MUX2_TOG;             /**< offset: 0x185C */
  __IO uint32_t WFE_A_STAGE3_MUX3;                 /**< offset: 0x1860 */
  __IO uint32_t WFE_A_STAGE3_MUX3_SET;             /**< offset: 0x1864 */
  __IO uint32_t WFE_A_STAGE3_MUX3_CLR;             /**< offset: 0x1868 */
  __IO uint32_t WFE_A_STAGE3_MUX3_TOG;             /**< offset: 0x186C */
  __IO uint32_t WFE_A_STG1_8X1_OUT0_0;             /**< offset: 0x1870 */
       uint8_t RESERVED_254[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT0_1;             /**< offset: 0x1880 */
       uint8_t RESERVED_255[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT0_2;             /**< offset: 0x1890 */
       uint8_t RESERVED_256[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT0_3;             /**< offset: 0x18A0 */
       uint8_t RESERVED_257[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT0_4;             /**< offset: 0x18B0 */
       uint8_t RESERVED_258[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT0_5;             /**< offset: 0x18C0 */
       uint8_t RESERVED_259[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT0_6;             /**< offset: 0x18D0 */
       uint8_t RESERVED_260[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT0_7;             /**< offset: 0x18E0 */
       uint8_t RESERVED_261[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT1_0;             /**< offset: 0x18F0 */
       uint8_t RESERVED_262[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT1_1;             /**< offset: 0x1900 */
       uint8_t RESERVED_263[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT1_2;             /**< offset: 0x1910 */
       uint8_t RESERVED_264[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT1_3;             /**< offset: 0x1920 */
       uint8_t RESERVED_265[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT1_4;             /**< offset: 0x1930 */
       uint8_t RESERVED_266[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT1_5;             /**< offset: 0x1940 */
       uint8_t RESERVED_267[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT1_6;             /**< offset: 0x1950 */
       uint8_t RESERVED_268[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT1_7;             /**< offset: 0x1960 */
       uint8_t RESERVED_269[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT2_0;             /**< offset: 0x1970 */
       uint8_t RESERVED_270[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT2_1;             /**< offset: 0x1980 */
       uint8_t RESERVED_271[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT2_2;             /**< offset: 0x1990 */
       uint8_t RESERVED_272[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT2_3;             /**< offset: 0x19A0 */
       uint8_t RESERVED_273[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT2_4;             /**< offset: 0x19B0 */
       uint8_t RESERVED_274[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT2_5;             /**< offset: 0x19C0 */
       uint8_t RESERVED_275[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT2_6;             /**< offset: 0x19D0 */
       uint8_t RESERVED_276[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT2_7;             /**< offset: 0x19E0 */
       uint8_t RESERVED_277[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT3_0;             /**< offset: 0x19F0 */
       uint8_t RESERVED_278[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT3_1;             /**< offset: 0x1A00 */
       uint8_t RESERVED_279[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT3_2;             /**< offset: 0x1A10 */
       uint8_t RESERVED_280[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT3_3;             /**< offset: 0x1A20 */
       uint8_t RESERVED_281[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT3_4;             /**< offset: 0x1A30 */
       uint8_t RESERVED_282[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT3_5;             /**< offset: 0x1A40 */
       uint8_t RESERVED_283[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT3_6;             /**< offset: 0x1A50 */
       uint8_t RESERVED_284[12];
  __IO uint32_t WFE_A_STG1_8X1_OUT3_7;             /**< offset: 0x1A60 */
       uint8_t RESERVED_285[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT0_0;             /**< offset: 0x1A70 */
       uint8_t RESERVED_286[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT0_1;             /**< offset: 0x1A80 */
       uint8_t RESERVED_287[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT0_2;             /**< offset: 0x1A90 */
       uint8_t RESERVED_288[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT0_3;             /**< offset: 0x1AA0 */
       uint8_t RESERVED_289[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT0_4;             /**< offset: 0x1AB0 */
       uint8_t RESERVED_290[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT0_5;             /**< offset: 0x1AC0 */
       uint8_t RESERVED_291[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT0_6;             /**< offset: 0x1AD0 */
       uint8_t RESERVED_292[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT0_7;             /**< offset: 0x1AE0 */
       uint8_t RESERVED_293[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT1_0;             /**< offset: 0x1AF0 */
       uint8_t RESERVED_294[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT1_1;             /**< offset: 0x1B00 */
       uint8_t RESERVED_295[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT1_2;             /**< offset: 0x1B10 */
       uint8_t RESERVED_296[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT1_3;             /**< offset: 0x1B20 */
       uint8_t RESERVED_297[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT1_4;             /**< offset: 0x1B30 */
       uint8_t RESERVED_298[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT1_5;             /**< offset: 0x1B40 */
       uint8_t RESERVED_299[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT1_6;             /**< offset: 0x1B50 */
       uint8_t RESERVED_300[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT1_7;             /**< offset: 0x1B60 */
       uint8_t RESERVED_301[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT2_0;             /**< offset: 0x1B70 */
       uint8_t RESERVED_302[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT2_1;             /**< offset: 0x1B80 */
       uint8_t RESERVED_303[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT2_2;             /**< offset: 0x1B90 */
       uint8_t RESERVED_304[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT2_3;             /**< offset: 0x1BA0 */
       uint8_t RESERVED_305[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT2_4;             /**< offset: 0x1BB0 */
       uint8_t RESERVED_306[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT2_5;             /**< offset: 0x1BC0 */
       uint8_t RESERVED_307[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT2_6;             /**< offset: 0x1BD0 */
       uint8_t RESERVED_308[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT2_7;             /**< offset: 0x1BE0 */
       uint8_t RESERVED_309[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT3_0;             /**< offset: 0x1BF0 */
       uint8_t RESERVED_310[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT3_1;             /**< offset: 0x1C00 */
       uint8_t RESERVED_311[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT3_2;             /**< offset: 0x1C10 */
       uint8_t RESERVED_312[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT3_3;             /**< offset: 0x1C20 */
       uint8_t RESERVED_313[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT3_4;             /**< offset: 0x1C30 */
       uint8_t RESERVED_314[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT3_5;             /**< offset: 0x1C40 */
       uint8_t RESERVED_315[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT3_6;             /**< offset: 0x1C50 */
       uint8_t RESERVED_316[12];
  __IO uint32_t WFE_A_STG2_5X6_OUT3_7;             /**< offset: 0x1C60 */
       uint8_t RESERVED_317[12];
  __IO uint32_t WFE_A_STAGE2_5X6_MASKS_0;          /**< offset: 0x1C70 */
       uint8_t RESERVED_318[12];
  __IO uint32_t WFE_A_STAGE2_5X6_ADDR_0;           /**< offset: 0x1C80 */
       uint8_t RESERVED_319[12];
  __IO uint32_t WFE_A_STG2_5X1_OUT0;               /**< offset: 0x1C90 */
       uint8_t RESERVED_320[12];
  __IO uint32_t WFE_A_STG2_5X1_OUT1;               /**< offset: 0x1CA0 */
       uint8_t RESERVED_321[12];
  __IO uint32_t WFE_A_STG2_5X1_OUT2;               /**< offset: 0x1CB0 */
       uint8_t RESERVED_322[12];
  __IO uint32_t WFE_A_STG2_5X1_OUT3;               /**< offset: 0x1CC0 */
       uint8_t RESERVED_323[12];
  __IO uint32_t WFE_A_STG2_5X1_MASKS;              /**< offset: 0x1CD0 */
       uint8_t RESERVED_324[44];
  __IO uint32_t WFE_B_CTRL;                        /**< offset: 0x1D00 */
  __IO uint32_t WFE_B_CTRL_SET;                    /**< offset: 0x1D04 */
  __IO uint32_t WFE_B_CTRL_CLR;                    /**< offset: 0x1D08 */
  __IO uint32_t WFE_B_CTRL_TOG;                    /**< offset: 0x1D0C */
  __IO uint32_t WFE_B_DIMENSIONS;                  /**< offset: 0x1D10 */
       uint8_t RESERVED_325[12];
  __IO uint32_t WFE_B_OFFSET;                      /**< offset: 0x1D20 */
       uint8_t RESERVED_326[12];
  __IO uint32_t WFE_B_SW_DATA_REGS;                /**< offset: 0x1D30 */
       uint8_t RESERVED_327[12];
  __IO uint32_t WFE_B_SW_FLAG_REGS;                /**< offset: 0x1D40 */
       uint8_t RESERVED_328[12];
  __IO uint32_t WFE_B_STAGE1_MUX0;                 /**< offset: 0x1D50 */
  __IO uint32_t WFE_B_STAGE1_MUX0_SET;             /**< offset: 0x1D54 */
  __IO uint32_t WFE_B_STAGE1_MUX0_CLR;             /**< offset: 0x1D58 */
  __IO uint32_t WFE_B_STAGE1_MUX0_TOG;             /**< offset: 0x1D5C */
  __IO uint32_t WFE_B_STAGE1_MUX1;                 /**< offset: 0x1D60 */
  __IO uint32_t WFE_B_STAGE1_MUX1_SET;             /**< offset: 0x1D64 */
  __IO uint32_t WFE_B_STAGE1_MUX1_CLR;             /**< offset: 0x1D68 */
  __IO uint32_t WFE_B_STAGE1_MUX1_TOG;             /**< offset: 0x1D6C */
  __IO uint32_t WFE_B_STAGE1_MUX2;                 /**< offset: 0x1D70 */
  __IO uint32_t WFE_B_STAGE1_MUX2_SET;             /**< offset: 0x1D74 */
  __IO uint32_t WFE_B_STAGE1_MUX2_CLR;             /**< offset: 0x1D78 */
  __IO uint32_t WFE_B_STAGE1_MUX2_TOG;             /**< offset: 0x1D7C */
  __IO uint32_t WFE_B_STAGE1_MUX3;                 /**< offset: 0x1D80 */
  __IO uint32_t WFE_B_STAGE1_MUX3_SET;             /**< offset: 0x1D84 */
  __IO uint32_t WFE_B_STAGE1_MUX3_CLR;             /**< offset: 0x1D88 */
  __IO uint32_t WFE_B_STAGE1_MUX3_TOG;             /**< offset: 0x1D8C */
  __IO uint32_t WFE_B_STAGE1_MUX4;                 /**< offset: 0x1D90 */
  __IO uint32_t WFE_B_STAGE1_MUX4_SET;             /**< offset: 0x1D94 */
  __IO uint32_t WFE_B_STAGE1_MUX4_CLR;             /**< offset: 0x1D98 */
  __IO uint32_t WFE_B_STAGE1_MUX4_TOG;             /**< offset: 0x1D9C */
  __IO uint32_t WFE_B_STAGE1_MUX5;                 /**< offset: 0x1DA0 */
  __IO uint32_t WFE_B_STAGE1_MUX5_SET;             /**< offset: 0x1DA4 */
  __IO uint32_t WFE_B_STAGE1_MUX5_CLR;             /**< offset: 0x1DA8 */
  __IO uint32_t WFE_B_STAGE1_MUX5_TOG;             /**< offset: 0x1DAC */
  __IO uint32_t WFE_B_STAGE1_MUX6;                 /**< offset: 0x1DB0 */
  __IO uint32_t WFE_B_STAGE1_MUX6_SET;             /**< offset: 0x1DB4 */
  __IO uint32_t WFE_B_STAGE1_MUX6_CLR;             /**< offset: 0x1DB8 */
  __IO uint32_t WFE_B_STAGE1_MUX6_TOG;             /**< offset: 0x1DBC */
  __IO uint32_t WFE_B_STAGE1_MUX7;                 /**< offset: 0x1DC0 */
  __IO uint32_t WFE_B_STAGE1_MUX7_SET;             /**< offset: 0x1DC4 */
  __IO uint32_t WFE_B_STAGE1_MUX7_CLR;             /**< offset: 0x1DC8 */
  __IO uint32_t WFE_B_STAGE1_MUX7_TOG;             /**< offset: 0x1DCC */
  __IO uint32_t WFE_B_STAGE1_MUX8;                 /**< offset: 0x1DD0 */
  __IO uint32_t WFE_B_STAGE1_MUX8_SET;             /**< offset: 0x1DD4 */
  __IO uint32_t WFE_B_STAGE1_MUX8_CLR;             /**< offset: 0x1DD8 */
  __IO uint32_t WFE_B_STAGE1_MUX8_TOG;             /**< offset: 0x1DDC */
  __IO uint32_t WFE_B_STAGE2_MUX0;                 /**< offset: 0x1DE0 */
  __IO uint32_t WFE_B_STAGE2_MUX0_SET;             /**< offset: 0x1DE4 */
  __IO uint32_t WFE_B_STAGE2_MUX0_CLR;             /**< offset: 0x1DE8 */
  __IO uint32_t WFE_B_STAGE2_MUX0_TOG;             /**< offset: 0x1DEC */
  __IO uint32_t WFE_B_STAGE2_MUX1;                 /**< offset: 0x1DF0 */
  __IO uint32_t WFE_B_STAGE2_MUX1_SET;             /**< offset: 0x1DF4 */
  __IO uint32_t WFE_B_STAGE2_MUX1_CLR;             /**< offset: 0x1DF8 */
  __IO uint32_t WFE_B_STAGE2_MUX1_TOG;             /**< offset: 0x1DFC */
  __IO uint32_t WFE_B_STAGE2_MUX2;                 /**< offset: 0x1E00 */
  __IO uint32_t WFE_B_STAGE2_MUX2_SET;             /**< offset: 0x1E04 */
  __IO uint32_t WFE_B_STAGE2_MUX2_CLR;             /**< offset: 0x1E08 */
  __IO uint32_t WFE_B_STAGE2_MUX2_TOG;             /**< offset: 0x1E0C */
  __IO uint32_t WFE_B_STAGE2_MUX3;                 /**< offset: 0x1E10 */
  __IO uint32_t WFE_B_STAGE2_MUX3_SET;             /**< offset: 0x1E14 */
  __IO uint32_t WFE_B_STAGE2_MUX3_CLR;             /**< offset: 0x1E18 */
  __IO uint32_t WFE_B_STAGE2_MUX3_TOG;             /**< offset: 0x1E1C */
  __IO uint32_t WFE_B_STAGE2_MUX4;                 /**< offset: 0x1E20 */
  __IO uint32_t WFE_B_STAGE2_MUX4_SET;             /**< offset: 0x1E24 */
  __IO uint32_t WFE_B_STAGE2_MUX4_CLR;             /**< offset: 0x1E28 */
  __IO uint32_t WFE_B_STAGE2_MUX4_TOG;             /**< offset: 0x1E2C */
  __IO uint32_t WFE_B_STAGE2_MUX5;                 /**< offset: 0x1E30 */
  __IO uint32_t WFE_B_STAGE2_MUX5_SET;             /**< offset: 0x1E34 */
  __IO uint32_t WFE_B_STAGE2_MUX5_CLR;             /**< offset: 0x1E38 */
  __IO uint32_t WFE_B_STAGE2_MUX5_TOG;             /**< offset: 0x1E3C */
  __IO uint32_t WFE_B_STAGE2_MUX6;                 /**< offset: 0x1E40 */
  __IO uint32_t WFE_B_STAGE2_MUX6_SET;             /**< offset: 0x1E44 */
  __IO uint32_t WFE_B_STAGE2_MUX6_CLR;             /**< offset: 0x1E48 */
  __IO uint32_t WFE_B_STAGE2_MUX6_TOG;             /**< offset: 0x1E4C */
  __IO uint32_t WFE_B_STAGE2_MUX7;                 /**< offset: 0x1E50 */
  __IO uint32_t WFE_B_STAGE2_MUX7_SET;             /**< offset: 0x1E54 */
  __IO uint32_t WFE_B_STAGE2_MUX7_CLR;             /**< offset: 0x1E58 */
  __IO uint32_t WFE_B_STAGE2_MUX7_TOG;             /**< offset: 0x1E5C */
  __IO uint32_t WFE_B_STAGE2_MUX8;                 /**< offset: 0x1E60 */
  __IO uint32_t WFE_B_STAGE2_MUX8_SET;             /**< offset: 0x1E64 */
  __IO uint32_t WFE_B_STAGE2_MUX8_CLR;             /**< offset: 0x1E68 */
  __IO uint32_t WFE_B_STAGE2_MUX8_TOG;             /**< offset: 0x1E6C */
  __IO uint32_t WFE_B_STAGE2_MUX9;                 /**< offset: 0x1E70 */
  __IO uint32_t WFE_B_STAGE2_MUX9_SET;             /**< offset: 0x1E74 */
  __IO uint32_t WFE_B_STAGE2_MUX9_CLR;             /**< offset: 0x1E78 */
  __IO uint32_t WFE_B_STAGE2_MUX9_TOG;             /**< offset: 0x1E7C */
  __IO uint32_t WFE_B_STAGE2_MUX10;                /**< offset: 0x1E80 */
  __IO uint32_t WFE_B_STAGE2_MUX10_SET;            /**< offset: 0x1E84 */
  __IO uint32_t WFE_B_STAGE2_MUX10_CLR;            /**< offset: 0x1E88 */
  __IO uint32_t WFE_B_STAGE2_MUX10_TOG;            /**< offset: 0x1E8C */
  __IO uint32_t WFE_B_STAGE2_MUX11;                /**< offset: 0x1E90 */
  __IO uint32_t WFE_B_STAGE2_MUX11_SET;            /**< offset: 0x1E94 */
  __IO uint32_t WFE_B_STAGE2_MUX11_CLR;            /**< offset: 0x1E98 */
  __IO uint32_t WFE_B_STAGE2_MUX11_TOG;            /**< offset: 0x1E9C */
  __IO uint32_t WFE_B_STAGE2_MUX12;                /**< offset: 0x1EA0 */
  __IO uint32_t WFE_B_STAGE2_MUX12_SET;            /**< offset: 0x1EA4 */
  __IO uint32_t WFE_B_STAGE2_MUX12_CLR;            /**< offset: 0x1EA8 */
  __IO uint32_t WFE_B_STAGE2_MUX12_TOG;            /**< offset: 0x1EAC */
  __IO uint32_t WFE_B_STAGE3_MUX0;                 /**< offset: 0x1EB0 */
  __IO uint32_t WFE_B_STAGE3_MUX0_SET;             /**< offset: 0x1EB4 */
  __IO uint32_t WFE_B_STAGE3_MUX0_CLR;             /**< offset: 0x1EB8 */
  __IO uint32_t WFE_B_STAGE3_MUX0_TOG;             /**< offset: 0x1EBC */
  __IO uint32_t WFE_B_STAGE3_MUX1;                 /**< offset: 0x1EC0 */
  __IO uint32_t WFE_B_STAGE3_MUX1_SET;             /**< offset: 0x1EC4 */
  __IO uint32_t WFE_B_STAGE3_MUX1_CLR;             /**< offset: 0x1EC8 */
  __IO uint32_t WFE_B_STAGE3_MUX1_TOG;             /**< offset: 0x1ECC */
  __IO uint32_t WFE_B_STAGE3_MUX2;                 /**< offset: 0x1ED0 */
  __IO uint32_t WFE_B_STAGE3_MUX2_SET;             /**< offset: 0x1ED4 */
  __IO uint32_t WFE_B_STAGE3_MUX2_CLR;             /**< offset: 0x1ED8 */
  __IO uint32_t WFE_B_STAGE3_MUX2_TOG;             /**< offset: 0x1EDC */
  __IO uint32_t WFE_B_STAGE3_MUX3;                 /**< offset: 0x1EE0 */
  __IO uint32_t WFE_B_STAGE3_MUX3_SET;             /**< offset: 0x1EE4 */
  __IO uint32_t WFE_B_STAGE3_MUX3_CLR;             /**< offset: 0x1EE8 */
  __IO uint32_t WFE_B_STAGE3_MUX3_TOG;             /**< offset: 0x1EEC */
  __IO uint32_t WFE_B_STAGE3_MUX4;                 /**< offset: 0x1EF0 */
  __IO uint32_t WFE_B_STAGE3_MUX4_SET;             /**< offset: 0x1EF4 */
  __IO uint32_t WFE_B_STAGE3_MUX4_CLR;             /**< offset: 0x1EF8 */
  __IO uint32_t WFE_B_STAGE3_MUX4_TOG;             /**< offset: 0x1EFC */
  __IO uint32_t WFE_B_STAGE3_MUX5;                 /**< offset: 0x1F00 */
  __IO uint32_t WFE_B_STAGE3_MUX5_SET;             /**< offset: 0x1F04 */
  __IO uint32_t WFE_B_STAGE3_MUX5_CLR;             /**< offset: 0x1F08 */
  __IO uint32_t WFE_B_STAGE3_MUX5_TOG;             /**< offset: 0x1F0C */
  __IO uint32_t WFE_B_STAGE3_MUX6;                 /**< offset: 0x1F10 */
  __IO uint32_t WFE_B_STAGE3_MUX6_SET;             /**< offset: 0x1F14 */
  __IO uint32_t WFE_B_STAGE3_MUX6_CLR;             /**< offset: 0x1F18 */
  __IO uint32_t WFE_B_STAGE3_MUX6_TOG;             /**< offset: 0x1F1C */
  __IO uint32_t WFE_B_STAGE3_MUX7;                 /**< offset: 0x1F20 */
  __IO uint32_t WFE_B_STAGE3_MUX7_SET;             /**< offset: 0x1F24 */
  __IO uint32_t WFE_B_STAGE3_MUX7_CLR;             /**< offset: 0x1F28 */
  __IO uint32_t WFE_B_STAGE3_MUX7_TOG;             /**< offset: 0x1F2C */
  __IO uint32_t WFE_B_STAGE3_MUX8;                 /**< offset: 0x1F30 */
  __IO uint32_t WFE_B_STAGE3_MUX8_SET;             /**< offset: 0x1F34 */
  __IO uint32_t WFE_B_STAGE3_MUX8_CLR;             /**< offset: 0x1F38 */
  __IO uint32_t WFE_B_STAGE3_MUX8_TOG;             /**< offset: 0x1F3C */
  __IO uint32_t WFE_B_STAGE3_MUX9;                 /**< offset: 0x1F40 */
  __IO uint32_t WFE_B_STAGE3_MUX9_SET;             /**< offset: 0x1F44 */
  __IO uint32_t WFE_B_STAGE3_MUX9_CLR;             /**< offset: 0x1F48 */
  __IO uint32_t WFE_B_STAGE3_MUX9_TOG;             /**< offset: 0x1F4C */
  __IO uint32_t WFE_B_STAGE3_MUX10;                /**< offset: 0x1F50 */
  __IO uint32_t WFE_B_STAGE3_MUX10_SET;            /**< offset: 0x1F54 */
  __IO uint32_t WFE_B_STAGE3_MUX10_CLR;            /**< offset: 0x1F58 */
  __IO uint32_t WFE_B_STAGE3_MUX10_TOG;            /**< offset: 0x1F5C */
  __IO uint32_t WFE_B_STG1_5X8_OUT0_0;             /**< offset: 0x1F60 */
       uint8_t RESERVED_329[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT0_1;             /**< offset: 0x1F70 */
       uint8_t RESERVED_330[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT0_2;             /**< offset: 0x1F80 */
       uint8_t RESERVED_331[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT0_3;             /**< offset: 0x1F90 */
       uint8_t RESERVED_332[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT0_4;             /**< offset: 0x1FA0 */
       uint8_t RESERVED_333[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT0_5;             /**< offset: 0x1FB0 */
       uint8_t RESERVED_334[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT0_6;             /**< offset: 0x1FC0 */
       uint8_t RESERVED_335[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT0_7;             /**< offset: 0x1FD0 */
       uint8_t RESERVED_336[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT1_0;             /**< offset: 0x1FE0 */
       uint8_t RESERVED_337[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT1_1;             /**< offset: 0x1FF0 */
       uint8_t RESERVED_338[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT1_2;             /**< offset: 0x2000 */
       uint8_t RESERVED_339[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT1_3;             /**< offset: 0x2010 */
       uint8_t RESERVED_340[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT1_4;             /**< offset: 0x2020 */
       uint8_t RESERVED_341[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT1_5;             /**< offset: 0x2030 */
       uint8_t RESERVED_342[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT1_6;             /**< offset: 0x2040 */
       uint8_t RESERVED_343[12];
  __IO uint32_t WFE_B_STG1_5X8_OUT1_7;             /**< offset: 0x2050 */
       uint8_t RESERVED_344[12];
  __IO uint32_t WFE_B_STAGE1_5X8_MASKS_0;          /**< offset: 0x2060 */
       uint8_t RESERVED_345[12];
  __IO uint32_t WFE_B_STG1_5X1_OUT0;               /**< offset: 0x2070 */
       uint8_t RESERVED_346[12];
  __IO uint32_t WFE_B_STG1_5X1_MASKS;              /**< offset: 0x2080 */
       uint8_t RESERVED_347[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT0_0;             /**< offset: 0x2090 */
       uint8_t RESERVED_348[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT0_1;             /**< offset: 0x20A0 */
       uint8_t RESERVED_349[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT0_2;             /**< offset: 0x20B0 */
       uint8_t RESERVED_350[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT0_3;             /**< offset: 0x20C0 */
       uint8_t RESERVED_351[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT0_4;             /**< offset: 0x20D0 */
       uint8_t RESERVED_352[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT0_5;             /**< offset: 0x20E0 */
       uint8_t RESERVED_353[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT0_6;             /**< offset: 0x20F0 */
       uint8_t RESERVED_354[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT0_7;             /**< offset: 0x2100 */
       uint8_t RESERVED_355[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT1_0;             /**< offset: 0x2110 */
       uint8_t RESERVED_356[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT1_1;             /**< offset: 0x2120 */
       uint8_t RESERVED_357[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT1_2;             /**< offset: 0x2130 */
       uint8_t RESERVED_358[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT1_3;             /**< offset: 0x2140 */
       uint8_t RESERVED_359[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT1_4;             /**< offset: 0x2150 */
       uint8_t RESERVED_360[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT1_5;             /**< offset: 0x2160 */
       uint8_t RESERVED_361[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT1_6;             /**< offset: 0x2170 */
       uint8_t RESERVED_362[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT1_7;             /**< offset: 0x2180 */
       uint8_t RESERVED_363[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT2_0;             /**< offset: 0x2190 */
       uint8_t RESERVED_364[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT2_1;             /**< offset: 0x21A0 */
       uint8_t RESERVED_365[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT2_2;             /**< offset: 0x21B0 */
       uint8_t RESERVED_366[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT2_3;             /**< offset: 0x21C0 */
       uint8_t RESERVED_367[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT2_4;             /**< offset: 0x21D0 */
       uint8_t RESERVED_368[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT2_5;             /**< offset: 0x21E0 */
       uint8_t RESERVED_369[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT2_6;             /**< offset: 0x21F0 */
       uint8_t RESERVED_370[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT2_7;             /**< offset: 0x2200 */
       uint8_t RESERVED_371[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT3_0;             /**< offset: 0x2210 */
       uint8_t RESERVED_372[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT3_1;             /**< offset: 0x2220 */
       uint8_t RESERVED_373[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT3_2;             /**< offset: 0x2230 */
       uint8_t RESERVED_374[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT3_3;             /**< offset: 0x2240 */
       uint8_t RESERVED_375[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT3_4;             /**< offset: 0x2250 */
       uint8_t RESERVED_376[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT3_5;             /**< offset: 0x2260 */
       uint8_t RESERVED_377[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT3_6;             /**< offset: 0x2270 */
       uint8_t RESERVED_378[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT3_7;             /**< offset: 0x2280 */
       uint8_t RESERVED_379[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT4_0;             /**< offset: 0x2290 */
       uint8_t RESERVED_380[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT4_1;             /**< offset: 0x22A0 */
       uint8_t RESERVED_381[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT4_2;             /**< offset: 0x22B0 */
       uint8_t RESERVED_382[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT4_3;             /**< offset: 0x22C0 */
       uint8_t RESERVED_383[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT4_4;             /**< offset: 0x22D0 */
       uint8_t RESERVED_384[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT4_5;             /**< offset: 0x22E0 */
       uint8_t RESERVED_385[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT4_6;             /**< offset: 0x22F0 */
       uint8_t RESERVED_386[12];
  __IO uint32_t WFE_B_STG1_8X1_OUT4_7;             /**< offset: 0x2300 */
       uint8_t RESERVED_387[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT0_0;             /**< offset: 0x2310 */
       uint8_t RESERVED_388[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT0_1;             /**< offset: 0x2320 */
       uint8_t RESERVED_389[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT0_2;             /**< offset: 0x2330 */
       uint8_t RESERVED_390[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT0_3;             /**< offset: 0x2340 */
       uint8_t RESERVED_391[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT0_4;             /**< offset: 0x2350 */
       uint8_t RESERVED_392[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT0_5;             /**< offset: 0x2360 */
       uint8_t RESERVED_393[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT0_6;             /**< offset: 0x2370 */
       uint8_t RESERVED_394[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT0_7;             /**< offset: 0x2380 */
       uint8_t RESERVED_395[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT1_0;             /**< offset: 0x2390 */
       uint8_t RESERVED_396[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT1_1;             /**< offset: 0x23A0 */
       uint8_t RESERVED_397[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT1_2;             /**< offset: 0x23B0 */
       uint8_t RESERVED_398[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT1_3;             /**< offset: 0x23C0 */
       uint8_t RESERVED_399[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT1_4;             /**< offset: 0x23D0 */
       uint8_t RESERVED_400[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT1_5;             /**< offset: 0x23E0 */
       uint8_t RESERVED_401[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT1_6;             /**< offset: 0x23F0 */
       uint8_t RESERVED_402[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT1_7;             /**< offset: 0x2400 */
       uint8_t RESERVED_403[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT2_0;             /**< offset: 0x2410 */
       uint8_t RESERVED_404[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT2_1;             /**< offset: 0x2420 */
       uint8_t RESERVED_405[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT2_2;             /**< offset: 0x2430 */
       uint8_t RESERVED_406[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT2_3;             /**< offset: 0x2440 */
       uint8_t RESERVED_407[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT2_4;             /**< offset: 0x2450 */
       uint8_t RESERVED_408[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT2_5;             /**< offset: 0x2460 */
       uint8_t RESERVED_409[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT2_6;             /**< offset: 0x2470 */
       uint8_t RESERVED_410[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT2_7;             /**< offset: 0x2480 */
       uint8_t RESERVED_411[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT3_0;             /**< offset: 0x2490 */
       uint8_t RESERVED_412[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT3_1;             /**< offset: 0x24A0 */
       uint8_t RESERVED_413[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT3_2;             /**< offset: 0x24B0 */
       uint8_t RESERVED_414[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT3_3;             /**< offset: 0x24C0 */
       uint8_t RESERVED_415[28];
  __IO uint32_t WFE_B_STG2_5X6_OUT3_4;             /**< offset: 0x24E0 */
       uint8_t RESERVED_416[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT3_5;             /**< offset: 0x24F0 */
       uint8_t RESERVED_417[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT3_6;             /**< offset: 0x2500 */
       uint8_t RESERVED_418[12];
  __IO uint32_t WFE_B_STG2_5X6_OUT3_7;             /**< offset: 0x2510 */
       uint8_t RESERVED_419[12];
  __IO uint32_t WFE_B_STAGE2_5X6_MASKS_0;          /**< offset: 0x2520 */
       uint8_t RESERVED_420[12];
  __IO uint32_t WFE_B_STAGE2_5X6_ADDR_0;           /**< offset: 0x2530 */
       uint8_t RESERVED_421[12];
  __IO uint32_t WFE_B_STG2_5X1_OUT0;               /**< offset: 0x2540 */
       uint8_t RESERVED_422[12];
  __IO uint32_t WFE_B_STG2_5X1_OUT1;               /**< offset: 0x2550 */
       uint8_t RESERVED_423[12];
  __IO uint32_t WFE_B_STG2_5X1_OUT2;               /**< offset: 0x2560 */
       uint8_t RESERVED_424[12];
  __IO uint32_t WFE_B_STG2_5X1_OUT3;               /**< offset: 0x2570 */
       uint8_t RESERVED_425[12];
  __IO uint32_t WFE_B_STG2_5X1_MASKS;              /**< offset: 0x2580 */
       uint8_t RESERVED_426[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT0_0;            /**< offset: 0x2590 */
       uint8_t RESERVED_427[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT0_1;            /**< offset: 0x25A0 */
       uint8_t RESERVED_428[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT0_2;            /**< offset: 0x25B0 */
       uint8_t RESERVED_429[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT0_3;            /**< offset: 0x25C0 */
       uint8_t RESERVED_430[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT0_4;            /**< offset: 0x25D0 */
       uint8_t RESERVED_431[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT0_5;            /**< offset: 0x25E0 */
       uint8_t RESERVED_432[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT0_6;            /**< offset: 0x25F0 */
       uint8_t RESERVED_433[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT0_7;            /**< offset: 0x2600 */
       uint8_t RESERVED_434[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT1_0;            /**< offset: 0x2610 */
       uint8_t RESERVED_435[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT1_1;            /**< offset: 0x2620 */
       uint8_t RESERVED_436[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT1_2;            /**< offset: 0x2630 */
       uint8_t RESERVED_437[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT1_3;            /**< offset: 0x2640 */
       uint8_t RESERVED_438[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT1_4;            /**< offset: 0x2650 */
       uint8_t RESERVED_439[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT1_5;            /**< offset: 0x2660 */
       uint8_t RESERVED_440[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT1_6;            /**< offset: 0x2670 */
       uint8_t RESERVED_441[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT1_7;            /**< offset: 0x2680 */
       uint8_t RESERVED_442[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT2_0;            /**< offset: 0x2690 */
       uint8_t RESERVED_443[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT2_1;            /**< offset: 0x26A0 */
       uint8_t RESERVED_444[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT2_2;            /**< offset: 0x26B0 */
       uint8_t RESERVED_445[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT2_3;            /**< offset: 0x26C0 */
       uint8_t RESERVED_446[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT2_4;            /**< offset: 0x26D0 */
       uint8_t RESERVED_447[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT2_5;            /**< offset: 0x26E0 */
       uint8_t RESERVED_448[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT2_6;            /**< offset: 0x26F0 */
       uint8_t RESERVED_449[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT2_7;            /**< offset: 0x2700 */
       uint8_t RESERVED_450[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT3_0;            /**< offset: 0x2710 */
       uint8_t RESERVED_451[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT3_1;            /**< offset: 0x2720 */
       uint8_t RESERVED_452[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT3_2;            /**< offset: 0x2730 */
       uint8_t RESERVED_453[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT3_3;            /**< offset: 0x2740 */
       uint8_t RESERVED_454[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT3_4;            /**< offset: 0x2750 */
       uint8_t RESERVED_455[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT3_5;            /**< offset: 0x2760 */
       uint8_t RESERVED_456[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT3_6;            /**< offset: 0x2770 */
       uint8_t RESERVED_457[12];
  __IO uint32_t WFE_B_STG3_F8X1_OUT3_7;            /**< offset: 0x2780 */
       uint8_t RESERVED_458[12];
  __IO uint32_t WFE_B_STG3_F8X1_MASKS;             /**< offset: 0x2790 */
       uint8_t RESERVED_459[124];
  __IO uint32_t ALU_A_CTRL;                        /**< offset: 0x2810 */
  __IO uint32_t ALU_A_CTRL_SET;                    /**< offset: 0x2814 */
  __IO uint32_t ALU_A_CTRL_CLR;                    /**< offset: 0x2818 */
  __IO uint32_t ALU_A_CTRL_TOG;                    /**< offset: 0x281C */
  __IO uint32_t ALU_A_BUF_SIZE;                    /**< offset: 0x2820 */
       uint8_t RESERVED_460[12];
  __IO uint32_t ALU_A_INST_ENTRY;                  /**< offset: 0x2830 */
       uint8_t RESERVED_461[12];
  __IO uint32_t ALU_A_PARAM;                       /**< offset: 0x2840 */
       uint8_t RESERVED_462[12];
  __IO uint32_t ALU_A_CONFIG;                      /**< offset: 0x2850 */
       uint8_t RESERVED_463[12];
  __IO uint32_t ALU_A_LUT_CONFIG;                  /**< offset: 0x2860 */
  __IO uint32_t ALU_A_LUT_CONFIG_SET;              /**< offset: 0x2864 */
  __IO uint32_t ALU_A_LUT_CONFIG_CLR;              /**< offset: 0x2868 */
  __IO uint32_t ALU_A_LUT_CONFIG_TOG;              /**< offset: 0x286C */
  __IO uint32_t ALU_A_LUT_DATA0;                   /**< offset: 0x2870 */
       uint8_t RESERVED_464[12];
  __IO uint32_t ALU_A_LUT_DATA1;                   /**< offset: 0x2880 */
       uint8_t RESERVED_465[12];
  __IO uint32_t ALU_A_DBG;                         /**< offset: 0x2890 */
       uint8_t RESERVED_466[12];
  __IO uint32_t ALU_B_CTRL;                        /**< offset: 0x28A0 */
  __IO uint32_t ALU_B_CTRL_SET;                    /**< offset: 0x28A4 */
  __IO uint32_t ALU_B_CTRL_CLR;                    /**< offset: 0x28A8 */
  __IO uint32_t ALU_B_CTRL_TOG;                    /**< offset: 0x28AC */
  __IO uint32_t ALU_B_BUF_SIZE;                    /**< offset: 0x28B0 */
       uint8_t RESERVED_467[12];
  __IO uint32_t ALU_B_INST_ENTRY;                  /**< offset: 0x28C0 */
       uint8_t RESERVED_468[12];
  __IO uint32_t ALU_B_PARAM;                       /**< offset: 0x28D0 */
       uint8_t RESERVED_469[12];
  __IO uint32_t ALU_B_CONFIG;                      /**< offset: 0x28E0 */
       uint8_t RESERVED_470[12];
  __IO uint32_t ALU_B_LUT_CONFIG;                  /**< offset: 0x28F0 */
  __IO uint32_t ALU_B_LUT_CONFIG_SET;              /**< offset: 0x28F4 */
  __IO uint32_t ALU_B_LUT_CONFIG_CLR;              /**< offset: 0x28F8 */
  __IO uint32_t ALU_B_LUT_CONFIG_TOG;              /**< offset: 0x28FC */
  __IO uint32_t ALU_B_LUT_DATA0;                   /**< offset: 0x2900 */
       uint8_t RESERVED_471[12];
  __IO uint32_t ALU_B_LUT_DATA1;                   /**< offset: 0x2910 */
       uint8_t RESERVED_472[12];
  __IO uint32_t ALU_B_DBG;                         /**< offset: 0x2920 */
       uint8_t RESERVED_473[220];
  __IO uint32_t HIST_A_CTRL;                       /**< Histogram Control Register., offset: 0x2A00 */
       uint8_t RESERVED_474[12];
  __IO uint32_t HIST_A_MASK;                       /**< Histogram Pixel Mask Register., offset: 0x2A10 */
       uint8_t RESERVED_475[12];
  __IO uint32_t HIST_A_BUF_SIZE;                   /**< Histogram Pixel Buffer Size Register., offset: 0x2A20 */
       uint8_t RESERVED_476[12];
  __I  uint32_t HIST_A_TOTAL_PIXEL;                /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2A30 */
       uint8_t RESERVED_477[12];
  __I  uint32_t HIST_A_ACTIVE_AREA_X;              /**< The X Coordinate Offset for Active Area., offset: 0x2A40 */
       uint8_t RESERVED_478[12];
  __I  uint32_t HIST_A_ACTIVE_AREA_Y;              /**< The Y Coordinate Offset for Active Area., offset: 0x2A50 */
       uint8_t RESERVED_479[12];
  __I  uint32_t HIST_A_RAW_STAT0;                  /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A60 */
       uint8_t RESERVED_480[12];
  __I  uint32_t HIST_A_RAW_STAT1;                  /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A70 */
       uint8_t RESERVED_481[12];
  __IO uint32_t HIST_B_CTRL;                       /**< Histogram Control Register., offset: 0x2A80 */
       uint8_t RESERVED_482[12];
  __IO uint32_t HIST_B_MASK;                       /**< Histogram Pixel Mask Register., offset: 0x2A90 */
       uint8_t RESERVED_483[12];
  __IO uint32_t HIST_B_BUF_SIZE;                   /**< Histogram Pixel Buffer Size Register., offset: 0x2AA0 */
       uint8_t RESERVED_484[12];
  __I  uint32_t HIST_B_TOTAL_PIXEL;                /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2AB0 */
       uint8_t RESERVED_485[12];
  __I  uint32_t HIST_B_ACTIVE_AREA_X;              /**< The X Coordinate Offset for Active Area., offset: 0x2AC0 */
       uint8_t RESERVED_486[12];
  __I  uint32_t HIST_B_ACTIVE_AREA_Y;              /**< The Y Coordinate Offset for Active Area., offset: 0x2AD0 */
       uint8_t RESERVED_487[12];
  __I  uint32_t HIST_B_RAW_STAT0;                  /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AE0 */
       uint8_t RESERVED_488[12];
  __I  uint32_t HIST_B_RAW_STAT1;                  /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AF0 */
       uint8_t RESERVED_489[12];
  __IO uint32_t HIST2_PARAM;                       /**< 2-level Histogram Parameter Register., offset: 0x2B00 */
       uint8_t RESERVED_490[12];
  __IO uint32_t HIST4_PARAM;                       /**< 4-level Histogram Parameter Register., offset: 0x2B10 */
       uint8_t RESERVED_491[12];
  __IO uint32_t HIST8_PARAM0;                      /**< 8-level Histogram Parameter 0 Register., offset: 0x2B20 */
       uint8_t RESERVED_492[12];
  __IO uint32_t HIST8_PARAM1;                      /**< 8-level Histogram Parameter 1 Register., offset: 0x2B30 */
       uint8_t RESERVED_493[12];
  __IO uint32_t HIST16_PARAM0;                     /**< 16-level Histogram Parameter 0 Register., offset: 0x2B40 */
       uint8_t RESERVED_494[12];
  __IO uint32_t HIST16_PARAM1;                     /**< 16-level Histogram Parameter 1 Register., offset: 0x2B50 */
       uint8_t RESERVED_495[12];
  __IO uint32_t HIST16_PARAM2;                     /**< 16-level Histogram Parameter 2 Register., offset: 0x2B60 */
       uint8_t RESERVED_496[12];
  __IO uint32_t HIST16_PARAM3;                     /**< 16-level Histogram Parameter 3 Register., offset: 0x2B70 */
       uint8_t RESERVED_497[12];
  __IO uint32_t HIST32_PARAM0;                     /**< 32-level Histogram Parameter 0 Register., offset: 0x2B80 */
       uint8_t RESERVED_498[12];
  __IO uint32_t HIST32_PARAM1;                     /**< 32-level Histogram Parameter 1 Register., offset: 0x2B90 */
       uint8_t RESERVED_499[12];
  __IO uint32_t HIST32_PARAM2;                     /**< 32-level Histogram Parameter 2 Register., offset: 0x2BA0 */
       uint8_t RESERVED_500[12];
  __IO uint32_t HIST32_PARAM3;                     /**< 32-level Histogram Parameter 3 Register., offset: 0x2BB0 */
       uint8_t RESERVED_501[12];
  __IO uint32_t HIST32_PARAM4;                     /**< 32-level Histogram Parameter 0 Register., offset: 0x2BC0 */
       uint8_t RESERVED_502[12];
  __IO uint32_t HIST32_PARAM5;                     /**< 32-level Histogram Parameter 1 Register., offset: 0x2BD0 */
       uint8_t RESERVED_503[12];
  __IO uint32_t HIST32_PARAM6;                     /**< 32-level Histogram Parameter 2 Register., offset: 0x2BE0 */
       uint8_t RESERVED_504[12];
  __IO uint32_t HIST32_PARAM7;                     /**< 32-level Histogram Parameter 3 Register., offset: 0x2BF0 */
       uint8_t RESERVED_505[12];
  __IO uint32_t COMP_CTRL;                         /**< offset: 0x2C00 */
  __IO uint32_t COMP_CTRL_SET;                     /**< offset: 0x2C04 */
  __IO uint32_t COMP_CTRL_CLR;                     /**< offset: 0x2C08 */
  __IO uint32_t COMP_CTRL_TOG;                     /**< offset: 0x2C0C */
  __IO uint32_t COMP_FORMAT0;                      /**< offset: 0x2C10 */
  __IO uint32_t COMP_FORMAT0_SET;                  /**< offset: 0x2C14 */
  __IO uint32_t COMP_FORMAT0_CLR;                  /**< offset: 0x2C18 */
  __IO uint32_t COMP_FORMAT0_TOG;                  /**< offset: 0x2C1C */
  __IO uint32_t COMP_FORMAT1;                      /**< offset: 0x2C20 */
       uint8_t RESERVED_506[12];
  __IO uint32_t COMP_FORMAT2;                      /**< offset: 0x2C30 */
       uint8_t RESERVED_507[12];
  __IO uint32_t COMP_MASK0;                        /**< offset: 0x2C40 */
       uint8_t RESERVED_508[12];
  __IO uint32_t COMP_MASK1;                        /**< offset: 0x2C50 */
       uint8_t RESERVED_509[12];
  __IO uint32_t COMP_BUFFER_SIZE;                  /**< offset: 0x2C60 */
       uint8_t RESERVED_510[12];
  __IO uint32_t COMP_SOURCE;                       /**< offset: 0x2C70 */
       uint8_t RESERVED_511[12];
  __IO uint32_t COMP_TARGET;                       /**< offset: 0x2C80 */
       uint8_t RESERVED_512[12];
  __IO uint32_t COMP_BUFFER_A;                     /**< offset: 0x2C90 */
       uint8_t RESERVED_513[12];
  __IO uint32_t COMP_BUFFER_B;                     /**< offset: 0x2CA0 */
       uint8_t RESERVED_514[12];
  __IO uint32_t COMP_BUFFER_C;                     /**< offset: 0x2CB0 */
       uint8_t RESERVED_515[12];
  __IO uint32_t COMP_BUFFER_D;                     /**< offset: 0x2CC0 */
       uint8_t RESERVED_516[12];
  __IO uint32_t COMP_DEBUG;                        /**< offset: 0x2CD0 */
       uint8_t RESERVED_517[12];
  __IO uint32_t BUS_MUX;                           /**< offset: 0x2CE0 */
       uint8_t RESERVED_518[12];
  __IO uint32_t HANDSHAKE_READY_MUX0;              /**< offset: 0x2CF0 */
       uint8_t RESERVED_519[12];
  __IO uint32_t HANDSHAKE_READY_MUX1;              /**< offset: 0x2D00 */
       uint8_t RESERVED_520[12];
  __IO uint32_t HANDSHAKE_DONE_MUX0;               /**< offset: 0x2D10 */
       uint8_t RESERVED_521[12];
  __IO uint32_t HANDSHAKE_DONE_MUX1;               /**< offset: 0x2D20 */
       uint8_t RESERVED_522[12];
  __IO uint32_t HANDSHAKE_CPU_FETCH;               /**< offset: 0x2D30 */
  __IO uint32_t HANDSHAKE_CPU_FETCH_SET;           /**< offset: 0x2D34 */
  __IO uint32_t HANDSHAKE_CPU_FETCH_CLR;           /**< offset: 0x2D38 */
  __IO uint32_t HANDSHAKE_CPU_FETCH_TOG;           /**< offset: 0x2D3C */
  __IO uint32_t HANDSHAKE_CPU_STORE;               /**< offset: 0x2D40 */
  __IO uint32_t HANDSHAKE_CPU_STORE_SET;           /**< offset: 0x2D44 */
  __IO uint32_t HANDSHAKE_CPU_STORE_CLR;           /**< offset: 0x2D48 */
  __IO uint32_t HANDSHAKE_CPU_STORE_TOG;           /**< offset: 0x2D4C */
  __IO uint32_t CFA_CTRL;                          /**< CFA RGB format control, offset: 0x2D50 */
  __IO uint32_t CFA_CTRL_SET;                      /**< CFA RGB format control, offset: 0x2D54 */
  __IO uint32_t CFA_CTRL_CLR;                      /**< CFA RGB format control, offset: 0x2D58 */
  __IO uint32_t CFA_CTRL_TOG;                      /**< CFA RGB format control, offset: 0x2D5C */
  __IO uint32_t CFA_SIZE;                          /**< CFA_SIZE, offset: 0x2D60 */
       uint8_t RESERVED_523[12];
  __IO uint32_t CFA_ARRAY0;                        /**< CFA_ARRAY0, offset: 0x2D70 */
       uint8_t RESERVED_524[12];
  __IO uint32_t CFA_ARRAY1;                        /**< CFA_ARRAY1, offset: 0x2D80 */
       uint8_t RESERVED_525[12];
  __IO uint32_t CFA_ARRAY2;                        /**< CFA_ARRAY2, offset: 0x2D90 */
       uint8_t RESERVED_526[12];
  __IO uint32_t CFA_ARRAY3;                        /**< CFA_ARRAY3, offset: 0x2DA0 */
       uint8_t RESERVED_527[12];
  __IO uint32_t CFA_ARRAY4;                        /**< CFA_ARRAY4, offset: 0x2DB0 */
       uint8_t RESERVED_528[12];
  __IO uint32_t CFA_ARRAY5;                        /**< CFA_ARRAY5, offset: 0x2DC0 */
       uint8_t RESERVED_529[12];
  __IO uint32_t CFA_ARRAY6;                        /**< CFA_ARRAY6, offset: 0x2DD0 */
       uint8_t RESERVED_530[12];
  __IO uint32_t CFA_ARRAY7;                        /**< CFA_ARRAY7, offset: 0x2DE0 */
       uint8_t RESERVED_531[12];
  __IO uint32_t CFA_ARRAY8;                        /**< CFA_ARRAY8, offset: 0x2DF0 */
       uint8_t RESERVED_532[12];
  __IO uint32_t CFA_ARRAY9;                        /**< CFA_ARRAY9, offset: 0x2E00 */
       uint8_t RESERVED_533[12];
  __IO uint32_t CFA_ARRAY10;                       /**< CFA_ARRAY10, offset: 0x2E10 */
       uint8_t RESERVED_534[12];
  __IO uint32_t CFA_ARRAY11;                       /**< CFA_ARRAY11, offset: 0x2E20 */
       uint8_t RESERVED_535[12];
  __IO uint32_t CFA_ARRAY12;                       /**< CFA_ARRAY12, offset: 0x2E30 */
       uint8_t RESERVED_536[12];
  __IO uint32_t CFA_ARRAY13;                       /**< CFA_ARRAY13, offset: 0x2E40 */
       uint8_t RESERVED_537[12];
  __IO uint32_t CFA_ARRAY14;                       /**< CFA_ARRAY14, offset: 0x2E50 */
       uint8_t RESERVED_538[12];
  __IO uint32_t CFA_ARRAY15;                       /**< CFA_ARRAY15, offset: 0x2E60 */
} PXP_Type;

/* ----------------------------------------------------------------------------
   -- PXP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PXP_Register_Masks PXP Register Masks
 * @{
 */

/*! @name CTRL - Control Register 0 */
/*! @{ */

#define PXP_CTRL_ENABLE_MASK                     (0x1U)
#define PXP_CTRL_ENABLE_SHIFT                    (0U)
/*! ENABLE - ENABLE */
#define PXP_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)

#define PXP_CTRL_IRQ_ENABLE_MASK                 (0x2U)
#define PXP_CTRL_IRQ_ENABLE_SHIFT                (1U)
/*! IRQ_ENABLE - IRQ_ENABLE */
#define PXP_CTRL_IRQ_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)

#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK            (0x4U)
#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT           (2U)
/*! NEXT_IRQ_ENABLE - NEXT_IRQ_ENABLE */
#define PXP_CTRL_NEXT_IRQ_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)

#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK         (0x8U)
#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT        (3U)
/*! LUT_DMA_IRQ_ENABLE - LUT_DMA_IRQ_ENABLE */
#define PXP_CTRL_LUT_DMA_IRQ_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK)

#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK      (0x10U)
#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT     (4U)
/*! ENABLE_LCD0_HANDSHAKE - ENABLE_LCD0_HANDSHAKE */
#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE(x)        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK)

#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK       (0x20U)
#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT      (5U)
/*! HANDSHAKE_ABORT_SKIP - HANDSHAKE_ABORT_SKIP */
#define PXP_CTRL_HANDSHAKE_ABORT_SKIP(x)         (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK)

#define PXP_CTRL_RSVD0_MASK                      (0xC0U)
#define PXP_CTRL_RSVD0_SHIFT                     (6U)
/*! RSVD0 - RSVD0 */
#define PXP_CTRL_RSVD0(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK)

#define PXP_CTRL_ROTATE0_MASK                    (0x300U)
#define PXP_CTRL_ROTATE0_SHIFT                   (8U)
/*! ROTATE0 - ROTATE0
 *  0b00..ROT_0 : rotate 0 degrees
 *  0b01..ROT_90 : rotate 90 degrees
 *  0b10..ROT_180 : rotate 180 degrees
 *  0b11..ROT_270 : rotate 270 degrees
 */
#define PXP_CTRL_ROTATE0(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE0_SHIFT)) & PXP_CTRL_ROTATE0_MASK)

#define PXP_CTRL_HFLIP0_MASK                     (0x400U)
#define PXP_CTRL_HFLIP0_SHIFT                    (10U)
/*! HFLIP0 - HFLIP0 */
#define PXP_CTRL_HFLIP0(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP0_SHIFT)) & PXP_CTRL_HFLIP0_MASK)

#define PXP_CTRL_VFLIP0_MASK                     (0x800U)
#define PXP_CTRL_VFLIP0_SHIFT                    (11U)
/*! VFLIP0 - VFLIP0 */
#define PXP_CTRL_VFLIP0(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP0_SHIFT)) & PXP_CTRL_VFLIP0_MASK)

#define PXP_CTRL_ROTATE1_MASK                    (0x3000U)
#define PXP_CTRL_ROTATE1_SHIFT                   (12U)
/*! ROTATE1 - ROTATE1
 *  0b00..ROT_0 : rotate 0 degrees
 *  0b01..ROT_90 : rotate 90 degrees
 *  0b10..ROT_180 : rotate 180 degrees
 *  0b11..ROT_270 : rotate 270 degrees
 */
#define PXP_CTRL_ROTATE1(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE1_SHIFT)) & PXP_CTRL_ROTATE1_MASK)

#define PXP_CTRL_HFLIP1_MASK                     (0x4000U)
#define PXP_CTRL_HFLIP1_SHIFT                    (14U)
/*! HFLIP1 - HFLIP1 */
#define PXP_CTRL_HFLIP1(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP1_SHIFT)) & PXP_CTRL_HFLIP1_MASK)

#define PXP_CTRL_VFLIP1_MASK                     (0x8000U)
#define PXP_CTRL_VFLIP1_SHIFT                    (15U)
/*! VFLIP1 - VFLIP1 */
#define PXP_CTRL_VFLIP1(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP1_SHIFT)) & PXP_CTRL_VFLIP1_MASK)

#define PXP_CTRL_ENABLE_PS_AS_OUT_MASK           (0x10000U)
#define PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT          (16U)
/*! ENABLE_PS_AS_OUT - ENABLE_PS_AS_OUT */
#define PXP_CTRL_ENABLE_PS_AS_OUT(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_ENABLE_PS_AS_OUT_MASK)

#define PXP_CTRL_ENABLE_DITHER_MASK              (0x20000U)
#define PXP_CTRL_ENABLE_DITHER_SHIFT             (17U)
/*! ENABLE_DITHER - ENABLE_DITHER */
#define PXP_CTRL_ENABLE_DITHER(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_DITHER_SHIFT)) & PXP_CTRL_ENABLE_DITHER_MASK)

#define PXP_CTRL_ENABLE_WFE_A_MASK               (0x40000U)
#define PXP_CTRL_ENABLE_WFE_A_SHIFT              (18U)
/*! ENABLE_WFE_A - ENABLE_WFE_A */
#define PXP_CTRL_ENABLE_WFE_A(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_WFE_A_SHIFT)) & PXP_CTRL_ENABLE_WFE_A_MASK)

#define PXP_CTRL_ENABLE_WFE_B_MASK               (0x80000U)
#define PXP_CTRL_ENABLE_WFE_B_SHIFT              (19U)
/*! ENABLE_WFE_B - ENABLE_WFE_B */
#define PXP_CTRL_ENABLE_WFE_B(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_ENABLE_WFE_B_MASK)

#define PXP_CTRL_ENABLE_INPUT_FETCH_STORE_MASK   (0x100000U)
#define PXP_CTRL_ENABLE_INPUT_FETCH_STORE_SHIFT  (20U)
/*! ENABLE_INPUT_FETCH_STORE - ENABLE_INPUT_FETCH_STORE */
#define PXP_CTRL_ENABLE_INPUT_FETCH_STORE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_INPUT_FETCH_STORE_SHIFT)) & PXP_CTRL_ENABLE_INPUT_FETCH_STORE_MASK)

#define PXP_CTRL_ENABLE_ALPHA_B_MASK             (0x200000U)
#define PXP_CTRL_ENABLE_ALPHA_B_SHIFT            (21U)
/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */
#define PXP_CTRL_ENABLE_ALPHA_B(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL_ENABLE_ALPHA_B_MASK)

#define PXP_CTRL_RSVD1_MASK                      (0x400000U)
#define PXP_CTRL_RSVD1_SHIFT                     (22U)
/*! RSVD1 - RSVD1 */
#define PXP_CTRL_RSVD1(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD1_SHIFT)) & PXP_CTRL_RSVD1_MASK)

#define PXP_CTRL_BLOCK_SIZE_MASK                 (0x800000U)
#define PXP_CTRL_BLOCK_SIZE_SHIFT                (23U)
/*! BLOCK_SIZE - BLOCK_SIZE
 *  0b0..BLK_SIZE_8X8 : Process 8x8 pixel blocks.
 *  0b1..BLK_SIZE_16X16 : Process 16x16 pixel blocks.
 */
#define PXP_CTRL_BLOCK_SIZE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)

#define PXP_CTRL_ENABLE_CSC2_MASK                (0x1000000U)
#define PXP_CTRL_ENABLE_CSC2_SHIFT               (24U)
/*! ENABLE_CSC2 - ENABLE_CSC2 */
#define PXP_CTRL_ENABLE_CSC2(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_CSC2_SHIFT)) & PXP_CTRL_ENABLE_CSC2_MASK)

#define PXP_CTRL_ENABLE_LUT_MASK                 (0x2000000U)
#define PXP_CTRL_ENABLE_LUT_SHIFT                (25U)
/*! ENABLE_LUT - ENABLE_LUT */
#define PXP_CTRL_ENABLE_LUT(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LUT_SHIFT)) & PXP_CTRL_ENABLE_LUT_MASK)

#define PXP_CTRL_ENABLE_ROTATE0_MASK             (0x4000000U)
#define PXP_CTRL_ENABLE_ROTATE0_SHIFT            (26U)
/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */
#define PXP_CTRL_ENABLE_ROTATE0(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_ENABLE_ROTATE0_MASK)

#define PXP_CTRL_ENABLE_ROTATE1_MASK             (0x8000000U)
#define PXP_CTRL_ENABLE_ROTATE1_SHIFT            (27U)
/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */
#define PXP_CTRL_ENABLE_ROTATE1(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_ENABLE_ROTATE1_MASK)

#define PXP_CTRL_RSVD2_MASK                      (0x10000000U)
#define PXP_CTRL_RSVD2_SHIFT                     (28U)
/*! RSVD2 - RSVD2 */
#define PXP_CTRL_RSVD2(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD2_SHIFT)) & PXP_CTRL_RSVD2_MASK)

#define PXP_CTRL_RSVD4_MASK                      (0x20000000U)
#define PXP_CTRL_RSVD4_SHIFT                     (29U)
/*! RSVD4 - RSVD4 */
#define PXP_CTRL_RSVD4(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD4_SHIFT)) & PXP_CTRL_RSVD4_MASK)

#define PXP_CTRL_CLKGATE_MASK                    (0x40000000U)
#define PXP_CTRL_CLKGATE_SHIFT                   (30U)
/*! CLKGATE - CLKGATE */
#define PXP_CTRL_CLKGATE(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)

#define PXP_CTRL_SFTRST_MASK                     (0x80000000U)
#define PXP_CTRL_SFTRST_SHIFT                    (31U)
/*! SFTRST - SFTRST */
#define PXP_CTRL_SFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)
/*! @} */

/*! @name CTRL_SET - Control Register 0 */
/*! @{ */

#define PXP_CTRL_SET_ENABLE_MASK                 (0x1U)
#define PXP_CTRL_SET_ENABLE_SHIFT                (0U)
/*! ENABLE - ENABLE */
#define PXP_CTRL_SET_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)

#define PXP_CTRL_SET_IRQ_ENABLE_MASK             (0x2U)
#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT            (1U)
/*! IRQ_ENABLE - IRQ_ENABLE */
#define PXP_CTRL_SET_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)

#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK        (0x4U)
#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT       (2U)
/*! NEXT_IRQ_ENABLE - NEXT_IRQ_ENABLE */
#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)

#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_MASK     (0x8U)
#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_SHIFT    (3U)
/*! LUT_DMA_IRQ_ENABLE - LUT_DMA_IRQ_ENABLE */
#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_MASK)

#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_MASK  (0x10U)
#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_SHIFT (4U)
/*! ENABLE_LCD0_HANDSHAKE - ENABLE_LCD0_HANDSHAKE */
#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_MASK)

#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_MASK   (0x20U)
#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_SHIFT  (5U)
/*! HANDSHAKE_ABORT_SKIP - HANDSHAKE_ABORT_SKIP */
#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_MASK)

#define PXP_CTRL_SET_RSVD0_MASK                  (0xC0U)
#define PXP_CTRL_SET_RSVD0_SHIFT                 (6U)
/*! RSVD0 - RSVD0 */
#define PXP_CTRL_SET_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK)

#define PXP_CTRL_SET_ROTATE0_MASK                (0x300U)
#define PXP_CTRL_SET_ROTATE0_SHIFT               (8U)
/*! ROTATE0 - ROTATE0 */
#define PXP_CTRL_SET_ROTATE0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE0_SHIFT)) & PXP_CTRL_SET_ROTATE0_MASK)

#define PXP_CTRL_SET_HFLIP0_MASK                 (0x400U)
#define PXP_CTRL_SET_HFLIP0_SHIFT                (10U)
/*! HFLIP0 - HFLIP0 */
#define PXP_CTRL_SET_HFLIP0(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP0_SHIFT)) & PXP_CTRL_SET_HFLIP0_MASK)

#define PXP_CTRL_SET_VFLIP0_MASK                 (0x800U)
#define PXP_CTRL_SET_VFLIP0_SHIFT                (11U)
/*! VFLIP0 - VFLIP0 */
#define PXP_CTRL_SET_VFLIP0(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP0_SHIFT)) & PXP_CTRL_SET_VFLIP0_MASK)

#define PXP_CTRL_SET_ROTATE1_MASK                (0x3000U)
#define PXP_CTRL_SET_ROTATE1_SHIFT               (12U)
/*! ROTATE1 - ROTATE1 */
#define PXP_CTRL_SET_ROTATE1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE1_SHIFT)) & PXP_CTRL_SET_ROTATE1_MASK)

#define PXP_CTRL_SET_HFLIP1_MASK                 (0x4000U)
#define PXP_CTRL_SET_HFLIP1_SHIFT                (14U)
/*! HFLIP1 - HFLIP1 */
#define PXP_CTRL_SET_HFLIP1(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP1_SHIFT)) & PXP_CTRL_SET_HFLIP1_MASK)

#define PXP_CTRL_SET_VFLIP1_MASK                 (0x8000U)
#define PXP_CTRL_SET_VFLIP1_SHIFT                (15U)
/*! VFLIP1 - VFLIP1 */
#define PXP_CTRL_SET_VFLIP1(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP1_SHIFT)) & PXP_CTRL_SET_VFLIP1_MASK)

#define PXP_CTRL_SET_ENABLE_PS_AS_OUT_MASK       (0x10000U)
#define PXP_CTRL_SET_ENABLE_PS_AS_OUT_SHIFT      (16U)
/*! ENABLE_PS_AS_OUT - ENABLE_PS_AS_OUT */
#define PXP_CTRL_SET_ENABLE_PS_AS_OUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_SET_ENABLE_PS_AS_OUT_MASK)

#define PXP_CTRL_SET_ENABLE_DITHER_MASK          (0x20000U)
#define PXP_CTRL_SET_ENABLE_DITHER_SHIFT         (17U)
/*! ENABLE_DITHER - ENABLE_DITHER */
#define PXP_CTRL_SET_ENABLE_DITHER(x)            (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_DITHER_SHIFT)) & PXP_CTRL_SET_ENABLE_DITHER_MASK)

#define PXP_CTRL_SET_ENABLE_WFE_A_MASK           (0x40000U)
#define PXP_CTRL_SET_ENABLE_WFE_A_SHIFT          (18U)
/*! ENABLE_WFE_A - ENABLE_WFE_A */
#define PXP_CTRL_SET_ENABLE_WFE_A(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_WFE_A_SHIFT)) & PXP_CTRL_SET_ENABLE_WFE_A_MASK)

#define PXP_CTRL_SET_ENABLE_WFE_B_MASK           (0x80000U)
#define PXP_CTRL_SET_ENABLE_WFE_B_SHIFT          (19U)
/*! ENABLE_WFE_B - ENABLE_WFE_B */
#define PXP_CTRL_SET_ENABLE_WFE_B(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_SET_ENABLE_WFE_B_MASK)

#define PXP_CTRL_SET_ENABLE_INPUT_FETCH_STORE_MASK (0x100000U)
#define PXP_CTRL_SET_ENABLE_INPUT_FETCH_STORE_SHIFT (20U)
/*! ENABLE_INPUT_FETCH_STORE - ENABLE_INPUT_FETCH_STORE */
#define PXP_CTRL_SET_ENABLE_INPUT_FETCH_STORE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_INPUT_FETCH_STORE_SHIFT)) & PXP_CTRL_SET_ENABLE_INPUT_FETCH_STORE_MASK)

#define PXP_CTRL_SET_ENABLE_ALPHA_B_MASK         (0x200000U)
#define PXP_CTRL_SET_ENABLE_ALPHA_B_SHIFT        (21U)
/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */
#define PXP_CTRL_SET_ENABLE_ALPHA_B(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL_SET_ENABLE_ALPHA_B_MASK)

#define PXP_CTRL_SET_RSVD1_MASK                  (0x400000U)
#define PXP_CTRL_SET_RSVD1_SHIFT                 (22U)
/*! RSVD1 - RSVD1 */
#define PXP_CTRL_SET_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD1_SHIFT)) & PXP_CTRL_SET_RSVD1_MASK)

#define PXP_CTRL_SET_BLOCK_SIZE_MASK             (0x800000U)
#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT            (23U)
/*! BLOCK_SIZE - BLOCK_SIZE */
#define PXP_CTRL_SET_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)

#define PXP_CTRL_SET_ENABLE_CSC2_MASK            (0x1000000U)
#define PXP_CTRL_SET_ENABLE_CSC2_SHIFT           (24U)
/*! ENABLE_CSC2 - ENABLE_CSC2 */
#define PXP_CTRL_SET_ENABLE_CSC2(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_CSC2_SHIFT)) & PXP_CTRL_SET_ENABLE_CSC2_MASK)

#define PXP_CTRL_SET_ENABLE_LUT_MASK             (0x2000000U)
#define PXP_CTRL_SET_ENABLE_LUT_SHIFT            (25U)
/*! ENABLE_LUT - ENABLE_LUT */
#define PXP_CTRL_SET_ENABLE_LUT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LUT_SHIFT)) & PXP_CTRL_SET_ENABLE_LUT_MASK)

#define PXP_CTRL_SET_ENABLE_ROTATE0_MASK         (0x4000000U)
#define PXP_CTRL_SET_ENABLE_ROTATE0_SHIFT        (26U)
/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */
#define PXP_CTRL_SET_ENABLE_ROTATE0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_SET_ENABLE_ROTATE0_MASK)

#define PXP_CTRL_SET_ENABLE_ROTATE1_MASK         (0x8000000U)
#define PXP_CTRL_SET_ENABLE_ROTATE1_SHIFT        (27U)
/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */
#define PXP_CTRL_SET_ENABLE_ROTATE1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_SET_ENABLE_ROTATE1_MASK)

#define PXP_CTRL_SET_RSVD2_MASK                  (0x10000000U)
#define PXP_CTRL_SET_RSVD2_SHIFT                 (28U)
/*! RSVD2 - RSVD2 */
#define PXP_CTRL_SET_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD2_SHIFT)) & PXP_CTRL_SET_RSVD2_MASK)

#define PXP_CTRL_SET_RSVD4_MASK                  (0x20000000U)
#define PXP_CTRL_SET_RSVD4_SHIFT                 (29U)
/*! RSVD4 - RSVD4 */
#define PXP_CTRL_SET_RSVD4(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD4_SHIFT)) & PXP_CTRL_SET_RSVD4_MASK)

#define PXP_CTRL_SET_CLKGATE_MASK                (0x40000000U)
#define PXP_CTRL_SET_CLKGATE_SHIFT               (30U)
/*! CLKGATE - CLKGATE */
#define PXP_CTRL_SET_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)

#define PXP_CTRL_SET_SFTRST_MASK                 (0x80000000U)
#define PXP_CTRL_SET_SFTRST_SHIFT                (31U)
/*! SFTRST - SFTRST */
#define PXP_CTRL_SET_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)
/*! @} */

/*! @name CTRL_CLR - Control Register 0 */
/*! @{ */

#define PXP_CTRL_CLR_ENABLE_MASK                 (0x1U)
#define PXP_CTRL_CLR_ENABLE_SHIFT                (0U)
/*! ENABLE - ENABLE */
#define PXP_CTRL_CLR_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)

#define PXP_CTRL_CLR_IRQ_ENABLE_MASK             (0x2U)
#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT            (1U)
/*! IRQ_ENABLE - IRQ_ENABLE */
#define PXP_CTRL_CLR_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)

#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK        (0x4U)
#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT       (2U)
/*! NEXT_IRQ_ENABLE - NEXT_IRQ_ENABLE */
#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)

#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_MASK     (0x8U)
#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_SHIFT    (3U)
/*! LUT_DMA_IRQ_ENABLE - LUT_DMA_IRQ_ENABLE */
#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_MASK)

#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_MASK  (0x10U)
#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_SHIFT (4U)
/*! ENABLE_LCD0_HANDSHAKE - ENABLE_LCD0_HANDSHAKE */
#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_MASK)

#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_MASK   (0x20U)
#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_SHIFT  (5U)
/*! HANDSHAKE_ABORT_SKIP - HANDSHAKE_ABORT_SKIP */
#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_MASK)

#define PXP_CTRL_CLR_RSVD0_MASK                  (0xC0U)
#define PXP_CTRL_CLR_RSVD0_SHIFT                 (6U)
/*! RSVD0 - RSVD0 */
#define PXP_CTRL_CLR_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK)

#define PXP_CTRL_CLR_ROTATE0_MASK                (0x300U)
#define PXP_CTRL_CLR_ROTATE0_SHIFT               (8U)
/*! ROTATE0 - ROTATE0 */
#define PXP_CTRL_CLR_ROTATE0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE0_SHIFT)) & PXP_CTRL_CLR_ROTATE0_MASK)

#define PXP_CTRL_CLR_HFLIP0_MASK                 (0x400U)
#define PXP_CTRL_CLR_HFLIP0_SHIFT                (10U)
/*! HFLIP0 - HFLIP0 */
#define PXP_CTRL_CLR_HFLIP0(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP0_SHIFT)) & PXP_CTRL_CLR_HFLIP0_MASK)

#define PXP_CTRL_CLR_VFLIP0_MASK                 (0x800U)
#define PXP_CTRL_CLR_VFLIP0_SHIFT                (11U)
/*! VFLIP0 - VFLIP0 */
#define PXP_CTRL_CLR_VFLIP0(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP0_SHIFT)) & PXP_CTRL_CLR_VFLIP0_MASK)

#define PXP_CTRL_CLR_ROTATE1_MASK                (0x3000U)
#define PXP_CTRL_CLR_ROTATE1_SHIFT               (12U)
/*! ROTATE1 - ROTATE1 */
#define PXP_CTRL_CLR_ROTATE1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE1_SHIFT)) & PXP_CTRL_CLR_ROTATE1_MASK)

#define PXP_CTRL_CLR_HFLIP1_MASK                 (0x4000U)
#define PXP_CTRL_CLR_HFLIP1_SHIFT                (14U)
/*! HFLIP1 - HFLIP1 */
#define PXP_CTRL_CLR_HFLIP1(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP1_SHIFT)) & PXP_CTRL_CLR_HFLIP1_MASK)

#define PXP_CTRL_CLR_VFLIP1_MASK                 (0x8000U)
#define PXP_CTRL_CLR_VFLIP1_SHIFT                (15U)
/*! VFLIP1 - VFLIP1 */
#define PXP_CTRL_CLR_VFLIP1(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP1_SHIFT)) & PXP_CTRL_CLR_VFLIP1_MASK)

#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT_MASK       (0x10000U)
#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT_SHIFT      (16U)
/*! ENABLE_PS_AS_OUT - ENABLE_PS_AS_OUT */
#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_CLR_ENABLE_PS_AS_OUT_MASK)

#define PXP_CTRL_CLR_ENABLE_DITHER_MASK          (0x20000U)
#define PXP_CTRL_CLR_ENABLE_DITHER_SHIFT         (17U)
/*! ENABLE_DITHER - ENABLE_DITHER */
#define PXP_CTRL_CLR_ENABLE_DITHER(x)            (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_DITHER_SHIFT)) & PXP_CTRL_CLR_ENABLE_DITHER_MASK)

#define PXP_CTRL_CLR_ENABLE_WFE_A_MASK           (0x40000U)
#define PXP_CTRL_CLR_ENABLE_WFE_A_SHIFT          (18U)
/*! ENABLE_WFE_A - ENABLE_WFE_A */
#define PXP_CTRL_CLR_ENABLE_WFE_A(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_WFE_A_SHIFT)) & PXP_CTRL_CLR_ENABLE_WFE_A_MASK)

#define PXP_CTRL_CLR_ENABLE_WFE_B_MASK           (0x80000U)
#define PXP_CTRL_CLR_ENABLE_WFE_B_SHIFT          (19U)
/*! ENABLE_WFE_B - ENABLE_WFE_B */
#define PXP_CTRL_CLR_ENABLE_WFE_B(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_CLR_ENABLE_WFE_B_MASK)

#define PXP_CTRL_CLR_ENABLE_INPUT_FETCH_STORE_MASK (0x100000U)
#define PXP_CTRL_CLR_ENABLE_INPUT_FETCH_STORE_SHIFT (20U)
/*! ENABLE_INPUT_FETCH_STORE - ENABLE_INPUT_FETCH_STORE */
#define PXP_CTRL_CLR_ENABLE_INPUT_FETCH_STORE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_INPUT_FETCH_STORE_SHIFT)) & PXP_CTRL_CLR_ENABLE_INPUT_FETCH_STORE_MASK)

#define PXP_CTRL_CLR_ENABLE_ALPHA_B_MASK         (0x200000U)
#define PXP_CTRL_CLR_ENABLE_ALPHA_B_SHIFT        (21U)
/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */
#define PXP_CTRL_CLR_ENABLE_ALPHA_B(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL_CLR_ENABLE_ALPHA_B_MASK)

#define PXP_CTRL_CLR_RSVD1_MASK                  (0x400000U)
#define PXP_CTRL_CLR_RSVD1_SHIFT                 (22U)
/*! RSVD1 - RSVD1 */
#define PXP_CTRL_CLR_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD1_SHIFT)) & PXP_CTRL_CLR_RSVD1_MASK)

#define PXP_CTRL_CLR_BLOCK_SIZE_MASK             (0x800000U)
#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT            (23U)
/*! BLOCK_SIZE - BLOCK_SIZE */
#define PXP_CTRL_CLR_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)

#define PXP_CTRL_CLR_ENABLE_CSC2_MASK            (0x1000000U)
#define PXP_CTRL_CLR_ENABLE_CSC2_SHIFT           (24U)
/*! ENABLE_CSC2 - ENABLE_CSC2 */
#define PXP_CTRL_CLR_ENABLE_CSC2(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_CSC2_SHIFT)) & PXP_CTRL_CLR_ENABLE_CSC2_MASK)

#define PXP_CTRL_CLR_ENABLE_LUT_MASK             (0x2000000U)
#define PXP_CTRL_CLR_ENABLE_LUT_SHIFT            (25U)
/*! ENABLE_LUT - ENABLE_LUT */
#define PXP_CTRL_CLR_ENABLE_LUT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LUT_SHIFT)) & PXP_CTRL_CLR_ENABLE_LUT_MASK)

#define PXP_CTRL_CLR_ENABLE_ROTATE0_MASK         (0x4000000U)
#define PXP_CTRL_CLR_ENABLE_ROTATE0_SHIFT        (26U)
/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */
#define PXP_CTRL_CLR_ENABLE_ROTATE0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_CLR_ENABLE_ROTATE0_MASK)

#define PXP_CTRL_CLR_ENABLE_ROTATE1_MASK         (0x8000000U)
#define PXP_CTRL_CLR_ENABLE_ROTATE1_SHIFT        (27U)
/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */
#define PXP_CTRL_CLR_ENABLE_ROTATE1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_CLR_ENABLE_ROTATE1_MASK)

#define PXP_CTRL_CLR_RSVD2_MASK                  (0x10000000U)
#define PXP_CTRL_CLR_RSVD2_SHIFT                 (28U)
/*! RSVD2 - RSVD2 */
#define PXP_CTRL_CLR_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD2_SHIFT)) & PXP_CTRL_CLR_RSVD2_MASK)

#define PXP_CTRL_CLR_RSVD4_MASK                  (0x20000000U)
#define PXP_CTRL_CLR_RSVD4_SHIFT                 (29U)
/*! RSVD4 - RSVD4 */
#define PXP_CTRL_CLR_RSVD4(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD4_SHIFT)) & PXP_CTRL_CLR_RSVD4_MASK)

#define PXP_CTRL_CLR_CLKGATE_MASK                (0x40000000U)
#define PXP_CTRL_CLR_CLKGATE_SHIFT               (30U)
/*! CLKGATE - CLKGATE */
#define PXP_CTRL_CLR_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)

#define PXP_CTRL_CLR_SFTRST_MASK                 (0x80000000U)
#define PXP_CTRL_CLR_SFTRST_SHIFT                (31U)
/*! SFTRST - SFTRST */
#define PXP_CTRL_CLR_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)
/*! @} */

/*! @name CTRL_TOG - Control Register 0 */
/*! @{ */

#define PXP_CTRL_TOG_ENABLE_MASK                 (0x1U)
#define PXP_CTRL_TOG_ENABLE_SHIFT                (0U)
/*! ENABLE - ENABLE */
#define PXP_CTRL_TOG_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)

#define PXP_CTRL_TOG_IRQ_ENABLE_MASK             (0x2U)
#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT            (1U)
/*! IRQ_ENABLE - IRQ_ENABLE */
#define PXP_CTRL_TOG_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)

#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK        (0x4U)
#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT       (2U)
/*! NEXT_IRQ_ENABLE - NEXT_IRQ_ENABLE */
#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)

#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_MASK     (0x8U)
#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_SHIFT    (3U)
/*! LUT_DMA_IRQ_ENABLE - LUT_DMA_IRQ_ENABLE */
#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_MASK)

#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_MASK  (0x10U)
#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_SHIFT (4U)
/*! ENABLE_LCD0_HANDSHAKE - ENABLE_LCD0_HANDSHAKE */
#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_MASK)

#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_MASK   (0x20U)
#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_SHIFT  (5U)
/*! HANDSHAKE_ABORT_SKIP - HANDSHAKE_ABORT_SKIP */
#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_MASK)

#define PXP_CTRL_TOG_RSVD0_MASK                  (0xC0U)
#define PXP_CTRL_TOG_RSVD0_SHIFT                 (6U)
/*! RSVD0 - RSVD0 */
#define PXP_CTRL_TOG_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK)

#define PXP_CTRL_TOG_ROTATE0_MASK                (0x300U)
#define PXP_CTRL_TOG_ROTATE0_SHIFT               (8U)
/*! ROTATE0 - ROTATE0 */
#define PXP_CTRL_TOG_ROTATE0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE0_SHIFT)) & PXP_CTRL_TOG_ROTATE0_MASK)

#define PXP_CTRL_TOG_HFLIP0_MASK                 (0x400U)
#define PXP_CTRL_TOG_HFLIP0_SHIFT                (10U)
/*! HFLIP0 - HFLIP0 */
#define PXP_CTRL_TOG_HFLIP0(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP0_SHIFT)) & PXP_CTRL_TOG_HFLIP0_MASK)

#define PXP_CTRL_TOG_VFLIP0_MASK                 (0x800U)
#define PXP_CTRL_TOG_VFLIP0_SHIFT                (11U)
/*! VFLIP0 - VFLIP0 */
#define PXP_CTRL_TOG_VFLIP0(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP0_SHIFT)) & PXP_CTRL_TOG_VFLIP0_MASK)

#define PXP_CTRL_TOG_ROTATE1_MASK                (0x3000U)
#define PXP_CTRL_TOG_ROTATE1_SHIFT               (12U)
/*! ROTATE1 - ROTATE1 */
#define PXP_CTRL_TOG_ROTATE1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE1_SHIFT)) & PXP_CTRL_TOG_ROTATE1_MASK)

#define PXP_CTRL_TOG_HFLIP1_MASK                 (0x4000U)
#define PXP_CTRL_TOG_HFLIP1_SHIFT                (14U)
/*! HFLIP1 - HFLIP1 */
#define PXP_CTRL_TOG_HFLIP1(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP1_SHIFT)) & PXP_CTRL_TOG_HFLIP1_MASK)

#define PXP_CTRL_TOG_VFLIP1_MASK                 (0x8000U)
#define PXP_CTRL_TOG_VFLIP1_SHIFT                (15U)
/*! VFLIP1 - VFLIP1 */
#define PXP_CTRL_TOG_VFLIP1(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP1_SHIFT)) & PXP_CTRL_TOG_VFLIP1_MASK)

#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT_MASK       (0x10000U)
#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT_SHIFT      (16U)
/*! ENABLE_PS_AS_OUT - ENABLE_PS_AS_OUT */
#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_TOG_ENABLE_PS_AS_OUT_MASK)

#define PXP_CTRL_TOG_ENABLE_DITHER_MASK          (0x20000U)
#define PXP_CTRL_TOG_ENABLE_DITHER_SHIFT         (17U)
/*! ENABLE_DITHER - ENABLE_DITHER */
#define PXP_CTRL_TOG_ENABLE_DITHER(x)            (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_DITHER_SHIFT)) & PXP_CTRL_TOG_ENABLE_DITHER_MASK)

#define PXP_CTRL_TOG_ENABLE_WFE_A_MASK           (0x40000U)
#define PXP_CTRL_TOG_ENABLE_WFE_A_SHIFT          (18U)
/*! ENABLE_WFE_A - ENABLE_WFE_A */
#define PXP_CTRL_TOG_ENABLE_WFE_A(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_WFE_A_SHIFT)) & PXP_CTRL_TOG_ENABLE_WFE_A_MASK)

#define PXP_CTRL_TOG_ENABLE_WFE_B_MASK           (0x80000U)
#define PXP_CTRL_TOG_ENABLE_WFE_B_SHIFT          (19U)
/*! ENABLE_WFE_B - ENABLE_WFE_B */
#define PXP_CTRL_TOG_ENABLE_WFE_B(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_TOG_ENABLE_WFE_B_MASK)

#define PXP_CTRL_TOG_ENABLE_INPUT_FETCH_STORE_MASK (0x100000U)
#define PXP_CTRL_TOG_ENABLE_INPUT_FETCH_STORE_SHIFT (20U)
/*! ENABLE_INPUT_FETCH_STORE - ENABLE_INPUT_FETCH_STORE */
#define PXP_CTRL_TOG_ENABLE_INPUT_FETCH_STORE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_INPUT_FETCH_STORE_SHIFT)) & PXP_CTRL_TOG_ENABLE_INPUT_FETCH_STORE_MASK)

#define PXP_CTRL_TOG_ENABLE_ALPHA_B_MASK         (0x200000U)
#define PXP_CTRL_TOG_ENABLE_ALPHA_B_SHIFT        (21U)
/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */
#define PXP_CTRL_TOG_ENABLE_ALPHA_B(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL_TOG_ENABLE_ALPHA_B_MASK)

#define PXP_CTRL_TOG_RSVD1_MASK                  (0x400000U)
#define PXP_CTRL_TOG_RSVD1_SHIFT                 (22U)
/*! RSVD1 - RSVD1 */
#define PXP_CTRL_TOG_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD1_SHIFT)) & PXP_CTRL_TOG_RSVD1_MASK)

#define PXP_CTRL_TOG_BLOCK_SIZE_MASK             (0x800000U)
#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT            (23U)
/*! BLOCK_SIZE - BLOCK_SIZE */
#define PXP_CTRL_TOG_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)

#define PXP_CTRL_TOG_ENABLE_CSC2_MASK            (0x1000000U)
#define PXP_CTRL_TOG_ENABLE_CSC2_SHIFT           (24U)
/*! ENABLE_CSC2 - ENABLE_CSC2 */
#define PXP_CTRL_TOG_ENABLE_CSC2(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_CSC2_SHIFT)) & PXP_CTRL_TOG_ENABLE_CSC2_MASK)

#define PXP_CTRL_TOG_ENABLE_LUT_MASK             (0x2000000U)
#define PXP_CTRL_TOG_ENABLE_LUT_SHIFT            (25U)
/*! ENABLE_LUT - ENABLE_LUT */
#define PXP_CTRL_TOG_ENABLE_LUT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LUT_SHIFT)) & PXP_CTRL_TOG_ENABLE_LUT_MASK)

#define PXP_CTRL_TOG_ENABLE_ROTATE0_MASK         (0x4000000U)
#define PXP_CTRL_TOG_ENABLE_ROTATE0_SHIFT        (26U)
/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */
#define PXP_CTRL_TOG_ENABLE_ROTATE0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_TOG_ENABLE_ROTATE0_MASK)

#define PXP_CTRL_TOG_ENABLE_ROTATE1_MASK         (0x8000000U)
#define PXP_CTRL_TOG_ENABLE_ROTATE1_SHIFT        (27U)
/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */
#define PXP_CTRL_TOG_ENABLE_ROTATE1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_TOG_ENABLE_ROTATE1_MASK)

#define PXP_CTRL_TOG_RSVD2_MASK                  (0x10000000U)
#define PXP_CTRL_TOG_RSVD2_SHIFT                 (28U)
/*! RSVD2 - RSVD2 */
#define PXP_CTRL_TOG_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD2_SHIFT)) & PXP_CTRL_TOG_RSVD2_MASK)

#define PXP_CTRL_TOG_RSVD4_MASK                  (0x20000000U)
#define PXP_CTRL_TOG_RSVD4_SHIFT                 (29U)
/*! RSVD4 - RSVD4 */
#define PXP_CTRL_TOG_RSVD4(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD4_SHIFT)) & PXP_CTRL_TOG_RSVD4_MASK)

#define PXP_CTRL_TOG_CLKGATE_MASK                (0x40000000U)
#define PXP_CTRL_TOG_CLKGATE_SHIFT               (30U)
/*! CLKGATE - CLKGATE */
#define PXP_CTRL_TOG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)

#define PXP_CTRL_TOG_SFTRST_MASK                 (0x80000000U)
#define PXP_CTRL_TOG_SFTRST_SHIFT                (31U)
/*! SFTRST - SFTRST */
#define PXP_CTRL_TOG_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)
/*! @} */

/*! @name STAT - Status Register */
/*! @{ */

#define PXP_STAT_IRQ0_MASK                       (0x1U)
#define PXP_STAT_IRQ0_SHIFT                      (0U)
/*! IRQ0 - IRQ0 */
#define PXP_STAT_IRQ0(x)                         (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ0_SHIFT)) & PXP_STAT_IRQ0_MASK)

#define PXP_STAT_AXI_WRITE_ERROR_0_MASK          (0x2U)
#define PXP_STAT_AXI_WRITE_ERROR_0_SHIFT         (1U)
/*! AXI_WRITE_ERROR_0 - AXI_WRITE_ERROR_0 */
#define PXP_STAT_AXI_WRITE_ERROR_0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_0_MASK)

#define PXP_STAT_AXI_READ_ERROR_0_MASK           (0x4U)
#define PXP_STAT_AXI_READ_ERROR_0_SHIFT          (2U)
/*! AXI_READ_ERROR_0 - AXI_READ_ERROR_0 */
#define PXP_STAT_AXI_READ_ERROR_0(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_AXI_READ_ERROR_0_MASK)

#define PXP_STAT_NEXT_IRQ_MASK                   (0x8U)
#define PXP_STAT_NEXT_IRQ_SHIFT                  (3U)
/*! NEXT_IRQ - NEXT_IRQ */
#define PXP_STAT_NEXT_IRQ(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)

#define PXP_STAT_AXI_ERROR_ID_0_MASK             (0xF0U)
#define PXP_STAT_AXI_ERROR_ID_0_SHIFT            (4U)
/*! AXI_ERROR_ID_0 - AXI_ERROR_ID_0 */
#define PXP_STAT_AXI_ERROR_ID_0(x)               (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_AXI_ERROR_ID_0_MASK)

#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK      (0x100U)
#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT     (8U)
/*! LUT_DMA_LOAD_DONE_IRQ - LUT_DMA_LOAD_DONE_IRQ */
#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define PXP_STAT_AXI_WRITE_ERROR_1_MASK          (0x200U)
#define PXP_STAT_AXI_WRITE_ERROR_1_SHIFT         (9U)
/*! AXI_WRITE_ERROR_1 - AXI_WRITE_ERROR_1 */
#define PXP_STAT_AXI_WRITE_ERROR_1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_1_MASK)

#define PXP_STAT_AXI_READ_ERROR_1_MASK           (0x400U)
#define PXP_STAT_AXI_READ_ERROR_1_SHIFT          (10U)
/*! AXI_READ_ERROR_1 - AXI_READ_ERROR_1 */
#define PXP_STAT_AXI_READ_ERROR_1(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_AXI_READ_ERROR_1_MASK)

#define PXP_STAT_RSVD2_MASK                      (0x800U)
#define PXP_STAT_RSVD2_SHIFT                     (11U)
/*! RSVD2 - RSVD2 */
#define PXP_STAT_RSVD2(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_STAT_RSVD2_SHIFT)) & PXP_STAT_RSVD2_MASK)

#define PXP_STAT_AXI_ERROR_ID_1_MASK             (0xF000U)
#define PXP_STAT_AXI_ERROR_ID_1_SHIFT            (12U)
/*! AXI_ERROR_ID_1 - AXI_ERROR_ID_1 */
#define PXP_STAT_AXI_ERROR_ID_1(x)               (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_AXI_ERROR_ID_1_MASK)

#define PXP_STAT_BLOCKY_MASK                     (0xFF0000U)
#define PXP_STAT_BLOCKY_SHIFT                    (16U)
/*! BLOCKY - BLOCKY */
#define PXP_STAT_BLOCKY(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)

#define PXP_STAT_BLOCKX_MASK                     (0xFF000000U)
#define PXP_STAT_BLOCKX_SHIFT                    (24U)
/*! BLOCKX - BLOCKX */
#define PXP_STAT_BLOCKX(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)
/*! @} */

/*! @name STAT_SET - Status Register */
/*! @{ */

#define PXP_STAT_SET_IRQ0_MASK                   (0x1U)
#define PXP_STAT_SET_IRQ0_SHIFT                  (0U)
/*! IRQ0 - IRQ0 */
#define PXP_STAT_SET_IRQ0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ0_SHIFT)) & PXP_STAT_SET_IRQ0_MASK)

#define PXP_STAT_SET_AXI_WRITE_ERROR_0_MASK      (0x2U)
#define PXP_STAT_SET_AXI_WRITE_ERROR_0_SHIFT     (1U)
/*! AXI_WRITE_ERROR_0 - AXI_WRITE_ERROR_0 */
#define PXP_STAT_SET_AXI_WRITE_ERROR_0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_0_MASK)

#define PXP_STAT_SET_AXI_READ_ERROR_0_MASK       (0x4U)
#define PXP_STAT_SET_AXI_READ_ERROR_0_SHIFT      (2U)
/*! AXI_READ_ERROR_0 - AXI_READ_ERROR_0 */
#define PXP_STAT_SET_AXI_READ_ERROR_0(x)         (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_0_MASK)

#define PXP_STAT_SET_NEXT_IRQ_MASK               (0x8U)
#define PXP_STAT_SET_NEXT_IRQ_SHIFT              (3U)
/*! NEXT_IRQ - NEXT_IRQ */
#define PXP_STAT_SET_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)

#define PXP_STAT_SET_AXI_ERROR_ID_0_MASK         (0xF0U)
#define PXP_STAT_SET_AXI_ERROR_ID_0_SHIFT        (4U)
/*! AXI_ERROR_ID_0 - AXI_ERROR_ID_0 */
#define PXP_STAT_SET_AXI_ERROR_ID_0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_0_MASK)

#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
/*! LUT_DMA_LOAD_DONE_IRQ - LUT_DMA_LOAD_DONE_IRQ */
#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define PXP_STAT_SET_AXI_WRITE_ERROR_1_MASK      (0x200U)
#define PXP_STAT_SET_AXI_WRITE_ERROR_1_SHIFT     (9U)
/*! AXI_WRITE_ERROR_1 - AXI_WRITE_ERROR_1 */
#define PXP_STAT_SET_AXI_WRITE_ERROR_1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_1_MASK)

#define PXP_STAT_SET_AXI_READ_ERROR_1_MASK       (0x400U)
#define PXP_STAT_SET_AXI_READ_ERROR_1_SHIFT      (10U)
/*! AXI_READ_ERROR_1 - AXI_READ_ERROR_1 */
#define PXP_STAT_SET_AXI_READ_ERROR_1(x)         (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_1_MASK)

#define PXP_STAT_SET_RSVD2_MASK                  (0x800U)
#define PXP_STAT_SET_RSVD2_SHIFT                 (11U)
/*! RSVD2 - RSVD2 */
#define PXP_STAT_SET_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_RSVD2_SHIFT)) & PXP_STAT_SET_RSVD2_MASK)

#define PXP_STAT_SET_AXI_ERROR_ID_1_MASK         (0xF000U)
#define PXP_STAT_SET_AXI_ERROR_ID_1_SHIFT        (12U)
/*! AXI_ERROR_ID_1 - AXI_ERROR_ID_1 */
#define PXP_STAT_SET_AXI_ERROR_ID_1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_1_MASK)

#define PXP_STAT_SET_BLOCKY_MASK                 (0xFF0000U)
#define PXP_STAT_SET_BLOCKY_SHIFT                (16U)
/*! BLOCKY - BLOCKY */
#define PXP_STAT_SET_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)

#define PXP_STAT_SET_BLOCKX_MASK                 (0xFF000000U)
#define PXP_STAT_SET_BLOCKX_SHIFT                (24U)
/*! BLOCKX - BLOCKX */
#define PXP_STAT_SET_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)
/*! @} */

/*! @name STAT_CLR - Status Register */
/*! @{ */

#define PXP_STAT_CLR_IRQ0_MASK                   (0x1U)
#define PXP_STAT_CLR_IRQ0_SHIFT                  (0U)
/*! IRQ0 - IRQ0 */
#define PXP_STAT_CLR_IRQ0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ0_SHIFT)) & PXP_STAT_CLR_IRQ0_MASK)

#define PXP_STAT_CLR_AXI_WRITE_ERROR_0_MASK      (0x2U)
#define PXP_STAT_CLR_AXI_WRITE_ERROR_0_SHIFT     (1U)
/*! AXI_WRITE_ERROR_0 - AXI_WRITE_ERROR_0 */
#define PXP_STAT_CLR_AXI_WRITE_ERROR_0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_0_MASK)

#define PXP_STAT_CLR_AXI_READ_ERROR_0_MASK       (0x4U)
#define PXP_STAT_CLR_AXI_READ_ERROR_0_SHIFT      (2U)
/*! AXI_READ_ERROR_0 - AXI_READ_ERROR_0 */
#define PXP_STAT_CLR_AXI_READ_ERROR_0(x)         (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_0_MASK)

#define PXP_STAT_CLR_NEXT_IRQ_MASK               (0x8U)
#define PXP_STAT_CLR_NEXT_IRQ_SHIFT              (3U)
/*! NEXT_IRQ - NEXT_IRQ */
#define PXP_STAT_CLR_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)

#define PXP_STAT_CLR_AXI_ERROR_ID_0_MASK         (0xF0U)
#define PXP_STAT_CLR_AXI_ERROR_ID_0_SHIFT        (4U)
/*! AXI_ERROR_ID_0 - AXI_ERROR_ID_0 */
#define PXP_STAT_CLR_AXI_ERROR_ID_0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_0_MASK)

#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
/*! LUT_DMA_LOAD_DONE_IRQ - LUT_DMA_LOAD_DONE_IRQ */
#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define PXP_STAT_CLR_AXI_WRITE_ERROR_1_MASK      (0x200U)
#define PXP_STAT_CLR_AXI_WRITE_ERROR_1_SHIFT     (9U)
/*! AXI_WRITE_ERROR_1 - AXI_WRITE_ERROR_1 */
#define PXP_STAT_CLR_AXI_WRITE_ERROR_1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_1_MASK)

#define PXP_STAT_CLR_AXI_READ_ERROR_1_MASK       (0x400U)
#define PXP_STAT_CLR_AXI_READ_ERROR_1_SHIFT      (10U)
/*! AXI_READ_ERROR_1 - AXI_READ_ERROR_1 */
#define PXP_STAT_CLR_AXI_READ_ERROR_1(x)         (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_1_MASK)

#define PXP_STAT_CLR_RSVD2_MASK                  (0x800U)
#define PXP_STAT_CLR_RSVD2_SHIFT                 (11U)
/*! RSVD2 - RSVD2 */
#define PXP_STAT_CLR_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_RSVD2_SHIFT)) & PXP_STAT_CLR_RSVD2_MASK)

#define PXP_STAT_CLR_AXI_ERROR_ID_1_MASK         (0xF000U)
#define PXP_STAT_CLR_AXI_ERROR_ID_1_SHIFT        (12U)
/*! AXI_ERROR_ID_1 - AXI_ERROR_ID_1 */
#define PXP_STAT_CLR_AXI_ERROR_ID_1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_1_MASK)

#define PXP_STAT_CLR_BLOCKY_MASK                 (0xFF0000U)
#define PXP_STAT_CLR_BLOCKY_SHIFT                (16U)
/*! BLOCKY - BLOCKY */
#define PXP_STAT_CLR_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)

#define PXP_STAT_CLR_BLOCKX_MASK                 (0xFF000000U)
#define PXP_STAT_CLR_BLOCKX_SHIFT                (24U)
/*! BLOCKX - BLOCKX */
#define PXP_STAT_CLR_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)
/*! @} */

/*! @name STAT_TOG - Status Register */
/*! @{ */

#define PXP_STAT_TOG_IRQ0_MASK                   (0x1U)
#define PXP_STAT_TOG_IRQ0_SHIFT                  (0U)
/*! IRQ0 - IRQ0 */
#define PXP_STAT_TOG_IRQ0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ0_SHIFT)) & PXP_STAT_TOG_IRQ0_MASK)

#define PXP_STAT_TOG_AXI_WRITE_ERROR_0_MASK      (0x2U)
#define PXP_STAT_TOG_AXI_WRITE_ERROR_0_SHIFT     (1U)
/*! AXI_WRITE_ERROR_0 - AXI_WRITE_ERROR_0 */
#define PXP_STAT_TOG_AXI_WRITE_ERROR_0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_0_MASK)

#define PXP_STAT_TOG_AXI_READ_ERROR_0_MASK       (0x4U)
#define PXP_STAT_TOG_AXI_READ_ERROR_0_SHIFT      (2U)
/*! AXI_READ_ERROR_0 - AXI_READ_ERROR_0 */
#define PXP_STAT_TOG_AXI_READ_ERROR_0(x)         (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_0_MASK)

#define PXP_STAT_TOG_NEXT_IRQ_MASK               (0x8U)
#define PXP_STAT_TOG_NEXT_IRQ_SHIFT              (3U)
/*! NEXT_IRQ - NEXT_IRQ */
#define PXP_STAT_TOG_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)

#define PXP_STAT_TOG_AXI_ERROR_ID_0_MASK         (0xF0U)
#define PXP_STAT_TOG_AXI_ERROR_ID_0_SHIFT        (4U)
/*! AXI_ERROR_ID_0 - AXI_ERROR_ID_0 */
#define PXP_STAT_TOG_AXI_ERROR_ID_0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_0_MASK)

#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
/*! LUT_DMA_LOAD_DONE_IRQ - LUT_DMA_LOAD_DONE_IRQ */
#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define PXP_STAT_TOG_AXI_WRITE_ERROR_1_MASK      (0x200U)
#define PXP_STAT_TOG_AXI_WRITE_ERROR_1_SHIFT     (9U)
/*! AXI_WRITE_ERROR_1 - AXI_WRITE_ERROR_1 */
#define PXP_STAT_TOG_AXI_WRITE_ERROR_1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_1_MASK)

#define PXP_STAT_TOG_AXI_READ_ERROR_1_MASK       (0x400U)
#define PXP_STAT_TOG_AXI_READ_ERROR_1_SHIFT      (10U)
/*! AXI_READ_ERROR_1 - AXI_READ_ERROR_1 */
#define PXP_STAT_TOG_AXI_READ_ERROR_1(x)         (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_1_MASK)

#define PXP_STAT_TOG_RSVD2_MASK                  (0x800U)
#define PXP_STAT_TOG_RSVD2_SHIFT                 (11U)
/*! RSVD2 - RSVD2 */
#define PXP_STAT_TOG_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_RSVD2_SHIFT)) & PXP_STAT_TOG_RSVD2_MASK)

#define PXP_STAT_TOG_AXI_ERROR_ID_1_MASK         (0xF000U)
#define PXP_STAT_TOG_AXI_ERROR_ID_1_SHIFT        (12U)
/*! AXI_ERROR_ID_1 - AXI_ERROR_ID_1 */
#define PXP_STAT_TOG_AXI_ERROR_ID_1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_1_MASK)

#define PXP_STAT_TOG_BLOCKY_MASK                 (0xFF0000U)
#define PXP_STAT_TOG_BLOCKY_SHIFT                (16U)
/*! BLOCKY - BLOCKY */
#define PXP_STAT_TOG_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)

#define PXP_STAT_TOG_BLOCKX_MASK                 (0xFF000000U)
#define PXP_STAT_TOG_BLOCKX_SHIFT                (24U)
/*! BLOCKX - BLOCKX */
#define PXP_STAT_TOG_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)
/*! @} */

/*! @name OUT_CTRL - Output Buffer Control Register */
/*! @{ */

#define PXP_OUT_CTRL_FORMAT_MASK                 (0x1FU)
#define PXP_OUT_CTRL_FORMAT_SHIFT                (0U)
/*! FORMAT - FORMAT
 *  0b00000..ARGB8888 : 32-bit pixels
 *  0b00100..RGB888 : 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
 *  0b00101..RGB888P : 24-bit pixels (packed 24-bit format)
 *  0b01000..ARGB1555 : 16-bit pixels
 *  0b01001..ARGB4444 : 16-bit pixels
 *  0b01100..RGB555 : 16-bit pixels
 *  0b01101..RGB444 : 16-bit pixels
 *  0b01110..RGB565 : 16-bit pixels
 *  0b10000..YUV1P444 : 32-bit pixels (1-plane XYUV unpacked)
 *  0b10010..UYVY1P422 : 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
 *  0b10011..VYUY1P422 : 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
 *  0b10100..Y8 : 8-bit monochrome pixels (1-plane Y luma output)
 *  0b10101..Y4 : 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
 *  0b11000..YUV2P422 : 16-bit pixels (2-plane UV interleaved bytes)
 *  0b11001..YUV2P420 : 16-bit pixels (2-plane UV)
 *  0b11010..YVU2P422 : 16-bit pixels (2-plane VU interleaved bytes)
 *  0b11011..YVU2P420 : 16-bit pixels (2-plane VU)
 */
#define PXP_OUT_CTRL_FORMAT(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)

#define PXP_OUT_CTRL_RSVD0_MASK                  (0xE0U)
#define PXP_OUT_CTRL_RSVD0_SHIFT                 (5U)
/*! RSVD0 - RSVD0 */
#define PXP_OUT_CTRL_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK)

#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK      (0x300U)
#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT     (8U)
/*! INTERLACED_OUTPUT - INTERLACED_OUTPUT
 *  0b00..PROGRESSIVE : All data written in progressive format to the OUTBUF Pointer.
 *  0b01..FIELD0 : Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
 *  0b10..FIELD1 : Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
 *  0b11..INTERLACED : Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
 */
#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x)        (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)

#define PXP_OUT_CTRL_RSVD1_MASK                  (0x7FFC00U)
#define PXP_OUT_CTRL_RSVD1_SHIFT                 (10U)
/*! RSVD1 - RSVD1 */
#define PXP_OUT_CTRL_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD1_SHIFT)) & PXP_OUT_CTRL_RSVD1_MASK)

#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK           (0x800000U)
#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT          (23U)
/*! ALPHA_OUTPUT - ALPHA_OUTPUT */
#define PXP_OUT_CTRL_ALPHA_OUTPUT(x)             (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)

#define PXP_OUT_CTRL_ALPHA_MASK                  (0xFF000000U)
#define PXP_OUT_CTRL_ALPHA_SHIFT                 (24U)
/*! ALPHA - ALPHA */
#define PXP_OUT_CTRL_ALPHA(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)
/*! @} */

/*! @name OUT_CTRL_SET - Output Buffer Control Register */
/*! @{ */

#define PXP_OUT_CTRL_SET_FORMAT_MASK             (0x1FU)
#define PXP_OUT_CTRL_SET_FORMAT_SHIFT            (0U)
/*! FORMAT - FORMAT */
#define PXP_OUT_CTRL_SET_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)

#define PXP_OUT_CTRL_SET_RSVD0_MASK              (0xE0U)
#define PXP_OUT_CTRL_SET_RSVD0_SHIFT             (5U)
/*! RSVD0 - RSVD0 */
#define PXP_OUT_CTRL_SET_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK)

#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK  (0x300U)
#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
/*! INTERLACED_OUTPUT - INTERLACED_OUTPUT */
#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)

#define PXP_OUT_CTRL_SET_RSVD1_MASK              (0x7FFC00U)
#define PXP_OUT_CTRL_SET_RSVD1_SHIFT             (10U)
/*! RSVD1 - RSVD1 */
#define PXP_OUT_CTRL_SET_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD1_SHIFT)) & PXP_OUT_CTRL_SET_RSVD1_MASK)

#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK       (0x800000U)
#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT      (23U)
/*! ALPHA_OUTPUT - ALPHA_OUTPUT */
#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)

#define PXP_OUT_CTRL_SET_ALPHA_MASK              (0xFF000000U)
#define PXP_OUT_CTRL_SET_ALPHA_SHIFT             (24U)
/*! ALPHA - ALPHA */
#define PXP_OUT_CTRL_SET_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)
/*! @} */

/*! @name OUT_CTRL_CLR - Output Buffer Control Register */
/*! @{ */

#define PXP_OUT_CTRL_CLR_FORMAT_MASK             (0x1FU)
#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT            (0U)
/*! FORMAT - FORMAT */
#define PXP_OUT_CTRL_CLR_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)

#define PXP_OUT_CTRL_CLR_RSVD0_MASK              (0xE0U)
#define PXP_OUT_CTRL_CLR_RSVD0_SHIFT             (5U)
/*! RSVD0 - RSVD0 */
#define PXP_OUT_CTRL_CLR_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK)

#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK  (0x300U)
#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
/*! INTERLACED_OUTPUT - INTERLACED_OUTPUT */
#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)

#define PXP_OUT_CTRL_CLR_RSVD1_MASK              (0x7FFC00U)
#define PXP_OUT_CTRL_CLR_RSVD1_SHIFT             (10U)
/*! RSVD1 - RSVD1 */
#define PXP_OUT_CTRL_CLR_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD1_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD1_MASK)

#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK       (0x800000U)
#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT      (23U)
/*! ALPHA_OUTPUT - ALPHA_OUTPUT */
#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)

#define PXP_OUT_CTRL_CLR_ALPHA_MASK              (0xFF000000U)
#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT             (24U)
/*! ALPHA - ALPHA */
#define PXP_OUT_CTRL_CLR_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)
/*! @} */

/*! @name OUT_CTRL_TOG - Output Buffer Control Register */
/*! @{ */

#define PXP_OUT_CTRL_TOG_FORMAT_MASK             (0x1FU)
#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT            (0U)
/*! FORMAT - FORMAT */
#define PXP_OUT_CTRL_TOG_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)

#define PXP_OUT_CTRL_TOG_RSVD0_MASK              (0xE0U)
#define PXP_OUT_CTRL_TOG_RSVD0_SHIFT             (5U)
/*! RSVD0 - RSVD0 */
#define PXP_OUT_CTRL_TOG_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK)

#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK  (0x300U)
#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
/*! INTERLACED_OUTPUT - INTERLACED_OUTPUT */
#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)

#define PXP_OUT_CTRL_TOG_RSVD1_MASK              (0x7FFC00U)
#define PXP_OUT_CTRL_TOG_RSVD1_SHIFT             (10U)
/*! RSVD1 - RSVD1 */
#define PXP_OUT_CTRL_TOG_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD1_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD1_MASK)

#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK       (0x800000U)
#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT      (23U)
/*! ALPHA_OUTPUT - ALPHA_OUTPUT */
#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)

#define PXP_OUT_CTRL_TOG_ALPHA_MASK              (0xFF000000U)
#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT             (24U)
/*! ALPHA - ALPHA */
#define PXP_OUT_CTRL_TOG_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)
/*! @} */

/*! @name OUT_BUF - Output Frame Buffer Pointer */
/*! @{ */

#define PXP_OUT_BUF_ADDR_MASK                    (0xFFFFFFFFU)
#define PXP_OUT_BUF_ADDR_SHIFT                   (0U)
/*! ADDR - ADDR */
#define PXP_OUT_BUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)
/*! @} */

/*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */
/*! @{ */

#define PXP_OUT_BUF2_ADDR_MASK                   (0xFFFFFFFFU)
#define PXP_OUT_BUF2_ADDR_SHIFT                  (0U)
/*! ADDR - ADDR */
#define PXP_OUT_BUF2_ADDR(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)
/*! @} */

/*! @name OUT_PITCH - Output Buffer Pitch */
/*! @{ */

#define PXP_OUT_PITCH_PITCH_MASK                 (0xFFFFU)
#define PXP_OUT_PITCH_PITCH_SHIFT                (0U)
/*! PITCH - PITCH */
#define PXP_OUT_PITCH_PITCH(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)

#define PXP_OUT_PITCH_RSVD_MASK                  (0xFFFF0000U)
#define PXP_OUT_PITCH_RSVD_SHIFT                 (16U)
/*! RSVD - RSVD */
#define PXP_OUT_PITCH_RSVD(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK)
/*! @} */

/*! @name OUT_LRC - Output Surface Lower Right Coordinate */
/*! @{ */

#define PXP_OUT_LRC_Y_MASK                       (0x3FFFU)
#define PXP_OUT_LRC_Y_SHIFT                      (0U)
/*! Y - Y */
#define PXP_OUT_LRC_Y(x)                         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)

#define PXP_OUT_LRC_RSVD0_MASK                   (0xC000U)
#define PXP_OUT_LRC_RSVD0_SHIFT                  (14U)
/*! RSVD0 - RSVD0 */
#define PXP_OUT_LRC_RSVD0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD0_SHIFT)) & PXP_OUT_LRC_RSVD0_MASK)

#define PXP_OUT_LRC_X_MASK                       (0x3FFF0000U)
#define PXP_OUT_LRC_X_SHIFT                      (16U)
/*! X - X */
#define PXP_OUT_LRC_X(x)                         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)

#define PXP_OUT_LRC_RSVD1_MASK                   (0xC0000000U)
#define PXP_OUT_LRC_RSVD1_SHIFT                  (30U)
/*! RSVD1 - RSVD1 */
#define PXP_OUT_LRC_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK)
/*! @} */

/*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */
/*! @{ */

#define PXP_OUT_PS_ULC_Y_MASK                    (0x3FFFU)
#define PXP_OUT_PS_ULC_Y_SHIFT                   (0U)
/*! Y - Y */
#define PXP_OUT_PS_ULC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)

#define PXP_OUT_PS_ULC_RSVD0_MASK                (0xC000U)
#define PXP_OUT_PS_ULC_RSVD0_SHIFT               (14U)
/*! RSVD0 - RSVD0 */
#define PXP_OUT_PS_ULC_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD0_SHIFT)) & PXP_OUT_PS_ULC_RSVD0_MASK)

#define PXP_OUT_PS_ULC_X_MASK                    (0x3FFF0000U)
#define PXP_OUT_PS_ULC_X_SHIFT                   (16U)
/*! X - X */
#define PXP_OUT_PS_ULC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)

#define PXP_OUT_PS_ULC_RSVD1_MASK                (0xC0000000U)
#define PXP_OUT_PS_ULC_RSVD1_SHIFT               (30U)
/*! RSVD1 - RSVD1 */
#define PXP_OUT_PS_ULC_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK)
/*! @} */

/*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */
/*! @{ */

#define PXP_OUT_PS_LRC_Y_MASK                    (0x3FFFU)
#define PXP_OUT_PS_LRC_Y_SHIFT                   (0U)
/*! Y - Y */
#define PXP_OUT_PS_LRC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)

#define PXP_OUT_PS_LRC_RSVD0_MASK                (0xC000U)
#define PXP_OUT_PS_LRC_RSVD0_SHIFT               (14U)
/*! RSVD0 - RSVD0 */
#define PXP_OUT_PS_LRC_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD0_SHIFT)) & PXP_OUT_PS_LRC_RSVD0_MASK)

#define PXP_OUT_PS_LRC_X_MASK                    (0x3FFF0000U)
#define PXP_OUT_PS_LRC_X_SHIFT                   (16U)
/*! X - X */
#define PXP_OUT_PS_LRC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)

#define PXP_OUT_PS_LRC_RSVD1_MASK                (0xC0000000U)
#define PXP_OUT_PS_LRC_RSVD1_SHIFT               (30U)
/*! RSVD1 - RSVD1 */
#define PXP_OUT_PS_LRC_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK)
/*! @} */

/*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */
/*! @{ */

#define PXP_OUT_AS_ULC_Y_MASK                    (0x3FFFU)
#define PXP_OUT_AS_ULC_Y_SHIFT                   (0U)
/*! Y - Y */
#define PXP_OUT_AS_ULC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)

#define PXP_OUT_AS_ULC_RSVD0_MASK                (0xC000U)
#define PXP_OUT_AS_ULC_RSVD0_SHIFT               (14U)
/*! RSVD0 - RSVD0 */
#define PXP_OUT_AS_ULC_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD0_SHIFT)) & PXP_OUT_AS_ULC_RSVD0_MASK)

#define PXP_OUT_AS_ULC_X_MASK                    (0x3FFF0000U)
#define PXP_OUT_AS_ULC_X_SHIFT                   (16U)
/*! X - X */
#define PXP_OUT_AS_ULC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)

#define PXP_OUT_AS_ULC_RSVD1_MASK                (0xC0000000U)
#define PXP_OUT_AS_ULC_RSVD1_SHIFT               (30U)
/*! RSVD1 - RSVD1 */
#define PXP_OUT_AS_ULC_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK)
/*! @} */

/*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */
/*! @{ */

#define PXP_OUT_AS_LRC_Y_MASK                    (0x3FFFU)
#define PXP_OUT_AS_LRC_Y_SHIFT                   (0U)
/*! Y - Y */
#define PXP_OUT_AS_LRC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)

#define PXP_OUT_AS_LRC_RSVD0_MASK                (0xC000U)
#define PXP_OUT_AS_LRC_RSVD0_SHIFT               (14U)
/*! RSVD0 - RSVD0 */
#define PXP_OUT_AS_LRC_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD0_SHIFT)) & PXP_OUT_AS_LRC_RSVD0_MASK)

#define PXP_OUT_AS_LRC_X_MASK                    (0x3FFF0000U)
#define PXP_OUT_AS_LRC_X_SHIFT                   (16U)
/*! X - X */
#define PXP_OUT_AS_LRC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)

#define PXP_OUT_AS_LRC_RSVD1_MASK                (0xC0000000U)
#define PXP_OUT_AS_LRC_RSVD1_SHIFT               (30U)
/*! RSVD1 - RSVD1 */
#define PXP_OUT_AS_LRC_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK)
/*! @} */

/*! @name PS_CTRL - Processed Surface (PS) Control Register */
/*! @{ */

#define PXP_PS_CTRL_FORMAT_MASK                  (0x3FU)
#define PXP_PS_CTRL_FORMAT_SHIFT                 (0U)
/*! FORMAT - FORMAT
 *  0b000100..RGB888 : 32-bit pixels (unpacked 24-bit format)
 *  0b001100..RGB555 : 16-bit pixels
 *  0b001101..RGB444 : 16-bit pixels
 *  0b001110..RGB565 : 16-bit pixels
 *  0b010000..YUV1P444 : 32-bit pixels (1-plane XYUV unpacked)
 *  0b010010..UYVY1P422 : 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
 *  0b010011..VYUY1P422 : 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
 *  0b010100..Y8 : 8-bit monochrome pixels (1-plane Y luma output)
 *  0b010101..Y4 : 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
 *  0b011000..YUV2P422 : 16-bit pixels (2-plane UV interleaved bytes)
 *  0b011001..YUV2P420 : 16-bit pixels (2-plane UV)
 *  0b011010..YVU2P422 : 16-bit pixels (2-plane VU interleaved bytes)
 *  0b011011..YVU2P420 : 16-bit pixels (2-plane VU)
 *  0b011110..YUV422 : 16-bit pixels (3-plane format)
 *  0b011111..YUV420 : 16-bit pixels (3-plane format)
 */
#define PXP_PS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)

#define PXP_PS_CTRL_WB_SWAP_MASK                 (0x40U)
#define PXP_PS_CTRL_WB_SWAP_SHIFT                (6U)
/*! WB_SWAP - WB_SWAP */
#define PXP_PS_CTRL_WB_SWAP(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)

#define PXP_PS_CTRL_RSVD0_MASK                   (0x80U)
#define PXP_PS_CTRL_RSVD0_SHIFT                  (7U)
/*! RSVD0 - RSVD0 */
#define PXP_PS_CTRL_RSVD0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK)

#define PXP_PS_CTRL_DECY_MASK                    (0x300U)
#define PXP_PS_CTRL_DECY_SHIFT                   (8U)
/*! DECY - DECY
 *  0b00..DISABLE : Disable pre-decimation filter.
 *  0b01..DECY2 : Decimate PS by 2.
 *  0b10..DECY4 : Decimate PS by 4.
 *  0b11..DECY8 : Decimate PS by 8.
 */
#define PXP_PS_CTRL_DECY(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)

#define PXP_PS_CTRL_DECX_MASK                    (0xC00U)
#define PXP_PS_CTRL_DECX_SHIFT                   (10U)
/*! DECX - DECX
 *  0b00..DISABLE : Disable pre-decimation filter.
 *  0b01..DECX2 : Decimate PS by 2.
 *  0b10..DECX4 : Decimate PS by 4.
 *  0b11..DECX8 : Decimate PS by 8.
 */
#define PXP_PS_CTRL_DECX(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)

#define PXP_PS_CTRL_RSVD1_MASK                   (0xFFFFF000U)
#define PXP_PS_CTRL_RSVD1_SHIFT                  (12U)
/*! RSVD1 - RSVD1 */
#define PXP_PS_CTRL_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK)
/*! @} */

/*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */
/*! @{ */

#define PXP_PS_CTRL_SET_FORMAT_MASK              (0x3FU)
#define PXP_PS_CTRL_SET_FORMAT_SHIFT             (0U)
/*! FORMAT - FORMAT */
#define PXP_PS_CTRL_SET_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)

#define PXP_PS_CTRL_SET_WB_SWAP_MASK             (0x40U)
#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT            (6U)
/*! WB_SWAP - WB_SWAP */
#define PXP_PS_CTRL_SET_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)

#define PXP_PS_CTRL_SET_RSVD0_MASK               (0x80U)
#define PXP_PS_CTRL_SET_RSVD0_SHIFT              (7U)
/*! RSVD0 - RSVD0 */
#define PXP_PS_CTRL_SET_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK)

#define PXP_PS_CTRL_SET_DECY_MASK                (0x300U)
#define PXP_PS_CTRL_SET_DECY_SHIFT               (8U)
/*! DECY - DECY */
#define PXP_PS_CTRL_SET_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)

#define PXP_PS_CTRL_SET_DECX_MASK                (0xC00U)
#define PXP_PS_CTRL_SET_DECX_SHIFT               (10U)
/*! DECX - DECX */
#define PXP_PS_CTRL_SET_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)

#define PXP_PS_CTRL_SET_RSVD1_MASK               (0xFFFFF000U)
#define PXP_PS_CTRL_SET_RSVD1_SHIFT              (12U)
/*! RSVD1 - RSVD1 */
#define PXP_PS_CTRL_SET_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK)
/*! @} */

/*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */
/*! @{ */

#define PXP_PS_CTRL_CLR_FORMAT_MASK              (0x3FU)
#define PXP_PS_CTRL_CLR_FORMAT_SHIFT             (0U)
/*! FORMAT - FORMAT */
#define PXP_PS_CTRL_CLR_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)

#define PXP_PS_CTRL_CLR_WB_SWAP_MASK             (0x40U)
#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT            (6U)
/*! WB_SWAP - WB_SWAP */
#define PXP_PS_CTRL_CLR_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)

#define PXP_PS_CTRL_CLR_RSVD0_MASK               (0x80U)
#define PXP_PS_CTRL_CLR_RSVD0_SHIFT              (7U)
/*! RSVD0 - RSVD0 */
#define PXP_PS_CTRL_CLR_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK)

#define PXP_PS_CTRL_CLR_DECY_MASK                (0x300U)
#define PXP_PS_CTRL_CLR_DECY_SHIFT               (8U)
/*! DECY - DECY */
#define PXP_PS_CTRL_CLR_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)

#define PXP_PS_CTRL_CLR_DECX_MASK                (0xC00U)
#define PXP_PS_CTRL_CLR_DECX_SHIFT               (10U)
/*! DECX - DECX */
#define PXP_PS_CTRL_CLR_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)

#define PXP_PS_CTRL_CLR_RSVD1_MASK               (0xFFFFF000U)
#define PXP_PS_CTRL_CLR_RSVD1_SHIFT              (12U)
/*! RSVD1 - RSVD1 */
#define PXP_PS_CTRL_CLR_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK)
/*! @} */

/*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */
/*! @{ */

#define PXP_PS_CTRL_TOG_FORMAT_MASK              (0x3FU)
#define PXP_PS_CTRL_TOG_FORMAT_SHIFT             (0U)
/*! FORMAT - FORMAT */
#define PXP_PS_CTRL_TOG_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)

#define PXP_PS_CTRL_TOG_WB_SWAP_MASK             (0x40U)
#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT            (6U)
/*! WB_SWAP - WB_SWAP */
#define PXP_PS_CTRL_TOG_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)

#define PXP_PS_CTRL_TOG_RSVD0_MASK               (0x80U)
#define PXP_PS_CTRL_TOG_RSVD0_SHIFT              (7U)
/*! RSVD0 - RSVD0 */
#define PXP_PS_CTRL_TOG_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK)

#define PXP_PS_CTRL_TOG_DECY_MASK                (0x300U)
#define PXP_PS_CTRL_TOG_DECY_SHIFT               (8U)
/*! DECY - DECY */
#define PXP_PS_CTRL_TOG_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)

#define PXP_PS_CTRL_TOG_DECX_MASK                (0xC00U)
#define PXP_PS_CTRL_TOG_DECX_SHIFT               (10U)
/*! DECX - DECX */
#define PXP_PS_CTRL_TOG_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)

#define PXP_PS_CTRL_TOG_RSVD1_MASK               (0xFFFFF000U)
#define PXP_PS_CTRL_TOG_RSVD1_SHIFT              (12U)
/*! RSVD1 - RSVD1 */
#define PXP_PS_CTRL_TOG_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK)
/*! @} */

/*! @name PS_BUF - PS Input Buffer Address */
/*! @{ */

#define PXP_PS_BUF_ADDR_MASK                     (0xFFFFFFFFU)
#define PXP_PS_BUF_ADDR_SHIFT                    (0U)
/*! ADDR - ADDR */
#define PXP_PS_BUF_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)
/*! @} */

/*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */
/*! @{ */

#define PXP_PS_UBUF_ADDR_MASK                    (0xFFFFFFFFU)
#define PXP_PS_UBUF_ADDR_SHIFT                   (0U)
/*! ADDR - ADDR */
#define PXP_PS_UBUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)
/*! @} */

/*! @name PS_VBUF - PS V/Cr Input Buffer Address */
/*! @{ */

#define PXP_PS_VBUF_ADDR_MASK                    (0xFFFFFFFFU)
#define PXP_PS_VBUF_ADDR_SHIFT                   (0U)
/*! ADDR - ADDR */
#define PXP_PS_VBUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)
/*! @} */

/*! @name PS_PITCH - Processed Surface Pitch */
/*! @{ */

#define PXP_PS_PITCH_PITCH_MASK                  (0xFFFFU)
#define PXP_PS_PITCH_PITCH_SHIFT                 (0U)
/*! PITCH - PITCH */
#define PXP_PS_PITCH_PITCH(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)

#define PXP_PS_PITCH_RSVD_MASK                   (0xFFFF0000U)
#define PXP_PS_PITCH_RSVD_SHIFT                  (16U)
/*! RSVD - RSVD */
#define PXP_PS_PITCH_RSVD(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK)
/*! @} */

/*! @name PS_BACKGROUND_0 - PS Background Color */
/*! @{ */

#define PXP_PS_BACKGROUND_0_COLOR_MASK           (0xFFFFFFU)
#define PXP_PS_BACKGROUND_0_COLOR_SHIFT          (0U)
/*! COLOR - COLOR */
#define PXP_PS_BACKGROUND_0_COLOR(x)             (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_0_COLOR_SHIFT)) & PXP_PS_BACKGROUND_0_COLOR_MASK)

#define PXP_PS_BACKGROUND_0_RSVD_MASK            (0xFF000000U)
#define PXP_PS_BACKGROUND_0_RSVD_SHIFT           (24U)
/*! RSVD - RSVD */
#define PXP_PS_BACKGROUND_0_RSVD(x)              (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_0_RSVD_SHIFT)) & PXP_PS_BACKGROUND_0_RSVD_MASK)
/*! @} */

/*! @name PS_SCALE - PS Scale Factor Register */
/*! @{ */

#define PXP_PS_SCALE_XSCALE_MASK                 (0x7FFFU)
#define PXP_PS_SCALE_XSCALE_SHIFT                (0U)
/*! XSCALE - XSCALE */
#define PXP_PS_SCALE_XSCALE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)

#define PXP_PS_SCALE_RSVD1_MASK                  (0x8000U)
#define PXP_PS_SCALE_RSVD1_SHIFT                 (15U)
/*! RSVD1 - RSVD1 */
#define PXP_PS_SCALE_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD1_SHIFT)) & PXP_PS_SCALE_RSVD1_MASK)

#define PXP_PS_SCALE_YSCALE_MASK                 (0x7FFF0000U)
#define PXP_PS_SCALE_YSCALE_SHIFT                (16U)
/*! YSCALE - YSCALE */
#define PXP_PS_SCALE_YSCALE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)

#define PXP_PS_SCALE_RSVD2_MASK                  (0x80000000U)
#define PXP_PS_SCALE_RSVD2_SHIFT                 (31U)
/*! RSVD2 - RSVD2 */
#define PXP_PS_SCALE_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK)
/*! @} */

/*! @name PS_OFFSET - PS Scale Offset Register */
/*! @{ */

#define PXP_PS_OFFSET_XOFFSET_MASK               (0xFFFU)
#define PXP_PS_OFFSET_XOFFSET_SHIFT              (0U)
/*! XOFFSET - XOFFSET */
#define PXP_PS_OFFSET_XOFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)

#define PXP_PS_OFFSET_RSVD1_MASK                 (0xF000U)
#define PXP_PS_OFFSET_RSVD1_SHIFT                (12U)
/*! RSVD1 - RSVD1 */
#define PXP_PS_OFFSET_RSVD1(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD1_SHIFT)) & PXP_PS_OFFSET_RSVD1_MASK)

#define PXP_PS_OFFSET_YOFFSET_MASK               (0xFFF0000U)
#define PXP_PS_OFFSET_YOFFSET_SHIFT              (16U)
/*! YOFFSET - YOFFSET */
#define PXP_PS_OFFSET_YOFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)

#define PXP_PS_OFFSET_RSVD2_MASK                 (0xF0000000U)
#define PXP_PS_OFFSET_RSVD2_SHIFT                (28U)
/*! RSVD2 - RSVD2 */
#define PXP_PS_OFFSET_RSVD2(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK)
/*! @} */

/*! @name PS_CLRKEYLOW_0 - PS Color Key Low */
/*! @{ */

#define PXP_PS_CLRKEYLOW_0_PIXEL_MASK            (0xFFFFFFU)
#define PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT           (0U)
/*! PIXEL - PIXEL */
#define PXP_PS_CLRKEYLOW_0_PIXEL(x)              (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_0_PIXEL_MASK)

#define PXP_PS_CLRKEYLOW_0_RSVD1_MASK            (0xFF000000U)
#define PXP_PS_CLRKEYLOW_0_RSVD1_SHIFT           (24U)
/*! RSVD1 - RSVD1 */
#define PXP_PS_CLRKEYLOW_0_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_0_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_0_RSVD1_MASK)
/*! @} */

/*! @name PS_CLRKEYHIGH_0 - PS Color Key High */
/*! @{ */

#define PXP_PS_CLRKEYHIGH_0_PIXEL_MASK           (0xFFFFFFU)
#define PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT          (0U)
/*! PIXEL - PIXEL */
#define PXP_PS_CLRKEYHIGH_0_PIXEL(x)             (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_0_PIXEL_MASK)

#define PXP_PS_CLRKEYHIGH_0_RSVD1_MASK           (0xFF000000U)
#define PXP_PS_CLRKEYHIGH_0_RSVD1_SHIFT          (24U)
/*! RSVD1 - RSVD1 */
#define PXP_PS_CLRKEYHIGH_0_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_0_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_0_RSVD1_MASK)
/*! @} */

/*! @name AS_CTRL - Alpha Surface Control */
/*! @{ */

#define PXP_AS_CTRL_RSVD0_MASK                   (0x1U)
#define PXP_AS_CTRL_RSVD0_SHIFT                  (0U)
/*! RSVD0 - RSVD0 */
#define PXP_AS_CTRL_RSVD0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK)

#define PXP_AS_CTRL_ALPHA_CTRL_MASK              (0x6U)
#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT             (1U)
/*! ALPHA_CTRL - ALPHA_CTRL
 *  0b00..Embedded : Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored.
 *  0b01..Override : Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels.
 *  0b10..Multiply : Indicates that the value in the ALPHA field should be used to scale all pixel alpha values.
 *        Each pixel alpha is multiplied by the value in the ALPHA field.
 *  0b11..ROPs : Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels.
 */
#define PXP_AS_CTRL_ALPHA_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)

#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK         (0x8U)
#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT        (3U)
/*! ENABLE_COLORKEY - ENABLE_COLORKEY */
#define PXP_AS_CTRL_ENABLE_COLORKEY(x)           (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)

#define PXP_AS_CTRL_FORMAT_MASK                  (0xF0U)
#define PXP_AS_CTRL_FORMAT_SHIFT                 (4U)
/*! FORMAT - FORMAT
 *  0b0000..ARGB8888 : 32-bit pixels with alpha
 *  0b0001..RGBA8888 : 32-bit pixels with alpha
 *  0b0100..RGB888 : 32-bit pixels without alpha (unpacked 24-bit format)
 *  0b1000..ARGB1555 : 16-bit pixels with alpha
 *  0b1001..ARGB4444 : 16-bit pixels with alpha
 *  0b1100..RGB555 : 16-bit pixels without alpha
 *  0b1101..RGB444 : 16-bit pixels without alpha
 *  0b1110..RGB565 : 16-bit pixels without alpha
 */
#define PXP_AS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)

#define PXP_AS_CTRL_ALPHA_MASK                   (0xFF00U)
#define PXP_AS_CTRL_ALPHA_SHIFT                  (8U)
/*! ALPHA - ALPHA */
#define PXP_AS_CTRL_ALPHA(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)

#define PXP_AS_CTRL_ROP_MASK                     (0xF0000U)
#define PXP_AS_CTRL_ROP_SHIFT                    (16U)
/*! ROP - ROP
 *  0b0000..MASKAS : AS AND PS
 *  0b0001..MASKNOTAS : nAS AND PS
 *  0b0010..MASKASNOT : AS AND nPS
 *  0b0011..MERGEAS : AS OR PS
 *  0b0100..MERGENOTAS : nAS OR PS
 *  0b0101..MERGEASNOT : AS OR nPS
 *  0b0110..NOTCOPYAS : nAS
 *  0b0111..NOT : nPS
 *  0b1000..NOTMASKAS : AS NAND PS
 *  0b1001..NOTMERGEAS : AS NOR PS
 *  0b1010..XORAS : AS XOR PS
 *  0b1011..NOTXORAS : AS XNOR PS
 */
#define PXP_AS_CTRL_ROP(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)

#define PXP_AS_CTRL_ALPHA0_INVERT_MASK           (0x100000U)
#define PXP_AS_CTRL_ALPHA0_INVERT_SHIFT          (20U)
/*! ALPHA0_INVERT - ALPHA0_INVERT */
#define PXP_AS_CTRL_ALPHA0_INVERT(x)             (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA0_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA0_INVERT_MASK)

#define PXP_AS_CTRL_ALPHA1_INVERT_MASK           (0x200000U)
#define PXP_AS_CTRL_ALPHA1_INVERT_SHIFT          (21U)
/*! ALPHA1_INVERT - ALPHA1_INVERT */
#define PXP_AS_CTRL_ALPHA1_INVERT(x)             (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA1_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA1_INVERT_MASK)

#define PXP_AS_CTRL_RSVD1_MASK                   (0xFFC00000U)
#define PXP_AS_CTRL_RSVD1_SHIFT                  (22U)
/*! RSVD1 - RSVD1 */
#define PXP_AS_CTRL_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK)
/*! @} */

/*! @name AS_BUF - Alpha Surface Buffer Pointer */
/*! @{ */

#define PXP_AS_BUF_ADDR_MASK                     (0xFFFFFFFFU)
#define PXP_AS_BUF_ADDR_SHIFT                    (0U)
/*! ADDR - ADDR */
#define PXP_AS_BUF_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)
/*! @} */

/*! @name AS_PITCH - Alpha Surface Pitch */
/*! @{ */

#define PXP_AS_PITCH_PITCH_MASK                  (0xFFFFU)
#define PXP_AS_PITCH_PITCH_SHIFT                 (0U)
/*! PITCH - PITCH */
#define PXP_AS_PITCH_PITCH(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)

#define PXP_AS_PITCH_RSVD_MASK                   (0xFFFF0000U)
#define PXP_AS_PITCH_RSVD_SHIFT                  (16U)
/*! RSVD - RSVD */
#define PXP_AS_PITCH_RSVD(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK)
/*! @} */

/*! @name AS_CLRKEYLOW_0 - Overlay Color Key Low */
/*! @{ */

#define PXP_AS_CLRKEYLOW_0_PIXEL_MASK            (0xFFFFFFU)
#define PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT           (0U)
/*! PIXEL - PIXEL */
#define PXP_AS_CLRKEYLOW_0_PIXEL(x)              (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_0_PIXEL_MASK)

#define PXP_AS_CLRKEYLOW_0_RSVD1_MASK            (0xFF000000U)
#define PXP_AS_CLRKEYLOW_0_RSVD1_SHIFT           (24U)
/*! RSVD1 - RSVD1 */
#define PXP_AS_CLRKEYLOW_0_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_0_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_0_RSVD1_MASK)
/*! @} */

/*! @name AS_CLRKEYHIGH_0 - Overlay Color Key High */
/*! @{ */

#define PXP_AS_CLRKEYHIGH_0_PIXEL_MASK           (0xFFFFFFU)
#define PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT          (0U)
/*! PIXEL - PIXEL */
#define PXP_AS_CLRKEYHIGH_0_PIXEL(x)             (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_0_PIXEL_MASK)

#define PXP_AS_CLRKEYHIGH_0_RSVD1_MASK           (0xFF000000U)
#define PXP_AS_CLRKEYHIGH_0_RSVD1_SHIFT          (24U)
/*! RSVD1 - RSVD1 */
#define PXP_AS_CLRKEYHIGH_0_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_0_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_0_RSVD1_MASK)
/*! @} */

/*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */
/*! @{ */

#define PXP_CSC1_COEF0_Y_OFFSET_MASK             (0x1FFU)
#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT            (0U)
/*! Y_OFFSET - Y_OFFSET */
#define PXP_CSC1_COEF0_Y_OFFSET(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)

#define PXP_CSC1_COEF0_UV_OFFSET_MASK            (0x3FE00U)
#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT           (9U)
/*! UV_OFFSET - UV_OFFSET */
#define PXP_CSC1_COEF0_UV_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)

#define PXP_CSC1_COEF0_C0_MASK                   (0x1FFC0000U)
#define PXP_CSC1_COEF0_C0_SHIFT                  (18U)
/*! C0 - C0 */
#define PXP_CSC1_COEF0_C0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)

#define PXP_CSC1_COEF0_RSVD1_MASK                (0x20000000U)
#define PXP_CSC1_COEF0_RSVD1_SHIFT               (29U)
/*! RSVD1 - RSVD1 */
#define PXP_CSC1_COEF0_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_RSVD1_SHIFT)) & PXP_CSC1_COEF0_RSVD1_MASK)

#define PXP_CSC1_COEF0_BYPASS_MASK               (0x40000000U)
#define PXP_CSC1_COEF0_BYPASS_SHIFT              (30U)
/*! BYPASS - BYPASS */
#define PXP_CSC1_COEF0_BYPASS(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)

#define PXP_CSC1_COEF0_YCBCR_MODE_MASK           (0x80000000U)
#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT          (31U)
/*! YCBCR_MODE - YCBCR_MODE */
#define PXP_CSC1_COEF0_YCBCR_MODE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)
/*! @} */

/*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */
/*! @{ */

#define PXP_CSC1_COEF1_C4_MASK                   (0x7FFU)
#define PXP_CSC1_COEF1_C4_SHIFT                  (0U)
/*! C4 - C4 */
#define PXP_CSC1_COEF1_C4(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)

#define PXP_CSC1_COEF1_RSVD0_MASK                (0xF800U)
#define PXP_CSC1_COEF1_RSVD0_SHIFT               (11U)
/*! RSVD0 - RSVD0 */
#define PXP_CSC1_COEF1_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD0_SHIFT)) & PXP_CSC1_COEF1_RSVD0_MASK)

#define PXP_CSC1_COEF1_C1_MASK                   (0x7FF0000U)
#define PXP_CSC1_COEF1_C1_SHIFT                  (16U)
/*! C1 - C1 */
#define PXP_CSC1_COEF1_C1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)

#define PXP_CSC1_COEF1_RSVD1_MASK                (0xF8000000U)
#define PXP_CSC1_COEF1_RSVD1_SHIFT               (27U)
/*! RSVD1 - RSVD1 */
#define PXP_CSC1_COEF1_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK)
/*! @} */

/*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */
/*! @{ */

#define PXP_CSC1_COEF2_C3_MASK                   (0x7FFU)
#define PXP_CSC1_COEF2_C3_SHIFT                  (0U)
/*! C3 - C3 */
#define PXP_CSC1_COEF2_C3(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)

#define PXP_CSC1_COEF2_RSVD0_MASK                (0xF800U)
#define PXP_CSC1_COEF2_RSVD0_SHIFT               (11U)
/*! RSVD0 - RSVD0 */
#define PXP_CSC1_COEF2_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD0_SHIFT)) & PXP_CSC1_COEF2_RSVD0_MASK)

#define PXP_CSC1_COEF2_C2_MASK                   (0x7FF0000U)
#define PXP_CSC1_COEF2_C2_SHIFT                  (16U)
/*! C2 - C2 */
#define PXP_CSC1_COEF2_C2(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)

#define PXP_CSC1_COEF2_RSVD1_MASK                (0xF8000000U)
#define PXP_CSC1_COEF2_RSVD1_SHIFT               (27U)
/*! RSVD1 - RSVD1 */
#define PXP_CSC1_COEF2_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK)
/*! @} */

/*! @name CSC2_CTRL - Color Space Conversion Control Register. */
/*! @{ */

#define PXP_CSC2_CTRL_BYPASS_MASK                (0x1U)
#define PXP_CSC2_CTRL_BYPASS_SHIFT               (0U)
/*! BYPASS - BYPASS */
#define PXP_CSC2_CTRL_BYPASS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_CTRL_BYPASS_SHIFT)) & PXP_CSC2_CTRL_BYPASS_MASK)

#define PXP_CSC2_CTRL_CSC_MODE_MASK              (0x6U)
#define PXP_CSC2_CTRL_CSC_MODE_SHIFT             (1U)
/*! CSC_MODE - CSC_MODE
 *  0b00..YUV2RGB : Convert from YUV to RGB.
 *  0b01..YCbCr2RGB : Convert from YCbCr to RGB.
 *  0b10..RGB2YUV : Convert from RGB to YUV.
 *  0b11..RGB2YCbCr : Convert from RGB to YCbCr.
 */
#define PXP_CSC2_CTRL_CSC_MODE(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_CTRL_CSC_MODE_SHIFT)) & PXP_CSC2_CTRL_CSC_MODE_MASK)

#define PXP_CSC2_CTRL_RSVD_MASK                  (0xFFFFFFF8U)
#define PXP_CSC2_CTRL_RSVD_SHIFT                 (3U)
/*! RSVD - RSVD */
#define PXP_CSC2_CTRL_RSVD(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_CTRL_RSVD_SHIFT)) & PXP_CSC2_CTRL_RSVD_MASK)
/*! @} */

/*! @name CSC2_COEF0 - Color Space Conversion Coefficient Register 0 */
/*! @{ */

#define PXP_CSC2_COEF0_A1_MASK                   (0x7FFU)
#define PXP_CSC2_COEF0_A1_SHIFT                  (0U)
/*! A1 - A1 */
#define PXP_CSC2_COEF0_A1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF0_A1_SHIFT)) & PXP_CSC2_COEF0_A1_MASK)

#define PXP_CSC2_COEF0_RSVD0_MASK                (0xF800U)
#define PXP_CSC2_COEF0_RSVD0_SHIFT               (11U)
/*! RSVD0 - RSVD0 */
#define PXP_CSC2_COEF0_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF0_RSVD0_SHIFT)) & PXP_CSC2_COEF0_RSVD0_MASK)

#define PXP_CSC2_COEF0_A2_MASK                   (0x7FF0000U)
#define PXP_CSC2_COEF0_A2_SHIFT                  (16U)
/*! A2 - A2 */
#define PXP_CSC2_COEF0_A2(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF0_A2_SHIFT)) & PXP_CSC2_COEF0_A2_MASK)

#define PXP_CSC2_COEF0_RSVD1_MASK                (0xF8000000U)
#define PXP_CSC2_COEF0_RSVD1_SHIFT               (27U)
/*! RSVD1 - RSVD1 */
#define PXP_CSC2_COEF0_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF0_RSVD1_SHIFT)) & PXP_CSC2_COEF0_RSVD1_MASK)
/*! @} */

/*! @name CSC2_COEF1 - Color Space Conversion Coefficient Register 1 */
/*! @{ */

#define PXP_CSC2_COEF1_A3_MASK                   (0x7FFU)
#define PXP_CSC2_COEF1_A3_SHIFT                  (0U)
/*! A3 - A3 */
#define PXP_CSC2_COEF1_A3(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF1_A3_SHIFT)) & PXP_CSC2_COEF1_A3_MASK)

#define PXP_CSC2_COEF1_RSVD0_MASK                (0xF800U)
#define PXP_CSC2_COEF1_RSVD0_SHIFT               (11U)
/*! RSVD0 - RSVD0 */
#define PXP_CSC2_COEF1_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF1_RSVD0_SHIFT)) & PXP_CSC2_COEF1_RSVD0_MASK)

#define PXP_CSC2_COEF1_B1_MASK                   (0x7FF0000U)
#define PXP_CSC2_COEF1_B1_SHIFT                  (16U)
/*! B1 - B1 */
#define PXP_CSC2_COEF1_B1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF1_B1_SHIFT)) & PXP_CSC2_COEF1_B1_MASK)

#define PXP_CSC2_COEF1_RSVD1_MASK                (0xF8000000U)
#define PXP_CSC2_COEF1_RSVD1_SHIFT               (27U)
/*! RSVD1 - RSVD1 */
#define PXP_CSC2_COEF1_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF1_RSVD1_SHIFT)) & PXP_CSC2_COEF1_RSVD1_MASK)
/*! @} */

/*! @name CSC2_COEF2 - Color Space Conversion Coefficient Register 2 */
/*! @{ */

#define PXP_CSC2_COEF2_B2_MASK                   (0x7FFU)
#define PXP_CSC2_COEF2_B2_SHIFT                  (0U)
/*! B2 - B2 */
#define PXP_CSC2_COEF2_B2(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF2_B2_SHIFT)) & PXP_CSC2_COEF2_B2_MASK)

#define PXP_CSC2_COEF2_RSVD0_MASK                (0xF800U)
#define PXP_CSC2_COEF2_RSVD0_SHIFT               (11U)
/*! RSVD0 - RSVD0 */
#define PXP_CSC2_COEF2_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF2_RSVD0_SHIFT)) & PXP_CSC2_COEF2_RSVD0_MASK)

#define PXP_CSC2_COEF2_B3_MASK                   (0x7FF0000U)
#define PXP_CSC2_COEF2_B3_SHIFT                  (16U)
/*! B3 - B3 */
#define PXP_CSC2_COEF2_B3(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF2_B3_SHIFT)) & PXP_CSC2_COEF2_B3_MASK)

#define PXP_CSC2_COEF2_RSVD1_MASK                (0xF8000000U)
#define PXP_CSC2_COEF2_RSVD1_SHIFT               (27U)
/*! RSVD1 - RSVD1 */
#define PXP_CSC2_COEF2_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF2_RSVD1_SHIFT)) & PXP_CSC2_COEF2_RSVD1_MASK)
/*! @} */

/*! @name CSC2_COEF3 - Color Space Conversion Coefficient Register 3 */
/*! @{ */

#define PXP_CSC2_COEF3_C1_MASK                   (0x7FFU)
#define PXP_CSC2_COEF3_C1_SHIFT                  (0U)
/*! C1 - C1 */
#define PXP_CSC2_COEF3_C1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF3_C1_SHIFT)) & PXP_CSC2_COEF3_C1_MASK)

#define PXP_CSC2_COEF3_RSVD0_MASK                (0xF800U)
#define PXP_CSC2_COEF3_RSVD0_SHIFT               (11U)
/*! RSVD0 - RSVD0 */
#define PXP_CSC2_COEF3_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF3_RSVD0_SHIFT)) & PXP_CSC2_COEF3_RSVD0_MASK)

#define PXP_CSC2_COEF3_C2_MASK                   (0x7FF0000U)
#define PXP_CSC2_COEF3_C2_SHIFT                  (16U)
/*! C2 - C2 */
#define PXP_CSC2_COEF3_C2(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF3_C2_SHIFT)) & PXP_CSC2_COEF3_C2_MASK)

#define PXP_CSC2_COEF3_RSVD1_MASK                (0xF8000000U)
#define PXP_CSC2_COEF3_RSVD1_SHIFT               (27U)
/*! RSVD1 - RSVD1 */
#define PXP_CSC2_COEF3_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF3_RSVD1_SHIFT)) & PXP_CSC2_COEF3_RSVD1_MASK)
/*! @} */

/*! @name CSC2_COEF4 - Color Space Conversion Coefficient Register 4 */
/*! @{ */

#define PXP_CSC2_COEF4_C3_MASK                   (0x7FFU)
#define PXP_CSC2_COEF4_C3_SHIFT                  (0U)
/*! C3 - C3 */
#define PXP_CSC2_COEF4_C3(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF4_C3_SHIFT)) & PXP_CSC2_COEF4_C3_MASK)

#define PXP_CSC2_COEF4_RSVD0_MASK                (0xF800U)
#define PXP_CSC2_COEF4_RSVD0_SHIFT               (11U)
/*! RSVD0 - RSVD0 */
#define PXP_CSC2_COEF4_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF4_RSVD0_SHIFT)) & PXP_CSC2_COEF4_RSVD0_MASK)

#define PXP_CSC2_COEF4_D1_MASK                   (0x1FF0000U)
#define PXP_CSC2_COEF4_D1_SHIFT                  (16U)
/*! D1 - D1 */
#define PXP_CSC2_COEF4_D1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF4_D1_SHIFT)) & PXP_CSC2_COEF4_D1_MASK)

#define PXP_CSC2_COEF4_RSVD1_MASK                (0xFE000000U)
#define PXP_CSC2_COEF4_RSVD1_SHIFT               (25U)
/*! RSVD1 - RSVD1 */
#define PXP_CSC2_COEF4_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF4_RSVD1_SHIFT)) & PXP_CSC2_COEF4_RSVD1_MASK)
/*! @} */

/*! @name CSC2_COEF5 - Color Space Conversion Coefficient Register 5 */
/*! @{ */

#define PXP_CSC2_COEF5_D2_MASK                   (0x1FFU)
#define PXP_CSC2_COEF5_D2_SHIFT                  (0U)
/*! D2 - D2 */
#define PXP_CSC2_COEF5_D2(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF5_D2_SHIFT)) & PXP_CSC2_COEF5_D2_MASK)

#define PXP_CSC2_COEF5_RSVD0_MASK                (0xFE00U)
#define PXP_CSC2_COEF5_RSVD0_SHIFT               (9U)
/*! RSVD0 - RSVD0 */
#define PXP_CSC2_COEF5_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF5_RSVD0_SHIFT)) & PXP_CSC2_COEF5_RSVD0_MASK)

#define PXP_CSC2_COEF5_D3_MASK                   (0x1FF0000U)
#define PXP_CSC2_COEF5_D3_SHIFT                  (16U)
/*! D3 - D3 */
#define PXP_CSC2_COEF5_D3(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF5_D3_SHIFT)) & PXP_CSC2_COEF5_D3_MASK)

#define PXP_CSC2_COEF5_RSVD1_MASK                (0xFE000000U)
#define PXP_CSC2_COEF5_RSVD1_SHIFT               (25U)
/*! RSVD1 - RSVD1 */
#define PXP_CSC2_COEF5_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF5_RSVD1_SHIFT)) & PXP_CSC2_COEF5_RSVD1_MASK)
/*! @} */

/*! @name LUT_CTRL - Lookup Table Control Register. */
/*! @{ */

#define PXP_LUT_CTRL_DMA_START_MASK              (0x1U)
#define PXP_LUT_CTRL_DMA_START_SHIFT             (0U)
/*! DMA_START - DMA_START */
#define PXP_LUT_CTRL_DMA_START(x)                (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_DMA_START_SHIFT)) & PXP_LUT_CTRL_DMA_START_MASK)

#define PXP_LUT_CTRL_RSVD0_MASK                  (0xFEU)
#define PXP_LUT_CTRL_RSVD0_SHIFT                 (1U)
/*! RSVD0 - RSVD0 */
#define PXP_LUT_CTRL_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_RSVD0_SHIFT)) & PXP_LUT_CTRL_RSVD0_MASK)

#define PXP_LUT_CTRL_INVALID_MASK                (0x100U)
#define PXP_LUT_CTRL_INVALID_SHIFT               (8U)
/*! INVALID - INVALID */
#define PXP_LUT_CTRL_INVALID(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_INVALID_SHIFT)) & PXP_LUT_CTRL_INVALID_MASK)

#define PXP_LUT_CTRL_LRU_UPD_MASK                (0x200U)
#define PXP_LUT_CTRL_LRU_UPD_SHIFT               (9U)
/*! LRU_UPD - LRU_UPD */
#define PXP_LUT_CTRL_LRU_UPD(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_LRU_UPD_SHIFT)) & PXP_LUT_CTRL_LRU_UPD_MASK)

#define PXP_LUT_CTRL_SEL_8KB_MASK                (0x400U)
#define PXP_LUT_CTRL_SEL_8KB_SHIFT               (10U)
/*! SEL_8KB - SEL_8KB */
#define PXP_LUT_CTRL_SEL_8KB(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_SEL_8KB_SHIFT)) & PXP_LUT_CTRL_SEL_8KB_MASK)

#define PXP_LUT_CTRL_RSVD1_MASK                  (0xF800U)
#define PXP_LUT_CTRL_RSVD1_SHIFT                 (11U)
/*! RSVD1 - RSVD1 */
#define PXP_LUT_CTRL_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_RSVD1_SHIFT)) & PXP_LUT_CTRL_RSVD1_MASK)

#define PXP_LUT_CTRL_OUT_MODE_MASK               (0x30000U)
#define PXP_LUT_CTRL_OUT_MODE_SHIFT              (16U)
/*! OUT_MODE - OUT_MODE
 *  0b00..RESERVED : Reserved, not valid when using the LUT to transform pixels.
 *  0b01..Y8 : R/Y byte lane 2 lookup, bytes 1,0 bypassed.
 *  0b10..RGBW4444CFA : Byte lane 2 = CFA_Y8, byte lane 1,0 = RGBW4444.
 *  0b11..RGB888 : RGB565->RGB888 conversion for Gamma correction.
 */
#define PXP_LUT_CTRL_OUT_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_OUT_MODE_SHIFT)) & PXP_LUT_CTRL_OUT_MODE_MASK)

#define PXP_LUT_CTRL_RSVD2_MASK                  (0xFC0000U)
#define PXP_LUT_CTRL_RSVD2_SHIFT                 (18U)
/*! RSVD2 - RSVD2 */
#define PXP_LUT_CTRL_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_RSVD2_SHIFT)) & PXP_LUT_CTRL_RSVD2_MASK)

#define PXP_LUT_CTRL_LOOKUP_MODE_MASK            (0x3000000U)
#define PXP_LUT_CTRL_LOOKUP_MODE_SHIFT           (24U)
/*! LOOKUP_MODE - LOOKUP_MODE
 *  0b00..CACHE_RGB565 : LUT ADDR = R[7:3],G[7:2],B[7:3]. Use all 16KB of LUT for indirect cached 128KB lookup.
 *  0b01..DIRECT_Y8 : LUT ADDR = 16'b0,Y[7:0]. Use only the first 256 bytes of LUT. Only the Y, or third data path byte, is tranformed.
 *  0b10..DIRECT_RGB444 : LUT ADDR = R[7:4],G[7:4],B[7:4]. Use one 8KB bank of LUT selected by SEL_8KB.
 *  0b11..DIRECT_RGB454 : LUT ADDR = R[7:4],G[7:3],B[7:4]. Use all 16KB of LUT.
 */
#define PXP_LUT_CTRL_LOOKUP_MODE(x)              (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_LOOKUP_MODE_SHIFT)) & PXP_LUT_CTRL_LOOKUP_MODE_MASK)

#define PXP_LUT_CTRL_RSVD3_MASK                  (0x7C000000U)
#define PXP_LUT_CTRL_RSVD3_SHIFT                 (26U)
/*! RSVD3 - RSVD3 */
#define PXP_LUT_CTRL_RSVD3(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_RSVD3_SHIFT)) & PXP_LUT_CTRL_RSVD3_MASK)

#define PXP_LUT_CTRL_BYPASS_MASK                 (0x80000000U)
#define PXP_LUT_CTRL_BYPASS_SHIFT                (31U)
/*! BYPASS - BYPASS */
#define PXP_LUT_CTRL_BYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_BYPASS_SHIFT)) & PXP_LUT_CTRL_BYPASS_MASK)
/*! @} */

/*! @name LUT_ADDR - Lookup Table Control Register. */
/*! @{ */

#define PXP_LUT_ADDR_ADDR_MASK                   (0x3FFFU)
#define PXP_LUT_ADDR_ADDR_SHIFT                  (0U)
/*! ADDR - ADDR */
#define PXP_LUT_ADDR_ADDR(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_LUT_ADDR_ADDR_SHIFT)) & PXP_LUT_ADDR_ADDR_MASK)

#define PXP_LUT_ADDR_RSVD1_MASK                  (0xC000U)
#define PXP_LUT_ADDR_RSVD1_SHIFT                 (14U)
/*! RSVD1 - RSVD1 */
#define PXP_LUT_ADDR_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_LUT_ADDR_RSVD1_SHIFT)) & PXP_LUT_ADDR_RSVD1_MASK)

#define PXP_LUT_ADDR_NUM_BYTES_MASK              (0x7FFF0000U)
#define PXP_LUT_ADDR_NUM_BYTES_SHIFT             (16U)
/*! NUM_BYTES - NUM_BYTES */
#define PXP_LUT_ADDR_NUM_BYTES(x)                (((uint32_t)(((uint32_t)(x)) << PXP_LUT_ADDR_NUM_BYTES_SHIFT)) & PXP_LUT_ADDR_NUM_BYTES_MASK)

#define PXP_LUT_ADDR_RSVD2_MASK                  (0x80000000U)
#define PXP_LUT_ADDR_RSVD2_SHIFT                 (31U)
/*! RSVD2 - RSVD2 */
#define PXP_LUT_ADDR_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_LUT_ADDR_RSVD2_SHIFT)) & PXP_LUT_ADDR_RSVD2_MASK)
/*! @} */

/*! @name LUT_DATA - Lookup Table Data Register. */
/*! @{ */

#define PXP_LUT_DATA_DATA_MASK                   (0xFFFFFFFFU)
#define PXP_LUT_DATA_DATA_SHIFT                  (0U)
/*! DATA - DATA */
#define PXP_LUT_DATA_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_LUT_DATA_DATA_SHIFT)) & PXP_LUT_DATA_DATA_MASK)
/*! @} */

/*! @name LUT_EXTMEM - Lookup Table External Memory Address Register. */
/*! @{ */

#define PXP_LUT_EXTMEM_ADDR_MASK                 (0xFFFFFFFFU)
#define PXP_LUT_EXTMEM_ADDR_SHIFT                (0U)
/*! ADDR - ADDR */
#define PXP_LUT_EXTMEM_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_LUT_EXTMEM_ADDR_SHIFT)) & PXP_LUT_EXTMEM_ADDR_MASK)
/*! @} */

/*! @name CFA - Color Filter Array Register. */
/*! @{ */

#define PXP_CFA_DATA_MASK                        (0xFFFFFFFFU)
#define PXP_CFA_DATA_SHIFT                       (0U)
/*! DATA - DATA */
#define PXP_CFA_DATA(x)                          (((uint32_t)(((uint32_t)(x)) << PXP_CFA_DATA_SHIFT)) & PXP_CFA_DATA_MASK)
/*! @} */

/*! @name ALPHA_A_CTRL - PXP Alpha Engine A Control Register. */
/*! @{ */

#define PXP_ALPHA_A_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U)
#define PXP_ALPHA_A_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U)
/*! PORTER_DUFF_ENABLE - PORTER_DUFF_ENABLE
 *  0b0..porter duff disable.
 *  0b1..porter duff enable.
 */
#define PXP_ALPHA_A_CTRL_PORTER_DUFF_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_ALPHA_A_CTRL_PORTER_DUFF_ENABLE_MASK)

#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK  (0x6U)
#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
/*! S0_S1_FACTOR_MODE - S0_S1_FACTOR_MODE
 *  0b00..using 1.
 *  0b01..using 0.
 *  0b10..using straight alpha.
 *  0b11..using inverse alpha.
 */
#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK)

#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
/*! S0_GLOBAL_ALPHA_MODE - S0_GLOBAL_ALPHA_MODE
 *  0b00..using global alpha.
 *  0b01..using local alpha.
 *  0b10..using scaled alpha.
 *  0b11..using scaled alpha.
 */
#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)

#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_MASK      (0x20U)
#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_SHIFT     (5U)
/*! S0_ALPHA_MODE - S0_ALPHA_MODE
 *  0b0..straight mode for s0 alpha
 *  0b1..inversed mode for s0 alpha
 */
#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_MASK)

#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE_MASK      (0x40U)
#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE_SHIFT     (6U)
/*! S0_COLOR_MODE - S0_COLOR_MODE
 *  0b0..straight mode for s0 color
 *  0b1..multiply mode for s0 color
 */
#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_COLOR_MODE_MASK)

#define PXP_ALPHA_A_CTRL_RSVD1_MASK              (0x80U)
#define PXP_ALPHA_A_CTRL_RSVD1_SHIFT             (7U)
/*! RSVD1 - RSVD1 */
#define PXP_ALPHA_A_CTRL_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_RSVD1_SHIFT)) & PXP_ALPHA_A_CTRL_RSVD1_MASK)

#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK  (0x300U)
#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
/*! S1_S0_FACTOR_MODE - S1_S0_FACTOR_MODE
 *  0b00..using 1.
 *  0b01..using 0.
 *  0b10..using straight alpha.
 *  0b11..using inverse alpha.
 */
#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK)

#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
/*! S1_GLOBAL_ALPHA_MODE - S1_GLOBAL_ALPHA_MODE
 *  0b00..using global alpha.
 *  0b01..using local alpha.
 *  0b10..using scaled alpha.
 *  0b11..using scaled alpha.
 */
#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)

#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_MASK      (0x1000U)
#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_SHIFT     (12U)
/*! S1_ALPHA_MODE - S1_ALPHA_MODE
 *  0b0..straight mode for s1 alpha
 *  0b1..inversed mode for s1 alpha
 */
#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_MASK)

#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE_MASK      (0x2000U)
#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE_SHIFT     (13U)
/*! S1_COLOR_MODE - S1_COLOR_MODE
 *  0b0..straight mode for s1 color
 *  0b1..multiply mode for s1 color
 */
#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_COLOR_MODE_MASK)

#define PXP_ALPHA_A_CTRL_RSVD0_MASK              (0xC000U)
#define PXP_ALPHA_A_CTRL_RSVD0_SHIFT             (14U)
/*! RSVD0 - RSVD0 */
#define PXP_ALPHA_A_CTRL_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_RSVD0_SHIFT)) & PXP_ALPHA_A_CTRL_RSVD0_MASK)

#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK    (0xFF0000U)
#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT   (16U)
/*! S0_GLOBAL_ALPHA - S0_GLOBAL_ALPHA */
#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(x)      (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK)

#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK    (0xFF000000U)
#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT   (24U)
/*! S1_GLOBAL_ALPHA - S1_GLOBAL_ALPHA */
#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(x)      (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK)
/*! @} */

/*! @name ALPHA_B_CTRL - PXP Alpha Engine B Control Register. */
/*! @{ */

#define PXP_ALPHA_B_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U)
#define PXP_ALPHA_B_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U)
/*! PORTER_DUFF_ENABLE - PORTER_DUFF_ENABLE
 *  0b0..porter duff disable.
 *  0b1..porter duff enable.
 */
#define PXP_ALPHA_B_CTRL_PORTER_DUFF_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_ALPHA_B_CTRL_PORTER_DUFF_ENABLE_MASK)

#define PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE_MASK  (0x6U)
#define PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
/*! S0_S1_FACTOR_MODE - S0_S1_FACTOR_MODE
 *  0b00..using 1.
 *  0b01..using 0.
 *  0b10..using straight alpha.
 *  0b11..using inverse alpha.
 */
#define PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE_MASK)

#define PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
#define PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
/*! S0_GLOBAL_ALPHA_MODE - S0_GLOBAL_ALPHA_MODE
 *  0b00..using global alpha.
 *  0b01..using local alpha.
 *  0b10..using scaled alpha.
 *  0b11..using scaled alpha.
 */
#define PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)

#define PXP_ALPHA_B_CTRL_S0_ALPHA_MODE_MASK      (0x20U)
#define PXP_ALPHA_B_CTRL_S0_ALPHA_MODE_SHIFT     (5U)
/*! S0_ALPHA_MODE - S0_ALPHA_MODE
 *  0b0..straight mode for s0 alpha
 *  0b1..inversed mode for s0 alpha
 */
#define PXP_ALPHA_B_CTRL_S0_ALPHA_MODE(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_ALPHA_B_CTRL_S0_ALPHA_MODE_MASK)

#define PXP_ALPHA_B_CTRL_S0_COLOR_MODE_MASK      (0x40U)
#define PXP_ALPHA_B_CTRL_S0_COLOR_MODE_SHIFT     (6U)
/*! S0_COLOR_MODE - S0_COLOR_MODE
 *  0b0..straight mode for s0 color
 *  0b1..multiply mode for s0 color
 */
#define PXP_ALPHA_B_CTRL_S0_COLOR_MODE(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_ALPHA_B_CTRL_S0_COLOR_MODE_MASK)

#define PXP_ALPHA_B_CTRL_RSVD1_MASK              (0x80U)
#define PXP_ALPHA_B_CTRL_RSVD1_SHIFT             (7U)
/*! RSVD1 - RSVD1 */
#define PXP_ALPHA_B_CTRL_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_RSVD1_SHIFT)) & PXP_ALPHA_B_CTRL_RSVD1_MASK)

#define PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE_MASK  (0x300U)
#define PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
/*! S1_S0_FACTOR_MODE - S1_S0_FACTOR_MODE
 *  0b00..using 1.
 *  0b01..using 0.
 *  0b10..using straight alpha.
 *  0b11..using inverse alpha.
 */
#define PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE_MASK)

#define PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
#define PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
/*! S1_GLOBAL_ALPHA_MODE - S1_GLOBAL_ALPHA_MODE
 *  0b00..using global alpha.
 *  0b01..using local alpha.
 *  0b10..using scaled alpha.
 *  0b11..using scaled alpha.
 */
#define PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)

#define PXP_ALPHA_B_CTRL_S1_ALPHA_MODE_MASK      (0x1000U)
#define PXP_ALPHA_B_CTRL_S1_ALPHA_MODE_SHIFT     (12U)
/*! S1_ALPHA_MODE - S1_ALPHA_MODE
 *  0b0..straight mode for s1 alpha
 *  0b1..inversed mode for s1 alpha
 */
#define PXP_ALPHA_B_CTRL_S1_ALPHA_MODE(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_ALPHA_B_CTRL_S1_ALPHA_MODE_MASK)

#define PXP_ALPHA_B_CTRL_S1_COLOR_MODE_MASK      (0x2000U)
#define PXP_ALPHA_B_CTRL_S1_COLOR_MODE_SHIFT     (13U)
/*! S1_COLOR_MODE - S1_COLOR_MODE
 *  0b0..straight mode for s1 color
 *  0b1..multiply mode for s1 color
 */
#define PXP_ALPHA_B_CTRL_S1_COLOR_MODE(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_ALPHA_B_CTRL_S1_COLOR_MODE_MASK)

#define PXP_ALPHA_B_CTRL_RSVD0_MASK              (0xC000U)
#define PXP_ALPHA_B_CTRL_RSVD0_SHIFT             (14U)
/*! RSVD0 - RSVD0 */
#define PXP_ALPHA_B_CTRL_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_RSVD0_SHIFT)) & PXP_ALPHA_B_CTRL_RSVD0_MASK)

#define PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MASK    (0xFF0000U)
#define PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_SHIFT   (16U)
/*! S0_GLOBAL_ALPHA - S0_GLOBAL_ALPHA */
#define PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA(x)      (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MASK)

#define PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MASK    (0xFF000000U)
#define PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_SHIFT   (24U)
/*! S1_GLOBAL_ALPHA - S1_GLOBAL_ALPHA */
#define PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA(x)      (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MASK)
/*! @} */

/*! @name ALPHA_B_CTRL_1 -  */
/*! @{ */

#define PXP_ALPHA_B_CTRL_1_ROP_ENABLE_MASK       (0x1U)
#define PXP_ALPHA_B_CTRL_1_ROP_ENABLE_SHIFT      (0U)
/*! ROP_ENABLE - ROP_ENABLE */
#define PXP_ALPHA_B_CTRL_1_ROP_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_1_ROP_ENABLE_SHIFT)) & PXP_ALPHA_B_CTRL_1_ROP_ENABLE_MASK)

#define PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_MASK (0x2U)
#define PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_SHIFT (1U)
/*! OL_CLRKEY_ENABLE - OL_CLRKEY_ENABLE */
#define PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_SHIFT)) & PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_MASK)

#define PXP_ALPHA_B_CTRL_1_RSVD1_MASK            (0xCU)
#define PXP_ALPHA_B_CTRL_1_RSVD1_SHIFT           (2U)
/*! RSVD1 - RSVD1 */
#define PXP_ALPHA_B_CTRL_1_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_1_RSVD1_SHIFT)) & PXP_ALPHA_B_CTRL_1_RSVD1_MASK)

#define PXP_ALPHA_B_CTRL_1_ROP_MASK              (0xF0U)
#define PXP_ALPHA_B_CTRL_1_ROP_SHIFT             (4U)
/*! ROP - ROP
 *  0b0000..MASKAS : AS AND PS
 *  0b0001..MASKNOTAS : nAS AND PS
 *  0b0010..MASKASNOT : AS AND nPS
 *  0b0011..MERGEAS : AS OR PS
 *  0b0100..MERGENOTAS : nAS OR PS
 *  0b0101..MERGEASNOT : AS OR nPS
 *  0b0110..NOTCOPYAS : nAS
 *  0b0111..NOT : nPS
 *  0b1000..NOTMASKAS : AS NAND PS
 *  0b1001..NOTMERGEAS : AS NOR PS
 *  0b1010..XORAS : AS XOR PS
 *  0b1011..NOTXORAS : AS XNOR PS
 */
#define PXP_ALPHA_B_CTRL_1_ROP(x)                (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_1_ROP_SHIFT)) & PXP_ALPHA_B_CTRL_1_ROP_MASK)

#define PXP_ALPHA_B_CTRL_1_RSVD0_MASK            (0xFFFFFF00U)
#define PXP_ALPHA_B_CTRL_1_RSVD0_SHIFT           (8U)
/*! RSVD0 - RSVD0 */
#define PXP_ALPHA_B_CTRL_1_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_B_CTRL_1_RSVD0_SHIFT)) & PXP_ALPHA_B_CTRL_1_RSVD0_MASK)
/*! @} */

/*! @name PS_BACKGROUND_1 - PS Background Color 1 */
/*! @{ */

#define PXP_PS_BACKGROUND_1_COLOR_MASK           (0xFFFFFFU)
#define PXP_PS_BACKGROUND_1_COLOR_SHIFT          (0U)
/*! COLOR - COLOR */
#define PXP_PS_BACKGROUND_1_COLOR(x)             (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_1_COLOR_SHIFT)) & PXP_PS_BACKGROUND_1_COLOR_MASK)

#define PXP_PS_BACKGROUND_1_RSVD_MASK            (0xFF000000U)
#define PXP_PS_BACKGROUND_1_RSVD_SHIFT           (24U)
/*! RSVD - RSVD */
#define PXP_PS_BACKGROUND_1_RSVD(x)              (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_1_RSVD_SHIFT)) & PXP_PS_BACKGROUND_1_RSVD_MASK)
/*! @} */

/*! @name PS_CLRKEYLOW_1 - PS Color Key Low 1 */
/*! @{ */

#define PXP_PS_CLRKEYLOW_1_PIXEL_MASK            (0xFFFFFFU)
#define PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT           (0U)
/*! PIXEL - PIXEL */
#define PXP_PS_CLRKEYLOW_1_PIXEL(x)              (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_1_PIXEL_MASK)

#define PXP_PS_CLRKEYLOW_1_RSVD1_MASK            (0xFF000000U)
#define PXP_PS_CLRKEYLOW_1_RSVD1_SHIFT           (24U)
/*! RSVD1 - RSVD1 */
#define PXP_PS_CLRKEYLOW_1_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_1_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_1_RSVD1_MASK)
/*! @} */

/*! @name PS_CLRKEYHIGH_1 - PS Color Key High 1 */
/*! @{ */

#define PXP_PS_CLRKEYHIGH_1_PIXEL_MASK           (0xFFFFFFU)
#define PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT          (0U)
/*! PIXEL - PIXEL */
#define PXP_PS_CLRKEYHIGH_1_PIXEL(x)             (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_1_PIXEL_MASK)

#define PXP_PS_CLRKEYHIGH_1_RSVD1_MASK           (0xFF000000U)
#define PXP_PS_CLRKEYHIGH_1_RSVD1_SHIFT          (24U)
/*! RSVD1 - RSVD1 */
#define PXP_PS_CLRKEYHIGH_1_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_1_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_1_RSVD1_MASK)
/*! @} */

/*! @name AS_CLRKEYLOW_1 - Overlay Color Key Low */
/*! @{ */

#define PXP_AS_CLRKEYLOW_1_PIXEL_MASK            (0xFFFFFFU)
#define PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT           (0U)
/*! PIXEL - PIXEL */
#define PXP_AS_CLRKEYLOW_1_PIXEL(x)              (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_1_PIXEL_MASK)

#define PXP_AS_CLRKEYLOW_1_RSVD1_MASK            (0xFF000000U)
#define PXP_AS_CLRKEYLOW_1_RSVD1_SHIFT           (24U)
/*! RSVD1 - RSVD1 */
#define PXP_AS_CLRKEYLOW_1_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_1_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_1_RSVD1_MASK)
/*! @} */

/*! @name AS_CLRKEYHIGH_1 - Overlay Color Key High */
/*! @{ */

#define PXP_AS_CLRKEYHIGH_1_PIXEL_MASK           (0xFFFFFFU)
#define PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT          (0U)
/*! PIXEL - PIXEL */
#define PXP_AS_CLRKEYHIGH_1_PIXEL(x)             (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_1_PIXEL_MASK)

#define PXP_AS_CLRKEYHIGH_1_RSVD1_MASK           (0xFF000000U)
#define PXP_AS_CLRKEYHIGH_1_RSVD1_SHIFT          (24U)
/*! RSVD1 - RSVD1 */
#define PXP_AS_CLRKEYHIGH_1_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_1_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_1_RSVD1_MASK)
/*! @} */

/*! @name CTRL2 - Control Register 2 */
/*! @{ */

#define PXP_CTRL2_ENABLE_MASK                    (0x1U)
#define PXP_CTRL2_ENABLE_SHIFT                   (0U)
/*! ENABLE - ENABLE */
#define PXP_CTRL2_ENABLE(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_SHIFT)) & PXP_CTRL2_ENABLE_MASK)

#define PXP_CTRL2_RSVD0_MASK                     (0xFEU)
#define PXP_CTRL2_RSVD0_SHIFT                    (1U)
/*! RSVD0 - RSVD0 */
#define PXP_CTRL2_RSVD0(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_RSVD0_SHIFT)) & PXP_CTRL2_RSVD0_MASK)

#define PXP_CTRL2_ROTATE0_MASK                   (0x300U)
#define PXP_CTRL2_ROTATE0_SHIFT                  (8U)
/*! ROTATE0 - ROTATE0
 *  0b00..
 *  0b01..
 *  0b10..
 *  0b11..
 */
#define PXP_CTRL2_ROTATE0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ROTATE0_SHIFT)) & PXP_CTRL2_ROTATE0_MASK)

#define PXP_CTRL2_HFLIP0_MASK                    (0x400U)
#define PXP_CTRL2_HFLIP0_SHIFT                   (10U)
/*! HFLIP0 - HFLIP0 */
#define PXP_CTRL2_HFLIP0(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_HFLIP0_SHIFT)) & PXP_CTRL2_HFLIP0_MASK)

#define PXP_CTRL2_VFLIP0_MASK                    (0x800U)
#define PXP_CTRL2_VFLIP0_SHIFT                   (11U)
/*! VFLIP0 - VFLIP0 */
#define PXP_CTRL2_VFLIP0(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_VFLIP0_SHIFT)) & PXP_CTRL2_VFLIP0_MASK)

#define PXP_CTRL2_ROTATE1_MASK                   (0x3000U)
#define PXP_CTRL2_ROTATE1_SHIFT                  (12U)
/*! ROTATE1 - ROTATE1
 *  0b00..
 *  0b01..
 *  0b10..
 *  0b11..
 */
#define PXP_CTRL2_ROTATE1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ROTATE1_SHIFT)) & PXP_CTRL2_ROTATE1_MASK)

#define PXP_CTRL2_HFLIP1_MASK                    (0x4000U)
#define PXP_CTRL2_HFLIP1_SHIFT                   (14U)
/*! HFLIP1 - HFLIP1 */
#define PXP_CTRL2_HFLIP1(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_HFLIP1_SHIFT)) & PXP_CTRL2_HFLIP1_MASK)

#define PXP_CTRL2_VFLIP1_MASK                    (0x8000U)
#define PXP_CTRL2_VFLIP1_SHIFT                   (15U)
/*! VFLIP1 - VFLIP1 */
#define PXP_CTRL2_VFLIP1(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_VFLIP1_SHIFT)) & PXP_CTRL2_VFLIP1_MASK)

#define PXP_CTRL2_RSVD1_MASK                     (0x10000U)
#define PXP_CTRL2_RSVD1_SHIFT                    (16U)
/*! RSVD1 - RSVD1 */
#define PXP_CTRL2_RSVD1(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_RSVD1_SHIFT)) & PXP_CTRL2_RSVD1_MASK)

#define PXP_CTRL2_ENABLE_DITHER_MASK             (0x20000U)
#define PXP_CTRL2_ENABLE_DITHER_SHIFT            (17U)
/*! ENABLE_DITHER - ENABLE_DITHER */
#define PXP_CTRL2_ENABLE_DITHER(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_ENABLE_DITHER_MASK)

#define PXP_CTRL2_ENABLE_WFE_A_MASK              (0x40000U)
#define PXP_CTRL2_ENABLE_WFE_A_SHIFT             (18U)
/*! ENABLE_WFE_A - ENABLE_WFE_A */
#define PXP_CTRL2_ENABLE_WFE_A(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_WFE_A_SHIFT)) & PXP_CTRL2_ENABLE_WFE_A_MASK)

#define PXP_CTRL2_ENABLE_WFE_B_MASK              (0x80000U)
#define PXP_CTRL2_ENABLE_WFE_B_SHIFT             (19U)
/*! ENABLE_WFE_B - ENABLE_WFE_B */
#define PXP_CTRL2_ENABLE_WFE_B(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_ENABLE_WFE_B_MASK)

#define PXP_CTRL2_ENABLE_INPUT_FETCH_STORE_MASK  (0x100000U)
#define PXP_CTRL2_ENABLE_INPUT_FETCH_STORE_SHIFT (20U)
/*! ENABLE_INPUT_FETCH_STORE - ENABLE_INPUT_FETCH_STORE */
#define PXP_CTRL2_ENABLE_INPUT_FETCH_STORE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_INPUT_FETCH_STORE_SHIFT)) & PXP_CTRL2_ENABLE_INPUT_FETCH_STORE_MASK)

#define PXP_CTRL2_ENABLE_ALPHA_B_MASK            (0x200000U)
#define PXP_CTRL2_ENABLE_ALPHA_B_SHIFT           (21U)
/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */
#define PXP_CTRL2_ENABLE_ALPHA_B(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL2_ENABLE_ALPHA_B_MASK)

#define PXP_CTRL2_RSVD2_MASK                     (0x400000U)
#define PXP_CTRL2_RSVD2_SHIFT                    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_CTRL2_RSVD2(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_RSVD2_SHIFT)) & PXP_CTRL2_RSVD2_MASK)

#define PXP_CTRL2_BLOCK_SIZE_MASK                (0x800000U)
#define PXP_CTRL2_BLOCK_SIZE_SHIFT               (23U)
/*! BLOCK_SIZE - BLOCK_SIZE
 *  0b0..BLK_SIZE_8X8 : Process 8x8 pixel blocks.
 *  0b1..BLK_SIZE_16X16 : Process 16x16 pixel blocks.
 */
#define PXP_CTRL2_BLOCK_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_BLOCK_SIZE_MASK)

#define PXP_CTRL2_ENABLE_CSC2_MASK               (0x1000000U)
#define PXP_CTRL2_ENABLE_CSC2_SHIFT              (24U)
/*! ENABLE_CSC2 - ENABLE_CSC2 */
#define PXP_CTRL2_ENABLE_CSC2(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_ENABLE_CSC2_MASK)

#define PXP_CTRL2_ENABLE_LUT_MASK                (0x2000000U)
#define PXP_CTRL2_ENABLE_LUT_SHIFT               (25U)
/*! ENABLE_LUT - ENABLE_LUT */
#define PXP_CTRL2_ENABLE_LUT(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_LUT_SHIFT)) & PXP_CTRL2_ENABLE_LUT_MASK)

#define PXP_CTRL2_ENABLE_ROTATE0_MASK            (0x4000000U)
#define PXP_CTRL2_ENABLE_ROTATE0_SHIFT           (26U)
/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */
#define PXP_CTRL2_ENABLE_ROTATE0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_ENABLE_ROTATE0_MASK)

#define PXP_CTRL2_ENABLE_ROTATE1_MASK            (0x8000000U)
#define PXP_CTRL2_ENABLE_ROTATE1_SHIFT           (27U)
/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */
#define PXP_CTRL2_ENABLE_ROTATE1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_ENABLE_ROTATE1_MASK)

#define PXP_CTRL2_RSVD3_MASK                     (0xF0000000U)
#define PXP_CTRL2_RSVD3_SHIFT                    (28U)
/*! RSVD3 - RSVD3 */
#define PXP_CTRL2_RSVD3(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_RSVD3_SHIFT)) & PXP_CTRL2_RSVD3_MASK)
/*! @} */

/*! @name CTRL2_SET - Control Register 2 */
/*! @{ */

#define PXP_CTRL2_SET_ENABLE_MASK                (0x1U)
#define PXP_CTRL2_SET_ENABLE_SHIFT               (0U)
/*! ENABLE - ENABLE */
#define PXP_CTRL2_SET_ENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_SHIFT)) & PXP_CTRL2_SET_ENABLE_MASK)

#define PXP_CTRL2_SET_RSVD0_MASK                 (0xFEU)
#define PXP_CTRL2_SET_RSVD0_SHIFT                (1U)
/*! RSVD0 - RSVD0 */
#define PXP_CTRL2_SET_RSVD0(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_RSVD0_SHIFT)) & PXP_CTRL2_SET_RSVD0_MASK)

#define PXP_CTRL2_SET_ROTATE0_MASK               (0x300U)
#define PXP_CTRL2_SET_ROTATE0_SHIFT              (8U)
/*! ROTATE0 - ROTATE0 */
#define PXP_CTRL2_SET_ROTATE0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ROTATE0_SHIFT)) & PXP_CTRL2_SET_ROTATE0_MASK)

#define PXP_CTRL2_SET_HFLIP0_MASK                (0x400U)
#define PXP_CTRL2_SET_HFLIP0_SHIFT               (10U)
/*! HFLIP0 - HFLIP0 */
#define PXP_CTRL2_SET_HFLIP0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_HFLIP0_SHIFT)) & PXP_CTRL2_SET_HFLIP0_MASK)

#define PXP_CTRL2_SET_VFLIP0_MASK                (0x800U)
#define PXP_CTRL2_SET_VFLIP0_SHIFT               (11U)
/*! VFLIP0 - VFLIP0 */
#define PXP_CTRL2_SET_VFLIP0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_VFLIP0_SHIFT)) & PXP_CTRL2_SET_VFLIP0_MASK)

#define PXP_CTRL2_SET_ROTATE1_MASK               (0x3000U)
#define PXP_CTRL2_SET_ROTATE1_SHIFT              (12U)
/*! ROTATE1 - ROTATE1 */
#define PXP_CTRL2_SET_ROTATE1(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ROTATE1_SHIFT)) & PXP_CTRL2_SET_ROTATE1_MASK)

#define PXP_CTRL2_SET_HFLIP1_MASK                (0x4000U)
#define PXP_CTRL2_SET_HFLIP1_SHIFT               (14U)
/*! HFLIP1 - HFLIP1 */
#define PXP_CTRL2_SET_HFLIP1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_HFLIP1_SHIFT)) & PXP_CTRL2_SET_HFLIP1_MASK)

#define PXP_CTRL2_SET_VFLIP1_MASK                (0x8000U)
#define PXP_CTRL2_SET_VFLIP1_SHIFT               (15U)
/*! VFLIP1 - VFLIP1 */
#define PXP_CTRL2_SET_VFLIP1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_VFLIP1_SHIFT)) & PXP_CTRL2_SET_VFLIP1_MASK)

#define PXP_CTRL2_SET_RSVD1_MASK                 (0x10000U)
#define PXP_CTRL2_SET_RSVD1_SHIFT                (16U)
/*! RSVD1 - RSVD1 */
#define PXP_CTRL2_SET_RSVD1(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_RSVD1_SHIFT)) & PXP_CTRL2_SET_RSVD1_MASK)

#define PXP_CTRL2_SET_ENABLE_DITHER_MASK         (0x20000U)
#define PXP_CTRL2_SET_ENABLE_DITHER_SHIFT        (17U)
/*! ENABLE_DITHER - ENABLE_DITHER */
#define PXP_CTRL2_SET_ENABLE_DITHER(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_SET_ENABLE_DITHER_MASK)

#define PXP_CTRL2_SET_ENABLE_WFE_A_MASK          (0x40000U)
#define PXP_CTRL2_SET_ENABLE_WFE_A_SHIFT         (18U)
/*! ENABLE_WFE_A - ENABLE_WFE_A */
#define PXP_CTRL2_SET_ENABLE_WFE_A(x)            (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_WFE_A_SHIFT)) & PXP_CTRL2_SET_ENABLE_WFE_A_MASK)

#define PXP_CTRL2_SET_ENABLE_WFE_B_MASK          (0x80000U)
#define PXP_CTRL2_SET_ENABLE_WFE_B_SHIFT         (19U)
/*! ENABLE_WFE_B - ENABLE_WFE_B */
#define PXP_CTRL2_SET_ENABLE_WFE_B(x)            (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_SET_ENABLE_WFE_B_MASK)

#define PXP_CTRL2_SET_ENABLE_INPUT_FETCH_STORE_MASK (0x100000U)
#define PXP_CTRL2_SET_ENABLE_INPUT_FETCH_STORE_SHIFT (20U)
/*! ENABLE_INPUT_FETCH_STORE - ENABLE_INPUT_FETCH_STORE */
#define PXP_CTRL2_SET_ENABLE_INPUT_FETCH_STORE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_INPUT_FETCH_STORE_SHIFT)) & PXP_CTRL2_SET_ENABLE_INPUT_FETCH_STORE_MASK)

#define PXP_CTRL2_SET_ENABLE_ALPHA_B_MASK        (0x200000U)
#define PXP_CTRL2_SET_ENABLE_ALPHA_B_SHIFT       (21U)
/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */
#define PXP_CTRL2_SET_ENABLE_ALPHA_B(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL2_SET_ENABLE_ALPHA_B_MASK)

#define PXP_CTRL2_SET_RSVD2_MASK                 (0x400000U)
#define PXP_CTRL2_SET_RSVD2_SHIFT                (22U)
/*! RSVD2 - RSVD2 */
#define PXP_CTRL2_SET_RSVD2(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_RSVD2_SHIFT)) & PXP_CTRL2_SET_RSVD2_MASK)

#define PXP_CTRL2_SET_BLOCK_SIZE_MASK            (0x800000U)
#define PXP_CTRL2_SET_BLOCK_SIZE_SHIFT           (23U)
/*! BLOCK_SIZE - BLOCK_SIZE */
#define PXP_CTRL2_SET_BLOCK_SIZE(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_SET_BLOCK_SIZE_MASK)

#define PXP_CTRL2_SET_ENABLE_CSC2_MASK           (0x1000000U)
#define PXP_CTRL2_SET_ENABLE_CSC2_SHIFT          (24U)
/*! ENABLE_CSC2 - ENABLE_CSC2 */
#define PXP_CTRL2_SET_ENABLE_CSC2(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_SET_ENABLE_CSC2_MASK)

#define PXP_CTRL2_SET_ENABLE_LUT_MASK            (0x2000000U)
#define PXP_CTRL2_SET_ENABLE_LUT_SHIFT           (25U)
/*! ENABLE_LUT - ENABLE_LUT */
#define PXP_CTRL2_SET_ENABLE_LUT(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_LUT_SHIFT)) & PXP_CTRL2_SET_ENABLE_LUT_MASK)

#define PXP_CTRL2_SET_ENABLE_ROTATE0_MASK        (0x4000000U)
#define PXP_CTRL2_SET_ENABLE_ROTATE0_SHIFT       (26U)
/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */
#define PXP_CTRL2_SET_ENABLE_ROTATE0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_SET_ENABLE_ROTATE0_MASK)

#define PXP_CTRL2_SET_ENABLE_ROTATE1_MASK        (0x8000000U)
#define PXP_CTRL2_SET_ENABLE_ROTATE1_SHIFT       (27U)
/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */
#define PXP_CTRL2_SET_ENABLE_ROTATE1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_SET_ENABLE_ROTATE1_MASK)

#define PXP_CTRL2_SET_RSVD3_MASK                 (0xF0000000U)
#define PXP_CTRL2_SET_RSVD3_SHIFT                (28U)
/*! RSVD3 - RSVD3 */
#define PXP_CTRL2_SET_RSVD3(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_RSVD3_SHIFT)) & PXP_CTRL2_SET_RSVD3_MASK)
/*! @} */

/*! @name CTRL2_CLR - Control Register 2 */
/*! @{ */

#define PXP_CTRL2_CLR_ENABLE_MASK                (0x1U)
#define PXP_CTRL2_CLR_ENABLE_SHIFT               (0U)
/*! ENABLE - ENABLE */
#define PXP_CTRL2_CLR_ENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_SHIFT)) & PXP_CTRL2_CLR_ENABLE_MASK)

#define PXP_CTRL2_CLR_RSVD0_MASK                 (0xFEU)
#define PXP_CTRL2_CLR_RSVD0_SHIFT                (1U)
/*! RSVD0 - RSVD0 */
#define PXP_CTRL2_CLR_RSVD0(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_RSVD0_SHIFT)) & PXP_CTRL2_CLR_RSVD0_MASK)

#define PXP_CTRL2_CLR_ROTATE0_MASK               (0x300U)
#define PXP_CTRL2_CLR_ROTATE0_SHIFT              (8U)
/*! ROTATE0 - ROTATE0 */
#define PXP_CTRL2_CLR_ROTATE0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ROTATE0_SHIFT)) & PXP_CTRL2_CLR_ROTATE0_MASK)

#define PXP_CTRL2_CLR_HFLIP0_MASK                (0x400U)
#define PXP_CTRL2_CLR_HFLIP0_SHIFT               (10U)
/*! HFLIP0 - HFLIP0 */
#define PXP_CTRL2_CLR_HFLIP0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_HFLIP0_SHIFT)) & PXP_CTRL2_CLR_HFLIP0_MASK)

#define PXP_CTRL2_CLR_VFLIP0_MASK                (0x800U)
#define PXP_CTRL2_CLR_VFLIP0_SHIFT               (11U)
/*! VFLIP0 - VFLIP0 */
#define PXP_CTRL2_CLR_VFLIP0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_VFLIP0_SHIFT)) & PXP_CTRL2_CLR_VFLIP0_MASK)

#define PXP_CTRL2_CLR_ROTATE1_MASK               (0x3000U)
#define PXP_CTRL2_CLR_ROTATE1_SHIFT              (12U)
/*! ROTATE1 - ROTATE1 */
#define PXP_CTRL2_CLR_ROTATE1(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ROTATE1_SHIFT)) & PXP_CTRL2_CLR_ROTATE1_MASK)

#define PXP_CTRL2_CLR_HFLIP1_MASK                (0x4000U)
#define PXP_CTRL2_CLR_HFLIP1_SHIFT               (14U)
/*! HFLIP1 - HFLIP1 */
#define PXP_CTRL2_CLR_HFLIP1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_HFLIP1_SHIFT)) & PXP_CTRL2_CLR_HFLIP1_MASK)

#define PXP_CTRL2_CLR_VFLIP1_MASK                (0x8000U)
#define PXP_CTRL2_CLR_VFLIP1_SHIFT               (15U)
/*! VFLIP1 - VFLIP1 */
#define PXP_CTRL2_CLR_VFLIP1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_VFLIP1_SHIFT)) & PXP_CTRL2_CLR_VFLIP1_MASK)

#define PXP_CTRL2_CLR_RSVD1_MASK                 (0x10000U)
#define PXP_CTRL2_CLR_RSVD1_SHIFT                (16U)
/*! RSVD1 - RSVD1 */
#define PXP_CTRL2_CLR_RSVD1(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_RSVD1_SHIFT)) & PXP_CTRL2_CLR_RSVD1_MASK)

#define PXP_CTRL2_CLR_ENABLE_DITHER_MASK         (0x20000U)
#define PXP_CTRL2_CLR_ENABLE_DITHER_SHIFT        (17U)
/*! ENABLE_DITHER - ENABLE_DITHER */
#define PXP_CTRL2_CLR_ENABLE_DITHER(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_CLR_ENABLE_DITHER_MASK)

#define PXP_CTRL2_CLR_ENABLE_WFE_A_MASK          (0x40000U)
#define PXP_CTRL2_CLR_ENABLE_WFE_A_SHIFT         (18U)
/*! ENABLE_WFE_A - ENABLE_WFE_A */
#define PXP_CTRL2_CLR_ENABLE_WFE_A(x)            (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_WFE_A_SHIFT)) & PXP_CTRL2_CLR_ENABLE_WFE_A_MASK)

#define PXP_CTRL2_CLR_ENABLE_WFE_B_MASK          (0x80000U)
#define PXP_CTRL2_CLR_ENABLE_WFE_B_SHIFT         (19U)
/*! ENABLE_WFE_B - ENABLE_WFE_B */
#define PXP_CTRL2_CLR_ENABLE_WFE_B(x)            (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_CLR_ENABLE_WFE_B_MASK)

#define PXP_CTRL2_CLR_ENABLE_INPUT_FETCH_STORE_MASK (0x100000U)
#define PXP_CTRL2_CLR_ENABLE_INPUT_FETCH_STORE_SHIFT (20U)
/*! ENABLE_INPUT_FETCH_STORE - ENABLE_INPUT_FETCH_STORE */
#define PXP_CTRL2_CLR_ENABLE_INPUT_FETCH_STORE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_INPUT_FETCH_STORE_SHIFT)) & PXP_CTRL2_CLR_ENABLE_INPUT_FETCH_STORE_MASK)

#define PXP_CTRL2_CLR_ENABLE_ALPHA_B_MASK        (0x200000U)
#define PXP_CTRL2_CLR_ENABLE_ALPHA_B_SHIFT       (21U)
/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */
#define PXP_CTRL2_CLR_ENABLE_ALPHA_B(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ALPHA_B_MASK)

#define PXP_CTRL2_CLR_RSVD2_MASK                 (0x400000U)
#define PXP_CTRL2_CLR_RSVD2_SHIFT                (22U)
/*! RSVD2 - RSVD2 */
#define PXP_CTRL2_CLR_RSVD2(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_RSVD2_SHIFT)) & PXP_CTRL2_CLR_RSVD2_MASK)

#define PXP_CTRL2_CLR_BLOCK_SIZE_MASK            (0x800000U)
#define PXP_CTRL2_CLR_BLOCK_SIZE_SHIFT           (23U)
/*! BLOCK_SIZE - BLOCK_SIZE */
#define PXP_CTRL2_CLR_BLOCK_SIZE(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_CLR_BLOCK_SIZE_MASK)

#define PXP_CTRL2_CLR_ENABLE_CSC2_MASK           (0x1000000U)
#define PXP_CTRL2_CLR_ENABLE_CSC2_SHIFT          (24U)
/*! ENABLE_CSC2 - ENABLE_CSC2 */
#define PXP_CTRL2_CLR_ENABLE_CSC2(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_CLR_ENABLE_CSC2_MASK)

#define PXP_CTRL2_CLR_ENABLE_LUT_MASK            (0x2000000U)
#define PXP_CTRL2_CLR_ENABLE_LUT_SHIFT           (25U)
/*! ENABLE_LUT - ENABLE_LUT */
#define PXP_CTRL2_CLR_ENABLE_LUT(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_LUT_SHIFT)) & PXP_CTRL2_CLR_ENABLE_LUT_MASK)

#define PXP_CTRL2_CLR_ENABLE_ROTATE0_MASK        (0x4000000U)
#define PXP_CTRL2_CLR_ENABLE_ROTATE0_SHIFT       (26U)
/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */
#define PXP_CTRL2_CLR_ENABLE_ROTATE0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ROTATE0_MASK)

#define PXP_CTRL2_CLR_ENABLE_ROTATE1_MASK        (0x8000000U)
#define PXP_CTRL2_CLR_ENABLE_ROTATE1_SHIFT       (27U)
/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */
#define PXP_CTRL2_CLR_ENABLE_ROTATE1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ROTATE1_MASK)

#define PXP_CTRL2_CLR_RSVD3_MASK                 (0xF0000000U)
#define PXP_CTRL2_CLR_RSVD3_SHIFT                (28U)
/*! RSVD3 - RSVD3 */
#define PXP_CTRL2_CLR_RSVD3(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_RSVD3_SHIFT)) & PXP_CTRL2_CLR_RSVD3_MASK)
/*! @} */

/*! @name CTRL2_TOG - Control Register 2 */
/*! @{ */

#define PXP_CTRL2_TOG_ENABLE_MASK                (0x1U)
#define PXP_CTRL2_TOG_ENABLE_SHIFT               (0U)
/*! ENABLE - ENABLE */
#define PXP_CTRL2_TOG_ENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_SHIFT)) & PXP_CTRL2_TOG_ENABLE_MASK)

#define PXP_CTRL2_TOG_RSVD0_MASK                 (0xFEU)
#define PXP_CTRL2_TOG_RSVD0_SHIFT                (1U)
/*! RSVD0 - RSVD0 */
#define PXP_CTRL2_TOG_RSVD0(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_RSVD0_SHIFT)) & PXP_CTRL2_TOG_RSVD0_MASK)

#define PXP_CTRL2_TOG_ROTATE0_MASK               (0x300U)
#define PXP_CTRL2_TOG_ROTATE0_SHIFT              (8U)
/*! ROTATE0 - ROTATE0 */
#define PXP_CTRL2_TOG_ROTATE0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ROTATE0_SHIFT)) & PXP_CTRL2_TOG_ROTATE0_MASK)

#define PXP_CTRL2_TOG_HFLIP0_MASK                (0x400U)
#define PXP_CTRL2_TOG_HFLIP0_SHIFT               (10U)
/*! HFLIP0 - HFLIP0 */
#define PXP_CTRL2_TOG_HFLIP0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_HFLIP0_SHIFT)) & PXP_CTRL2_TOG_HFLIP0_MASK)

#define PXP_CTRL2_TOG_VFLIP0_MASK                (0x800U)
#define PXP_CTRL2_TOG_VFLIP0_SHIFT               (11U)
/*! VFLIP0 - VFLIP0 */
#define PXP_CTRL2_TOG_VFLIP0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_VFLIP0_SHIFT)) & PXP_CTRL2_TOG_VFLIP0_MASK)

#define PXP_CTRL2_TOG_ROTATE1_MASK               (0x3000U)
#define PXP_CTRL2_TOG_ROTATE1_SHIFT              (12U)
/*! ROTATE1 - ROTATE1 */
#define PXP_CTRL2_TOG_ROTATE1(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ROTATE1_SHIFT)) & PXP_CTRL2_TOG_ROTATE1_MASK)

#define PXP_CTRL2_TOG_HFLIP1_MASK                (0x4000U)
#define PXP_CTRL2_TOG_HFLIP1_SHIFT               (14U)
/*! HFLIP1 - HFLIP1 */
#define PXP_CTRL2_TOG_HFLIP1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_HFLIP1_SHIFT)) & PXP_CTRL2_TOG_HFLIP1_MASK)

#define PXP_CTRL2_TOG_VFLIP1_MASK                (0x8000U)
#define PXP_CTRL2_TOG_VFLIP1_SHIFT               (15U)
/*! VFLIP1 - VFLIP1 */
#define PXP_CTRL2_TOG_VFLIP1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_VFLIP1_SHIFT)) & PXP_CTRL2_TOG_VFLIP1_MASK)

#define PXP_CTRL2_TOG_RSVD1_MASK                 (0x10000U)
#define PXP_CTRL2_TOG_RSVD1_SHIFT                (16U)
/*! RSVD1 - RSVD1 */
#define PXP_CTRL2_TOG_RSVD1(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_RSVD1_SHIFT)) & PXP_CTRL2_TOG_RSVD1_MASK)

#define PXP_CTRL2_TOG_ENABLE_DITHER_MASK         (0x20000U)
#define PXP_CTRL2_TOG_ENABLE_DITHER_SHIFT        (17U)
/*! ENABLE_DITHER - ENABLE_DITHER */
#define PXP_CTRL2_TOG_ENABLE_DITHER(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_TOG_ENABLE_DITHER_MASK)

#define PXP_CTRL2_TOG_ENABLE_WFE_A_MASK          (0x40000U)
#define PXP_CTRL2_TOG_ENABLE_WFE_A_SHIFT         (18U)
/*! ENABLE_WFE_A - ENABLE_WFE_A */
#define PXP_CTRL2_TOG_ENABLE_WFE_A(x)            (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_WFE_A_SHIFT)) & PXP_CTRL2_TOG_ENABLE_WFE_A_MASK)

#define PXP_CTRL2_TOG_ENABLE_WFE_B_MASK          (0x80000U)
#define PXP_CTRL2_TOG_ENABLE_WFE_B_SHIFT         (19U)
/*! ENABLE_WFE_B - ENABLE_WFE_B */
#define PXP_CTRL2_TOG_ENABLE_WFE_B(x)            (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_TOG_ENABLE_WFE_B_MASK)

#define PXP_CTRL2_TOG_ENABLE_INPUT_FETCH_STORE_MASK (0x100000U)
#define PXP_CTRL2_TOG_ENABLE_INPUT_FETCH_STORE_SHIFT (20U)
/*! ENABLE_INPUT_FETCH_STORE - ENABLE_INPUT_FETCH_STORE */
#define PXP_CTRL2_TOG_ENABLE_INPUT_FETCH_STORE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_INPUT_FETCH_STORE_SHIFT)) & PXP_CTRL2_TOG_ENABLE_INPUT_FETCH_STORE_MASK)

#define PXP_CTRL2_TOG_ENABLE_ALPHA_B_MASK        (0x200000U)
#define PXP_CTRL2_TOG_ENABLE_ALPHA_B_SHIFT       (21U)
/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */
#define PXP_CTRL2_TOG_ENABLE_ALPHA_B(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ALPHA_B_MASK)

#define PXP_CTRL2_TOG_RSVD2_MASK                 (0x400000U)
#define PXP_CTRL2_TOG_RSVD2_SHIFT                (22U)
/*! RSVD2 - RSVD2 */
#define PXP_CTRL2_TOG_RSVD2(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_RSVD2_SHIFT)) & PXP_CTRL2_TOG_RSVD2_MASK)

#define PXP_CTRL2_TOG_BLOCK_SIZE_MASK            (0x800000U)
#define PXP_CTRL2_TOG_BLOCK_SIZE_SHIFT           (23U)
/*! BLOCK_SIZE - BLOCK_SIZE */
#define PXP_CTRL2_TOG_BLOCK_SIZE(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_TOG_BLOCK_SIZE_MASK)

#define PXP_CTRL2_TOG_ENABLE_CSC2_MASK           (0x1000000U)
#define PXP_CTRL2_TOG_ENABLE_CSC2_SHIFT          (24U)
/*! ENABLE_CSC2 - ENABLE_CSC2 */
#define PXP_CTRL2_TOG_ENABLE_CSC2(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_TOG_ENABLE_CSC2_MASK)

#define PXP_CTRL2_TOG_ENABLE_LUT_MASK            (0x2000000U)
#define PXP_CTRL2_TOG_ENABLE_LUT_SHIFT           (25U)
/*! ENABLE_LUT - ENABLE_LUT */
#define PXP_CTRL2_TOG_ENABLE_LUT(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_LUT_SHIFT)) & PXP_CTRL2_TOG_ENABLE_LUT_MASK)

#define PXP_CTRL2_TOG_ENABLE_ROTATE0_MASK        (0x4000000U)
#define PXP_CTRL2_TOG_ENABLE_ROTATE0_SHIFT       (26U)
/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */
#define PXP_CTRL2_TOG_ENABLE_ROTATE0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ROTATE0_MASK)

#define PXP_CTRL2_TOG_ENABLE_ROTATE1_MASK        (0x8000000U)
#define PXP_CTRL2_TOG_ENABLE_ROTATE1_SHIFT       (27U)
/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */
#define PXP_CTRL2_TOG_ENABLE_ROTATE1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ROTATE1_MASK)

#define PXP_CTRL2_TOG_RSVD3_MASK                 (0xF0000000U)
#define PXP_CTRL2_TOG_RSVD3_SHIFT                (28U)
/*! RSVD3 - RSVD3 */
#define PXP_CTRL2_TOG_RSVD3(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_RSVD3_SHIFT)) & PXP_CTRL2_TOG_RSVD3_MASK)
/*! @} */

/*! @name POWER_REG0 - PXP Power Control Register. */
/*! @{ */

#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK (0x7U)
#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT (0U)
/*! LUT_LP_STATE_WAY0_BANK0 - LUT_LP_STATE_WAY0_BANK0
 *  0b000..NONE : Memory is not in low power state.
 *  0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention.
 */
#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK)

#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK (0x38U)
#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT (3U)
/*! LUT_LP_STATE_WAY0_BANKN - LUT_LP_STATE_WAY0_BANKN
 *  0b000..NONE : Memory is not in low power state.
 *  0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention.
 */
#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK)

#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK (0x1C0U)
#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT (6U)
/*! LUT_LP_STATE_WAY1_BANKN - LUT_LP_STATE_WAY1_BANKN
 *  0b000..NONE : Memory is not in low power state.
 *  0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention.
 */
#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK)

#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK    (0xE00U)
#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT   (9U)
/*! ROT0_MEM_LP_STATE - ROT0_MEM_LP_STATE
 *  0b000..NONE : Memory is not in low power state.
 *  0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention.
 */
#define PXP_POWER_REG0_ROT0_MEM_LP_STATE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK)

#define PXP_POWER_REG0_CTRL_MASK                 (0xFFFFF000U)
#define PXP_POWER_REG0_CTRL_SHIFT                (12U)
/*! CTRL - CTRL */
#define PXP_POWER_REG0_CTRL(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_CTRL_SHIFT)) & PXP_POWER_REG0_CTRL_MASK)
/*! @} */

/*! @name POWER_REG1 - PXP Power Control Register 1. */
/*! @{ */

#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK    (0x7U)
#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT   (0U)
/*! ROT1_MEM_LP_STATE - ROT1_MEM_LP_STATE
 *  0b000..NONE : Memory is not in low power state.
 *  0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention.
 */
#define PXP_POWER_REG1_ROT1_MEM_LP_STATE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK)

#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK (0x38U)
#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT (3U)
/*! DITH0_LUT_MEM_LP_STATE - DITH0_LUT_MEM_LP_STATE
 *  0b000..NONE : Memory is not in low power state.
 *  0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention.
 */
#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK)

#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK (0x1C0U)
#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT (6U)
/*! DITH0_ERR0_MEM_LP_STATE - DITH0_ERR0_MEM_LP_STATE
 *  0b000..NONE : Memory is not in low power state.
 *  0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention.
 */
#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK)

#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK (0xE00U)
#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT (9U)
/*! DITH0_ERR1_MEM_LP_STATE - DITH0_ERR1_MEM_LP_STATE
 *  0b000..NONE : Memory is not in low power state.
 *  0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention.
 */
#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK)

#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK (0x7000U)
#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT (12U)
/*! DITH1_LUT_MEM_LP_STATE - DITH1_LUT_MEM_LP_STATE
 *  0b000..NONE : Memory is not in low power state.
 *  0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention.
 */
#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK)

#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK (0x38000U)
#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT (15U)
/*! DITH2_LUT_MEM_LP_STATE - DITH2_LUT_MEM_LP_STATE
 *  0b000..NONE : Memory is not in low power state.
 *  0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention.
 */
#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK)

#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK   (0x1C0000U)
#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT  (18U)
/*! ALU_A_MEM_LP_STATE - ALU_A_MEM_LP_STATE
 *  0b000..NONE : Memory is not in low power state.
 *  0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention.
 */
#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK)

#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK   (0xE00000U)
#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT  (21U)
/*! ALU_B_MEM_LP_STATE - ALU_B_MEM_LP_STATE
 *  0b000..NONE : Memory is not in low power state.
 *  0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents.
 *  0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention.
 */
#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK)

#define PXP_POWER_REG1_RSVD0_MASK                (0xFF000000U)
#define PXP_POWER_REG1_RSVD0_SHIFT               (24U)
/*! RSVD0 - RSVD0 */
#define PXP_POWER_REG1_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_RSVD0_SHIFT)) & PXP_POWER_REG1_RSVD0_MASK)
/*! @} */

/*! @name DATA_PATH_CTRL0 -  */
/*! @{ */

#define PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK        (0x3U)
#define PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT       (0U)
/*! MUX0_SEL - MUX0_SEL
 *  0b00..Input from Process Surface engine.
 *  0b01..Input stage Fetch engine, Channel 0
 *  0b10..Input stage Fetch engine, Channel 1
 *  0b11..No output
 */
#define PXP_DATA_PATH_CTRL0_MUX0_SEL(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK        (0xCU)
#define PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT       (2U)
/*! MUX1_SEL - MUX1_SEL
 *  0b00..Input stage Fetch engine, Channel 0
 *  0b01..Output of the Rotation1 engine
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX1_SEL(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX2_SEL_MASK        (0x30U)
#define PXP_DATA_PATH_CTRL0_MUX2_SEL_SHIFT       (4U)
/*! MUX2_SEL - MUX2_SEL
 *  0b00..Input stage Fetch engine, Channel 1
 *  0b01..Output of the Rotation1 engine
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX2_SEL(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX2_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX2_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK        (0xC0U)
#define PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT       (6U)
/*! MUX3_SEL - MUX3_SEL
 *  0b00..Output of the CSC1 engine
 *  0b01..Output of the Rotation1 engine
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX3_SEL(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX4_SEL_MASK        (0x300U)
#define PXP_DATA_PATH_CTRL0_MUX4_SEL_SHIFT       (8U)
/*! MUX4_SEL - MUX4_SEL
 *  0b00..No output
 *  0b01..No output
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX4_SEL(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX4_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX4_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX5_SEL_MASK        (0xC00U)
#define PXP_DATA_PATH_CTRL0_MUX5_SEL_SHIFT       (10U)
/*! MUX5_SEL - MUX5_SEL
 *  0b00..Output of MUX1
 *  0b01..Output of alpha blending / color key 1
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX5_SEL(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX5_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX5_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX6_SEL_MASK        (0x3000U)
#define PXP_DATA_PATH_CTRL0_MUX6_SEL_SHIFT       (12U)
/*! MUX6_SEL - MUX6_SEL
 *  0b00..Output of alpha blending / color key 1
 *  0b01..Output of alpha blending / color key 0
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX6_SEL(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX6_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX6_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX7_SEL_MASK        (0xC000U)
#define PXP_DATA_PATH_CTRL0_MUX7_SEL_SHIFT       (14U)
/*! MUX7_SEL - MUX7_SEL
 *  0b00..Output of MUX 5
 *  0b01..Output of CSC2
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX7_SEL(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX7_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX7_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK        (0x30000U)
#define PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT       (16U)
/*! MUX8_SEL - MUX8_SEL
 *  0b00..Output of CSC2
 *  0b01..Output of alpha blending / color key 0
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX8_SEL(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK        (0xC0000U)
#define PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT       (18U)
/*! MUX9_SEL - MUX9_SEL
 *  0b00..Output of MUX 7
 *  0b01..Output of MUX 8
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX9_SEL(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX10_SEL_MASK       (0x300000U)
#define PXP_DATA_PATH_CTRL0_MUX10_SEL_SHIFT      (20U)
/*! MUX10_SEL - MUX10_SEL
 *  0b00..Output of MUX 7
 *  0b01..Output of LUT
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX10_SEL(x)         (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX10_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX10_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK       (0xC00000U)
#define PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT      (22U)
/*! MUX11_SEL - MUX11_SEL
 *  0b00..Output of LUT
 *  0b01..Output of MUX 8
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX11_SEL(x)         (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK       (0x3000000U)
#define PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT      (24U)
/*! MUX12_SEL - MUX12_SEL
 *  0b00..Output of MUX 10
 *  0b01..Output of MUX 11
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX12_SEL(x)         (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX13_SEL_MASK       (0xC000000U)
#define PXP_DATA_PATH_CTRL0_MUX13_SEL_SHIFT      (26U)
/*! MUX13_SEL - MUX13_SEL
 *  0b00..No output
 *  0b01..Input stage Fetch engine, Channel 1
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX13_SEL(x)         (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX13_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX13_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK       (0x30000000U)
#define PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT      (28U)
/*! MUX14_SEL - MUX14_SEL
 *  0b00..Output of Rotation 0.
 *  0b01..Output of MUX 11
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX14_SEL(x)         (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_MUX15_SEL_MASK       (0xC0000000U)
#define PXP_DATA_PATH_CTRL0_MUX15_SEL_SHIFT      (30U)
/*! MUX15_SEL - MUX15_SEL
 *  0b00..Output of Input fetch, Channel 0
 *  0b01..Output of MUX 10
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL0_MUX15_SEL(x)         (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX15_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX15_SEL_MASK)
/*! @} */

/*! @name DATA_PATH_CTRL0_SET -  */
/*! @{ */

#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_MASK    (0x3U)
#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_SHIFT   (0U)
/*! MUX0_SEL - MUX0_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_MASK    (0xCU)
#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_SHIFT   (2U)
/*! MUX1_SEL - MUX1_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX2_SEL_MASK    (0x30U)
#define PXP_DATA_PATH_CTRL0_SET_MUX2_SEL_SHIFT   (4U)
/*! MUX2_SEL - MUX2_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX2_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX2_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX2_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_MASK    (0xC0U)
#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_SHIFT   (6U)
/*! MUX3_SEL - MUX3_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX4_SEL_MASK    (0x300U)
#define PXP_DATA_PATH_CTRL0_SET_MUX4_SEL_SHIFT   (8U)
/*! MUX4_SEL - MUX4_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX4_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX4_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX4_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX5_SEL_MASK    (0xC00U)
#define PXP_DATA_PATH_CTRL0_SET_MUX5_SEL_SHIFT   (10U)
/*! MUX5_SEL - MUX5_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX5_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX5_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX5_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX6_SEL_MASK    (0x3000U)
#define PXP_DATA_PATH_CTRL0_SET_MUX6_SEL_SHIFT   (12U)
/*! MUX6_SEL - MUX6_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX6_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX6_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX6_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX7_SEL_MASK    (0xC000U)
#define PXP_DATA_PATH_CTRL0_SET_MUX7_SEL_SHIFT   (14U)
/*! MUX7_SEL - MUX7_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX7_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX7_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX7_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_MASK    (0x30000U)
#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_SHIFT   (16U)
/*! MUX8_SEL - MUX8_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_MASK    (0xC0000U)
#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_SHIFT   (18U)
/*! MUX9_SEL - MUX9_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX10_SEL_MASK   (0x300000U)
#define PXP_DATA_PATH_CTRL0_SET_MUX10_SEL_SHIFT  (20U)
/*! MUX10_SEL - MUX10_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX10_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX10_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX10_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_MASK   (0xC00000U)
#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_SHIFT  (22U)
/*! MUX11_SEL - MUX11_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_MASK   (0x3000000U)
#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_SHIFT  (24U)
/*! MUX12_SEL - MUX12_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX13_SEL_MASK   (0xC000000U)
#define PXP_DATA_PATH_CTRL0_SET_MUX13_SEL_SHIFT  (26U)
/*! MUX13_SEL - MUX13_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX13_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX13_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX13_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_MASK   (0x30000000U)
#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_SHIFT  (28U)
/*! MUX14_SEL - MUX14_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_SET_MUX15_SEL_MASK   (0xC0000000U)
#define PXP_DATA_PATH_CTRL0_SET_MUX15_SEL_SHIFT  (30U)
/*! MUX15_SEL - MUX15_SEL */
#define PXP_DATA_PATH_CTRL0_SET_MUX15_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX15_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX15_SEL_MASK)
/*! @} */

/*! @name DATA_PATH_CTRL0_CLR -  */
/*! @{ */

#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_MASK    (0x3U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_SHIFT   (0U)
/*! MUX0_SEL - MUX0_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_MASK    (0xCU)
#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_SHIFT   (2U)
/*! MUX1_SEL - MUX1_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX2_SEL_MASK    (0x30U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX2_SEL_SHIFT   (4U)
/*! MUX2_SEL - MUX2_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX2_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX2_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX2_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_MASK    (0xC0U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_SHIFT   (6U)
/*! MUX3_SEL - MUX3_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX4_SEL_MASK    (0x300U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX4_SEL_SHIFT   (8U)
/*! MUX4_SEL - MUX4_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX4_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX4_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX4_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX5_SEL_MASK    (0xC00U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX5_SEL_SHIFT   (10U)
/*! MUX5_SEL - MUX5_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX5_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX5_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX5_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX6_SEL_MASK    (0x3000U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX6_SEL_SHIFT   (12U)
/*! MUX6_SEL - MUX6_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX6_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX6_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX6_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX7_SEL_MASK    (0xC000U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX7_SEL_SHIFT   (14U)
/*! MUX7_SEL - MUX7_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX7_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX7_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX7_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_MASK    (0x30000U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_SHIFT   (16U)
/*! MUX8_SEL - MUX8_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_MASK    (0xC0000U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_SHIFT   (18U)
/*! MUX9_SEL - MUX9_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX10_SEL_MASK   (0x300000U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX10_SEL_SHIFT  (20U)
/*! MUX10_SEL - MUX10_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX10_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX10_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX10_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_MASK   (0xC00000U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_SHIFT  (22U)
/*! MUX11_SEL - MUX11_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_MASK   (0x3000000U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_SHIFT  (24U)
/*! MUX12_SEL - MUX12_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX13_SEL_MASK   (0xC000000U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX13_SEL_SHIFT  (26U)
/*! MUX13_SEL - MUX13_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX13_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX13_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX13_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_MASK   (0x30000000U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_SHIFT  (28U)
/*! MUX14_SEL - MUX14_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_CLR_MUX15_SEL_MASK   (0xC0000000U)
#define PXP_DATA_PATH_CTRL0_CLR_MUX15_SEL_SHIFT  (30U)
/*! MUX15_SEL - MUX15_SEL */
#define PXP_DATA_PATH_CTRL0_CLR_MUX15_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX15_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX15_SEL_MASK)
/*! @} */

/*! @name DATA_PATH_CTRL0_TOG -  */
/*! @{ */

#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_MASK    (0x3U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_SHIFT   (0U)
/*! MUX0_SEL - MUX0_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_MASK    (0xCU)
#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_SHIFT   (2U)
/*! MUX1_SEL - MUX1_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX2_SEL_MASK    (0x30U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX2_SEL_SHIFT   (4U)
/*! MUX2_SEL - MUX2_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX2_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX2_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX2_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_MASK    (0xC0U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_SHIFT   (6U)
/*! MUX3_SEL - MUX3_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX4_SEL_MASK    (0x300U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX4_SEL_SHIFT   (8U)
/*! MUX4_SEL - MUX4_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX4_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX4_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX4_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX5_SEL_MASK    (0xC00U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX5_SEL_SHIFT   (10U)
/*! MUX5_SEL - MUX5_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX5_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX5_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX5_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX6_SEL_MASK    (0x3000U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX6_SEL_SHIFT   (12U)
/*! MUX6_SEL - MUX6_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX6_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX6_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX6_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX7_SEL_MASK    (0xC000U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX7_SEL_SHIFT   (14U)
/*! MUX7_SEL - MUX7_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX7_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX7_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX7_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_MASK    (0x30000U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_SHIFT   (16U)
/*! MUX8_SEL - MUX8_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_MASK    (0xC0000U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_SHIFT   (18U)
/*! MUX9_SEL - MUX9_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX10_SEL_MASK   (0x300000U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX10_SEL_SHIFT  (20U)
/*! MUX10_SEL - MUX10_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX10_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX10_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX10_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_MASK   (0xC00000U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_SHIFT  (22U)
/*! MUX11_SEL - MUX11_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_MASK   (0x3000000U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_SHIFT  (24U)
/*! MUX12_SEL - MUX12_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX13_SEL_MASK   (0xC000000U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX13_SEL_SHIFT  (26U)
/*! MUX13_SEL - MUX13_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX13_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX13_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX13_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_MASK   (0x30000000U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_SHIFT  (28U)
/*! MUX14_SEL - MUX14_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_MASK)

#define PXP_DATA_PATH_CTRL0_TOG_MUX15_SEL_MASK   (0xC0000000U)
#define PXP_DATA_PATH_CTRL0_TOG_MUX15_SEL_SHIFT  (30U)
/*! MUX15_SEL - MUX15_SEL */
#define PXP_DATA_PATH_CTRL0_TOG_MUX15_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX15_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX15_SEL_MASK)
/*! @} */

/*! @name DATA_PATH_CTRL1 -  */
/*! @{ */

#define PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK       (0x3U)
#define PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT      (0U)
/*! MUX16_SEL - MUX16_SEL
 *  0b00..Output of ALU A Engine
 *  0b01..histogram_pixel output from output
 *  0b10..Output of ALU B Engine
 *  0b11..No output
 */
#define PXP_DATA_PATH_CTRL1_MUX16_SEL(x)         (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK)

#define PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK       (0xCU)
#define PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT      (2U)
/*! MUX17_SEL - MUX17_SEL
 *  0b00..Output of ALU A
 *  0b01..Output of ALU B
 *  0b10..No output
 *  0b11..No Output
 */
#define PXP_DATA_PATH_CTRL1_MUX17_SEL(x)         (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK)

#define PXP_DATA_PATH_CTRL1_RSVD0_MASK           (0xFFFFFFF0U)
#define PXP_DATA_PATH_CTRL1_RSVD0_SHIFT          (4U)
/*! RSVD0 - RSVD0 */
#define PXP_DATA_PATH_CTRL1_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_RSVD0_SHIFT)) & PXP_DATA_PATH_CTRL1_RSVD0_MASK)
/*! @} */

/*! @name DATA_PATH_CTRL1_SET -  */
/*! @{ */

#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_MASK   (0x3U)
#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_SHIFT  (0U)
/*! MUX16_SEL - MUX16_SEL */
#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_MASK)

#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_MASK   (0xCU)
#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_SHIFT  (2U)
/*! MUX17_SEL - MUX17_SEL */
#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_MASK)

#define PXP_DATA_PATH_CTRL1_SET_RSVD0_MASK       (0xFFFFFFF0U)
#define PXP_DATA_PATH_CTRL1_SET_RSVD0_SHIFT      (4U)
/*! RSVD0 - RSVD0 */
#define PXP_DATA_PATH_CTRL1_SET_RSVD0(x)         (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_SET_RSVD0_SHIFT)) & PXP_DATA_PATH_CTRL1_SET_RSVD0_MASK)
/*! @} */

/*! @name DATA_PATH_CTRL1_CLR -  */
/*! @{ */

#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_MASK   (0x3U)
#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_SHIFT  (0U)
/*! MUX16_SEL - MUX16_SEL */
#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_MASK)

#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_MASK   (0xCU)
#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_SHIFT  (2U)
/*! MUX17_SEL - MUX17_SEL */
#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_MASK)

#define PXP_DATA_PATH_CTRL1_CLR_RSVD0_MASK       (0xFFFFFFF0U)
#define PXP_DATA_PATH_CTRL1_CLR_RSVD0_SHIFT      (4U)
/*! RSVD0 - RSVD0 */
#define PXP_DATA_PATH_CTRL1_CLR_RSVD0(x)         (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_CLR_RSVD0_SHIFT)) & PXP_DATA_PATH_CTRL1_CLR_RSVD0_MASK)
/*! @} */

/*! @name DATA_PATH_CTRL1_TOG -  */
/*! @{ */

#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_MASK   (0x3U)
#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_SHIFT  (0U)
/*! MUX16_SEL - MUX16_SEL */
#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_MASK)

#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_MASK   (0xCU)
#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_SHIFT  (2U)
/*! MUX17_SEL - MUX17_SEL */
#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_MASK)

#define PXP_DATA_PATH_CTRL1_TOG_RSVD0_MASK       (0xFFFFFFF0U)
#define PXP_DATA_PATH_CTRL1_TOG_RSVD0_SHIFT      (4U)
/*! RSVD0 - RSVD0 */
#define PXP_DATA_PATH_CTRL1_TOG_RSVD0(x)         (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_TOG_RSVD0_SHIFT)) & PXP_DATA_PATH_CTRL1_TOG_RSVD0_MASK)
/*! @} */

/*! @name INIT_MEM_CTRL - Initialize memory buffer control Register */
/*! @{ */

#define PXP_INIT_MEM_CTRL_ADDR_MASK              (0xFFFFU)
#define PXP_INIT_MEM_CTRL_ADDR_SHIFT             (0U)
/*! ADDR - ADDR */
#define PXP_INIT_MEM_CTRL_ADDR(x)                (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_ADDR_MASK)

#define PXP_INIT_MEM_CTRL_RSVD0_MASK             (0x7FF0000U)
#define PXP_INIT_MEM_CTRL_RSVD0_SHIFT            (16U)
/*! RSVD0 - RSVD0 */
#define PXP_INIT_MEM_CTRL_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_RSVD0_SHIFT)) & PXP_INIT_MEM_CTRL_RSVD0_MASK)

#define PXP_INIT_MEM_CTRL_SELECT_MASK            (0x78000000U)
#define PXP_INIT_MEM_CTRL_SELECT_SHIFT           (27U)
/*! SELECT - SELECT
 *  0b0000..DITHER0_LUT : Select the LUT memory for access
 *  0b0001..DITHER0_ERR0 : Select the ERR0 memory for access
 *  0b0010..DITHER0_ERR1 : Select the ERR1 memory for access
 *  0b0011..DITHER1_LUT : Select the LUT memory for access
 *  0b0100..DITHER2_LUT : Select the LUT memory for access
 *  0b0101..ALU_A : Select the ALU instr memory for access
 *  0b0110..ALU_B : Select the ALU instr memory for access
 *  0b0111..WFE_A_FETCH : Select the WFE-A fetch memory for access
 *  0b1000..WFE_B_FETCH : Select the WFE-B fetch memory for access
 */
#define PXP_INIT_MEM_CTRL_SELECT(x)              (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_SELECT_MASK)

#define PXP_INIT_MEM_CTRL_START_MASK             (0x80000000U)
#define PXP_INIT_MEM_CTRL_START_SHIFT            (31U)
/*! START - START */
#define PXP_INIT_MEM_CTRL_START(x)               (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_START_SHIFT)) & PXP_INIT_MEM_CTRL_START_MASK)
/*! @} */

/*! @name INIT_MEM_CTRL_SET - Initialize memory buffer control Register */
/*! @{ */

#define PXP_INIT_MEM_CTRL_SET_ADDR_MASK          (0xFFFFU)
#define PXP_INIT_MEM_CTRL_SET_ADDR_SHIFT         (0U)
/*! ADDR - ADDR */
#define PXP_INIT_MEM_CTRL_SET_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_SET_ADDR_MASK)

#define PXP_INIT_MEM_CTRL_SET_RSVD0_MASK         (0x7FF0000U)
#define PXP_INIT_MEM_CTRL_SET_RSVD0_SHIFT        (16U)
/*! RSVD0 - RSVD0 */
#define PXP_INIT_MEM_CTRL_SET_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_RSVD0_SHIFT)) & PXP_INIT_MEM_CTRL_SET_RSVD0_MASK)

#define PXP_INIT_MEM_CTRL_SET_SELECT_MASK        (0x78000000U)
#define PXP_INIT_MEM_CTRL_SET_SELECT_SHIFT       (27U)
/*! SELECT - SELECT */
#define PXP_INIT_MEM_CTRL_SET_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_SET_SELECT_MASK)

#define PXP_INIT_MEM_CTRL_SET_START_MASK         (0x80000000U)
#define PXP_INIT_MEM_CTRL_SET_START_SHIFT        (31U)
/*! START - START */
#define PXP_INIT_MEM_CTRL_SET_START(x)           (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_START_SHIFT)) & PXP_INIT_MEM_CTRL_SET_START_MASK)
/*! @} */

/*! @name INIT_MEM_CTRL_CLR - Initialize memory buffer control Register */
/*! @{ */

#define PXP_INIT_MEM_CTRL_CLR_ADDR_MASK          (0xFFFFU)
#define PXP_INIT_MEM_CTRL_CLR_ADDR_SHIFT         (0U)
/*! ADDR - ADDR */
#define PXP_INIT_MEM_CTRL_CLR_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_ADDR_MASK)

#define PXP_INIT_MEM_CTRL_CLR_RSVD0_MASK         (0x7FF0000U)
#define PXP_INIT_MEM_CTRL_CLR_RSVD0_SHIFT        (16U)
/*! RSVD0 - RSVD0 */
#define PXP_INIT_MEM_CTRL_CLR_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_RSVD0_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_RSVD0_MASK)

#define PXP_INIT_MEM_CTRL_CLR_SELECT_MASK        (0x78000000U)
#define PXP_INIT_MEM_CTRL_CLR_SELECT_SHIFT       (27U)
/*! SELECT - SELECT */
#define PXP_INIT_MEM_CTRL_CLR_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_SELECT_MASK)

#define PXP_INIT_MEM_CTRL_CLR_START_MASK         (0x80000000U)
#define PXP_INIT_MEM_CTRL_CLR_START_SHIFT        (31U)
/*! START - START */
#define PXP_INIT_MEM_CTRL_CLR_START(x)           (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_START_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_START_MASK)
/*! @} */

/*! @name INIT_MEM_CTRL_TOG - Initialize memory buffer control Register */
/*! @{ */

#define PXP_INIT_MEM_CTRL_TOG_ADDR_MASK          (0xFFFFU)
#define PXP_INIT_MEM_CTRL_TOG_ADDR_SHIFT         (0U)
/*! ADDR - ADDR */
#define PXP_INIT_MEM_CTRL_TOG_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_ADDR_MASK)

#define PXP_INIT_MEM_CTRL_TOG_RSVD0_MASK         (0x7FF0000U)
#define PXP_INIT_MEM_CTRL_TOG_RSVD0_SHIFT        (16U)
/*! RSVD0 - RSVD0 */
#define PXP_INIT_MEM_CTRL_TOG_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_RSVD0_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_RSVD0_MASK)

#define PXP_INIT_MEM_CTRL_TOG_SELECT_MASK        (0x78000000U)
#define PXP_INIT_MEM_CTRL_TOG_SELECT_SHIFT       (27U)
/*! SELECT - SELECT */
#define PXP_INIT_MEM_CTRL_TOG_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_SELECT_MASK)

#define PXP_INIT_MEM_CTRL_TOG_START_MASK         (0x80000000U)
#define PXP_INIT_MEM_CTRL_TOG_START_SHIFT        (31U)
/*! START - START */
#define PXP_INIT_MEM_CTRL_TOG_START(x)           (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_START_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_START_MASK)
/*! @} */

/*! @name INIT_MEM_DATA - Write data Register */
/*! @{ */

#define PXP_INIT_MEM_DATA_DATA_MASK              (0xFFFFFFFFU)
#define PXP_INIT_MEM_DATA_DATA_SHIFT             (0U)
/*! DATA - DATA */
#define PXP_INIT_MEM_DATA_DATA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_DATA_DATA_SHIFT)) & PXP_INIT_MEM_DATA_DATA_MASK)
/*! @} */

/*! @name INIT_MEM_DATA_HIGH - Write data Register */
/*! @{ */

#define PXP_INIT_MEM_DATA_HIGH_DATA_MASK         (0xFFFFFFFFU)
#define PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT        (0U)
/*! DATA - DATA */
#define PXP_INIT_MEM_DATA_HIGH_DATA(x)           (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT)) & PXP_INIT_MEM_DATA_HIGH_DATA_MASK)
/*! @} */

/*! @name IRQ_MASK - PXP IRQ Mask Register */
/*! @{ */

#define PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_MASK (0x1U)
#define PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT (0U)
/*! FIRST_CH0_PREFETCH_IRQ_EN - FIRST_CH0_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_MASK (0x2U)
#define PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT (1U)
/*! FIRST_CH1_PREFETCH_IRQ_EN - FIRST_CH1_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_MASK (0x4U)
#define PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_SHIFT (2U)
/*! FIRST_CH0_STORE_IRQ_EN - FIRST_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_MASK (0x8U)
#define PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_SHIFT (3U)
/*! FIRST_CH1_STORE_IRQ_EN - FIRST_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_MASK (0x10U)
#define PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_SHIFT (4U)
/*! DITHER_CH0_PREFETCH_IRQ_EN - DITHER_CH0_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_MASK (0x20U)
#define PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_SHIFT (5U)
/*! DITHER_CH1_PREFETCH_IRQ_EN - DITHER_CH1_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_MASK (0x40U)
#define PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_SHIFT (6U)
/*! DITHER_CH0_STORE_IRQ_EN - DITHER_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN(x)  (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_MASK (0x80U)
#define PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_SHIFT (7U)
/*! DITHER_CH1_STORE_IRQ_EN - DITHER_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN(x)  (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_MASK (0x100U)
#define PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_SHIFT (8U)
/*! WFE_A_CH0_STORE_IRQ_EN - WFE_A_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_MASK (0x200U)
#define PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_SHIFT (9U)
/*! WFE_A_CH1_STORE_IRQ_EN - WFE_A_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U)
#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U)
/*! WFE_B_CH0_STORE_IRQ_EN - WFE_B_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U)
#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U)
/*! WFE_B_CH1_STORE_IRQ_EN - WFE_B_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_MASK     (0x1000U)
#define PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_SHIFT    (12U)
/*! FIRST_STORE_IRQ_EN - FIRST_STORE_IRQ_EN */
#define PXP_IRQ_MASK_FIRST_STORE_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_MASK    (0x2000U)
#define PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_SHIFT   (13U)
/*! DITHER_STORE_IRQ_EN - DITHER_STORE_IRQ_EN */
#define PXP_IRQ_MASK_DITHER_STORE_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_MASK     (0x4000U)
#define PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_SHIFT    (14U)
/*! WFE_A_STORE_IRQ_EN - WFE_A_STORE_IRQ_EN */
#define PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK     (0x8000U)
#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_SHIFT    (15U)
/*! WFE_B_STORE_IRQ_EN - WFE_B_STORE_IRQ_EN */
#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_RSVD1_MASK                  (0x7FFF0000U)
#define PXP_IRQ_MASK_RSVD1_SHIFT                 (16U)
/*! RSVD1 - RSVD1 */
#define PXP_IRQ_MASK_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_RSVD1_SHIFT)) & PXP_IRQ_MASK_RSVD1_MASK)

#define PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_MASK   (0x80000000U)
#define PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_SHIFT  (31U)
/*! COMPRESS_DONE_IRQ_EN - COMPRESS_DONE_IRQ_EN */
#define PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_MASK)
/*! @} */

/*! @name IRQ_MASK_SET - PXP IRQ Mask Register */
/*! @{ */

#define PXP_IRQ_MASK_SET_FIRST_CH0_PREFETCH_IRQ_EN_MASK (0x1U)
#define PXP_IRQ_MASK_SET_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT (0U)
/*! FIRST_CH0_PREFETCH_IRQ_EN - FIRST_CH0_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_SET_FIRST_CH0_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_FIRST_CH0_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_FIRST_CH1_PREFETCH_IRQ_EN_MASK (0x2U)
#define PXP_IRQ_MASK_SET_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT (1U)
/*! FIRST_CH1_PREFETCH_IRQ_EN - FIRST_CH1_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_SET_FIRST_CH1_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_FIRST_CH1_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_FIRST_CH0_STORE_IRQ_EN_MASK (0x4U)
#define PXP_IRQ_MASK_SET_FIRST_CH0_STORE_IRQ_EN_SHIFT (2U)
/*! FIRST_CH0_STORE_IRQ_EN - FIRST_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_SET_FIRST_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_FIRST_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_FIRST_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_FIRST_CH1_STORE_IRQ_EN_MASK (0x8U)
#define PXP_IRQ_MASK_SET_FIRST_CH1_STORE_IRQ_EN_SHIFT (3U)
/*! FIRST_CH1_STORE_IRQ_EN - FIRST_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_SET_FIRST_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_FIRST_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_FIRST_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_DITHER_CH0_PREFETCH_IRQ_EN_MASK (0x10U)
#define PXP_IRQ_MASK_SET_DITHER_CH0_PREFETCH_IRQ_EN_SHIFT (4U)
/*! DITHER_CH0_PREFETCH_IRQ_EN - DITHER_CH0_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_SET_DITHER_CH0_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_DITHER_CH0_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_DITHER_CH0_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_DITHER_CH1_PREFETCH_IRQ_EN_MASK (0x20U)
#define PXP_IRQ_MASK_SET_DITHER_CH1_PREFETCH_IRQ_EN_SHIFT (5U)
/*! DITHER_CH1_PREFETCH_IRQ_EN - DITHER_CH1_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_SET_DITHER_CH1_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_DITHER_CH1_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_DITHER_CH1_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_DITHER_CH0_STORE_IRQ_EN_MASK (0x40U)
#define PXP_IRQ_MASK_SET_DITHER_CH0_STORE_IRQ_EN_SHIFT (6U)
/*! DITHER_CH0_STORE_IRQ_EN - DITHER_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_SET_DITHER_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_DITHER_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_DITHER_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_DITHER_CH1_STORE_IRQ_EN_MASK (0x80U)
#define PXP_IRQ_MASK_SET_DITHER_CH1_STORE_IRQ_EN_SHIFT (7U)
/*! DITHER_CH1_STORE_IRQ_EN - DITHER_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_SET_DITHER_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_DITHER_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_DITHER_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_WFE_A_CH0_STORE_IRQ_EN_MASK (0x100U)
#define PXP_IRQ_MASK_SET_WFE_A_CH0_STORE_IRQ_EN_SHIFT (8U)
/*! WFE_A_CH0_STORE_IRQ_EN - WFE_A_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_SET_WFE_A_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_A_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_A_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_WFE_A_CH1_STORE_IRQ_EN_MASK (0x200U)
#define PXP_IRQ_MASK_SET_WFE_A_CH1_STORE_IRQ_EN_SHIFT (9U)
/*! WFE_A_CH1_STORE_IRQ_EN - WFE_A_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_SET_WFE_A_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_A_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_A_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U)
#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U)
/*! WFE_B_CH0_STORE_IRQ_EN - WFE_B_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U)
#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U)
/*! WFE_B_CH1_STORE_IRQ_EN - WFE_B_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_FIRST_STORE_IRQ_EN_MASK (0x1000U)
#define PXP_IRQ_MASK_SET_FIRST_STORE_IRQ_EN_SHIFT (12U)
/*! FIRST_STORE_IRQ_EN - FIRST_STORE_IRQ_EN */
#define PXP_IRQ_MASK_SET_FIRST_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_FIRST_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_FIRST_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_DITHER_STORE_IRQ_EN_MASK (0x2000U)
#define PXP_IRQ_MASK_SET_DITHER_STORE_IRQ_EN_SHIFT (13U)
/*! DITHER_STORE_IRQ_EN - DITHER_STORE_IRQ_EN */
#define PXP_IRQ_MASK_SET_DITHER_STORE_IRQ_EN(x)  (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_DITHER_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_DITHER_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_WFE_A_STORE_IRQ_EN_MASK (0x4000U)
#define PXP_IRQ_MASK_SET_WFE_A_STORE_IRQ_EN_SHIFT (14U)
/*! WFE_A_STORE_IRQ_EN - WFE_A_STORE_IRQ_EN */
#define PXP_IRQ_MASK_SET_WFE_A_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_A_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_A_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_MASK (0x8000U)
#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_SHIFT (15U)
/*! WFE_B_STORE_IRQ_EN - WFE_B_STORE_IRQ_EN */
#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_SET_RSVD1_MASK              (0x7FFF0000U)
#define PXP_IRQ_MASK_SET_RSVD1_SHIFT             (16U)
/*! RSVD1 - RSVD1 */
#define PXP_IRQ_MASK_SET_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_RSVD1_SHIFT)) & PXP_IRQ_MASK_SET_RSVD1_MASK)

#define PXP_IRQ_MASK_SET_COMPRESS_DONE_IRQ_EN_MASK (0x80000000U)
#define PXP_IRQ_MASK_SET_COMPRESS_DONE_IRQ_EN_SHIFT (31U)
/*! COMPRESS_DONE_IRQ_EN - COMPRESS_DONE_IRQ_EN */
#define PXP_IRQ_MASK_SET_COMPRESS_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_COMPRESS_DONE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_COMPRESS_DONE_IRQ_EN_MASK)
/*! @} */

/*! @name IRQ_MASK_CLR - PXP IRQ Mask Register */
/*! @{ */

#define PXP_IRQ_MASK_CLR_FIRST_CH0_PREFETCH_IRQ_EN_MASK (0x1U)
#define PXP_IRQ_MASK_CLR_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT (0U)
/*! FIRST_CH0_PREFETCH_IRQ_EN - FIRST_CH0_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_CLR_FIRST_CH0_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_FIRST_CH0_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_FIRST_CH1_PREFETCH_IRQ_EN_MASK (0x2U)
#define PXP_IRQ_MASK_CLR_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT (1U)
/*! FIRST_CH1_PREFETCH_IRQ_EN - FIRST_CH1_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_CLR_FIRST_CH1_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_FIRST_CH1_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_FIRST_CH0_STORE_IRQ_EN_MASK (0x4U)
#define PXP_IRQ_MASK_CLR_FIRST_CH0_STORE_IRQ_EN_SHIFT (2U)
/*! FIRST_CH0_STORE_IRQ_EN - FIRST_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_CLR_FIRST_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_FIRST_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_FIRST_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_FIRST_CH1_STORE_IRQ_EN_MASK (0x8U)
#define PXP_IRQ_MASK_CLR_FIRST_CH1_STORE_IRQ_EN_SHIFT (3U)
/*! FIRST_CH1_STORE_IRQ_EN - FIRST_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_CLR_FIRST_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_FIRST_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_FIRST_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_DITHER_CH0_PREFETCH_IRQ_EN_MASK (0x10U)
#define PXP_IRQ_MASK_CLR_DITHER_CH0_PREFETCH_IRQ_EN_SHIFT (4U)
/*! DITHER_CH0_PREFETCH_IRQ_EN - DITHER_CH0_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_CLR_DITHER_CH0_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_DITHER_CH0_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_DITHER_CH0_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_DITHER_CH1_PREFETCH_IRQ_EN_MASK (0x20U)
#define PXP_IRQ_MASK_CLR_DITHER_CH1_PREFETCH_IRQ_EN_SHIFT (5U)
/*! DITHER_CH1_PREFETCH_IRQ_EN - DITHER_CH1_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_CLR_DITHER_CH1_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_DITHER_CH1_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_DITHER_CH1_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_DITHER_CH0_STORE_IRQ_EN_MASK (0x40U)
#define PXP_IRQ_MASK_CLR_DITHER_CH0_STORE_IRQ_EN_SHIFT (6U)
/*! DITHER_CH0_STORE_IRQ_EN - DITHER_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_CLR_DITHER_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_DITHER_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_DITHER_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_DITHER_CH1_STORE_IRQ_EN_MASK (0x80U)
#define PXP_IRQ_MASK_CLR_DITHER_CH1_STORE_IRQ_EN_SHIFT (7U)
/*! DITHER_CH1_STORE_IRQ_EN - DITHER_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_CLR_DITHER_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_DITHER_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_DITHER_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_WFE_A_CH0_STORE_IRQ_EN_MASK (0x100U)
#define PXP_IRQ_MASK_CLR_WFE_A_CH0_STORE_IRQ_EN_SHIFT (8U)
/*! WFE_A_CH0_STORE_IRQ_EN - WFE_A_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_CLR_WFE_A_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_A_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_A_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_WFE_A_CH1_STORE_IRQ_EN_MASK (0x200U)
#define PXP_IRQ_MASK_CLR_WFE_A_CH1_STORE_IRQ_EN_SHIFT (9U)
/*! WFE_A_CH1_STORE_IRQ_EN - WFE_A_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_CLR_WFE_A_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_A_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_A_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U)
#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U)
/*! WFE_B_CH0_STORE_IRQ_EN - WFE_B_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U)
#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U)
/*! WFE_B_CH1_STORE_IRQ_EN - WFE_B_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_FIRST_STORE_IRQ_EN_MASK (0x1000U)
#define PXP_IRQ_MASK_CLR_FIRST_STORE_IRQ_EN_SHIFT (12U)
/*! FIRST_STORE_IRQ_EN - FIRST_STORE_IRQ_EN */
#define PXP_IRQ_MASK_CLR_FIRST_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_FIRST_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_FIRST_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_DITHER_STORE_IRQ_EN_MASK (0x2000U)
#define PXP_IRQ_MASK_CLR_DITHER_STORE_IRQ_EN_SHIFT (13U)
/*! DITHER_STORE_IRQ_EN - DITHER_STORE_IRQ_EN */
#define PXP_IRQ_MASK_CLR_DITHER_STORE_IRQ_EN(x)  (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_DITHER_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_DITHER_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_WFE_A_STORE_IRQ_EN_MASK (0x4000U)
#define PXP_IRQ_MASK_CLR_WFE_A_STORE_IRQ_EN_SHIFT (14U)
/*! WFE_A_STORE_IRQ_EN - WFE_A_STORE_IRQ_EN */
#define PXP_IRQ_MASK_CLR_WFE_A_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_A_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_A_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_MASK (0x8000U)
#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_SHIFT (15U)
/*! WFE_B_STORE_IRQ_EN - WFE_B_STORE_IRQ_EN */
#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_CLR_RSVD1_MASK              (0x7FFF0000U)
#define PXP_IRQ_MASK_CLR_RSVD1_SHIFT             (16U)
/*! RSVD1 - RSVD1 */
#define PXP_IRQ_MASK_CLR_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_RSVD1_SHIFT)) & PXP_IRQ_MASK_CLR_RSVD1_MASK)

#define PXP_IRQ_MASK_CLR_COMPRESS_DONE_IRQ_EN_MASK (0x80000000U)
#define PXP_IRQ_MASK_CLR_COMPRESS_DONE_IRQ_EN_SHIFT (31U)
/*! COMPRESS_DONE_IRQ_EN - COMPRESS_DONE_IRQ_EN */
#define PXP_IRQ_MASK_CLR_COMPRESS_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_COMPRESS_DONE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_COMPRESS_DONE_IRQ_EN_MASK)
/*! @} */

/*! @name IRQ_MASK_TOG - PXP IRQ Mask Register */
/*! @{ */

#define PXP_IRQ_MASK_TOG_FIRST_CH0_PREFETCH_IRQ_EN_MASK (0x1U)
#define PXP_IRQ_MASK_TOG_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT (0U)
/*! FIRST_CH0_PREFETCH_IRQ_EN - FIRST_CH0_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_TOG_FIRST_CH0_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_FIRST_CH0_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_FIRST_CH1_PREFETCH_IRQ_EN_MASK (0x2U)
#define PXP_IRQ_MASK_TOG_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT (1U)
/*! FIRST_CH1_PREFETCH_IRQ_EN - FIRST_CH1_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_TOG_FIRST_CH1_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_FIRST_CH1_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_FIRST_CH0_STORE_IRQ_EN_MASK (0x4U)
#define PXP_IRQ_MASK_TOG_FIRST_CH0_STORE_IRQ_EN_SHIFT (2U)
/*! FIRST_CH0_STORE_IRQ_EN - FIRST_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_TOG_FIRST_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_FIRST_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_FIRST_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_FIRST_CH1_STORE_IRQ_EN_MASK (0x8U)
#define PXP_IRQ_MASK_TOG_FIRST_CH1_STORE_IRQ_EN_SHIFT (3U)
/*! FIRST_CH1_STORE_IRQ_EN - FIRST_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_TOG_FIRST_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_FIRST_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_FIRST_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_DITHER_CH0_PREFETCH_IRQ_EN_MASK (0x10U)
#define PXP_IRQ_MASK_TOG_DITHER_CH0_PREFETCH_IRQ_EN_SHIFT (4U)
/*! DITHER_CH0_PREFETCH_IRQ_EN - DITHER_CH0_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_TOG_DITHER_CH0_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_DITHER_CH0_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_DITHER_CH0_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_DITHER_CH1_PREFETCH_IRQ_EN_MASK (0x20U)
#define PXP_IRQ_MASK_TOG_DITHER_CH1_PREFETCH_IRQ_EN_SHIFT (5U)
/*! DITHER_CH1_PREFETCH_IRQ_EN - DITHER_CH1_PREFETCH_IRQ_EN */
#define PXP_IRQ_MASK_TOG_DITHER_CH1_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_DITHER_CH1_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_DITHER_CH1_PREFETCH_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_DITHER_CH0_STORE_IRQ_EN_MASK (0x40U)
#define PXP_IRQ_MASK_TOG_DITHER_CH0_STORE_IRQ_EN_SHIFT (6U)
/*! DITHER_CH0_STORE_IRQ_EN - DITHER_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_TOG_DITHER_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_DITHER_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_DITHER_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_DITHER_CH1_STORE_IRQ_EN_MASK (0x80U)
#define PXP_IRQ_MASK_TOG_DITHER_CH1_STORE_IRQ_EN_SHIFT (7U)
/*! DITHER_CH1_STORE_IRQ_EN - DITHER_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_TOG_DITHER_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_DITHER_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_DITHER_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_WFE_A_CH0_STORE_IRQ_EN_MASK (0x100U)
#define PXP_IRQ_MASK_TOG_WFE_A_CH0_STORE_IRQ_EN_SHIFT (8U)
/*! WFE_A_CH0_STORE_IRQ_EN - WFE_A_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_TOG_WFE_A_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_A_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_A_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_WFE_A_CH1_STORE_IRQ_EN_MASK (0x200U)
#define PXP_IRQ_MASK_TOG_WFE_A_CH1_STORE_IRQ_EN_SHIFT (9U)
/*! WFE_A_CH1_STORE_IRQ_EN - WFE_A_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_TOG_WFE_A_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_A_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_A_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U)
#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U)
/*! WFE_B_CH0_STORE_IRQ_EN - WFE_B_CH0_STORE_IRQ_EN */
#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U)
#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U)
/*! WFE_B_CH1_STORE_IRQ_EN - WFE_B_CH1_STORE_IRQ_EN */
#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_FIRST_STORE_IRQ_EN_MASK (0x1000U)
#define PXP_IRQ_MASK_TOG_FIRST_STORE_IRQ_EN_SHIFT (12U)
/*! FIRST_STORE_IRQ_EN - FIRST_STORE_IRQ_EN */
#define PXP_IRQ_MASK_TOG_FIRST_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_FIRST_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_FIRST_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_DITHER_STORE_IRQ_EN_MASK (0x2000U)
#define PXP_IRQ_MASK_TOG_DITHER_STORE_IRQ_EN_SHIFT (13U)
/*! DITHER_STORE_IRQ_EN - DITHER_STORE_IRQ_EN */
#define PXP_IRQ_MASK_TOG_DITHER_STORE_IRQ_EN(x)  (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_DITHER_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_DITHER_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_WFE_A_STORE_IRQ_EN_MASK (0x4000U)
#define PXP_IRQ_MASK_TOG_WFE_A_STORE_IRQ_EN_SHIFT (14U)
/*! WFE_A_STORE_IRQ_EN - WFE_A_STORE_IRQ_EN */
#define PXP_IRQ_MASK_TOG_WFE_A_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_A_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_A_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_MASK (0x8000U)
#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_SHIFT (15U)
/*! WFE_B_STORE_IRQ_EN - WFE_B_STORE_IRQ_EN */
#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_MASK)

#define PXP_IRQ_MASK_TOG_RSVD1_MASK              (0x7FFF0000U)
#define PXP_IRQ_MASK_TOG_RSVD1_SHIFT             (16U)
/*! RSVD1 - RSVD1 */
#define PXP_IRQ_MASK_TOG_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_RSVD1_SHIFT)) & PXP_IRQ_MASK_TOG_RSVD1_MASK)

#define PXP_IRQ_MASK_TOG_COMPRESS_DONE_IRQ_EN_MASK (0x80000000U)
#define PXP_IRQ_MASK_TOG_COMPRESS_DONE_IRQ_EN_SHIFT (31U)
/*! COMPRESS_DONE_IRQ_EN - COMPRESS_DONE_IRQ_EN */
#define PXP_IRQ_MASK_TOG_COMPRESS_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_COMPRESS_DONE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_COMPRESS_DONE_IRQ_EN_MASK)
/*! @} */

/*! @name IRQ - PXP Interrupt Register */
/*! @{ */

#define PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_MASK      (0x1U)
#define PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_SHIFT     (0U)
/*! FIRST_CH0_PREFETCH_IRQ - FIRST_CH0_PREFETCH_IRQ */
#define PXP_IRQ_FIRST_CH0_PREFETCH_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_MASK)

#define PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_MASK      (0x2U)
#define PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_SHIFT     (1U)
/*! FIRST_CH1_PREFETCH_IRQ - FIRST_CH1_PREFETCH_IRQ */
#define PXP_IRQ_FIRST_CH1_PREFETCH_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_MASK)

#define PXP_IRQ_FIRST_CH0_STORE_IRQ_MASK         (0x4U)
#define PXP_IRQ_FIRST_CH0_STORE_IRQ_SHIFT        (2U)
/*! FIRST_CH0_STORE_IRQ - FIRST_CH0_STORE_IRQ */
#define PXP_IRQ_FIRST_CH0_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_FIRST_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_FIRST_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_FIRST_CH1_STORE_IRQ_MASK         (0x8U)
#define PXP_IRQ_FIRST_CH1_STORE_IRQ_SHIFT        (3U)
/*! FIRST_CH1_STORE_IRQ - FIRST_CH1_STORE_IRQ */
#define PXP_IRQ_FIRST_CH1_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_FIRST_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_FIRST_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_MASK     (0x10U)
#define PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_SHIFT    (4U)
/*! DITHER_CH0_PREFETCH_IRQ - DITHER_CH0_PREFETCH_IRQ */
#define PXP_IRQ_DITHER_CH0_PREFETCH_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_MASK)

#define PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_MASK     (0x20U)
#define PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_SHIFT    (5U)
/*! DITHER_CH1_PREFETCH_IRQ - DITHER_CH1_PREFETCH_IRQ */
#define PXP_IRQ_DITHER_CH1_PREFETCH_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_MASK)

#define PXP_IRQ_DITHER_CH0_STORE_IRQ_MASK        (0x40U)
#define PXP_IRQ_DITHER_CH0_STORE_IRQ_SHIFT       (6U)
/*! DITHER_CH0_STORE_IRQ - DITHER_CH0_STORE_IRQ */
#define PXP_IRQ_DITHER_CH0_STORE_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_DITHER_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_DITHER_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_DITHER_CH1_STORE_IRQ_MASK        (0x80U)
#define PXP_IRQ_DITHER_CH1_STORE_IRQ_SHIFT       (7U)
/*! DITHER_CH1_STORE_IRQ - DITHER_CH1_STORE_IRQ */
#define PXP_IRQ_DITHER_CH1_STORE_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_DITHER_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_DITHER_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_WFE_A_CH0_STORE_IRQ_MASK         (0x100U)
#define PXP_IRQ_WFE_A_CH0_STORE_IRQ_SHIFT        (8U)
/*! WFE_A_CH0_STORE_IRQ - WFE_A_CH0_STORE_IRQ */
#define PXP_IRQ_WFE_A_CH0_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_A_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_A_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_WFE_A_CH1_STORE_IRQ_MASK         (0x200U)
#define PXP_IRQ_WFE_A_CH1_STORE_IRQ_SHIFT        (9U)
/*! WFE_A_CH1_STORE_IRQ - WFE_A_CH1_STORE_IRQ */
#define PXP_IRQ_WFE_A_CH1_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_A_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_A_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK         (0x400U)
#define PXP_IRQ_WFE_B_CH0_STORE_IRQ_SHIFT        (10U)
/*! WFE_B_CH0_STORE_IRQ - WFE_B_CH0_STORE_IRQ */
#define PXP_IRQ_WFE_B_CH0_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK         (0x800U)
#define PXP_IRQ_WFE_B_CH1_STORE_IRQ_SHIFT        (11U)
/*! WFE_B_CH1_STORE_IRQ - WFE_B_CH1_STORE_IRQ */
#define PXP_IRQ_WFE_B_CH1_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_FIRST_STORE_IRQ_MASK             (0x1000U)
#define PXP_IRQ_FIRST_STORE_IRQ_SHIFT            (12U)
/*! FIRST_STORE_IRQ - FIRST_STORE_IRQ */
#define PXP_IRQ_FIRST_STORE_IRQ(x)               (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_FIRST_STORE_IRQ_SHIFT)) & PXP_IRQ_FIRST_STORE_IRQ_MASK)

#define PXP_IRQ_DITHER_STORE_IRQ_MASK            (0x2000U)
#define PXP_IRQ_DITHER_STORE_IRQ_SHIFT           (13U)
/*! DITHER_STORE_IRQ - DITHER_STORE_IRQ */
#define PXP_IRQ_DITHER_STORE_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_DITHER_STORE_IRQ_SHIFT)) & PXP_IRQ_DITHER_STORE_IRQ_MASK)

#define PXP_IRQ_WFE_A_STORE_IRQ_MASK             (0x4000U)
#define PXP_IRQ_WFE_A_STORE_IRQ_SHIFT            (14U)
/*! WFE_A_STORE_IRQ - WFE_A_STORE_IRQ */
#define PXP_IRQ_WFE_A_STORE_IRQ(x)               (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_A_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_A_STORE_IRQ_MASK)

#define PXP_IRQ_WFE_B_STORE_IRQ_MASK             (0x8000U)
#define PXP_IRQ_WFE_B_STORE_IRQ_SHIFT            (15U)
/*! WFE_B_STORE_IRQ - WFE_B_STORE_IRQ */
#define PXP_IRQ_WFE_B_STORE_IRQ(x)               (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_STORE_IRQ_MASK)

#define PXP_IRQ_RSVD1_MASK                       (0x7FFF0000U)
#define PXP_IRQ_RSVD1_SHIFT                      (16U)
/*! RSVD1 - RSVD1 */
#define PXP_IRQ_RSVD1(x)                         (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_RSVD1_SHIFT)) & PXP_IRQ_RSVD1_MASK)

#define PXP_IRQ_COMPRESS_DONE_IRQ_MASK           (0x80000000U)
#define PXP_IRQ_COMPRESS_DONE_IRQ_SHIFT          (31U)
/*! COMPRESS_DONE_IRQ - COMPRESS_DONE_IRQ */
#define PXP_IRQ_COMPRESS_DONE_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_COMPRESS_DONE_IRQ_SHIFT)) & PXP_IRQ_COMPRESS_DONE_IRQ_MASK)
/*! @} */

/*! @name IRQ_SET - PXP Interrupt Register */
/*! @{ */

#define PXP_IRQ_SET_FIRST_CH0_PREFETCH_IRQ_MASK  (0x1U)
#define PXP_IRQ_SET_FIRST_CH0_PREFETCH_IRQ_SHIFT (0U)
/*! FIRST_CH0_PREFETCH_IRQ - FIRST_CH0_PREFETCH_IRQ */
#define PXP_IRQ_SET_FIRST_CH0_PREFETCH_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_FIRST_CH0_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_SET_FIRST_CH0_PREFETCH_IRQ_MASK)

#define PXP_IRQ_SET_FIRST_CH1_PREFETCH_IRQ_MASK  (0x2U)
#define PXP_IRQ_SET_FIRST_CH1_PREFETCH_IRQ_SHIFT (1U)
/*! FIRST_CH1_PREFETCH_IRQ - FIRST_CH1_PREFETCH_IRQ */
#define PXP_IRQ_SET_FIRST_CH1_PREFETCH_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_FIRST_CH1_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_SET_FIRST_CH1_PREFETCH_IRQ_MASK)

#define PXP_IRQ_SET_FIRST_CH0_STORE_IRQ_MASK     (0x4U)
#define PXP_IRQ_SET_FIRST_CH0_STORE_IRQ_SHIFT    (2U)
/*! FIRST_CH0_STORE_IRQ - FIRST_CH0_STORE_IRQ */
#define PXP_IRQ_SET_FIRST_CH0_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_FIRST_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_FIRST_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_SET_FIRST_CH1_STORE_IRQ_MASK     (0x8U)
#define PXP_IRQ_SET_FIRST_CH1_STORE_IRQ_SHIFT    (3U)
/*! FIRST_CH1_STORE_IRQ - FIRST_CH1_STORE_IRQ */
#define PXP_IRQ_SET_FIRST_CH1_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_FIRST_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_FIRST_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_SET_DITHER_CH0_PREFETCH_IRQ_MASK (0x10U)
#define PXP_IRQ_SET_DITHER_CH0_PREFETCH_IRQ_SHIFT (4U)
/*! DITHER_CH0_PREFETCH_IRQ - DITHER_CH0_PREFETCH_IRQ */
#define PXP_IRQ_SET_DITHER_CH0_PREFETCH_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_DITHER_CH0_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_SET_DITHER_CH0_PREFETCH_IRQ_MASK)

#define PXP_IRQ_SET_DITHER_CH1_PREFETCH_IRQ_MASK (0x20U)
#define PXP_IRQ_SET_DITHER_CH1_PREFETCH_IRQ_SHIFT (5U)
/*! DITHER_CH1_PREFETCH_IRQ - DITHER_CH1_PREFETCH_IRQ */
#define PXP_IRQ_SET_DITHER_CH1_PREFETCH_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_DITHER_CH1_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_SET_DITHER_CH1_PREFETCH_IRQ_MASK)

#define PXP_IRQ_SET_DITHER_CH0_STORE_IRQ_MASK    (0x40U)
#define PXP_IRQ_SET_DITHER_CH0_STORE_IRQ_SHIFT   (6U)
/*! DITHER_CH0_STORE_IRQ - DITHER_CH0_STORE_IRQ */
#define PXP_IRQ_SET_DITHER_CH0_STORE_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_DITHER_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_DITHER_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_SET_DITHER_CH1_STORE_IRQ_MASK    (0x80U)
#define PXP_IRQ_SET_DITHER_CH1_STORE_IRQ_SHIFT   (7U)
/*! DITHER_CH1_STORE_IRQ - DITHER_CH1_STORE_IRQ */
#define PXP_IRQ_SET_DITHER_CH1_STORE_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_DITHER_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_DITHER_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_SET_WFE_A_CH0_STORE_IRQ_MASK     (0x100U)
#define PXP_IRQ_SET_WFE_A_CH0_STORE_IRQ_SHIFT    (8U)
/*! WFE_A_CH0_STORE_IRQ - WFE_A_CH0_STORE_IRQ */
#define PXP_IRQ_SET_WFE_A_CH0_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_A_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_A_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_SET_WFE_A_CH1_STORE_IRQ_MASK     (0x200U)
#define PXP_IRQ_SET_WFE_A_CH1_STORE_IRQ_SHIFT    (9U)
/*! WFE_A_CH1_STORE_IRQ - WFE_A_CH1_STORE_IRQ */
#define PXP_IRQ_SET_WFE_A_CH1_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_A_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_A_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_MASK     (0x400U)
#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_SHIFT    (10U)
/*! WFE_B_CH0_STORE_IRQ - WFE_B_CH0_STORE_IRQ */
#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_MASK     (0x800U)
#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_SHIFT    (11U)
/*! WFE_B_CH1_STORE_IRQ - WFE_B_CH1_STORE_IRQ */
#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_SET_FIRST_STORE_IRQ_MASK         (0x1000U)
#define PXP_IRQ_SET_FIRST_STORE_IRQ_SHIFT        (12U)
/*! FIRST_STORE_IRQ - FIRST_STORE_IRQ */
#define PXP_IRQ_SET_FIRST_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_FIRST_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_FIRST_STORE_IRQ_MASK)

#define PXP_IRQ_SET_DITHER_STORE_IRQ_MASK        (0x2000U)
#define PXP_IRQ_SET_DITHER_STORE_IRQ_SHIFT       (13U)
/*! DITHER_STORE_IRQ - DITHER_STORE_IRQ */
#define PXP_IRQ_SET_DITHER_STORE_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_DITHER_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_DITHER_STORE_IRQ_MASK)

#define PXP_IRQ_SET_WFE_A_STORE_IRQ_MASK         (0x4000U)
#define PXP_IRQ_SET_WFE_A_STORE_IRQ_SHIFT        (14U)
/*! WFE_A_STORE_IRQ - WFE_A_STORE_IRQ */
#define PXP_IRQ_SET_WFE_A_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_A_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_A_STORE_IRQ_MASK)

#define PXP_IRQ_SET_WFE_B_STORE_IRQ_MASK         (0x8000U)
#define PXP_IRQ_SET_WFE_B_STORE_IRQ_SHIFT        (15U)
/*! WFE_B_STORE_IRQ - WFE_B_STORE_IRQ */
#define PXP_IRQ_SET_WFE_B_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_STORE_IRQ_MASK)

#define PXP_IRQ_SET_RSVD1_MASK                   (0x7FFF0000U)
#define PXP_IRQ_SET_RSVD1_SHIFT                  (16U)
/*! RSVD1 - RSVD1 */
#define PXP_IRQ_SET_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_RSVD1_SHIFT)) & PXP_IRQ_SET_RSVD1_MASK)

#define PXP_IRQ_SET_COMPRESS_DONE_IRQ_MASK       (0x80000000U)
#define PXP_IRQ_SET_COMPRESS_DONE_IRQ_SHIFT      (31U)
/*! COMPRESS_DONE_IRQ - COMPRESS_DONE_IRQ */
#define PXP_IRQ_SET_COMPRESS_DONE_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_COMPRESS_DONE_IRQ_SHIFT)) & PXP_IRQ_SET_COMPRESS_DONE_IRQ_MASK)
/*! @} */

/*! @name IRQ_CLR - PXP Interrupt Register */
/*! @{ */

#define PXP_IRQ_CLR_FIRST_CH0_PREFETCH_IRQ_MASK  (0x1U)
#define PXP_IRQ_CLR_FIRST_CH0_PREFETCH_IRQ_SHIFT (0U)
/*! FIRST_CH0_PREFETCH_IRQ - FIRST_CH0_PREFETCH_IRQ */
#define PXP_IRQ_CLR_FIRST_CH0_PREFETCH_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_FIRST_CH0_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_CLR_FIRST_CH0_PREFETCH_IRQ_MASK)

#define PXP_IRQ_CLR_FIRST_CH1_PREFETCH_IRQ_MASK  (0x2U)
#define PXP_IRQ_CLR_FIRST_CH1_PREFETCH_IRQ_SHIFT (1U)
/*! FIRST_CH1_PREFETCH_IRQ - FIRST_CH1_PREFETCH_IRQ */
#define PXP_IRQ_CLR_FIRST_CH1_PREFETCH_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_FIRST_CH1_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_CLR_FIRST_CH1_PREFETCH_IRQ_MASK)

#define PXP_IRQ_CLR_FIRST_CH0_STORE_IRQ_MASK     (0x4U)
#define PXP_IRQ_CLR_FIRST_CH0_STORE_IRQ_SHIFT    (2U)
/*! FIRST_CH0_STORE_IRQ - FIRST_CH0_STORE_IRQ */
#define PXP_IRQ_CLR_FIRST_CH0_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_FIRST_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_FIRST_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_CLR_FIRST_CH1_STORE_IRQ_MASK     (0x8U)
#define PXP_IRQ_CLR_FIRST_CH1_STORE_IRQ_SHIFT    (3U)
/*! FIRST_CH1_STORE_IRQ - FIRST_CH1_STORE_IRQ */
#define PXP_IRQ_CLR_FIRST_CH1_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_FIRST_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_FIRST_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_CLR_DITHER_CH0_PREFETCH_IRQ_MASK (0x10U)
#define PXP_IRQ_CLR_DITHER_CH0_PREFETCH_IRQ_SHIFT (4U)
/*! DITHER_CH0_PREFETCH_IRQ - DITHER_CH0_PREFETCH_IRQ */
#define PXP_IRQ_CLR_DITHER_CH0_PREFETCH_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_DITHER_CH0_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_CLR_DITHER_CH0_PREFETCH_IRQ_MASK)

#define PXP_IRQ_CLR_DITHER_CH1_PREFETCH_IRQ_MASK (0x20U)
#define PXP_IRQ_CLR_DITHER_CH1_PREFETCH_IRQ_SHIFT (5U)
/*! DITHER_CH1_PREFETCH_IRQ - DITHER_CH1_PREFETCH_IRQ */
#define PXP_IRQ_CLR_DITHER_CH1_PREFETCH_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_DITHER_CH1_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_CLR_DITHER_CH1_PREFETCH_IRQ_MASK)

#define PXP_IRQ_CLR_DITHER_CH0_STORE_IRQ_MASK    (0x40U)
#define PXP_IRQ_CLR_DITHER_CH0_STORE_IRQ_SHIFT   (6U)
/*! DITHER_CH0_STORE_IRQ - DITHER_CH0_STORE_IRQ */
#define PXP_IRQ_CLR_DITHER_CH0_STORE_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_DITHER_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_DITHER_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_CLR_DITHER_CH1_STORE_IRQ_MASK    (0x80U)
#define PXP_IRQ_CLR_DITHER_CH1_STORE_IRQ_SHIFT   (7U)
/*! DITHER_CH1_STORE_IRQ - DITHER_CH1_STORE_IRQ */
#define PXP_IRQ_CLR_DITHER_CH1_STORE_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_DITHER_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_DITHER_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_CLR_WFE_A_CH0_STORE_IRQ_MASK     (0x100U)
#define PXP_IRQ_CLR_WFE_A_CH0_STORE_IRQ_SHIFT    (8U)
/*! WFE_A_CH0_STORE_IRQ - WFE_A_CH0_STORE_IRQ */
#define PXP_IRQ_CLR_WFE_A_CH0_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_A_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_A_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_CLR_WFE_A_CH1_STORE_IRQ_MASK     (0x200U)
#define PXP_IRQ_CLR_WFE_A_CH1_STORE_IRQ_SHIFT    (9U)
/*! WFE_A_CH1_STORE_IRQ - WFE_A_CH1_STORE_IRQ */
#define PXP_IRQ_CLR_WFE_A_CH1_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_A_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_A_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_MASK     (0x400U)
#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_SHIFT    (10U)
/*! WFE_B_CH0_STORE_IRQ - WFE_B_CH0_STORE_IRQ */
#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_MASK     (0x800U)
#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_SHIFT    (11U)
/*! WFE_B_CH1_STORE_IRQ - WFE_B_CH1_STORE_IRQ */
#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_CLR_FIRST_STORE_IRQ_MASK         (0x1000U)
#define PXP_IRQ_CLR_FIRST_STORE_IRQ_SHIFT        (12U)
/*! FIRST_STORE_IRQ - FIRST_STORE_IRQ */
#define PXP_IRQ_CLR_FIRST_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_FIRST_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_FIRST_STORE_IRQ_MASK)

#define PXP_IRQ_CLR_DITHER_STORE_IRQ_MASK        (0x2000U)
#define PXP_IRQ_CLR_DITHER_STORE_IRQ_SHIFT       (13U)
/*! DITHER_STORE_IRQ - DITHER_STORE_IRQ */
#define PXP_IRQ_CLR_DITHER_STORE_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_DITHER_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_DITHER_STORE_IRQ_MASK)

#define PXP_IRQ_CLR_WFE_A_STORE_IRQ_MASK         (0x4000U)
#define PXP_IRQ_CLR_WFE_A_STORE_IRQ_SHIFT        (14U)
/*! WFE_A_STORE_IRQ - WFE_A_STORE_IRQ */
#define PXP_IRQ_CLR_WFE_A_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_A_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_A_STORE_IRQ_MASK)

#define PXP_IRQ_CLR_WFE_B_STORE_IRQ_MASK         (0x8000U)
#define PXP_IRQ_CLR_WFE_B_STORE_IRQ_SHIFT        (15U)
/*! WFE_B_STORE_IRQ - WFE_B_STORE_IRQ */
#define PXP_IRQ_CLR_WFE_B_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_STORE_IRQ_MASK)

#define PXP_IRQ_CLR_RSVD1_MASK                   (0x7FFF0000U)
#define PXP_IRQ_CLR_RSVD1_SHIFT                  (16U)
/*! RSVD1 - RSVD1 */
#define PXP_IRQ_CLR_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_RSVD1_SHIFT)) & PXP_IRQ_CLR_RSVD1_MASK)

#define PXP_IRQ_CLR_COMPRESS_DONE_IRQ_MASK       (0x80000000U)
#define PXP_IRQ_CLR_COMPRESS_DONE_IRQ_SHIFT      (31U)
/*! COMPRESS_DONE_IRQ - COMPRESS_DONE_IRQ */
#define PXP_IRQ_CLR_COMPRESS_DONE_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_COMPRESS_DONE_IRQ_SHIFT)) & PXP_IRQ_CLR_COMPRESS_DONE_IRQ_MASK)
/*! @} */

/*! @name IRQ_TOG - PXP Interrupt Register */
/*! @{ */

#define PXP_IRQ_TOG_FIRST_CH0_PREFETCH_IRQ_MASK  (0x1U)
#define PXP_IRQ_TOG_FIRST_CH0_PREFETCH_IRQ_SHIFT (0U)
/*! FIRST_CH0_PREFETCH_IRQ - FIRST_CH0_PREFETCH_IRQ */
#define PXP_IRQ_TOG_FIRST_CH0_PREFETCH_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_FIRST_CH0_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_TOG_FIRST_CH0_PREFETCH_IRQ_MASK)

#define PXP_IRQ_TOG_FIRST_CH1_PREFETCH_IRQ_MASK  (0x2U)
#define PXP_IRQ_TOG_FIRST_CH1_PREFETCH_IRQ_SHIFT (1U)
/*! FIRST_CH1_PREFETCH_IRQ - FIRST_CH1_PREFETCH_IRQ */
#define PXP_IRQ_TOG_FIRST_CH1_PREFETCH_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_FIRST_CH1_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_TOG_FIRST_CH1_PREFETCH_IRQ_MASK)

#define PXP_IRQ_TOG_FIRST_CH0_STORE_IRQ_MASK     (0x4U)
#define PXP_IRQ_TOG_FIRST_CH0_STORE_IRQ_SHIFT    (2U)
/*! FIRST_CH0_STORE_IRQ - FIRST_CH0_STORE_IRQ */
#define PXP_IRQ_TOG_FIRST_CH0_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_FIRST_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_FIRST_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_TOG_FIRST_CH1_STORE_IRQ_MASK     (0x8U)
#define PXP_IRQ_TOG_FIRST_CH1_STORE_IRQ_SHIFT    (3U)
/*! FIRST_CH1_STORE_IRQ - FIRST_CH1_STORE_IRQ */
#define PXP_IRQ_TOG_FIRST_CH1_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_FIRST_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_FIRST_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_TOG_DITHER_CH0_PREFETCH_IRQ_MASK (0x10U)
#define PXP_IRQ_TOG_DITHER_CH0_PREFETCH_IRQ_SHIFT (4U)
/*! DITHER_CH0_PREFETCH_IRQ - DITHER_CH0_PREFETCH_IRQ */
#define PXP_IRQ_TOG_DITHER_CH0_PREFETCH_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_DITHER_CH0_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_TOG_DITHER_CH0_PREFETCH_IRQ_MASK)

#define PXP_IRQ_TOG_DITHER_CH1_PREFETCH_IRQ_MASK (0x20U)
#define PXP_IRQ_TOG_DITHER_CH1_PREFETCH_IRQ_SHIFT (5U)
/*! DITHER_CH1_PREFETCH_IRQ - DITHER_CH1_PREFETCH_IRQ */
#define PXP_IRQ_TOG_DITHER_CH1_PREFETCH_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_DITHER_CH1_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_TOG_DITHER_CH1_PREFETCH_IRQ_MASK)

#define PXP_IRQ_TOG_DITHER_CH0_STORE_IRQ_MASK    (0x40U)
#define PXP_IRQ_TOG_DITHER_CH0_STORE_IRQ_SHIFT   (6U)
/*! DITHER_CH0_STORE_IRQ - DITHER_CH0_STORE_IRQ */
#define PXP_IRQ_TOG_DITHER_CH0_STORE_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_DITHER_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_DITHER_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_TOG_DITHER_CH1_STORE_IRQ_MASK    (0x80U)
#define PXP_IRQ_TOG_DITHER_CH1_STORE_IRQ_SHIFT   (7U)
/*! DITHER_CH1_STORE_IRQ - DITHER_CH1_STORE_IRQ */
#define PXP_IRQ_TOG_DITHER_CH1_STORE_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_DITHER_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_DITHER_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_TOG_WFE_A_CH0_STORE_IRQ_MASK     (0x100U)
#define PXP_IRQ_TOG_WFE_A_CH0_STORE_IRQ_SHIFT    (8U)
/*! WFE_A_CH0_STORE_IRQ - WFE_A_CH0_STORE_IRQ */
#define PXP_IRQ_TOG_WFE_A_CH0_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_A_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_A_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_TOG_WFE_A_CH1_STORE_IRQ_MASK     (0x200U)
#define PXP_IRQ_TOG_WFE_A_CH1_STORE_IRQ_SHIFT    (9U)
/*! WFE_A_CH1_STORE_IRQ - WFE_A_CH1_STORE_IRQ */
#define PXP_IRQ_TOG_WFE_A_CH1_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_A_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_A_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_MASK     (0x400U)
#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_SHIFT    (10U)
/*! WFE_B_CH0_STORE_IRQ - WFE_B_CH0_STORE_IRQ */
#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_MASK)

#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_MASK     (0x800U)
#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_SHIFT    (11U)
/*! WFE_B_CH1_STORE_IRQ - WFE_B_CH1_STORE_IRQ */
#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_MASK)

#define PXP_IRQ_TOG_FIRST_STORE_IRQ_MASK         (0x1000U)
#define PXP_IRQ_TOG_FIRST_STORE_IRQ_SHIFT        (12U)
/*! FIRST_STORE_IRQ - FIRST_STORE_IRQ */
#define PXP_IRQ_TOG_FIRST_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_FIRST_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_FIRST_STORE_IRQ_MASK)

#define PXP_IRQ_TOG_DITHER_STORE_IRQ_MASK        (0x2000U)
#define PXP_IRQ_TOG_DITHER_STORE_IRQ_SHIFT       (13U)
/*! DITHER_STORE_IRQ - DITHER_STORE_IRQ */
#define PXP_IRQ_TOG_DITHER_STORE_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_DITHER_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_DITHER_STORE_IRQ_MASK)

#define PXP_IRQ_TOG_WFE_A_STORE_IRQ_MASK         (0x4000U)
#define PXP_IRQ_TOG_WFE_A_STORE_IRQ_SHIFT        (14U)
/*! WFE_A_STORE_IRQ - WFE_A_STORE_IRQ */
#define PXP_IRQ_TOG_WFE_A_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_A_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_A_STORE_IRQ_MASK)

#define PXP_IRQ_TOG_WFE_B_STORE_IRQ_MASK         (0x8000U)
#define PXP_IRQ_TOG_WFE_B_STORE_IRQ_SHIFT        (15U)
/*! WFE_B_STORE_IRQ - WFE_B_STORE_IRQ */
#define PXP_IRQ_TOG_WFE_B_STORE_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_STORE_IRQ_MASK)

#define PXP_IRQ_TOG_RSVD1_MASK                   (0x7FFF0000U)
#define PXP_IRQ_TOG_RSVD1_SHIFT                  (16U)
/*! RSVD1 - RSVD1 */
#define PXP_IRQ_TOG_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_RSVD1_SHIFT)) & PXP_IRQ_TOG_RSVD1_MASK)

#define PXP_IRQ_TOG_COMPRESS_DONE_IRQ_MASK       (0x80000000U)
#define PXP_IRQ_TOG_COMPRESS_DONE_IRQ_SHIFT      (31U)
/*! COMPRESS_DONE_IRQ - COMPRESS_DONE_IRQ */
#define PXP_IRQ_TOG_COMPRESS_DONE_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_COMPRESS_DONE_IRQ_SHIFT)) & PXP_IRQ_TOG_COMPRESS_DONE_IRQ_MASK)
/*! @} */

/*! @name NEXT - Next Frame Pointer */
/*! @{ */

#define PXP_NEXT_ENABLED_MASK                    (0x1U)
#define PXP_NEXT_ENABLED_SHIFT                   (0U)
/*! ENABLED - ENABLED */
#define PXP_NEXT_ENABLED(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)

#define PXP_NEXT_RSVD_MASK                       (0x2U)
#define PXP_NEXT_RSVD_SHIFT                      (1U)
/*! RSVD - RSVD */
#define PXP_NEXT_RSVD(x)                         (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_RSVD_SHIFT)) & PXP_NEXT_RSVD_MASK)

#define PXP_NEXT_POINTER_MASK                    (0xFFFFFFFCU)
#define PXP_NEXT_POINTER_SHIFT                   (2U)
/*! POINTER - POINTER */
#define PXP_NEXT_POINTER(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)
/*! @} */

/*! @name INPUT_FETCH_CTRL_CH0 - Pre-fetch engine Control Channel 0 Register */
/*! @{ */

#define PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK      (0x1U)
#define PXP_INPUT_FETCH_CTRL_CH0_CH_EN_SHIFT     (0U)
/*! CH_EN - CH_EN
 *  0b0..Prefetch function is disable
 *  0b1..Prefetch function is enable
 */
#define PXP_INPUT_FETCH_CTRL_CH0_CH_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN_MASK   (0x2U)
#define PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN_SHIFT  (1U)
/*! BLOCK_EN - BLOCK_EN
 *  0b0..Prefetch in scan mode
 *  0b1..Prefetch in block mode
 */
#define PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16_MASK   (0x4U)
#define PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16_SHIFT  (2U)
/*! BLOCK_16 - BLOCK_16
 *  0b0..BLK_SIZE_8x8 : Block size is 8x8
 *  0b1..BLK_SIZE_16x16 : Block size is 16x16
 */
#define PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16(x)     (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN
 *  0b0..Handshake with the store engine is disabled
 *  0b1..Handshake with the store engine is enabled
 */
#define PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN
 *  0b0..Channel 0 is from memory
 *  0b1..Channel 0 is from previous process engine
 */
#define PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE_MASK  (0x20U)
#define PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE_SHIFT (5U)
/*! HIGH_BYTE - HIGH_BYTE
 *  0b0..In 64 bit mode, the output high byte will use channel1.
 *  0b1..In 64 bit mode, the output high byte will use channel0
 */
#define PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_RSVD4_MASK      (0x1C0U)
#define PXP_INPUT_FETCH_CTRL_CH0_RSVD4_SHIFT     (6U)
/*! RSVD4 - RSVD4 */
#define PXP_INPUT_FETCH_CTRL_CH0_RSVD4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_RSVD4_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_RSVD4_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_HFLIP_MASK      (0x200U)
#define PXP_INPUT_FETCH_CTRL_CH0_HFLIP_SHIFT     (9U)
/*! HFLIP - HFLIP
 *  0b0..HFLIP disable
 *  0b1..VFLIP enable
 */
#define PXP_INPUT_FETCH_CTRL_CH0_HFLIP(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_HFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_VFLIP_MASK      (0x400U)
#define PXP_INPUT_FETCH_CTRL_CH0_VFLIP_SHIFT     (10U)
/*! VFLIP - VFLIP
 *  0b0..VFLIP disable
 *  0b1..VFLIP enable
 */
#define PXP_INPUT_FETCH_CTRL_CH0_VFLIP(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_VFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_RSVD3_MASK      (0x800U)
#define PXP_INPUT_FETCH_CTRL_CH0_RSVD3_SHIFT     (11U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_CTRL_CH0_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_RSVD3_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_RSVD3_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE
 *  0b00..ROT_0 : Rotate image by 0 degrees.
 *  0b01..ROT_90 : Rotate image by 90 degrees.
 *  0b10..ROT_180 : Rotate image by 180 degrees.
 *  0b11..ROT_270 : Rotate image by 270 degrees.
 */
#define PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_RSVD2_MASK      (0xC000U)
#define PXP_INPUT_FETCH_CTRL_CH0_RSVD2_SHIFT     (14U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_CTRL_CH0_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_RSVD2_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_RSVD2_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES
 *  0b00..NUM_8_BYTES : 8 bytes.
 *  0b01..NUM_16_BYTES : 16 bytes.
 *  0b10..NUM_32_BYTES : 32 bytes.
 *  0b11..NUM_64_BYTES : 64 bytes.
 */
#define PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_RSVD1_MASK      (0xFC0000U)
#define PXP_INPUT_FETCH_CTRL_CH0_RSVD1_SHIFT     (18U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_CTRL_CH0_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_RSVD1_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_RSVD1_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM
 *  0b00..1 line.
 *  0b01..8 lines
 *  0b10..16 lines
 *  0b11..16 lines
 */
#define PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_RSVD0_MASK      (0x7C000000U)
#define PXP_INPUT_FETCH_CTRL_CH0_RSVD0_SHIFT     (26U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_CTRL_CH0_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_RSVD0_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_RSVD0_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN_MASK   (0x80000000U)
#define PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN_SHIFT  (31U)
/*! ARBIT_EN - ARBIT_EN
 *  0b0..Arbitration disable. If using 2 channels, will output 2 axi bus sets.
 *  0b1..Arbitration enable. If using 2 channel, will only output 1 axi bus sets
 */
#define PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN_MASK)
/*! @} */

/*! @name INPUT_FETCH_CTRL_CH0_SET - Pre-fetch engine Control Channel 0 Register */
/*! @{ */

#define PXP_INPUT_FETCH_CTRL_CH0_SET_CH_EN_MASK  (0x1U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_CH_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_EN_MASK (0x2U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_16_MASK (0x4U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_16_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_HANDSHAKE_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_BYPASS_PIXEL_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_BYPASS_PIXEL_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_HIGH_BYTE_MASK (0x20U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_HIGH_BYTE_SHIFT (5U)
/*! HIGH_BYTE - HIGH_BYTE */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_HIGH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_HIGH_BYTE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_HIGH_BYTE_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD4_MASK  (0x1C0U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD4_SHIFT (6U)
/*! RSVD4 - RSVD4 */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD4(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD4_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD4_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_HFLIP_MASK  (0x200U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_HFLIP_SHIFT (9U)
/*! HFLIP - HFLIP */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_HFLIP(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_HFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_VFLIP_MASK  (0x400U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_VFLIP_SHIFT (10U)
/*! VFLIP - VFLIP */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_VFLIP(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_VFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD3_MASK  (0x800U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD3_SHIFT (11U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD3_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD3_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_ROTATION_ANGLE_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD2_MASK  (0xC000U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD2_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD2_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_RD_NUM_BYTES_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD1_MASK  (0xFC0000U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD1_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD1_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD0_MASK  (0x7C000000U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD0_SHIFT (26U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD0_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_RSVD0_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_SET_ARBIT_EN_MASK (0x80000000U)
#define PXP_INPUT_FETCH_CTRL_CH0_SET_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_SET_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_ARBIT_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_ARBIT_EN_MASK)
/*! @} */

/*! @name INPUT_FETCH_CTRL_CH0_CLR - Pre-fetch engine Control Channel 0 Register */
/*! @{ */

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_CH_EN_MASK  (0x1U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_CH_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_EN_MASK (0x2U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_16_MASK (0x4U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_16_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_HANDSHAKE_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_BYPASS_PIXEL_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_BYPASS_PIXEL_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HIGH_BYTE_MASK (0x20U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HIGH_BYTE_SHIFT (5U)
/*! HIGH_BYTE - HIGH_BYTE */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HIGH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_HIGH_BYTE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_HIGH_BYTE_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD4_MASK  (0x1C0U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD4_SHIFT (6U)
/*! RSVD4 - RSVD4 */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD4(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD4_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD4_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HFLIP_MASK  (0x200U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HFLIP_SHIFT (9U)
/*! HFLIP - HFLIP */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HFLIP(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_HFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_VFLIP_MASK  (0x400U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_VFLIP_SHIFT (10U)
/*! VFLIP - VFLIP */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_VFLIP(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_VFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD3_MASK  (0x800U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD3_SHIFT (11U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD3_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD3_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD2_MASK  (0xC000U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD2_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD2_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD1_MASK  (0xFC0000U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD1_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD1_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD0_MASK  (0x7C000000U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD0_SHIFT (26U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD0_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_RSVD0_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_CLR_ARBIT_EN_MASK (0x80000000U)
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_CLR_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_ARBIT_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_ARBIT_EN_MASK)
/*! @} */

/*! @name INPUT_FETCH_CTRL_CH0_TOG - Pre-fetch engine Control Channel 0 Register */
/*! @{ */

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_CH_EN_MASK  (0x1U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_CH_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_EN_MASK (0x2U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_16_MASK (0x4U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_16_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_HANDSHAKE_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_BYPASS_PIXEL_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_BYPASS_PIXEL_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HIGH_BYTE_MASK (0x20U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HIGH_BYTE_SHIFT (5U)
/*! HIGH_BYTE - HIGH_BYTE */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HIGH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_HIGH_BYTE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_HIGH_BYTE_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD4_MASK  (0x1C0U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD4_SHIFT (6U)
/*! RSVD4 - RSVD4 */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD4(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD4_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD4_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HFLIP_MASK  (0x200U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HFLIP_SHIFT (9U)
/*! HFLIP - HFLIP */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HFLIP(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_HFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_VFLIP_MASK  (0x400U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_VFLIP_SHIFT (10U)
/*! VFLIP - VFLIP */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_VFLIP(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_VFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD3_MASK  (0x800U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD3_SHIFT (11U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD3_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD3_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD2_MASK  (0xC000U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD2_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD2_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD1_MASK  (0xFC0000U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD1_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD1_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD0_MASK  (0x7C000000U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD0_SHIFT (26U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD0_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_RSVD0_MASK)

#define PXP_INPUT_FETCH_CTRL_CH0_TOG_ARBIT_EN_MASK (0x80000000U)
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_INPUT_FETCH_CTRL_CH0_TOG_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_ARBIT_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_ARBIT_EN_MASK)
/*! @} */

/*! @name INPUT_FETCH_CTRL_CH1 - Pre-fetch engine Control Channel 1 Register */
/*! @{ */

#define PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK      (0x1U)
#define PXP_INPUT_FETCH_CTRL_CH1_CH_EN_SHIFT     (0U)
/*! CH_EN - CH_EN
 *  0b0..prefetch function is disable
 *  0b1..prefetch function is enable
 */
#define PXP_INPUT_FETCH_CTRL_CH1_CH_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN_MASK   (0x2U)
#define PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN_SHIFT  (1U)
/*! BLOCK_EN - BLOCK_EN
 *  0b0..Prefetch in scan mode
 *  0b1..Prefetch in block mode
 */
#define PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16_MASK   (0x4U)
#define PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16_SHIFT  (2U)
/*! BLOCK_16 - BLOCK_16
 *  0b0..BLK_SIZE_8x8 : Block size is 8x8
 *  0b1..BLK_SIZE_16x16 : Block size is 16x16
 */
#define PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16(x)     (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN
 *  0b0..Handshake with the store engine is disabled
 *  0b1..Handshake with the store engine is enabled
 */
#define PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN
 *  0b0..Channel 1 is from memory
 *  0b1..Channel 1 is from previous process engine
 */
#define PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_RSVD4_MASK      (0x1E0U)
#define PXP_INPUT_FETCH_CTRL_CH1_RSVD4_SHIFT     (5U)
/*! RSVD4 - RSVD4 */
#define PXP_INPUT_FETCH_CTRL_CH1_RSVD4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_RSVD4_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_RSVD4_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_HFLIP_MASK      (0x200U)
#define PXP_INPUT_FETCH_CTRL_CH1_HFLIP_SHIFT     (9U)
/*! HFLIP - HFLIP
 *  0b0..HFLIP disable
 *  0b1..VFLIP enable
 */
#define PXP_INPUT_FETCH_CTRL_CH1_HFLIP(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_HFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_VFLIP_MASK      (0x400U)
#define PXP_INPUT_FETCH_CTRL_CH1_VFLIP_SHIFT     (10U)
/*! VFLIP - VFLIP
 *  0b0..VFLIP disable
 *  0b1..VFLIP enable
 */
#define PXP_INPUT_FETCH_CTRL_CH1_VFLIP(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_VFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_RSVD3_MASK      (0x800U)
#define PXP_INPUT_FETCH_CTRL_CH1_RSVD3_SHIFT     (11U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_CTRL_CH1_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_RSVD3_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_RSVD3_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE
 *  0b00..ROT_0 : Rotate image by 0 degrees.
 *  0b01..ROT_90 : Rotate image by 90 degrees.
 *  0b10..ROT_180 : Rotate image by 180 degrees.
 *  0b11..ROT_270 : Rotate image by 270 degrees.
 */
#define PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_RSVD2_MASK      (0xC000U)
#define PXP_INPUT_FETCH_CTRL_CH1_RSVD2_SHIFT     (14U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_CTRL_CH1_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_RSVD2_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_RSVD2_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES
 *  0b00..NUM_8_BYTES : 8 bytes.
 *  0b01..NUM_16_BYTES : 16 bytes.
 *  0b10..NUM_32_BYTES : 32 bytes.
 *  0b11..NUM_64_BYTES : 64 bytes.
 */
#define PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_RSVD1_MASK      (0xFC0000U)
#define PXP_INPUT_FETCH_CTRL_CH1_RSVD1_SHIFT     (18U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_CTRL_CH1_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_RSVD1_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_RSVD1_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM
 *  0b00..1 line.
 *  0b01..8 lines
 *  0b10..16 lines
 *  0b11..16 lines
 */
#define PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_RSVD0_MASK      (0xFC000000U)
#define PXP_INPUT_FETCH_CTRL_CH1_RSVD0_SHIFT     (26U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_CTRL_CH1_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_RSVD0_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_CTRL_CH1_SET - Pre-fetch engine Control Channel 1 Register */
/*! @{ */

#define PXP_INPUT_FETCH_CTRL_CH1_SET_CH_EN_MASK  (0x1U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_CH_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_EN_MASK (0x2U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_16_MASK (0x4U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_16_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_HANDSHAKE_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_BYPASS_PIXEL_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_BYPASS_PIXEL_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD4_MASK  (0x1E0U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD4_SHIFT (5U)
/*! RSVD4 - RSVD4 */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD4(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD4_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD4_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_HFLIP_MASK  (0x200U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_HFLIP_SHIFT (9U)
/*! HFLIP - HFLIP */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_HFLIP(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_HFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_VFLIP_MASK  (0x400U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_VFLIP_SHIFT (10U)
/*! VFLIP - VFLIP */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_VFLIP(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_VFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD3_MASK  (0x800U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD3_SHIFT (11U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD3_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD3_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_ROTATION_ANGLE_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD2_MASK  (0xC000U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD2_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD2_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_RD_NUM_BYTES_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD1_MASK  (0xFC0000U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD1_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD1_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD0_MASK  (0xFC000000U)
#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD0_SHIFT (26U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD0_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_CTRL_CH1_CLR - Pre-fetch engine Control Channel 1 Register */
/*! @{ */

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_CH_EN_MASK  (0x1U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_CH_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_EN_MASK (0x2U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_16_MASK (0x4U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_16_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_HANDSHAKE_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_BYPASS_PIXEL_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_BYPASS_PIXEL_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD4_MASK  (0x1E0U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD4_SHIFT (5U)
/*! RSVD4 - RSVD4 */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD4(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD4_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD4_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_HFLIP_MASK  (0x200U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_HFLIP_SHIFT (9U)
/*! HFLIP - HFLIP */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_HFLIP(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_HFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_VFLIP_MASK  (0x400U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_VFLIP_SHIFT (10U)
/*! VFLIP - VFLIP */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_VFLIP(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_VFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD3_MASK  (0x800U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD3_SHIFT (11U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD3_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD3_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD2_MASK  (0xC000U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD2_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD2_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD1_MASK  (0xFC0000U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD1_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD1_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD0_MASK  (0xFC000000U)
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD0_SHIFT (26U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD0_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_CTRL_CH1_TOG - Pre-fetch engine Control Channel 1 Register */
/*! @{ */

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_CH_EN_MASK  (0x1U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_CH_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_EN_MASK (0x2U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_16_MASK (0x4U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_16_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_HANDSHAKE_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_BYPASS_PIXEL_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_BYPASS_PIXEL_EN_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD4_MASK  (0x1E0U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD4_SHIFT (5U)
/*! RSVD4 - RSVD4 */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD4(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD4_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD4_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_HFLIP_MASK  (0x200U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_HFLIP_SHIFT (9U)
/*! HFLIP - HFLIP */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_HFLIP(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_HFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_VFLIP_MASK  (0x400U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_VFLIP_SHIFT (10U)
/*! VFLIP - VFLIP */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_VFLIP(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_VFLIP_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD3_MASK  (0x800U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD3_SHIFT (11U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD3_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD3_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD2_MASK  (0xC000U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD2_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD2_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD1_MASK  (0xFC0000U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD1_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD1_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD0_MASK  (0xFC000000U)
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD0_SHIFT (26U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD0_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_STATUS_CH0 - Pre-fetch engine status Channel 0 Register */
/*! @{ */

#define PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_MASK (0xFFFFU)
#define PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_SHIFT (0U)
/*! PREFETCH_BLOCK_X - PREFETCH_BLOCK_X */
#define PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_SHIFT)) & PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_MASK)

#define PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_SHIFT (16U)
/*! PREFETCH_BLOCK_Y - PREFETCH_BLOCK_Y */
#define PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_SHIFT)) & PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_MASK)
/*! @} */

/*! @name INPUT_FETCH_STATUS_CH1 - Store engine status Channel 1 Register */
/*! @{ */

#define PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_MASK (0xFFFFU)
#define PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_SHIFT (0U)
/*! PREFETCH_BLOCK_X - PREFETCH_BLOCK_X */
#define PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_SHIFT)) & PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_MASK)

#define PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_SHIFT (16U)
/*! PREFETCH_BLOCK_Y - PREFETCH_BLOCK_Y */
#define PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_SHIFT)) & PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_MASK)
/*! @} */

/*! @name INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 -  */
/*! @{ */

#define PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_MASK (0xFFFFU)
#define PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_SHIFT (0U)
/*! ACTIVE_SIZE_ULC_X - ACTIVE_SIZE_ULC_X */
#define PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_SHIFT)) & PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_MASK)

#define PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_SHIFT (16U)
/*! ACTIVE_SIZE_ULC_Y - ACTIVE_SIZE_ULC_Y */
#define PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_SHIFT)) & PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_MASK)
/*! @} */

/*! @name INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 -  */
/*! @{ */

#define PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_MASK (0xFFFFU)
#define PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_SHIFT (0U)
/*! ACTIVE_SIZE_LRC_X - ACTIVE_SIZE_LRC_X */
#define PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_SHIFT)) & PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_MASK)

#define PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_SHIFT (16U)
/*! ACTIVE_SIZE_LRC_Y - ACTIVE_SIZE_LRC_Y */
#define PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_SHIFT)) & PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_MASK)
/*! @} */

/*! @name INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 -  */
/*! @{ */

#define PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_MASK (0xFFFFU)
#define PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_SHIFT (0U)
/*! ACTIVE_SIZE_ULC_X - ACTIVE_SIZE_ULC_X */
#define PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_SHIFT)) & PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_MASK)

#define PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_SHIFT (16U)
/*! ACTIVE_SIZE_ULC_Y - ACTIVE_SIZE_ULC_Y */
#define PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_SHIFT)) & PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_MASK)
/*! @} */

/*! @name INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 -  */
/*! @{ */

#define PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_MASK (0xFFFFU)
#define PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_SHIFT (0U)
/*! ACTIVE_SIZE_LRC_X - ACTIVE_SIZE_LRC_X */
#define PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_SHIFT)) & PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_MASK)

#define PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_SHIFT (16U)
/*! ACTIVE_SIZE_LRC_Y - ACTIVE_SIZE_LRC_Y */
#define PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_SHIFT)) & PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_MASK)
/*! @} */

/*! @name INPUT_FETCH_SIZE_CH0 -  */
/*! @{ */

#define PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_MASK (0xFFFFU)
#define PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_SHIFT (0U)
/*! INPUT_TOTAL_WIDTH - INPUT_TOTAL_WIDTH */
#define PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_SHIFT)) & PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_MASK)

#define PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_SHIFT (16U)
/*! INPUT_TOTAL_HEIGHT - INPUT_TOTAL_HEIGHT */
#define PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_SHIFT)) & PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_MASK)
/*! @} */

/*! @name INPUT_FETCH_SIZE_CH1 -  */
/*! @{ */

#define PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_MASK (0xFFFFU)
#define PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_SHIFT (0U)
/*! INPUT_TOTAL_WIDTH - INPUT_TOTAL_WIDTH */
#define PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_SHIFT)) & PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_MASK)

#define PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_SHIFT (16U)
/*! INPUT_TOTAL_HEIGHT - INPUT_TOTAL_HEIGHT */
#define PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_SHIFT)) & PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_MASK)
/*! @} */

/*! @name INPUT_FETCH_BACKGROUND_COLOR_CH0 -  */
/*! @{ */

#define PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_MASK (0xFFFFFFFFU)
#define PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_SHIFT (0U)
/*! BACKGROUND_COLOR - BACKGROUND_COLOR */
#define PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_SHIFT)) & PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_MASK)
/*! @} */

/*! @name INPUT_FETCH_BACKGROUND_COLOR_CH1 -  */
/*! @{ */

#define PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_MASK (0xFFFFFFFFU)
#define PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_SHIFT (0U)
/*! BACKGROUND_COLOR - BACKGROUND_COLOR */
#define PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_SHIFT)) & PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_MASK)
/*! @} */

/*! @name INPUT_FETCH_PITCH -  */
/*! @{ */

#define PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_MASK (0xFFFFU)
#define PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_SHIFT (0U)
/*! CH0_INPUT_PITCH - CH0_INPUT_PITCH */
#define PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_SHIFT)) & PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_MASK)

#define PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_SHIFT (16U)
/*! CH1_INPUT_PITCH - CH1_INPUT_PITCH */
#define PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_SHIFT)) & PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_CTRL_CH0 -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP
 *  0b00..8 bits
 *  0b01..16 bits
 *  0b10..32 bits
 *  0b11..64 bits
 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1_MASK (0xFCU)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_MASK (0x700U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT
 *  0b000..RGB 565
 *  0b001..RGB 555
 *  0b010..ARGB 1555
 *  0b011..RGB 444
 *  0b100..ARGB 4444
 *  0b101..YUYV/YVYU
 *  0b110..UYVY/VYUY
 *  0b111..YUV422_2P
 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_MASK (0x800U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN
 *  0b0..channel0 format expanding disable
 *  0b1..channel0 format expanding enable
 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS
 *  0b0..channel0 data will do shift function
 *  0b1..channel0 will bypass shift function
 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0_MASK (0xFFFFE000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_CTRL_CH0_SET -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_RSVD1_MASK (0xFCU)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT_MASK (0x700U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN_MASK (0x800U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_RSVD0_MASK (0xFFFFE000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_CTRL_CH0_CLR -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_RSVD1_MASK (0xFCU)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT_MASK (0x700U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN_MASK (0x800U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_RSVD0_MASK (0xFFFFE000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_CTRL_CH0_TOG -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_RSVD1_MASK (0xFCU)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT_MASK (0x700U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN_MASK (0x800U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_RSVD0_MASK (0xFFFFE000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_CTRL_CH1 -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP
 *  0b00..8 bits
 *  0b01..16 bits
 *  0b10..32 bits
 *  0b11..32 bits
 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1_MASK (0xFCU)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_MASK (0x700U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT
 *  0b000..RGB 565
 *  0b001..RGB 555
 *  0b010..ARGB 1555
 *  0b011..RGB 444
 *  0b100..ARGB 4444
 *  0b101..YUYV/YVYU
 *  0b110..UYVY/VYUY
 *  0b111..YUV422_2P
 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_MASK (0x800U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN
 *  0b0..channel1 format expanding disable
 *  0b1..channel1 format expanding enable
 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS
 *  0b0..channel1 data will do shift function
 *  0b1..channel1 will bypass shift function
 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0_MASK (0xFFFFE000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_CTRL_CH1_SET -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_RSVD1_MASK (0xFCU)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT_MASK (0x700U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN_MASK (0x800U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_RSVD0_MASK (0xFFFFE000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_CTRL_CH1_CLR -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_RSVD1_MASK (0xFCU)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT_MASK (0x700U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN_MASK (0x800U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_RSVD0_MASK (0xFFFFE000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_CTRL_CH1_TOG -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_RSVD1_MASK (0xFCU)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT_MASK (0x700U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN_MASK (0x800U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS_MASK)

#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_RSVD0_MASK (0xFFFFE000U)
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_OFFSET_CH0 -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0_MASK (0x1FU)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3_MASK (0xE0U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1_MASK (0x1F00U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2_MASK (0xE000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2_MASK (0x1F0000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1_MASK (0xE00000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_MASK (0x1F000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0_MASK (0xE0000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_OFFSET_CH0_SET -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0_MASK (0x1FU)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD3_MASK (0xE0U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1_MASK (0x1F00U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD2_MASK (0xE000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2_MASK (0x1F0000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD1_MASK (0xE00000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3_MASK (0x1F000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD0_MASK (0xE0000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_OFFSET_CH0_CLR -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0_MASK (0x1FU)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD3_MASK (0xE0U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1_MASK (0x1F00U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD2_MASK (0xE000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2_MASK (0x1F0000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD1_MASK (0xE00000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3_MASK (0x1F000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD0_MASK (0xE0000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_OFFSET_CH0_TOG -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0_MASK (0x1FU)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD3_MASK (0xE0U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1_MASK (0x1F00U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD2_MASK (0xE000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2_MASK (0x1F0000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD1_MASK (0xE00000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3_MASK (0x1F000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD0_MASK (0xE0000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_OFFSET_CH1 -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0_MASK (0x1FU)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3_MASK (0xE0U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1_MASK (0x1F00U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2_MASK (0xE000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2_MASK (0x1F0000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1_MASK (0xE00000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_MASK (0x1F000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0_MASK (0xE0000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_OFFSET_CH1_SET -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0_MASK (0x1FU)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD3_MASK (0xE0U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1_MASK (0x1F00U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD2_MASK (0xE000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2_MASK (0x1F0000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD1_MASK (0xE00000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3_MASK (0x1F000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD0_MASK (0xE0000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_OFFSET_CH1_CLR -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0_MASK (0x1FU)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD3_MASK (0xE0U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1_MASK (0x1F00U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD2_MASK (0xE000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2_MASK (0x1F0000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD1_MASK (0xE00000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3_MASK (0x1F000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD0_MASK (0xE0000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_OFFSET_CH1_TOG -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0_MASK (0x1FU)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD3_MASK (0xE0U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1_MASK (0x1F00U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD2_MASK (0xE000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2_MASK (0x1F0000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD1_MASK (0xE00000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD1_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3_MASK (0x1F000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3_MASK)

#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD0_MASK (0xE0000000U)
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_WIDTH_CH0 -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0_MASK (0xFU)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1_MASK (0xF0U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2_MASK (0xF00U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_MASK (0xF000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_WIDTH_CH0_SET -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0_MASK (0xFU)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1_MASK (0xF0U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2_MASK (0xF00U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3_MASK (0xF000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_RSVD0_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_WIDTH_CH0_CLR -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0_MASK (0xFU)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1_MASK (0xF0U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2_MASK (0xF00U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3_MASK (0xF000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_RSVD0_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_WIDTH_CH0_TOG -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0_MASK (0xFU)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1_MASK (0xF0U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2_MASK (0xF00U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3_MASK (0xF000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_RSVD0_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_WIDTH_CH1 -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0_MASK (0xFU)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1_MASK (0xF0U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2_MASK (0xF00U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_MASK (0xF000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_WIDTH_CH1_SET -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0_MASK (0xFU)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1_MASK (0xF0U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2_MASK (0xF00U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3_MASK (0xF000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_RSVD0_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_WIDTH_CH1_CLR -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0_MASK (0xFU)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1_MASK (0xF0U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2_MASK (0xF00U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3_MASK (0xF000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_RSVD0_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_SHIFT_WIDTH_CH1_TOG -  */
/*! @{ */

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0_MASK (0xFU)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1_MASK (0xF0U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2_MASK (0xF00U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3_MASK (0xF000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3_MASK)

#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_RSVD0_MASK (0xFFFF0000U)
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_RSVD0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name INPUT_FETCH_ADDR_0_CH0 -  */
/*! @{ */

#define PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_SHIFT (0U)
/*! INPUT_BASE_ADDR0 - INPUT_BASE_ADDR0 */
#define PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_SHIFT)) & PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_MASK)
/*! @} */

/*! @name INPUT_FETCH_ADDR_1_CH0 -  */
/*! @{ */

#define PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_MASK (0xFFFFFFFFU)
#define PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_SHIFT (0U)
/*! INPUT_BASE_ADDR1 - INPUT_BASE_ADDR1 */
#define PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_SHIFT)) & PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_MASK)
/*! @} */

/*! @name INPUT_FETCH_ADDR_0_CH1 -  */
/*! @{ */

#define PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_SHIFT (0U)
/*! INPUT_BASE_ADDR0 - INPUT_BASE_ADDR0 */
#define PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_SHIFT)) & PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_MASK)
/*! @} */

/*! @name INPUT_FETCH_ADDR_1_CH1 -  */
/*! @{ */

#define PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_MASK (0xFFFFFFFFU)
#define PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_SHIFT (0U)
/*! INPUT_BASE_ADDR1 - INPUT_BASE_ADDR1 */
#define PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_SHIFT)) & PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_MASK)
/*! @} */

/*! @name INPUT_STORE_CTRL_CH0 - Store engine Control Channel 0 Register */
/*! @{ */

#define PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK      (0x1U)
#define PXP_INPUT_STORE_CTRL_CH0_CH_EN_SHIFT     (0U)
/*! CH_EN - CH_EN
 *  0b0..Store function is disable
 *  0b1..Store function is enable
 */
#define PXP_INPUT_STORE_CTRL_CH0_CH_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN_MASK   (0x2U)
#define PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN_SHIFT  (1U)
/*! BLOCK_EN - BLOCK_EN
 *  0b0..Store in scan mode
 *  0b1..Store in block mode
 */
#define PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_BLOCK_16_MASK   (0x4U)
#define PXP_INPUT_STORE_CTRL_CH0_BLOCK_16_SHIFT  (2U)
/*! BLOCK_16 - BLOCK_16
 *  0b0..BLK_SIZE_8x8 : Block size is 8x8
 *  0b1..BLK_SIZE_16x16 : Block size is 16x16
 */
#define PXP_INPUT_STORE_CTRL_CH0_BLOCK_16(x)     (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_BLOCK_16_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN
 *  0b0..Handshake with the prefetch engine is disabled
 *  0b1..Handshake with the prefetch engine is enabled
 */
#define PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN_MASK   (0x10U)
#define PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN_SHIFT  (4U)
/*! ARRAY_EN - ARRAY_EN
 *  0b0..Array Handshake Disabled
 *  0b1..Array Handshake Enabled
 */
#define PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM
 *  0b00..Using 1x1 Array
 *  0b01..Using 3x3 Array
 *  0b10..Using 5x5 Array
 *  0b11..Using 5x5 Array
 */
#define PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_RSVD3_MASK      (0x80U)
#define PXP_INPUT_STORE_CTRL_CH0_RSVD3_SHIFT     (7U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_STORE_CTRL_CH0_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_RSVD3_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_RSVD3_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN
 *  0b0..store bypass mode disable.
 *  0b1..store bypass mode enable. Data will bypass to store output.
 */
#define PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN
 *  0b0..store memory mode disable.
 *  0b1..store memory mode enable. Data will store to memory
 */
#define PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL_MASK (0x400U)
#define PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL
 *  0b0..select 64 shift out data to pack
 *  0b1..select low 32 bit shift out data to pack
 */
#define PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN_MASK (0x800U)
#define PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN
 *  0b0..Fill data mode disable.
 *  0b1..Fill data mode enable. When using fill_data mode, store_engine will store fixed data defined in fill_data register
 */
#define PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_RSVD2_MASK      (0xF000U)
#define PXP_INPUT_STORE_CTRL_CH0_RSVD2_SHIFT     (12U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_CTRL_CH0_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_RSVD2_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_RSVD2_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES
 *  0b00..NUM_8_BYTES : 8 bytes
 *  0b01..NUM_16_BYTES : 16 bytes
 *  0b10..NUM_32_BYTES : 32 bytes
 *  0b11..NUM_64_BYTES : 64 bytes
 */
#define PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_RSVD1_MASK      (0xFC0000U)
#define PXP_INPUT_STORE_CTRL_CH0_RSVD1_SHIFT     (18U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_CTRL_CH0_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_RSVD1_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_RSVD1_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL
 *  0b0..combine 2 channel disable
 *  0b1..combine 2 channel enable
 */
#define PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_RSVD0_MASK      (0x7E000000U)
#define PXP_INPUT_STORE_CTRL_CH0_RSVD0_SHIFT     (25U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_CTRL_CH0_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_RSVD0_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_RSVD0_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN_MASK   (0x80000000U)
#define PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN_SHIFT  (31U)
/*! ARBIT_EN - ARBIT_EN
 *  0b0..Arbitration disable. If using 2 channels, will output 2 axi bus sets
 *  0b1..Arbitration enable. If using 2 channel, will only output 1 axi bus sets
 */
#define PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN_MASK)
/*! @} */

/*! @name INPUT_STORE_CTRL_CH0_SET - Store engine Control Channel 0 Register */
/*! @{ */

#define PXP_INPUT_STORE_CTRL_CH0_SET_CH_EN_MASK  (0x1U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_INPUT_STORE_CTRL_CH0_SET_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_CH_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_EN_MASK (0x2U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_16_MASK (0x4U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_16_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_INPUT_STORE_CTRL_CH0_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_ARRAY_EN_MASK (0x10U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_INPUT_STORE_CTRL_CH0_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_ARRAY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_INPUT_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_RSVD3_MASK  (0x80U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_STORE_CTRL_CH0_SET_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_RSVD3_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_RSVD3_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_INPUT_STORE_CTRL_CH0_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_INPUT_STORE_CTRL_CH0_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK (0x400U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_INPUT_STORE_CTRL_CH0_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK (0x800U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN */
#define PXP_INPUT_STORE_CTRL_CH0_SET_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_RSVD2_MASK  (0xF000U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_RSVD2_SHIFT (12U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_CTRL_CH0_SET_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_RSVD2_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_RSVD2_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_INPUT_STORE_CTRL_CH0_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_RSVD1_MASK  (0xFC0000U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_CTRL_CH0_SET_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_RSVD1_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_RSVD1_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL */
#define PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_RSVD0_MASK  (0x7E000000U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_RSVD0_SHIFT (25U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_CTRL_CH0_SET_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_RSVD0_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_RSVD0_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_SET_ARBIT_EN_MASK (0x80000000U)
#define PXP_INPUT_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_INPUT_STORE_CTRL_CH0_SET_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_ARBIT_EN_MASK)
/*! @} */

/*! @name INPUT_STORE_CTRL_CH0_CLR - Store engine Control Channel 0 Register */
/*! @{ */

#define PXP_INPUT_STORE_CTRL_CH0_CLR_CH_EN_MASK  (0x1U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_CH_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK (0x2U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_16_MASK (0x4U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_16_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK (0x10U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD3_MASK  (0x80U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD3_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD3_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK (0x400U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK (0x800U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD2_MASK  (0xF000U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD2_SHIFT (12U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD2_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD2_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD1_MASK  (0xFC0000U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD1_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD1_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD0_MASK  (0x7E000000U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD0_SHIFT (25U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD0_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_RSVD0_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK (0x80000000U)
#define PXP_INPUT_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_INPUT_STORE_CTRL_CH0_CLR_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK)
/*! @} */

/*! @name INPUT_STORE_CTRL_CH0_TOG - Store engine Control Channel 0 Register */
/*! @{ */

#define PXP_INPUT_STORE_CTRL_CH0_TOG_CH_EN_MASK  (0x1U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_CH_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK (0x2U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_16_MASK (0x4U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_16_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK (0x10U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD3_MASK  (0x80U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD3_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD3_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK (0x400U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK (0x800U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD2_MASK  (0xF000U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD2_SHIFT (12U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD2_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD2_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD1_MASK  (0xFC0000U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD1_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD1_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD0_MASK  (0x7E000000U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD0_SHIFT (25U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD0_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_RSVD0_MASK)

#define PXP_INPUT_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK (0x80000000U)
#define PXP_INPUT_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_INPUT_STORE_CTRL_CH0_TOG_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK)
/*! @} */

/*! @name INPUT_STORE_CTRL_CH1 - Store engine Control Channel 1 Register */
/*! @{ */

#define PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK      (0x1U)
#define PXP_INPUT_STORE_CTRL_CH1_CH_EN_SHIFT     (0U)
/*! CH_EN - CH_EN
 *  0b0..Store function is disable
 *  0b1..Store function is enable
 */
#define PXP_INPUT_STORE_CTRL_CH1_CH_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN_MASK   (0x2U)
#define PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN_SHIFT  (1U)
/*! BLOCK_EN - BLOCK_EN
 *  0b0..Store in scan mode
 *  0b1..Store in block mode
 */
#define PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_BLOCK_16_MASK   (0x4U)
#define PXP_INPUT_STORE_CTRL_CH1_BLOCK_16_SHIFT  (2U)
/*! BLOCK_16 - BLOCK_16
 *  0b0..BLK_SIZE_8x8 : Block size is 8x8
 *  0b1..BLK_SIZE_16x16 : Block size is 16x16
 */
#define PXP_INPUT_STORE_CTRL_CH1_BLOCK_16(x)     (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_BLOCK_16_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN
 *  0b0..Handshake with the fetch engine is disabled
 *  0b1..Handshake with the fetch engine is enabled
 */
#define PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN_MASK   (0x10U)
#define PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN_SHIFT  (4U)
/*! ARRAY_EN - ARRAY_EN
 *  0b0..Array Handshake Disabled
 *  0b1..Array Handshake Enabled
 */
#define PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM
 *  0b00..Using 1x1 Array
 *  0b01..Using 3x3 Array
 *  0b10..Using 5x5 Array
 *  0b11..Using 5x5 Array
 */
#define PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_RSVD3_MASK      (0x80U)
#define PXP_INPUT_STORE_CTRL_CH1_RSVD3_SHIFT     (7U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_STORE_CTRL_CH1_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_RSVD3_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_RSVD3_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN
 *  0b0..store bypass mode disable.
 *  0b1..store bypass mode enable. Data will bypass to store output.
 */
#define PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN
 *  0b0..store memory mode disable.
 *  0b1..store memory mode enable. Data will store to memory.
 */
#define PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL_MASK (0x400U)
#define PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL
 *  0b0..select 64 shift out data to pack
 *  0b1..select channel 0 high 32 bit shift out data to pack
 */
#define PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_RSVD1_MASK      (0xF800U)
#define PXP_INPUT_STORE_CTRL_CH1_RSVD1_SHIFT     (11U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_CTRL_CH1_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_RSVD1_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_RSVD1_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES
 *  0b00..NUM_8_BYTES : 8 bytes
 *  0b01..NUM_16_BYTES : 16 bytes
 *  0b10..NUM_32_BYTES : 32 bytes
 *  0b11..NUM_64_BYTES : 64 bytes
 */
#define PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_RSVD0_MASK      (0xFFFC0000U)
#define PXP_INPUT_STORE_CTRL_CH1_RSVD0_SHIFT     (18U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_CTRL_CH1_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_RSVD0_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_CTRL_CH1_SET - Store engine Control Channel 1 Register */
/*! @{ */

#define PXP_INPUT_STORE_CTRL_CH1_SET_CH_EN_MASK  (0x1U)
#define PXP_INPUT_STORE_CTRL_CH1_SET_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_INPUT_STORE_CTRL_CH1_SET_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_CH_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_EN_MASK (0x2U)
#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_16_MASK (0x4U)
#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_16_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_INPUT_STORE_CTRL_CH1_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_SET_ARRAY_EN_MASK (0x10U)
#define PXP_INPUT_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_INPUT_STORE_CTRL_CH1_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_ARRAY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_INPUT_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_INPUT_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_SET_RSVD3_MASK  (0x80U)
#define PXP_INPUT_STORE_CTRL_CH1_SET_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_STORE_CTRL_CH1_SET_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_RSVD3_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_RSVD3_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_INPUT_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_INPUT_STORE_CTRL_CH1_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_INPUT_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_INPUT_STORE_CTRL_CH1_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK (0x400U)
#define PXP_INPUT_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_INPUT_STORE_CTRL_CH1_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_SET_RSVD1_MASK  (0xF800U)
#define PXP_INPUT_STORE_CTRL_CH1_SET_RSVD1_SHIFT (11U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_CTRL_CH1_SET_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_RSVD1_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_RSVD1_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_INPUT_STORE_CTRL_CH1_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_SET_RSVD0_MASK  (0xFFFC0000U)
#define PXP_INPUT_STORE_CTRL_CH1_SET_RSVD0_SHIFT (18U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_CTRL_CH1_SET_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_RSVD0_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_CTRL_CH1_CLR - Store engine Control Channel 1 Register */
/*! @{ */

#define PXP_INPUT_STORE_CTRL_CH1_CLR_CH_EN_MASK  (0x1U)
#define PXP_INPUT_STORE_CTRL_CH1_CLR_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_INPUT_STORE_CTRL_CH1_CLR_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_CH_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK (0x2U)
#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_16_MASK (0x4U)
#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_16_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_INPUT_STORE_CTRL_CH1_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK (0x10U)
#define PXP_INPUT_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_INPUT_STORE_CTRL_CH1_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_INPUT_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_INPUT_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD3_MASK  (0x80U)
#define PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD3_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD3_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK (0x400U)
#define PXP_INPUT_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_INPUT_STORE_CTRL_CH1_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD1_MASK  (0xF800U)
#define PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD1_SHIFT (11U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD1_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD1_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_INPUT_STORE_CTRL_CH1_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD0_MASK  (0xFFFC0000U)
#define PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD0_SHIFT (18U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD0_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_CTRL_CH1_TOG - Store engine Control Channel 1 Register */
/*! @{ */

#define PXP_INPUT_STORE_CTRL_CH1_TOG_CH_EN_MASK  (0x1U)
#define PXP_INPUT_STORE_CTRL_CH1_TOG_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_INPUT_STORE_CTRL_CH1_TOG_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_CH_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK (0x2U)
#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_16_MASK (0x4U)
#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_16_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK (0x8U)
#define PXP_INPUT_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_INPUT_STORE_CTRL_CH1_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK (0x10U)
#define PXP_INPUT_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_INPUT_STORE_CTRL_CH1_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_INPUT_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_INPUT_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD3_MASK  (0x80U)
#define PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD3_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD3_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK (0x400U)
#define PXP_INPUT_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_INPUT_STORE_CTRL_CH1_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD1_MASK  (0xF800U)
#define PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD1_SHIFT (11U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD1_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD1_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_INPUT_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_INPUT_STORE_CTRL_CH1_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK)

#define PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD0_MASK  (0xFFFC0000U)
#define PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD0_SHIFT (18U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD0_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_STATUS_CH0 - Store engine status Channel 0 Register */
/*! @{ */

#define PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X_MASK (0xFFFFU)
#define PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT (0U)
/*! STORE_BLOCK_X - STORE_BLOCK_X */
#define PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT)) & PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X_MASK)

#define PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK (0xFFFF0000U)
#define PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT (16U)
/*! STORE_BLOCK_Y - STORE_BLOCK_Y */
#define PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT)) & PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK)
/*! @} */

/*! @name INPUT_STORE_STATUS_CH1 - Store engine status Channel 1 Register */
/*! @{ */

#define PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X_MASK (0xFFFFU)
#define PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT (0U)
/*! STORE_BLOCK_X - STORE_BLOCK_X */
#define PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT)) & PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X_MASK)

#define PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK (0xFFFF0000U)
#define PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT (16U)
/*! STORE_BLOCK_Y - STORE_BLOCK_Y */
#define PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT)) & PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK)
/*! @} */

/*! @name INPUT_STORE_SIZE_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH_MASK  (0xFFFFU)
#define PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH_SHIFT (0U)
/*! OUT_WIDTH - OUT_WIDTH */
#define PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH_SHIFT)) & PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH_MASK)

#define PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT_MASK (0xFFFF0000U)
#define PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT (16U)
/*! OUT_HEIGHT - OUT_HEIGHT */
#define PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT)) & PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT_MASK)
/*! @} */

/*! @name INPUT_STORE_SIZE_CH1 -  */
/*! @{ */

#define PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH_MASK  (0xFFFFU)
#define PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH_SHIFT (0U)
/*! OUT_WIDTH - OUT_WIDTH */
#define PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH(x)    (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH_SHIFT)) & PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH_MASK)

#define PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT_MASK (0xFFFF0000U)
#define PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT (16U)
/*! OUT_HEIGHT - OUT_HEIGHT */
#define PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT)) & PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT_MASK)
/*! @} */

/*! @name INPUT_STORE_PITCH -  */
/*! @{ */

#define PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_MASK (0xFFFFU)
#define PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_SHIFT (0U)
/*! CH0_OUT_PITCH - CH0_OUT_PITCH */
#define PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_SHIFT)) & PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_MASK)

#define PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH_MASK (0xFFFF0000U)
#define PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH_SHIFT (16U)
/*! CH1_OUT_PITCH - CH1_OUT_PITCH */
#define PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH_SHIFT)) & PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH_MASK)
/*! @} */

/*! @name INPUT_STORE_SHIFT_CTRL_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2_MASK (0x3U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP
 *  0b00..8 bits
 *  0b01..16 bits
 *  0b10..32 bits
 *  0b11..64 bits
 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1_MASK (0x40U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK (0x80U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS
 *  0b0..data will do shift processing.
 *  0b1..data will bypass shift module.
 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0_MASK (0xFFFFFF00U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_SHIFT_CTRL_CH0_SET -  */
/*! @{ */

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD2_MASK (0x3U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD2_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD2_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD1_MASK (0x40U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD1_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD1_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK (0x80U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD0_MASK (0xFFFFFF00U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD0_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_SHIFT_CTRL_CH0_CLR -  */
/*! @{ */

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_MASK (0x3U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_MASK (0x40U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK (0x80U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_MASK (0xFFFFFF00U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_SHIFT_CTRL_CH0_TOG -  */
/*! @{ */

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_MASK (0x3U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_MASK (0x40U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK (0x80U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_MASK (0xFFFFFF00U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_SHIFT_CTRL_CH1 -  */
/*! @{ */

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2_MASK (0x3U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP
 *  0b00..8 bits
 *  0b01..16 bits
 *  0b10..32 bits
 *  0b11..32 bits
 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_SHIFT_CTRL_CH1_SET -  */
/*! @{ */

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_RSVD2_MASK (0x3U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_RSVD2_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_RSVD2_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_RSVD0_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_SHIFT_CTRL_CH1_CLR -  */
/*! @{ */

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_MASK (0x3U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_SHIFT_CTRL_CH1_TOG -  */
/*! @{ */

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_MASK (0x3U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK)

#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_ADDR_0_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT (0U)
/*! OUT_BASE_ADDR0 - OUT_BASE_ADDR0 */
#define PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT)) & PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK)
/*! @} */

/*! @name INPUT_STORE_ADDR_1_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT (0U)
/*! OUT_BASE_ADDR1 - OUT_BASE_ADDR1 */
#define PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT)) & PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK)
/*! @} */

/*! @name INPUT_STORE_FILL_DATA_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT (0U)
/*! FILL_DATA_CH0 - FILL_DATA_CH0 */
#define PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT)) & PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_ADDR_0_CH1 -  */
/*! @{ */

#define PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT (0U)
/*! OUT_BASE_ADDR0 - OUT_BASE_ADDR0 */
#define PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT)) & PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK)
/*! @} */

/*! @name INPUT_STORE_ADDR_1_CH1 -  */
/*! @{ */

#define PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT (0U)
/*! OUT_BASE_ADDR1 - OUT_BASE_ADDR1 */
#define PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT)) & PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK0_H_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT (0U)
/*! D_MASK0_H_CH0 - D_MASK0_H_CH0 */
#define PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK0_L_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT (0U)
/*! D_MASK0_L_CH0 - D_MASK0_L_CH0 */
#define PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK1_H_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT (0U)
/*! D_MASK1_H_CH0 - D_MASK1_H_CH0 */
#define PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK1_L_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT (0U)
/*! D_MASK1_L_CH0 - D_MASK1_L_CH0 */
#define PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK2_H_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT (0U)
/*! D_MASK2_H_CH0 - D_MASK2_H_CH0 */
#define PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK2_L_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT (0U)
/*! D_MASK2_L_CH0 - D_MASK2_L_CH0 */
#define PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK3_H_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT (0U)
/*! D_MASK3_H_CH0 - D_MASK3_H_CH0 */
#define PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK3_L_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT (0U)
/*! D_MASK3_L_CH0 - D_MASK3_L_CH0 */
#define PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK4_H_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT (0U)
/*! D_MASK4_H_CH0 - D_MASK4_H_CH0 */
#define PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK4_L_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT (0U)
/*! D_MASK4_L_CH0 - D_MASK4_L_CH0 */
#define PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK5_H_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT (0U)
/*! D_MASK5_H_CH0 - D_MASK5_H_CH0 */
#define PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK5_L_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT (0U)
/*! D_MASK5_L_CH0 - D_MASK5_L_CH0 */
#define PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK6_H_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT (0U)
/*! D_MASK6_H_CH0 - D_MASK6_H_CH0 */
#define PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK6_L_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT (0U)
/*! D_MASK6_L_CH0 - D_MASK6_L_CH0 */
#define PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK7_H_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT (0U)
/*! D_MASK7_H_CH0 - D_MASK7_H_CH0 */
#define PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_MASK7_L_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT (0U)
/*! D_MASK7_L_CH0 - D_MASK7_L_CH0 */
#define PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT)) & PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK)
/*! @} */

/*! @name INPUT_STORE_D_SHIFT_L_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK (0x3FU)
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT (0U)
/*! D_SHIFT_WIDTH0 - D_SHIFT_WIDTH0 */
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK)

#define PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3_MASK (0x40U)
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3_SHIFT (6U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3_MASK)

#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK (0x80U)
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT (7U)
/*! D_SHIFT_FLAG0 - D_SHIFT_FLAG0 */
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK)

#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK (0x3F00U)
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT (8U)
/*! D_SHIFT_WIDTH1 - D_SHIFT_WIDTH1 */
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK)

#define PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2_MASK (0x4000U)
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2_MASK)

#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK (0x8000U)
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT (15U)
/*! D_SHIFT_FLAG1 - D_SHIFT_FLAG1 */
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK)

#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK (0x3F0000U)
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT (16U)
/*! D_SHIFT_WIDTH2 - D_SHIFT_WIDTH2 */
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK)

#define PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1_MASK (0x400000U)
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1_SHIFT (22U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1_MASK)

#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK (0x800000U)
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT (23U)
/*! D_SHIFT_FLAG2 - D_SHIFT_FLAG2 */
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK)

#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK (0x3F000000U)
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT (24U)
/*! D_SHIFT_WIDTH3 - D_SHIFT_WIDTH3 */
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK)

#define PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0_MASK (0x40000000U)
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0_SHIFT (30U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0_MASK)

#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK (0x80000000U)
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT (31U)
/*! D_SHIFT_FLAG3 - D_SHIFT_FLAG3 */
#define PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK)
/*! @} */

/*! @name INPUT_STORE_D_SHIFT_H_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK (0x3FU)
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT (0U)
/*! D_SHIFT_WIDTH4 - D_SHIFT_WIDTH4 */
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK)

#define PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3_MASK (0x40U)
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3_SHIFT (6U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3_MASK)

#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK (0x80U)
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT (7U)
/*! D_SHIFT_FLAG4 - D_SHIFT_FLAG4 */
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK)

#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK (0x3F00U)
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT (8U)
/*! D_SHIFT_WIDTH5 - D_SHIFT_WIDTH5 */
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK)

#define PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2_MASK (0x4000U)
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2_MASK)

#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK (0x8000U)
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT (15U)
/*! D_SHIFT_FLAG5 - D_SHIFT_FLAG5 */
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK)

#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK (0x3F0000U)
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT (16U)
/*! D_SHIFT_WIDTH6 - D_SHIFT_WIDTH6 */
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK)

#define PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1_MASK (0x400000U)
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1_SHIFT (22U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1_MASK)

#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK (0x800000U)
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT (23U)
/*! D_SHIFT_FLAG6 - D_SHIFT_FLAG6 */
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK)

#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK (0x3F000000U)
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT (24U)
/*! D_SHIFT_WIDTH7 - D_SHIFT_WIDTH7 */
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK)

#define PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0_MASK (0x40000000U)
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0_SHIFT (30U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0_MASK)

#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK (0x80000000U)
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT (31U)
/*! D_SHIFT_FLAG7 - D_SHIFT_FLAG7 */
#define PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT)) & PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK)
/*! @} */

/*! @name INPUT_STORE_F_SHIFT_L_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK (0x3FU)
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT (0U)
/*! F_SHIFT_WIDTH0 - F_SHIFT_WIDTH0 */
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK)

#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK (0x40U)
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT (6U)
/*! F_SHIFT_FLAG0 - F_SHIFT_FLAG0 */
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK)

#define PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3_MASK (0x80U)
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3_MASK)

#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK (0x3F00U)
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT (8U)
/*! F_SHIFT_WIDTH1 - F_SHIFT_WIDTH1 */
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK)

#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK (0x4000U)
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT (14U)
/*! F_SHIFT_FLAG1 - F_SHIFT_FLAG1 */
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK)

#define PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2_MASK (0x8000U)
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2_SHIFT (15U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2_MASK)

#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK (0x3F0000U)
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT (16U)
/*! F_SHIFT_WIDTH2 - F_SHIFT_WIDTH2 */
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK)

#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK (0x400000U)
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT (22U)
/*! F_SHIFT_FLAG2 - F_SHIFT_FLAG2 */
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK)

#define PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1_MASK (0x800000U)
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1_SHIFT (23U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1_MASK)

#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK (0x3F000000U)
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT (24U)
/*! F_SHIFT_WIDTH3 - F_SHIFT_WIDTH3 */
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK)

#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK (0x40000000U)
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT (30U)
/*! F_SHIFT_FLAG3 - F_SHIFT_FLAG3 */
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK)

#define PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0_MASK (0x80000000U)
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0_SHIFT (31U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_F_SHIFT_H_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK (0x3FU)
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT (0U)
/*! F_SHIFT_WIDTH4 - F_SHIFT_WIDTH4 */
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK)

#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK (0x40U)
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT (6U)
/*! F_SHIFT_FLAG4 - F_SHIFT_FLAG4 */
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK)

#define PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3_MASK (0x80U)
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3_MASK)

#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK (0x3F00U)
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT (8U)
/*! F_SHIFT_WIDTH5 - F_SHIFT_WIDTH5 */
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK)

#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK (0x4000U)
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT (14U)
/*! F_SHIFT_FLAG5 - F_SHIFT_FLAG5 */
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK)

#define PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2_MASK (0x8000U)
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2_SHIFT (15U)
/*! RSVD2 - RSVD2 */
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2_MASK)

#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK (0x3F0000U)
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT (16U)
/*! F_SHIFT_WIDTH6 - F_SHIFT_WIDTH6 */
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK)

#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK (0x400000U)
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT (22U)
/*! F_SHIFT_FLAG6 - F_SHIFT_FLAG6 */
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK)

#define PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1_MASK (0x800000U)
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1_SHIFT (23U)
/*! RSVD1 - RSVD1 */
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1_MASK)

#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK (0x3F000000U)
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT (24U)
/*! F_SHIFT_WIDTH7 - F_SHIFT_WIDTH7 */
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK)

#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK (0x40000000U)
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT (30U)
/*! F_SHIFT_FLAG7 - F_SHIFT_FLAG7 */
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK)

#define PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0_MASK (0x80000000U)
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0_SHIFT (31U)
/*! RSVD0 - RSVD0 */
#define PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0_SHIFT)) & PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0_MASK)
/*! @} */

/*! @name INPUT_STORE_F_MASK_L_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0_MASK (0xFFU)
#define PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0_SHIFT (0U)
/*! F_MASK0 - F_MASK0 */
#define PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0_SHIFT)) & PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0_MASK)

#define PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1_MASK (0xFF00U)
#define PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1_SHIFT (8U)
/*! F_MASK1 - F_MASK1 */
#define PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1_SHIFT)) & PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1_MASK)

#define PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2_MASK (0xFF0000U)
#define PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2_SHIFT (16U)
/*! F_MASK2 - F_MASK2 */
#define PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2_SHIFT)) & PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2_MASK)

#define PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3_MASK (0xFF000000U)
#define PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3_SHIFT (24U)
/*! F_MASK3 - F_MASK3 */
#define PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3_SHIFT)) & PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3_MASK)
/*! @} */

/*! @name INPUT_STORE_F_MASK_H_CH0 -  */
/*! @{ */

#define PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4_MASK (0xFFU)
#define PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4_SHIFT (0U)
/*! F_MASK4 - F_MASK4 */
#define PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4_SHIFT)) & PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4_MASK)

#define PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5_MASK (0xFF00U)
#define PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5_SHIFT (8U)
/*! F_MASK5 - F_MASK5 */
#define PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5_SHIFT)) & PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5_MASK)

#define PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6_MASK (0xFF0000U)
#define PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6_SHIFT (16U)
/*! F_MASK6 - F_MASK6 */
#define PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6_SHIFT)) & PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6_MASK)

#define PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7_MASK (0xFF000000U)
#define PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7_SHIFT (24U)
/*! F_MASK7 - F_MASK7 */
#define PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7(x)  (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7_SHIFT)) & PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7_MASK)
/*! @} */

/*! @name DITHER_FETCH_CTRL_CH0 - Pre-fetch engine Control Channel 0 Register */
/*! @{ */

#define PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK     (0x1U)
#define PXP_DITHER_FETCH_CTRL_CH0_CH_EN_SHIFT    (0U)
/*! CH_EN - CH_EN
 *  0b0..Prefetch function is disable
 *  0b1..Prefetch function is enable
 */
#define PXP_DITHER_FETCH_CTRL_CH0_CH_EN(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CH_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN_MASK  (0x2U)
#define PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN
 *  0b0..Prefetch in scan mode
 *  0b1..Prefetch in block mode
 */
#define PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16_MASK  (0x4U)
#define PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16
 *  0b0..BLK_SIZE_8x8 : Block size is 8x8
 *  0b1..BLK_SIZE_16x16 : Block size is 16x16
 */
#define PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN
 *  0b0..Handshake with the store engine is disabled
 *  0b1..Handshake with the store engine is enabled
 */
#define PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN
 *  0b0..Channel 0 is from memory
 *  0b1..Channel 0 is from previous process engine
 */
#define PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE_MASK (0x20U)
#define PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE_SHIFT (5U)
/*! HIGH_BYTE - HIGH_BYTE
 *  0b0..In 64 bit mode, the output high byte will use channel1.
 *  0b1..In 64 bit mode, the output high byte will use channel0
 */
#define PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_RSVD4_MASK     (0x1C0U)
#define PXP_DITHER_FETCH_CTRL_CH0_RSVD4_SHIFT    (6U)
/*! RSVD4 - RSVD4 */
#define PXP_DITHER_FETCH_CTRL_CH0_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_RSVD4_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_RSVD4_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_HFLIP_MASK     (0x200U)
#define PXP_DITHER_FETCH_CTRL_CH0_HFLIP_SHIFT    (9U)
/*! HFLIP - HFLIP
 *  0b0..HFLIP disable
 *  0b1..VFLIP enable
 */
#define PXP_DITHER_FETCH_CTRL_CH0_HFLIP(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_HFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_HFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_VFLIP_MASK     (0x400U)
#define PXP_DITHER_FETCH_CTRL_CH0_VFLIP_SHIFT    (10U)
/*! VFLIP - VFLIP
 *  0b0..VFLIP disable
 *  0b1..VFLIP enable
 */
#define PXP_DITHER_FETCH_CTRL_CH0_VFLIP(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_VFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_VFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_RSVD3_MASK     (0x800U)
#define PXP_DITHER_FETCH_CTRL_CH0_RSVD3_SHIFT    (11U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_CTRL_CH0_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_RSVD3_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_RSVD3_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE
 *  0b00..ROT_0 : Rotate image by 0 degrees.
 *  0b01..ROT_90 : Rotate image by 90 degrees.
 *  0b10..ROT_180 : Rotate image by 180 degrees.
 *  0b11..ROT_270 : Rotate image by 270 degrees.
 */
#define PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_RSVD2_MASK     (0xC000U)
#define PXP_DITHER_FETCH_CTRL_CH0_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_CTRL_CH0_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_RSVD2_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_RSVD2_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES
 *  0b00..NUM_8_BYTES : 8 bytes.
 *  0b01..NUM_16_BYTES : 16 bytes.
 *  0b10..NUM_32_BYTES : 32 bytes.
 *  0b11..NUM_64_BYTES : 64 bytes.
 */
#define PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_RSVD1_MASK     (0xFC0000U)
#define PXP_DITHER_FETCH_CTRL_CH0_RSVD1_SHIFT    (18U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_CTRL_CH0_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_RSVD1_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_RSVD1_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM
 *  0b00..1 line.
 *  0b01..8 lines
 *  0b10..16 lines
 *  0b11..16 lines
 */
#define PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_RSVD0_MASK     (0x7C000000U)
#define PXP_DITHER_FETCH_CTRL_CH0_RSVD0_SHIFT    (26U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_CTRL_CH0_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_RSVD0_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_RSVD0_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN_MASK  (0x80000000U)
#define PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN
 *  0b0..Arbitration disable. If using 2 channels, will output 2 axi bus sets.
 *  0b1..Arbitration enable. If using 2 channel, will only output 1 axi bus sets
 */
#define PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN_MASK)
/*! @} */

/*! @name DITHER_FETCH_CTRL_CH0_SET - Pre-fetch engine Control Channel 0 Register */
/*! @{ */

#define PXP_DITHER_FETCH_CTRL_CH0_SET_CH_EN_MASK (0x1U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_CH_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_CH_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_CH_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_BLOCK_EN_MASK (0x2U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_BLOCK_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_BLOCK_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_BLOCK_16_MASK (0x4U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_BLOCK_16_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_BLOCK_16_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_HANDSHAKE_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_BYPASS_PIXEL_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_BYPASS_PIXEL_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_HIGH_BYTE_MASK (0x20U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_HIGH_BYTE_SHIFT (5U)
/*! HIGH_BYTE - HIGH_BYTE */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_HIGH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_HIGH_BYTE_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_HIGH_BYTE_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD4_MASK (0x1C0U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD4_SHIFT (6U)
/*! RSVD4 - RSVD4 */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD4(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD4_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD4_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_HFLIP_MASK (0x200U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_HFLIP_SHIFT (9U)
/*! HFLIP - HFLIP */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_HFLIP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_HFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_HFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_VFLIP_MASK (0x400U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_VFLIP_SHIFT (10U)
/*! VFLIP - VFLIP */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_VFLIP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_VFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_VFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD3_MASK (0x800U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD3_SHIFT (11U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD3_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD3_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_ROTATION_ANGLE_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_ROTATION_ANGLE_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD2_MASK (0xC000U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD2_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD2_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_RD_NUM_BYTES_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_RD_NUM_BYTES_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD1_MASK (0xFC0000U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD1_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD1_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD0_MASK (0x7C000000U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD0_SHIFT (26U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD0_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_RSVD0_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_SET_ARBIT_EN_MASK (0x80000000U)
#define PXP_DITHER_FETCH_CTRL_CH0_SET_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_SET_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_SET_ARBIT_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_SET_ARBIT_EN_MASK)
/*! @} */

/*! @name DITHER_FETCH_CTRL_CH0_CLR - Pre-fetch engine Control Channel 0 Register */
/*! @{ */

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_CH_EN_MASK (0x1U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_CH_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_CH_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_CH_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_BLOCK_EN_MASK (0x2U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_BLOCK_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_BLOCK_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_BLOCK_16_MASK (0x4U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_BLOCK_16_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_BLOCK_16_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_HANDSHAKE_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_BYPASS_PIXEL_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_BYPASS_PIXEL_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_HIGH_BYTE_MASK (0x20U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_HIGH_BYTE_SHIFT (5U)
/*! HIGH_BYTE - HIGH_BYTE */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_HIGH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_HIGH_BYTE_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_HIGH_BYTE_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD4_MASK (0x1C0U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD4_SHIFT (6U)
/*! RSVD4 - RSVD4 */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD4(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD4_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD4_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_HFLIP_MASK (0x200U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_HFLIP_SHIFT (9U)
/*! HFLIP - HFLIP */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_HFLIP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_HFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_HFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_VFLIP_MASK (0x400U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_VFLIP_SHIFT (10U)
/*! VFLIP - VFLIP */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_VFLIP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_VFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_VFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD3_MASK (0x800U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD3_SHIFT (11U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD3_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD3_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD2_MASK (0xC000U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD2_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD2_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD1_MASK (0xFC0000U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD1_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD1_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD0_MASK (0x7C000000U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD0_SHIFT (26U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD0_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_RSVD0_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_CLR_ARBIT_EN_MASK (0x80000000U)
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_CLR_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_CLR_ARBIT_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_CLR_ARBIT_EN_MASK)
/*! @} */

/*! @name DITHER_FETCH_CTRL_CH0_TOG - Pre-fetch engine Control Channel 0 Register */
/*! @{ */

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_CH_EN_MASK (0x1U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_CH_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_CH_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_CH_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_BLOCK_EN_MASK (0x2U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_BLOCK_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_BLOCK_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_BLOCK_16_MASK (0x4U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_BLOCK_16_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_BLOCK_16_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_HANDSHAKE_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_BYPASS_PIXEL_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_BYPASS_PIXEL_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_HIGH_BYTE_MASK (0x20U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_HIGH_BYTE_SHIFT (5U)
/*! HIGH_BYTE - HIGH_BYTE */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_HIGH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_HIGH_BYTE_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_HIGH_BYTE_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD4_MASK (0x1C0U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD4_SHIFT (6U)
/*! RSVD4 - RSVD4 */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD4(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD4_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD4_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_HFLIP_MASK (0x200U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_HFLIP_SHIFT (9U)
/*! HFLIP - HFLIP */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_HFLIP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_HFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_HFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_VFLIP_MASK (0x400U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_VFLIP_SHIFT (10U)
/*! VFLIP - VFLIP */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_VFLIP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_VFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_VFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD3_MASK (0x800U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD3_SHIFT (11U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD3_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD3_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD2_MASK (0xC000U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD2_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD2_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD1_MASK (0xFC0000U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD1_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD1_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD0_MASK (0x7C000000U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD0_SHIFT (26U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD0_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_RSVD0_MASK)

#define PXP_DITHER_FETCH_CTRL_CH0_TOG_ARBIT_EN_MASK (0x80000000U)
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_DITHER_FETCH_CTRL_CH0_TOG_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH0_TOG_ARBIT_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH0_TOG_ARBIT_EN_MASK)
/*! @} */

/*! @name DITHER_FETCH_CTRL_CH1 - Pre-fetch engine Control Channel 1 Register */
/*! @{ */

#define PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK     (0x1U)
#define PXP_DITHER_FETCH_CTRL_CH1_CH_EN_SHIFT    (0U)
/*! CH_EN - CH_EN
 *  0b0..Prefetch function is disable
 *  0b1..Prefetch function is enable
 */
#define PXP_DITHER_FETCH_CTRL_CH1_CH_EN(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CH_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN_MASK  (0x2U)
#define PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN
 *  0b0..Prefetch in scan mode
 *  0b1..Prefetch in block mode
 */
#define PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16_MASK  (0x4U)
#define PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16
 *  0b0..BLK_SIZE_8x8 : Block size is 8x8
 *  0b1..BLK_SIZE_16x16 : Block size is 16x16
 */
#define PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN
 *  0b0..Handshake with the store engine is disabled
 *  0b1..Handshake with the store engine is enabled
 */
#define PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN
 *  0b0..Channel 1 is from memory
 *  0b1..Channel 1 is from previous process engine
 */
#define PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_RSVD4_MASK     (0x1E0U)
#define PXP_DITHER_FETCH_CTRL_CH1_RSVD4_SHIFT    (5U)
/*! RSVD4 - RSVD4 */
#define PXP_DITHER_FETCH_CTRL_CH1_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_RSVD4_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_RSVD4_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_HFLIP_MASK     (0x200U)
#define PXP_DITHER_FETCH_CTRL_CH1_HFLIP_SHIFT    (9U)
/*! HFLIP - HFLIP
 *  0b0..HFLIP disable
 *  0b1..VFLIP enable
 */
#define PXP_DITHER_FETCH_CTRL_CH1_HFLIP(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_HFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_HFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_VFLIP_MASK     (0x400U)
#define PXP_DITHER_FETCH_CTRL_CH1_VFLIP_SHIFT    (10U)
/*! VFLIP - VFLIP
 *  0b0..VFLIP disable
 *  0b1..VFLIP enable
 */
#define PXP_DITHER_FETCH_CTRL_CH1_VFLIP(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_VFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_VFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_RSVD3_MASK     (0x800U)
#define PXP_DITHER_FETCH_CTRL_CH1_RSVD3_SHIFT    (11U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_CTRL_CH1_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_RSVD3_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_RSVD3_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE
 *  0b00..ROT_0 : Rotate image by 0 degrees.
 *  0b01..ROT_90 : Rotate image by 90 degrees.
 *  0b10..ROT_180 : Rotate image by 180 degrees.
 *  0b11..ROT_270 : Rotate image by 270 degrees.
 */
#define PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_RSVD2_MASK     (0xC000U)
#define PXP_DITHER_FETCH_CTRL_CH1_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_CTRL_CH1_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_RSVD2_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_RSVD2_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES
 *  0b00..NUM_8_BYTES : 8 bytes.
 *  0b01..NUM_16_BYTES : 16 bytes.
 *  0b10..NUM_32_BYTES : 32 bytes.
 *  0b11..NUM_64_BYTES : 64 bytes.
 */
#define PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_RSVD1_MASK     (0xFC0000U)
#define PXP_DITHER_FETCH_CTRL_CH1_RSVD1_SHIFT    (18U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_CTRL_CH1_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_RSVD1_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_RSVD1_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM
 *  0b00..1 line.
 *  0b01..8 lines
 *  0b10..16 lines
 *  0b11..16 lines
 */
#define PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_RSVD0_MASK     (0xFC000000U)
#define PXP_DITHER_FETCH_CTRL_CH1_RSVD0_SHIFT    (26U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_CTRL_CH1_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_RSVD0_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_CTRL_CH1_SET - Pre-fetch engine Control Channel 1 Register */
/*! @{ */

#define PXP_DITHER_FETCH_CTRL_CH1_SET_CH_EN_MASK (0x1U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_CH_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_CH_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_CH_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_BLOCK_EN_MASK (0x2U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_BLOCK_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_BLOCK_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_BLOCK_16_MASK (0x4U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_BLOCK_16_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_BLOCK_16_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_HANDSHAKE_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_BYPASS_PIXEL_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_BYPASS_PIXEL_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD4_MASK (0x1E0U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD4_SHIFT (5U)
/*! RSVD4 - RSVD4 */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD4(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD4_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD4_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_HFLIP_MASK (0x200U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_HFLIP_SHIFT (9U)
/*! HFLIP - HFLIP */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_HFLIP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_HFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_HFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_VFLIP_MASK (0x400U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_VFLIP_SHIFT (10U)
/*! VFLIP - VFLIP */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_VFLIP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_VFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_VFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD3_MASK (0x800U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD3_SHIFT (11U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD3_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD3_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_ROTATION_ANGLE_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_ROTATION_ANGLE_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD2_MASK (0xC000U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD2_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD2_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_RD_NUM_BYTES_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_RD_NUM_BYTES_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD1_MASK (0xFC0000U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD1_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD1_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD0_MASK (0xFC000000U)
#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD0_SHIFT (26U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD0_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_CTRL_CH1_CLR - Pre-fetch engine Control Channel 1 Register */
/*! @{ */

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_CH_EN_MASK (0x1U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_CH_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_CH_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_CH_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_BLOCK_EN_MASK (0x2U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_BLOCK_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_BLOCK_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_BLOCK_16_MASK (0x4U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_BLOCK_16_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_BLOCK_16_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_HANDSHAKE_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_BYPASS_PIXEL_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_BYPASS_PIXEL_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD4_MASK (0x1E0U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD4_SHIFT (5U)
/*! RSVD4 - RSVD4 */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD4(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD4_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD4_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_HFLIP_MASK (0x200U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_HFLIP_SHIFT (9U)
/*! HFLIP - HFLIP */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_HFLIP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_HFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_HFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_VFLIP_MASK (0x400U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_VFLIP_SHIFT (10U)
/*! VFLIP - VFLIP */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_VFLIP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_VFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_VFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD3_MASK (0x800U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD3_SHIFT (11U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD3_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD3_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD2_MASK (0xC000U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD2_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD2_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD1_MASK (0xFC0000U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD1_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD1_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD0_MASK (0xFC000000U)
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD0_SHIFT (26U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD0_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_CTRL_CH1_TOG - Pre-fetch engine Control Channel 1 Register */
/*! @{ */

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_CH_EN_MASK (0x1U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_CH_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_CH_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_CH_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_BLOCK_EN_MASK (0x2U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_BLOCK_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_BLOCK_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_BLOCK_16_MASK (0x4U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_BLOCK_16_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_BLOCK_16_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_HANDSHAKE_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_BYPASS_PIXEL_EN_MASK (0x10U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_BYPASS_PIXEL_EN_SHIFT (4U)
/*! BYPASS_PIXEL_EN - BYPASS_PIXEL_EN */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_BYPASS_PIXEL_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_BYPASS_PIXEL_EN_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_BYPASS_PIXEL_EN_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD4_MASK (0x1E0U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD4_SHIFT (5U)
/*! RSVD4 - RSVD4 */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD4(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD4_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD4_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_HFLIP_MASK (0x200U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_HFLIP_SHIFT (9U)
/*! HFLIP - HFLIP */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_HFLIP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_HFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_HFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_VFLIP_MASK (0x400U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_VFLIP_SHIFT (10U)
/*! VFLIP - VFLIP */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_VFLIP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_VFLIP_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_VFLIP_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD3_MASK (0x800U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD3_SHIFT (11U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD3_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD3_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE_MASK (0x3000U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE_SHIFT (12U)
/*! ROTATION_ANGLE - ROTATION_ANGLE */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD2_MASK (0xC000U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD2_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD2_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES_SHIFT (16U)
/*! RD_NUM_BYTES - RD_NUM_BYTES */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD1_MASK (0xFC0000U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD1_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD1_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_HANDSHAKE_SCAN_LINE_NUM_MASK (0x3000000U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_HANDSHAKE_SCAN_LINE_NUM_SHIFT (24U)
/*! HANDSHAKE_SCAN_LINE_NUM - HANDSHAKE_SCAN_LINE_NUM */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_HANDSHAKE_SCAN_LINE_NUM_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_HANDSHAKE_SCAN_LINE_NUM_MASK)

#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD0_MASK (0xFC000000U)
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD0_SHIFT (26U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD0_SHIFT)) & PXP_DITHER_FETCH_CTRL_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_STATUS_CH0 - Pre-fetch engine status Channel 0 Register */
/*! @{ */

#define PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_MASK (0xFFFFU)
#define PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_SHIFT (0U)
/*! PREFETCH_BLOCK_X - PREFETCH_BLOCK_X */
#define PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_SHIFT)) & PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_MASK)

#define PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_SHIFT (16U)
/*! PREFETCH_BLOCK_Y - PREFETCH_BLOCK_Y */
#define PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_SHIFT)) & PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_MASK)
/*! @} */

/*! @name DITHER_FETCH_STATUS_CH1 - Store engine status Channel 1 Register */
/*! @{ */

#define PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_MASK (0xFFFFU)
#define PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_SHIFT (0U)
/*! PREFETCH_BLOCK_X - PREFETCH_BLOCK_X */
#define PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_SHIFT)) & PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_MASK)

#define PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_SHIFT (16U)
/*! PREFETCH_BLOCK_Y - PREFETCH_BLOCK_Y */
#define PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_SHIFT)) & PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_MASK)
/*! @} */

/*! @name DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 -  */
/*! @{ */

#define PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_MASK (0xFFFFU)
#define PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_SHIFT (0U)
/*! ACTIVE_SIZE_ULC_X - ACTIVE_SIZE_ULC_X */
#define PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_SHIFT)) & PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_MASK)

#define PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_SHIFT (16U)
/*! ACTIVE_SIZE_ULC_Y - ACTIVE_SIZE_ULC_Y */
#define PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_SHIFT)) & PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_MASK)
/*! @} */

/*! @name DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 -  */
/*! @{ */

#define PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_MASK (0xFFFFU)
#define PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_SHIFT (0U)
/*! ACTIVE_SIZE_LRC_X - ACTIVE_SIZE_LRC_X */
#define PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_SHIFT)) & PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_MASK)

#define PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_SHIFT (16U)
/*! ACTIVE_SIZE_LRC_Y - ACTIVE_SIZE_LRC_Y */
#define PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_SHIFT)) & PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_MASK)
/*! @} */

/*! @name DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 -  */
/*! @{ */

#define PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_MASK (0xFFFFU)
#define PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_SHIFT (0U)
/*! ACTIVE_SIZE_ULC_X - ACTIVE_SIZE_ULC_X */
#define PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_SHIFT)) & PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_MASK)

#define PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_SHIFT (16U)
/*! ACTIVE_SIZE_ULC_Y - ACTIVE_SIZE_ULC_Y */
#define PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_SHIFT)) & PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_MASK)
/*! @} */

/*! @name DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 -  */
/*! @{ */

#define PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_MASK (0xFFFFU)
#define PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_SHIFT (0U)
/*! ACTIVE_SIZE_LRC_X - ACTIVE_SIZE_LRC_X */
#define PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_SHIFT)) & PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_MASK)

#define PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_SHIFT (16U)
/*! ACTIVE_SIZE_LRC_Y - ACTIVE_SIZE_LRC_Y */
#define PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_SHIFT)) & PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_MASK)
/*! @} */

/*! @name DITHER_FETCH_SIZE_CH0 -  */
/*! @{ */

#define PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_MASK (0xFFFFU)
#define PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_SHIFT (0U)
/*! INPUT_TOTAL_WIDTH - INPUT_TOTAL_WIDTH */
#define PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_SHIFT)) & PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_MASK)

#define PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_SHIFT (16U)
/*! INPUT_TOTAL_HEIGHT - INPUT_TOTAL_HEIGHT */
#define PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_SHIFT)) & PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_MASK)
/*! @} */

/*! @name DITHER_FETCH_SIZE_CH1 -  */
/*! @{ */

#define PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_MASK (0xFFFFU)
#define PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_SHIFT (0U)
/*! INPUT_TOTAL_WIDTH - INPUT_TOTAL_WIDTH */
#define PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_SHIFT)) & PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_MASK)

#define PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_SHIFT (16U)
/*! INPUT_TOTAL_HEIGHT - INPUT_TOTAL_HEIGHT */
#define PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_SHIFT)) & PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_MASK)
/*! @} */

/*! @name DITHER_FETCH_BACKGROUND_COLOR_CH0 -  */
/*! @{ */

#define PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_MASK (0xFFFFFFFFU)
#define PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_SHIFT (0U)
/*! BACKGROUND_COLOR - BACKGROUND_COLOR */
#define PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_SHIFT)) & PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_MASK)
/*! @} */

/*! @name DITHER_FETCH_BACKGROUND_COLOR_CH1 -  */
/*! @{ */

#define PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_MASK (0xFFFFFFFFU)
#define PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_SHIFT (0U)
/*! BACKGROUND_COLOR - BACKGROUND_COLOR */
#define PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_SHIFT)) & PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_MASK)
/*! @} */

/*! @name DITHER_FETCH_PITCH -  */
/*! @{ */

#define PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH_MASK (0xFFFFU)
#define PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH_SHIFT (0U)
/*! CH0_INPUT_PITCH - CH0_INPUT_PITCH */
#define PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH_SHIFT)) & PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH_MASK)

#define PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH_SHIFT (16U)
/*! CH1_INPUT_PITCH - CH1_INPUT_PITCH */
#define PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH_SHIFT)) & PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_CTRL_CH0 -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP
 *  0b00..8 bits
 *  0b01..16 bits
 *  0b10..32 bits
 *  0b11..32 bits
 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1_MASK (0xFCU)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_MASK (0x700U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT
 *  0b000..RGB 565
 *  0b001..RGB 555
 *  0b010..ARGB 1555
 *  0b011..RGB 444
 *  0b100..ARGB 4444
 *  0b101..YUYV/YVYU
 *  0b110..UYVY/VYUY
 *  0b111..YUV422_2P
 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_MASK (0x800U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN
 *  0b0..channel0 format expanding disable
 *  0b1..channel0 format expanding enable
 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS
 *  0b0..channel0 data will do shift function
 *  0b1..channel0 will bypass shift function
 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0_MASK (0xFFFFE000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_CTRL_CH0_SET -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_RSVD1_MASK (0xFCU)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT_MASK (0x700U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN_MASK (0x800U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_RSVD0_MASK (0xFFFFE000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_CTRL_CH0_CLR -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_RSVD1_MASK (0xFCU)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT_MASK (0x700U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN_MASK (0x800U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_RSVD0_MASK (0xFFFFE000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_CTRL_CH0_TOG -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_RSVD1_MASK (0xFCU)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT_MASK (0x700U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN_MASK (0x800U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_RSVD0_MASK (0xFFFFE000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_CTRL_CH1 -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP
 *  0b00..8 bits
 *  0b01..16 bits
 *  0b10..32 bits
 *  0b11..32 bits
 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1_MASK (0xFCU)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_MASK (0x700U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT
 *  0b000..RGB 565
 *  0b001..RGB 555
 *  0b010..ARGB 1555
 *  0b011..RGB 444
 *  0b100..ARGB 4444
 *  0b101..YUYV/YVYU
 *  0b110..UYVY/VYUY
 *  0b111..YUV422_2P
 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_MASK (0x800U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN
 *  0b0..channel1 format expanding disable
 *  0b1..channel1 format expanding enable
 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS
 *  0b0..channel1 data will do shift function
 *  0b1..channel1 will bypass shift function
 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0_MASK (0xFFFFE000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_CTRL_CH1_SET -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_RSVD1_MASK (0xFCU)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT_MASK (0x700U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN_MASK (0x800U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_RSVD0_MASK (0xFFFFE000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_CTRL_CH1_CLR -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_RSVD1_MASK (0xFCU)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT_MASK (0x700U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN_MASK (0x800U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_RSVD0_MASK (0xFFFFE000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_CTRL_CH1_TOG -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP_MASK (0x3U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP_SHIFT (0U)
/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_RSVD1_MASK (0xFCU)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_RSVD1_SHIFT (2U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT_MASK (0x700U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT_SHIFT (8U)
/*! EXPAND_FORMAT - EXPAND_FORMAT */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN_MASK (0x800U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN_SHIFT (11U)
/*! EXPAND_EN - EXPAND_EN */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS_MASK (0x1000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS_SHIFT (12U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS_MASK)

#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_RSVD0_MASK (0xFFFFE000U)
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_RSVD0_SHIFT (13U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_OFFSET_CH0 -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0_MASK (0x1FU)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3_MASK (0xE0U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1_MASK (0x1F00U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2_MASK (0xE000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2_MASK (0x1F0000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1_MASK (0xE00000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3_MASK (0x1F000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0_MASK (0xE0000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_OFFSET_CH0_SET -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0_MASK (0x1FU)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD3_MASK (0xE0U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1_MASK (0x1F00U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD2_MASK (0xE000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2_MASK (0x1F0000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD1_MASK (0xE00000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3_MASK (0x1F000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD0_MASK (0xE0000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_OFFSET_CH0_CLR -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0_MASK (0x1FU)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD3_MASK (0xE0U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1_MASK (0x1F00U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD2_MASK (0xE000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2_MASK (0x1F0000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD1_MASK (0xE00000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3_MASK (0x1F000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD0_MASK (0xE0000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_OFFSET_CH0_TOG -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0_MASK (0x1FU)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD3_MASK (0xE0U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1_MASK (0x1F00U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD2_MASK (0xE000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2_MASK (0x1F0000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD1_MASK (0xE00000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3_MASK (0x1F000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD0_MASK (0xE0000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_OFFSET_CH1 -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0_MASK (0x1FU)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3_MASK (0xE0U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1_MASK (0x1F00U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2_MASK (0xE000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2_MASK (0x1F0000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1_MASK (0xE00000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3_MASK (0x1F000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0_MASK (0xE0000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_OFFSET_CH1_SET -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0_MASK (0x1FU)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD3_MASK (0xE0U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1_MASK (0x1F00U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD2_MASK (0xE000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2_MASK (0x1F0000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD1_MASK (0xE00000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3_MASK (0x1F000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD0_MASK (0xE0000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_OFFSET_CH1_CLR -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0_MASK (0x1FU)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD3_MASK (0xE0U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1_MASK (0x1F00U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD2_MASK (0xE000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2_MASK (0x1F0000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD1_MASK (0xE00000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3_MASK (0x1F000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD0_MASK (0xE0000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_OFFSET_CH1_TOG -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0_MASK (0x1FU)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0_SHIFT (0U)
/*! OFFSET0 - OFFSET0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD3_MASK (0xE0U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1_MASK (0x1F00U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1_SHIFT (8U)
/*! OFFSET1 - OFFSET1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD2_MASK (0xE000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2_MASK (0x1F0000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2_SHIFT (16U)
/*! OFFSET2 - OFFSET2 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD1_MASK (0xE00000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD1_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3_MASK (0x1F000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3_SHIFT (24U)
/*! OFFSET3 - OFFSET3 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3_MASK)

#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD0_MASK (0xE0000000U)
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_WIDTH_CH0 -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0_MASK (0xFU)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1_MASK (0xF0U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2_MASK (0xF00U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3_MASK (0xF000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_WIDTH_CH0_SET -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0_MASK (0xFU)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1_MASK (0xF0U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2_MASK (0xF00U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3_MASK (0xF000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_RSVD0_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_WIDTH_CH0_CLR -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0_MASK (0xFU)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1_MASK (0xF0U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2_MASK (0xF00U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3_MASK (0xF000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_RSVD0_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_WIDTH_CH0_TOG -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0_MASK (0xFU)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1_MASK (0xF0U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2_MASK (0xF00U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3_MASK (0xF000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_RSVD0_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_WIDTH_CH1 -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0_MASK (0xFU)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1_MASK (0xF0U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2_MASK (0xF00U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3_MASK (0xF000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_WIDTH_CH1_SET -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0_MASK (0xFU)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1_MASK (0xF0U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2_MASK (0xF00U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3_MASK (0xF000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_RSVD0_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_WIDTH_CH1_CLR -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0_MASK (0xFU)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1_MASK (0xF0U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2_MASK (0xF00U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3_MASK (0xF000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_RSVD0_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_SHIFT_WIDTH_CH1_TOG -  */
/*! @{ */

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0_MASK (0xFU)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0_SHIFT (0U)
/*! WIDTH0 - WIDTH0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1_MASK (0xF0U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1_SHIFT (4U)
/*! WIDTH1 - WIDTH1 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2_MASK (0xF00U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2_SHIFT (8U)
/*! WIDTH2 - WIDTH2 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3_MASK (0xF000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3_SHIFT (12U)
/*! WIDTH3 - WIDTH3 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3_MASK)

#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_RSVD0_MASK (0xFFFF0000U)
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_RSVD0_SHIFT (16U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_RSVD0_SHIFT)) & PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name DITHER_FETCH_ADDR_0_CH0 -  */
/*! @{ */

#define PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_SHIFT (0U)
/*! INPUT_BASE_ADDR0 - INPUT_BASE_ADDR0 */
#define PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_SHIFT)) & PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_MASK)
/*! @} */

/*! @name DITHER_FETCH_ADDR_1_CH0 -  */
/*! @{ */

#define PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_MASK (0xFFFFFFFFU)
#define PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_SHIFT (0U)
/*! INPUT_BASE_ADDR1 - INPUT_BASE_ADDR1 */
#define PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_SHIFT)) & PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_MASK)
/*! @} */

/*! @name DITHER_FETCH_ADDR_0_CH1 -  */
/*! @{ */

#define PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_SHIFT (0U)
/*! INPUT_BASE_ADDR0 - INPUT_BASE_ADDR0 */
#define PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_SHIFT)) & PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_MASK)
/*! @} */

/*! @name DITHER_FETCH_ADDR_1_CH1 -  */
/*! @{ */

#define PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_MASK (0xFFFFFFFFU)
#define PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_SHIFT (0U)
/*! INPUT_BASE_ADDR1 - INPUT_BASE_ADDR1 */
#define PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_SHIFT)) & PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_MASK)
/*! @} */

/*! @name DITHER_STORE_CTRL_CH0 - Store engine Control Channel 0 Register */
/*! @{ */

#define PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK     (0x1U)
#define PXP_DITHER_STORE_CTRL_CH0_CH_EN_SHIFT    (0U)
/*! CH_EN - CH_EN
 *  0b0..Store function is disable
 *  0b1..Store function is enable
 */
#define PXP_DITHER_STORE_CTRL_CH0_CH_EN(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CH_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN_MASK  (0x2U)
#define PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN
 *  0b0..Store in scan mode
 *  0b1..Store in block mode
 */
#define PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_BLOCK_16_MASK  (0x4U)
#define PXP_DITHER_STORE_CTRL_CH0_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16
 *  0b0..BLK_SIZE_8x8 : Block size is 8x8
 *  0b1..BLK_SIZE_16x16 : Block size is 16x16
 */
#define PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_BLOCK_16_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_BLOCK_16_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN
 *  0b0..Handshake with the prefetch engine is disabled
 *  0b1..Handshake with the prefetch engine is enabled
 */
#define PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN_MASK  (0x10U)
#define PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN
 *  0b0..Array Handshake Disabled
 *  0b1..Array Handshake Enabled
 */
#define PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM
 *  0b00..Using 1x1 Array
 *  0b01..Using 3x3 Array
 *  0b10..Using 5x5 Array
 *  0b11..Using 5x5 Array
 */
#define PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_RSVD3_MASK     (0x80U)
#define PXP_DITHER_STORE_CTRL_CH0_RSVD3_SHIFT    (7U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_STORE_CTRL_CH0_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_RSVD3_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_RSVD3_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN
 *  0b0..store bypass mode disable.
 *  0b1..store bypass mode enable. Data will bypass to store output.
 */
#define PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN
 *  0b0..store memory mode disable.
 *  0b1..store memory mode enable. Data will store to memory
 */
#define PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL_MASK (0x400U)
#define PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL
 *  0b0..select 64 shift out data to pack
 *  0b1..select low 32 bit shift out data to pack
 */
#define PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN_MASK (0x800U)
#define PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN
 *  0b0..Fill data mode disable.
 *  0b1..Fill data mode enable. When using fill_data mode, store_engine will store fixed data defined in fill_data register
 */
#define PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_RSVD2_MASK     (0xF000U)
#define PXP_DITHER_STORE_CTRL_CH0_RSVD2_SHIFT    (12U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_CTRL_CH0_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_RSVD2_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_RSVD2_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES
 *  0b00..NUM_8_BYTES : 8 bytes
 *  0b01..NUM_16_BYTES : 16 bytes
 *  0b10..NUM_32_BYTES : 32 bytes
 *  0b11..NUM_64_BYTES : 64 bytes
 */
#define PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_RSVD1_MASK     (0xFC0000U)
#define PXP_DITHER_STORE_CTRL_CH0_RSVD1_SHIFT    (18U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_CTRL_CH0_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_RSVD1_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_RSVD1_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL
 *  0b0..combine 2 channel disable
 *  0b1..combine 2 channel enable
 */
#define PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_RSVD0_MASK     (0x7E000000U)
#define PXP_DITHER_STORE_CTRL_CH0_RSVD0_SHIFT    (25U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_CTRL_CH0_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_RSVD0_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_RSVD0_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN_MASK  (0x80000000U)
#define PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN
 *  0b0..Arbitration disable. If using 2 channels, will output 2 axi bus sets
 *  0b1..Arbitration enable. If using 2 channel, will only output 1 axi bus sets
 */
#define PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN_MASK)
/*! @} */

/*! @name DITHER_STORE_CTRL_CH0_SET - Store engine Control Channel 0 Register */
/*! @{ */

#define PXP_DITHER_STORE_CTRL_CH0_SET_CH_EN_MASK (0x1U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_DITHER_STORE_CTRL_CH0_SET_CH_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_CH_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_CH_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_BLOCK_EN_MASK (0x2U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_DITHER_STORE_CTRL_CH0_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_BLOCK_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_BLOCK_16_MASK (0x4U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_DITHER_STORE_CTRL_CH0_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_BLOCK_16_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_DITHER_STORE_CTRL_CH0_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_ARRAY_EN_MASK (0x10U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_DITHER_STORE_CTRL_CH0_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_ARRAY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_DITHER_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_RSVD3_MASK (0x80U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_STORE_CTRL_CH0_SET_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_RSVD3_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_RSVD3_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_DITHER_STORE_CTRL_CH0_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_DITHER_STORE_CTRL_CH0_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK (0x400U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_DITHER_STORE_CTRL_CH0_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK (0x800U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN */
#define PXP_DITHER_STORE_CTRL_CH0_SET_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_RSVD2_MASK (0xF000U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_RSVD2_SHIFT (12U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_CTRL_CH0_SET_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_RSVD2_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_RSVD2_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_DITHER_STORE_CTRL_CH0_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_RSVD1_MASK (0xFC0000U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_CTRL_CH0_SET_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_RSVD1_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_RSVD1_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL */
#define PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_RSVD0_MASK (0x7E000000U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_RSVD0_SHIFT (25U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_CTRL_CH0_SET_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_RSVD0_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_RSVD0_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_SET_ARBIT_EN_MASK (0x80000000U)
#define PXP_DITHER_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_DITHER_STORE_CTRL_CH0_SET_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_SET_ARBIT_EN_MASK)
/*! @} */

/*! @name DITHER_STORE_CTRL_CH0_CLR - Store engine Control Channel 0 Register */
/*! @{ */

#define PXP_DITHER_STORE_CTRL_CH0_CLR_CH_EN_MASK (0x1U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_CH_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_CH_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_CH_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK (0x2U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_BLOCK_16_MASK (0x4U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_BLOCK_16_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK (0x10U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD3_MASK (0x80U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD3_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD3_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK (0x400U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK (0x800U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD2_MASK (0xF000U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD2_SHIFT (12U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD2_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD2_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD1_MASK (0xFC0000U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD1_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD1_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD0_MASK (0x7E000000U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD0_SHIFT (25U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD0_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_RSVD0_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK (0x80000000U)
#define PXP_DITHER_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_DITHER_STORE_CTRL_CH0_CLR_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK)
/*! @} */

/*! @name DITHER_STORE_CTRL_CH0_TOG - Store engine Control Channel 0 Register */
/*! @{ */

#define PXP_DITHER_STORE_CTRL_CH0_TOG_CH_EN_MASK (0x1U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_CH_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_CH_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_CH_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK (0x2U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_BLOCK_16_MASK (0x4U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_BLOCK_16_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK (0x10U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD3_MASK (0x80U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD3_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD3_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK (0x400U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK (0x800U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD2_MASK (0xF000U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD2_SHIFT (12U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD2_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD2_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD1_MASK (0xFC0000U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD1_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD1_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD0_MASK (0x7E000000U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD0_SHIFT (25U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD0_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_RSVD0_MASK)

#define PXP_DITHER_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK (0x80000000U)
#define PXP_DITHER_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_DITHER_STORE_CTRL_CH0_TOG_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK)
/*! @} */

/*! @name DITHER_STORE_CTRL_CH1 - Store engine Control Channel 1 Register */
/*! @{ */

#define PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK     (0x1U)
#define PXP_DITHER_STORE_CTRL_CH1_CH_EN_SHIFT    (0U)
/*! CH_EN - CH_EN
 *  0b0..Store function is disable
 *  0b1..Store function is enable
 */
#define PXP_DITHER_STORE_CTRL_CH1_CH_EN(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CH_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN_MASK  (0x2U)
#define PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN
 *  0b0..Store in scan mode
 *  0b1..Store in block mode
 */
#define PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_BLOCK_16_MASK  (0x4U)
#define PXP_DITHER_STORE_CTRL_CH1_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16
 *  0b0..BLK_SIZE_8x8 : Block size is 8x8
 *  0b1..BLK_SIZE_16x16 : Block size is 16x16
 */
#define PXP_DITHER_STORE_CTRL_CH1_BLOCK_16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_BLOCK_16_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_BLOCK_16_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN
 *  0b0..Handshake with the fetch engine is disabled
 *  0b1..Handshake with the fetch engine is enabled
 */
#define PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN_MASK  (0x10U)
#define PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN
 *  0b0..Array Handshake Disabled
 *  0b1..Array Handshake Enabled
 */
#define PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM
 *  0b00..Using 1x1 Array
 *  0b01..Using 3x3 Array
 *  0b10..Using 5x5 Array
 *  0b11..Using 5x5 Array
 */
#define PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_RSVD3_MASK     (0x80U)
#define PXP_DITHER_STORE_CTRL_CH1_RSVD3_SHIFT    (7U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_STORE_CTRL_CH1_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_RSVD3_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_RSVD3_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN
 *  0b0..store bypass mode disable.
 *  0b1..store bypass mode enable. Data will bypass to store output.
 */
#define PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN
 *  0b0..store memory mode disable.
 *  0b1..store memory mode enable. Data will store to memory
 */
#define PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL_MASK (0x400U)
#define PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL
 *  0b0..select 64 shift out data to pack
 *  0b1..select channel 0 high 32 bit shift out data to pack
 */
#define PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_RSVD1_MASK     (0xF800U)
#define PXP_DITHER_STORE_CTRL_CH1_RSVD1_SHIFT    (11U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_CTRL_CH1_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_RSVD1_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_RSVD1_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES
 *  0b00..NUM_8_BYTES : 8 bytes
 *  0b01..NUM_16_BYTES : 16 bytes
 *  0b10..NUM_32_BYTES : 32 bytes
 *  0b11..NUM_64_BYTES : 64 bytes
 */
#define PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_RSVD0_MASK     (0xFFFC0000U)
#define PXP_DITHER_STORE_CTRL_CH1_RSVD0_SHIFT    (18U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_CTRL_CH1_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_RSVD0_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_CTRL_CH1_SET - Store engine Control Channel 1 Register */
/*! @{ */

#define PXP_DITHER_STORE_CTRL_CH1_SET_CH_EN_MASK (0x1U)
#define PXP_DITHER_STORE_CTRL_CH1_SET_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_DITHER_STORE_CTRL_CH1_SET_CH_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_SET_CH_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_SET_CH_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_SET_BLOCK_EN_MASK (0x2U)
#define PXP_DITHER_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_DITHER_STORE_CTRL_CH1_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_SET_BLOCK_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_SET_BLOCK_16_MASK (0x4U)
#define PXP_DITHER_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_DITHER_STORE_CTRL_CH1_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_SET_BLOCK_16_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_DITHER_STORE_CTRL_CH1_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_SET_ARRAY_EN_MASK (0x10U)
#define PXP_DITHER_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_DITHER_STORE_CTRL_CH1_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_SET_ARRAY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_DITHER_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_DITHER_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_SET_RSVD3_MASK (0x80U)
#define PXP_DITHER_STORE_CTRL_CH1_SET_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_STORE_CTRL_CH1_SET_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_SET_RSVD3_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_SET_RSVD3_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_DITHER_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_DITHER_STORE_CTRL_CH1_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_DITHER_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_DITHER_STORE_CTRL_CH1_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK (0x400U)
#define PXP_DITHER_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_DITHER_STORE_CTRL_CH1_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_SET_RSVD1_MASK (0xF800U)
#define PXP_DITHER_STORE_CTRL_CH1_SET_RSVD1_SHIFT (11U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_CTRL_CH1_SET_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_SET_RSVD1_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_SET_RSVD1_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_DITHER_STORE_CTRL_CH1_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_SET_RSVD0_MASK (0xFFFC0000U)
#define PXP_DITHER_STORE_CTRL_CH1_SET_RSVD0_SHIFT (18U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_CTRL_CH1_SET_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_SET_RSVD0_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_CTRL_CH1_CLR - Store engine Control Channel 1 Register */
/*! @{ */

#define PXP_DITHER_STORE_CTRL_CH1_CLR_CH_EN_MASK (0x1U)
#define PXP_DITHER_STORE_CTRL_CH1_CLR_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_DITHER_STORE_CTRL_CH1_CLR_CH_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CLR_CH_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CLR_CH_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK (0x2U)
#define PXP_DITHER_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_DITHER_STORE_CTRL_CH1_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_CLR_BLOCK_16_MASK (0x4U)
#define PXP_DITHER_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_DITHER_STORE_CTRL_CH1_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CLR_BLOCK_16_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_DITHER_STORE_CTRL_CH1_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK (0x10U)
#define PXP_DITHER_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_DITHER_STORE_CTRL_CH1_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_DITHER_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_DITHER_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD3_MASK (0x80U)
#define PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD3_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD3_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_DITHER_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_DITHER_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_DITHER_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_DITHER_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK (0x400U)
#define PXP_DITHER_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_DITHER_STORE_CTRL_CH1_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD1_MASK (0xF800U)
#define PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD1_SHIFT (11U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD1_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD1_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_DITHER_STORE_CTRL_CH1_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD0_MASK (0xFFFC0000U)
#define PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD0_SHIFT (18U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD0_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_CTRL_CH1_TOG - Store engine Control Channel 1 Register */
/*! @{ */

#define PXP_DITHER_STORE_CTRL_CH1_TOG_CH_EN_MASK (0x1U)
#define PXP_DITHER_STORE_CTRL_CH1_TOG_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_DITHER_STORE_CTRL_CH1_TOG_CH_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_TOG_CH_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_TOG_CH_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK (0x2U)
#define PXP_DITHER_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_DITHER_STORE_CTRL_CH1_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_TOG_BLOCK_16_MASK (0x4U)
#define PXP_DITHER_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_DITHER_STORE_CTRL_CH1_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_TOG_BLOCK_16_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK (0x8U)
#define PXP_DITHER_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_DITHER_STORE_CTRL_CH1_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK (0x10U)
#define PXP_DITHER_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_DITHER_STORE_CTRL_CH1_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_DITHER_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_DITHER_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD3_MASK (0x80U)
#define PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD3_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD3_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_DITHER_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_DITHER_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_DITHER_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_DITHER_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK (0x400U)
#define PXP_DITHER_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_DITHER_STORE_CTRL_CH1_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD1_MASK (0xF800U)
#define PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD1_SHIFT (11U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD1_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD1_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_DITHER_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_DITHER_STORE_CTRL_CH1_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK)

#define PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD0_MASK (0xFFFC0000U)
#define PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD0_SHIFT (18U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD0_SHIFT)) & PXP_DITHER_STORE_CTRL_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_STATUS_CH0 - Store engine status Channel 0 Register */
/*! @{ */

#define PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X_MASK (0xFFFFU)
#define PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT (0U)
/*! STORE_BLOCK_X - STORE_BLOCK_X */
#define PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT)) & PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X_MASK)

#define PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK (0xFFFF0000U)
#define PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT (16U)
/*! STORE_BLOCK_Y - STORE_BLOCK_Y */
#define PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT)) & PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK)
/*! @} */

/*! @name DITHER_STORE_STATUS_CH1 - Store engine status Channel 1 Register */
/*! @{ */

#define PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X_MASK (0xFFFFU)
#define PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT (0U)
/*! STORE_BLOCK_X - STORE_BLOCK_X */
#define PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT)) & PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X_MASK)

#define PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK (0xFFFF0000U)
#define PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT (16U)
/*! STORE_BLOCK_Y - STORE_BLOCK_Y */
#define PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT)) & PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK)
/*! @} */

/*! @name DITHER_STORE_SIZE_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK (0xFFFFU)
#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT (0U)
/*! OUT_WIDTH - OUT_WIDTH */
#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT)) & PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK)

#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK (0xFFFF0000U)
#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT (16U)
/*! OUT_HEIGHT - OUT_HEIGHT */
#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT)) & PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK)
/*! @} */

/*! @name DITHER_STORE_SIZE_CH1 -  */
/*! @{ */

#define PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH_MASK (0xFFFFU)
#define PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH_SHIFT (0U)
/*! OUT_WIDTH - OUT_WIDTH */
#define PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH_SHIFT)) & PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH_MASK)

#define PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT_MASK (0xFFFF0000U)
#define PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT (16U)
/*! OUT_HEIGHT - OUT_HEIGHT */
#define PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT)) & PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT_MASK)
/*! @} */

/*! @name DITHER_STORE_PITCH -  */
/*! @{ */

#define PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_MASK (0xFFFFU)
#define PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_SHIFT (0U)
/*! CH0_OUT_PITCH - CH0_OUT_PITCH */
#define PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_SHIFT)) & PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_MASK)

#define PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH_MASK (0xFFFF0000U)
#define PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH_SHIFT (16U)
/*! CH1_OUT_PITCH - CH1_OUT_PITCH */
#define PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH_SHIFT)) & PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH_MASK)
/*! @} */

/*! @name DITHER_STORE_SHIFT_CTRL_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2_MASK (0x3U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP
 *  0b00..8 bits
 *  0b01..16 bits
 *  0b10..32 bits
 *  0b11..32 bits
 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1_MASK (0x40U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK (0x80U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS
 *  0b0..data will do shift processing.
 *  0b1..data will bypass shift module.
 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0_MASK (0xFFFFFF00U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_SHIFT_CTRL_CH0_SET -  */
/*! @{ */

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD2_MASK (0x3U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD2_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD2_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD1_MASK (0x40U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD1_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD1_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK (0x80U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD0_MASK (0xFFFFFF00U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD0_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_SHIFT_CTRL_CH0_CLR -  */
/*! @{ */

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_MASK (0x3U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_MASK (0x40U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK (0x80U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_MASK (0xFFFFFF00U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_SHIFT_CTRL_CH0_TOG -  */
/*! @{ */

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_MASK (0x3U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_MASK (0x40U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK (0x80U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_MASK (0xFFFFFF00U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_SHIFT_CTRL_CH1 -  */
/*! @{ */

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2_MASK (0x3U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP
 *  0b00..8 bits
 *  0b01..16 bits
 *  0b10..32 bits
 *  0b11..32 bits
 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_SHIFT_CTRL_CH1_SET -  */
/*! @{ */

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_RSVD2_MASK (0x3U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_RSVD2_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_RSVD2_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_RSVD0_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_SHIFT_CTRL_CH1_CLR -  */
/*! @{ */

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_MASK (0x3U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_SHIFT_CTRL_CH1_TOG -  */
/*! @{ */

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_MASK (0x3U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK)

#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_SHIFT)) & PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_ADDR_0_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT (0U)
/*! OUT_BASE_ADDR0 - OUT_BASE_ADDR0 */
#define PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT)) & PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK)
/*! @} */

/*! @name DITHER_STORE_ADDR_1_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT (0U)
/*! OUT_BASE_ADDR1 - OUT_BASE_ADDR1 */
#define PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT)) & PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK)
/*! @} */

/*! @name DITHER_STORE_FILL_DATA_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT (0U)
/*! FILL_DATA_CH0 - FILL_DATA_CH0 */
#define PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT)) & PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_ADDR_0_CH1 -  */
/*! @{ */

#define PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT (0U)
/*! OUT_BASE_ADDR0 - OUT_BASE_ADDR0 */
#define PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT)) & PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK)
/*! @} */

/*! @name DITHER_STORE_ADDR_1_CH1 -  */
/*! @{ */

#define PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT (0U)
/*! OUT_BASE_ADDR1 - OUT_BASE_ADDR1 */
#define PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT)) & PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK0_H_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT (0U)
/*! D_MASK0_H_CH0 - D_MASK0_H_CH0 */
#define PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK0_L_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT (0U)
/*! D_MASK0_L_CH0 - D_MASK0_L_CH0 */
#define PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK1_H_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT (0U)
/*! D_MASK1_H_CH0 - D_MASK1_H_CH0 */
#define PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK1_L_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT (0U)
/*! D_MASK1_L_CH0 - D_MASK1_L_CH0 */
#define PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK2_H_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT (0U)
/*! D_MASK2_H_CH0 - D_MASK2_H_CH0 */
#define PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK2_L_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT (0U)
/*! D_MASK2_L_CH0 - D_MASK2_L_CH0 */
#define PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK3_H_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT (0U)
/*! D_MASK3_H_CH0 - D_MASK3_H_CH0 */
#define PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK3_L_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT (0U)
/*! D_MASK3_L_CH0 - D_MASK3_L_CH0 */
#define PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK4_H_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT (0U)
/*! D_MASK4_H_CH0 - D_MASK4_H_CH0 */
#define PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK4_L_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT (0U)
/*! D_MASK4_L_CH0 - D_MASK4_L_CH0 */
#define PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK5_H_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT (0U)
/*! D_MASK5_H_CH0 - D_MASK5_H_CH0 */
#define PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK5_L_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT (0U)
/*! D_MASK5_L_CH0 - D_MASK5_L_CH0 */
#define PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK6_H_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT (0U)
/*! D_MASK6_H_CH0 - D_MASK6_H_CH0 */
#define PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK6_L_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT (0U)
/*! D_MASK6_L_CH0 - D_MASK6_L_CH0 */
#define PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK7_H_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT (0U)
/*! D_MASK7_H_CH0 - D_MASK7_H_CH0 */
#define PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_MASK7_L_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT (0U)
/*! D_MASK7_L_CH0 - D_MASK7_L_CH0 */
#define PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT)) & PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK)
/*! @} */

/*! @name DITHER_STORE_D_SHIFT_L_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK (0x3FU)
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT (0U)
/*! D_SHIFT_WIDTH0 - D_SHIFT_WIDTH0 */
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK)

#define PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3_MASK (0x40U)
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3_SHIFT (6U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3_MASK)

#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK (0x80U)
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT (7U)
/*! D_SHIFT_FLAG0 - D_SHIFT_FLAG0 */
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK)

#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK (0x3F00U)
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT (8U)
/*! D_SHIFT_WIDTH1 - D_SHIFT_WIDTH1 */
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK)

#define PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2_MASK (0x4000U)
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2_MASK)

#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK (0x8000U)
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT (15U)
/*! D_SHIFT_FLAG1 - D_SHIFT_FLAG1 */
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK)

#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK (0x3F0000U)
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT (16U)
/*! D_SHIFT_WIDTH2 - D_SHIFT_WIDTH2 */
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK)

#define PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1_MASK (0x400000U)
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1_SHIFT (22U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1_MASK)

#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK (0x800000U)
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT (23U)
/*! D_SHIFT_FLAG2 - D_SHIFT_FLAG2 */
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK)

#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK (0x3F000000U)
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT (24U)
/*! D_SHIFT_WIDTH3 - D_SHIFT_WIDTH3 */
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK)

#define PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0_MASK (0x40000000U)
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0_SHIFT (30U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0_MASK)

#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK (0x80000000U)
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT (31U)
/*! D_SHIFT_FLAG3 - D_SHIFT_FLAG3 */
#define PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK)
/*! @} */

/*! @name DITHER_STORE_D_SHIFT_H_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK (0x3FU)
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT (0U)
/*! D_SHIFT_WIDTH4 - D_SHIFT_WIDTH4 */
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK)

#define PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3_MASK (0x40U)
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3_SHIFT (6U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3_MASK)

#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK (0x80U)
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT (7U)
/*! D_SHIFT_FLAG4 - D_SHIFT_FLAG4 */
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK)

#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK (0x3F00U)
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT (8U)
/*! D_SHIFT_WIDTH5 - D_SHIFT_WIDTH5 */
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK)

#define PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2_MASK (0x4000U)
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2_MASK)

#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK (0x8000U)
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT (15U)
/*! D_SHIFT_FLAG5 - D_SHIFT_FLAG5 */
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK)

#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK (0x3F0000U)
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT (16U)
/*! D_SHIFT_WIDTH6 - D_SHIFT_WIDTH6 */
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK)

#define PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1_MASK (0x400000U)
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1_SHIFT (22U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1_MASK)

#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK (0x800000U)
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT (23U)
/*! D_SHIFT_FLAG6 - D_SHIFT_FLAG6 */
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK)

#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK (0x3F000000U)
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT (24U)
/*! D_SHIFT_WIDTH7 - D_SHIFT_WIDTH7 */
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK)

#define PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0_MASK (0x40000000U)
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0_SHIFT (30U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0_MASK)

#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK (0x80000000U)
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT (31U)
/*! D_SHIFT_FLAG7 - D_SHIFT_FLAG7 */
#define PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT)) & PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK)
/*! @} */

/*! @name DITHER_STORE_F_SHIFT_L_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK (0x3FU)
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT (0U)
/*! F_SHIFT_WIDTH0 - F_SHIFT_WIDTH0 */
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK)

#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK (0x40U)
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT (6U)
/*! F_SHIFT_FLAG0 - F_SHIFT_FLAG0 */
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK)

#define PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3_MASK (0x80U)
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3_MASK)

#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK (0x3F00U)
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT (8U)
/*! F_SHIFT_WIDTH1 - F_SHIFT_WIDTH1 */
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK)

#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK (0x4000U)
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT (14U)
/*! F_SHIFT_FLAG1 - F_SHIFT_FLAG1 */
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK)

#define PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2_MASK (0x8000U)
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2_SHIFT (15U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2_MASK)

#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK (0x3F0000U)
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT (16U)
/*! F_SHIFT_WIDTH2 - F_SHIFT_WIDTH2 */
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK)

#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK (0x400000U)
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT (22U)
/*! F_SHIFT_FLAG2 - F_SHIFT_FLAG2 */
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK)

#define PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1_MASK (0x800000U)
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1_SHIFT (23U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1_MASK)

#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK (0x3F000000U)
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT (24U)
/*! F_SHIFT_WIDTH3 - F_SHIFT_WIDTH3 */
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK)

#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK (0x40000000U)
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT (30U)
/*! F_SHIFT_FLAG3 - F_SHIFT_FLAG3 */
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK)

#define PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0_MASK (0x80000000U)
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0_SHIFT (31U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_F_SHIFT_H_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK (0x3FU)
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT (0U)
/*! F_SHIFT_WIDTH4 - F_SHIFT_WIDTH4 */
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK)

#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK (0x40U)
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT (6U)
/*! F_SHIFT_FLAG4 - F_SHIFT_FLAG4 */
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK)

#define PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3_MASK (0x80U)
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3_MASK)

#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK (0x3F00U)
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT (8U)
/*! F_SHIFT_WIDTH5 - F_SHIFT_WIDTH5 */
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK)

#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK (0x4000U)
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT (14U)
/*! F_SHIFT_FLAG5 - F_SHIFT_FLAG5 */
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK)

#define PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2_MASK (0x8000U)
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2_SHIFT (15U)
/*! RSVD2 - RSVD2 */
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2_MASK)

#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK (0x3F0000U)
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT (16U)
/*! F_SHIFT_WIDTH6 - F_SHIFT_WIDTH6 */
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK)

#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK (0x400000U)
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT (22U)
/*! F_SHIFT_FLAG6 - F_SHIFT_FLAG6 */
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK)

#define PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1_MASK (0x800000U)
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1_SHIFT (23U)
/*! RSVD1 - RSVD1 */
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1_MASK)

#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK (0x3F000000U)
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT (24U)
/*! F_SHIFT_WIDTH7 - F_SHIFT_WIDTH7 */
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK)

#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK (0x40000000U)
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT (30U)
/*! F_SHIFT_FLAG7 - F_SHIFT_FLAG7 */
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK)

#define PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0_MASK (0x80000000U)
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0_SHIFT (31U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0_SHIFT)) & PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0_MASK)
/*! @} */

/*! @name DITHER_STORE_F_MASK_L_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0_MASK (0xFFU)
#define PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0_SHIFT (0U)
/*! F_MASK0 - F_MASK0 */
#define PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0_SHIFT)) & PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0_MASK)

#define PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1_MASK (0xFF00U)
#define PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1_SHIFT (8U)
/*! F_MASK1 - F_MASK1 */
#define PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1_SHIFT)) & PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1_MASK)

#define PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2_MASK (0xFF0000U)
#define PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2_SHIFT (16U)
/*! F_MASK2 - F_MASK2 */
#define PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2_SHIFT)) & PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2_MASK)

#define PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3_MASK (0xFF000000U)
#define PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3_SHIFT (24U)
/*! F_MASK3 - F_MASK3 */
#define PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3_SHIFT)) & PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3_MASK)
/*! @} */

/*! @name DITHER_STORE_F_MASK_H_CH0 -  */
/*! @{ */

#define PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4_MASK (0xFFU)
#define PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4_SHIFT (0U)
/*! F_MASK4 - F_MASK4 */
#define PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4_SHIFT)) & PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4_MASK)

#define PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5_MASK (0xFF00U)
#define PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5_SHIFT (8U)
/*! F_MASK5 - F_MASK5 */
#define PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5_SHIFT)) & PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5_MASK)

#define PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6_MASK (0xFF0000U)
#define PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6_SHIFT (16U)
/*! F_MASK6 - F_MASK6 */
#define PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6_SHIFT)) & PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6_MASK)

#define PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7_MASK (0xFF000000U)
#define PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7_SHIFT (24U)
/*! F_MASK7 - F_MASK7 */
#define PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7_SHIFT)) & PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7_MASK)
/*! @} */

/*! @name WFA_FETCH_CTRL - Fetch engine Control for WFE A Register */
/*! @{ */

#define PXP_WFA_FETCH_CTRL_BF1_EN_MASK           (0x1U)
#define PXP_WFA_FETCH_CTRL_BF1_EN_SHIFT          (0U)
/*! BF1_EN - BF1_EN
 *  0b0..Disabled. The buffer1 fetch will not work
 *  0b1..Enabled. The buffer1 fetch will start to work
 */
#define PXP_WFA_FETCH_CTRL_BF1_EN(x)             (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF1_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_BF1_EN_MASK)

#define PXP_WFA_FETCH_CTRL_BF1_SRAM_IF_MASK      (0x2U)
#define PXP_WFA_FETCH_CTRL_BF1_SRAM_IF_SHIFT     (1U)
/*! BF1_SRAM_IF - BF1_SRAM_IF
 *  0b0..external axi bus fetch.
 *  0b1..internal sram fetch
 */
#define PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF1_SRAM_IF_SHIFT)) & PXP_WFA_FETCH_CTRL_BF1_SRAM_IF_MASK)

#define PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_MASK     (0x4U)
#define PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_SHIFT    (2U)
/*! BF1_HSK_MODE - BF1_HSK_MODE
 *  0b0..Normal Mode
 *  0b1..Handshake Mode
 */
#define PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE_MASK  (0x8U)
#define PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE_SHIFT (3U)
/*! BF1_BYPASS_MODE - BF1_BYPASS_MODE
 *  0b0..Normal Mode
 *  0b1..Bypass Mode
 */
#define PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_BF1_BURST_LEN_MASK    (0x10U)
#define PXP_WFA_FETCH_CTRL_BF1_BURST_LEN_SHIFT   (4U)
/*! BF1_BURST_LEN - BF1_BURST_LEN
 *  0b0..Burst length is 4
 *  0b1..Burst length is 8
 */
#define PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF1_BURST_LEN_SHIFT)) & PXP_WFA_FETCH_CTRL_BF1_BURST_LEN_MASK)

#define PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE_MASK  (0x20U)
#define PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE_SHIFT (5U)
/*! BF1_BORDER_MODE - BF1_BORDER_MODE
 *  0b0..Normal Mode
 *  0b1..SW REG Mode
 */
#define PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_RSVD2_MASK            (0xC0U)
#define PXP_WFA_FETCH_CTRL_RSVD2_SHIFT           (6U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_FETCH_CTRL_RSVD2(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_RSVD2_SHIFT)) & PXP_WFA_FETCH_CTRL_RSVD2_MASK)

#define PXP_WFA_FETCH_CTRL_BF2_EN_MASK           (0x100U)
#define PXP_WFA_FETCH_CTRL_BF2_EN_SHIFT          (8U)
/*! BF2_EN - BF2_EN
 *  0b0..Disabled. The buffer2 fetch will not work
 *  0b1..Enabled. The buffer2 fetch will start to work
 */
#define PXP_WFA_FETCH_CTRL_BF2_EN(x)             (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF2_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_BF2_EN_MASK)

#define PXP_WFA_FETCH_CTRL_BF2_SRAM_IF_MASK      (0x200U)
#define PXP_WFA_FETCH_CTRL_BF2_SRAM_IF_SHIFT     (9U)
/*! BF2_SRAM_IF - BF2_SRAM_IF
 *  0b0..external axi bus fetch.
 *  0b1..internal sram fetch
 */
#define PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF2_SRAM_IF_SHIFT)) & PXP_WFA_FETCH_CTRL_BF2_SRAM_IF_MASK)

#define PXP_WFA_FETCH_CTRL_BF2_HSK_MODE_MASK     (0x400U)
#define PXP_WFA_FETCH_CTRL_BF2_HSK_MODE_SHIFT    (10U)
/*! BF2_HSK_MODE - BF2_HSK_MODE
 *  0b0..Normal Mode
 *  0b1..Handshake Mode
 */
#define PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF2_HSK_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_BF2_HSK_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE_MASK  (0x800U)
#define PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE_SHIFT (11U)
/*! BF2_BYPASS_MODE - BF2_BYPASS_MODE
 *  0b0..Normal Mode
 *  0b1..Bypass Mode
 */
#define PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_BF2_BURST_LEN_MASK    (0x1000U)
#define PXP_WFA_FETCH_CTRL_BF2_BURST_LEN_SHIFT   (12U)
/*! BF2_BURST_LEN - BF2_BURST_LEN
 *  0b0..Burst length is 4
 *  0b1..Burst length is 8
 */
#define PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF2_BURST_LEN_SHIFT)) & PXP_WFA_FETCH_CTRL_BF2_BURST_LEN_MASK)

#define PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE_MASK  (0x2000U)
#define PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE_SHIFT (13U)
/*! BF2_BORDER_MODE - BF2_BORDER_MODE
 *  0b0..Normal Mode
 *  0b1..SW REG Mode
 */
#define PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_RSVD1_MASK            (0xC000U)
#define PXP_WFA_FETCH_CTRL_RSVD1_SHIFT           (14U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_FETCH_CTRL_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_RSVD1_SHIFT)) & PXP_WFA_FETCH_CTRL_RSVD1_MASK)

#define PXP_WFA_FETCH_CTRL_BF1_BYTES_PP_MASK     (0x30000U)
#define PXP_WFA_FETCH_CTRL_BF1_BYTES_PP_SHIFT    (16U)
/*! BF1_BYTES_PP - BF1_BYTES_PP */
#define PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF1_BYTES_PP_SHIFT)) & PXP_WFA_FETCH_CTRL_BF1_BYTES_PP_MASK)

#define PXP_WFA_FETCH_CTRL_BF1_LINE_MODE_MASK    (0xC0000U)
#define PXP_WFA_FETCH_CTRL_BF1_LINE_MODE_SHIFT   (18U)
/*! BF1_LINE_MODE - BF1_LINE_MODE
 *  0b00..One line fetched
 *  0b01..Three lines fetched
 *  0b10..Five lines fetched
 *  0b11..Reserved
 */
#define PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF1_LINE_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_BF1_LINE_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_BF2_BYTES_PP_MASK     (0x300000U)
#define PXP_WFA_FETCH_CTRL_BF2_BYTES_PP_SHIFT    (20U)
/*! BF2_BYTES_PP - BF2_BYTES_PP */
#define PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF2_BYTES_PP_SHIFT)) & PXP_WFA_FETCH_CTRL_BF2_BYTES_PP_MASK)

#define PXP_WFA_FETCH_CTRL_BF2_LINE_MODE_MASK    (0xC00000U)
#define PXP_WFA_FETCH_CTRL_BF2_LINE_MODE_SHIFT   (22U)
/*! BF2_LINE_MODE - BF2_LINE_MODE
 *  0b00..One line fetched
 *  0b01..Three lines fetched
 *  0b10..Five lines fetched
 *  0b11..Reserved
 */
#define PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BF2_LINE_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_BF2_LINE_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_RSVD0_MASK            (0xF000000U)
#define PXP_WFA_FETCH_CTRL_RSVD0_SHIFT           (24U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_FETCH_CTRL_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_RSVD0_SHIFT)) & PXP_WFA_FETCH_CTRL_RSVD0_MASK)

#define PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_MASK    (0x10000000U)
#define PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_SHIFT   (28U)
/*! BUF1_DONE_IRQ - BUF1_DONE_IRQ */
#define PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_SHIFT)) & PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_MASK)

#define PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_MASK    (0x20000000U)
#define PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_SHIFT   (29U)
/*! BUF2_DONE_IRQ - BUF2_DONE_IRQ */
#define PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_SHIFT)) & PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_MASK)

#define PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN_MASK (0x40000000U)
#define PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN_SHIFT (30U)
/*! BUF1_DONE_IRQ_EN - BUF1_DONE_IRQ_EN */
#define PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN_MASK)

#define PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN_MASK (0x80000000U)
#define PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN_SHIFT (31U)
/*! BUF2_DONE_IRQ_EN - BUF2_DONE_IRQ_EN */
#define PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN_MASK)
/*! @} */

/*! @name WFA_FETCH_CTRL_SET - Fetch engine Control for WFE A Register */
/*! @{ */

#define PXP_WFA_FETCH_CTRL_SET_BF1_EN_MASK       (0x1U)
#define PXP_WFA_FETCH_CTRL_SET_BF1_EN_SHIFT      (0U)
/*! BF1_EN - BF1_EN */
#define PXP_WFA_FETCH_CTRL_SET_BF1_EN(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF1_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF1_EN_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF1_SRAM_IF_MASK  (0x2U)
#define PXP_WFA_FETCH_CTRL_SET_BF1_SRAM_IF_SHIFT (1U)
/*! BF1_SRAM_IF - BF1_SRAM_IF */
#define PXP_WFA_FETCH_CTRL_SET_BF1_SRAM_IF(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF1_SRAM_IF_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF1_SRAM_IF_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF1_HSK_MODE_MASK (0x4U)
#define PXP_WFA_FETCH_CTRL_SET_BF1_HSK_MODE_SHIFT (2U)
/*! BF1_HSK_MODE - BF1_HSK_MODE */
#define PXP_WFA_FETCH_CTRL_SET_BF1_HSK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF1_HSK_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF1_HSK_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF1_BYPASS_MODE_MASK (0x8U)
#define PXP_WFA_FETCH_CTRL_SET_BF1_BYPASS_MODE_SHIFT (3U)
/*! BF1_BYPASS_MODE - BF1_BYPASS_MODE */
#define PXP_WFA_FETCH_CTRL_SET_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF1_BYPASS_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF1_BYPASS_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF1_BURST_LEN_MASK (0x10U)
#define PXP_WFA_FETCH_CTRL_SET_BF1_BURST_LEN_SHIFT (4U)
/*! BF1_BURST_LEN - BF1_BURST_LEN */
#define PXP_WFA_FETCH_CTRL_SET_BF1_BURST_LEN(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF1_BURST_LEN_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF1_BURST_LEN_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF1_BORDER_MODE_MASK (0x20U)
#define PXP_WFA_FETCH_CTRL_SET_BF1_BORDER_MODE_SHIFT (5U)
/*! BF1_BORDER_MODE - BF1_BORDER_MODE */
#define PXP_WFA_FETCH_CTRL_SET_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF1_BORDER_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF1_BORDER_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_SET_RSVD2_MASK        (0xC0U)
#define PXP_WFA_FETCH_CTRL_SET_RSVD2_SHIFT       (6U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_FETCH_CTRL_SET_RSVD2(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_RSVD2_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_RSVD2_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF2_EN_MASK       (0x100U)
#define PXP_WFA_FETCH_CTRL_SET_BF2_EN_SHIFT      (8U)
/*! BF2_EN - BF2_EN */
#define PXP_WFA_FETCH_CTRL_SET_BF2_EN(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF2_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF2_EN_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF2_SRAM_IF_MASK  (0x200U)
#define PXP_WFA_FETCH_CTRL_SET_BF2_SRAM_IF_SHIFT (9U)
/*! BF2_SRAM_IF - BF2_SRAM_IF */
#define PXP_WFA_FETCH_CTRL_SET_BF2_SRAM_IF(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF2_SRAM_IF_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF2_SRAM_IF_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF2_HSK_MODE_MASK (0x400U)
#define PXP_WFA_FETCH_CTRL_SET_BF2_HSK_MODE_SHIFT (10U)
/*! BF2_HSK_MODE - BF2_HSK_MODE */
#define PXP_WFA_FETCH_CTRL_SET_BF2_HSK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF2_HSK_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF2_HSK_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF2_BYPASS_MODE_MASK (0x800U)
#define PXP_WFA_FETCH_CTRL_SET_BF2_BYPASS_MODE_SHIFT (11U)
/*! BF2_BYPASS_MODE - BF2_BYPASS_MODE */
#define PXP_WFA_FETCH_CTRL_SET_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF2_BYPASS_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF2_BYPASS_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF2_BURST_LEN_MASK (0x1000U)
#define PXP_WFA_FETCH_CTRL_SET_BF2_BURST_LEN_SHIFT (12U)
/*! BF2_BURST_LEN - BF2_BURST_LEN */
#define PXP_WFA_FETCH_CTRL_SET_BF2_BURST_LEN(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF2_BURST_LEN_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF2_BURST_LEN_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF2_BORDER_MODE_MASK (0x2000U)
#define PXP_WFA_FETCH_CTRL_SET_BF2_BORDER_MODE_SHIFT (13U)
/*! BF2_BORDER_MODE - BF2_BORDER_MODE */
#define PXP_WFA_FETCH_CTRL_SET_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF2_BORDER_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF2_BORDER_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_SET_RSVD1_MASK        (0xC000U)
#define PXP_WFA_FETCH_CTRL_SET_RSVD1_SHIFT       (14U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_FETCH_CTRL_SET_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_RSVD1_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_RSVD1_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF1_BYTES_PP_MASK (0x30000U)
#define PXP_WFA_FETCH_CTRL_SET_BF1_BYTES_PP_SHIFT (16U)
/*! BF1_BYTES_PP - BF1_BYTES_PP */
#define PXP_WFA_FETCH_CTRL_SET_BF1_BYTES_PP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF1_BYTES_PP_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF1_BYTES_PP_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF1_LINE_MODE_MASK (0xC0000U)
#define PXP_WFA_FETCH_CTRL_SET_BF1_LINE_MODE_SHIFT (18U)
/*! BF1_LINE_MODE - BF1_LINE_MODE */
#define PXP_WFA_FETCH_CTRL_SET_BF1_LINE_MODE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF1_LINE_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF1_LINE_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF2_BYTES_PP_MASK (0x300000U)
#define PXP_WFA_FETCH_CTRL_SET_BF2_BYTES_PP_SHIFT (20U)
/*! BF2_BYTES_PP - BF2_BYTES_PP */
#define PXP_WFA_FETCH_CTRL_SET_BF2_BYTES_PP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF2_BYTES_PP_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF2_BYTES_PP_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BF2_LINE_MODE_MASK (0xC00000U)
#define PXP_WFA_FETCH_CTRL_SET_BF2_LINE_MODE_SHIFT (22U)
/*! BF2_LINE_MODE - BF2_LINE_MODE */
#define PXP_WFA_FETCH_CTRL_SET_BF2_LINE_MODE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BF2_LINE_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BF2_LINE_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_SET_RSVD0_MASK        (0xF000000U)
#define PXP_WFA_FETCH_CTRL_SET_RSVD0_SHIFT       (24U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_FETCH_CTRL_SET_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_RSVD0_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_RSVD0_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BUF1_DONE_IRQ_MASK (0x10000000U)
#define PXP_WFA_FETCH_CTRL_SET_BUF1_DONE_IRQ_SHIFT (28U)
/*! BUF1_DONE_IRQ - BUF1_DONE_IRQ */
#define PXP_WFA_FETCH_CTRL_SET_BUF1_DONE_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BUF1_DONE_IRQ_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BUF1_DONE_IRQ_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BUF2_DONE_IRQ_MASK (0x20000000U)
#define PXP_WFA_FETCH_CTRL_SET_BUF2_DONE_IRQ_SHIFT (29U)
/*! BUF2_DONE_IRQ - BUF2_DONE_IRQ */
#define PXP_WFA_FETCH_CTRL_SET_BUF2_DONE_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BUF2_DONE_IRQ_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BUF2_DONE_IRQ_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_MASK (0x40000000U)
#define PXP_WFA_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_SHIFT (30U)
/*! BUF1_DONE_IRQ_EN - BUF1_DONE_IRQ_EN */
#define PXP_WFA_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_MASK)

#define PXP_WFA_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_MASK (0x80000000U)
#define PXP_WFA_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_SHIFT (31U)
/*! BUF2_DONE_IRQ_EN - BUF2_DONE_IRQ_EN */
#define PXP_WFA_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_MASK)
/*! @} */

/*! @name WFA_FETCH_CTRL_CLR - Fetch engine Control for WFE A Register */
/*! @{ */

#define PXP_WFA_FETCH_CTRL_CLR_BF1_EN_MASK       (0x1U)
#define PXP_WFA_FETCH_CTRL_CLR_BF1_EN_SHIFT      (0U)
/*! BF1_EN - BF1_EN */
#define PXP_WFA_FETCH_CTRL_CLR_BF1_EN(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF1_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF1_EN_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF1_SRAM_IF_MASK  (0x2U)
#define PXP_WFA_FETCH_CTRL_CLR_BF1_SRAM_IF_SHIFT (1U)
/*! BF1_SRAM_IF - BF1_SRAM_IF */
#define PXP_WFA_FETCH_CTRL_CLR_BF1_SRAM_IF(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF1_SRAM_IF_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF1_SRAM_IF_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF1_HSK_MODE_MASK (0x4U)
#define PXP_WFA_FETCH_CTRL_CLR_BF1_HSK_MODE_SHIFT (2U)
/*! BF1_HSK_MODE - BF1_HSK_MODE */
#define PXP_WFA_FETCH_CTRL_CLR_BF1_HSK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF1_HSK_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF1_HSK_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF1_BYPASS_MODE_MASK (0x8U)
#define PXP_WFA_FETCH_CTRL_CLR_BF1_BYPASS_MODE_SHIFT (3U)
/*! BF1_BYPASS_MODE - BF1_BYPASS_MODE */
#define PXP_WFA_FETCH_CTRL_CLR_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF1_BYPASS_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF1_BYPASS_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF1_BURST_LEN_MASK (0x10U)
#define PXP_WFA_FETCH_CTRL_CLR_BF1_BURST_LEN_SHIFT (4U)
/*! BF1_BURST_LEN - BF1_BURST_LEN */
#define PXP_WFA_FETCH_CTRL_CLR_BF1_BURST_LEN(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF1_BURST_LEN_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF1_BURST_LEN_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF1_BORDER_MODE_MASK (0x20U)
#define PXP_WFA_FETCH_CTRL_CLR_BF1_BORDER_MODE_SHIFT (5U)
/*! BF1_BORDER_MODE - BF1_BORDER_MODE */
#define PXP_WFA_FETCH_CTRL_CLR_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF1_BORDER_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF1_BORDER_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_RSVD2_MASK        (0xC0U)
#define PXP_WFA_FETCH_CTRL_CLR_RSVD2_SHIFT       (6U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_FETCH_CTRL_CLR_RSVD2(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_RSVD2_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_RSVD2_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF2_EN_MASK       (0x100U)
#define PXP_WFA_FETCH_CTRL_CLR_BF2_EN_SHIFT      (8U)
/*! BF2_EN - BF2_EN */
#define PXP_WFA_FETCH_CTRL_CLR_BF2_EN(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF2_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF2_EN_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF2_SRAM_IF_MASK  (0x200U)
#define PXP_WFA_FETCH_CTRL_CLR_BF2_SRAM_IF_SHIFT (9U)
/*! BF2_SRAM_IF - BF2_SRAM_IF */
#define PXP_WFA_FETCH_CTRL_CLR_BF2_SRAM_IF(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF2_SRAM_IF_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF2_SRAM_IF_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF2_HSK_MODE_MASK (0x400U)
#define PXP_WFA_FETCH_CTRL_CLR_BF2_HSK_MODE_SHIFT (10U)
/*! BF2_HSK_MODE - BF2_HSK_MODE */
#define PXP_WFA_FETCH_CTRL_CLR_BF2_HSK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF2_HSK_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF2_HSK_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF2_BYPASS_MODE_MASK (0x800U)
#define PXP_WFA_FETCH_CTRL_CLR_BF2_BYPASS_MODE_SHIFT (11U)
/*! BF2_BYPASS_MODE - BF2_BYPASS_MODE */
#define PXP_WFA_FETCH_CTRL_CLR_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF2_BYPASS_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF2_BYPASS_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF2_BURST_LEN_MASK (0x1000U)
#define PXP_WFA_FETCH_CTRL_CLR_BF2_BURST_LEN_SHIFT (12U)
/*! BF2_BURST_LEN - BF2_BURST_LEN */
#define PXP_WFA_FETCH_CTRL_CLR_BF2_BURST_LEN(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF2_BURST_LEN_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF2_BURST_LEN_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF2_BORDER_MODE_MASK (0x2000U)
#define PXP_WFA_FETCH_CTRL_CLR_BF2_BORDER_MODE_SHIFT (13U)
/*! BF2_BORDER_MODE - BF2_BORDER_MODE */
#define PXP_WFA_FETCH_CTRL_CLR_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF2_BORDER_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF2_BORDER_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_RSVD1_MASK        (0xC000U)
#define PXP_WFA_FETCH_CTRL_CLR_RSVD1_SHIFT       (14U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_FETCH_CTRL_CLR_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_RSVD1_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_RSVD1_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF1_BYTES_PP_MASK (0x30000U)
#define PXP_WFA_FETCH_CTRL_CLR_BF1_BYTES_PP_SHIFT (16U)
/*! BF1_BYTES_PP - BF1_BYTES_PP */
#define PXP_WFA_FETCH_CTRL_CLR_BF1_BYTES_PP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF1_BYTES_PP_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF1_BYTES_PP_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF1_LINE_MODE_MASK (0xC0000U)
#define PXP_WFA_FETCH_CTRL_CLR_BF1_LINE_MODE_SHIFT (18U)
/*! BF1_LINE_MODE - BF1_LINE_MODE */
#define PXP_WFA_FETCH_CTRL_CLR_BF1_LINE_MODE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF1_LINE_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF1_LINE_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF2_BYTES_PP_MASK (0x300000U)
#define PXP_WFA_FETCH_CTRL_CLR_BF2_BYTES_PP_SHIFT (20U)
/*! BF2_BYTES_PP - BF2_BYTES_PP */
#define PXP_WFA_FETCH_CTRL_CLR_BF2_BYTES_PP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF2_BYTES_PP_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF2_BYTES_PP_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BF2_LINE_MODE_MASK (0xC00000U)
#define PXP_WFA_FETCH_CTRL_CLR_BF2_LINE_MODE_SHIFT (22U)
/*! BF2_LINE_MODE - BF2_LINE_MODE */
#define PXP_WFA_FETCH_CTRL_CLR_BF2_LINE_MODE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BF2_LINE_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BF2_LINE_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_RSVD0_MASK        (0xF000000U)
#define PXP_WFA_FETCH_CTRL_CLR_RSVD0_SHIFT       (24U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_FETCH_CTRL_CLR_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_RSVD0_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_RSVD0_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BUF1_DONE_IRQ_MASK (0x10000000U)
#define PXP_WFA_FETCH_CTRL_CLR_BUF1_DONE_IRQ_SHIFT (28U)
/*! BUF1_DONE_IRQ - BUF1_DONE_IRQ */
#define PXP_WFA_FETCH_CTRL_CLR_BUF1_DONE_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BUF1_DONE_IRQ_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BUF1_DONE_IRQ_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BUF2_DONE_IRQ_MASK (0x20000000U)
#define PXP_WFA_FETCH_CTRL_CLR_BUF2_DONE_IRQ_SHIFT (29U)
/*! BUF2_DONE_IRQ - BUF2_DONE_IRQ */
#define PXP_WFA_FETCH_CTRL_CLR_BUF2_DONE_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BUF2_DONE_IRQ_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BUF2_DONE_IRQ_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_MASK (0x40000000U)
#define PXP_WFA_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_SHIFT (30U)
/*! BUF1_DONE_IRQ_EN - BUF1_DONE_IRQ_EN */
#define PXP_WFA_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_MASK)

#define PXP_WFA_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_MASK (0x80000000U)
#define PXP_WFA_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_SHIFT (31U)
/*! BUF2_DONE_IRQ_EN - BUF2_DONE_IRQ_EN */
#define PXP_WFA_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_MASK)
/*! @} */

/*! @name WFA_FETCH_CTRL_TOG - Fetch engine Control for WFE A Register */
/*! @{ */

#define PXP_WFA_FETCH_CTRL_TOG_BF1_EN_MASK       (0x1U)
#define PXP_WFA_FETCH_CTRL_TOG_BF1_EN_SHIFT      (0U)
/*! BF1_EN - BF1_EN */
#define PXP_WFA_FETCH_CTRL_TOG_BF1_EN(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF1_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF1_EN_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF1_SRAM_IF_MASK  (0x2U)
#define PXP_WFA_FETCH_CTRL_TOG_BF1_SRAM_IF_SHIFT (1U)
/*! BF1_SRAM_IF - BF1_SRAM_IF */
#define PXP_WFA_FETCH_CTRL_TOG_BF1_SRAM_IF(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF1_SRAM_IF_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF1_SRAM_IF_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF1_HSK_MODE_MASK (0x4U)
#define PXP_WFA_FETCH_CTRL_TOG_BF1_HSK_MODE_SHIFT (2U)
/*! BF1_HSK_MODE - BF1_HSK_MODE */
#define PXP_WFA_FETCH_CTRL_TOG_BF1_HSK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF1_HSK_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF1_HSK_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF1_BYPASS_MODE_MASK (0x8U)
#define PXP_WFA_FETCH_CTRL_TOG_BF1_BYPASS_MODE_SHIFT (3U)
/*! BF1_BYPASS_MODE - BF1_BYPASS_MODE */
#define PXP_WFA_FETCH_CTRL_TOG_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF1_BYPASS_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF1_BYPASS_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF1_BURST_LEN_MASK (0x10U)
#define PXP_WFA_FETCH_CTRL_TOG_BF1_BURST_LEN_SHIFT (4U)
/*! BF1_BURST_LEN - BF1_BURST_LEN */
#define PXP_WFA_FETCH_CTRL_TOG_BF1_BURST_LEN(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF1_BURST_LEN_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF1_BURST_LEN_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF1_BORDER_MODE_MASK (0x20U)
#define PXP_WFA_FETCH_CTRL_TOG_BF1_BORDER_MODE_SHIFT (5U)
/*! BF1_BORDER_MODE - BF1_BORDER_MODE */
#define PXP_WFA_FETCH_CTRL_TOG_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF1_BORDER_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF1_BORDER_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_RSVD2_MASK        (0xC0U)
#define PXP_WFA_FETCH_CTRL_TOG_RSVD2_SHIFT       (6U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_FETCH_CTRL_TOG_RSVD2(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_RSVD2_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_RSVD2_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF2_EN_MASK       (0x100U)
#define PXP_WFA_FETCH_CTRL_TOG_BF2_EN_SHIFT      (8U)
/*! BF2_EN - BF2_EN */
#define PXP_WFA_FETCH_CTRL_TOG_BF2_EN(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF2_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF2_EN_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF2_SRAM_IF_MASK  (0x200U)
#define PXP_WFA_FETCH_CTRL_TOG_BF2_SRAM_IF_SHIFT (9U)
/*! BF2_SRAM_IF - BF2_SRAM_IF */
#define PXP_WFA_FETCH_CTRL_TOG_BF2_SRAM_IF(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF2_SRAM_IF_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF2_SRAM_IF_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF2_HSK_MODE_MASK (0x400U)
#define PXP_WFA_FETCH_CTRL_TOG_BF2_HSK_MODE_SHIFT (10U)
/*! BF2_HSK_MODE - BF2_HSK_MODE */
#define PXP_WFA_FETCH_CTRL_TOG_BF2_HSK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF2_HSK_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF2_HSK_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF2_BYPASS_MODE_MASK (0x800U)
#define PXP_WFA_FETCH_CTRL_TOG_BF2_BYPASS_MODE_SHIFT (11U)
/*! BF2_BYPASS_MODE - BF2_BYPASS_MODE */
#define PXP_WFA_FETCH_CTRL_TOG_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF2_BYPASS_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF2_BYPASS_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF2_BURST_LEN_MASK (0x1000U)
#define PXP_WFA_FETCH_CTRL_TOG_BF2_BURST_LEN_SHIFT (12U)
/*! BF2_BURST_LEN - BF2_BURST_LEN */
#define PXP_WFA_FETCH_CTRL_TOG_BF2_BURST_LEN(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF2_BURST_LEN_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF2_BURST_LEN_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF2_BORDER_MODE_MASK (0x2000U)
#define PXP_WFA_FETCH_CTRL_TOG_BF2_BORDER_MODE_SHIFT (13U)
/*! BF2_BORDER_MODE - BF2_BORDER_MODE */
#define PXP_WFA_FETCH_CTRL_TOG_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF2_BORDER_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF2_BORDER_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_RSVD1_MASK        (0xC000U)
#define PXP_WFA_FETCH_CTRL_TOG_RSVD1_SHIFT       (14U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_FETCH_CTRL_TOG_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_RSVD1_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_RSVD1_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF1_BYTES_PP_MASK (0x30000U)
#define PXP_WFA_FETCH_CTRL_TOG_BF1_BYTES_PP_SHIFT (16U)
/*! BF1_BYTES_PP - BF1_BYTES_PP */
#define PXP_WFA_FETCH_CTRL_TOG_BF1_BYTES_PP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF1_BYTES_PP_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF1_BYTES_PP_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF1_LINE_MODE_MASK (0xC0000U)
#define PXP_WFA_FETCH_CTRL_TOG_BF1_LINE_MODE_SHIFT (18U)
/*! BF1_LINE_MODE - BF1_LINE_MODE */
#define PXP_WFA_FETCH_CTRL_TOG_BF1_LINE_MODE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF1_LINE_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF1_LINE_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF2_BYTES_PP_MASK (0x300000U)
#define PXP_WFA_FETCH_CTRL_TOG_BF2_BYTES_PP_SHIFT (20U)
/*! BF2_BYTES_PP - BF2_BYTES_PP */
#define PXP_WFA_FETCH_CTRL_TOG_BF2_BYTES_PP(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF2_BYTES_PP_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF2_BYTES_PP_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BF2_LINE_MODE_MASK (0xC00000U)
#define PXP_WFA_FETCH_CTRL_TOG_BF2_LINE_MODE_SHIFT (22U)
/*! BF2_LINE_MODE - BF2_LINE_MODE */
#define PXP_WFA_FETCH_CTRL_TOG_BF2_LINE_MODE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BF2_LINE_MODE_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BF2_LINE_MODE_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_RSVD0_MASK        (0xF000000U)
#define PXP_WFA_FETCH_CTRL_TOG_RSVD0_SHIFT       (24U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_FETCH_CTRL_TOG_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_RSVD0_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_RSVD0_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BUF1_DONE_IRQ_MASK (0x10000000U)
#define PXP_WFA_FETCH_CTRL_TOG_BUF1_DONE_IRQ_SHIFT (28U)
/*! BUF1_DONE_IRQ - BUF1_DONE_IRQ */
#define PXP_WFA_FETCH_CTRL_TOG_BUF1_DONE_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BUF1_DONE_IRQ_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BUF1_DONE_IRQ_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BUF2_DONE_IRQ_MASK (0x20000000U)
#define PXP_WFA_FETCH_CTRL_TOG_BUF2_DONE_IRQ_SHIFT (29U)
/*! BUF2_DONE_IRQ - BUF2_DONE_IRQ */
#define PXP_WFA_FETCH_CTRL_TOG_BUF2_DONE_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BUF2_DONE_IRQ_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BUF2_DONE_IRQ_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_MASK (0x40000000U)
#define PXP_WFA_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_SHIFT (30U)
/*! BUF1_DONE_IRQ_EN - BUF1_DONE_IRQ_EN */
#define PXP_WFA_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_MASK)

#define PXP_WFA_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_MASK (0x80000000U)
#define PXP_WFA_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_SHIFT (31U)
/*! BUF2_DONE_IRQ_EN - BUF2_DONE_IRQ_EN */
#define PXP_WFA_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFA_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_MASK)
/*! @} */

/*! @name WFA_FETCH_BUF1_ADDR -  */
/*! @{ */

#define PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR_MASK    (0xFFFFFFFFU)
#define PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR_SHIFT   (0U)
/*! BUF_ADDR - BUF_ADDR */
#define PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR_SHIFT)) & PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR_MASK)
/*! @} */

/*! @name WFA_FETCH_BUF1_PITCH -  */
/*! @{ */

#define PXP_WFA_FETCH_BUF1_PITCH_PITCH_MASK      (0xFFFFU)
#define PXP_WFA_FETCH_BUF1_PITCH_PITCH_SHIFT     (0U)
/*! PITCH - PITCH */
#define PXP_WFA_FETCH_BUF1_PITCH_PITCH(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF1_PITCH_PITCH_SHIFT)) & PXP_WFA_FETCH_BUF1_PITCH_PITCH_MASK)

#define PXP_WFA_FETCH_BUF1_PITCH_RSVD_MASK       (0xFFFF0000U)
#define PXP_WFA_FETCH_BUF1_PITCH_RSVD_SHIFT      (16U)
/*! RSVD - RSVD */
#define PXP_WFA_FETCH_BUF1_PITCH_RSVD(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF1_PITCH_RSVD_SHIFT)) & PXP_WFA_FETCH_BUF1_PITCH_RSVD_MASK)
/*! @} */

/*! @name WFA_FETCH_BUF1_SIZE -  */
/*! @{ */

#define PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH_MASK   (0x3FFFU)
#define PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH_SHIFT  (0U)
/*! BUF_WIDTH - BUF_WIDTH */
#define PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH_SHIFT)) & PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH_MASK)

#define PXP_WFA_FETCH_BUF1_SIZE_RSVD1_MASK       (0xC000U)
#define PXP_WFA_FETCH_BUF1_SIZE_RSVD1_SHIFT      (14U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_FETCH_BUF1_SIZE_RSVD1(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF1_SIZE_RSVD1_SHIFT)) & PXP_WFA_FETCH_BUF1_SIZE_RSVD1_MASK)

#define PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT_MASK  (0x3FFF0000U)
#define PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT_SHIFT (16U)
/*! BUF_HEIGHT - BUF_HEIGHT */
#define PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT_SHIFT)) & PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT_MASK)

#define PXP_WFA_FETCH_BUF1_SIZE_RSVD0_MASK       (0xC0000000U)
#define PXP_WFA_FETCH_BUF1_SIZE_RSVD0_SHIFT      (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_FETCH_BUF1_SIZE_RSVD0(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF1_SIZE_RSVD0_SHIFT)) & PXP_WFA_FETCH_BUF1_SIZE_RSVD0_MASK)
/*! @} */

/*! @name WFA_FETCH_BUF2_ADDR -  */
/*! @{ */

#define PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR_MASK    (0xFFFFFFFFU)
#define PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR_SHIFT   (0U)
/*! BUF_ADDR - BUF_ADDR */
#define PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR_SHIFT)) & PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR_MASK)
/*! @} */

/*! @name WFA_FETCH_BUF2_PITCH -  */
/*! @{ */

#define PXP_WFA_FETCH_BUF2_PITCH_PITCH_MASK      (0xFFFFU)
#define PXP_WFA_FETCH_BUF2_PITCH_PITCH_SHIFT     (0U)
/*! PITCH - PITCH */
#define PXP_WFA_FETCH_BUF2_PITCH_PITCH(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF2_PITCH_PITCH_SHIFT)) & PXP_WFA_FETCH_BUF2_PITCH_PITCH_MASK)

#define PXP_WFA_FETCH_BUF2_PITCH_RSVD_MASK       (0xFFFF0000U)
#define PXP_WFA_FETCH_BUF2_PITCH_RSVD_SHIFT      (16U)
/*! RSVD - RSVD */
#define PXP_WFA_FETCH_BUF2_PITCH_RSVD(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF2_PITCH_RSVD_SHIFT)) & PXP_WFA_FETCH_BUF2_PITCH_RSVD_MASK)
/*! @} */

/*! @name WFA_FETCH_BUF2_SIZE -  */
/*! @{ */

#define PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH_MASK   (0x3FFFU)
#define PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH_SHIFT  (0U)
/*! BUF_WIDTH - BUF_WIDTH */
#define PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH_SHIFT)) & PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH_MASK)

#define PXP_WFA_FETCH_BUF2_SIZE_RSVD1_MASK       (0xC000U)
#define PXP_WFA_FETCH_BUF2_SIZE_RSVD1_SHIFT      (14U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_FETCH_BUF2_SIZE_RSVD1(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF2_SIZE_RSVD1_SHIFT)) & PXP_WFA_FETCH_BUF2_SIZE_RSVD1_MASK)

#define PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT_MASK  (0x3FFF0000U)
#define PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT_SHIFT (16U)
/*! BUF_HEIGHT - BUF_HEIGHT */
#define PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT_SHIFT)) & PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT_MASK)

#define PXP_WFA_FETCH_BUF2_SIZE_RSVD0_MASK       (0xC0000000U)
#define PXP_WFA_FETCH_BUF2_SIZE_RSVD0_SHIFT      (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_FETCH_BUF2_SIZE_RSVD0(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF2_SIZE_RSVD0_SHIFT)) & PXP_WFA_FETCH_BUF2_SIZE_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_PIXEL0_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_PIXEL1_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_PIXEL2_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_PIXEL3_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_PIXEL4_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_PIXEL5_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_PIXEL6_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_PIXEL7_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG0_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG0_MASK_L_OFS_MASK      (0x1FU)
#define PXP_WFA_ARRAY_FLAG0_MASK_L_OFS_SHIFT     (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG0_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG0_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD5_MASK      (0xE0U)
#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD5_SHIFT     (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG0_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG0_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG0_MASK_H_OFS_MASK      (0x1F00U)
#define PXP_WFA_ARRAY_FLAG0_MASK_H_OFS_SHIFT     (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG0_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG0_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD4_MASK      (0xE000U)
#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD4_SHIFT     (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG0_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG0_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X_MASK   (0x30000U)
#define PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X_SHIFT  (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD3_MASK      (0xC0000U)
#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD3_SHIFT     (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG0_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG0_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y_MASK   (0x300000U)
#define PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y_SHIFT  (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD2_MASK      (0xC00000U)
#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD2_SHIFT     (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG0_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG0_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X_MASK     (0x1000000U)
#define PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X_SHIFT    (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y_MASK     (0x2000000U)
#define PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y_SHIFT    (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD1_MASK      (0xC000000U)
#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD1_SHIFT     (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG0_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG0_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL_MASK    (0x30000000U)
#define PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL_SHIFT   (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD0_MASK      (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD0_SHIFT     (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG0_MASK_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG0_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG0_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG1_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG1_MASK_L_OFS_MASK      (0x1FU)
#define PXP_WFA_ARRAY_FLAG1_MASK_L_OFS_SHIFT     (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG1_MASK_L_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG1_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG1_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD5_MASK      (0xE0U)
#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD5_SHIFT     (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG1_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG1_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG1_MASK_H_OFS_MASK      (0x1F00U)
#define PXP_WFA_ARRAY_FLAG1_MASK_H_OFS_SHIFT     (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG1_MASK_H_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG1_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG1_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD4_MASK      (0xE000U)
#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD4_SHIFT     (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG1_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG1_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X_MASK   (0x30000U)
#define PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X_SHIFT  (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD3_MASK      (0xC0000U)
#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD3_SHIFT     (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG1_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG1_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y_MASK   (0x300000U)
#define PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y_SHIFT  (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD2_MASK      (0xC00000U)
#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD2_SHIFT     (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG1_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG1_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X_MASK     (0x1000000U)
#define PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X_SHIFT    (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y_MASK     (0x2000000U)
#define PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y_SHIFT    (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD1_MASK      (0xC000000U)
#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD1_SHIFT     (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG1_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG1_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL_MASK    (0x30000000U)
#define PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL_SHIFT   (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD0_MASK      (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD0_SHIFT     (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG1_MASK_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG1_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG1_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG2_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG2_MASK_L_OFS_MASK      (0x1FU)
#define PXP_WFA_ARRAY_FLAG2_MASK_L_OFS_SHIFT     (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG2_MASK_L_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG2_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG2_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD5_MASK      (0xE0U)
#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD5_SHIFT     (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG2_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG2_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG2_MASK_H_OFS_MASK      (0x1F00U)
#define PXP_WFA_ARRAY_FLAG2_MASK_H_OFS_SHIFT     (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG2_MASK_H_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG2_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG2_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD4_MASK      (0xE000U)
#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD4_SHIFT     (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG2_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG2_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X_MASK   (0x30000U)
#define PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X_SHIFT  (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD3_MASK      (0xC0000U)
#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD3_SHIFT     (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG2_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG2_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y_MASK   (0x300000U)
#define PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y_SHIFT  (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD2_MASK      (0xC00000U)
#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD2_SHIFT     (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG2_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG2_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X_MASK     (0x1000000U)
#define PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X_SHIFT    (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y_MASK     (0x2000000U)
#define PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y_SHIFT    (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD1_MASK      (0xC000000U)
#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD1_SHIFT     (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG2_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG2_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL_MASK    (0x30000000U)
#define PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL_SHIFT   (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD0_MASK      (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD0_SHIFT     (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG2_MASK_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG2_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG2_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG3_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG3_MASK_L_OFS_MASK      (0x1FU)
#define PXP_WFA_ARRAY_FLAG3_MASK_L_OFS_SHIFT     (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG3_MASK_L_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG3_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG3_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD5_MASK      (0xE0U)
#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD5_SHIFT     (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG3_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG3_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG3_MASK_H_OFS_MASK      (0x1F00U)
#define PXP_WFA_ARRAY_FLAG3_MASK_H_OFS_SHIFT     (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG3_MASK_H_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG3_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG3_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD4_MASK      (0xE000U)
#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD4_SHIFT     (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG3_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG3_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X_MASK   (0x30000U)
#define PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X_SHIFT  (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD3_MASK      (0xC0000U)
#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD3_SHIFT     (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG3_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG3_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y_MASK   (0x300000U)
#define PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y_SHIFT  (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD2_MASK      (0xC00000U)
#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD2_SHIFT     (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG3_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG3_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X_MASK     (0x1000000U)
#define PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X_SHIFT    (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y_MASK     (0x2000000U)
#define PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y_SHIFT    (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD1_MASK      (0xC000000U)
#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD1_SHIFT     (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG3_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG3_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL_MASK    (0x30000000U)
#define PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL_SHIFT   (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD0_MASK      (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD0_SHIFT     (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG3_MASK_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG3_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG3_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG4_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG4_MASK_L_OFS_MASK      (0x1FU)
#define PXP_WFA_ARRAY_FLAG4_MASK_L_OFS_SHIFT     (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG4_MASK_L_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG4_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG4_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD5_MASK      (0xE0U)
#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD5_SHIFT     (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG4_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG4_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG4_MASK_H_OFS_MASK      (0x1F00U)
#define PXP_WFA_ARRAY_FLAG4_MASK_H_OFS_SHIFT     (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG4_MASK_H_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG4_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG4_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD4_MASK      (0xE000U)
#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD4_SHIFT     (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG4_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG4_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X_MASK   (0x30000U)
#define PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X_SHIFT  (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD3_MASK      (0xC0000U)
#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD3_SHIFT     (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG4_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG4_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y_MASK   (0x300000U)
#define PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y_SHIFT  (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD2_MASK      (0xC00000U)
#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD2_SHIFT     (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG4_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG4_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X_MASK     (0x1000000U)
#define PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X_SHIFT    (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y_MASK     (0x2000000U)
#define PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y_SHIFT    (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD1_MASK      (0xC000000U)
#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD1_SHIFT     (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG4_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG4_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL_MASK    (0x30000000U)
#define PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL_SHIFT   (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD0_MASK      (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD0_SHIFT     (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG4_MASK_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG4_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG4_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG5_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG5_MASK_L_OFS_MASK      (0x1FU)
#define PXP_WFA_ARRAY_FLAG5_MASK_L_OFS_SHIFT     (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG5_MASK_L_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG5_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG5_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD5_MASK      (0xE0U)
#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD5_SHIFT     (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG5_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG5_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG5_MASK_H_OFS_MASK      (0x1F00U)
#define PXP_WFA_ARRAY_FLAG5_MASK_H_OFS_SHIFT     (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG5_MASK_H_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG5_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG5_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD4_MASK      (0xE000U)
#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD4_SHIFT     (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG5_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG5_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X_MASK   (0x30000U)
#define PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X_SHIFT  (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD3_MASK      (0xC0000U)
#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD3_SHIFT     (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG5_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG5_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y_MASK   (0x300000U)
#define PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y_SHIFT  (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD2_MASK      (0xC00000U)
#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD2_SHIFT     (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG5_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG5_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X_MASK     (0x1000000U)
#define PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X_SHIFT    (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y_MASK     (0x2000000U)
#define PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y_SHIFT    (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD1_MASK      (0xC000000U)
#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD1_SHIFT     (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG5_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG5_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL_MASK    (0x30000000U)
#define PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL_SHIFT   (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD0_MASK      (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD0_SHIFT     (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG5_MASK_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG5_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG5_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG6_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG6_MASK_L_OFS_MASK      (0x1FU)
#define PXP_WFA_ARRAY_FLAG6_MASK_L_OFS_SHIFT     (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG6_MASK_L_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG6_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG6_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD5_MASK      (0xE0U)
#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD5_SHIFT     (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG6_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG6_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG6_MASK_H_OFS_MASK      (0x1F00U)
#define PXP_WFA_ARRAY_FLAG6_MASK_H_OFS_SHIFT     (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG6_MASK_H_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG6_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG6_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD4_MASK      (0xE000U)
#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD4_SHIFT     (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG6_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG6_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X_MASK   (0x30000U)
#define PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X_SHIFT  (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD3_MASK      (0xC0000U)
#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD3_SHIFT     (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG6_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG6_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y_MASK   (0x300000U)
#define PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y_SHIFT  (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD2_MASK      (0xC00000U)
#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD2_SHIFT     (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG6_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG6_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X_MASK     (0x1000000U)
#define PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X_SHIFT    (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y_MASK     (0x2000000U)
#define PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y_SHIFT    (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD1_MASK      (0xC000000U)
#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD1_SHIFT     (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG6_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG6_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL_MASK    (0x30000000U)
#define PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL_SHIFT   (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD0_MASK      (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD0_SHIFT     (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG6_MASK_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG6_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG6_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG7_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG7_MASK_L_OFS_MASK      (0x1FU)
#define PXP_WFA_ARRAY_FLAG7_MASK_L_OFS_SHIFT     (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG7_MASK_L_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG7_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG7_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD5_MASK      (0xE0U)
#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD5_SHIFT     (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG7_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG7_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG7_MASK_H_OFS_MASK      (0x1F00U)
#define PXP_WFA_ARRAY_FLAG7_MASK_H_OFS_SHIFT     (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG7_MASK_H_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG7_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG7_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD4_MASK      (0xE000U)
#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD4_SHIFT     (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG7_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG7_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X_MASK   (0x30000U)
#define PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X_SHIFT  (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD3_MASK      (0xC0000U)
#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD3_SHIFT     (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG7_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG7_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y_MASK   (0x300000U)
#define PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y_SHIFT  (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD2_MASK      (0xC00000U)
#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD2_SHIFT     (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG7_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG7_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X_MASK     (0x1000000U)
#define PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X_SHIFT    (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y_MASK     (0x2000000U)
#define PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y_SHIFT    (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD1_MASK      (0xC000000U)
#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD1_SHIFT     (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG7_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG7_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL_MASK    (0x30000000U)
#define PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL_SHIFT   (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD0_MASK      (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD0_SHIFT     (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG7_MASK_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG7_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG7_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_FETCH_BUF1_CORD -  */
/*! @{ */

#define PXP_WFA_FETCH_BUF1_CORD_XCORD_MASK       (0x3FFFU)
#define PXP_WFA_FETCH_BUF1_CORD_XCORD_SHIFT      (0U)
/*! XCORD - XCORD */
#define PXP_WFA_FETCH_BUF1_CORD_XCORD(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF1_CORD_XCORD_SHIFT)) & PXP_WFA_FETCH_BUF1_CORD_XCORD_MASK)

#define PXP_WFA_FETCH_BUF1_CORD_RSVD1_MASK       (0xC000U)
#define PXP_WFA_FETCH_BUF1_CORD_RSVD1_SHIFT      (14U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_FETCH_BUF1_CORD_RSVD1(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF1_CORD_RSVD1_SHIFT)) & PXP_WFA_FETCH_BUF1_CORD_RSVD1_MASK)

#define PXP_WFA_FETCH_BUF1_CORD_YCORD_MASK       (0x3FFF0000U)
#define PXP_WFA_FETCH_BUF1_CORD_YCORD_SHIFT      (16U)
/*! YCORD - YCORD */
#define PXP_WFA_FETCH_BUF1_CORD_YCORD(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF1_CORD_YCORD_SHIFT)) & PXP_WFA_FETCH_BUF1_CORD_YCORD_MASK)

#define PXP_WFA_FETCH_BUF1_CORD_RSVD0_MASK       (0xC0000000U)
#define PXP_WFA_FETCH_BUF1_CORD_RSVD0_SHIFT      (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_FETCH_BUF1_CORD_RSVD0(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF1_CORD_RSVD0_SHIFT)) & PXP_WFA_FETCH_BUF1_CORD_RSVD0_MASK)
/*! @} */

/*! @name WFA_FETCH_BUF2_CORD -  */
/*! @{ */

#define PXP_WFA_FETCH_BUF2_CORD_XCORD_MASK       (0x3FFFU)
#define PXP_WFA_FETCH_BUF2_CORD_XCORD_SHIFT      (0U)
/*! XCORD - XCORD */
#define PXP_WFA_FETCH_BUF2_CORD_XCORD(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF2_CORD_XCORD_SHIFT)) & PXP_WFA_FETCH_BUF2_CORD_XCORD_MASK)

#define PXP_WFA_FETCH_BUF2_CORD_RSVD1_MASK       (0xC000U)
#define PXP_WFA_FETCH_BUF2_CORD_RSVD1_SHIFT      (14U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_FETCH_BUF2_CORD_RSVD1(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF2_CORD_RSVD1_SHIFT)) & PXP_WFA_FETCH_BUF2_CORD_RSVD1_MASK)

#define PXP_WFA_FETCH_BUF2_CORD_YCORD_MASK       (0x3FFF0000U)
#define PXP_WFA_FETCH_BUF2_CORD_YCORD_SHIFT      (16U)
/*! YCORD - YCORD */
#define PXP_WFA_FETCH_BUF2_CORD_YCORD(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF2_CORD_YCORD_SHIFT)) & PXP_WFA_FETCH_BUF2_CORD_YCORD_MASK)

#define PXP_WFA_FETCH_BUF2_CORD_RSVD0_MASK       (0xC0000000U)
#define PXP_WFA_FETCH_BUF2_CORD_RSVD0_SHIFT      (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_FETCH_BUF2_CORD_RSVD0(x)         (((uint32_t)(((uint32_t)(x)) << PXP_WFA_FETCH_BUF2_CORD_RSVD0_SHIFT)) & PXP_WFA_FETCH_BUF2_CORD_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG8_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG8_MASK_L_OFS_MASK      (0x1FU)
#define PXP_WFA_ARRAY_FLAG8_MASK_L_OFS_SHIFT     (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG8_MASK_L_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG8_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG8_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD5_MASK      (0xE0U)
#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD5_SHIFT     (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG8_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG8_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG8_MASK_H_OFS_MASK      (0x1F00U)
#define PXP_WFA_ARRAY_FLAG8_MASK_H_OFS_SHIFT     (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG8_MASK_H_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG8_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG8_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD4_MASK      (0xE000U)
#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD4_SHIFT     (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG8_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG8_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X_MASK   (0x30000U)
#define PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X_SHIFT  (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD3_MASK      (0xC0000U)
#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD3_SHIFT     (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG8_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG8_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y_MASK   (0x300000U)
#define PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y_SHIFT  (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD2_MASK      (0xC00000U)
#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD2_SHIFT     (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG8_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG8_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X_MASK     (0x1000000U)
#define PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X_SHIFT    (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y_MASK     (0x2000000U)
#define PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y_SHIFT    (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD1_MASK      (0xC000000U)
#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD1_SHIFT     (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG8_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG8_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL_MASK    (0x30000000U)
#define PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL_SHIFT   (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD0_MASK      (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD0_SHIFT     (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG8_MASK_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG8_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG8_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG9_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG9_MASK_L_OFS_MASK      (0x1FU)
#define PXP_WFA_ARRAY_FLAG9_MASK_L_OFS_SHIFT     (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG9_MASK_L_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG9_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG9_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD5_MASK      (0xE0U)
#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD5_SHIFT     (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG9_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG9_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG9_MASK_H_OFS_MASK      (0x1F00U)
#define PXP_WFA_ARRAY_FLAG9_MASK_H_OFS_SHIFT     (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG9_MASK_H_OFS(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG9_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG9_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD4_MASK      (0xE000U)
#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD4_SHIFT     (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG9_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG9_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X_MASK   (0x30000U)
#define PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X_SHIFT  (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD3_MASK      (0xC0000U)
#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD3_SHIFT     (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG9_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG9_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y_MASK   (0x300000U)
#define PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y_SHIFT  (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD2_MASK      (0xC00000U)
#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD2_SHIFT     (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG9_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG9_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X_MASK     (0x1000000U)
#define PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X_SHIFT    (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y_MASK     (0x2000000U)
#define PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y_SHIFT    (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD1_MASK      (0xC000000U)
#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD1_SHIFT     (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG9_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG9_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL_MASK    (0x30000000U)
#define PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL_SHIFT   (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD0_MASK      (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD0_SHIFT     (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG9_MASK_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG9_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG9_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG10_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG10_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_FLAG10_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG10_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG10_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG10_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG10_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG10_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG10_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_FLAG10_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG10_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG10_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG10_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG10_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG10_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG10_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG10_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG10_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG10_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG10_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG10_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG10_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG10_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG10_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG11_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG11_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_FLAG11_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG11_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG11_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG11_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG11_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG11_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG11_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_FLAG11_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG11_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG11_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG11_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG11_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG11_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG11_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG11_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG11_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG11_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG11_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG11_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG11_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG11_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG11_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG12_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG12_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_FLAG12_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG12_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG12_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG12_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG12_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG12_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG12_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_FLAG12_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG12_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG12_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG12_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG12_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG12_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG12_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG12_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG12_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG12_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG12_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG12_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG12_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG12_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG12_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG13_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG13_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_FLAG13_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG13_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG13_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG13_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG13_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG13_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG13_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_FLAG13_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG13_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG13_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG13_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG13_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG13_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG13_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG13_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG13_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG13_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG13_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG13_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG13_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG13_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG13_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG14_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG14_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_FLAG14_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG14_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG14_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG14_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG14_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG14_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG14_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_FLAG14_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG14_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG14_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG14_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG14_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG14_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG14_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG14_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG14_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG14_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG14_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG14_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG14_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG14_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG14_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_FLAG15_MASK -  */
/*! @{ */

#define PXP_WFA_ARRAY_FLAG15_MASK_L_OFS_MASK     (0x1FU)
#define PXP_WFA_ARRAY_FLAG15_MASK_L_OFS_SHIFT    (0U)
/*! L_OFS - L_OFS */
#define PXP_WFA_ARRAY_FLAG15_MASK_L_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG15_MASK_L_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG15_MASK_L_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD5_MASK     (0xE0U)
#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD5_SHIFT    (5U)
/*! RSVD5 - RSVD5 */
#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG15_MASK_RSVD5_SHIFT)) & PXP_WFA_ARRAY_FLAG15_MASK_RSVD5_MASK)

#define PXP_WFA_ARRAY_FLAG15_MASK_H_OFS_MASK     (0x1F00U)
#define PXP_WFA_ARRAY_FLAG15_MASK_H_OFS_SHIFT    (8U)
/*! H_OFS - H_OFS */
#define PXP_WFA_ARRAY_FLAG15_MASK_H_OFS(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG15_MASK_H_OFS_SHIFT)) & PXP_WFA_ARRAY_FLAG15_MASK_H_OFS_MASK)

#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD4_MASK     (0xE000U)
#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD4_SHIFT    (13U)
/*! RSVD4 - RSVD4 */
#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG15_MASK_RSVD4_SHIFT)) & PXP_WFA_ARRAY_FLAG15_MASK_RSVD4_MASK)

#define PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X_MASK  (0x30000U)
#define PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X_SHIFT (16U)
/*! OFFSET_X - OFFSET_X */
#define PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X_SHIFT)) & PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X_MASK)

#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD3_MASK     (0xC0000U)
#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD3_SHIFT    (18U)
/*! RSVD3 - RSVD3 */
#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG15_MASK_RSVD3_SHIFT)) & PXP_WFA_ARRAY_FLAG15_MASK_RSVD3_MASK)

#define PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y_MASK  (0x300000U)
#define PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y_SHIFT (20U)
/*! OFFSET_Y - OFFSET_Y */
#define PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y_MASK)

#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD2_MASK     (0xC00000U)
#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD2_SHIFT    (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG15_MASK_RSVD2_SHIFT)) & PXP_WFA_ARRAY_FLAG15_MASK_RSVD2_MASK)

#define PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X_MASK    (0x1000000U)
#define PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X_SHIFT   (24U)
/*! SIGN_X - SIGN_X
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X_SHIFT)) & PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X_MASK)

#define PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y_MASK    (0x2000000U)
#define PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y_SHIFT   (25U)
/*! SIGN_Y - SIGN_Y
 *  0b0..Positive Offset
 *  0b1..Negative Offset
 */
#define PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y_SHIFT)) & PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y_MASK)

#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD1_MASK     (0xC000000U)
#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD1_SHIFT    (26U)
/*! RSVD1 - RSVD1 */
#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG15_MASK_RSVD1_SHIFT)) & PXP_WFA_ARRAY_FLAG15_MASK_RSVD1_MASK)

#define PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL_MASK   (0x30000000U)
#define PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL_SHIFT  (28U)
/*! BUF_SEL - BUF_SEL
 *  0b00..Pixel from buffer 1
 *  0b01..Pixel from buffer 2
 *  0b10..Pixel from SW_PIXEL0
 */
#define PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL_SHIFT)) & PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL_MASK)

#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD0_MASK     (0xC0000000U)
#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_FLAG15_MASK_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_FLAG15_MASK_RSVD0_SHIFT)) & PXP_WFA_ARRAY_FLAG15_MASK_RSVD0_MASK)
/*! @} */

/*! @name WFA_ARRAY_REG0 -  */
/*! @{ */

#define PXP_WFA_ARRAY_REG0_SW_PIXLE0_MASK        (0xFFU)
#define PXP_WFA_ARRAY_REG0_SW_PIXLE0_SHIFT       (0U)
/*! SW_PIXLE0 - SW_PIXLE0 */
#define PXP_WFA_ARRAY_REG0_SW_PIXLE0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG0_SW_PIXLE0_SHIFT)) & PXP_WFA_ARRAY_REG0_SW_PIXLE0_MASK)

#define PXP_WFA_ARRAY_REG0_SW_PIXLE1_MASK        (0xFF00U)
#define PXP_WFA_ARRAY_REG0_SW_PIXLE1_SHIFT       (8U)
/*! SW_PIXLE1 - SW_PIXLE1 */
#define PXP_WFA_ARRAY_REG0_SW_PIXLE1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG0_SW_PIXLE1_SHIFT)) & PXP_WFA_ARRAY_REG0_SW_PIXLE1_MASK)

#define PXP_WFA_ARRAY_REG0_SW_PIXLE2_MASK        (0xFF0000U)
#define PXP_WFA_ARRAY_REG0_SW_PIXLE2_SHIFT       (16U)
/*! SW_PIXLE2 - SW_PIXLE2 */
#define PXP_WFA_ARRAY_REG0_SW_PIXLE2(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG0_SW_PIXLE2_SHIFT)) & PXP_WFA_ARRAY_REG0_SW_PIXLE2_MASK)

#define PXP_WFA_ARRAY_REG0_SW_PIXLE3_MASK        (0xFF000000U)
#define PXP_WFA_ARRAY_REG0_SW_PIXLE3_SHIFT       (24U)
/*! SW_PIXLE3 - SW_PIXLE3 */
#define PXP_WFA_ARRAY_REG0_SW_PIXLE3(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG0_SW_PIXLE3_SHIFT)) & PXP_WFA_ARRAY_REG0_SW_PIXLE3_MASK)
/*! @} */

/*! @name WFA_ARRAY_REG1 -  */
/*! @{ */

#define PXP_WFA_ARRAY_REG1_SW_PIXLE4_MASK        (0xFFU)
#define PXP_WFA_ARRAY_REG1_SW_PIXLE4_SHIFT       (0U)
/*! SW_PIXLE4 - SW_PIXLE4 */
#define PXP_WFA_ARRAY_REG1_SW_PIXLE4(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG1_SW_PIXLE4_SHIFT)) & PXP_WFA_ARRAY_REG1_SW_PIXLE4_MASK)

#define PXP_WFA_ARRAY_REG1_SW_PIXLE5_MASK        (0xFF00U)
#define PXP_WFA_ARRAY_REG1_SW_PIXLE5_SHIFT       (8U)
/*! SW_PIXLE5 - SW_PIXLE5 */
#define PXP_WFA_ARRAY_REG1_SW_PIXLE5(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG1_SW_PIXLE5_SHIFT)) & PXP_WFA_ARRAY_REG1_SW_PIXLE5_MASK)

#define PXP_WFA_ARRAY_REG1_SW_PIXLE6_MASK        (0xFF0000U)
#define PXP_WFA_ARRAY_REG1_SW_PIXLE6_SHIFT       (16U)
/*! SW_PIXLE6 - SW_PIXLE6 */
#define PXP_WFA_ARRAY_REG1_SW_PIXLE6(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG1_SW_PIXLE6_SHIFT)) & PXP_WFA_ARRAY_REG1_SW_PIXLE6_MASK)

#define PXP_WFA_ARRAY_REG1_SW_PIXLE7_MASK        (0xFF000000U)
#define PXP_WFA_ARRAY_REG1_SW_PIXLE7_SHIFT       (24U)
/*! SW_PIXLE7 - SW_PIXLE7 */
#define PXP_WFA_ARRAY_REG1_SW_PIXLE7(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG1_SW_PIXLE7_SHIFT)) & PXP_WFA_ARRAY_REG1_SW_PIXLE7_MASK)
/*! @} */

/*! @name WFA_ARRAY_REG2 -  */
/*! @{ */

#define PXP_WFA_ARRAY_REG2_SW_FLAG0_MASK         (0x1U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG0_SHIFT        (0U)
/*! SW_FLAG0 - SW_FLAG0 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG0_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG0_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG1_MASK         (0x2U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG1_SHIFT        (1U)
/*! SW_FLAG1 - SW_FLAG1 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG1_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG1_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG2_MASK         (0x4U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG2_SHIFT        (2U)
/*! SW_FLAG2 - SW_FLAG2 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG2_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG2_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG3_MASK         (0x8U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG3_SHIFT        (3U)
/*! SW_FLAG3 - SW_FLAG3 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG3_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG3_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG4_MASK         (0x10U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG4_SHIFT        (4U)
/*! SW_FLAG4 - SW_FLAG4 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG4(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG4_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG4_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG5_MASK         (0x20U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG5_SHIFT        (5U)
/*! SW_FLAG5 - SW_FLAG5 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG5(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG5_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG5_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG6_MASK         (0x40U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG6_SHIFT        (6U)
/*! SW_FLAG6 - SW_FLAG6 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG6(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG6_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG6_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG7_MASK         (0x80U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG7_SHIFT        (7U)
/*! SW_FLAG7 - SW_FLAG7 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG7(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG7_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG7_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG8_MASK         (0x100U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG8_SHIFT        (8U)
/*! SW_FLAG8 - SW_FLAG8 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG8(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG8_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG8_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG9_MASK         (0x200U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG9_SHIFT        (9U)
/*! SW_FLAG9 - SW_FLAG9 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG9(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG9_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG9_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG10_MASK        (0x400U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG10_SHIFT       (10U)
/*! SW_FLAG10 - SW_FLAG10 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG10(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG10_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG10_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG11_MASK        (0x800U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG11_SHIFT       (11U)
/*! SW_FLAG11 - SW_FLAG11 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG11(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG11_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG11_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG12_MASK        (0x1000U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG12_SHIFT       (12U)
/*! SW_FLAG12 - SW_FLAG12 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG12(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG12_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG12_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG13_MASK        (0x2000U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG13_SHIFT       (13U)
/*! SW_FLAG13 - SW_FLAG13 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG13(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG13_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG13_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG14_MASK        (0x4000U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG14_SHIFT       (14U)
/*! SW_FLAG14 - SW_FLAG14 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG14(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG14_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG14_MASK)

#define PXP_WFA_ARRAY_REG2_SW_FLAG15_MASK        (0x8000U)
#define PXP_WFA_ARRAY_REG2_SW_FLAG15_SHIFT       (15U)
/*! SW_FLAG15 - SW_FLAG15 */
#define PXP_WFA_ARRAY_REG2_SW_FLAG15(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_SW_FLAG15_SHIFT)) & PXP_WFA_ARRAY_REG2_SW_FLAG15_MASK)

#define PXP_WFA_ARRAY_REG2_RSVD0_MASK            (0xFFFF0000U)
#define PXP_WFA_ARRAY_REG2_RSVD0_SHIFT           (16U)
/*! RSVD0 - RSVD0 */
#define PXP_WFA_ARRAY_REG2_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFA_ARRAY_REG2_RSVD0_SHIFT)) & PXP_WFA_ARRAY_REG2_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_CTRL_CH0 - Pre-fetch engine Control Channel 0 Register */
/*! @{ */

#define PXP_WFE_A_STORE_CTRL_CH0_CH_EN_MASK      (0x1U)
#define PXP_WFE_A_STORE_CTRL_CH0_CH_EN_SHIFT     (0U)
/*! CH_EN - CH_EN
 *  0b0..Store function is disable
 *  0b1..Store function is enable
 */
#define PXP_WFE_A_STORE_CTRL_CH0_CH_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CH_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CH_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN_MASK   (0x2U)
#define PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN_SHIFT  (1U)
/*! BLOCK_EN - BLOCK_EN
 *  0b0..Store in scan mode
 *  0b1..Store in block mode
 */
#define PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16_MASK   (0x4U)
#define PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16_SHIFT  (2U)
/*! BLOCK_16 - BLOCK_16
 *  0b0..BLK_SIZE_8x8 : Block size is 8x8
 *  0b1..BLK_SIZE_16x16 : Block size is 16x16
 */
#define PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN
 *  0b0..Handshake with the prefetch engine is disabled
 *  0b1..Handshake with the prefetch engine is enabled
 */
#define PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN_MASK   (0x10U)
#define PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN_SHIFT  (4U)
/*! ARRAY_EN - ARRAY_EN
 *  0b0..Array Handshake Disabled
 *  0b1..Array Handshake Enabled
 */
#define PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM
 *  0b00..Using 1x1 Array
 *  0b01..Using 3x3 Array
 *  0b10..Using 5x5 Array
 *  0b11..Using 5x5 Array
 */
#define PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_RSVD3_MASK      (0x80U)
#define PXP_WFE_A_STORE_CTRL_CH0_RSVD3_SHIFT     (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STORE_CTRL_CH0_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_RSVD3_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_RSVD3_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN
 *  0b0..store bypass mode disable.
 *  0b1..store bypass mode enable. Data will bypass to store output.
 */
#define PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN
 *  0b0..store memory mode disable.
 *  0b1..store memory mode enable. Data will store to memory
 */
#define PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL
 *  0b0..select 64 shift out data to pack
 *  0b1..select low 32 bit shift out data to pack
 */
#define PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN_MASK (0x800U)
#define PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN
 *  0b0..Fill data mode disable.
 *  0b1..Fill data mode enable. When using fill_data mode, store_engine will store fixed data defined in fill_data register
 */
#define PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_RSVD2_MASK      (0xF000U)
#define PXP_WFE_A_STORE_CTRL_CH0_RSVD2_SHIFT     (12U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_CTRL_CH0_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_RSVD2_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_RSVD2_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES
 *  0b00..NUM_8_BYTES : 8 bytes
 *  0b01..NUM_16_BYTES : 16 bytes
 *  0b10..NUM_32_BYTES : 32 bytes
 *  0b11..NUM_64_BYTES : 64 bytes
 */
#define PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_RSVD1_MASK      (0xFC0000U)
#define PXP_WFE_A_STORE_CTRL_CH0_RSVD1_SHIFT     (18U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_CTRL_CH0_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_RSVD1_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_RSVD1_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL
 *  0b0..combine 2 channel disable
 *  0b1..combine 2 channel enable
 */
#define PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_RSVD0_MASK      (0x7E000000U)
#define PXP_WFE_A_STORE_CTRL_CH0_RSVD0_SHIFT     (25U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_CTRL_CH0_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_RSVD0_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_RSVD0_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN_MASK   (0x80000000U)
#define PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN_SHIFT  (31U)
/*! ARBIT_EN - ARBIT_EN
 *  0b0..Arbitration disable. If using 2 channels, will output 2 axi bus sets
 *  0b1..Arbitration enable. If using 2 channel, will only output 1 axi bus sets
 */
#define PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN_MASK)
/*! @} */

/*! @name WFE_A_STORE_CTRL_CH0_SET - Pre-fetch engine Control Channel 0 Register */
/*! @{ */

#define PXP_WFE_A_STORE_CTRL_CH0_SET_CH_EN_MASK  (0x1U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_CH_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_CH_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_BLOCK_EN_MASK (0x2U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_BLOCK_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_BLOCK_16_MASK (0x4U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_BLOCK_16_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_ARRAY_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_ARRAY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD3_MASK  (0x80U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD3_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD3_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK (0x800U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD2_MASK  (0xF000U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD2_SHIFT (12U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD2_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD2_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD1_MASK  (0xFC0000U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD1_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD1_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD0_MASK  (0x7E000000U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD0_SHIFT (25U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD0_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_RSVD0_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_SET_ARBIT_EN_MASK (0x80000000U)
#define PXP_WFE_A_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_SET_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_SET_ARBIT_EN_MASK)
/*! @} */

/*! @name WFE_A_STORE_CTRL_CH0_CLR - Pre-fetch engine Control Channel 0 Register */
/*! @{ */

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_CH_EN_MASK  (0x1U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_CH_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_CH_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK (0x2U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_BLOCK_16_MASK (0x4U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_BLOCK_16_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD3_MASK  (0x80U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD3_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK (0x800U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD2_MASK  (0xF000U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD2_SHIFT (12U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD2_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD1_MASK  (0xFC0000U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD1_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD0_MASK  (0x7E000000U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD0_SHIFT (25U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_RSVD0_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK (0x80000000U)
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_CLR_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK)
/*! @} */

/*! @name WFE_A_STORE_CTRL_CH0_TOG - Pre-fetch engine Control Channel 0 Register */
/*! @{ */

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_CH_EN_MASK  (0x1U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_CH_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_CH_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK (0x2U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_BLOCK_16_MASK (0x4U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_BLOCK_16_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD3_MASK  (0x80U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD3_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK (0x800U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD2_MASK  (0xF000U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD2_SHIFT (12U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD2_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD1_MASK  (0xFC0000U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD1_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD0_MASK  (0x7E000000U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD0_SHIFT (25U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_RSVD0_MASK)

#define PXP_WFE_A_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK (0x80000000U)
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_WFE_A_STORE_CTRL_CH0_TOG_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK)
/*! @} */

/*! @name WFE_A_STORE_CTRL_CH1 - Pre-fetch engine Control Channel 1 Register */
/*! @{ */

#define PXP_WFE_A_STORE_CTRL_CH1_CH_EN_MASK      (0x1U)
#define PXP_WFE_A_STORE_CTRL_CH1_CH_EN_SHIFT     (0U)
/*! CH_EN - CH_EN
 *  0b0..Store function is disable
 *  0b1..Store function is enable
 */
#define PXP_WFE_A_STORE_CTRL_CH1_CH_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CH_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CH_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN_MASK   (0x2U)
#define PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN_SHIFT  (1U)
/*! BLOCK_EN - BLOCK_EN
 *  0b0..Store in scan mode
 *  0b1..Store in block mode
 */
#define PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16_MASK   (0x4U)
#define PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16_SHIFT  (2U)
/*! BLOCK_16 - BLOCK_16
 *  0b0..BLK_SIZE_8x8 : Block size is 8x8
 *  0b1..BLK_SIZE_16x16 : Block size is 16x16
 */
#define PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN
 *  0b0..Handshake with the fetch engine is disabled
 *  0b1..Handshake with the fetch engine is enabled
 */
#define PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN_MASK   (0x10U)
#define PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN_SHIFT  (4U)
/*! ARRAY_EN - ARRAY_EN
 *  0b0..Array Handshake Disabled
 *  0b1..Array Handshake Enabled
 */
#define PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM
 *  0b00..Using 1x1 Array
 *  0b01..Using 3x3 Array
 *  0b10..Using 5x5 Array
 *  0b11..Using 5x5 Array
 */
#define PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_RSVD3_MASK      (0x80U)
#define PXP_WFE_A_STORE_CTRL_CH1_RSVD3_SHIFT     (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STORE_CTRL_CH1_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_RSVD3_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_RSVD3_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN
 *  0b0..store bypass mode disable.
 *  0b1..store bypass mode enable. Data will bypass to store output.
 */
#define PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN
 *  0b0..store memory mode disable.
 *  0b1..store memory mode enable. Data will store to memory
 */
#define PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL
 *  0b0..select 64 shift out data to pack
 *  0b1..select channel 0 high 32 bit shift out data to pack
 */
#define PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_RSVD1_MASK      (0xF800U)
#define PXP_WFE_A_STORE_CTRL_CH1_RSVD1_SHIFT     (11U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_CTRL_CH1_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_RSVD1_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_RSVD1_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES
 *  0b00..NUM_8_BYTES : 8 bytes
 *  0b01..NUM_16_BYTES : 16 bytes
 *  0b10..NUM_32_BYTES : 32 bytes
 *  0b11..NUM_64_BYTES : 64 bytes
 */
#define PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_RSVD0_MASK      (0xFFFC0000U)
#define PXP_WFE_A_STORE_CTRL_CH1_RSVD0_SHIFT     (18U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_CTRL_CH1_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_RSVD0_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_CTRL_CH1_SET - Pre-fetch engine Control Channel 1 Register */
/*! @{ */

#define PXP_WFE_A_STORE_CTRL_CH1_SET_CH_EN_MASK  (0x1U)
#define PXP_WFE_A_STORE_CTRL_CH1_SET_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_SET_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_SET_CH_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_SET_CH_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_SET_BLOCK_EN_MASK (0x2U)
#define PXP_WFE_A_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_SET_BLOCK_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_SET_BLOCK_16_MASK (0x4U)
#define PXP_WFE_A_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_WFE_A_STORE_CTRL_CH1_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_SET_BLOCK_16_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_A_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_SET_ARRAY_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_SET_ARRAY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_A_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_WFE_A_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD3_MASK  (0x80U)
#define PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD3_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD3_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_A_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_A_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_A_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_WFE_A_STORE_CTRL_CH1_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD1_MASK  (0xF800U)
#define PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD1_SHIFT (11U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD1_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD1_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_A_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_WFE_A_STORE_CTRL_CH1_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD0_MASK  (0xFFFC0000U)
#define PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD0_SHIFT (18U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD0_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_CTRL_CH1_CLR - Pre-fetch engine Control Channel 1 Register */
/*! @{ */

#define PXP_WFE_A_STORE_CTRL_CH1_CLR_CH_EN_MASK  (0x1U)
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CLR_CH_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CLR_CH_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK (0x2U)
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_CLR_BLOCK_16_MASK (0x4U)
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CLR_BLOCK_16_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD3_MASK  (0x80U)
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD3_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD1_MASK  (0xF800U)
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD1_SHIFT (11U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD1_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD0_MASK  (0xFFFC0000U)
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD0_SHIFT (18U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_CTRL_CH1_TOG - Pre-fetch engine Control Channel 1 Register */
/*! @{ */

#define PXP_WFE_A_STORE_CTRL_CH1_TOG_CH_EN_MASK  (0x1U)
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_TOG_CH_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_TOG_CH_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK (0x2U)
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_TOG_BLOCK_16_MASK (0x4U)
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_TOG_BLOCK_16_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD3_MASK  (0x80U)
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD3_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD1_MASK  (0xF800U)
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD1_SHIFT (11U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD1_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK)

#define PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD0_MASK  (0xFFFC0000U)
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD0_SHIFT (18U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STORE_CTRL_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_STATUS_CH0 - Store engine status Channel 0 Register */
/*! @{ */

#define PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X_MASK (0xFFFFU)
#define PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT (0U)
/*! STORE_BLOCK_X - STORE_BLOCK_X */
#define PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT)) & PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X_MASK)

#define PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK (0xFFFF0000U)
#define PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT (16U)
/*! STORE_BLOCK_Y - STORE_BLOCK_Y */
#define PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT)) & PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK)
/*! @} */

/*! @name WFE_A_STORE_STATUS_CH1 - Store engine status Channel 1 Register */
/*! @{ */

#define PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X_MASK (0xFFFFU)
#define PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT (0U)
/*! STORE_BLOCK_X - STORE_BLOCK_X */
#define PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT)) & PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X_MASK)

#define PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK (0xFFFF0000U)
#define PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT (16U)
/*! STORE_BLOCK_Y - STORE_BLOCK_Y */
#define PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT)) & PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK)
/*! @} */

/*! @name WFE_A_STORE_SIZE_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH_MASK  (0xFFFFU)
#define PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH_SHIFT (0U)
/*! OUT_WIDTH - OUT_WIDTH */
#define PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH_SHIFT)) & PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH_MASK)

#define PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT_MASK (0xFFFF0000U)
#define PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT (16U)
/*! OUT_HEIGHT - OUT_HEIGHT */
#define PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT)) & PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT_MASK)
/*! @} */

/*! @name WFE_A_STORE_SIZE_CH1 -  */
/*! @{ */

#define PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH_MASK  (0xFFFFU)
#define PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH_SHIFT (0U)
/*! OUT_WIDTH - OUT_WIDTH */
#define PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH_SHIFT)) & PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH_MASK)

#define PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT_MASK (0xFFFF0000U)
#define PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT (16U)
/*! OUT_HEIGHT - OUT_HEIGHT */
#define PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT)) & PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT_MASK)
/*! @} */

/*! @name WFE_A_STORE_PITCH -  */
/*! @{ */

#define PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH_MASK (0xFFFFU)
#define PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH_SHIFT (0U)
/*! CH0_OUT_PITCH - CH0_OUT_PITCH */
#define PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH_SHIFT)) & PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH_MASK)

#define PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH_MASK (0xFFFF0000U)
#define PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH_SHIFT (16U)
/*! CH1_OUT_PITCH - CH1_OUT_PITCH */
#define PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH_SHIFT)) & PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH_MASK)
/*! @} */

/*! @name WFE_A_STORE_SHIFT_CTRL_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2_MASK (0x3U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP
 *  0b00..8 bits
 *  0b01..16 bits
 *  0b10..32 bits
 *  0b11..32 bits
 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1_MASK (0x40U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK (0x80U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS
 *  0b0..data will do shift processing.
 *  0b1..data will bypass shift module.
 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0_MASK (0xFFFFFF00U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_SHIFT_CTRL_CH0_SET -  */
/*! @{ */

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD2_MASK (0x3U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD2_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD2_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD1_MASK (0x40U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD1_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD1_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK (0x80U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD0_MASK (0xFFFFFF00U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD0_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_SHIFT_CTRL_CH0_CLR -  */
/*! @{ */

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_MASK (0x3U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_MASK (0x40U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK (0x80U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_MASK (0xFFFFFF00U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_SHIFT_CTRL_CH0_TOG -  */
/*! @{ */

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_MASK (0x3U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_MASK (0x40U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK (0x80U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_MASK (0xFFFFFF00U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_SHIFT_CTRL_CH1 -  */
/*! @{ */

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2_MASK (0x3U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP
 *  0b00..8 bits
 *  0b01..16 bits
 *  0b10..32 bits
 *  0b11..32 bits
 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_SHIFT_CTRL_CH1_SET -  */
/*! @{ */

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_RSVD2_MASK (0x3U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_RSVD2_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_RSVD2_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_RSVD0_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_SHIFT_CTRL_CH1_CLR -  */
/*! @{ */

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_MASK (0x3U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_SHIFT_CTRL_CH1_TOG -  */
/*! @{ */

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_MASK (0x3U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_ADDR_0_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT (0U)
/*! OUT_BASE_ADDR0 - OUT_BASE_ADDR0 */
#define PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT)) & PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK)
/*! @} */

/*! @name WFE_A_STORE_ADDR_1_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT (0U)
/*! OUT_BASE_ADDR1 - OUT_BASE_ADDR1 */
#define PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT)) & PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK)
/*! @} */

/*! @name WFE_A_STORE_FILL_DATA_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT (0U)
/*! FILL_DATA_CH0 - FILL_DATA_CH0 */
#define PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT)) & PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_ADDR_0_CH1 -  */
/*! @{ */

#define PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT (0U)
/*! OUT_BASE_ADDR0 - OUT_BASE_ADDR0 */
#define PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT)) & PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK)
/*! @} */

/*! @name WFE_A_STORE_ADDR_1_CH1 -  */
/*! @{ */

#define PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT (0U)
/*! OUT_BASE_ADDR1 - OUT_BASE_ADDR1 */
#define PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT)) & PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK0_H_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT (0U)
/*! D_MASK0_H_CH0 - D_MASK0_H_CH0 */
#define PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK0_L_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT (0U)
/*! D_MASK0_L_CH0 - D_MASK0_L_CH0 */
#define PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK1_H_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT (0U)
/*! D_MASK1_H_CH0 - D_MASK1_H_CH0 */
#define PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK1_L_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT (0U)
/*! D_MASK1_L_CH0 - D_MASK1_L_CH0 */
#define PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK2_H_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT (0U)
/*! D_MASK2_H_CH0 - D_MASK2_H_CH0 */
#define PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK2_L_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT (0U)
/*! D_MASK2_L_CH0 - D_MASK2_L_CH0 */
#define PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK3_H_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT (0U)
/*! D_MASK3_H_CH0 - D_MASK3_H_CH0 */
#define PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK3_L_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT (0U)
/*! D_MASK3_L_CH0 - D_MASK3_L_CH0 */
#define PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK4_H_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT (0U)
/*! D_MASK4_H_CH0 - D_MASK4_H_CH0 */
#define PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK4_L_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT (0U)
/*! D_MASK4_L_CH0 - D_MASK4_L_CH0 */
#define PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK5_H_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT (0U)
/*! D_MASK5_H_CH0 - D_MASK5_H_CH0 */
#define PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK5_L_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT (0U)
/*! D_MASK5_L_CH0 - D_MASK5_L_CH0 */
#define PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK6_H_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT (0U)
/*! D_MASK6_H_CH0 - D_MASK6_H_CH0 */
#define PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK6_L_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT (0U)
/*! D_MASK6_L_CH0 - D_MASK6_L_CH0 */
#define PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK7_H_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT (0U)
/*! D_MASK7_H_CH0 - D_MASK7_H_CH0 */
#define PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_MASK7_L_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT (0U)
/*! D_MASK7_L_CH0 - D_MASK7_L_CH0 */
#define PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT)) & PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_SHIFT_L_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK (0x3FU)
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT (0U)
/*! D_SHIFT_WIDTH0 - D_SHIFT_WIDTH0 */
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3_MASK (0x40U)
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3_SHIFT (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK (0x80U)
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT (7U)
/*! D_SHIFT_FLAG0 - D_SHIFT_FLAG0 */
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK (0x3F00U)
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT (8U)
/*! D_SHIFT_WIDTH1 - D_SHIFT_WIDTH1 */
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2_MASK (0x4000U)
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK (0x8000U)
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT (15U)
/*! D_SHIFT_FLAG1 - D_SHIFT_FLAG1 */
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK (0x3F0000U)
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT (16U)
/*! D_SHIFT_WIDTH2 - D_SHIFT_WIDTH2 */
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1_MASK (0x400000U)
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1_SHIFT (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK (0x800000U)
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT (23U)
/*! D_SHIFT_FLAG2 - D_SHIFT_FLAG2 */
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK (0x3F000000U)
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT (24U)
/*! D_SHIFT_WIDTH3 - D_SHIFT_WIDTH3 */
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0_MASK (0x40000000U)
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0_SHIFT (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK (0x80000000U)
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT (31U)
/*! D_SHIFT_FLAG3 - D_SHIFT_FLAG3 */
#define PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK)
/*! @} */

/*! @name WFE_A_STORE_D_SHIFT_H_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK (0x3FU)
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT (0U)
/*! D_SHIFT_WIDTH4 - D_SHIFT_WIDTH4 */
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3_MASK (0x40U)
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3_SHIFT (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK (0x80U)
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT (7U)
/*! D_SHIFT_FLAG4 - D_SHIFT_FLAG4 */
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK (0x3F00U)
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT (8U)
/*! D_SHIFT_WIDTH5 - D_SHIFT_WIDTH5 */
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2_MASK (0x4000U)
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK (0x8000U)
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT (15U)
/*! D_SHIFT_FLAG5 - D_SHIFT_FLAG5 */
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK (0x3F0000U)
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT (16U)
/*! D_SHIFT_WIDTH6 - D_SHIFT_WIDTH6 */
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1_MASK (0x400000U)
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1_SHIFT (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK (0x800000U)
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT (23U)
/*! D_SHIFT_FLAG6 - D_SHIFT_FLAG6 */
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK (0x3F000000U)
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT (24U)
/*! D_SHIFT_WIDTH7 - D_SHIFT_WIDTH7 */
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0_MASK (0x40000000U)
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0_SHIFT (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0_MASK)

#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK (0x80000000U)
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT (31U)
/*! D_SHIFT_FLAG7 - D_SHIFT_FLAG7 */
#define PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT)) & PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK)
/*! @} */

/*! @name WFE_A_STORE_F_SHIFT_L_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK (0x3FU)
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT (0U)
/*! F_SHIFT_WIDTH0 - F_SHIFT_WIDTH0 */
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK (0x40U)
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT (6U)
/*! F_SHIFT_FLAG0 - F_SHIFT_FLAG0 */
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3_MASK (0x80U)
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK (0x3F00U)
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT (8U)
/*! F_SHIFT_WIDTH1 - F_SHIFT_WIDTH1 */
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK (0x4000U)
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT (14U)
/*! F_SHIFT_FLAG1 - F_SHIFT_FLAG1 */
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2_MASK (0x8000U)
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2_SHIFT (15U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK (0x3F0000U)
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT (16U)
/*! F_SHIFT_WIDTH2 - F_SHIFT_WIDTH2 */
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK (0x400000U)
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT (22U)
/*! F_SHIFT_FLAG2 - F_SHIFT_FLAG2 */
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1_MASK (0x800000U)
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1_SHIFT (23U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK (0x3F000000U)
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT (24U)
/*! F_SHIFT_WIDTH3 - F_SHIFT_WIDTH3 */
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK (0x40000000U)
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT (30U)
/*! F_SHIFT_FLAG3 - F_SHIFT_FLAG3 */
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0_MASK (0x80000000U)
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0_SHIFT (31U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_F_SHIFT_H_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK (0x3FU)
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT (0U)
/*! F_SHIFT_WIDTH4 - F_SHIFT_WIDTH4 */
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK (0x40U)
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT (6U)
/*! F_SHIFT_FLAG4 - F_SHIFT_FLAG4 */
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3_MASK (0x80U)
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK (0x3F00U)
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT (8U)
/*! F_SHIFT_WIDTH5 - F_SHIFT_WIDTH5 */
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK (0x4000U)
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT (14U)
/*! F_SHIFT_FLAG5 - F_SHIFT_FLAG5 */
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2_MASK (0x8000U)
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2_SHIFT (15U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK (0x3F0000U)
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT (16U)
/*! F_SHIFT_WIDTH6 - F_SHIFT_WIDTH6 */
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK (0x400000U)
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT (22U)
/*! F_SHIFT_FLAG6 - F_SHIFT_FLAG6 */
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1_MASK (0x800000U)
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1_SHIFT (23U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK (0x3F000000U)
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT (24U)
/*! F_SHIFT_WIDTH7 - F_SHIFT_WIDTH7 */
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK (0x40000000U)
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT (30U)
/*! F_SHIFT_FLAG7 - F_SHIFT_FLAG7 */
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK)

#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0_MASK (0x80000000U)
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0_SHIFT (31U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0_SHIFT)) & PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STORE_F_MASK_L_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0_MASK (0xFFU)
#define PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0_SHIFT (0U)
/*! F_MASK0 - F_MASK0 */
#define PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0_SHIFT)) & PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0_MASK)

#define PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1_MASK (0xFF00U)
#define PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1_SHIFT (8U)
/*! F_MASK1 - F_MASK1 */
#define PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1_SHIFT)) & PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1_MASK)

#define PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2_MASK (0xFF0000U)
#define PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2_SHIFT (16U)
/*! F_MASK2 - F_MASK2 */
#define PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2_SHIFT)) & PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2_MASK)

#define PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3_MASK (0xFF000000U)
#define PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3_SHIFT (24U)
/*! F_MASK3 - F_MASK3 */
#define PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3_SHIFT)) & PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3_MASK)
/*! @} */

/*! @name WFE_A_STORE_F_MASK_H_CH0 -  */
/*! @{ */

#define PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4_MASK (0xFFU)
#define PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4_SHIFT (0U)
/*! F_MASK4 - F_MASK4 */
#define PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4_SHIFT)) & PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4_MASK)

#define PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5_MASK (0xFF00U)
#define PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5_SHIFT (8U)
/*! F_MASK5 - F_MASK5 */
#define PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5_SHIFT)) & PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5_MASK)

#define PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6_MASK (0xFF0000U)
#define PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6_SHIFT (16U)
/*! F_MASK6 - F_MASK6 */
#define PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6_SHIFT)) & PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6_MASK)

#define PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7_MASK (0xFF000000U)
#define PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7_SHIFT (24U)
/*! F_MASK7 - F_MASK7 */
#define PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7_SHIFT)) & PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7_MASK)
/*! @} */

/*! @name WFE_B_STORE_CTRL_CH0 - Store engine Control Channel 0 Register */
/*! @{ */

#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN_MASK      (0x1U)
#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN_SHIFT     (0U)
/*! CH_EN - CH_EN
 *  0b0..Store function is disable
 *  0b1..Store function is enable
 */
#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CH_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_MASK   (0x2U)
#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_SHIFT  (1U)
/*! BLOCK_EN - BLOCK_EN
 *  0b0..Store in scan mode
 *  0b1..Store in block mode
 */
#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_MASK   (0x4U)
#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_SHIFT  (2U)
/*! BLOCK_16 - BLOCK_16
 *  0b0..BLK_SIZE_8x8 : Block size is 8x8
 *  0b1..BLK_SIZE_16x16 : Block size is 16x16
 */
#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN
 *  0b0..Handshake with the prefetch engine is disabled
 *  0b1..Handshake with the prefetch engine is enabled
 */
#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_MASK   (0x10U)
#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_SHIFT  (4U)
/*! ARRAY_EN - ARRAY_EN
 *  0b0..Array Handshake Disabled
 *  0b1..Array Handshake Enabled
 */
#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM
 *  0b00..Using 1x1 Array
 *  0b01..Using 3x3 Array
 *  0b10..Using 5x5 Array
 *  0b11..Using 5x5 Array
 */
#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_RSVD3_MASK      (0x80U)
#define PXP_WFE_B_STORE_CTRL_CH0_RSVD3_SHIFT     (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STORE_CTRL_CH0_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_RSVD3_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_RSVD3_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN
 *  0b0..store bypass mode disable.
 *  0b1..store bypass mode enable. Data will bypass to store output.
 */
#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN
 *  0b0..store memory mode disable.
 *  0b1..store memory mode enable. Data will store to memory
 */
#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL
 *  0b0..select 64 shift out data to pack
 *  0b1..select low 32 bit shift out data to pack
 */
#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_MASK (0x800U)
#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN
 *  0b0..Fill data mode disable.
 *  0b1..Fill data mode enable. When using fill_data mode, store_engine will store fixed data defined in fill_data register
 */
#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_RSVD2_MASK      (0xF000U)
#define PXP_WFE_B_STORE_CTRL_CH0_RSVD2_SHIFT     (12U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_CTRL_CH0_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_RSVD2_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_RSVD2_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES
 *  0b00..NUM_8_BYTES : 8 bytes
 *  0b01..NUM_16_BYTES : 16 bytes
 *  0b10..NUM_32_BYTES : 32 bytes
 *  0b11..NUM_64_BYTES : 64 bytes
 */
#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_RSVD1_MASK      (0xFC0000U)
#define PXP_WFE_B_STORE_CTRL_CH0_RSVD1_SHIFT     (18U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_CTRL_CH0_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_RSVD1_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_RSVD1_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL
 *  0b0..combine 2 channel disable
 *  0b1..combine 2 channel enable
 */
#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_RSVD0_MASK      (0x7E000000U)
#define PXP_WFE_B_STORE_CTRL_CH0_RSVD0_SHIFT     (25U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_CTRL_CH0_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_RSVD0_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_RSVD0_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_MASK   (0x80000000U)
#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_SHIFT  (31U)
/*! ARBIT_EN - ARBIT_EN
 *  0b0..Arbitration disable. If using 2 channels, will output 2 axi bus sets
 *  0b1..Arbitration enable. If using 2 channel, will only output 1 axi bus sets
 */
#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_MASK)
/*! @} */

/*! @name WFE_B_STORE_CTRL_CH0_SET - Store engine Control Channel 0 Register */
/*! @{ */

#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_MASK  (0x1U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_MASK (0x2U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_MASK (0x4U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD3_MASK  (0x80U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD3_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD3_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK (0x800U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD2_MASK  (0xF000U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD2_SHIFT (12U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD2_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD2_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD1_MASK  (0xFC0000U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD1_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD1_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD0_MASK  (0x7E000000U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD0_SHIFT (25U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD0_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_RSVD0_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_MASK (0x80000000U)
#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_MASK)
/*! @} */

/*! @name WFE_B_STORE_CTRL_CH0_CLR - Store engine Control Channel 0 Register */
/*! @{ */

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_MASK  (0x1U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK (0x2U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_MASK (0x4U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD3_MASK  (0x80U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD3_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK (0x800U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD2_MASK  (0xF000U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD2_SHIFT (12U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD2_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD1_MASK  (0xFC0000U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD1_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD0_MASK  (0x7E000000U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD0_SHIFT (25U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_RSVD0_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK (0x80000000U)
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK)
/*! @} */

/*! @name WFE_B_STORE_CTRL_CH0_TOG - Store engine Control Channel 0 Register */
/*! @{ */

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_MASK  (0x1U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK (0x2U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_MASK (0x4U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD3_MASK  (0x80U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD3_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK (0x800U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT (11U)
/*! FILL_DATA_EN - FILL_DATA_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD2_MASK  (0xF000U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD2_SHIFT (12U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD2_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD1_MASK  (0xFC0000U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD1_SHIFT (18U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD1_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK (0x1000000U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT (24U)
/*! COMBINE_2CHANNEL - COMBINE_2CHANNEL */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD0_MASK  (0x7E000000U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD0_SHIFT (25U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_RSVD0_MASK)

#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK (0x80000000U)
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT (31U)
/*! ARBIT_EN - ARBIT_EN */
#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK)
/*! @} */

/*! @name WFE_B_STORE_CTRL_CH1 - Store engine Control Channel 1 Register */
/*! @{ */

#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN_MASK      (0x1U)
#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN_SHIFT     (0U)
/*! CH_EN - CH_EN
 *  0b0..Store function is disable
 *  0b1..Store function is enable
 */
#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CH_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_MASK   (0x2U)
#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_SHIFT  (1U)
/*! BLOCK_EN - BLOCK_EN
 *  0b0..Store in scan mode
 *  0b1..Store in block mode
 */
#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_MASK   (0x4U)
#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_SHIFT  (2U)
/*! BLOCK_16 - BLOCK_16
 *  0b0..BLK_SIZE_8x8 : Block size is 8x8
 *  0b1..BLK_SIZE_16x16 : Block size is 16x16
 */
#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN
 *  0b0..Handshake with the fetch engine is disabled
 *  0b1..Handshake with the fetch engine is enabled
 */
#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_MASK   (0x10U)
#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_SHIFT  (4U)
/*! ARRAY_EN - ARRAY_EN
 *  0b0..Array Handshake Disabled
 *  0b1..Array Handshake Enabled
 */
#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM
 *  0b00..Using 1x1 Array
 *  0b01..Using 3x3 Array
 *  0b10..Using 5x5 Array
 *  0b11..Using 5x5 Array
 */
#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_RSVD3_MASK      (0x80U)
#define PXP_WFE_B_STORE_CTRL_CH1_RSVD3_SHIFT     (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STORE_CTRL_CH1_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_RSVD3_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_RSVD3_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN
 *  0b0..store bypass mode disable.
 *  0b1..store bypass mode enable. Data will bypass to store output.
 */
#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN
 *  0b0..store memory mode disable.
 *  0b1..store memory mode enable. Data will store to memory
 */
#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL
 *  0b0..select 64 shift out data to pack
 *  0b1..select channel 0 high 32 bit shift out data to pack
 */
#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_RSVD1_MASK      (0xF800U)
#define PXP_WFE_B_STORE_CTRL_CH1_RSVD1_SHIFT     (11U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_CTRL_CH1_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_RSVD1_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_RSVD1_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES
 *  0b00..NUM_8_BYTES : 8 bytes
 *  0b01..NUM_16_BYTES : 16 bytes
 *  0b10..NUM_32_BYTES : 32 bytes
 *  0b11..NUM_64_BYTES : 64 bytes
 */
#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_RSVD0_MASK      (0xFFFC0000U)
#define PXP_WFE_B_STORE_CTRL_CH1_RSVD0_SHIFT     (18U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_CTRL_CH1_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_RSVD0_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_CTRL_CH1_SET - Store engine Control Channel 1 Register */
/*! @{ */

#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_MASK  (0x1U)
#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_MASK (0x2U)
#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_MASK (0x4U)
#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD3_MASK  (0x80U)
#define PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD3_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD3_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD1_MASK  (0xF800U)
#define PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD1_SHIFT (11U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD1_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD1_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD0_MASK  (0xFFFC0000U)
#define PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD0_SHIFT (18U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD0_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_CTRL_CH1_CLR - Store engine Control Channel 1 Register */
/*! @{ */

#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_MASK  (0x1U)
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK (0x2U)
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_MASK (0x4U)
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD3_MASK  (0x80U)
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD3_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD1_MASK  (0xF800U)
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD1_SHIFT (11U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD1_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD0_MASK  (0xFFFC0000U)
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD0_SHIFT (18U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_CTRL_CH1_TOG - Store engine Control Channel 1 Register */
/*! @{ */

#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_MASK  (0x1U)
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_SHIFT (0U)
/*! CH_EN - CH_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK (0x2U)
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT (1U)
/*! BLOCK_EN - BLOCK_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_MASK (0x4U)
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT (2U)
/*! BLOCK_16 - BLOCK_16 */
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK (0x8U)
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT (3U)
/*! HANDSHAKE_EN - HANDSHAKE_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT (4U)
/*! ARRAY_EN - ARRAY_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK (0x60U)
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT (5U)
/*! ARRAY_LINE_NUM - ARRAY_LINE_NUM */
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD3_MASK  (0x80U)
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD3_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK (0x100U)
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT (8U)
/*! STORE_BYPASS_EN - STORE_BYPASS_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK (0x200U)
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT (9U)
/*! STORE_MEMORY_EN - STORE_MEMORY_EN */
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK (0x400U)
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT (10U)
/*! PACK_IN_SEL - PACK_IN_SEL */
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD1_MASK  (0xF800U)
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD1_SHIFT (11U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD1_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK (0x30000U)
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT (16U)
/*! WR_NUM_BYTES - WR_NUM_BYTES */
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK)

#define PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD0_MASK  (0xFFFC0000U)
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD0_SHIFT (18U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_STATUS_CH0 - Store engine status Channel 0 Register */
/*! @{ */

#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_MASK (0xFFFFU)
#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT (0U)
/*! STORE_BLOCK_X - STORE_BLOCK_X */
#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_MASK)

#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK (0xFFFF0000U)
#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT (16U)
/*! STORE_BLOCK_Y - STORE_BLOCK_Y */
#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK)
/*! @} */

/*! @name WFE_B_STORE_STATUS_CH1 - Store engine status Channel 1 Register */
/*! @{ */

#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_MASK (0xFFFFU)
#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT (0U)
/*! STORE_BLOCK_X - STORE_BLOCK_X */
#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_MASK)

#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK (0xFFFF0000U)
#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT (16U)
/*! STORE_BLOCK_Y - STORE_BLOCK_Y */
#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK)
/*! @} */

/*! @name WFE_B_STORE_SIZE_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_MASK  (0xFFFFU)
#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_SHIFT (0U)
/*! OUT_WIDTH - OUT_WIDTH */
#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_MASK)

#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_MASK (0xFFFF0000U)
#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT (16U)
/*! OUT_HEIGHT - OUT_HEIGHT */
#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_MASK)
/*! @} */

/*! @name WFE_B_STORE_SIZE_CH1 -  */
/*! @{ */

#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_MASK  (0xFFFFU)
#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_SHIFT (0U)
/*! OUT_WIDTH - OUT_WIDTH */
#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_MASK)

#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_MASK (0xFFFF0000U)
#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT (16U)
/*! OUT_HEIGHT - OUT_HEIGHT */
#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_MASK)
/*! @} */

/*! @name WFE_B_STORE_PITCH -  */
/*! @{ */

#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_MASK (0xFFFFU)
#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_SHIFT (0U)
/*! CH0_OUT_PITCH - CH0_OUT_PITCH */
#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_SHIFT)) & PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_MASK)

#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_MASK (0xFFFF0000U)
#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_SHIFT (16U)
/*! CH1_OUT_PITCH - CH1_OUT_PITCH */
#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_SHIFT)) & PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_MASK)
/*! @} */

/*! @name WFE_B_STORE_SHIFT_CTRL_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2_MASK (0x3U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP
 *  0b00..8 bits
 *  0b01..16 bits
 *  0b10..32 bits
 *  0b11..32 bits
 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1_MASK (0x40U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK (0x80U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS
 *  0b0..data will do shift processing.
 *  0b1..data will bypass shift module.
 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0_MASK (0xFFFFFF00U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_SET -  */
/*! @{ */

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD2_MASK (0x3U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD2_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD2_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD1_MASK (0x40U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD1_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD1_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK (0x80U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD0_MASK (0xFFFFFF00U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD0_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_CLR -  */
/*! @{ */

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_MASK (0x3U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD2_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_MASK (0x40U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD1_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK (0x80U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_MASK (0xFFFFFF00U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_TOG -  */
/*! @{ */

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_MASK (0x3U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD2_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_MASK (0x40U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_SHIFT (6U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD1_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK (0x80U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT (7U)
/*! SHIFT_BYPASS - SHIFT_BYPASS */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_MASK (0xFFFFFF00U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_SHIFT (8U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_SHIFT_CTRL_CH1 -  */
/*! @{ */

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2_MASK (0x3U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP
 *  0b00..8 bits
 *  0b01..16 bits
 *  0b10..32 bits
 *  0b11..32 bits
 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN
 *  0b0..YUYV422 2 plane disabled.
 *  0b1..YUYV422 2 plane enabled.
 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_SET -  */
/*! @{ */

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_RSVD2_MASK (0x3U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_RSVD2_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_RSVD2_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_RSVD0_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_CLR -  */
/*! @{ */

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_MASK (0x3U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_RSVD2_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_TOG -  */
/*! @{ */

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_MASK (0x3U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_SHIFT (0U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_RSVD2_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U)
/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK (0x10U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT (4U)
/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK (0x20U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT (5U)
/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK)

#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_MASK (0xFFFFFFC0U)
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_SHIFT (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_ADDR_0_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT (0U)
/*! OUT_BASE_ADDR0 - OUT_BASE_ADDR0 */
#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT)) & PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK)
/*! @} */

/*! @name WFE_B_STORE_ADDR_1_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT (0U)
/*! OUT_BASE_ADDR1 - OUT_BASE_ADDR1 */
#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT)) & PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK)
/*! @} */

/*! @name WFE_B_STORE_FILL_DATA_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT (0U)
/*! FILL_DATA_CH0 - FILL_DATA_CH0 */
#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT)) & PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_ADDR_0_CH1 -  */
/*! @{ */

#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT (0U)
/*! OUT_BASE_ADDR0 - OUT_BASE_ADDR0 */
#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT)) & PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK)
/*! @} */

/*! @name WFE_B_STORE_ADDR_1_CH1 -  */
/*! @{ */

#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT (0U)
/*! OUT_BASE_ADDR1 - OUT_BASE_ADDR1 */
#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT)) & PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK0_H_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT (0U)
/*! D_MASK0_H_CH0 - D_MASK0_H_CH0 */
#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK0_L_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT (0U)
/*! D_MASK0_L_CH0 - D_MASK0_L_CH0 */
#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK1_H_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT (0U)
/*! D_MASK1_H_CH0 - D_MASK1_H_CH0 */
#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK1_L_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT (0U)
/*! D_MASK1_L_CH0 - D_MASK1_L_CH0 */
#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK2_H_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT (0U)
/*! D_MASK2_H_CH0 - D_MASK2_H_CH0 */
#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK2_L_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT (0U)
/*! D_MASK2_L_CH0 - D_MASK2_L_CH0 */
#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK3_H_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT (0U)
/*! D_MASK3_H_CH0 - D_MASK3_H_CH0 */
#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK3_L_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT (0U)
/*! D_MASK3_L_CH0 - D_MASK3_L_CH0 */
#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK4_H_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT (0U)
/*! D_MASK4_H_CH0 - D_MASK4_H_CH0 */
#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK4_L_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT (0U)
/*! D_MASK4_L_CH0 - D_MASK4_L_CH0 */
#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK5_H_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT (0U)
/*! D_MASK5_H_CH0 - D_MASK5_H_CH0 */
#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK5_L_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT (0U)
/*! D_MASK5_L_CH0 - D_MASK5_L_CH0 */
#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK6_H_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT (0U)
/*! D_MASK6_H_CH0 - D_MASK6_H_CH0 */
#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK6_L_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT (0U)
/*! D_MASK6_L_CH0 - D_MASK6_L_CH0 */
#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK7_H_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT (0U)
/*! D_MASK7_H_CH0 - D_MASK7_H_CH0 */
#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_MASK7_L_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK (0xFFFFFFFFU)
#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT (0U)
/*! D_MASK7_L_CH0 - D_MASK7_L_CH0 */
#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_SHIFT_L_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK (0x3FU)
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT (0U)
/*! D_SHIFT_WIDTH0 - D_SHIFT_WIDTH0 */
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3_MASK (0x40U)
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3_SHIFT (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK (0x80U)
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT (7U)
/*! D_SHIFT_FLAG0 - D_SHIFT_FLAG0 */
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK (0x3F00U)
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT (8U)
/*! D_SHIFT_WIDTH1 - D_SHIFT_WIDTH1 */
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2_MASK (0x4000U)
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK (0x8000U)
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT (15U)
/*! D_SHIFT_FLAG1 - D_SHIFT_FLAG1 */
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK (0x3F0000U)
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT (16U)
/*! D_SHIFT_WIDTH2 - D_SHIFT_WIDTH2 */
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1_MASK (0x400000U)
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1_SHIFT (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK (0x800000U)
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT (23U)
/*! D_SHIFT_FLAG2 - D_SHIFT_FLAG2 */
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK (0x3F000000U)
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT (24U)
/*! D_SHIFT_WIDTH3 - D_SHIFT_WIDTH3 */
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0_MASK (0x40000000U)
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0_SHIFT (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK (0x80000000U)
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT (31U)
/*! D_SHIFT_FLAG3 - D_SHIFT_FLAG3 */
#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK)
/*! @} */

/*! @name WFE_B_STORE_D_SHIFT_H_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK (0x3FU)
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT (0U)
/*! D_SHIFT_WIDTH4 - D_SHIFT_WIDTH4 */
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3_MASK (0x40U)
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3_SHIFT (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK (0x80U)
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT (7U)
/*! D_SHIFT_FLAG4 - D_SHIFT_FLAG4 */
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK (0x3F00U)
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT (8U)
/*! D_SHIFT_WIDTH5 - D_SHIFT_WIDTH5 */
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2_MASK (0x4000U)
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2_SHIFT (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK (0x8000U)
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT (15U)
/*! D_SHIFT_FLAG5 - D_SHIFT_FLAG5 */
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK (0x3F0000U)
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT (16U)
/*! D_SHIFT_WIDTH6 - D_SHIFT_WIDTH6 */
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1_MASK (0x400000U)
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1_SHIFT (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK (0x800000U)
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT (23U)
/*! D_SHIFT_FLAG6 - D_SHIFT_FLAG6 */
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK (0x3F000000U)
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT (24U)
/*! D_SHIFT_WIDTH7 - D_SHIFT_WIDTH7 */
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0_MASK (0x40000000U)
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0_SHIFT (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0_MASK)

#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK (0x80000000U)
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT (31U)
/*! D_SHIFT_FLAG7 - D_SHIFT_FLAG7 */
#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK)
/*! @} */

/*! @name WFE_B_STORE_F_SHIFT_L_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK (0x3FU)
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT (0U)
/*! F_SHIFT_WIDTH0 - F_SHIFT_WIDTH0 */
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK (0x40U)
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT (6U)
/*! F_SHIFT_FLAG0 - F_SHIFT_FLAG0 */
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3_MASK (0x80U)
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK (0x3F00U)
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT (8U)
/*! F_SHIFT_WIDTH1 - F_SHIFT_WIDTH1 */
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK (0x4000U)
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT (14U)
/*! F_SHIFT_FLAG1 - F_SHIFT_FLAG1 */
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2_MASK (0x8000U)
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2_SHIFT (15U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK (0x3F0000U)
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT (16U)
/*! F_SHIFT_WIDTH2 - F_SHIFT_WIDTH2 */
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK (0x400000U)
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT (22U)
/*! F_SHIFT_FLAG2 - F_SHIFT_FLAG2 */
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1_MASK (0x800000U)
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1_SHIFT (23U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK (0x3F000000U)
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT (24U)
/*! F_SHIFT_WIDTH3 - F_SHIFT_WIDTH3 */
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK (0x40000000U)
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT (30U)
/*! F_SHIFT_FLAG3 - F_SHIFT_FLAG3 */
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0_MASK (0x80000000U)
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0_SHIFT (31U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_F_SHIFT_H_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK (0x3FU)
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT (0U)
/*! F_SHIFT_WIDTH4 - F_SHIFT_WIDTH4 */
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK (0x40U)
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT (6U)
/*! F_SHIFT_FLAG4 - F_SHIFT_FLAG4 */
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3_MASK (0x80U)
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3_SHIFT (7U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK (0x3F00U)
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT (8U)
/*! F_SHIFT_WIDTH5 - F_SHIFT_WIDTH5 */
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK (0x4000U)
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT (14U)
/*! F_SHIFT_FLAG5 - F_SHIFT_FLAG5 */
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2_MASK (0x8000U)
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2_SHIFT (15U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK (0x3F0000U)
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT (16U)
/*! F_SHIFT_WIDTH6 - F_SHIFT_WIDTH6 */
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK (0x400000U)
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT (22U)
/*! F_SHIFT_FLAG6 - F_SHIFT_FLAG6 */
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1_MASK (0x800000U)
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1_SHIFT (23U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK (0x3F000000U)
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT (24U)
/*! F_SHIFT_WIDTH7 - F_SHIFT_WIDTH7 */
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK (0x40000000U)
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT (30U)
/*! F_SHIFT_FLAG7 - F_SHIFT_FLAG7 */
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK)

#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0_MASK (0x80000000U)
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0_SHIFT (31U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STORE_F_MASK_L_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_MASK (0xFFU)
#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_SHIFT (0U)
/*! F_MASK0 - F_MASK0 */
#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_MASK)

#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_MASK (0xFF00U)
#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_SHIFT (8U)
/*! F_MASK1 - F_MASK1 */
#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_MASK)

#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_MASK (0xFF0000U)
#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_SHIFT (16U)
/*! F_MASK2 - F_MASK2 */
#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_MASK)

#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_MASK (0xFF000000U)
#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_SHIFT (24U)
/*! F_MASK3 - F_MASK3 */
#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_MASK)
/*! @} */

/*! @name WFE_B_STORE_F_MASK_H_CH0 -  */
/*! @{ */

#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_MASK (0xFFU)
#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_SHIFT (0U)
/*! F_MASK4 - F_MASK4 */
#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_MASK)

#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_MASK (0xFF00U)
#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_SHIFT (8U)
/*! F_MASK5 - F_MASK5 */
#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_MASK)

#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_MASK (0xFF0000U)
#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_SHIFT (16U)
/*! F_MASK6 - F_MASK6 */
#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_MASK)

#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_MASK (0xFF000000U)
#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_SHIFT (24U)
/*! F_MASK7 - F_MASK7 */
#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_MASK)
/*! @} */

/*! @name FETCH_WFE_A_DEBUG -  */
/*! @{ */

#define PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE_MASK   (0xFFFFFFU)
#define PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE_SHIFT  (0U)
/*! DEBUG_VALUE - DEBUG_VALUE */
#define PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE_SHIFT)) & PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE_MASK)

#define PXP_FETCH_WFE_A_DEBUG_ITEM_SEL_MASK      (0xF000000U)
#define PXP_FETCH_WFE_A_DEBUG_ITEM_SEL_SHIFT     (24U)
/*! ITEM_SEL - ITEM_SEL */
#define PXP_FETCH_WFE_A_DEBUG_ITEM_SEL(x)        (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_A_DEBUG_ITEM_SEL_SHIFT)) & PXP_FETCH_WFE_A_DEBUG_ITEM_SEL_MASK)

#define PXP_FETCH_WFE_A_DEBUG_BUF_SEL_MASK       (0x10000000U)
#define PXP_FETCH_WFE_A_DEBUG_BUF_SEL_SHIFT      (28U)
/*! BUF_SEL - BUF_SEL
 *  0b0..BF0 : Buffer 0 select
 *  0b1..BF1 : Buffer 1 select
 */
#define PXP_FETCH_WFE_A_DEBUG_BUF_SEL(x)         (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_A_DEBUG_BUF_SEL_SHIFT)) & PXP_FETCH_WFE_A_DEBUG_BUF_SEL_MASK)

#define PXP_FETCH_WFE_A_DEBUG_RSVD_MASK          (0xE0000000U)
#define PXP_FETCH_WFE_A_DEBUG_RSVD_SHIFT         (29U)
/*! RSVD - RSVD */
#define PXP_FETCH_WFE_A_DEBUG_RSVD(x)            (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_A_DEBUG_RSVD_SHIFT)) & PXP_FETCH_WFE_A_DEBUG_RSVD_MASK)
/*! @} */

/*! @name FETCH_WFE_B_DEBUG -  */
/*! @{ */

#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_MASK   (0xFFFFFFU)
#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_SHIFT  (0U)
/*! DEBUG_VALUE - DEBUG_VALUE */
#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_MASK)

#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_MASK      (0xF000000U)
#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_SHIFT     (24U)
/*! ITEM_SEL - ITEM_SEL */
#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL(x)        (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_MASK)

#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL_MASK       (0x10000000U)
#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL_SHIFT      (28U)
/*! BUF_SEL - BUF_SEL
 *  0b0..BF0 : Buffer 0 select
 *  0b1..BF1 : Buffer 1 select
 */
#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL(x)         (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_BUF_SEL_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_BUF_SEL_MASK)

#define PXP_FETCH_WFE_B_DEBUG_RSVD_MASK          (0xE0000000U)
#define PXP_FETCH_WFE_B_DEBUG_RSVD_SHIFT         (29U)
/*! RSVD - RSVD */
#define PXP_FETCH_WFE_B_DEBUG_RSVD(x)            (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_RSVD_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_RSVD_MASK)
/*! @} */

/*! @name DITHER_CTRL - Dither Control Register 0 */
/*! @{ */

#define PXP_DITHER_CTRL_ENABLE0_MASK             (0x1U)
#define PXP_DITHER_CTRL_ENABLE0_SHIFT            (0U)
/*! ENABLE0 - ENABLE0
 *  0b0..Disabled : The dither engine 0 will not process any frames.
 *  0b1..Enabled : The dither engine 0 is on and ready for processing
 */
#define PXP_DITHER_CTRL_ENABLE0(x)               (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_ENABLE0_MASK)

#define PXP_DITHER_CTRL_ENABLE1_MASK             (0x2U)
#define PXP_DITHER_CTRL_ENABLE1_SHIFT            (1U)
/*! ENABLE1 - ENABLE1
 *  0b0..Disabled : The dither engine 1 will not process any frames.
 *  0b1..Enabled : The dither engine 1 is on and ready for processing
 */
#define PXP_DITHER_CTRL_ENABLE1(x)               (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_ENABLE1_MASK)

#define PXP_DITHER_CTRL_ENABLE2_MASK             (0x4U)
#define PXP_DITHER_CTRL_ENABLE2_SHIFT            (2U)
/*! ENABLE2 - ENABLE2
 *  0b0..Disabled : The dither engine 2 will not process any frames.
 *  0b1..Enabled : The dither engine 2 is on and ready for processing
 */
#define PXP_DITHER_CTRL_ENABLE2(x)               (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_ENABLE2_MASK)

#define PXP_DITHER_CTRL_DITHER_MODE0_MASK        (0x38U)
#define PXP_DITHER_CTRL_DITHER_MODE0_SHIFT       (3U)
/*! DITHER_MODE0 - DITHER_MODE0
 *  0b000..Pass through.
 *  0b001..Floyd-Steinberg.
 *  0b010..Atkinson.
 *  0b011..Ordered.
 *  0b100..No Dithering, quantization only.
 *  0b101..Sierra
 *  0b110..Reserved.
 *  0b111..Reserved.
 */
#define PXP_DITHER_CTRL_DITHER_MODE0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE0_MASK)

#define PXP_DITHER_CTRL_DITHER_MODE1_MASK        (0x1C0U)
#define PXP_DITHER_CTRL_DITHER_MODE1_SHIFT       (6U)
/*! DITHER_MODE1 - DITHER_MODE1
 *  0b000..Pass through.
 *  0b001..Reserved.
 *  0b010..Reserved
 *  0b011..Ordered.
 *  0b100..No Dithering, quantization only.
 *  0b101..Reserved.
 *  0b110..Reserved.
 *  0b111..Reserved.
 */
#define PXP_DITHER_CTRL_DITHER_MODE1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE1_MASK)

#define PXP_DITHER_CTRL_DITHER_MODE2_MASK        (0xE00U)
#define PXP_DITHER_CTRL_DITHER_MODE2_SHIFT       (9U)
/*! DITHER_MODE2 - DITHER_MODE2
 *  0b000..Pass through.
 *  0b001..Reserved.
 *  0b010..Reserved.
 *  0b011..Ordered.
 *  0b100..No Dithering, quantization only.
 *  0b101..Reserved.
 *  0b110..Reserved.
 *  0b111..Reserved.
 */
#define PXP_DITHER_CTRL_DITHER_MODE2(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE2_MASK)

#define PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK       (0x7000U)
#define PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT      (12U)
/*! NUM_QUANT_BIT - NUM_QUANT_BIT
 *  0b000..Reserved.
 *  0b001..Quantize down to 1 bit.
 *  0b010..Quantize down to 2 bits.
 *  0b011..Quantize down to 3 bits.
 *  0b100..Quantize down to 4 bits.
 *  0b101..Quantize down to 5 bits.
 *  0b110..Quantize down to 6 bits.
 *  0b111..Quantize down to 7 bits.
 */
#define PXP_DITHER_CTRL_NUM_QUANT_BIT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK)

#define PXP_DITHER_CTRL_LUT_MODE_MASK            (0x18000U)
#define PXP_DITHER_CTRL_LUT_MODE_SHIFT           (15U)
/*! LUT_MODE - LUT_MODE
 *  0b00..LUT mode off.
 *  0b01..Use LUT at pre-diter stage.
 *  0b10..Use LUT at post-dither stage.
 *  0b11..Reserved`
 */
#define PXP_DITHER_CTRL_LUT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_LUT_MODE_MASK)

#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK    (0x60000U)
#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT   (17U)
/*! IDX_MATRIX0_SIZE - IDX_MATRIX0_SIZE
 *  0b00..4x4
 *  0b01..8x8
 *  0b10..16x16
 *  0b11..Input value of index
 */
#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK)

#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK    (0x180000U)
#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT   (19U)
/*! IDX_MATRIX1_SIZE - IDX_MATRIX1_SIZE
 *  0b00..4x4
 *  0b01..8x8
 *  0b10..16x16
 *  0b11..Input value of index
 */
#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK)

#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK    (0x600000U)
#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT   (21U)
/*! IDX_MATRIX2_SIZE - IDX_MATRIX2_SIZE
 *  0b00..4x4
 *  0b01..8x8
 *  0b10..16x16
 *  0b11..Input value of index
 */
#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK)

#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE_MASK    (0x800000U)
#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE_SHIFT   (23U)
/*! FINAL_LUT_ENABLE - FINAL_LUT_ENABLE
 *  0b0..Disabled : The dither engine 2 will not process any frames.
 *  0b1..Enabled : The dither engine 2 is on and ready for processing
 */
#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_FINAL_LUT_ENABLE_MASK)

#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE_MASK  (0x1000000U)
#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE_SHIFT (24U)
/*! ORDERED_ROUND_MODE - ORDERED_ROUND_MODE
 *  0b0..Use truncation method.
 *  0b1..Use rounding method.
 */
#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_ORDERED_ROUND_MODE_MASK)

#define PXP_DITHER_CTRL_RSVD0_MASK               (0x1E000000U)
#define PXP_DITHER_CTRL_RSVD0_SHIFT              (25U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_CTRL_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_RSVD0_SHIFT)) & PXP_DITHER_CTRL_RSVD0_MASK)

#define PXP_DITHER_CTRL_BUSY2_MASK               (0x20000000U)
#define PXP_DITHER_CTRL_BUSY2_SHIFT              (29U)
/*! BUSY2 - BUSY2 */
#define PXP_DITHER_CTRL_BUSY2(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY2_SHIFT)) & PXP_DITHER_CTRL_BUSY2_MASK)

#define PXP_DITHER_CTRL_BUSY1_MASK               (0x40000000U)
#define PXP_DITHER_CTRL_BUSY1_SHIFT              (30U)
/*! BUSY1 - BUSY1 */
#define PXP_DITHER_CTRL_BUSY1(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY1_SHIFT)) & PXP_DITHER_CTRL_BUSY1_MASK)

#define PXP_DITHER_CTRL_BUSY0_MASK               (0x80000000U)
#define PXP_DITHER_CTRL_BUSY0_SHIFT              (31U)
/*! BUSY0 - BUSY0 */
#define PXP_DITHER_CTRL_BUSY0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY0_SHIFT)) & PXP_DITHER_CTRL_BUSY0_MASK)
/*! @} */

/*! @name DITHER_CTRL_SET - Dither Control Register 0 */
/*! @{ */

#define PXP_DITHER_CTRL_SET_ENABLE0_MASK         (0x1U)
#define PXP_DITHER_CTRL_SET_ENABLE0_SHIFT        (0U)
/*! ENABLE0 - ENABLE0 */
#define PXP_DITHER_CTRL_SET_ENABLE0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE0_MASK)

#define PXP_DITHER_CTRL_SET_ENABLE1_MASK         (0x2U)
#define PXP_DITHER_CTRL_SET_ENABLE1_SHIFT        (1U)
/*! ENABLE1 - ENABLE1 */
#define PXP_DITHER_CTRL_SET_ENABLE1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE1_MASK)

#define PXP_DITHER_CTRL_SET_ENABLE2_MASK         (0x4U)
#define PXP_DITHER_CTRL_SET_ENABLE2_SHIFT        (2U)
/*! ENABLE2 - ENABLE2 */
#define PXP_DITHER_CTRL_SET_ENABLE2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE2_MASK)

#define PXP_DITHER_CTRL_SET_DITHER_MODE0_MASK    (0x38U)
#define PXP_DITHER_CTRL_SET_DITHER_MODE0_SHIFT   (3U)
/*! DITHER_MODE0 - DITHER_MODE0 */
#define PXP_DITHER_CTRL_SET_DITHER_MODE0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE0_MASK)

#define PXP_DITHER_CTRL_SET_DITHER_MODE1_MASK    (0x1C0U)
#define PXP_DITHER_CTRL_SET_DITHER_MODE1_SHIFT   (6U)
/*! DITHER_MODE1 - DITHER_MODE1 */
#define PXP_DITHER_CTRL_SET_DITHER_MODE1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE1_MASK)

#define PXP_DITHER_CTRL_SET_DITHER_MODE2_MASK    (0xE00U)
#define PXP_DITHER_CTRL_SET_DITHER_MODE2_SHIFT   (9U)
/*! DITHER_MODE2 - DITHER_MODE2 */
#define PXP_DITHER_CTRL_SET_DITHER_MODE2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE2_MASK)

#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_MASK   (0x7000U)
#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_SHIFT  (12U)
/*! NUM_QUANT_BIT - NUM_QUANT_BIT */
#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_MASK)

#define PXP_DITHER_CTRL_SET_LUT_MODE_MASK        (0x18000U)
#define PXP_DITHER_CTRL_SET_LUT_MODE_SHIFT       (15U)
/*! LUT_MODE - LUT_MODE */
#define PXP_DITHER_CTRL_SET_LUT_MODE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_SET_LUT_MODE_MASK)

#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_MASK (0x60000U)
#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_SHIFT (17U)
/*! IDX_MATRIX0_SIZE - IDX_MATRIX0_SIZE */
#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_MASK)

#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_MASK (0x180000U)
#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_SHIFT (19U)
/*! IDX_MATRIX1_SIZE - IDX_MATRIX1_SIZE */
#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_MASK)

#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_MASK (0x600000U)
#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_SHIFT (21U)
/*! IDX_MATRIX2_SIZE - IDX_MATRIX2_SIZE */
#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_MASK)

#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_MASK (0x800000U)
#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_SHIFT (23U)
/*! FINAL_LUT_ENABLE - FINAL_LUT_ENABLE */
#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_MASK)

#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_MASK (0x1000000U)
#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_SHIFT (24U)
/*! ORDERED_ROUND_MODE - ORDERED_ROUND_MODE */
#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_MASK)

#define PXP_DITHER_CTRL_SET_RSVD0_MASK           (0x1E000000U)
#define PXP_DITHER_CTRL_SET_RSVD0_SHIFT          (25U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_CTRL_SET_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_RSVD0_SHIFT)) & PXP_DITHER_CTRL_SET_RSVD0_MASK)

#define PXP_DITHER_CTRL_SET_BUSY2_MASK           (0x20000000U)
#define PXP_DITHER_CTRL_SET_BUSY2_SHIFT          (29U)
/*! BUSY2 - BUSY2 */
#define PXP_DITHER_CTRL_SET_BUSY2(x)             (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY2_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY2_MASK)

#define PXP_DITHER_CTRL_SET_BUSY1_MASK           (0x40000000U)
#define PXP_DITHER_CTRL_SET_BUSY1_SHIFT          (30U)
/*! BUSY1 - BUSY1 */
#define PXP_DITHER_CTRL_SET_BUSY1(x)             (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY1_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY1_MASK)

#define PXP_DITHER_CTRL_SET_BUSY0_MASK           (0x80000000U)
#define PXP_DITHER_CTRL_SET_BUSY0_SHIFT          (31U)
/*! BUSY0 - BUSY0 */
#define PXP_DITHER_CTRL_SET_BUSY0(x)             (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY0_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY0_MASK)
/*! @} */

/*! @name DITHER_CTRL_CLR - Dither Control Register 0 */
/*! @{ */

#define PXP_DITHER_CTRL_CLR_ENABLE0_MASK         (0x1U)
#define PXP_DITHER_CTRL_CLR_ENABLE0_SHIFT        (0U)
/*! ENABLE0 - ENABLE0 */
#define PXP_DITHER_CTRL_CLR_ENABLE0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE0_MASK)

#define PXP_DITHER_CTRL_CLR_ENABLE1_MASK         (0x2U)
#define PXP_DITHER_CTRL_CLR_ENABLE1_SHIFT        (1U)
/*! ENABLE1 - ENABLE1 */
#define PXP_DITHER_CTRL_CLR_ENABLE1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE1_MASK)

#define PXP_DITHER_CTRL_CLR_ENABLE2_MASK         (0x4U)
#define PXP_DITHER_CTRL_CLR_ENABLE2_SHIFT        (2U)
/*! ENABLE2 - ENABLE2 */
#define PXP_DITHER_CTRL_CLR_ENABLE2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE2_MASK)

#define PXP_DITHER_CTRL_CLR_DITHER_MODE0_MASK    (0x38U)
#define PXP_DITHER_CTRL_CLR_DITHER_MODE0_SHIFT   (3U)
/*! DITHER_MODE0 - DITHER_MODE0 */
#define PXP_DITHER_CTRL_CLR_DITHER_MODE0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE0_MASK)

#define PXP_DITHER_CTRL_CLR_DITHER_MODE1_MASK    (0x1C0U)
#define PXP_DITHER_CTRL_CLR_DITHER_MODE1_SHIFT   (6U)
/*! DITHER_MODE1 - DITHER_MODE1 */
#define PXP_DITHER_CTRL_CLR_DITHER_MODE1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE1_MASK)

#define PXP_DITHER_CTRL_CLR_DITHER_MODE2_MASK    (0xE00U)
#define PXP_DITHER_CTRL_CLR_DITHER_MODE2_SHIFT   (9U)
/*! DITHER_MODE2 - DITHER_MODE2 */
#define PXP_DITHER_CTRL_CLR_DITHER_MODE2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE2_MASK)

#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_MASK   (0x7000U)
#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_SHIFT  (12U)
/*! NUM_QUANT_BIT - NUM_QUANT_BIT */
#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_MASK)

#define PXP_DITHER_CTRL_CLR_LUT_MODE_MASK        (0x18000U)
#define PXP_DITHER_CTRL_CLR_LUT_MODE_SHIFT       (15U)
/*! LUT_MODE - LUT_MODE */
#define PXP_DITHER_CTRL_CLR_LUT_MODE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_CLR_LUT_MODE_MASK)

#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_MASK (0x60000U)
#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_SHIFT (17U)
/*! IDX_MATRIX0_SIZE - IDX_MATRIX0_SIZE */
#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_MASK)

#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_MASK (0x180000U)
#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_SHIFT (19U)
/*! IDX_MATRIX1_SIZE - IDX_MATRIX1_SIZE */
#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_MASK)

#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_MASK (0x600000U)
#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_SHIFT (21U)
/*! IDX_MATRIX2_SIZE - IDX_MATRIX2_SIZE */
#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_MASK)

#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_MASK (0x800000U)
#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_SHIFT (23U)
/*! FINAL_LUT_ENABLE - FINAL_LUT_ENABLE */
#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_MASK)

#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_MASK (0x1000000U)
#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_SHIFT (24U)
/*! ORDERED_ROUND_MODE - ORDERED_ROUND_MODE */
#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_MASK)

#define PXP_DITHER_CTRL_CLR_RSVD0_MASK           (0x1E000000U)
#define PXP_DITHER_CTRL_CLR_RSVD0_SHIFT          (25U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_CTRL_CLR_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_RSVD0_SHIFT)) & PXP_DITHER_CTRL_CLR_RSVD0_MASK)

#define PXP_DITHER_CTRL_CLR_BUSY2_MASK           (0x20000000U)
#define PXP_DITHER_CTRL_CLR_BUSY2_SHIFT          (29U)
/*! BUSY2 - BUSY2 */
#define PXP_DITHER_CTRL_CLR_BUSY2(x)             (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY2_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY2_MASK)

#define PXP_DITHER_CTRL_CLR_BUSY1_MASK           (0x40000000U)
#define PXP_DITHER_CTRL_CLR_BUSY1_SHIFT          (30U)
/*! BUSY1 - BUSY1 */
#define PXP_DITHER_CTRL_CLR_BUSY1(x)             (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY1_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY1_MASK)

#define PXP_DITHER_CTRL_CLR_BUSY0_MASK           (0x80000000U)
#define PXP_DITHER_CTRL_CLR_BUSY0_SHIFT          (31U)
/*! BUSY0 - BUSY0 */
#define PXP_DITHER_CTRL_CLR_BUSY0(x)             (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY0_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY0_MASK)
/*! @} */

/*! @name DITHER_CTRL_TOG - Dither Control Register 0 */
/*! @{ */

#define PXP_DITHER_CTRL_TOG_ENABLE0_MASK         (0x1U)
#define PXP_DITHER_CTRL_TOG_ENABLE0_SHIFT        (0U)
/*! ENABLE0 - ENABLE0 */
#define PXP_DITHER_CTRL_TOG_ENABLE0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE0_MASK)

#define PXP_DITHER_CTRL_TOG_ENABLE1_MASK         (0x2U)
#define PXP_DITHER_CTRL_TOG_ENABLE1_SHIFT        (1U)
/*! ENABLE1 - ENABLE1 */
#define PXP_DITHER_CTRL_TOG_ENABLE1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE1_MASK)

#define PXP_DITHER_CTRL_TOG_ENABLE2_MASK         (0x4U)
#define PXP_DITHER_CTRL_TOG_ENABLE2_SHIFT        (2U)
/*! ENABLE2 - ENABLE2 */
#define PXP_DITHER_CTRL_TOG_ENABLE2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE2_MASK)

#define PXP_DITHER_CTRL_TOG_DITHER_MODE0_MASK    (0x38U)
#define PXP_DITHER_CTRL_TOG_DITHER_MODE0_SHIFT   (3U)
/*! DITHER_MODE0 - DITHER_MODE0 */
#define PXP_DITHER_CTRL_TOG_DITHER_MODE0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE0_MASK)

#define PXP_DITHER_CTRL_TOG_DITHER_MODE1_MASK    (0x1C0U)
#define PXP_DITHER_CTRL_TOG_DITHER_MODE1_SHIFT   (6U)
/*! DITHER_MODE1 - DITHER_MODE1 */
#define PXP_DITHER_CTRL_TOG_DITHER_MODE1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE1_MASK)

#define PXP_DITHER_CTRL_TOG_DITHER_MODE2_MASK    (0xE00U)
#define PXP_DITHER_CTRL_TOG_DITHER_MODE2_SHIFT   (9U)
/*! DITHER_MODE2 - DITHER_MODE2 */
#define PXP_DITHER_CTRL_TOG_DITHER_MODE2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE2_MASK)

#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_MASK   (0x7000U)
#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_SHIFT  (12U)
/*! NUM_QUANT_BIT - NUM_QUANT_BIT */
#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_MASK)

#define PXP_DITHER_CTRL_TOG_LUT_MODE_MASK        (0x18000U)
#define PXP_DITHER_CTRL_TOG_LUT_MODE_SHIFT       (15U)
/*! LUT_MODE - LUT_MODE */
#define PXP_DITHER_CTRL_TOG_LUT_MODE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_TOG_LUT_MODE_MASK)

#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_MASK (0x60000U)
#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_SHIFT (17U)
/*! IDX_MATRIX0_SIZE - IDX_MATRIX0_SIZE */
#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_MASK)

#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_MASK (0x180000U)
#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_SHIFT (19U)
/*! IDX_MATRIX1_SIZE - IDX_MATRIX1_SIZE */
#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_MASK)

#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_MASK (0x600000U)
#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_SHIFT (21U)
/*! IDX_MATRIX2_SIZE - IDX_MATRIX2_SIZE */
#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_MASK)

#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_MASK (0x800000U)
#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_SHIFT (23U)
/*! FINAL_LUT_ENABLE - FINAL_LUT_ENABLE */
#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_MASK)

#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_MASK (0x1000000U)
#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_SHIFT (24U)
/*! ORDERED_ROUND_MODE - ORDERED_ROUND_MODE */
#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_MASK)

#define PXP_DITHER_CTRL_TOG_RSVD0_MASK           (0x1E000000U)
#define PXP_DITHER_CTRL_TOG_RSVD0_SHIFT          (25U)
/*! RSVD0 - RSVD0 */
#define PXP_DITHER_CTRL_TOG_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_RSVD0_SHIFT)) & PXP_DITHER_CTRL_TOG_RSVD0_MASK)

#define PXP_DITHER_CTRL_TOG_BUSY2_MASK           (0x20000000U)
#define PXP_DITHER_CTRL_TOG_BUSY2_SHIFT          (29U)
/*! BUSY2 - BUSY2 */
#define PXP_DITHER_CTRL_TOG_BUSY2(x)             (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY2_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY2_MASK)

#define PXP_DITHER_CTRL_TOG_BUSY1_MASK           (0x40000000U)
#define PXP_DITHER_CTRL_TOG_BUSY1_SHIFT          (30U)
/*! BUSY1 - BUSY1 */
#define PXP_DITHER_CTRL_TOG_BUSY1(x)             (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY1_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY1_MASK)

#define PXP_DITHER_CTRL_TOG_BUSY0_MASK           (0x80000000U)
#define PXP_DITHER_CTRL_TOG_BUSY0_SHIFT          (31U)
/*! BUSY0 - BUSY0 */
#define PXP_DITHER_CTRL_TOG_BUSY0(x)             (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY0_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY0_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA0 - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK    (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT   (0U)
/*! DATA0 - DATA0 */
#define PXP_DITHER_FINAL_LUT_DATA0_DATA0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK)

#define PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK    (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT   (8U)
/*! DATA1 - DATA1 */
#define PXP_DITHER_FINAL_LUT_DATA0_DATA1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK)

#define PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK    (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT   (16U)
/*! DATA2 - DATA2 */
#define PXP_DITHER_FINAL_LUT_DATA0_DATA2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK)

#define PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK    (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT   (24U)
/*! DATA3 - DATA3 */
#define PXP_DITHER_FINAL_LUT_DATA0_DATA3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA0_SET - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_MASK (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_SHIFT (0U)
/*! DATA0 - DATA0 */
#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_MASK)

#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_MASK (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_SHIFT (8U)
/*! DATA1 - DATA1 */
#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_MASK)

#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_MASK (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_SHIFT (16U)
/*! DATA2 - DATA2 */
#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_MASK)

#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_MASK (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_SHIFT (24U)
/*! DATA3 - DATA3 */
#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA0_CLR - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_MASK (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_SHIFT (0U)
/*! DATA0 - DATA0 */
#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_MASK)

#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_MASK (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_SHIFT (8U)
/*! DATA1 - DATA1 */
#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_MASK)

#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_MASK (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_SHIFT (16U)
/*! DATA2 - DATA2 */
#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_MASK)

#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_MASK (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_SHIFT (24U)
/*! DATA3 - DATA3 */
#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA0_TOG - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_MASK (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_SHIFT (0U)
/*! DATA0 - DATA0 */
#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_MASK)

#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_MASK (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_SHIFT (8U)
/*! DATA1 - DATA1 */
#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_MASK)

#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_MASK (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_SHIFT (16U)
/*! DATA2 - DATA2 */
#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_MASK)

#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_MASK (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_SHIFT (24U)
/*! DATA3 - DATA3 */
#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA1 - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK    (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT   (0U)
/*! DATA4 - DATA4 */
#define PXP_DITHER_FINAL_LUT_DATA1_DATA4(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK)

#define PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK    (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT   (8U)
/*! DATA5 - DATA5 */
#define PXP_DITHER_FINAL_LUT_DATA1_DATA5(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK)

#define PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK    (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT   (16U)
/*! DATA6 - DATA6 */
#define PXP_DITHER_FINAL_LUT_DATA1_DATA6(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK)

#define PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK    (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT   (24U)
/*! DATA7 - DATA7 */
#define PXP_DITHER_FINAL_LUT_DATA1_DATA7(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA1_SET - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_MASK (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_SHIFT (0U)
/*! DATA4 - DATA4 */
#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_MASK)

#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_MASK (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_SHIFT (8U)
/*! DATA5 - DATA5 */
#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_MASK)

#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_MASK (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_SHIFT (16U)
/*! DATA6 - DATA6 */
#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_MASK)

#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_MASK (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_SHIFT (24U)
/*! DATA7 - DATA7 */
#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA1_CLR - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_MASK (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_SHIFT (0U)
/*! DATA4 - DATA4 */
#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_MASK)

#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_MASK (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_SHIFT (8U)
/*! DATA5 - DATA5 */
#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_MASK)

#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_MASK (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_SHIFT (16U)
/*! DATA6 - DATA6 */
#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_MASK)

#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_MASK (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_SHIFT (24U)
/*! DATA7 - DATA7 */
#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA1_TOG - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_MASK (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_SHIFT (0U)
/*! DATA4 - DATA4 */
#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_MASK)

#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_MASK (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_SHIFT (8U)
/*! DATA5 - DATA5 */
#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_MASK)

#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_MASK (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_SHIFT (16U)
/*! DATA6 - DATA6 */
#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_MASK)

#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_MASK (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_SHIFT (24U)
/*! DATA7 - DATA7 */
#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA2 - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK    (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT   (0U)
/*! DATA8 - DATA8 */
#define PXP_DITHER_FINAL_LUT_DATA2_DATA8(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK)

#define PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK    (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT   (8U)
/*! DATA9 - DATA9 */
#define PXP_DITHER_FINAL_LUT_DATA2_DATA9(x)      (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK)

#define PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK   (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT  (16U)
/*! DATA10 - DATA10 */
#define PXP_DITHER_FINAL_LUT_DATA2_DATA10(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK)

#define PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK   (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT  (24U)
/*! DATA11 - DATA11 */
#define PXP_DITHER_FINAL_LUT_DATA2_DATA11(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA2_SET - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_MASK (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_SHIFT (0U)
/*! DATA8 - DATA8 */
#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_MASK)

#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_MASK (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_SHIFT (8U)
/*! DATA9 - DATA9 */
#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_MASK)

#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_MASK (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_SHIFT (16U)
/*! DATA10 - DATA10 */
#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_MASK)

#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_MASK (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_SHIFT (24U)
/*! DATA11 - DATA11 */
#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA2_CLR - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_MASK (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_SHIFT (0U)
/*! DATA8 - DATA8 */
#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_MASK)

#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_MASK (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_SHIFT (8U)
/*! DATA9 - DATA9 */
#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_MASK)

#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_MASK (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_SHIFT (16U)
/*! DATA10 - DATA10 */
#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_MASK)

#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_MASK (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_SHIFT (24U)
/*! DATA11 - DATA11 */
#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA2_TOG - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_MASK (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_SHIFT (0U)
/*! DATA8 - DATA8 */
#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_MASK)

#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_MASK (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_SHIFT (8U)
/*! DATA9 - DATA9 */
#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9(x)  (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_MASK)

#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_MASK (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_SHIFT (16U)
/*! DATA10 - DATA10 */
#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_MASK)

#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_MASK (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_SHIFT (24U)
/*! DATA11 - DATA11 */
#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA3 - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK   (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT  (0U)
/*! DATA12 - DATA12 */
#define PXP_DITHER_FINAL_LUT_DATA3_DATA12(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK)

#define PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK   (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT  (8U)
/*! DATA13 - DATA13 */
#define PXP_DITHER_FINAL_LUT_DATA3_DATA13(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK)

#define PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK   (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT  (16U)
/*! DATA14 - DATA14 */
#define PXP_DITHER_FINAL_LUT_DATA3_DATA14(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK)

#define PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK   (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT  (24U)
/*! DATA15 - DATA15 */
#define PXP_DITHER_FINAL_LUT_DATA3_DATA15(x)     (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA3_SET - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_MASK (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_SHIFT (0U)
/*! DATA12 - DATA12 */
#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_MASK)

#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_MASK (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_SHIFT (8U)
/*! DATA13 - DATA13 */
#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_MASK)

#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_MASK (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_SHIFT (16U)
/*! DATA14 - DATA14 */
#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_MASK)

#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_MASK (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_SHIFT (24U)
/*! DATA15 - DATA15 */
#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA3_CLR - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_MASK (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_SHIFT (0U)
/*! DATA12 - DATA12 */
#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_MASK)

#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_MASK (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_SHIFT (8U)
/*! DATA13 - DATA13 */
#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_MASK)

#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_MASK (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_SHIFT (16U)
/*! DATA14 - DATA14 */
#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_MASK)

#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_MASK (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_SHIFT (24U)
/*! DATA15 - DATA15 */
#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_MASK)
/*! @} */

/*! @name DITHER_FINAL_LUT_DATA3_TOG - Final stage lookup value Register */
/*! @{ */

#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_MASK (0xFFU)
#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_SHIFT (0U)
/*! DATA12 - DATA12 */
#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_MASK)

#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_MASK (0xFF00U)
#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_SHIFT (8U)
/*! DATA13 - DATA13 */
#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_MASK)

#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_MASK (0xFF0000U)
#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_SHIFT (16U)
/*! DATA14 - DATA14 */
#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_MASK)

#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_MASK (0xFF000000U)
#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_SHIFT (24U)
/*! DATA15 - DATA15 */
#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_MASK)
/*! @} */

/*! @name WFE_A_CTRL -  */
/*! @{ */

#define PXP_WFE_A_CTRL_ENABLE_MASK               (0x1U)
#define PXP_WFE_A_CTRL_ENABLE_SHIFT              (0U)
/*! ENABLE - ENABLE
 *  0b0..Disabled, the WFE A sub-block will not process any frames
 *  0b1..The WFE A sub-block is on and ready for processing.
 */
#define PXP_WFE_A_CTRL_ENABLE(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_ENABLE_SHIFT)) & PXP_WFE_A_CTRL_ENABLE_MASK)

#define PXP_WFE_A_CTRL_RSVD1_MASK                (0x2U)
#define PXP_WFE_A_CTRL_RSVD1_SHIFT               (1U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_CTRL_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_RSVD1_SHIFT)) & PXP_WFE_A_CTRL_RSVD1_MASK)

#define PXP_WFE_A_CTRL_SW_RESET_MASK             (0x4U)
#define PXP_WFE_A_CTRL_SW_RESET_SHIFT            (2U)
/*! SW_RESET - SW_RESET */
#define PXP_WFE_A_CTRL_SW_RESET(x)               (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_SW_RESET_SHIFT)) & PXP_WFE_A_CTRL_SW_RESET_MASK)

#define PXP_WFE_A_CTRL_ALU_REGISTER_ENABLE_MASK  (0x8U)
#define PXP_WFE_A_CTRL_ALU_REGISTER_ENABLE_SHIFT (3U)
/*! ALU_REGISTER_ENABLE - ALU_REGISTER_ENABLE
 *  0b0..Disabled, the WFE will use the output of alu inside directly.
 *  0b1..Enable, the WFE will use the register output of alu inside.
 */
#define PXP_WFE_A_CTRL_ALU_REGISTER_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_ALU_REGISTER_ENABLE_SHIFT)) & PXP_WFE_A_CTRL_ALU_REGISTER_ENABLE_MASK)

#define PXP_WFE_A_CTRL_RSVD0_MASK                (0x7FFFFFF0U)
#define PXP_WFE_A_CTRL_RSVD0_SHIFT               (4U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_CTRL_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_RSVD0_SHIFT)) & PXP_WFE_A_CTRL_RSVD0_MASK)

#define PXP_WFE_A_CTRL_DONE_MASK                 (0x80000000U)
#define PXP_WFE_A_CTRL_DONE_SHIFT                (31U)
/*! DONE - DONE */
#define PXP_WFE_A_CTRL_DONE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_DONE_SHIFT)) & PXP_WFE_A_CTRL_DONE_MASK)
/*! @} */

/*! @name WFE_A_CTRL_SET -  */
/*! @{ */

#define PXP_WFE_A_CTRL_SET_ENABLE_MASK           (0x1U)
#define PXP_WFE_A_CTRL_SET_ENABLE_SHIFT          (0U)
/*! ENABLE - ENABLE */
#define PXP_WFE_A_CTRL_SET_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_SET_ENABLE_SHIFT)) & PXP_WFE_A_CTRL_SET_ENABLE_MASK)

#define PXP_WFE_A_CTRL_SET_RSVD1_MASK            (0x2U)
#define PXP_WFE_A_CTRL_SET_RSVD1_SHIFT           (1U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_CTRL_SET_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_SET_RSVD1_SHIFT)) & PXP_WFE_A_CTRL_SET_RSVD1_MASK)

#define PXP_WFE_A_CTRL_SET_SW_RESET_MASK         (0x4U)
#define PXP_WFE_A_CTRL_SET_SW_RESET_SHIFT        (2U)
/*! SW_RESET - SW_RESET */
#define PXP_WFE_A_CTRL_SET_SW_RESET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_SET_SW_RESET_SHIFT)) & PXP_WFE_A_CTRL_SET_SW_RESET_MASK)

#define PXP_WFE_A_CTRL_SET_ALU_REGISTER_ENABLE_MASK (0x8U)
#define PXP_WFE_A_CTRL_SET_ALU_REGISTER_ENABLE_SHIFT (3U)
/*! ALU_REGISTER_ENABLE - ALU_REGISTER_ENABLE */
#define PXP_WFE_A_CTRL_SET_ALU_REGISTER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_SET_ALU_REGISTER_ENABLE_SHIFT)) & PXP_WFE_A_CTRL_SET_ALU_REGISTER_ENABLE_MASK)

#define PXP_WFE_A_CTRL_SET_RSVD0_MASK            (0x7FFFFFF0U)
#define PXP_WFE_A_CTRL_SET_RSVD0_SHIFT           (4U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_CTRL_SET_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_SET_RSVD0_SHIFT)) & PXP_WFE_A_CTRL_SET_RSVD0_MASK)

#define PXP_WFE_A_CTRL_SET_DONE_MASK             (0x80000000U)
#define PXP_WFE_A_CTRL_SET_DONE_SHIFT            (31U)
/*! DONE - DONE */
#define PXP_WFE_A_CTRL_SET_DONE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_SET_DONE_SHIFT)) & PXP_WFE_A_CTRL_SET_DONE_MASK)
/*! @} */

/*! @name WFE_A_CTRL_CLR -  */
/*! @{ */

#define PXP_WFE_A_CTRL_CLR_ENABLE_MASK           (0x1U)
#define PXP_WFE_A_CTRL_CLR_ENABLE_SHIFT          (0U)
/*! ENABLE - ENABLE */
#define PXP_WFE_A_CTRL_CLR_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_CLR_ENABLE_SHIFT)) & PXP_WFE_A_CTRL_CLR_ENABLE_MASK)

#define PXP_WFE_A_CTRL_CLR_RSVD1_MASK            (0x2U)
#define PXP_WFE_A_CTRL_CLR_RSVD1_SHIFT           (1U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_CTRL_CLR_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_CLR_RSVD1_SHIFT)) & PXP_WFE_A_CTRL_CLR_RSVD1_MASK)

#define PXP_WFE_A_CTRL_CLR_SW_RESET_MASK         (0x4U)
#define PXP_WFE_A_CTRL_CLR_SW_RESET_SHIFT        (2U)
/*! SW_RESET - SW_RESET */
#define PXP_WFE_A_CTRL_CLR_SW_RESET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_CLR_SW_RESET_SHIFT)) & PXP_WFE_A_CTRL_CLR_SW_RESET_MASK)

#define PXP_WFE_A_CTRL_CLR_ALU_REGISTER_ENABLE_MASK (0x8U)
#define PXP_WFE_A_CTRL_CLR_ALU_REGISTER_ENABLE_SHIFT (3U)
/*! ALU_REGISTER_ENABLE - ALU_REGISTER_ENABLE */
#define PXP_WFE_A_CTRL_CLR_ALU_REGISTER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_CLR_ALU_REGISTER_ENABLE_SHIFT)) & PXP_WFE_A_CTRL_CLR_ALU_REGISTER_ENABLE_MASK)

#define PXP_WFE_A_CTRL_CLR_RSVD0_MASK            (0x7FFFFFF0U)
#define PXP_WFE_A_CTRL_CLR_RSVD0_SHIFT           (4U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_CTRL_CLR_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_CLR_RSVD0_SHIFT)) & PXP_WFE_A_CTRL_CLR_RSVD0_MASK)

#define PXP_WFE_A_CTRL_CLR_DONE_MASK             (0x80000000U)
#define PXP_WFE_A_CTRL_CLR_DONE_SHIFT            (31U)
/*! DONE - DONE */
#define PXP_WFE_A_CTRL_CLR_DONE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_CLR_DONE_SHIFT)) & PXP_WFE_A_CTRL_CLR_DONE_MASK)
/*! @} */

/*! @name WFE_A_CTRL_TOG -  */
/*! @{ */

#define PXP_WFE_A_CTRL_TOG_ENABLE_MASK           (0x1U)
#define PXP_WFE_A_CTRL_TOG_ENABLE_SHIFT          (0U)
/*! ENABLE - ENABLE */
#define PXP_WFE_A_CTRL_TOG_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_TOG_ENABLE_SHIFT)) & PXP_WFE_A_CTRL_TOG_ENABLE_MASK)

#define PXP_WFE_A_CTRL_TOG_RSVD1_MASK            (0x2U)
#define PXP_WFE_A_CTRL_TOG_RSVD1_SHIFT           (1U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_CTRL_TOG_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_TOG_RSVD1_SHIFT)) & PXP_WFE_A_CTRL_TOG_RSVD1_MASK)

#define PXP_WFE_A_CTRL_TOG_SW_RESET_MASK         (0x4U)
#define PXP_WFE_A_CTRL_TOG_SW_RESET_SHIFT        (2U)
/*! SW_RESET - SW_RESET */
#define PXP_WFE_A_CTRL_TOG_SW_RESET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_TOG_SW_RESET_SHIFT)) & PXP_WFE_A_CTRL_TOG_SW_RESET_MASK)

#define PXP_WFE_A_CTRL_TOG_ALU_REGISTER_ENABLE_MASK (0x8U)
#define PXP_WFE_A_CTRL_TOG_ALU_REGISTER_ENABLE_SHIFT (3U)
/*! ALU_REGISTER_ENABLE - ALU_REGISTER_ENABLE */
#define PXP_WFE_A_CTRL_TOG_ALU_REGISTER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_TOG_ALU_REGISTER_ENABLE_SHIFT)) & PXP_WFE_A_CTRL_TOG_ALU_REGISTER_ENABLE_MASK)

#define PXP_WFE_A_CTRL_TOG_RSVD0_MASK            (0x7FFFFFF0U)
#define PXP_WFE_A_CTRL_TOG_RSVD0_SHIFT           (4U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_CTRL_TOG_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_TOG_RSVD0_SHIFT)) & PXP_WFE_A_CTRL_TOG_RSVD0_MASK)

#define PXP_WFE_A_CTRL_TOG_DONE_MASK             (0x80000000U)
#define PXP_WFE_A_CTRL_TOG_DONE_SHIFT            (31U)
/*! DONE - DONE */
#define PXP_WFE_A_CTRL_TOG_DONE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_CTRL_TOG_DONE_SHIFT)) & PXP_WFE_A_CTRL_TOG_DONE_MASK)
/*! @} */

/*! @name WFE_A_DIMENSIONS -  */
/*! @{ */

#define PXP_WFE_A_DIMENSIONS_WIDTH_MASK          (0x1FFFU)
#define PXP_WFE_A_DIMENSIONS_WIDTH_SHIFT         (0U)
/*! WIDTH - WIDTH */
#define PXP_WFE_A_DIMENSIONS_WIDTH(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_DIMENSIONS_WIDTH_SHIFT)) & PXP_WFE_A_DIMENSIONS_WIDTH_MASK)

#define PXP_WFE_A_DIMENSIONS_RSVD1_MASK          (0xE000U)
#define PXP_WFE_A_DIMENSIONS_RSVD1_SHIFT         (13U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_DIMENSIONS_RSVD1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_DIMENSIONS_RSVD1_SHIFT)) & PXP_WFE_A_DIMENSIONS_RSVD1_MASK)

#define PXP_WFE_A_DIMENSIONS_HEIGHT_MASK         (0x1FFF0000U)
#define PXP_WFE_A_DIMENSIONS_HEIGHT_SHIFT        (16U)
/*! HEIGHT - HEIGHT */
#define PXP_WFE_A_DIMENSIONS_HEIGHT(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_DIMENSIONS_HEIGHT_SHIFT)) & PXP_WFE_A_DIMENSIONS_HEIGHT_MASK)

#define PXP_WFE_A_DIMENSIONS_RSVD0_MASK          (0xE0000000U)
#define PXP_WFE_A_DIMENSIONS_RSVD0_SHIFT         (29U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_DIMENSIONS_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_DIMENSIONS_RSVD0_SHIFT)) & PXP_WFE_A_DIMENSIONS_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_OFFSET -  */
/*! @{ */

#define PXP_WFE_A_OFFSET_X_OFFSET_MASK           (0x1FFFU)
#define PXP_WFE_A_OFFSET_X_OFFSET_SHIFT          (0U)
/*! X_OFFSET - X_OFFSET */
#define PXP_WFE_A_OFFSET_X_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_OFFSET_X_OFFSET_SHIFT)) & PXP_WFE_A_OFFSET_X_OFFSET_MASK)

#define PXP_WFE_A_OFFSET_RSVD1_MASK              (0xE000U)
#define PXP_WFE_A_OFFSET_RSVD1_SHIFT             (13U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_OFFSET_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_OFFSET_RSVD1_SHIFT)) & PXP_WFE_A_OFFSET_RSVD1_MASK)

#define PXP_WFE_A_OFFSET_Y_OFFSET_MASK           (0x1FFF0000U)
#define PXP_WFE_A_OFFSET_Y_OFFSET_SHIFT          (16U)
/*! Y_OFFSET - Y_OFFSET */
#define PXP_WFE_A_OFFSET_Y_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_OFFSET_Y_OFFSET_SHIFT)) & PXP_WFE_A_OFFSET_Y_OFFSET_MASK)

#define PXP_WFE_A_OFFSET_RSVD0_MASK              (0xE0000000U)
#define PXP_WFE_A_OFFSET_RSVD0_SHIFT             (29U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_OFFSET_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_OFFSET_RSVD0_SHIFT)) & PXP_WFE_A_OFFSET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_SW_DATA_REGS -  */
/*! @{ */

#define PXP_WFE_A_SW_DATA_REGS_VAL0_MASK         (0xFFU)
#define PXP_WFE_A_SW_DATA_REGS_VAL0_SHIFT        (0U)
/*! VAL0 - VAL0 */
#define PXP_WFE_A_SW_DATA_REGS_VAL0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_SW_DATA_REGS_VAL0_SHIFT)) & PXP_WFE_A_SW_DATA_REGS_VAL0_MASK)

#define PXP_WFE_A_SW_DATA_REGS_VAL1_MASK         (0xFF00U)
#define PXP_WFE_A_SW_DATA_REGS_VAL1_SHIFT        (8U)
/*! VAL1 - VAL1 */
#define PXP_WFE_A_SW_DATA_REGS_VAL1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_SW_DATA_REGS_VAL1_SHIFT)) & PXP_WFE_A_SW_DATA_REGS_VAL1_MASK)

#define PXP_WFE_A_SW_DATA_REGS_VAL2_MASK         (0xFF0000U)
#define PXP_WFE_A_SW_DATA_REGS_VAL2_SHIFT        (16U)
/*! VAL2 - VAL2 */
#define PXP_WFE_A_SW_DATA_REGS_VAL2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_SW_DATA_REGS_VAL2_SHIFT)) & PXP_WFE_A_SW_DATA_REGS_VAL2_MASK)

#define PXP_WFE_A_SW_DATA_REGS_VAL3_MASK         (0xFF000000U)
#define PXP_WFE_A_SW_DATA_REGS_VAL3_SHIFT        (24U)
/*! VAL3 - VAL3 */
#define PXP_WFE_A_SW_DATA_REGS_VAL3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_SW_DATA_REGS_VAL3_SHIFT)) & PXP_WFE_A_SW_DATA_REGS_VAL3_MASK)
/*! @} */

/*! @name WFE_A_SW_FLAG_REGS -  */
/*! @{ */

#define PXP_WFE_A_SW_FLAG_REGS_VAL0_MASK         (0x1U)
#define PXP_WFE_A_SW_FLAG_REGS_VAL0_SHIFT        (0U)
/*! VAL0 - VAL0 */
#define PXP_WFE_A_SW_FLAG_REGS_VAL0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_SW_FLAG_REGS_VAL0_SHIFT)) & PXP_WFE_A_SW_FLAG_REGS_VAL0_MASK)

#define PXP_WFE_A_SW_FLAG_REGS_VAL1_MASK         (0x2U)
#define PXP_WFE_A_SW_FLAG_REGS_VAL1_SHIFT        (1U)
/*! VAL1 - VAL1 */
#define PXP_WFE_A_SW_FLAG_REGS_VAL1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_SW_FLAG_REGS_VAL1_SHIFT)) & PXP_WFE_A_SW_FLAG_REGS_VAL1_MASK)

#define PXP_WFE_A_SW_FLAG_REGS_VAL2_MASK         (0x4U)
#define PXP_WFE_A_SW_FLAG_REGS_VAL2_SHIFT        (2U)
/*! VAL2 - VAL2 */
#define PXP_WFE_A_SW_FLAG_REGS_VAL2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_SW_FLAG_REGS_VAL2_SHIFT)) & PXP_WFE_A_SW_FLAG_REGS_VAL2_MASK)

#define PXP_WFE_A_SW_FLAG_REGS_VAL3_MASK         (0x8U)
#define PXP_WFE_A_SW_FLAG_REGS_VAL3_SHIFT        (3U)
/*! VAL3 - VAL3 */
#define PXP_WFE_A_SW_FLAG_REGS_VAL3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_SW_FLAG_REGS_VAL3_SHIFT)) & PXP_WFE_A_SW_FLAG_REGS_VAL3_MASK)

#define PXP_WFE_A_SW_FLAG_REGS_RSVD_MASK         (0xFFFFFFF0U)
#define PXP_WFE_A_SW_FLAG_REGS_RSVD_SHIFT        (4U)
/*! RSVD - RSVD */
#define PXP_WFE_A_SW_FLAG_REGS_RSVD(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_SW_FLAG_REGS_RSVD_SHIFT)) & PXP_WFE_A_SW_FLAG_REGS_RSVD_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX0 -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX0_MUX0_MASK          (0x3FU)
#define PXP_WFE_A_STAGE1_MUX0_MUX0_SHIFT         (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_A_STAGE1_MUX0_MUX0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_MUX0_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_MUX0_MASK)

#define PXP_WFE_A_STAGE1_MUX0_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE1_MUX0_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX0_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX0_MUX1_MASK          (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX0_MUX1_SHIFT         (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_A_STAGE1_MUX0_MUX1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_MUX1_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_MUX1_MASK)

#define PXP_WFE_A_STAGE1_MUX0_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE1_MUX0_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX0_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX0_MUX2_MASK          (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX0_MUX2_SHIFT         (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_A_STAGE1_MUX0_MUX2(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_MUX2_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_MUX2_MASK)

#define PXP_WFE_A_STAGE1_MUX0_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX0_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX0_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX0_MUX3_MASK          (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX0_MUX3_SHIFT         (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_A_STAGE1_MUX0_MUX3(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_MUX3_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_MUX3_MASK)

#define PXP_WFE_A_STAGE1_MUX0_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX0_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX0_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX0_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX0_SET_MUX0_MASK      (0x3FU)
#define PXP_WFE_A_STAGE1_MUX0_SET_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_A_STAGE1_MUX0_SET_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_SET_MUX0_MASK)

#define PXP_WFE_A_STAGE1_MUX0_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX0_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX0_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX0_SET_MUX1_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX0_SET_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_A_STAGE1_MUX0_SET_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_SET_MUX1_MASK)

#define PXP_WFE_A_STAGE1_MUX0_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX0_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX0_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX0_SET_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX0_SET_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_A_STAGE1_MUX0_SET_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_SET_MUX2_MASK)

#define PXP_WFE_A_STAGE1_MUX0_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX0_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX0_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX0_SET_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX0_SET_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_A_STAGE1_MUX0_SET_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_SET_MUX3_MASK)

#define PXP_WFE_A_STAGE1_MUX0_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX0_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX0_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX0_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX0_CLR_MUX0_MASK      (0x3FU)
#define PXP_WFE_A_STAGE1_MUX0_CLR_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_A_STAGE1_MUX0_CLR_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_CLR_MUX0_MASK)

#define PXP_WFE_A_STAGE1_MUX0_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX0_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX0_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX0_CLR_MUX1_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX0_CLR_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_A_STAGE1_MUX0_CLR_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_CLR_MUX1_MASK)

#define PXP_WFE_A_STAGE1_MUX0_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX0_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX0_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX0_CLR_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX0_CLR_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_A_STAGE1_MUX0_CLR_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_CLR_MUX2_MASK)

#define PXP_WFE_A_STAGE1_MUX0_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX0_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX0_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX0_CLR_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX0_CLR_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_A_STAGE1_MUX0_CLR_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_CLR_MUX3_MASK)

#define PXP_WFE_A_STAGE1_MUX0_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX0_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX0_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX0_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX0_TOG_MUX0_MASK      (0x3FU)
#define PXP_WFE_A_STAGE1_MUX0_TOG_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_A_STAGE1_MUX0_TOG_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_TOG_MUX0_MASK)

#define PXP_WFE_A_STAGE1_MUX0_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX0_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX0_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX0_TOG_MUX1_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX0_TOG_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_A_STAGE1_MUX0_TOG_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_TOG_MUX1_MASK)

#define PXP_WFE_A_STAGE1_MUX0_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX0_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX0_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX0_TOG_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX0_TOG_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_A_STAGE1_MUX0_TOG_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_TOG_MUX2_MASK)

#define PXP_WFE_A_STAGE1_MUX0_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX0_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX0_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX0_TOG_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX0_TOG_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_A_STAGE1_MUX0_TOG_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_TOG_MUX3_MASK)

#define PXP_WFE_A_STAGE1_MUX0_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX0_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX0_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX0_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX0_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX1 -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX1_MUX4_MASK          (0x3FU)
#define PXP_WFE_A_STAGE1_MUX1_MUX4_SHIFT         (0U)
/*! MUX4 - MUX4
 *  0b000000..INC : Increment operation.
 *  0b000001..DEC : Decrement operation.
 *  0b000010..ADD : Addition operation.
 *  0b000011..MINUS : Subtraction operation.
 *  0b000100..AND : Bitwise AND operation. A AND B.
 *  0b000101..OR : Bitwise OR operation. A OR B.
 *  0b000110..XOR : Bitwise XOR operation. A XOR B.
 *  0b000111..SHIFTLEFT : Shift A operand left by B operand places.
 *  0b001000..SHIFTRIGHT : Shift A operand right by B operand places.
 *  0b001001..BIT_AND : Reduction AND operation on A operand.
 *  0b001010..BIT_OR : Reduction OR operation on A operand.
 *  0b001011..BIT_CMP : Compare A and B operands and set equal flag if A and B are equal. All other output is 0.
 *  0b001100..NOP : No operation. All outputs are 0.
 */
#define PXP_WFE_A_STAGE1_MUX1_MUX4(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_MUX4_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_MUX4_MASK)

#define PXP_WFE_A_STAGE1_MUX1_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE1_MUX1_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX1_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX1_MUX5_MASK          (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX1_MUX5_SHIFT         (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_A_STAGE1_MUX1_MUX5(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_MUX5_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_MUX5_MASK)

#define PXP_WFE_A_STAGE1_MUX1_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE1_MUX1_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX1_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX1_MUX6_MASK          (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX1_MUX6_SHIFT         (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_A_STAGE1_MUX1_MUX6(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_MUX6_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_MUX6_MASK)

#define PXP_WFE_A_STAGE1_MUX1_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX1_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX1_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX1_MUX7_MASK          (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX1_MUX7_SHIFT         (24U)
/*! MUX7 - MUX7
 *  0b000000..INC : Increment operation.
 *  0b000001..DEC : Decrement operation.
 *  0b000010..ADD : Addition operation.
 *  0b000011..MINUS : Subtraction operation.
 *  0b000100..AND : Bitwise AND operation. A AND B.
 *  0b000101..OR : Bitwise OR operation. A OR B.
 *  0b000110..XOR : Bitwise XOR operation. A XOR B.
 *  0b000111..SHIFTLEFT : Shift A operand left by B operand places.
 *  0b001000..SHIFTRIGHT : Shift A operand right by B operand places.
 *  0b001001..BIT_AND : Reduction AND operation on A operand.
 *  0b001010..BIT_OR : Reduction OR operation on A operand.
 *  0b001011..BIT_CMP : Compare A and B operands and set equal flag if A and B are equal. All other output is 0.
 *  0b001100..NOP : No operation. All outputs are 0.
 */
#define PXP_WFE_A_STAGE1_MUX1_MUX7(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_MUX7_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_MUX7_MASK)

#define PXP_WFE_A_STAGE1_MUX1_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX1_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX1_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX1_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX1_SET_MUX4_MASK      (0x3FU)
#define PXP_WFE_A_STAGE1_MUX1_SET_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_A_STAGE1_MUX1_SET_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_SET_MUX4_MASK)

#define PXP_WFE_A_STAGE1_MUX1_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX1_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX1_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX1_SET_MUX5_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX1_SET_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_A_STAGE1_MUX1_SET_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_SET_MUX5_MASK)

#define PXP_WFE_A_STAGE1_MUX1_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX1_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX1_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX1_SET_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX1_SET_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_A_STAGE1_MUX1_SET_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_SET_MUX6_MASK)

#define PXP_WFE_A_STAGE1_MUX1_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX1_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX1_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX1_SET_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX1_SET_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_A_STAGE1_MUX1_SET_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_SET_MUX7_MASK)

#define PXP_WFE_A_STAGE1_MUX1_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX1_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX1_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX1_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX1_CLR_MUX4_MASK      (0x3FU)
#define PXP_WFE_A_STAGE1_MUX1_CLR_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_A_STAGE1_MUX1_CLR_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_CLR_MUX4_MASK)

#define PXP_WFE_A_STAGE1_MUX1_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX1_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX1_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX1_CLR_MUX5_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX1_CLR_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_A_STAGE1_MUX1_CLR_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_CLR_MUX5_MASK)

#define PXP_WFE_A_STAGE1_MUX1_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX1_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX1_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX1_CLR_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX1_CLR_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_A_STAGE1_MUX1_CLR_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_CLR_MUX6_MASK)

#define PXP_WFE_A_STAGE1_MUX1_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX1_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX1_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX1_CLR_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX1_CLR_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_A_STAGE1_MUX1_CLR_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_CLR_MUX7_MASK)

#define PXP_WFE_A_STAGE1_MUX1_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX1_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX1_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX1_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX1_TOG_MUX4_MASK      (0x3FU)
#define PXP_WFE_A_STAGE1_MUX1_TOG_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_A_STAGE1_MUX1_TOG_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_TOG_MUX4_MASK)

#define PXP_WFE_A_STAGE1_MUX1_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX1_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX1_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX1_TOG_MUX5_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX1_TOG_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_A_STAGE1_MUX1_TOG_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_TOG_MUX5_MASK)

#define PXP_WFE_A_STAGE1_MUX1_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX1_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX1_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX1_TOG_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX1_TOG_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_A_STAGE1_MUX1_TOG_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_TOG_MUX6_MASK)

#define PXP_WFE_A_STAGE1_MUX1_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX1_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX1_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX1_TOG_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX1_TOG_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_A_STAGE1_MUX1_TOG_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_TOG_MUX7_MASK)

#define PXP_WFE_A_STAGE1_MUX1_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX1_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX1_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX1_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX1_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX2 -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX2_MUX8_MASK          (0x3FU)
#define PXP_WFE_A_STAGE1_MUX2_MUX8_SHIFT         (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_A_STAGE1_MUX2_MUX8(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_MUX8_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_MUX8_MASK)

#define PXP_WFE_A_STAGE1_MUX2_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE1_MUX2_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX2_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX2_MUX9_MASK          (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX2_MUX9_SHIFT         (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_A_STAGE1_MUX2_MUX9(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_MUX9_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_MUX9_MASK)

#define PXP_WFE_A_STAGE1_MUX2_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE1_MUX2_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX2_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX2_MUX10_MASK         (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX2_MUX10_SHIFT        (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_A_STAGE1_MUX2_MUX10(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_MUX10_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_MUX10_MASK)

#define PXP_WFE_A_STAGE1_MUX2_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX2_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX2_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX2_MUX11_MASK         (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX2_MUX11_SHIFT        (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_A_STAGE1_MUX2_MUX11(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_MUX11_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_MUX11_MASK)

#define PXP_WFE_A_STAGE1_MUX2_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX2_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX2_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX2_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX2_SET_MUX8_MASK      (0x3FU)
#define PXP_WFE_A_STAGE1_MUX2_SET_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_A_STAGE1_MUX2_SET_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_SET_MUX8_MASK)

#define PXP_WFE_A_STAGE1_MUX2_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX2_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX2_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX2_SET_MUX9_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX2_SET_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_A_STAGE1_MUX2_SET_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_SET_MUX9_MASK)

#define PXP_WFE_A_STAGE1_MUX2_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX2_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX2_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX2_SET_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX2_SET_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_A_STAGE1_MUX2_SET_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_SET_MUX10_MASK)

#define PXP_WFE_A_STAGE1_MUX2_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX2_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX2_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX2_SET_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX2_SET_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_A_STAGE1_MUX2_SET_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_SET_MUX11_MASK)

#define PXP_WFE_A_STAGE1_MUX2_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX2_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX2_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX2_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX2_CLR_MUX8_MASK      (0x3FU)
#define PXP_WFE_A_STAGE1_MUX2_CLR_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_A_STAGE1_MUX2_CLR_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_CLR_MUX8_MASK)

#define PXP_WFE_A_STAGE1_MUX2_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX2_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX2_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX2_CLR_MUX9_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX2_CLR_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_A_STAGE1_MUX2_CLR_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_CLR_MUX9_MASK)

#define PXP_WFE_A_STAGE1_MUX2_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX2_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX2_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX2_CLR_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX2_CLR_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_A_STAGE1_MUX2_CLR_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_CLR_MUX10_MASK)

#define PXP_WFE_A_STAGE1_MUX2_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX2_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX2_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX2_CLR_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX2_CLR_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_A_STAGE1_MUX2_CLR_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_CLR_MUX11_MASK)

#define PXP_WFE_A_STAGE1_MUX2_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX2_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX2_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX2_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX2_TOG_MUX8_MASK      (0x3FU)
#define PXP_WFE_A_STAGE1_MUX2_TOG_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_A_STAGE1_MUX2_TOG_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_TOG_MUX8_MASK)

#define PXP_WFE_A_STAGE1_MUX2_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX2_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX2_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX2_TOG_MUX9_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX2_TOG_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_A_STAGE1_MUX2_TOG_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_TOG_MUX9_MASK)

#define PXP_WFE_A_STAGE1_MUX2_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX2_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX2_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX2_TOG_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX2_TOG_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_A_STAGE1_MUX2_TOG_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_TOG_MUX10_MASK)

#define PXP_WFE_A_STAGE1_MUX2_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX2_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX2_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX2_TOG_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX2_TOG_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_A_STAGE1_MUX2_TOG_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_TOG_MUX11_MASK)

#define PXP_WFE_A_STAGE1_MUX2_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX2_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX2_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX2_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX2_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX3 -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX3_MUX12_MASK         (0x3FU)
#define PXP_WFE_A_STAGE1_MUX3_MUX12_SHIFT        (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_A_STAGE1_MUX3_MUX12(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_MUX12_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_MUX12_MASK)

#define PXP_WFE_A_STAGE1_MUX3_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE1_MUX3_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX3_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX3_MUX13_MASK         (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX3_MUX13_SHIFT        (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_A_STAGE1_MUX3_MUX13(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_MUX13_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_MUX13_MASK)

#define PXP_WFE_A_STAGE1_MUX3_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE1_MUX3_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX3_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX3_MUX14_MASK         (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX3_MUX14_SHIFT        (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_A_STAGE1_MUX3_MUX14(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_MUX14_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_MUX14_MASK)

#define PXP_WFE_A_STAGE1_MUX3_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX3_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX3_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX3_MUX15_MASK         (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX3_MUX15_SHIFT        (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_A_STAGE1_MUX3_MUX15(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_MUX15_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_MUX15_MASK)

#define PXP_WFE_A_STAGE1_MUX3_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX3_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX3_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX3_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX3_SET_MUX12_MASK     (0x3FU)
#define PXP_WFE_A_STAGE1_MUX3_SET_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_A_STAGE1_MUX3_SET_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_SET_MUX12_MASK)

#define PXP_WFE_A_STAGE1_MUX3_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX3_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX3_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX3_SET_MUX13_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX3_SET_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_A_STAGE1_MUX3_SET_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_SET_MUX13_MASK)

#define PXP_WFE_A_STAGE1_MUX3_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX3_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX3_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX3_SET_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX3_SET_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_A_STAGE1_MUX3_SET_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_SET_MUX14_MASK)

#define PXP_WFE_A_STAGE1_MUX3_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX3_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX3_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX3_SET_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX3_SET_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_A_STAGE1_MUX3_SET_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_SET_MUX15_MASK)

#define PXP_WFE_A_STAGE1_MUX3_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX3_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX3_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX3_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX3_CLR_MUX12_MASK     (0x3FU)
#define PXP_WFE_A_STAGE1_MUX3_CLR_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_A_STAGE1_MUX3_CLR_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_CLR_MUX12_MASK)

#define PXP_WFE_A_STAGE1_MUX3_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX3_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX3_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX3_CLR_MUX13_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX3_CLR_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_A_STAGE1_MUX3_CLR_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_CLR_MUX13_MASK)

#define PXP_WFE_A_STAGE1_MUX3_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX3_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX3_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX3_CLR_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX3_CLR_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_A_STAGE1_MUX3_CLR_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_CLR_MUX14_MASK)

#define PXP_WFE_A_STAGE1_MUX3_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX3_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX3_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX3_CLR_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX3_CLR_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_A_STAGE1_MUX3_CLR_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_CLR_MUX15_MASK)

#define PXP_WFE_A_STAGE1_MUX3_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX3_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX3_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX3_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX3_TOG_MUX12_MASK     (0x3FU)
#define PXP_WFE_A_STAGE1_MUX3_TOG_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_A_STAGE1_MUX3_TOG_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_TOG_MUX12_MASK)

#define PXP_WFE_A_STAGE1_MUX3_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX3_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX3_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX3_TOG_MUX13_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX3_TOG_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_A_STAGE1_MUX3_TOG_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_TOG_MUX13_MASK)

#define PXP_WFE_A_STAGE1_MUX3_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX3_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX3_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX3_TOG_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE1_MUX3_TOG_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_A_STAGE1_MUX3_TOG_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_TOG_MUX14_MASK)

#define PXP_WFE_A_STAGE1_MUX3_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE1_MUX3_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX3_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX3_TOG_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE1_MUX3_TOG_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_A_STAGE1_MUX3_TOG_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_TOG_MUX15_MASK)

#define PXP_WFE_A_STAGE1_MUX3_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE1_MUX3_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX3_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX3_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX3_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX4 -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX4_MUX16_MASK         (0x3FU)
#define PXP_WFE_A_STAGE1_MUX4_MUX16_SHIFT        (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_A_STAGE1_MUX4_MUX16(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_MUX16_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_MUX16_MASK)

#define PXP_WFE_A_STAGE1_MUX4_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE1_MUX4_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX4_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX4_MUX17_MASK         (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX4_MUX17_SHIFT        (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_A_STAGE1_MUX4_MUX17(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_MUX17_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_MUX17_MASK)

#define PXP_WFE_A_STAGE1_MUX4_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE1_MUX4_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX4_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX4_RSVD1_MASK         (0xFF0000U)
#define PXP_WFE_A_STAGE1_MUX4_RSVD1_SHIFT        (16U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX4_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX4_RSVD0_MASK         (0xFF000000U)
#define PXP_WFE_A_STAGE1_MUX4_RSVD0_SHIFT        (24U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX4_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX4_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX4_SET_MUX16_MASK     (0x3FU)
#define PXP_WFE_A_STAGE1_MUX4_SET_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_A_STAGE1_MUX4_SET_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_SET_MUX16_MASK)

#define PXP_WFE_A_STAGE1_MUX4_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX4_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX4_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX4_SET_MUX17_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX4_SET_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_A_STAGE1_MUX4_SET_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_SET_MUX17_MASK)

#define PXP_WFE_A_STAGE1_MUX4_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX4_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX4_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX4_SET_RSVD1_MASK     (0xFF0000U)
#define PXP_WFE_A_STAGE1_MUX4_SET_RSVD1_SHIFT    (16U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX4_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX4_SET_RSVD0_MASK     (0xFF000000U)
#define PXP_WFE_A_STAGE1_MUX4_SET_RSVD0_SHIFT    (24U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX4_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX4_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX4_CLR_MUX16_MASK     (0x3FU)
#define PXP_WFE_A_STAGE1_MUX4_CLR_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_A_STAGE1_MUX4_CLR_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_CLR_MUX16_MASK)

#define PXP_WFE_A_STAGE1_MUX4_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX4_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX4_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX4_CLR_MUX17_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX4_CLR_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_A_STAGE1_MUX4_CLR_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_CLR_MUX17_MASK)

#define PXP_WFE_A_STAGE1_MUX4_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX4_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX4_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX4_CLR_RSVD1_MASK     (0xFF0000U)
#define PXP_WFE_A_STAGE1_MUX4_CLR_RSVD1_SHIFT    (16U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX4_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX4_CLR_RSVD0_MASK     (0xFF000000U)
#define PXP_WFE_A_STAGE1_MUX4_CLR_RSVD0_SHIFT    (24U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX4_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE1_MUX4_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE1_MUX4_TOG_MUX16_MASK     (0x3FU)
#define PXP_WFE_A_STAGE1_MUX4_TOG_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_A_STAGE1_MUX4_TOG_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_TOG_MUX16_MASK)

#define PXP_WFE_A_STAGE1_MUX4_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE1_MUX4_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE1_MUX4_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE1_MUX4_TOG_MUX17_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE1_MUX4_TOG_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_A_STAGE1_MUX4_TOG_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_TOG_MUX17_MASK)

#define PXP_WFE_A_STAGE1_MUX4_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE1_MUX4_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE1_MUX4_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE1_MUX4_TOG_RSVD1_MASK     (0xFF0000U)
#define PXP_WFE_A_STAGE1_MUX4_TOG_RSVD1_SHIFT    (16U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE1_MUX4_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE1_MUX4_TOG_RSVD0_MASK     (0xFF000000U)
#define PXP_WFE_A_STAGE1_MUX4_TOG_RSVD0_SHIFT    (24U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE1_MUX4_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE1_MUX4_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE1_MUX4_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX0 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX0_MUX0_MASK          (0x3FU)
#define PXP_WFE_A_STAGE2_MUX0_MUX0_SHIFT         (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_A_STAGE2_MUX0_MUX0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_MUX0_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_MUX0_MASK)

#define PXP_WFE_A_STAGE2_MUX0_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE2_MUX0_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX0_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX0_MUX1_MASK          (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX0_MUX1_SHIFT         (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_A_STAGE2_MUX0_MUX1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_MUX1_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_MUX1_MASK)

#define PXP_WFE_A_STAGE2_MUX0_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE2_MUX0_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX0_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX0_MUX2_MASK          (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX0_MUX2_SHIFT         (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_A_STAGE2_MUX0_MUX2(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_MUX2_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_MUX2_MASK)

#define PXP_WFE_A_STAGE2_MUX0_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX0_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX0_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX0_MUX3_MASK          (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX0_MUX3_SHIFT         (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_A_STAGE2_MUX0_MUX3(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_MUX3_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_MUX3_MASK)

#define PXP_WFE_A_STAGE2_MUX0_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX0_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX0_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX0_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX0_SET_MUX0_MASK      (0x3FU)
#define PXP_WFE_A_STAGE2_MUX0_SET_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_A_STAGE2_MUX0_SET_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_SET_MUX0_MASK)

#define PXP_WFE_A_STAGE2_MUX0_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX0_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX0_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX0_SET_MUX1_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX0_SET_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_A_STAGE2_MUX0_SET_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_SET_MUX1_MASK)

#define PXP_WFE_A_STAGE2_MUX0_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX0_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX0_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX0_SET_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX0_SET_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_A_STAGE2_MUX0_SET_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_SET_MUX2_MASK)

#define PXP_WFE_A_STAGE2_MUX0_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX0_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX0_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX0_SET_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX0_SET_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_A_STAGE2_MUX0_SET_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_SET_MUX3_MASK)

#define PXP_WFE_A_STAGE2_MUX0_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX0_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX0_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX0_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX0_CLR_MUX0_MASK      (0x3FU)
#define PXP_WFE_A_STAGE2_MUX0_CLR_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_A_STAGE2_MUX0_CLR_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_CLR_MUX0_MASK)

#define PXP_WFE_A_STAGE2_MUX0_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX0_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX0_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX0_CLR_MUX1_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX0_CLR_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_A_STAGE2_MUX0_CLR_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_CLR_MUX1_MASK)

#define PXP_WFE_A_STAGE2_MUX0_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX0_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX0_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX0_CLR_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX0_CLR_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_A_STAGE2_MUX0_CLR_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_CLR_MUX2_MASK)

#define PXP_WFE_A_STAGE2_MUX0_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX0_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX0_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX0_CLR_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX0_CLR_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_A_STAGE2_MUX0_CLR_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_CLR_MUX3_MASK)

#define PXP_WFE_A_STAGE2_MUX0_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX0_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX0_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX0_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX0_TOG_MUX0_MASK      (0x3FU)
#define PXP_WFE_A_STAGE2_MUX0_TOG_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_A_STAGE2_MUX0_TOG_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_TOG_MUX0_MASK)

#define PXP_WFE_A_STAGE2_MUX0_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX0_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX0_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX0_TOG_MUX1_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX0_TOG_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_A_STAGE2_MUX0_TOG_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_TOG_MUX1_MASK)

#define PXP_WFE_A_STAGE2_MUX0_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX0_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX0_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX0_TOG_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX0_TOG_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_A_STAGE2_MUX0_TOG_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_TOG_MUX2_MASK)

#define PXP_WFE_A_STAGE2_MUX0_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX0_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX0_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX0_TOG_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX0_TOG_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_A_STAGE2_MUX0_TOG_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_TOG_MUX3_MASK)

#define PXP_WFE_A_STAGE2_MUX0_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX0_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX0_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX0_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX0_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX1 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX1_MUX4_MASK          (0x3FU)
#define PXP_WFE_A_STAGE2_MUX1_MUX4_SHIFT         (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_A_STAGE2_MUX1_MUX4(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_MUX4_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_MUX4_MASK)

#define PXP_WFE_A_STAGE2_MUX1_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE2_MUX1_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX1_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX1_MUX5_MASK          (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX1_MUX5_SHIFT         (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_A_STAGE2_MUX1_MUX5(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_MUX5_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_MUX5_MASK)

#define PXP_WFE_A_STAGE2_MUX1_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE2_MUX1_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX1_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX1_MUX6_MASK          (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX1_MUX6_SHIFT         (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_A_STAGE2_MUX1_MUX6(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_MUX6_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_MUX6_MASK)

#define PXP_WFE_A_STAGE2_MUX1_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX1_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX1_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX1_MUX7_MASK          (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX1_MUX7_SHIFT         (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_A_STAGE2_MUX1_MUX7(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_MUX7_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_MUX7_MASK)

#define PXP_WFE_A_STAGE2_MUX1_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX1_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX1_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX1_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX1_SET_MUX4_MASK      (0x3FU)
#define PXP_WFE_A_STAGE2_MUX1_SET_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_A_STAGE2_MUX1_SET_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_SET_MUX4_MASK)

#define PXP_WFE_A_STAGE2_MUX1_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX1_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX1_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX1_SET_MUX5_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX1_SET_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_A_STAGE2_MUX1_SET_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_SET_MUX5_MASK)

#define PXP_WFE_A_STAGE2_MUX1_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX1_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX1_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX1_SET_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX1_SET_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_A_STAGE2_MUX1_SET_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_SET_MUX6_MASK)

#define PXP_WFE_A_STAGE2_MUX1_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX1_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX1_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX1_SET_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX1_SET_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_A_STAGE2_MUX1_SET_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_SET_MUX7_MASK)

#define PXP_WFE_A_STAGE2_MUX1_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX1_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX1_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX1_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX1_CLR_MUX4_MASK      (0x3FU)
#define PXP_WFE_A_STAGE2_MUX1_CLR_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_A_STAGE2_MUX1_CLR_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_CLR_MUX4_MASK)

#define PXP_WFE_A_STAGE2_MUX1_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX1_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX1_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX1_CLR_MUX5_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX1_CLR_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_A_STAGE2_MUX1_CLR_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_CLR_MUX5_MASK)

#define PXP_WFE_A_STAGE2_MUX1_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX1_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX1_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX1_CLR_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX1_CLR_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_A_STAGE2_MUX1_CLR_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_CLR_MUX6_MASK)

#define PXP_WFE_A_STAGE2_MUX1_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX1_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX1_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX1_CLR_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX1_CLR_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_A_STAGE2_MUX1_CLR_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_CLR_MUX7_MASK)

#define PXP_WFE_A_STAGE2_MUX1_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX1_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX1_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX1_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX1_TOG_MUX4_MASK      (0x3FU)
#define PXP_WFE_A_STAGE2_MUX1_TOG_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_A_STAGE2_MUX1_TOG_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_TOG_MUX4_MASK)

#define PXP_WFE_A_STAGE2_MUX1_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX1_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX1_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX1_TOG_MUX5_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX1_TOG_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_A_STAGE2_MUX1_TOG_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_TOG_MUX5_MASK)

#define PXP_WFE_A_STAGE2_MUX1_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX1_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX1_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX1_TOG_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX1_TOG_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_A_STAGE2_MUX1_TOG_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_TOG_MUX6_MASK)

#define PXP_WFE_A_STAGE2_MUX1_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX1_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX1_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX1_TOG_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX1_TOG_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_A_STAGE2_MUX1_TOG_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_TOG_MUX7_MASK)

#define PXP_WFE_A_STAGE2_MUX1_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX1_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX1_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX1_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX1_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX2 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX2_MUX8_MASK          (0x3FU)
#define PXP_WFE_A_STAGE2_MUX2_MUX8_SHIFT         (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_A_STAGE2_MUX2_MUX8(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_MUX8_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_MUX8_MASK)

#define PXP_WFE_A_STAGE2_MUX2_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE2_MUX2_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX2_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX2_MUX9_MASK          (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX2_MUX9_SHIFT         (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_A_STAGE2_MUX2_MUX9(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_MUX9_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_MUX9_MASK)

#define PXP_WFE_A_STAGE2_MUX2_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE2_MUX2_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX2_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX2_MUX10_MASK         (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX2_MUX10_SHIFT        (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_A_STAGE2_MUX2_MUX10(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_MUX10_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_MUX10_MASK)

#define PXP_WFE_A_STAGE2_MUX2_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX2_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX2_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX2_MUX11_MASK         (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX2_MUX11_SHIFT        (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_A_STAGE2_MUX2_MUX11(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_MUX11_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_MUX11_MASK)

#define PXP_WFE_A_STAGE2_MUX2_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX2_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX2_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX2_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX2_SET_MUX8_MASK      (0x3FU)
#define PXP_WFE_A_STAGE2_MUX2_SET_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_A_STAGE2_MUX2_SET_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_SET_MUX8_MASK)

#define PXP_WFE_A_STAGE2_MUX2_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX2_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX2_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX2_SET_MUX9_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX2_SET_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_A_STAGE2_MUX2_SET_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_SET_MUX9_MASK)

#define PXP_WFE_A_STAGE2_MUX2_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX2_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX2_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX2_SET_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX2_SET_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_A_STAGE2_MUX2_SET_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_SET_MUX10_MASK)

#define PXP_WFE_A_STAGE2_MUX2_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX2_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX2_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX2_SET_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX2_SET_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_A_STAGE2_MUX2_SET_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_SET_MUX11_MASK)

#define PXP_WFE_A_STAGE2_MUX2_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX2_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX2_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX2_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX2_CLR_MUX8_MASK      (0x3FU)
#define PXP_WFE_A_STAGE2_MUX2_CLR_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_A_STAGE2_MUX2_CLR_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_CLR_MUX8_MASK)

#define PXP_WFE_A_STAGE2_MUX2_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX2_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX2_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX2_CLR_MUX9_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX2_CLR_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_A_STAGE2_MUX2_CLR_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_CLR_MUX9_MASK)

#define PXP_WFE_A_STAGE2_MUX2_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX2_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX2_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX2_CLR_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX2_CLR_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_A_STAGE2_MUX2_CLR_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_CLR_MUX10_MASK)

#define PXP_WFE_A_STAGE2_MUX2_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX2_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX2_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX2_CLR_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX2_CLR_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_A_STAGE2_MUX2_CLR_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_CLR_MUX11_MASK)

#define PXP_WFE_A_STAGE2_MUX2_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX2_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX2_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX2_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX2_TOG_MUX8_MASK      (0x3FU)
#define PXP_WFE_A_STAGE2_MUX2_TOG_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_A_STAGE2_MUX2_TOG_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_TOG_MUX8_MASK)

#define PXP_WFE_A_STAGE2_MUX2_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX2_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX2_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX2_TOG_MUX9_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX2_TOG_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_A_STAGE2_MUX2_TOG_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_TOG_MUX9_MASK)

#define PXP_WFE_A_STAGE2_MUX2_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX2_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX2_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX2_TOG_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX2_TOG_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_A_STAGE2_MUX2_TOG_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_TOG_MUX10_MASK)

#define PXP_WFE_A_STAGE2_MUX2_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX2_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX2_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX2_TOG_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX2_TOG_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_A_STAGE2_MUX2_TOG_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_TOG_MUX11_MASK)

#define PXP_WFE_A_STAGE2_MUX2_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX2_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX2_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX2_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX2_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX3 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX3_MUX12_MASK         (0x3FU)
#define PXP_WFE_A_STAGE2_MUX3_MUX12_SHIFT        (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_A_STAGE2_MUX3_MUX12(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_MUX12_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_MUX12_MASK)

#define PXP_WFE_A_STAGE2_MUX3_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE2_MUX3_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX3_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX3_MUX13_MASK         (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX3_MUX13_SHIFT        (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_A_STAGE2_MUX3_MUX13(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_MUX13_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_MUX13_MASK)

#define PXP_WFE_A_STAGE2_MUX3_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE2_MUX3_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX3_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX3_MUX14_MASK         (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX3_MUX14_SHIFT        (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_A_STAGE2_MUX3_MUX14(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_MUX14_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_MUX14_MASK)

#define PXP_WFE_A_STAGE2_MUX3_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX3_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX3_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX3_MUX15_MASK         (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX3_MUX15_SHIFT        (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_A_STAGE2_MUX3_MUX15(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_MUX15_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_MUX15_MASK)

#define PXP_WFE_A_STAGE2_MUX3_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX3_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX3_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX3_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX3_SET_MUX12_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX3_SET_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_A_STAGE2_MUX3_SET_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_SET_MUX12_MASK)

#define PXP_WFE_A_STAGE2_MUX3_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX3_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX3_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX3_SET_MUX13_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX3_SET_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_A_STAGE2_MUX3_SET_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_SET_MUX13_MASK)

#define PXP_WFE_A_STAGE2_MUX3_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX3_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX3_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX3_SET_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX3_SET_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_A_STAGE2_MUX3_SET_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_SET_MUX14_MASK)

#define PXP_WFE_A_STAGE2_MUX3_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX3_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX3_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX3_SET_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX3_SET_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_A_STAGE2_MUX3_SET_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_SET_MUX15_MASK)

#define PXP_WFE_A_STAGE2_MUX3_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX3_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX3_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX3_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX3_CLR_MUX12_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX3_CLR_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_A_STAGE2_MUX3_CLR_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_CLR_MUX12_MASK)

#define PXP_WFE_A_STAGE2_MUX3_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX3_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX3_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX3_CLR_MUX13_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX3_CLR_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_A_STAGE2_MUX3_CLR_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_CLR_MUX13_MASK)

#define PXP_WFE_A_STAGE2_MUX3_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX3_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX3_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX3_CLR_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX3_CLR_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_A_STAGE2_MUX3_CLR_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_CLR_MUX14_MASK)

#define PXP_WFE_A_STAGE2_MUX3_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX3_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX3_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX3_CLR_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX3_CLR_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_A_STAGE2_MUX3_CLR_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_CLR_MUX15_MASK)

#define PXP_WFE_A_STAGE2_MUX3_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX3_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX3_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX3_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX3_TOG_MUX12_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX3_TOG_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_A_STAGE2_MUX3_TOG_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_TOG_MUX12_MASK)

#define PXP_WFE_A_STAGE2_MUX3_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX3_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX3_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX3_TOG_MUX13_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX3_TOG_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_A_STAGE2_MUX3_TOG_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_TOG_MUX13_MASK)

#define PXP_WFE_A_STAGE2_MUX3_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX3_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX3_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX3_TOG_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX3_TOG_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_A_STAGE2_MUX3_TOG_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_TOG_MUX14_MASK)

#define PXP_WFE_A_STAGE2_MUX3_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX3_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX3_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX3_TOG_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX3_TOG_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_A_STAGE2_MUX3_TOG_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_TOG_MUX15_MASK)

#define PXP_WFE_A_STAGE2_MUX3_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX3_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX3_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX3_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX3_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX4 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX4_MUX16_MASK         (0x3FU)
#define PXP_WFE_A_STAGE2_MUX4_MUX16_SHIFT        (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_A_STAGE2_MUX4_MUX16(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_MUX16_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_MUX16_MASK)

#define PXP_WFE_A_STAGE2_MUX4_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE2_MUX4_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX4_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX4_MUX17_MASK         (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX4_MUX17_SHIFT        (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_A_STAGE2_MUX4_MUX17(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_MUX17_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_MUX17_MASK)

#define PXP_WFE_A_STAGE2_MUX4_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE2_MUX4_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX4_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX4_MUX18_MASK         (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX4_MUX18_SHIFT        (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_A_STAGE2_MUX4_MUX18(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_MUX18_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_MUX18_MASK)

#define PXP_WFE_A_STAGE2_MUX4_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX4_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX4_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX4_MUX19_MASK         (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX4_MUX19_SHIFT        (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_A_STAGE2_MUX4_MUX19(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_MUX19_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_MUX19_MASK)

#define PXP_WFE_A_STAGE2_MUX4_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX4_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX4_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX4_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX4_SET_MUX16_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX4_SET_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_A_STAGE2_MUX4_SET_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_SET_MUX16_MASK)

#define PXP_WFE_A_STAGE2_MUX4_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX4_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX4_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX4_SET_MUX17_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX4_SET_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_A_STAGE2_MUX4_SET_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_SET_MUX17_MASK)

#define PXP_WFE_A_STAGE2_MUX4_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX4_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX4_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX4_SET_MUX18_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX4_SET_MUX18_SHIFT    (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_A_STAGE2_MUX4_SET_MUX18(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_SET_MUX18_MASK)

#define PXP_WFE_A_STAGE2_MUX4_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX4_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX4_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX4_SET_MUX19_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX4_SET_MUX19_SHIFT    (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_A_STAGE2_MUX4_SET_MUX19(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_SET_MUX19_MASK)

#define PXP_WFE_A_STAGE2_MUX4_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX4_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX4_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX4_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX4_CLR_MUX16_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX4_CLR_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_A_STAGE2_MUX4_CLR_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_CLR_MUX16_MASK)

#define PXP_WFE_A_STAGE2_MUX4_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX4_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX4_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX4_CLR_MUX17_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX4_CLR_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_A_STAGE2_MUX4_CLR_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_CLR_MUX17_MASK)

#define PXP_WFE_A_STAGE2_MUX4_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX4_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX4_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX4_CLR_MUX18_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX4_CLR_MUX18_SHIFT    (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_A_STAGE2_MUX4_CLR_MUX18(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_CLR_MUX18_MASK)

#define PXP_WFE_A_STAGE2_MUX4_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX4_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX4_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX4_CLR_MUX19_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX4_CLR_MUX19_SHIFT    (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_A_STAGE2_MUX4_CLR_MUX19(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_CLR_MUX19_MASK)

#define PXP_WFE_A_STAGE2_MUX4_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX4_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX4_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX4_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX4_TOG_MUX16_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX4_TOG_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_A_STAGE2_MUX4_TOG_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_TOG_MUX16_MASK)

#define PXP_WFE_A_STAGE2_MUX4_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX4_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX4_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX4_TOG_MUX17_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX4_TOG_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_A_STAGE2_MUX4_TOG_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_TOG_MUX17_MASK)

#define PXP_WFE_A_STAGE2_MUX4_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX4_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX4_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX4_TOG_MUX18_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX4_TOG_MUX18_SHIFT    (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_A_STAGE2_MUX4_TOG_MUX18(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_TOG_MUX18_MASK)

#define PXP_WFE_A_STAGE2_MUX4_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX4_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX4_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX4_TOG_MUX19_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX4_TOG_MUX19_SHIFT    (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_A_STAGE2_MUX4_TOG_MUX19(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_TOG_MUX19_MASK)

#define PXP_WFE_A_STAGE2_MUX4_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX4_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX4_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX4_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX4_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX5 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX5_MUX20_MASK         (0x3FU)
#define PXP_WFE_A_STAGE2_MUX5_MUX20_SHIFT        (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_A_STAGE2_MUX5_MUX20(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_MUX20_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_MUX20_MASK)

#define PXP_WFE_A_STAGE2_MUX5_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE2_MUX5_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX5_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX5_MUX21_MASK         (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX5_MUX21_SHIFT        (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_A_STAGE2_MUX5_MUX21(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_MUX21_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_MUX21_MASK)

#define PXP_WFE_A_STAGE2_MUX5_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE2_MUX5_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX5_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX5_MUX22_MASK         (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX5_MUX22_SHIFT        (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_A_STAGE2_MUX5_MUX22(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_MUX22_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_MUX22_MASK)

#define PXP_WFE_A_STAGE2_MUX5_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX5_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX5_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX5_MUX23_MASK         (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX5_MUX23_SHIFT        (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_A_STAGE2_MUX5_MUX23(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_MUX23_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_MUX23_MASK)

#define PXP_WFE_A_STAGE2_MUX5_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX5_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX5_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX5_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX5_SET_MUX20_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX5_SET_MUX20_SHIFT    (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_A_STAGE2_MUX5_SET_MUX20(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_SET_MUX20_MASK)

#define PXP_WFE_A_STAGE2_MUX5_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX5_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX5_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX5_SET_MUX21_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX5_SET_MUX21_SHIFT    (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_A_STAGE2_MUX5_SET_MUX21(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_SET_MUX21_MASK)

#define PXP_WFE_A_STAGE2_MUX5_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX5_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX5_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX5_SET_MUX22_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX5_SET_MUX22_SHIFT    (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_A_STAGE2_MUX5_SET_MUX22(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_SET_MUX22_MASK)

#define PXP_WFE_A_STAGE2_MUX5_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX5_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX5_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX5_SET_MUX23_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX5_SET_MUX23_SHIFT    (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_A_STAGE2_MUX5_SET_MUX23(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_SET_MUX23_MASK)

#define PXP_WFE_A_STAGE2_MUX5_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX5_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX5_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX5_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX5_CLR_MUX20_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX5_CLR_MUX20_SHIFT    (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_A_STAGE2_MUX5_CLR_MUX20(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_CLR_MUX20_MASK)

#define PXP_WFE_A_STAGE2_MUX5_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX5_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX5_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX5_CLR_MUX21_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX5_CLR_MUX21_SHIFT    (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_A_STAGE2_MUX5_CLR_MUX21(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_CLR_MUX21_MASK)

#define PXP_WFE_A_STAGE2_MUX5_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX5_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX5_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX5_CLR_MUX22_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX5_CLR_MUX22_SHIFT    (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_A_STAGE2_MUX5_CLR_MUX22(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_CLR_MUX22_MASK)

#define PXP_WFE_A_STAGE2_MUX5_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX5_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX5_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX5_CLR_MUX23_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX5_CLR_MUX23_SHIFT    (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_A_STAGE2_MUX5_CLR_MUX23(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_CLR_MUX23_MASK)

#define PXP_WFE_A_STAGE2_MUX5_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX5_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX5_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX5_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX5_TOG_MUX20_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX5_TOG_MUX20_SHIFT    (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_A_STAGE2_MUX5_TOG_MUX20(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_TOG_MUX20_MASK)

#define PXP_WFE_A_STAGE2_MUX5_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX5_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX5_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX5_TOG_MUX21_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX5_TOG_MUX21_SHIFT    (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_A_STAGE2_MUX5_TOG_MUX21(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_TOG_MUX21_MASK)

#define PXP_WFE_A_STAGE2_MUX5_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX5_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX5_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX5_TOG_MUX22_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX5_TOG_MUX22_SHIFT    (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_A_STAGE2_MUX5_TOG_MUX22(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_TOG_MUX22_MASK)

#define PXP_WFE_A_STAGE2_MUX5_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX5_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX5_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX5_TOG_MUX23_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX5_TOG_MUX23_SHIFT    (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_A_STAGE2_MUX5_TOG_MUX23(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_TOG_MUX23_MASK)

#define PXP_WFE_A_STAGE2_MUX5_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX5_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX5_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX5_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX5_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX6 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX6_MUX24_MASK         (0x3FU)
#define PXP_WFE_A_STAGE2_MUX6_MUX24_SHIFT        (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_A_STAGE2_MUX6_MUX24(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_MUX24_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_MUX24_MASK)

#define PXP_WFE_A_STAGE2_MUX6_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE2_MUX6_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX6_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX6_MUX25_MASK         (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX6_MUX25_SHIFT        (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_A_STAGE2_MUX6_MUX25(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_MUX25_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_MUX25_MASK)

#define PXP_WFE_A_STAGE2_MUX6_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE2_MUX6_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX6_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX6_MUX26_MASK         (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX6_MUX26_SHIFT        (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_A_STAGE2_MUX6_MUX26(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_MUX26_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_MUX26_MASK)

#define PXP_WFE_A_STAGE2_MUX6_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX6_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX6_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX6_MUX27_MASK         (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX6_MUX27_SHIFT        (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_A_STAGE2_MUX6_MUX27(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_MUX27_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_MUX27_MASK)

#define PXP_WFE_A_STAGE2_MUX6_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX6_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX6_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX6_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX6_SET_MUX24_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX6_SET_MUX24_SHIFT    (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_A_STAGE2_MUX6_SET_MUX24(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_SET_MUX24_MASK)

#define PXP_WFE_A_STAGE2_MUX6_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX6_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX6_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX6_SET_MUX25_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX6_SET_MUX25_SHIFT    (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_A_STAGE2_MUX6_SET_MUX25(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_SET_MUX25_MASK)

#define PXP_WFE_A_STAGE2_MUX6_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX6_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX6_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX6_SET_MUX26_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX6_SET_MUX26_SHIFT    (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_A_STAGE2_MUX6_SET_MUX26(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_SET_MUX26_MASK)

#define PXP_WFE_A_STAGE2_MUX6_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX6_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX6_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX6_SET_MUX27_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX6_SET_MUX27_SHIFT    (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_A_STAGE2_MUX6_SET_MUX27(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_SET_MUX27_MASK)

#define PXP_WFE_A_STAGE2_MUX6_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX6_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX6_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX6_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX6_CLR_MUX24_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX6_CLR_MUX24_SHIFT    (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_A_STAGE2_MUX6_CLR_MUX24(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_CLR_MUX24_MASK)

#define PXP_WFE_A_STAGE2_MUX6_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX6_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX6_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX6_CLR_MUX25_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX6_CLR_MUX25_SHIFT    (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_A_STAGE2_MUX6_CLR_MUX25(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_CLR_MUX25_MASK)

#define PXP_WFE_A_STAGE2_MUX6_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX6_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX6_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX6_CLR_MUX26_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX6_CLR_MUX26_SHIFT    (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_A_STAGE2_MUX6_CLR_MUX26(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_CLR_MUX26_MASK)

#define PXP_WFE_A_STAGE2_MUX6_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX6_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX6_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX6_CLR_MUX27_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX6_CLR_MUX27_SHIFT    (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_A_STAGE2_MUX6_CLR_MUX27(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_CLR_MUX27_MASK)

#define PXP_WFE_A_STAGE2_MUX6_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX6_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX6_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX6_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX6_TOG_MUX24_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX6_TOG_MUX24_SHIFT    (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_A_STAGE2_MUX6_TOG_MUX24(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_TOG_MUX24_MASK)

#define PXP_WFE_A_STAGE2_MUX6_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX6_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX6_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX6_TOG_MUX25_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX6_TOG_MUX25_SHIFT    (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_A_STAGE2_MUX6_TOG_MUX25(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_TOG_MUX25_MASK)

#define PXP_WFE_A_STAGE2_MUX6_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX6_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX6_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX6_TOG_MUX26_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX6_TOG_MUX26_SHIFT    (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_A_STAGE2_MUX6_TOG_MUX26(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_TOG_MUX26_MASK)

#define PXP_WFE_A_STAGE2_MUX6_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX6_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX6_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX6_TOG_MUX27_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX6_TOG_MUX27_SHIFT    (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_A_STAGE2_MUX6_TOG_MUX27(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_TOG_MUX27_MASK)

#define PXP_WFE_A_STAGE2_MUX6_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX6_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX6_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX6_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX6_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX7 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX7_MUX28_MASK         (0x3FU)
#define PXP_WFE_A_STAGE2_MUX7_MUX28_SHIFT        (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_A_STAGE2_MUX7_MUX28(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_MUX28_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_MUX28_MASK)

#define PXP_WFE_A_STAGE2_MUX7_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE2_MUX7_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX7_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX7_MUX29_MASK         (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX7_MUX29_SHIFT        (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_A_STAGE2_MUX7_MUX29(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_MUX29_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_MUX29_MASK)

#define PXP_WFE_A_STAGE2_MUX7_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE2_MUX7_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX7_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX7_MUX30_MASK         (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX7_MUX30_SHIFT        (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_A_STAGE2_MUX7_MUX30(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_MUX30_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_MUX30_MASK)

#define PXP_WFE_A_STAGE2_MUX7_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX7_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX7_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX7_MUX31_MASK         (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX7_MUX31_SHIFT        (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_A_STAGE2_MUX7_MUX31(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_MUX31_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_MUX31_MASK)

#define PXP_WFE_A_STAGE2_MUX7_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX7_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX7_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX7_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX7_SET_MUX28_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX7_SET_MUX28_SHIFT    (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_A_STAGE2_MUX7_SET_MUX28(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_SET_MUX28_MASK)

#define PXP_WFE_A_STAGE2_MUX7_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX7_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX7_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX7_SET_MUX29_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX7_SET_MUX29_SHIFT    (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_A_STAGE2_MUX7_SET_MUX29(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_SET_MUX29_MASK)

#define PXP_WFE_A_STAGE2_MUX7_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX7_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX7_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX7_SET_MUX30_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX7_SET_MUX30_SHIFT    (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_A_STAGE2_MUX7_SET_MUX30(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_SET_MUX30_MASK)

#define PXP_WFE_A_STAGE2_MUX7_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX7_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX7_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX7_SET_MUX31_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX7_SET_MUX31_SHIFT    (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_A_STAGE2_MUX7_SET_MUX31(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_SET_MUX31_MASK)

#define PXP_WFE_A_STAGE2_MUX7_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX7_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX7_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX7_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX7_CLR_MUX28_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX7_CLR_MUX28_SHIFT    (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_A_STAGE2_MUX7_CLR_MUX28(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_CLR_MUX28_MASK)

#define PXP_WFE_A_STAGE2_MUX7_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX7_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX7_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX7_CLR_MUX29_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX7_CLR_MUX29_SHIFT    (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_A_STAGE2_MUX7_CLR_MUX29(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_CLR_MUX29_MASK)

#define PXP_WFE_A_STAGE2_MUX7_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX7_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX7_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX7_CLR_MUX30_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX7_CLR_MUX30_SHIFT    (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_A_STAGE2_MUX7_CLR_MUX30(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_CLR_MUX30_MASK)

#define PXP_WFE_A_STAGE2_MUX7_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX7_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX7_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX7_CLR_MUX31_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX7_CLR_MUX31_SHIFT    (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_A_STAGE2_MUX7_CLR_MUX31(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_CLR_MUX31_MASK)

#define PXP_WFE_A_STAGE2_MUX7_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX7_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX7_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX7_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX7_TOG_MUX28_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX7_TOG_MUX28_SHIFT    (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_A_STAGE2_MUX7_TOG_MUX28(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_TOG_MUX28_MASK)

#define PXP_WFE_A_STAGE2_MUX7_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX7_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX7_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX7_TOG_MUX29_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX7_TOG_MUX29_SHIFT    (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_A_STAGE2_MUX7_TOG_MUX29(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_TOG_MUX29_MASK)

#define PXP_WFE_A_STAGE2_MUX7_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX7_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX7_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX7_TOG_MUX30_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX7_TOG_MUX30_SHIFT    (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_A_STAGE2_MUX7_TOG_MUX30(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_TOG_MUX30_MASK)

#define PXP_WFE_A_STAGE2_MUX7_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX7_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX7_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX7_TOG_MUX31_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX7_TOG_MUX31_SHIFT    (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_A_STAGE2_MUX7_TOG_MUX31(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_TOG_MUX31_MASK)

#define PXP_WFE_A_STAGE2_MUX7_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX7_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX7_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX7_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX7_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX8 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX8_MUX32_MASK         (0x3FU)
#define PXP_WFE_A_STAGE2_MUX8_MUX32_SHIFT        (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_A_STAGE2_MUX8_MUX32(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_MUX32_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_MUX32_MASK)

#define PXP_WFE_A_STAGE2_MUX8_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE2_MUX8_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX8_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX8_MUX33_MASK         (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX8_MUX33_SHIFT        (8U)
/*! MUX33 - MUX33 */
#define PXP_WFE_A_STAGE2_MUX8_MUX33(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_MUX33_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_MUX33_MASK)

#define PXP_WFE_A_STAGE2_MUX8_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE2_MUX8_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX8_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX8_MUX34_MASK         (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX8_MUX34_SHIFT        (16U)
/*! MUX34 - MUX34 */
#define PXP_WFE_A_STAGE2_MUX8_MUX34(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_MUX34_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_MUX34_MASK)

#define PXP_WFE_A_STAGE2_MUX8_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX8_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX8_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX8_MUX35_MASK         (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX8_MUX35_SHIFT        (24U)
/*! MUX35 - MUX35 */
#define PXP_WFE_A_STAGE2_MUX8_MUX35(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_MUX35_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_MUX35_MASK)

#define PXP_WFE_A_STAGE2_MUX8_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX8_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX8_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX8_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX8_SET_MUX32_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX8_SET_MUX32_SHIFT    (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_A_STAGE2_MUX8_SET_MUX32(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_SET_MUX32_MASK)

#define PXP_WFE_A_STAGE2_MUX8_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX8_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX8_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX8_SET_MUX33_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX8_SET_MUX33_SHIFT    (8U)
/*! MUX33 - MUX33 */
#define PXP_WFE_A_STAGE2_MUX8_SET_MUX33(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_SET_MUX33_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_SET_MUX33_MASK)

#define PXP_WFE_A_STAGE2_MUX8_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX8_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX8_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX8_SET_MUX34_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX8_SET_MUX34_SHIFT    (16U)
/*! MUX34 - MUX34 */
#define PXP_WFE_A_STAGE2_MUX8_SET_MUX34(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_SET_MUX34_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_SET_MUX34_MASK)

#define PXP_WFE_A_STAGE2_MUX8_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX8_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX8_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX8_SET_MUX35_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX8_SET_MUX35_SHIFT    (24U)
/*! MUX35 - MUX35 */
#define PXP_WFE_A_STAGE2_MUX8_SET_MUX35(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_SET_MUX35_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_SET_MUX35_MASK)

#define PXP_WFE_A_STAGE2_MUX8_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX8_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX8_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX8_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX8_CLR_MUX32_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX8_CLR_MUX32_SHIFT    (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_A_STAGE2_MUX8_CLR_MUX32(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_CLR_MUX32_MASK)

#define PXP_WFE_A_STAGE2_MUX8_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX8_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX8_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX8_CLR_MUX33_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX8_CLR_MUX33_SHIFT    (8U)
/*! MUX33 - MUX33 */
#define PXP_WFE_A_STAGE2_MUX8_CLR_MUX33(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_CLR_MUX33_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_CLR_MUX33_MASK)

#define PXP_WFE_A_STAGE2_MUX8_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX8_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX8_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX8_CLR_MUX34_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX8_CLR_MUX34_SHIFT    (16U)
/*! MUX34 - MUX34 */
#define PXP_WFE_A_STAGE2_MUX8_CLR_MUX34(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_CLR_MUX34_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_CLR_MUX34_MASK)

#define PXP_WFE_A_STAGE2_MUX8_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX8_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX8_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX8_CLR_MUX35_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX8_CLR_MUX35_SHIFT    (24U)
/*! MUX35 - MUX35 */
#define PXP_WFE_A_STAGE2_MUX8_CLR_MUX35(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_CLR_MUX35_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_CLR_MUX35_MASK)

#define PXP_WFE_A_STAGE2_MUX8_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX8_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX8_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX8_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX8_TOG_MUX32_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX8_TOG_MUX32_SHIFT    (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_A_STAGE2_MUX8_TOG_MUX32(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_TOG_MUX32_MASK)

#define PXP_WFE_A_STAGE2_MUX8_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX8_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX8_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX8_TOG_MUX33_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX8_TOG_MUX33_SHIFT    (8U)
/*! MUX33 - MUX33 */
#define PXP_WFE_A_STAGE2_MUX8_TOG_MUX33(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_TOG_MUX33_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_TOG_MUX33_MASK)

#define PXP_WFE_A_STAGE2_MUX8_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX8_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX8_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX8_TOG_MUX34_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX8_TOG_MUX34_SHIFT    (16U)
/*! MUX34 - MUX34 */
#define PXP_WFE_A_STAGE2_MUX8_TOG_MUX34(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_TOG_MUX34_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_TOG_MUX34_MASK)

#define PXP_WFE_A_STAGE2_MUX8_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX8_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX8_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX8_TOG_MUX35_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX8_TOG_MUX35_SHIFT    (24U)
/*! MUX35 - MUX35 */
#define PXP_WFE_A_STAGE2_MUX8_TOG_MUX35(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_TOG_MUX35_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_TOG_MUX35_MASK)

#define PXP_WFE_A_STAGE2_MUX8_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX8_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX8_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX8_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX8_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX9 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX9_MUX36_MASK         (0x3FU)
#define PXP_WFE_A_STAGE2_MUX9_MUX36_SHIFT        (0U)
/*! MUX36 - MUX36 */
#define PXP_WFE_A_STAGE2_MUX9_MUX36(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_MUX36_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_MUX36_MASK)

#define PXP_WFE_A_STAGE2_MUX9_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE2_MUX9_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX9_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX9_MUX37_MASK         (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX9_MUX37_SHIFT        (8U)
/*! MUX37 - MUX37 */
#define PXP_WFE_A_STAGE2_MUX9_MUX37(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_MUX37_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_MUX37_MASK)

#define PXP_WFE_A_STAGE2_MUX9_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE2_MUX9_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX9_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX9_MUX38_MASK         (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX9_MUX38_SHIFT        (16U)
/*! MUX38 - MUX38 */
#define PXP_WFE_A_STAGE2_MUX9_MUX38(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_MUX38_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_MUX38_MASK)

#define PXP_WFE_A_STAGE2_MUX9_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX9_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX9_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX9_MUX39_MASK         (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX9_MUX39_SHIFT        (24U)
/*! MUX39 - MUX39 */
#define PXP_WFE_A_STAGE2_MUX9_MUX39(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_MUX39_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_MUX39_MASK)

#define PXP_WFE_A_STAGE2_MUX9_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX9_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX9_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX9_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX9_SET_MUX36_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX9_SET_MUX36_SHIFT    (0U)
/*! MUX36 - MUX36 */
#define PXP_WFE_A_STAGE2_MUX9_SET_MUX36(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_SET_MUX36_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_SET_MUX36_MASK)

#define PXP_WFE_A_STAGE2_MUX9_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX9_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX9_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX9_SET_MUX37_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX9_SET_MUX37_SHIFT    (8U)
/*! MUX37 - MUX37 */
#define PXP_WFE_A_STAGE2_MUX9_SET_MUX37(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_SET_MUX37_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_SET_MUX37_MASK)

#define PXP_WFE_A_STAGE2_MUX9_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX9_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX9_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX9_SET_MUX38_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX9_SET_MUX38_SHIFT    (16U)
/*! MUX38 - MUX38 */
#define PXP_WFE_A_STAGE2_MUX9_SET_MUX38(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_SET_MUX38_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_SET_MUX38_MASK)

#define PXP_WFE_A_STAGE2_MUX9_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX9_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX9_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX9_SET_MUX39_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX9_SET_MUX39_SHIFT    (24U)
/*! MUX39 - MUX39 */
#define PXP_WFE_A_STAGE2_MUX9_SET_MUX39(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_SET_MUX39_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_SET_MUX39_MASK)

#define PXP_WFE_A_STAGE2_MUX9_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX9_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX9_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX9_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX9_CLR_MUX36_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX9_CLR_MUX36_SHIFT    (0U)
/*! MUX36 - MUX36 */
#define PXP_WFE_A_STAGE2_MUX9_CLR_MUX36(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_CLR_MUX36_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_CLR_MUX36_MASK)

#define PXP_WFE_A_STAGE2_MUX9_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX9_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX9_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX9_CLR_MUX37_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX9_CLR_MUX37_SHIFT    (8U)
/*! MUX37 - MUX37 */
#define PXP_WFE_A_STAGE2_MUX9_CLR_MUX37(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_CLR_MUX37_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_CLR_MUX37_MASK)

#define PXP_WFE_A_STAGE2_MUX9_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX9_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX9_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX9_CLR_MUX38_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX9_CLR_MUX38_SHIFT    (16U)
/*! MUX38 - MUX38 */
#define PXP_WFE_A_STAGE2_MUX9_CLR_MUX38(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_CLR_MUX38_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_CLR_MUX38_MASK)

#define PXP_WFE_A_STAGE2_MUX9_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX9_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX9_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX9_CLR_MUX39_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX9_CLR_MUX39_SHIFT    (24U)
/*! MUX39 - MUX39 */
#define PXP_WFE_A_STAGE2_MUX9_CLR_MUX39(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_CLR_MUX39_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_CLR_MUX39_MASK)

#define PXP_WFE_A_STAGE2_MUX9_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX9_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX9_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX9_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX9_TOG_MUX36_MASK     (0x3FU)
#define PXP_WFE_A_STAGE2_MUX9_TOG_MUX36_SHIFT    (0U)
/*! MUX36 - MUX36 */
#define PXP_WFE_A_STAGE2_MUX9_TOG_MUX36(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_TOG_MUX36_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_TOG_MUX36_MASK)

#define PXP_WFE_A_STAGE2_MUX9_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE2_MUX9_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX9_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX9_TOG_MUX37_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX9_TOG_MUX37_SHIFT    (8U)
/*! MUX37 - MUX37 */
#define PXP_WFE_A_STAGE2_MUX9_TOG_MUX37(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_TOG_MUX37_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_TOG_MUX37_MASK)

#define PXP_WFE_A_STAGE2_MUX9_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE2_MUX9_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX9_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX9_TOG_MUX38_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX9_TOG_MUX38_SHIFT    (16U)
/*! MUX38 - MUX38 */
#define PXP_WFE_A_STAGE2_MUX9_TOG_MUX38(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_TOG_MUX38_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_TOG_MUX38_MASK)

#define PXP_WFE_A_STAGE2_MUX9_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX9_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX9_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX9_TOG_MUX39_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX9_TOG_MUX39_SHIFT    (24U)
/*! MUX39 - MUX39 */
#define PXP_WFE_A_STAGE2_MUX9_TOG_MUX39(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_TOG_MUX39_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_TOG_MUX39_MASK)

#define PXP_WFE_A_STAGE2_MUX9_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX9_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX9_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX9_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX9_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX10 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX10_MUX40_MASK        (0x3FU)
#define PXP_WFE_A_STAGE2_MUX10_MUX40_SHIFT       (0U)
/*! MUX40 - MUX40
 *  0b000000..INC : Increment operation.
 *  0b000001..DEC : Decrement operation.
 *  0b000010..ADD : Addition operation.
 *  0b000011..MINUS : Subtraction operation.
 *  0b000100..AND : Bitwise AND operation. A AND B.
 *  0b000101..OR : Bitwise OR operation. A OR B.
 *  0b000110..XOR : Bitwise XOR operation. A XOR B.
 *  0b000111..SHIFTLEFT : Shift A operand left by B operand places.
 *  0b001000..SHIFTRIGHT : Shift A operand right by B operand places.
 *  0b001001..BIT_AND : Reduction AND operation on A operand.
 *  0b001010..BIT_OR : Reduction OR operation on A operand.
 *  0b001011..BIT_CMP : Compare A and B operands and set equal flag if A and B are equal. All other output is 0.
 *  0b001100..NOP : No operation. All outputs are 0.
 */
#define PXP_WFE_A_STAGE2_MUX10_MUX40(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_MUX40_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_MUX40_MASK)

#define PXP_WFE_A_STAGE2_MUX10_RSVD3_MASK        (0xC0U)
#define PXP_WFE_A_STAGE2_MUX10_RSVD3_SHIFT       (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX10_RSVD3(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX10_MUX41_MASK        (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX10_MUX41_SHIFT       (8U)
/*! MUX41 - MUX41 */
#define PXP_WFE_A_STAGE2_MUX10_MUX41(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_MUX41_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_MUX41_MASK)

#define PXP_WFE_A_STAGE2_MUX10_RSVD2_MASK        (0xC000U)
#define PXP_WFE_A_STAGE2_MUX10_RSVD2_SHIFT       (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX10_RSVD2(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX10_MUX42_MASK        (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX10_MUX42_SHIFT       (16U)
/*! MUX42 - MUX42 */
#define PXP_WFE_A_STAGE2_MUX10_MUX42(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_MUX42_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_MUX42_MASK)

#define PXP_WFE_A_STAGE2_MUX10_RSVD1_MASK        (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX10_RSVD1_SHIFT       (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX10_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX10_MUX43_MASK        (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX10_MUX43_SHIFT       (24U)
/*! MUX43 - MUX43
 *  0b000000..INC : Increment operation.
 *  0b000001..DEC : Decrement operation.
 *  0b000010..ADD : Addition operation.
 *  0b000011..MINUS : Subtraction operation.
 *  0b000100..AND : Bitwise AND operation. A AND B.
 *  0b000101..OR : Bitwise OR operation. A OR B.
 *  0b000110..XOR : Bitwise XOR operation. A XOR B.
 *  0b000111..SHIFTLEFT : Shift A operand left by B operand places.
 *  0b001000..SHIFTRIGHT : Shift A operand right by B operand places.
 *  0b001001..BIT_AND : Reduction AND operation on A operand.
 *  0b001010..BIT_OR : Reduction OR operation on A operand.
 *  0b001011..BIT_CMP : Compare A and B operands and set equal flag if A and B are equal. All other output is 0.
 *  0b001100..NOP : No operation. All outputs are 0.
 */
#define PXP_WFE_A_STAGE2_MUX10_MUX43(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_MUX43_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_MUX43_MASK)

#define PXP_WFE_A_STAGE2_MUX10_RSVD0_MASK        (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX10_RSVD0_SHIFT       (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX10_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX10_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX10_SET_MUX40_MASK    (0x3FU)
#define PXP_WFE_A_STAGE2_MUX10_SET_MUX40_SHIFT   (0U)
/*! MUX40 - MUX40 */
#define PXP_WFE_A_STAGE2_MUX10_SET_MUX40(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_SET_MUX40_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_SET_MUX40_MASK)

#define PXP_WFE_A_STAGE2_MUX10_SET_RSVD3_MASK    (0xC0U)
#define PXP_WFE_A_STAGE2_MUX10_SET_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX10_SET_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX10_SET_MUX41_MASK    (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX10_SET_MUX41_SHIFT   (8U)
/*! MUX41 - MUX41 */
#define PXP_WFE_A_STAGE2_MUX10_SET_MUX41(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_SET_MUX41_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_SET_MUX41_MASK)

#define PXP_WFE_A_STAGE2_MUX10_SET_RSVD2_MASK    (0xC000U)
#define PXP_WFE_A_STAGE2_MUX10_SET_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX10_SET_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX10_SET_MUX42_MASK    (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX10_SET_MUX42_SHIFT   (16U)
/*! MUX42 - MUX42 */
#define PXP_WFE_A_STAGE2_MUX10_SET_MUX42(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_SET_MUX42_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_SET_MUX42_MASK)

#define PXP_WFE_A_STAGE2_MUX10_SET_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX10_SET_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX10_SET_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX10_SET_MUX43_MASK    (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX10_SET_MUX43_SHIFT   (24U)
/*! MUX43 - MUX43 */
#define PXP_WFE_A_STAGE2_MUX10_SET_MUX43(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_SET_MUX43_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_SET_MUX43_MASK)

#define PXP_WFE_A_STAGE2_MUX10_SET_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX10_SET_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX10_SET_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX10_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX10_CLR_MUX40_MASK    (0x3FU)
#define PXP_WFE_A_STAGE2_MUX10_CLR_MUX40_SHIFT   (0U)
/*! MUX40 - MUX40 */
#define PXP_WFE_A_STAGE2_MUX10_CLR_MUX40(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_CLR_MUX40_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_CLR_MUX40_MASK)

#define PXP_WFE_A_STAGE2_MUX10_CLR_RSVD3_MASK    (0xC0U)
#define PXP_WFE_A_STAGE2_MUX10_CLR_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX10_CLR_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX10_CLR_MUX41_MASK    (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX10_CLR_MUX41_SHIFT   (8U)
/*! MUX41 - MUX41 */
#define PXP_WFE_A_STAGE2_MUX10_CLR_MUX41(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_CLR_MUX41_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_CLR_MUX41_MASK)

#define PXP_WFE_A_STAGE2_MUX10_CLR_RSVD2_MASK    (0xC000U)
#define PXP_WFE_A_STAGE2_MUX10_CLR_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX10_CLR_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX10_CLR_MUX42_MASK    (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX10_CLR_MUX42_SHIFT   (16U)
/*! MUX42 - MUX42 */
#define PXP_WFE_A_STAGE2_MUX10_CLR_MUX42(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_CLR_MUX42_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_CLR_MUX42_MASK)

#define PXP_WFE_A_STAGE2_MUX10_CLR_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX10_CLR_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX10_CLR_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX10_CLR_MUX43_MASK    (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX10_CLR_MUX43_SHIFT   (24U)
/*! MUX43 - MUX43 */
#define PXP_WFE_A_STAGE2_MUX10_CLR_MUX43(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_CLR_MUX43_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_CLR_MUX43_MASK)

#define PXP_WFE_A_STAGE2_MUX10_CLR_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX10_CLR_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX10_CLR_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX10_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX10_TOG_MUX40_MASK    (0x3FU)
#define PXP_WFE_A_STAGE2_MUX10_TOG_MUX40_SHIFT   (0U)
/*! MUX40 - MUX40 */
#define PXP_WFE_A_STAGE2_MUX10_TOG_MUX40(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_TOG_MUX40_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_TOG_MUX40_MASK)

#define PXP_WFE_A_STAGE2_MUX10_TOG_RSVD3_MASK    (0xC0U)
#define PXP_WFE_A_STAGE2_MUX10_TOG_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX10_TOG_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX10_TOG_MUX41_MASK    (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX10_TOG_MUX41_SHIFT   (8U)
/*! MUX41 - MUX41 */
#define PXP_WFE_A_STAGE2_MUX10_TOG_MUX41(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_TOG_MUX41_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_TOG_MUX41_MASK)

#define PXP_WFE_A_STAGE2_MUX10_TOG_RSVD2_MASK    (0xC000U)
#define PXP_WFE_A_STAGE2_MUX10_TOG_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX10_TOG_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX10_TOG_MUX42_MASK    (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX10_TOG_MUX42_SHIFT   (16U)
/*! MUX42 - MUX42 */
#define PXP_WFE_A_STAGE2_MUX10_TOG_MUX42(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_TOG_MUX42_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_TOG_MUX42_MASK)

#define PXP_WFE_A_STAGE2_MUX10_TOG_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX10_TOG_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX10_TOG_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX10_TOG_MUX43_MASK    (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX10_TOG_MUX43_SHIFT   (24U)
/*! MUX43 - MUX43 */
#define PXP_WFE_A_STAGE2_MUX10_TOG_MUX43(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_TOG_MUX43_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_TOG_MUX43_MASK)

#define PXP_WFE_A_STAGE2_MUX10_TOG_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX10_TOG_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX10_TOG_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX10_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX10_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX11 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX11_MUX44_MASK        (0x3FU)
#define PXP_WFE_A_STAGE2_MUX11_MUX44_SHIFT       (0U)
/*! MUX44 - MUX44 */
#define PXP_WFE_A_STAGE2_MUX11_MUX44(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_MUX44_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_MUX44_MASK)

#define PXP_WFE_A_STAGE2_MUX11_RSVD3_MASK        (0xC0U)
#define PXP_WFE_A_STAGE2_MUX11_RSVD3_SHIFT       (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX11_RSVD3(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX11_MUX45_MASK        (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX11_MUX45_SHIFT       (8U)
/*! MUX45 - MUX45 */
#define PXP_WFE_A_STAGE2_MUX11_MUX45(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_MUX45_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_MUX45_MASK)

#define PXP_WFE_A_STAGE2_MUX11_RSVD2_MASK        (0xC000U)
#define PXP_WFE_A_STAGE2_MUX11_RSVD2_SHIFT       (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX11_RSVD2(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX11_MUX46_MASK        (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX11_MUX46_SHIFT       (16U)
/*! MUX46 - MUX46 */
#define PXP_WFE_A_STAGE2_MUX11_MUX46(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_MUX46_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_MUX46_MASK)

#define PXP_WFE_A_STAGE2_MUX11_RSVD1_MASK        (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX11_RSVD1_SHIFT       (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX11_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX11_MUX47_MASK        (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX11_MUX47_SHIFT       (24U)
/*! MUX47 - MUX47 */
#define PXP_WFE_A_STAGE2_MUX11_MUX47(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_MUX47_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_MUX47_MASK)

#define PXP_WFE_A_STAGE2_MUX11_RSVD0_MASK        (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX11_RSVD0_SHIFT       (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX11_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX11_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX11_SET_MUX44_MASK    (0x3FU)
#define PXP_WFE_A_STAGE2_MUX11_SET_MUX44_SHIFT   (0U)
/*! MUX44 - MUX44 */
#define PXP_WFE_A_STAGE2_MUX11_SET_MUX44(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_SET_MUX44_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_SET_MUX44_MASK)

#define PXP_WFE_A_STAGE2_MUX11_SET_RSVD3_MASK    (0xC0U)
#define PXP_WFE_A_STAGE2_MUX11_SET_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX11_SET_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX11_SET_MUX45_MASK    (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX11_SET_MUX45_SHIFT   (8U)
/*! MUX45 - MUX45 */
#define PXP_WFE_A_STAGE2_MUX11_SET_MUX45(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_SET_MUX45_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_SET_MUX45_MASK)

#define PXP_WFE_A_STAGE2_MUX11_SET_RSVD2_MASK    (0xC000U)
#define PXP_WFE_A_STAGE2_MUX11_SET_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX11_SET_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX11_SET_MUX46_MASK    (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX11_SET_MUX46_SHIFT   (16U)
/*! MUX46 - MUX46 */
#define PXP_WFE_A_STAGE2_MUX11_SET_MUX46(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_SET_MUX46_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_SET_MUX46_MASK)

#define PXP_WFE_A_STAGE2_MUX11_SET_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX11_SET_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX11_SET_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX11_SET_MUX47_MASK    (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX11_SET_MUX47_SHIFT   (24U)
/*! MUX47 - MUX47 */
#define PXP_WFE_A_STAGE2_MUX11_SET_MUX47(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_SET_MUX47_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_SET_MUX47_MASK)

#define PXP_WFE_A_STAGE2_MUX11_SET_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX11_SET_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX11_SET_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX11_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX11_CLR_MUX44_MASK    (0x3FU)
#define PXP_WFE_A_STAGE2_MUX11_CLR_MUX44_SHIFT   (0U)
/*! MUX44 - MUX44 */
#define PXP_WFE_A_STAGE2_MUX11_CLR_MUX44(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_CLR_MUX44_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_CLR_MUX44_MASK)

#define PXP_WFE_A_STAGE2_MUX11_CLR_RSVD3_MASK    (0xC0U)
#define PXP_WFE_A_STAGE2_MUX11_CLR_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX11_CLR_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX11_CLR_MUX45_MASK    (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX11_CLR_MUX45_SHIFT   (8U)
/*! MUX45 - MUX45 */
#define PXP_WFE_A_STAGE2_MUX11_CLR_MUX45(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_CLR_MUX45_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_CLR_MUX45_MASK)

#define PXP_WFE_A_STAGE2_MUX11_CLR_RSVD2_MASK    (0xC000U)
#define PXP_WFE_A_STAGE2_MUX11_CLR_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX11_CLR_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX11_CLR_MUX46_MASK    (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX11_CLR_MUX46_SHIFT   (16U)
/*! MUX46 - MUX46 */
#define PXP_WFE_A_STAGE2_MUX11_CLR_MUX46(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_CLR_MUX46_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_CLR_MUX46_MASK)

#define PXP_WFE_A_STAGE2_MUX11_CLR_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX11_CLR_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX11_CLR_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX11_CLR_MUX47_MASK    (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX11_CLR_MUX47_SHIFT   (24U)
/*! MUX47 - MUX47 */
#define PXP_WFE_A_STAGE2_MUX11_CLR_MUX47(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_CLR_MUX47_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_CLR_MUX47_MASK)

#define PXP_WFE_A_STAGE2_MUX11_CLR_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX11_CLR_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX11_CLR_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX11_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX11_TOG_MUX44_MASK    (0x3FU)
#define PXP_WFE_A_STAGE2_MUX11_TOG_MUX44_SHIFT   (0U)
/*! MUX44 - MUX44 */
#define PXP_WFE_A_STAGE2_MUX11_TOG_MUX44(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_TOG_MUX44_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_TOG_MUX44_MASK)

#define PXP_WFE_A_STAGE2_MUX11_TOG_RSVD3_MASK    (0xC0U)
#define PXP_WFE_A_STAGE2_MUX11_TOG_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX11_TOG_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX11_TOG_MUX45_MASK    (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX11_TOG_MUX45_SHIFT   (8U)
/*! MUX45 - MUX45 */
#define PXP_WFE_A_STAGE2_MUX11_TOG_MUX45(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_TOG_MUX45_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_TOG_MUX45_MASK)

#define PXP_WFE_A_STAGE2_MUX11_TOG_RSVD2_MASK    (0xC000U)
#define PXP_WFE_A_STAGE2_MUX11_TOG_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_MUX11_TOG_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_MUX11_TOG_MUX46_MASK    (0x3F0000U)
#define PXP_WFE_A_STAGE2_MUX11_TOG_MUX46_SHIFT   (16U)
/*! MUX46 - MUX46 */
#define PXP_WFE_A_STAGE2_MUX11_TOG_MUX46(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_TOG_MUX46_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_TOG_MUX46_MASK)

#define PXP_WFE_A_STAGE2_MUX11_TOG_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_A_STAGE2_MUX11_TOG_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_MUX11_TOG_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_MUX11_TOG_MUX47_MASK    (0x3F000000U)
#define PXP_WFE_A_STAGE2_MUX11_TOG_MUX47_SHIFT   (24U)
/*! MUX47 - MUX47 */
#define PXP_WFE_A_STAGE2_MUX11_TOG_MUX47(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_TOG_MUX47_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_TOG_MUX47_MASK)

#define PXP_WFE_A_STAGE2_MUX11_TOG_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_A_STAGE2_MUX11_TOG_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX11_TOG_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX11_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX11_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX12 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX12_MUX48_MASK        (0x3FU)
#define PXP_WFE_A_STAGE2_MUX12_MUX48_SHIFT       (0U)
/*! MUX48 - MUX48 */
#define PXP_WFE_A_STAGE2_MUX12_MUX48(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_MUX48_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_MUX48_MASK)

#define PXP_WFE_A_STAGE2_MUX12_RSVD3_MASK        (0xC0U)
#define PXP_WFE_A_STAGE2_MUX12_RSVD3_SHIFT       (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX12_RSVD3(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX12_MUX49_MASK        (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX12_MUX49_SHIFT       (8U)
/*! MUX49 - MUX49 */
#define PXP_WFE_A_STAGE2_MUX12_MUX49(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_MUX49_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_MUX49_MASK)

#define PXP_WFE_A_STAGE2_MUX12_RSVD0_MASK        (0xFFFFC000U)
#define PXP_WFE_A_STAGE2_MUX12_RSVD0_SHIFT       (14U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX12_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX12_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX12_SET_MUX48_MASK    (0x3FU)
#define PXP_WFE_A_STAGE2_MUX12_SET_MUX48_SHIFT   (0U)
/*! MUX48 - MUX48 */
#define PXP_WFE_A_STAGE2_MUX12_SET_MUX48(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_SET_MUX48_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_SET_MUX48_MASK)

#define PXP_WFE_A_STAGE2_MUX12_SET_RSVD3_MASK    (0xC0U)
#define PXP_WFE_A_STAGE2_MUX12_SET_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX12_SET_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX12_SET_MUX49_MASK    (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX12_SET_MUX49_SHIFT   (8U)
/*! MUX49 - MUX49 */
#define PXP_WFE_A_STAGE2_MUX12_SET_MUX49(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_SET_MUX49_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_SET_MUX49_MASK)

#define PXP_WFE_A_STAGE2_MUX12_SET_RSVD0_MASK    (0xFFFFC000U)
#define PXP_WFE_A_STAGE2_MUX12_SET_RSVD0_SHIFT   (14U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX12_SET_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX12_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX12_CLR_MUX48_MASK    (0x3FU)
#define PXP_WFE_A_STAGE2_MUX12_CLR_MUX48_SHIFT   (0U)
/*! MUX48 - MUX48 */
#define PXP_WFE_A_STAGE2_MUX12_CLR_MUX48(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_CLR_MUX48_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_CLR_MUX48_MASK)

#define PXP_WFE_A_STAGE2_MUX12_CLR_RSVD3_MASK    (0xC0U)
#define PXP_WFE_A_STAGE2_MUX12_CLR_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX12_CLR_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX12_CLR_MUX49_MASK    (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX12_CLR_MUX49_SHIFT   (8U)
/*! MUX49 - MUX49 */
#define PXP_WFE_A_STAGE2_MUX12_CLR_MUX49(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_CLR_MUX49_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_CLR_MUX49_MASK)

#define PXP_WFE_A_STAGE2_MUX12_CLR_RSVD0_MASK    (0xFFFFC000U)
#define PXP_WFE_A_STAGE2_MUX12_CLR_RSVD0_SHIFT   (14U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX12_CLR_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_MUX12_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_MUX12_TOG_MUX48_MASK    (0x3FU)
#define PXP_WFE_A_STAGE2_MUX12_TOG_MUX48_SHIFT   (0U)
/*! MUX48 - MUX48 */
#define PXP_WFE_A_STAGE2_MUX12_TOG_MUX48(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_TOG_MUX48_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_TOG_MUX48_MASK)

#define PXP_WFE_A_STAGE2_MUX12_TOG_RSVD3_MASK    (0xC0U)
#define PXP_WFE_A_STAGE2_MUX12_TOG_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_MUX12_TOG_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_MUX12_TOG_MUX49_MASK    (0x3F00U)
#define PXP_WFE_A_STAGE2_MUX12_TOG_MUX49_SHIFT   (8U)
/*! MUX49 - MUX49 */
#define PXP_WFE_A_STAGE2_MUX12_TOG_MUX49(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_TOG_MUX49_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_TOG_MUX49_MASK)

#define PXP_WFE_A_STAGE2_MUX12_TOG_RSVD0_MASK    (0xFFFFC000U)
#define PXP_WFE_A_STAGE2_MUX12_TOG_RSVD0_SHIFT   (14U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_MUX12_TOG_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_MUX12_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_MUX12_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX0 -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX0_MUX0_MASK          (0x3FU)
#define PXP_WFE_A_STAGE3_MUX0_MUX0_SHIFT         (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_A_STAGE3_MUX0_MUX0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_MUX0_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_MUX0_MASK)

#define PXP_WFE_A_STAGE3_MUX0_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE3_MUX0_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX0_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX0_MUX1_MASK          (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX0_MUX1_SHIFT         (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_A_STAGE3_MUX0_MUX1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_MUX1_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_MUX1_MASK)

#define PXP_WFE_A_STAGE3_MUX0_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE3_MUX0_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX0_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX0_MUX2_MASK          (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX0_MUX2_SHIFT         (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_A_STAGE3_MUX0_MUX2(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_MUX2_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_MUX2_MASK)

#define PXP_WFE_A_STAGE3_MUX0_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX0_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX0_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX0_MUX3_MASK          (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX0_MUX3_SHIFT         (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_A_STAGE3_MUX0_MUX3(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_MUX3_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_MUX3_MASK)

#define PXP_WFE_A_STAGE3_MUX0_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX0_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX0_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX0_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX0_SET_MUX0_MASK      (0x3FU)
#define PXP_WFE_A_STAGE3_MUX0_SET_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_A_STAGE3_MUX0_SET_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_SET_MUX0_MASK)

#define PXP_WFE_A_STAGE3_MUX0_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE3_MUX0_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX0_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX0_SET_MUX1_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX0_SET_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_A_STAGE3_MUX0_SET_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_SET_MUX1_MASK)

#define PXP_WFE_A_STAGE3_MUX0_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE3_MUX0_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX0_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX0_SET_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX0_SET_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_A_STAGE3_MUX0_SET_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_SET_MUX2_MASK)

#define PXP_WFE_A_STAGE3_MUX0_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX0_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX0_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX0_SET_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX0_SET_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_A_STAGE3_MUX0_SET_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_SET_MUX3_MASK)

#define PXP_WFE_A_STAGE3_MUX0_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX0_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX0_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX0_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX0_CLR_MUX0_MASK      (0x3FU)
#define PXP_WFE_A_STAGE3_MUX0_CLR_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_A_STAGE3_MUX0_CLR_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_CLR_MUX0_MASK)

#define PXP_WFE_A_STAGE3_MUX0_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE3_MUX0_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX0_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX0_CLR_MUX1_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX0_CLR_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_A_STAGE3_MUX0_CLR_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_CLR_MUX1_MASK)

#define PXP_WFE_A_STAGE3_MUX0_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE3_MUX0_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX0_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX0_CLR_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX0_CLR_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_A_STAGE3_MUX0_CLR_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_CLR_MUX2_MASK)

#define PXP_WFE_A_STAGE3_MUX0_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX0_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX0_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX0_CLR_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX0_CLR_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_A_STAGE3_MUX0_CLR_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_CLR_MUX3_MASK)

#define PXP_WFE_A_STAGE3_MUX0_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX0_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX0_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX0_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX0_TOG_MUX0_MASK      (0x3FU)
#define PXP_WFE_A_STAGE3_MUX0_TOG_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_A_STAGE3_MUX0_TOG_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_TOG_MUX0_MASK)

#define PXP_WFE_A_STAGE3_MUX0_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE3_MUX0_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX0_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX0_TOG_MUX1_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX0_TOG_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_A_STAGE3_MUX0_TOG_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_TOG_MUX1_MASK)

#define PXP_WFE_A_STAGE3_MUX0_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE3_MUX0_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX0_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX0_TOG_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX0_TOG_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_A_STAGE3_MUX0_TOG_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_TOG_MUX2_MASK)

#define PXP_WFE_A_STAGE3_MUX0_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX0_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX0_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX0_TOG_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX0_TOG_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_A_STAGE3_MUX0_TOG_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_TOG_MUX3_MASK)

#define PXP_WFE_A_STAGE3_MUX0_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX0_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX0_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX0_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX0_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX1 -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX1_MUX4_MASK          (0x3FU)
#define PXP_WFE_A_STAGE3_MUX1_MUX4_SHIFT         (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_A_STAGE3_MUX1_MUX4(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_MUX4_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_MUX4_MASK)

#define PXP_WFE_A_STAGE3_MUX1_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE3_MUX1_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX1_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX1_MUX5_MASK          (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX1_MUX5_SHIFT         (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_A_STAGE3_MUX1_MUX5(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_MUX5_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_MUX5_MASK)

#define PXP_WFE_A_STAGE3_MUX1_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE3_MUX1_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX1_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX1_MUX6_MASK          (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX1_MUX6_SHIFT         (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_A_STAGE3_MUX1_MUX6(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_MUX6_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_MUX6_MASK)

#define PXP_WFE_A_STAGE3_MUX1_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX1_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX1_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX1_MUX7_MASK          (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX1_MUX7_SHIFT         (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_A_STAGE3_MUX1_MUX7(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_MUX7_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_MUX7_MASK)

#define PXP_WFE_A_STAGE3_MUX1_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX1_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX1_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX1_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX1_SET_MUX4_MASK      (0x3FU)
#define PXP_WFE_A_STAGE3_MUX1_SET_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_A_STAGE3_MUX1_SET_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_SET_MUX4_MASK)

#define PXP_WFE_A_STAGE3_MUX1_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE3_MUX1_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX1_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX1_SET_MUX5_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX1_SET_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_A_STAGE3_MUX1_SET_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_SET_MUX5_MASK)

#define PXP_WFE_A_STAGE3_MUX1_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE3_MUX1_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX1_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX1_SET_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX1_SET_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_A_STAGE3_MUX1_SET_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_SET_MUX6_MASK)

#define PXP_WFE_A_STAGE3_MUX1_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX1_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX1_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX1_SET_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX1_SET_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_A_STAGE3_MUX1_SET_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_SET_MUX7_MASK)

#define PXP_WFE_A_STAGE3_MUX1_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX1_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX1_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX1_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX1_CLR_MUX4_MASK      (0x3FU)
#define PXP_WFE_A_STAGE3_MUX1_CLR_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_A_STAGE3_MUX1_CLR_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_CLR_MUX4_MASK)

#define PXP_WFE_A_STAGE3_MUX1_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE3_MUX1_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX1_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX1_CLR_MUX5_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX1_CLR_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_A_STAGE3_MUX1_CLR_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_CLR_MUX5_MASK)

#define PXP_WFE_A_STAGE3_MUX1_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE3_MUX1_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX1_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX1_CLR_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX1_CLR_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_A_STAGE3_MUX1_CLR_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_CLR_MUX6_MASK)

#define PXP_WFE_A_STAGE3_MUX1_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX1_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX1_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX1_CLR_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX1_CLR_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_A_STAGE3_MUX1_CLR_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_CLR_MUX7_MASK)

#define PXP_WFE_A_STAGE3_MUX1_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX1_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX1_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX1_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX1_TOG_MUX4_MASK      (0x3FU)
#define PXP_WFE_A_STAGE3_MUX1_TOG_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_A_STAGE3_MUX1_TOG_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_TOG_MUX4_MASK)

#define PXP_WFE_A_STAGE3_MUX1_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE3_MUX1_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX1_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX1_TOG_MUX5_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX1_TOG_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_A_STAGE3_MUX1_TOG_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_TOG_MUX5_MASK)

#define PXP_WFE_A_STAGE3_MUX1_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE3_MUX1_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX1_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX1_TOG_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX1_TOG_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_A_STAGE3_MUX1_TOG_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_TOG_MUX6_MASK)

#define PXP_WFE_A_STAGE3_MUX1_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX1_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX1_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX1_TOG_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX1_TOG_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_A_STAGE3_MUX1_TOG_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_TOG_MUX7_MASK)

#define PXP_WFE_A_STAGE3_MUX1_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX1_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX1_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX1_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX1_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX2 -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX2_MUX8_MASK          (0x3FU)
#define PXP_WFE_A_STAGE3_MUX2_MUX8_SHIFT         (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_A_STAGE3_MUX2_MUX8(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_MUX8_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_MUX8_MASK)

#define PXP_WFE_A_STAGE3_MUX2_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE3_MUX2_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX2_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX2_MUX9_MASK          (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX2_MUX9_SHIFT         (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_A_STAGE3_MUX2_MUX9(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_MUX9_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_MUX9_MASK)

#define PXP_WFE_A_STAGE3_MUX2_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE3_MUX2_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX2_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX2_MUX10_MASK         (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX2_MUX10_SHIFT        (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_A_STAGE3_MUX2_MUX10(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_MUX10_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_MUX10_MASK)

#define PXP_WFE_A_STAGE3_MUX2_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX2_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX2_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX2_MUX11_MASK         (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX2_MUX11_SHIFT        (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_A_STAGE3_MUX2_MUX11(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_MUX11_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_MUX11_MASK)

#define PXP_WFE_A_STAGE3_MUX2_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX2_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX2_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX2_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX2_SET_MUX8_MASK      (0x3FU)
#define PXP_WFE_A_STAGE3_MUX2_SET_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_A_STAGE3_MUX2_SET_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_SET_MUX8_MASK)

#define PXP_WFE_A_STAGE3_MUX2_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE3_MUX2_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX2_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX2_SET_MUX9_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX2_SET_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_A_STAGE3_MUX2_SET_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_SET_MUX9_MASK)

#define PXP_WFE_A_STAGE3_MUX2_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE3_MUX2_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX2_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX2_SET_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX2_SET_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_A_STAGE3_MUX2_SET_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_SET_MUX10_MASK)

#define PXP_WFE_A_STAGE3_MUX2_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX2_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX2_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX2_SET_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX2_SET_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_A_STAGE3_MUX2_SET_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_SET_MUX11_MASK)

#define PXP_WFE_A_STAGE3_MUX2_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX2_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX2_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX2_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX2_CLR_MUX8_MASK      (0x3FU)
#define PXP_WFE_A_STAGE3_MUX2_CLR_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_A_STAGE3_MUX2_CLR_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_CLR_MUX8_MASK)

#define PXP_WFE_A_STAGE3_MUX2_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE3_MUX2_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX2_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX2_CLR_MUX9_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX2_CLR_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_A_STAGE3_MUX2_CLR_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_CLR_MUX9_MASK)

#define PXP_WFE_A_STAGE3_MUX2_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE3_MUX2_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX2_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX2_CLR_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX2_CLR_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_A_STAGE3_MUX2_CLR_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_CLR_MUX10_MASK)

#define PXP_WFE_A_STAGE3_MUX2_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX2_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX2_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX2_CLR_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX2_CLR_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_A_STAGE3_MUX2_CLR_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_CLR_MUX11_MASK)

#define PXP_WFE_A_STAGE3_MUX2_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX2_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX2_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX2_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX2_TOG_MUX8_MASK      (0x3FU)
#define PXP_WFE_A_STAGE3_MUX2_TOG_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_A_STAGE3_MUX2_TOG_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_TOG_MUX8_MASK)

#define PXP_WFE_A_STAGE3_MUX2_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE3_MUX2_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX2_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX2_TOG_MUX9_MASK      (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX2_TOG_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_A_STAGE3_MUX2_TOG_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_TOG_MUX9_MASK)

#define PXP_WFE_A_STAGE3_MUX2_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE3_MUX2_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX2_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX2_TOG_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX2_TOG_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_A_STAGE3_MUX2_TOG_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_TOG_MUX10_MASK)

#define PXP_WFE_A_STAGE3_MUX2_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX2_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX2_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX2_TOG_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX2_TOG_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_A_STAGE3_MUX2_TOG_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_TOG_MUX11_MASK)

#define PXP_WFE_A_STAGE3_MUX2_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX2_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX2_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX2_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX2_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX3 -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX3_MUX12_MASK         (0x3FU)
#define PXP_WFE_A_STAGE3_MUX3_MUX12_SHIFT        (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_A_STAGE3_MUX3_MUX12(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_MUX12_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_MUX12_MASK)

#define PXP_WFE_A_STAGE3_MUX3_RSVD3_MASK         (0xC0U)
#define PXP_WFE_A_STAGE3_MUX3_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX3_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX3_MUX13_MASK         (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX3_MUX13_SHIFT        (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_A_STAGE3_MUX3_MUX13(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_MUX13_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_MUX13_MASK)

#define PXP_WFE_A_STAGE3_MUX3_RSVD2_MASK         (0xC000U)
#define PXP_WFE_A_STAGE3_MUX3_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX3_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX3_MUX14_MASK         (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX3_MUX14_SHIFT        (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_A_STAGE3_MUX3_MUX14(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_MUX14_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_MUX14_MASK)

#define PXP_WFE_A_STAGE3_MUX3_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX3_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX3_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX3_MUX15_MASK         (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX3_MUX15_SHIFT        (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_A_STAGE3_MUX3_MUX15(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_MUX15_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_MUX15_MASK)

#define PXP_WFE_A_STAGE3_MUX3_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX3_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX3_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX3_SET -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX3_SET_MUX12_MASK     (0x3FU)
#define PXP_WFE_A_STAGE3_MUX3_SET_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_A_STAGE3_MUX3_SET_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_SET_MUX12_MASK)

#define PXP_WFE_A_STAGE3_MUX3_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE3_MUX3_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX3_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_SET_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_SET_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX3_SET_MUX13_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX3_SET_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_A_STAGE3_MUX3_SET_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_SET_MUX13_MASK)

#define PXP_WFE_A_STAGE3_MUX3_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE3_MUX3_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX3_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_SET_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_SET_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX3_SET_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX3_SET_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_A_STAGE3_MUX3_SET_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_SET_MUX14_MASK)

#define PXP_WFE_A_STAGE3_MUX3_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX3_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX3_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_SET_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_SET_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX3_SET_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX3_SET_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_A_STAGE3_MUX3_SET_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_SET_MUX15_MASK)

#define PXP_WFE_A_STAGE3_MUX3_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX3_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX3_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_SET_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX3_CLR -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX3_CLR_MUX12_MASK     (0x3FU)
#define PXP_WFE_A_STAGE3_MUX3_CLR_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_A_STAGE3_MUX3_CLR_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_CLR_MUX12_MASK)

#define PXP_WFE_A_STAGE3_MUX3_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE3_MUX3_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX3_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_CLR_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_CLR_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX3_CLR_MUX13_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX3_CLR_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_A_STAGE3_MUX3_CLR_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_CLR_MUX13_MASK)

#define PXP_WFE_A_STAGE3_MUX3_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE3_MUX3_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX3_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_CLR_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_CLR_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX3_CLR_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX3_CLR_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_A_STAGE3_MUX3_CLR_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_CLR_MUX14_MASK)

#define PXP_WFE_A_STAGE3_MUX3_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX3_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX3_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_CLR_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_CLR_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX3_CLR_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX3_CLR_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_A_STAGE3_MUX3_CLR_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_CLR_MUX15_MASK)

#define PXP_WFE_A_STAGE3_MUX3_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX3_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX3_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_CLR_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE3_MUX3_TOG -  */
/*! @{ */

#define PXP_WFE_A_STAGE3_MUX3_TOG_MUX12_MASK     (0x3FU)
#define PXP_WFE_A_STAGE3_MUX3_TOG_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_A_STAGE3_MUX3_TOG_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_TOG_MUX12_MASK)

#define PXP_WFE_A_STAGE3_MUX3_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STAGE3_MUX3_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE3_MUX3_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_TOG_RSVD3_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_TOG_RSVD3_MASK)

#define PXP_WFE_A_STAGE3_MUX3_TOG_MUX13_MASK     (0x3F00U)
#define PXP_WFE_A_STAGE3_MUX3_TOG_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_A_STAGE3_MUX3_TOG_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_TOG_MUX13_MASK)

#define PXP_WFE_A_STAGE3_MUX3_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STAGE3_MUX3_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE3_MUX3_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_TOG_RSVD2_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_TOG_RSVD2_MASK)

#define PXP_WFE_A_STAGE3_MUX3_TOG_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_A_STAGE3_MUX3_TOG_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_A_STAGE3_MUX3_TOG_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_TOG_MUX14_MASK)

#define PXP_WFE_A_STAGE3_MUX3_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STAGE3_MUX3_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE3_MUX3_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_TOG_RSVD1_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_TOG_RSVD1_MASK)

#define PXP_WFE_A_STAGE3_MUX3_TOG_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_A_STAGE3_MUX3_TOG_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_A_STAGE3_MUX3_TOG_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_TOG_MUX15_MASK)

#define PXP_WFE_A_STAGE3_MUX3_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STAGE3_MUX3_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE3_MUX3_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE3_MUX3_TOG_RSVD0_SHIFT)) & PXP_WFE_A_STAGE3_MUX3_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT0_0 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0_MASK   (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1_MASK   (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1_SHIFT  (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2_MASK   (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2_SHIFT  (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3_MASK   (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3_SHIFT  (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4_MASK   (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4_SHIFT  (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5_MASK   (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5_SHIFT  (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6_MASK   (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6_SHIFT  (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7_MASK   (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7_SHIFT  (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8_MASK   (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8_SHIFT  (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9_MASK   (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9_SHIFT  (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10_MASK  (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10_SHIFT (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11_MASK  (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11_SHIFT (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12_MASK  (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12_SHIFT (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13_MASK  (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13_SHIFT (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14_MASK  (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14_SHIFT (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15_MASK  (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15_SHIFT (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16_MASK  (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16_SHIFT (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17_MASK  (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17_SHIFT (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18_MASK  (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18_SHIFT (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19_MASK  (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19_SHIFT (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20_MASK  (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20_SHIFT (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21_MASK  (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21_SHIFT (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22_MASK  (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22_SHIFT (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23_MASK  (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23_SHIFT (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24_MASK  (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24_SHIFT (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25_MASK  (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25_SHIFT (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26_MASK  (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26_SHIFT (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27_MASK  (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27_SHIFT (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28_MASK  (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28_SHIFT (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29_MASK  (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29_SHIFT (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30_MASK  (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30_SHIFT (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31_MASK  (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31_SHIFT (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT0_1 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32_MASK  (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32_SHIFT (0U)
/*! LUTOUT32 - LUTOUT32 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33_MASK  (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33_SHIFT (1U)
/*! LUTOUT33 - LUTOUT33 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34_MASK  (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34_SHIFT (2U)
/*! LUTOUT34 - LUTOUT34 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35_MASK  (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35_SHIFT (3U)
/*! LUTOUT35 - LUTOUT35 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36_MASK  (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36_SHIFT (4U)
/*! LUTOUT36 - LUTOUT36 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37_MASK  (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37_SHIFT (5U)
/*! LUTOUT37 - LUTOUT37 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38_MASK  (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38_SHIFT (6U)
/*! LUTOUT38 - LUTOUT38 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39_MASK  (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39_SHIFT (7U)
/*! LUTOUT39 - LUTOUT39 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40_MASK  (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40_SHIFT (8U)
/*! LUTOUT40 - LUTOUT40 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41_MASK  (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41_SHIFT (9U)
/*! LUTOUT41 - LUTOUT41 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42_MASK  (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42_SHIFT (10U)
/*! LUTOUT42 - LUTOUT42 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43_MASK  (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43_SHIFT (11U)
/*! LUTOUT43 - LUTOUT43 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44_MASK  (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44_SHIFT (12U)
/*! LUTOUT44 - LUTOUT44 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45_MASK  (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45_SHIFT (13U)
/*! LUTOUT45 - LUTOUT45 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46_MASK  (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46_SHIFT (14U)
/*! LUTOUT46 - LUTOUT46 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47_MASK  (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47_SHIFT (15U)
/*! LUTOUT47 - LUTOUT47 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48_MASK  (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48_SHIFT (16U)
/*! LUTOUT48 - LUTOUT48 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49_MASK  (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49_SHIFT (17U)
/*! LUTOUT49 - LUTOUT49 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50_MASK  (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50_SHIFT (18U)
/*! LUTOUT50 - LUTOUT50 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51_MASK  (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51_SHIFT (19U)
/*! LUTOUT51 - LUTOUT51 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52_MASK  (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52_SHIFT (20U)
/*! LUTOUT52 - LUTOUT52 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53_MASK  (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53_SHIFT (21U)
/*! LUTOUT53 - LUTOUT53 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54_MASK  (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54_SHIFT (22U)
/*! LUTOUT54 - LUTOUT54 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55_MASK  (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55_SHIFT (23U)
/*! LUTOUT55 - LUTOUT55 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56_MASK  (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56_SHIFT (24U)
/*! LUTOUT56 - LUTOUT56 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57_MASK  (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57_SHIFT (25U)
/*! LUTOUT57 - LUTOUT57 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58_MASK  (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58_SHIFT (26U)
/*! LUTOUT58 - LUTOUT58 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59_MASK  (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59_SHIFT (27U)
/*! LUTOUT59 - LUTOUT59 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60_MASK  (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60_SHIFT (28U)
/*! LUTOUT60 - LUTOUT60 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61_MASK  (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61_SHIFT (29U)
/*! LUTOUT61 - LUTOUT61 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62_MASK  (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62_SHIFT (30U)
/*! LUTOUT62 - LUTOUT62 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63_MASK  (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63_SHIFT (31U)
/*! LUTOUT63 - LUTOUT63 */
#define PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT0_2 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64_MASK  (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64_SHIFT (0U)
/*! LUTOUT64 - LUTOUT64 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65_MASK  (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65_SHIFT (1U)
/*! LUTOUT65 - LUTOUT65 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66_MASK  (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66_SHIFT (2U)
/*! LUTOUT66 - LUTOUT66 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67_MASK  (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67_SHIFT (3U)
/*! LUTOUT67 - LUTOUT67 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68_MASK  (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68_SHIFT (4U)
/*! LUTOUT68 - LUTOUT68 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69_MASK  (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69_SHIFT (5U)
/*! LUTOUT69 - LUTOUT69 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70_MASK  (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70_SHIFT (6U)
/*! LUTOUT70 - LUTOUT70 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71_MASK  (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71_SHIFT (7U)
/*! LUTOUT71 - LUTOUT71 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72_MASK  (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72_SHIFT (8U)
/*! LUTOUT72 - LUTOUT72 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73_MASK  (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73_SHIFT (9U)
/*! LUTOUT73 - LUTOUT73 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74_MASK  (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74_SHIFT (10U)
/*! LUTOUT74 - LUTOUT74 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75_MASK  (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75_SHIFT (11U)
/*! LUTOUT75 - LUTOUT75 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76_MASK  (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76_SHIFT (12U)
/*! LUTOUT76 - LUTOUT76 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77_MASK  (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77_SHIFT (13U)
/*! LUTOUT77 - LUTOUT77 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78_MASK  (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78_SHIFT (14U)
/*! LUTOUT78 - LUTOUT78 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79_MASK  (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79_SHIFT (15U)
/*! LUTOUT79 - LUTOUT79 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80_MASK  (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80_SHIFT (16U)
/*! LUTOUT80 - LUTOUT80 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81_MASK  (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81_SHIFT (17U)
/*! LUTOUT81 - LUTOUT81 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82_MASK  (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82_SHIFT (18U)
/*! LUTOUT82 - LUTOUT82 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83_MASK  (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83_SHIFT (19U)
/*! LUTOUT83 - LUTOUT83 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84_MASK  (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84_SHIFT (20U)
/*! LUTOUT84 - LUTOUT84 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85_MASK  (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85_SHIFT (21U)
/*! LUTOUT85 - LUTOUT85 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86_MASK  (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86_SHIFT (22U)
/*! LUTOUT86 - LUTOUT86 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87_MASK  (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87_SHIFT (23U)
/*! LUTOUT87 - LUTOUT87 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88_MASK  (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88_SHIFT (24U)
/*! LUTOUT88 - LUTOUT88 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89_MASK  (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89_SHIFT (25U)
/*! LUTOUT89 - LUTOUT89 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90_MASK  (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90_SHIFT (26U)
/*! LUTOUT90 - LUTOUT90 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91_MASK  (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91_SHIFT (27U)
/*! LUTOUT91 - LUTOUT91 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92_MASK  (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92_SHIFT (28U)
/*! LUTOUT92 - LUTOUT92 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93_MASK  (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93_SHIFT (29U)
/*! LUTOUT93 - LUTOUT93 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94_MASK  (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94_SHIFT (30U)
/*! LUTOUT94 - LUTOUT94 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95_MASK  (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95_SHIFT (31U)
/*! LUTOUT95 - LUTOUT95 */
#define PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT0_3 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96_MASK  (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96_SHIFT (0U)
/*! LUTOUT96 - LUTOUT96 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97_MASK  (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97_SHIFT (1U)
/*! LUTOUT97 - LUTOUT97 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98_MASK  (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98_SHIFT (2U)
/*! LUTOUT98 - LUTOUT98 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99_MASK  (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99_SHIFT (3U)
/*! LUTOUT99 - LUTOUT99 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100_SHIFT (4U)
/*! LUTOUT100 - LUTOUT100 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101_SHIFT (5U)
/*! LUTOUT101 - LUTOUT101 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102_SHIFT (6U)
/*! LUTOUT102 - LUTOUT102 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103_SHIFT (7U)
/*! LUTOUT103 - LUTOUT103 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104_SHIFT (8U)
/*! LUTOUT104 - LUTOUT104 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105_SHIFT (9U)
/*! LUTOUT105 - LUTOUT105 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106_SHIFT (10U)
/*! LUTOUT106 - LUTOUT106 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107_SHIFT (11U)
/*! LUTOUT107 - LUTOUT107 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108_SHIFT (12U)
/*! LUTOUT108 - LUTOUT108 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109_SHIFT (13U)
/*! LUTOUT109 - LUTOUT109 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110_SHIFT (14U)
/*! LUTOUT110 - LUTOUT110 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111_SHIFT (15U)
/*! LUTOUT111 - LUTOUT111 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112_SHIFT (16U)
/*! LUTOUT112 - LUTOUT112 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113_SHIFT (17U)
/*! LUTOUT113 - LUTOUT113 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114_SHIFT (18U)
/*! LUTOUT114 - LUTOUT114 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115_SHIFT (19U)
/*! LUTOUT115 - LUTOUT115 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116_SHIFT (20U)
/*! LUTOUT116 - LUTOUT116 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117_SHIFT (21U)
/*! LUTOUT117 - LUTOUT117 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118_SHIFT (22U)
/*! LUTOUT118 - LUTOUT118 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119_SHIFT (23U)
/*! LUTOUT119 - LUTOUT119 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120_SHIFT (24U)
/*! LUTOUT120 - LUTOUT120 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121_SHIFT (25U)
/*! LUTOUT121 - LUTOUT121 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122_SHIFT (26U)
/*! LUTOUT122 - LUTOUT122 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123_SHIFT (27U)
/*! LUTOUT123 - LUTOUT123 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124_SHIFT (28U)
/*! LUTOUT124 - LUTOUT124 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125_SHIFT (29U)
/*! LUTOUT125 - LUTOUT125 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126_SHIFT (30U)
/*! LUTOUT126 - LUTOUT126 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127_SHIFT (31U)
/*! LUTOUT127 - LUTOUT127 */
#define PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT0_4 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128_SHIFT (0U)
/*! LUTOUT128 - LUTOUT128 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129_SHIFT (1U)
/*! LUTOUT129 - LUTOUT129 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130_SHIFT (2U)
/*! LUTOUT130 - LUTOUT130 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131_SHIFT (3U)
/*! LUTOUT131 - LUTOUT131 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132_SHIFT (4U)
/*! LUTOUT132 - LUTOUT132 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133_SHIFT (5U)
/*! LUTOUT133 - LUTOUT133 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134_SHIFT (6U)
/*! LUTOUT134 - LUTOUT134 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135_SHIFT (7U)
/*! LUTOUT135 - LUTOUT135 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136_SHIFT (8U)
/*! LUTOUT136 - LUTOUT136 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137_SHIFT (9U)
/*! LUTOUT137 - LUTOUT137 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138_SHIFT (10U)
/*! LUTOUT138 - LUTOUT138 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139_SHIFT (11U)
/*! LUTOUT139 - LUTOUT139 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140_SHIFT (12U)
/*! LUTOUT140 - LUTOUT140 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141_SHIFT (13U)
/*! LUTOUT141 - LUTOUT141 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142_SHIFT (14U)
/*! LUTOUT142 - LUTOUT142 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143_SHIFT (15U)
/*! LUTOUT143 - LUTOUT143 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144_SHIFT (16U)
/*! LUTOUT144 - LUTOUT144 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145_SHIFT (17U)
/*! LUTOUT145 - LUTOUT145 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146_SHIFT (18U)
/*! LUTOUT146 - LUTOUT146 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147_SHIFT (19U)
/*! LUTOUT147 - LUTOUT147 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148_SHIFT (20U)
/*! LUTOUT148 - LUTOUT148 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149_SHIFT (21U)
/*! LUTOUT149 - LUTOUT149 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150_SHIFT (22U)
/*! LUTOUT150 - LUTOUT150 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151_SHIFT (23U)
/*! LUTOUT151 - LUTOUT151 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152_SHIFT (24U)
/*! LUTOUT152 - LUTOUT152 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153_SHIFT (25U)
/*! LUTOUT153 - LUTOUT153 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154_SHIFT (26U)
/*! LUTOUT154 - LUTOUT154 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155_SHIFT (27U)
/*! LUTOUT155 - LUTOUT155 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156_SHIFT (28U)
/*! LUTOUT156 - LUTOUT156 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157_SHIFT (29U)
/*! LUTOUT157 - LUTOUT157 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158_SHIFT (30U)
/*! LUTOUT158 - LUTOUT158 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159_SHIFT (31U)
/*! LUTOUT159 - LUTOUT159 */
#define PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT0_5 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160_SHIFT (0U)
/*! LUTOUT160 - LUTOUT160 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161_SHIFT (1U)
/*! LUTOUT161 - LUTOUT161 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162_SHIFT (2U)
/*! LUTOUT162 - LUTOUT162 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163_SHIFT (3U)
/*! LUTOUT163 - LUTOUT163 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164_SHIFT (4U)
/*! LUTOUT164 - LUTOUT164 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165_SHIFT (5U)
/*! LUTOUT165 - LUTOUT165 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166_SHIFT (6U)
/*! LUTOUT166 - LUTOUT166 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167_SHIFT (7U)
/*! LUTOUT167 - LUTOUT167 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168_SHIFT (8U)
/*! LUTOUT168 - LUTOUT168 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169_SHIFT (9U)
/*! LUTOUT169 - LUTOUT169 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170_SHIFT (10U)
/*! LUTOUT170 - LUTOUT170 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171_SHIFT (11U)
/*! LUTOUT171 - LUTOUT171 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172_SHIFT (12U)
/*! LUTOUT172 - LUTOUT172 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173_SHIFT (13U)
/*! LUTOUT173 - LUTOUT173 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174_SHIFT (14U)
/*! LUTOUT174 - LUTOUT174 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175_SHIFT (15U)
/*! LUTOUT175 - LUTOUT175 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176_SHIFT (16U)
/*! LUTOUT176 - LUTOUT176 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177_SHIFT (17U)
/*! LUTOUT177 - LUTOUT177 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178_SHIFT (18U)
/*! LUTOUT178 - LUTOUT178 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179_SHIFT (19U)
/*! LUTOUT179 - LUTOUT179 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180_SHIFT (20U)
/*! LUTOUT180 - LUTOUT180 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181_SHIFT (21U)
/*! LUTOUT181 - LUTOUT181 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182_SHIFT (22U)
/*! LUTOUT182 - LUTOUT182 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183_SHIFT (23U)
/*! LUTOUT183 - LUTOUT183 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184_SHIFT (24U)
/*! LUTOUT184 - LUTOUT184 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185_SHIFT (25U)
/*! LUTOUT185 - LUTOUT185 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186_SHIFT (26U)
/*! LUTOUT186 - LUTOUT186 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187_SHIFT (27U)
/*! LUTOUT187 - LUTOUT187 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188_SHIFT (28U)
/*! LUTOUT188 - LUTOUT188 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189_SHIFT (29U)
/*! LUTOUT189 - LUTOUT189 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190_SHIFT (30U)
/*! LUTOUT190 - LUTOUT190 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191_SHIFT (31U)
/*! LUTOUT191 - LUTOUT191 */
#define PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT0_6 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192_SHIFT (0U)
/*! LUTOUT192 - LUTOUT192 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193_SHIFT (1U)
/*! LUTOUT193 - LUTOUT193 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194_SHIFT (2U)
/*! LUTOUT194 - LUTOUT194 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195_SHIFT (3U)
/*! LUTOUT195 - LUTOUT195 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196_SHIFT (4U)
/*! LUTOUT196 - LUTOUT196 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197_SHIFT (5U)
/*! LUTOUT197 - LUTOUT197 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198_SHIFT (6U)
/*! LUTOUT198 - LUTOUT198 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199_SHIFT (7U)
/*! LUTOUT199 - LUTOUT199 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200_SHIFT (8U)
/*! LUTOUT200 - LUTOUT200 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201_SHIFT (9U)
/*! LUTOUT201 - LUTOUT201 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202_SHIFT (10U)
/*! LUTOUT202 - LUTOUT202 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203_SHIFT (11U)
/*! LUTOUT203 - LUTOUT203 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204_SHIFT (12U)
/*! LUTOUT204 - LUTOUT204 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205_SHIFT (13U)
/*! LUTOUT205 - LUTOUT205 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206_SHIFT (14U)
/*! LUTOUT206 - LUTOUT206 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207_SHIFT (15U)
/*! LUTOUT207 - LUTOUT207 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208_SHIFT (16U)
/*! LUTOUT208 - LUTOUT208 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209_SHIFT (17U)
/*! LUTOUT209 - LUTOUT209 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210_SHIFT (18U)
/*! LUTOUT210 - LUTOUT210 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211_SHIFT (19U)
/*! LUTOUT211 - LUTOUT211 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212_SHIFT (20U)
/*! LUTOUT212 - LUTOUT212 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213_SHIFT (21U)
/*! LUTOUT213 - LUTOUT213 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214_SHIFT (22U)
/*! LUTOUT214 - LUTOUT214 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215_SHIFT (23U)
/*! LUTOUT215 - LUTOUT215 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216_SHIFT (24U)
/*! LUTOUT216 - LUTOUT216 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217_SHIFT (25U)
/*! LUTOUT217 - LUTOUT217 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218_SHIFT (26U)
/*! LUTOUT218 - LUTOUT218 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219_SHIFT (27U)
/*! LUTOUT219 - LUTOUT219 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220_SHIFT (28U)
/*! LUTOUT220 - LUTOUT220 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221_SHIFT (29U)
/*! LUTOUT221 - LUTOUT221 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222_SHIFT (30U)
/*! LUTOUT222 - LUTOUT222 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223_SHIFT (31U)
/*! LUTOUT223 - LUTOUT223 */
#define PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT0_7 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224_SHIFT (0U)
/*! LUTOUT224 - LUTOUT224 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225_SHIFT (1U)
/*! LUTOUT225 - LUTOUT225 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226_SHIFT (2U)
/*! LUTOUT226 - LUTOUT226 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227_SHIFT (3U)
/*! LUTOUT227 - LUTOUT227 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228_SHIFT (4U)
/*! LUTOUT228 - LUTOUT228 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229_SHIFT (5U)
/*! LUTOUT229 - LUTOUT229 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230_SHIFT (6U)
/*! LUTOUT230 - LUTOUT230 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231_SHIFT (7U)
/*! LUTOUT231 - LUTOUT231 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232_SHIFT (8U)
/*! LUTOUT232 - LUTOUT232 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233_SHIFT (9U)
/*! LUTOUT233 - LUTOUT233 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234_SHIFT (10U)
/*! LUTOUT234 - LUTOUT234 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235_SHIFT (11U)
/*! LUTOUT235 - LUTOUT235 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236_SHIFT (12U)
/*! LUTOUT236 - LUTOUT236 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237_SHIFT (13U)
/*! LUTOUT237 - LUTOUT237 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238_SHIFT (14U)
/*! LUTOUT238 - LUTOUT238 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239_SHIFT (15U)
/*! LUTOUT239 - LUTOUT239 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240_SHIFT (16U)
/*! LUTOUT240 - LUTOUT240 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241_SHIFT (17U)
/*! LUTOUT241 - LUTOUT241 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242_SHIFT (18U)
/*! LUTOUT242 - LUTOUT242 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243_SHIFT (19U)
/*! LUTOUT243 - LUTOUT243 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244_SHIFT (20U)
/*! LUTOUT244 - LUTOUT244 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245_SHIFT (21U)
/*! LUTOUT245 - LUTOUT245 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246_SHIFT (22U)
/*! LUTOUT246 - LUTOUT246 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247_SHIFT (23U)
/*! LUTOUT247 - LUTOUT247 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248_SHIFT (24U)
/*! LUTOUT248 - LUTOUT248 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249_SHIFT (25U)
/*! LUTOUT249 - LUTOUT249 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250_SHIFT (26U)
/*! LUTOUT250 - LUTOUT250 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251_SHIFT (27U)
/*! LUTOUT251 - LUTOUT251 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252_SHIFT (28U)
/*! LUTOUT252 - LUTOUT252 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253_SHIFT (29U)
/*! LUTOUT253 - LUTOUT253 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254_SHIFT (30U)
/*! LUTOUT254 - LUTOUT254 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254_MASK)

#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255_SHIFT (31U)
/*! LUTOUT255 - LUTOUT255 */
#define PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT1_0 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0_MASK   (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1_MASK   (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1_SHIFT  (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2_MASK   (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2_SHIFT  (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3_MASK   (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3_SHIFT  (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4_MASK   (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4_SHIFT  (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5_MASK   (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5_SHIFT  (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6_MASK   (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6_SHIFT  (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7_MASK   (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7_SHIFT  (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8_MASK   (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8_SHIFT  (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9_MASK   (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9_SHIFT  (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10_MASK  (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10_SHIFT (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11_MASK  (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11_SHIFT (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12_MASK  (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12_SHIFT (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13_MASK  (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13_SHIFT (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14_MASK  (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14_SHIFT (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15_MASK  (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15_SHIFT (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16_MASK  (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16_SHIFT (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17_MASK  (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17_SHIFT (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18_MASK  (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18_SHIFT (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19_MASK  (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19_SHIFT (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20_MASK  (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20_SHIFT (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21_MASK  (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21_SHIFT (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22_MASK  (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22_SHIFT (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23_MASK  (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23_SHIFT (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24_MASK  (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24_SHIFT (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25_MASK  (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25_SHIFT (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26_MASK  (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26_SHIFT (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27_MASK  (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27_SHIFT (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28_MASK  (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28_SHIFT (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29_MASK  (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29_SHIFT (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30_MASK  (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30_SHIFT (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31_MASK  (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31_SHIFT (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT1_1 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32_MASK  (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32_SHIFT (0U)
/*! LUTOUT32 - LUTOUT32 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33_MASK  (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33_SHIFT (1U)
/*! LUTOUT33 - LUTOUT33 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34_MASK  (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34_SHIFT (2U)
/*! LUTOUT34 - LUTOUT34 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35_MASK  (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35_SHIFT (3U)
/*! LUTOUT35 - LUTOUT35 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36_MASK  (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36_SHIFT (4U)
/*! LUTOUT36 - LUTOUT36 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37_MASK  (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37_SHIFT (5U)
/*! LUTOUT37 - LUTOUT37 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38_MASK  (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38_SHIFT (6U)
/*! LUTOUT38 - LUTOUT38 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39_MASK  (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39_SHIFT (7U)
/*! LUTOUT39 - LUTOUT39 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40_MASK  (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40_SHIFT (8U)
/*! LUTOUT40 - LUTOUT40 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41_MASK  (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41_SHIFT (9U)
/*! LUTOUT41 - LUTOUT41 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42_MASK  (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42_SHIFT (10U)
/*! LUTOUT42 - LUTOUT42 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43_MASK  (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43_SHIFT (11U)
/*! LUTOUT43 - LUTOUT43 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44_MASK  (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44_SHIFT (12U)
/*! LUTOUT44 - LUTOUT44 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45_MASK  (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45_SHIFT (13U)
/*! LUTOUT45 - LUTOUT45 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46_MASK  (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46_SHIFT (14U)
/*! LUTOUT46 - LUTOUT46 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47_MASK  (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47_SHIFT (15U)
/*! LUTOUT47 - LUTOUT47 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48_MASK  (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48_SHIFT (16U)
/*! LUTOUT48 - LUTOUT48 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49_MASK  (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49_SHIFT (17U)
/*! LUTOUT49 - LUTOUT49 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50_MASK  (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50_SHIFT (18U)
/*! LUTOUT50 - LUTOUT50 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51_MASK  (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51_SHIFT (19U)
/*! LUTOUT51 - LUTOUT51 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52_MASK  (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52_SHIFT (20U)
/*! LUTOUT52 - LUTOUT52 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53_MASK  (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53_SHIFT (21U)
/*! LUTOUT53 - LUTOUT53 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54_MASK  (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54_SHIFT (22U)
/*! LUTOUT54 - LUTOUT54 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55_MASK  (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55_SHIFT (23U)
/*! LUTOUT55 - LUTOUT55 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56_MASK  (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56_SHIFT (24U)
/*! LUTOUT56 - LUTOUT56 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57_MASK  (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57_SHIFT (25U)
/*! LUTOUT57 - LUTOUT57 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58_MASK  (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58_SHIFT (26U)
/*! LUTOUT58 - LUTOUT58 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59_MASK  (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59_SHIFT (27U)
/*! LUTOUT59 - LUTOUT59 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60_MASK  (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60_SHIFT (28U)
/*! LUTOUT60 - LUTOUT60 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61_MASK  (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61_SHIFT (29U)
/*! LUTOUT61 - LUTOUT61 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62_MASK  (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62_SHIFT (30U)
/*! LUTOUT62 - LUTOUT62 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63_MASK  (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63_SHIFT (31U)
/*! LUTOUT63 - LUTOUT63 */
#define PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT1_2 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64_MASK  (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64_SHIFT (0U)
/*! LUTOUT64 - LUTOUT64 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65_MASK  (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65_SHIFT (1U)
/*! LUTOUT65 - LUTOUT65 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66_MASK  (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66_SHIFT (2U)
/*! LUTOUT66 - LUTOUT66 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67_MASK  (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67_SHIFT (3U)
/*! LUTOUT67 - LUTOUT67 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68_MASK  (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68_SHIFT (4U)
/*! LUTOUT68 - LUTOUT68 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69_MASK  (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69_SHIFT (5U)
/*! LUTOUT69 - LUTOUT69 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70_MASK  (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70_SHIFT (6U)
/*! LUTOUT70 - LUTOUT70 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71_MASK  (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71_SHIFT (7U)
/*! LUTOUT71 - LUTOUT71 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72_MASK  (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72_SHIFT (8U)
/*! LUTOUT72 - LUTOUT72 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73_MASK  (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73_SHIFT (9U)
/*! LUTOUT73 - LUTOUT73 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74_MASK  (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74_SHIFT (10U)
/*! LUTOUT74 - LUTOUT74 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75_MASK  (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75_SHIFT (11U)
/*! LUTOUT75 - LUTOUT75 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76_MASK  (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76_SHIFT (12U)
/*! LUTOUT76 - LUTOUT76 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77_MASK  (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77_SHIFT (13U)
/*! LUTOUT77 - LUTOUT77 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78_MASK  (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78_SHIFT (14U)
/*! LUTOUT78 - LUTOUT78 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79_MASK  (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79_SHIFT (15U)
/*! LUTOUT79 - LUTOUT79 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80_MASK  (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80_SHIFT (16U)
/*! LUTOUT80 - LUTOUT80 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81_MASK  (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81_SHIFT (17U)
/*! LUTOUT81 - LUTOUT81 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82_MASK  (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82_SHIFT (18U)
/*! LUTOUT82 - LUTOUT82 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83_MASK  (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83_SHIFT (19U)
/*! LUTOUT83 - LUTOUT83 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84_MASK  (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84_SHIFT (20U)
/*! LUTOUT84 - LUTOUT84 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85_MASK  (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85_SHIFT (21U)
/*! LUTOUT85 - LUTOUT85 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86_MASK  (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86_SHIFT (22U)
/*! LUTOUT86 - LUTOUT86 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87_MASK  (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87_SHIFT (23U)
/*! LUTOUT87 - LUTOUT87 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88_MASK  (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88_SHIFT (24U)
/*! LUTOUT88 - LUTOUT88 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89_MASK  (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89_SHIFT (25U)
/*! LUTOUT89 - LUTOUT89 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90_MASK  (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90_SHIFT (26U)
/*! LUTOUT90 - LUTOUT90 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91_MASK  (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91_SHIFT (27U)
/*! LUTOUT91 - LUTOUT91 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92_MASK  (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92_SHIFT (28U)
/*! LUTOUT92 - LUTOUT92 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93_MASK  (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93_SHIFT (29U)
/*! LUTOUT93 - LUTOUT93 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94_MASK  (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94_SHIFT (30U)
/*! LUTOUT94 - LUTOUT94 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95_MASK  (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95_SHIFT (31U)
/*! LUTOUT95 - LUTOUT95 */
#define PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT1_3 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96_MASK  (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96_SHIFT (0U)
/*! LUTOUT96 - LUTOUT96 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97_MASK  (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97_SHIFT (1U)
/*! LUTOUT97 - LUTOUT97 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98_MASK  (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98_SHIFT (2U)
/*! LUTOUT98 - LUTOUT98 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99_MASK  (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99_SHIFT (3U)
/*! LUTOUT99 - LUTOUT99 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100_SHIFT (4U)
/*! LUTOUT100 - LUTOUT100 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101_SHIFT (5U)
/*! LUTOUT101 - LUTOUT101 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102_SHIFT (6U)
/*! LUTOUT102 - LUTOUT102 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103_SHIFT (7U)
/*! LUTOUT103 - LUTOUT103 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104_SHIFT (8U)
/*! LUTOUT104 - LUTOUT104 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105_SHIFT (9U)
/*! LUTOUT105 - LUTOUT105 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106_SHIFT (10U)
/*! LUTOUT106 - LUTOUT106 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107_SHIFT (11U)
/*! LUTOUT107 - LUTOUT107 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108_SHIFT (12U)
/*! LUTOUT108 - LUTOUT108 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109_SHIFT (13U)
/*! LUTOUT109 - LUTOUT109 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110_SHIFT (14U)
/*! LUTOUT110 - LUTOUT110 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111_SHIFT (15U)
/*! LUTOUT111 - LUTOUT111 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112_SHIFT (16U)
/*! LUTOUT112 - LUTOUT112 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113_SHIFT (17U)
/*! LUTOUT113 - LUTOUT113 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114_SHIFT (18U)
/*! LUTOUT114 - LUTOUT114 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115_SHIFT (19U)
/*! LUTOUT115 - LUTOUT115 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116_SHIFT (20U)
/*! LUTOUT116 - LUTOUT116 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117_SHIFT (21U)
/*! LUTOUT117 - LUTOUT117 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118_SHIFT (22U)
/*! LUTOUT118 - LUTOUT118 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119_SHIFT (23U)
/*! LUTOUT119 - LUTOUT119 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120_SHIFT (24U)
/*! LUTOUT120 - LUTOUT120 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121_SHIFT (25U)
/*! LUTOUT121 - LUTOUT121 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122_SHIFT (26U)
/*! LUTOUT122 - LUTOUT122 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123_SHIFT (27U)
/*! LUTOUT123 - LUTOUT123 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124_SHIFT (28U)
/*! LUTOUT124 - LUTOUT124 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125_SHIFT (29U)
/*! LUTOUT125 - LUTOUT125 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126_SHIFT (30U)
/*! LUTOUT126 - LUTOUT126 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127_SHIFT (31U)
/*! LUTOUT127 - LUTOUT127 */
#define PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT1_4 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128_SHIFT (0U)
/*! LUTOUT128 - LUTOUT128 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129_SHIFT (1U)
/*! LUTOUT129 - LUTOUT129 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130_SHIFT (2U)
/*! LUTOUT130 - LUTOUT130 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131_SHIFT (3U)
/*! LUTOUT131 - LUTOUT131 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132_SHIFT (4U)
/*! LUTOUT132 - LUTOUT132 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133_SHIFT (5U)
/*! LUTOUT133 - LUTOUT133 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134_SHIFT (6U)
/*! LUTOUT134 - LUTOUT134 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135_SHIFT (7U)
/*! LUTOUT135 - LUTOUT135 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136_SHIFT (8U)
/*! LUTOUT136 - LUTOUT136 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137_SHIFT (9U)
/*! LUTOUT137 - LUTOUT137 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138_SHIFT (10U)
/*! LUTOUT138 - LUTOUT138 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139_SHIFT (11U)
/*! LUTOUT139 - LUTOUT139 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140_SHIFT (12U)
/*! LUTOUT140 - LUTOUT140 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141_SHIFT (13U)
/*! LUTOUT141 - LUTOUT141 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142_SHIFT (14U)
/*! LUTOUT142 - LUTOUT142 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143_SHIFT (15U)
/*! LUTOUT143 - LUTOUT143 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144_SHIFT (16U)
/*! LUTOUT144 - LUTOUT144 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145_SHIFT (17U)
/*! LUTOUT145 - LUTOUT145 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146_SHIFT (18U)
/*! LUTOUT146 - LUTOUT146 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147_SHIFT (19U)
/*! LUTOUT147 - LUTOUT147 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148_SHIFT (20U)
/*! LUTOUT148 - LUTOUT148 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149_SHIFT (21U)
/*! LUTOUT149 - LUTOUT149 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150_SHIFT (22U)
/*! LUTOUT150 - LUTOUT150 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151_SHIFT (23U)
/*! LUTOUT151 - LUTOUT151 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152_SHIFT (24U)
/*! LUTOUT152 - LUTOUT152 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153_SHIFT (25U)
/*! LUTOUT153 - LUTOUT153 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154_SHIFT (26U)
/*! LUTOUT154 - LUTOUT154 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155_SHIFT (27U)
/*! LUTOUT155 - LUTOUT155 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156_SHIFT (28U)
/*! LUTOUT156 - LUTOUT156 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157_SHIFT (29U)
/*! LUTOUT157 - LUTOUT157 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158_SHIFT (30U)
/*! LUTOUT158 - LUTOUT158 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159_SHIFT (31U)
/*! LUTOUT159 - LUTOUT159 */
#define PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT1_5 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160_SHIFT (0U)
/*! LUTOUT160 - LUTOUT160 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161_SHIFT (1U)
/*! LUTOUT161 - LUTOUT161 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162_SHIFT (2U)
/*! LUTOUT162 - LUTOUT162 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163_SHIFT (3U)
/*! LUTOUT163 - LUTOUT163 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164_SHIFT (4U)
/*! LUTOUT164 - LUTOUT164 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165_SHIFT (5U)
/*! LUTOUT165 - LUTOUT165 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166_SHIFT (6U)
/*! LUTOUT166 - LUTOUT166 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167_SHIFT (7U)
/*! LUTOUT167 - LUTOUT167 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168_SHIFT (8U)
/*! LUTOUT168 - LUTOUT168 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169_SHIFT (9U)
/*! LUTOUT169 - LUTOUT169 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170_SHIFT (10U)
/*! LUTOUT170 - LUTOUT170 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171_SHIFT (11U)
/*! LUTOUT171 - LUTOUT171 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172_SHIFT (12U)
/*! LUTOUT172 - LUTOUT172 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173_SHIFT (13U)
/*! LUTOUT173 - LUTOUT173 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174_SHIFT (14U)
/*! LUTOUT174 - LUTOUT174 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175_SHIFT (15U)
/*! LUTOUT175 - LUTOUT175 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176_SHIFT (16U)
/*! LUTOUT176 - LUTOUT176 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177_SHIFT (17U)
/*! LUTOUT177 - LUTOUT177 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178_SHIFT (18U)
/*! LUTOUT178 - LUTOUT178 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179_SHIFT (19U)
/*! LUTOUT179 - LUTOUT179 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180_SHIFT (20U)
/*! LUTOUT180 - LUTOUT180 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181_SHIFT (21U)
/*! LUTOUT181 - LUTOUT181 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182_SHIFT (22U)
/*! LUTOUT182 - LUTOUT182 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183_SHIFT (23U)
/*! LUTOUT183 - LUTOUT183 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184_SHIFT (24U)
/*! LUTOUT184 - LUTOUT184 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185_SHIFT (25U)
/*! LUTOUT185 - LUTOUT185 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186_SHIFT (26U)
/*! LUTOUT186 - LUTOUT186 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187_SHIFT (27U)
/*! LUTOUT187 - LUTOUT187 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188_SHIFT (28U)
/*! LUTOUT188 - LUTOUT188 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189_SHIFT (29U)
/*! LUTOUT189 - LUTOUT189 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190_SHIFT (30U)
/*! LUTOUT190 - LUTOUT190 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191_SHIFT (31U)
/*! LUTOUT191 - LUTOUT191 */
#define PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT1_6 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192_SHIFT (0U)
/*! LUTOUT192 - LUTOUT192 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193_SHIFT (1U)
/*! LUTOUT193 - LUTOUT193 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194_SHIFT (2U)
/*! LUTOUT194 - LUTOUT194 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195_SHIFT (3U)
/*! LUTOUT195 - LUTOUT195 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196_SHIFT (4U)
/*! LUTOUT196 - LUTOUT196 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197_SHIFT (5U)
/*! LUTOUT197 - LUTOUT197 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198_SHIFT (6U)
/*! LUTOUT198 - LUTOUT198 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199_SHIFT (7U)
/*! LUTOUT199 - LUTOUT199 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200_SHIFT (8U)
/*! LUTOUT200 - LUTOUT200 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201_SHIFT (9U)
/*! LUTOUT201 - LUTOUT201 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202_SHIFT (10U)
/*! LUTOUT202 - LUTOUT202 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203_SHIFT (11U)
/*! LUTOUT203 - LUTOUT203 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204_SHIFT (12U)
/*! LUTOUT204 - LUTOUT204 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205_SHIFT (13U)
/*! LUTOUT205 - LUTOUT205 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206_SHIFT (14U)
/*! LUTOUT206 - LUTOUT206 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207_SHIFT (15U)
/*! LUTOUT207 - LUTOUT207 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208_SHIFT (16U)
/*! LUTOUT208 - LUTOUT208 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209_SHIFT (17U)
/*! LUTOUT209 - LUTOUT209 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210_SHIFT (18U)
/*! LUTOUT210 - LUTOUT210 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211_SHIFT (19U)
/*! LUTOUT211 - LUTOUT211 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212_SHIFT (20U)
/*! LUTOUT212 - LUTOUT212 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213_SHIFT (21U)
/*! LUTOUT213 - LUTOUT213 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214_SHIFT (22U)
/*! LUTOUT214 - LUTOUT214 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215_SHIFT (23U)
/*! LUTOUT215 - LUTOUT215 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216_SHIFT (24U)
/*! LUTOUT216 - LUTOUT216 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217_SHIFT (25U)
/*! LUTOUT217 - LUTOUT217 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218_SHIFT (26U)
/*! LUTOUT218 - LUTOUT218 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219_SHIFT (27U)
/*! LUTOUT219 - LUTOUT219 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220_SHIFT (28U)
/*! LUTOUT220 - LUTOUT220 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221_SHIFT (29U)
/*! LUTOUT221 - LUTOUT221 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222_SHIFT (30U)
/*! LUTOUT222 - LUTOUT222 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223_SHIFT (31U)
/*! LUTOUT223 - LUTOUT223 */
#define PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT1_7 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224_SHIFT (0U)
/*! LUTOUT224 - LUTOUT224 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225_SHIFT (1U)
/*! LUTOUT225 - LUTOUT225 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226_SHIFT (2U)
/*! LUTOUT226 - LUTOUT226 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227_SHIFT (3U)
/*! LUTOUT227 - LUTOUT227 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228_SHIFT (4U)
/*! LUTOUT228 - LUTOUT228 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229_SHIFT (5U)
/*! LUTOUT229 - LUTOUT229 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230_SHIFT (6U)
/*! LUTOUT230 - LUTOUT230 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231_SHIFT (7U)
/*! LUTOUT231 - LUTOUT231 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232_SHIFT (8U)
/*! LUTOUT232 - LUTOUT232 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233_SHIFT (9U)
/*! LUTOUT233 - LUTOUT233 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234_SHIFT (10U)
/*! LUTOUT234 - LUTOUT234 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235_SHIFT (11U)
/*! LUTOUT235 - LUTOUT235 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236_SHIFT (12U)
/*! LUTOUT236 - LUTOUT236 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237_SHIFT (13U)
/*! LUTOUT237 - LUTOUT237 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238_SHIFT (14U)
/*! LUTOUT238 - LUTOUT238 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239_SHIFT (15U)
/*! LUTOUT239 - LUTOUT239 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240_SHIFT (16U)
/*! LUTOUT240 - LUTOUT240 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241_SHIFT (17U)
/*! LUTOUT241 - LUTOUT241 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242_SHIFT (18U)
/*! LUTOUT242 - LUTOUT242 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243_SHIFT (19U)
/*! LUTOUT243 - LUTOUT243 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244_SHIFT (20U)
/*! LUTOUT244 - LUTOUT244 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245_SHIFT (21U)
/*! LUTOUT245 - LUTOUT245 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246_SHIFT (22U)
/*! LUTOUT246 - LUTOUT246 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247_SHIFT (23U)
/*! LUTOUT247 - LUTOUT247 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248_SHIFT (24U)
/*! LUTOUT248 - LUTOUT248 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249_SHIFT (25U)
/*! LUTOUT249 - LUTOUT249 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250_SHIFT (26U)
/*! LUTOUT250 - LUTOUT250 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251_SHIFT (27U)
/*! LUTOUT251 - LUTOUT251 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252_SHIFT (28U)
/*! LUTOUT252 - LUTOUT252 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253_SHIFT (29U)
/*! LUTOUT253 - LUTOUT253 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254_SHIFT (30U)
/*! LUTOUT254 - LUTOUT254 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254_MASK)

#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255_SHIFT (31U)
/*! LUTOUT255 - LUTOUT255 */
#define PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT2_0 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0_MASK   (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1_MASK   (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1_SHIFT  (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2_MASK   (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2_SHIFT  (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3_MASK   (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3_SHIFT  (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4_MASK   (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4_SHIFT  (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5_MASK   (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5_SHIFT  (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6_MASK   (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6_SHIFT  (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7_MASK   (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7_SHIFT  (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8_MASK   (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8_SHIFT  (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9_MASK   (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9_SHIFT  (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10_MASK  (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10_SHIFT (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11_MASK  (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11_SHIFT (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12_MASK  (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12_SHIFT (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13_MASK  (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13_SHIFT (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14_MASK  (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14_SHIFT (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15_MASK  (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15_SHIFT (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16_MASK  (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16_SHIFT (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17_MASK  (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17_SHIFT (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18_MASK  (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18_SHIFT (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19_MASK  (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19_SHIFT (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20_MASK  (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20_SHIFT (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21_MASK  (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21_SHIFT (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22_MASK  (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22_SHIFT (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23_MASK  (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23_SHIFT (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24_MASK  (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24_SHIFT (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25_MASK  (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25_SHIFT (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26_MASK  (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26_SHIFT (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27_MASK  (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27_SHIFT (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28_MASK  (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28_SHIFT (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29_MASK  (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29_SHIFT (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30_MASK  (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30_SHIFT (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31_MASK  (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31_SHIFT (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT2_1 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32_MASK  (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32_SHIFT (0U)
/*! LUTOUT32 - LUTOUT32 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33_MASK  (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33_SHIFT (1U)
/*! LUTOUT33 - LUTOUT33 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34_MASK  (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34_SHIFT (2U)
/*! LUTOUT34 - LUTOUT34 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35_MASK  (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35_SHIFT (3U)
/*! LUTOUT35 - LUTOUT35 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36_MASK  (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36_SHIFT (4U)
/*! LUTOUT36 - LUTOUT36 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37_MASK  (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37_SHIFT (5U)
/*! LUTOUT37 - LUTOUT37 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38_MASK  (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38_SHIFT (6U)
/*! LUTOUT38 - LUTOUT38 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39_MASK  (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39_SHIFT (7U)
/*! LUTOUT39 - LUTOUT39 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40_MASK  (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40_SHIFT (8U)
/*! LUTOUT40 - LUTOUT40 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41_MASK  (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41_SHIFT (9U)
/*! LUTOUT41 - LUTOUT41 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42_MASK  (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42_SHIFT (10U)
/*! LUTOUT42 - LUTOUT42 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43_MASK  (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43_SHIFT (11U)
/*! LUTOUT43 - LUTOUT43 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44_MASK  (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44_SHIFT (12U)
/*! LUTOUT44 - LUTOUT44 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45_MASK  (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45_SHIFT (13U)
/*! LUTOUT45 - LUTOUT45 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46_MASK  (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46_SHIFT (14U)
/*! LUTOUT46 - LUTOUT46 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47_MASK  (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47_SHIFT (15U)
/*! LUTOUT47 - LUTOUT47 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48_MASK  (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48_SHIFT (16U)
/*! LUTOUT48 - LUTOUT48 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49_MASK  (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49_SHIFT (17U)
/*! LUTOUT49 - LUTOUT49 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50_MASK  (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50_SHIFT (18U)
/*! LUTOUT50 - LUTOUT50 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51_MASK  (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51_SHIFT (19U)
/*! LUTOUT51 - LUTOUT51 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52_MASK  (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52_SHIFT (20U)
/*! LUTOUT52 - LUTOUT52 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53_MASK  (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53_SHIFT (21U)
/*! LUTOUT53 - LUTOUT53 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54_MASK  (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54_SHIFT (22U)
/*! LUTOUT54 - LUTOUT54 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55_MASK  (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55_SHIFT (23U)
/*! LUTOUT55 - LUTOUT55 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56_MASK  (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56_SHIFT (24U)
/*! LUTOUT56 - LUTOUT56 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57_MASK  (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57_SHIFT (25U)
/*! LUTOUT57 - LUTOUT57 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58_MASK  (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58_SHIFT (26U)
/*! LUTOUT58 - LUTOUT58 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59_MASK  (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59_SHIFT (27U)
/*! LUTOUT59 - LUTOUT59 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60_MASK  (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60_SHIFT (28U)
/*! LUTOUT60 - LUTOUT60 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61_MASK  (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61_SHIFT (29U)
/*! LUTOUT61 - LUTOUT61 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62_MASK  (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62_SHIFT (30U)
/*! LUTOUT62 - LUTOUT62 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63_MASK  (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63_SHIFT (31U)
/*! LUTOUT63 - LUTOUT63 */
#define PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT2_2 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64_MASK  (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64_SHIFT (0U)
/*! LUTOUT64 - LUTOUT64 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65_MASK  (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65_SHIFT (1U)
/*! LUTOUT65 - LUTOUT65 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66_MASK  (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66_SHIFT (2U)
/*! LUTOUT66 - LUTOUT66 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67_MASK  (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67_SHIFT (3U)
/*! LUTOUT67 - LUTOUT67 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68_MASK  (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68_SHIFT (4U)
/*! LUTOUT68 - LUTOUT68 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69_MASK  (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69_SHIFT (5U)
/*! LUTOUT69 - LUTOUT69 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70_MASK  (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70_SHIFT (6U)
/*! LUTOUT70 - LUTOUT70 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71_MASK  (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71_SHIFT (7U)
/*! LUTOUT71 - LUTOUT71 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72_MASK  (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72_SHIFT (8U)
/*! LUTOUT72 - LUTOUT72 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73_MASK  (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73_SHIFT (9U)
/*! LUTOUT73 - LUTOUT73 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74_MASK  (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74_SHIFT (10U)
/*! LUTOUT74 - LUTOUT74 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75_MASK  (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75_SHIFT (11U)
/*! LUTOUT75 - LUTOUT75 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76_MASK  (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76_SHIFT (12U)
/*! LUTOUT76 - LUTOUT76 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77_MASK  (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77_SHIFT (13U)
/*! LUTOUT77 - LUTOUT77 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78_MASK  (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78_SHIFT (14U)
/*! LUTOUT78 - LUTOUT78 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79_MASK  (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79_SHIFT (15U)
/*! LUTOUT79 - LUTOUT79 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80_MASK  (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80_SHIFT (16U)
/*! LUTOUT80 - LUTOUT80 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81_MASK  (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81_SHIFT (17U)
/*! LUTOUT81 - LUTOUT81 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82_MASK  (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82_SHIFT (18U)
/*! LUTOUT82 - LUTOUT82 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83_MASK  (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83_SHIFT (19U)
/*! LUTOUT83 - LUTOUT83 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84_MASK  (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84_SHIFT (20U)
/*! LUTOUT84 - LUTOUT84 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85_MASK  (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85_SHIFT (21U)
/*! LUTOUT85 - LUTOUT85 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86_MASK  (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86_SHIFT (22U)
/*! LUTOUT86 - LUTOUT86 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87_MASK  (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87_SHIFT (23U)
/*! LUTOUT87 - LUTOUT87 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88_MASK  (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88_SHIFT (24U)
/*! LUTOUT88 - LUTOUT88 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89_MASK  (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89_SHIFT (25U)
/*! LUTOUT89 - LUTOUT89 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90_MASK  (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90_SHIFT (26U)
/*! LUTOUT90 - LUTOUT90 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91_MASK  (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91_SHIFT (27U)
/*! LUTOUT91 - LUTOUT91 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92_MASK  (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92_SHIFT (28U)
/*! LUTOUT92 - LUTOUT92 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93_MASK  (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93_SHIFT (29U)
/*! LUTOUT93 - LUTOUT93 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94_MASK  (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94_SHIFT (30U)
/*! LUTOUT94 - LUTOUT94 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95_MASK  (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95_SHIFT (31U)
/*! LUTOUT95 - LUTOUT95 */
#define PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT2_3 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96_MASK  (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96_SHIFT (0U)
/*! LUTOUT96 - LUTOUT96 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97_MASK  (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97_SHIFT (1U)
/*! LUTOUT97 - LUTOUT97 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98_MASK  (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98_SHIFT (2U)
/*! LUTOUT98 - LUTOUT98 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99_MASK  (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99_SHIFT (3U)
/*! LUTOUT99 - LUTOUT99 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100_SHIFT (4U)
/*! LUTOUT100 - LUTOUT100 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101_SHIFT (5U)
/*! LUTOUT101 - LUTOUT101 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102_SHIFT (6U)
/*! LUTOUT102 - LUTOUT102 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103_SHIFT (7U)
/*! LUTOUT103 - LUTOUT103 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104_SHIFT (8U)
/*! LUTOUT104 - LUTOUT104 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105_SHIFT (9U)
/*! LUTOUT105 - LUTOUT105 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106_SHIFT (10U)
/*! LUTOUT106 - LUTOUT106 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107_SHIFT (11U)
/*! LUTOUT107 - LUTOUT107 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108_SHIFT (12U)
/*! LUTOUT108 - LUTOUT108 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109_SHIFT (13U)
/*! LUTOUT109 - LUTOUT109 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110_SHIFT (14U)
/*! LUTOUT110 - LUTOUT110 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111_SHIFT (15U)
/*! LUTOUT111 - LUTOUT111 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112_SHIFT (16U)
/*! LUTOUT112 - LUTOUT112 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113_SHIFT (17U)
/*! LUTOUT113 - LUTOUT113 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114_SHIFT (18U)
/*! LUTOUT114 - LUTOUT114 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115_SHIFT (19U)
/*! LUTOUT115 - LUTOUT115 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116_SHIFT (20U)
/*! LUTOUT116 - LUTOUT116 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117_SHIFT (21U)
/*! LUTOUT117 - LUTOUT117 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118_SHIFT (22U)
/*! LUTOUT118 - LUTOUT118 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119_SHIFT (23U)
/*! LUTOUT119 - LUTOUT119 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120_SHIFT (24U)
/*! LUTOUT120 - LUTOUT120 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121_SHIFT (25U)
/*! LUTOUT121 - LUTOUT121 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122_SHIFT (26U)
/*! LUTOUT122 - LUTOUT122 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123_SHIFT (27U)
/*! LUTOUT123 - LUTOUT123 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124_SHIFT (28U)
/*! LUTOUT124 - LUTOUT124 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125_SHIFT (29U)
/*! LUTOUT125 - LUTOUT125 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126_SHIFT (30U)
/*! LUTOUT126 - LUTOUT126 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127_SHIFT (31U)
/*! LUTOUT127 - LUTOUT127 */
#define PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT2_4 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128_SHIFT (0U)
/*! LUTOUT128 - LUTOUT128 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129_SHIFT (1U)
/*! LUTOUT129 - LUTOUT129 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130_SHIFT (2U)
/*! LUTOUT130 - LUTOUT130 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131_SHIFT (3U)
/*! LUTOUT131 - LUTOUT131 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132_SHIFT (4U)
/*! LUTOUT132 - LUTOUT132 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133_SHIFT (5U)
/*! LUTOUT133 - LUTOUT133 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134_SHIFT (6U)
/*! LUTOUT134 - LUTOUT134 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135_SHIFT (7U)
/*! LUTOUT135 - LUTOUT135 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136_SHIFT (8U)
/*! LUTOUT136 - LUTOUT136 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137_SHIFT (9U)
/*! LUTOUT137 - LUTOUT137 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138_SHIFT (10U)
/*! LUTOUT138 - LUTOUT138 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139_SHIFT (11U)
/*! LUTOUT139 - LUTOUT139 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140_SHIFT (12U)
/*! LUTOUT140 - LUTOUT140 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141_SHIFT (13U)
/*! LUTOUT141 - LUTOUT141 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142_SHIFT (14U)
/*! LUTOUT142 - LUTOUT142 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143_SHIFT (15U)
/*! LUTOUT143 - LUTOUT143 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144_SHIFT (16U)
/*! LUTOUT144 - LUTOUT144 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145_SHIFT (17U)
/*! LUTOUT145 - LUTOUT145 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146_SHIFT (18U)
/*! LUTOUT146 - LUTOUT146 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147_SHIFT (19U)
/*! LUTOUT147 - LUTOUT147 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148_SHIFT (20U)
/*! LUTOUT148 - LUTOUT148 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149_SHIFT (21U)
/*! LUTOUT149 - LUTOUT149 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150_SHIFT (22U)
/*! LUTOUT150 - LUTOUT150 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151_SHIFT (23U)
/*! LUTOUT151 - LUTOUT151 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152_SHIFT (24U)
/*! LUTOUT152 - LUTOUT152 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153_SHIFT (25U)
/*! LUTOUT153 - LUTOUT153 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154_SHIFT (26U)
/*! LUTOUT154 - LUTOUT154 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155_SHIFT (27U)
/*! LUTOUT155 - LUTOUT155 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156_SHIFT (28U)
/*! LUTOUT156 - LUTOUT156 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157_SHIFT (29U)
/*! LUTOUT157 - LUTOUT157 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158_SHIFT (30U)
/*! LUTOUT158 - LUTOUT158 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159_SHIFT (31U)
/*! LUTOUT159 - LUTOUT159 */
#define PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT2_5 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160_SHIFT (0U)
/*! LUTOUT160 - LUTOUT160 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161_SHIFT (1U)
/*! LUTOUT161 - LUTOUT161 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162_SHIFT (2U)
/*! LUTOUT162 - LUTOUT162 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163_SHIFT (3U)
/*! LUTOUT163 - LUTOUT163 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164_SHIFT (4U)
/*! LUTOUT164 - LUTOUT164 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165_SHIFT (5U)
/*! LUTOUT165 - LUTOUT165 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166_SHIFT (6U)
/*! LUTOUT166 - LUTOUT166 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167_SHIFT (7U)
/*! LUTOUT167 - LUTOUT167 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168_SHIFT (8U)
/*! LUTOUT168 - LUTOUT168 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169_SHIFT (9U)
/*! LUTOUT169 - LUTOUT169 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170_SHIFT (10U)
/*! LUTOUT170 - LUTOUT170 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171_SHIFT (11U)
/*! LUTOUT171 - LUTOUT171 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172_SHIFT (12U)
/*! LUTOUT172 - LUTOUT172 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173_SHIFT (13U)
/*! LUTOUT173 - LUTOUT173 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174_SHIFT (14U)
/*! LUTOUT174 - LUTOUT174 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175_SHIFT (15U)
/*! LUTOUT175 - LUTOUT175 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176_SHIFT (16U)
/*! LUTOUT176 - LUTOUT176 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177_SHIFT (17U)
/*! LUTOUT177 - LUTOUT177 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178_SHIFT (18U)
/*! LUTOUT178 - LUTOUT178 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179_SHIFT (19U)
/*! LUTOUT179 - LUTOUT179 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180_SHIFT (20U)
/*! LUTOUT180 - LUTOUT180 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181_SHIFT (21U)
/*! LUTOUT181 - LUTOUT181 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182_SHIFT (22U)
/*! LUTOUT182 - LUTOUT182 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183_SHIFT (23U)
/*! LUTOUT183 - LUTOUT183 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184_SHIFT (24U)
/*! LUTOUT184 - LUTOUT184 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185_SHIFT (25U)
/*! LUTOUT185 - LUTOUT185 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186_SHIFT (26U)
/*! LUTOUT186 - LUTOUT186 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187_SHIFT (27U)
/*! LUTOUT187 - LUTOUT187 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188_SHIFT (28U)
/*! LUTOUT188 - LUTOUT188 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189_SHIFT (29U)
/*! LUTOUT189 - LUTOUT189 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190_SHIFT (30U)
/*! LUTOUT190 - LUTOUT190 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191_SHIFT (31U)
/*! LUTOUT191 - LUTOUT191 */
#define PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT2_6 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192_SHIFT (0U)
/*! LUTOUT192 - LUTOUT192 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193_SHIFT (1U)
/*! LUTOUT193 - LUTOUT193 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194_SHIFT (2U)
/*! LUTOUT194 - LUTOUT194 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195_SHIFT (3U)
/*! LUTOUT195 - LUTOUT195 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196_SHIFT (4U)
/*! LUTOUT196 - LUTOUT196 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197_SHIFT (5U)
/*! LUTOUT197 - LUTOUT197 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198_SHIFT (6U)
/*! LUTOUT198 - LUTOUT198 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199_SHIFT (7U)
/*! LUTOUT199 - LUTOUT199 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200_SHIFT (8U)
/*! LUTOUT200 - LUTOUT200 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201_SHIFT (9U)
/*! LUTOUT201 - LUTOUT201 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202_SHIFT (10U)
/*! LUTOUT202 - LUTOUT202 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203_SHIFT (11U)
/*! LUTOUT203 - LUTOUT203 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204_SHIFT (12U)
/*! LUTOUT204 - LUTOUT204 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205_SHIFT (13U)
/*! LUTOUT205 - LUTOUT205 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206_SHIFT (14U)
/*! LUTOUT206 - LUTOUT206 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207_SHIFT (15U)
/*! LUTOUT207 - LUTOUT207 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208_SHIFT (16U)
/*! LUTOUT208 - LUTOUT208 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209_SHIFT (17U)
/*! LUTOUT209 - LUTOUT209 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210_SHIFT (18U)
/*! LUTOUT210 - LUTOUT210 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211_SHIFT (19U)
/*! LUTOUT211 - LUTOUT211 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212_SHIFT (20U)
/*! LUTOUT212 - LUTOUT212 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213_SHIFT (21U)
/*! LUTOUT213 - LUTOUT213 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214_SHIFT (22U)
/*! LUTOUT214 - LUTOUT214 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215_SHIFT (23U)
/*! LUTOUT215 - LUTOUT215 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216_SHIFT (24U)
/*! LUTOUT216 - LUTOUT216 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217_SHIFT (25U)
/*! LUTOUT217 - LUTOUT217 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218_SHIFT (26U)
/*! LUTOUT218 - LUTOUT218 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219_SHIFT (27U)
/*! LUTOUT219 - LUTOUT219 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220_SHIFT (28U)
/*! LUTOUT220 - LUTOUT220 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221_SHIFT (29U)
/*! LUTOUT221 - LUTOUT221 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222_SHIFT (30U)
/*! LUTOUT222 - LUTOUT222 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223_SHIFT (31U)
/*! LUTOUT223 - LUTOUT223 */
#define PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT2_7 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224_SHIFT (0U)
/*! LUTOUT224 - LUTOUT224 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225_SHIFT (1U)
/*! LUTOUT225 - LUTOUT225 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226_SHIFT (2U)
/*! LUTOUT226 - LUTOUT226 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227_SHIFT (3U)
/*! LUTOUT227 - LUTOUT227 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228_SHIFT (4U)
/*! LUTOUT228 - LUTOUT228 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229_SHIFT (5U)
/*! LUTOUT229 - LUTOUT229 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230_SHIFT (6U)
/*! LUTOUT230 - LUTOUT230 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231_SHIFT (7U)
/*! LUTOUT231 - LUTOUT231 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232_SHIFT (8U)
/*! LUTOUT232 - LUTOUT232 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233_SHIFT (9U)
/*! LUTOUT233 - LUTOUT233 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234_SHIFT (10U)
/*! LUTOUT234 - LUTOUT234 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235_SHIFT (11U)
/*! LUTOUT235 - LUTOUT235 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236_SHIFT (12U)
/*! LUTOUT236 - LUTOUT236 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237_SHIFT (13U)
/*! LUTOUT237 - LUTOUT237 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238_SHIFT (14U)
/*! LUTOUT238 - LUTOUT238 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239_SHIFT (15U)
/*! LUTOUT239 - LUTOUT239 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240_SHIFT (16U)
/*! LUTOUT240 - LUTOUT240 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241_SHIFT (17U)
/*! LUTOUT241 - LUTOUT241 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242_SHIFT (18U)
/*! LUTOUT242 - LUTOUT242 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243_SHIFT (19U)
/*! LUTOUT243 - LUTOUT243 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244_SHIFT (20U)
/*! LUTOUT244 - LUTOUT244 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245_SHIFT (21U)
/*! LUTOUT245 - LUTOUT245 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246_SHIFT (22U)
/*! LUTOUT246 - LUTOUT246 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247_SHIFT (23U)
/*! LUTOUT247 - LUTOUT247 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248_SHIFT (24U)
/*! LUTOUT248 - LUTOUT248 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249_SHIFT (25U)
/*! LUTOUT249 - LUTOUT249 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250_SHIFT (26U)
/*! LUTOUT250 - LUTOUT250 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251_SHIFT (27U)
/*! LUTOUT251 - LUTOUT251 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252_SHIFT (28U)
/*! LUTOUT252 - LUTOUT252 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253_SHIFT (29U)
/*! LUTOUT253 - LUTOUT253 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254_SHIFT (30U)
/*! LUTOUT254 - LUTOUT254 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254_MASK)

#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255_SHIFT (31U)
/*! LUTOUT255 - LUTOUT255 */
#define PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT3_0 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0_MASK   (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1_MASK   (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1_SHIFT  (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2_MASK   (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2_SHIFT  (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3_MASK   (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3_SHIFT  (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4_MASK   (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4_SHIFT  (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5_MASK   (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5_SHIFT  (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6_MASK   (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6_SHIFT  (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7_MASK   (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7_SHIFT  (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8_MASK   (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8_SHIFT  (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9_MASK   (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9_SHIFT  (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10_MASK  (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10_SHIFT (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11_MASK  (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11_SHIFT (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12_MASK  (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12_SHIFT (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13_MASK  (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13_SHIFT (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14_MASK  (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14_SHIFT (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15_MASK  (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15_SHIFT (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16_MASK  (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16_SHIFT (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17_MASK  (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17_SHIFT (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18_MASK  (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18_SHIFT (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19_MASK  (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19_SHIFT (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20_MASK  (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20_SHIFT (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21_MASK  (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21_SHIFT (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22_MASK  (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22_SHIFT (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23_MASK  (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23_SHIFT (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24_MASK  (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24_SHIFT (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25_MASK  (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25_SHIFT (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26_MASK  (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26_SHIFT (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27_MASK  (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27_SHIFT (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28_MASK  (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28_SHIFT (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29_MASK  (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29_SHIFT (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30_MASK  (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30_SHIFT (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31_MASK  (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31_SHIFT (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT3_1 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32_MASK  (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32_SHIFT (0U)
/*! LUTOUT32 - LUTOUT32 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33_MASK  (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33_SHIFT (1U)
/*! LUTOUT33 - LUTOUT33 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34_MASK  (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34_SHIFT (2U)
/*! LUTOUT34 - LUTOUT34 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35_MASK  (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35_SHIFT (3U)
/*! LUTOUT35 - LUTOUT35 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36_MASK  (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36_SHIFT (4U)
/*! LUTOUT36 - LUTOUT36 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37_MASK  (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37_SHIFT (5U)
/*! LUTOUT37 - LUTOUT37 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38_MASK  (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38_SHIFT (6U)
/*! LUTOUT38 - LUTOUT38 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39_MASK  (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39_SHIFT (7U)
/*! LUTOUT39 - LUTOUT39 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40_MASK  (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40_SHIFT (8U)
/*! LUTOUT40 - LUTOUT40 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41_MASK  (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41_SHIFT (9U)
/*! LUTOUT41 - LUTOUT41 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42_MASK  (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42_SHIFT (10U)
/*! LUTOUT42 - LUTOUT42 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43_MASK  (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43_SHIFT (11U)
/*! LUTOUT43 - LUTOUT43 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44_MASK  (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44_SHIFT (12U)
/*! LUTOUT44 - LUTOUT44 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45_MASK  (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45_SHIFT (13U)
/*! LUTOUT45 - LUTOUT45 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46_MASK  (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46_SHIFT (14U)
/*! LUTOUT46 - LUTOUT46 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47_MASK  (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47_SHIFT (15U)
/*! LUTOUT47 - LUTOUT47 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48_MASK  (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48_SHIFT (16U)
/*! LUTOUT48 - LUTOUT48 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49_MASK  (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49_SHIFT (17U)
/*! LUTOUT49 - LUTOUT49 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50_MASK  (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50_SHIFT (18U)
/*! LUTOUT50 - LUTOUT50 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51_MASK  (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51_SHIFT (19U)
/*! LUTOUT51 - LUTOUT51 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52_MASK  (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52_SHIFT (20U)
/*! LUTOUT52 - LUTOUT52 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53_MASK  (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53_SHIFT (21U)
/*! LUTOUT53 - LUTOUT53 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54_MASK  (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54_SHIFT (22U)
/*! LUTOUT54 - LUTOUT54 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55_MASK  (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55_SHIFT (23U)
/*! LUTOUT55 - LUTOUT55 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56_MASK  (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56_SHIFT (24U)
/*! LUTOUT56 - LUTOUT56 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57_MASK  (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57_SHIFT (25U)
/*! LUTOUT57 - LUTOUT57 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58_MASK  (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58_SHIFT (26U)
/*! LUTOUT58 - LUTOUT58 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59_MASK  (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59_SHIFT (27U)
/*! LUTOUT59 - LUTOUT59 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60_MASK  (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60_SHIFT (28U)
/*! LUTOUT60 - LUTOUT60 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61_MASK  (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61_SHIFT (29U)
/*! LUTOUT61 - LUTOUT61 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62_MASK  (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62_SHIFT (30U)
/*! LUTOUT62 - LUTOUT62 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63_MASK  (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63_SHIFT (31U)
/*! LUTOUT63 - LUTOUT63 */
#define PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT3_2 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64_MASK  (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64_SHIFT (0U)
/*! LUTOUT64 - LUTOUT64 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65_MASK  (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65_SHIFT (1U)
/*! LUTOUT65 - LUTOUT65 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66_MASK  (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66_SHIFT (2U)
/*! LUTOUT66 - LUTOUT66 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67_MASK  (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67_SHIFT (3U)
/*! LUTOUT67 - LUTOUT67 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68_MASK  (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68_SHIFT (4U)
/*! LUTOUT68 - LUTOUT68 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69_MASK  (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69_SHIFT (5U)
/*! LUTOUT69 - LUTOUT69 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70_MASK  (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70_SHIFT (6U)
/*! LUTOUT70 - LUTOUT70 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71_MASK  (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71_SHIFT (7U)
/*! LUTOUT71 - LUTOUT71 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72_MASK  (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72_SHIFT (8U)
/*! LUTOUT72 - LUTOUT72 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73_MASK  (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73_SHIFT (9U)
/*! LUTOUT73 - LUTOUT73 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74_MASK  (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74_SHIFT (10U)
/*! LUTOUT74 - LUTOUT74 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75_MASK  (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75_SHIFT (11U)
/*! LUTOUT75 - LUTOUT75 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76_MASK  (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76_SHIFT (12U)
/*! LUTOUT76 - LUTOUT76 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77_MASK  (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77_SHIFT (13U)
/*! LUTOUT77 - LUTOUT77 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78_MASK  (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78_SHIFT (14U)
/*! LUTOUT78 - LUTOUT78 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79_MASK  (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79_SHIFT (15U)
/*! LUTOUT79 - LUTOUT79 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80_MASK  (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80_SHIFT (16U)
/*! LUTOUT80 - LUTOUT80 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81_MASK  (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81_SHIFT (17U)
/*! LUTOUT81 - LUTOUT81 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82_MASK  (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82_SHIFT (18U)
/*! LUTOUT82 - LUTOUT82 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83_MASK  (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83_SHIFT (19U)
/*! LUTOUT83 - LUTOUT83 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84_MASK  (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84_SHIFT (20U)
/*! LUTOUT84 - LUTOUT84 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85_MASK  (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85_SHIFT (21U)
/*! LUTOUT85 - LUTOUT85 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86_MASK  (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86_SHIFT (22U)
/*! LUTOUT86 - LUTOUT86 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87_MASK  (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87_SHIFT (23U)
/*! LUTOUT87 - LUTOUT87 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88_MASK  (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88_SHIFT (24U)
/*! LUTOUT88 - LUTOUT88 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89_MASK  (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89_SHIFT (25U)
/*! LUTOUT89 - LUTOUT89 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90_MASK  (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90_SHIFT (26U)
/*! LUTOUT90 - LUTOUT90 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91_MASK  (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91_SHIFT (27U)
/*! LUTOUT91 - LUTOUT91 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92_MASK  (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92_SHIFT (28U)
/*! LUTOUT92 - LUTOUT92 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93_MASK  (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93_SHIFT (29U)
/*! LUTOUT93 - LUTOUT93 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94_MASK  (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94_SHIFT (30U)
/*! LUTOUT94 - LUTOUT94 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95_MASK  (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95_SHIFT (31U)
/*! LUTOUT95 - LUTOUT95 */
#define PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT3_3 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96_MASK  (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96_SHIFT (0U)
/*! LUTOUT96 - LUTOUT96 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97_MASK  (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97_SHIFT (1U)
/*! LUTOUT97 - LUTOUT97 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98_MASK  (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98_SHIFT (2U)
/*! LUTOUT98 - LUTOUT98 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99_MASK  (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99_SHIFT (3U)
/*! LUTOUT99 - LUTOUT99 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100_SHIFT (4U)
/*! LUTOUT100 - LUTOUT100 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101_SHIFT (5U)
/*! LUTOUT101 - LUTOUT101 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102_SHIFT (6U)
/*! LUTOUT102 - LUTOUT102 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103_SHIFT (7U)
/*! LUTOUT103 - LUTOUT103 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104_SHIFT (8U)
/*! LUTOUT104 - LUTOUT104 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105_SHIFT (9U)
/*! LUTOUT105 - LUTOUT105 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106_SHIFT (10U)
/*! LUTOUT106 - LUTOUT106 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107_SHIFT (11U)
/*! LUTOUT107 - LUTOUT107 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108_SHIFT (12U)
/*! LUTOUT108 - LUTOUT108 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109_SHIFT (13U)
/*! LUTOUT109 - LUTOUT109 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110_SHIFT (14U)
/*! LUTOUT110 - LUTOUT110 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111_SHIFT (15U)
/*! LUTOUT111 - LUTOUT111 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112_SHIFT (16U)
/*! LUTOUT112 - LUTOUT112 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113_SHIFT (17U)
/*! LUTOUT113 - LUTOUT113 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114_SHIFT (18U)
/*! LUTOUT114 - LUTOUT114 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115_SHIFT (19U)
/*! LUTOUT115 - LUTOUT115 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116_SHIFT (20U)
/*! LUTOUT116 - LUTOUT116 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117_SHIFT (21U)
/*! LUTOUT117 - LUTOUT117 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118_SHIFT (22U)
/*! LUTOUT118 - LUTOUT118 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119_SHIFT (23U)
/*! LUTOUT119 - LUTOUT119 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120_SHIFT (24U)
/*! LUTOUT120 - LUTOUT120 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121_SHIFT (25U)
/*! LUTOUT121 - LUTOUT121 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122_SHIFT (26U)
/*! LUTOUT122 - LUTOUT122 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123_SHIFT (27U)
/*! LUTOUT123 - LUTOUT123 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124_SHIFT (28U)
/*! LUTOUT124 - LUTOUT124 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125_SHIFT (29U)
/*! LUTOUT125 - LUTOUT125 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126_SHIFT (30U)
/*! LUTOUT126 - LUTOUT126 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127_SHIFT (31U)
/*! LUTOUT127 - LUTOUT127 */
#define PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT3_4 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128_SHIFT (0U)
/*! LUTOUT128 - LUTOUT128 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129_SHIFT (1U)
/*! LUTOUT129 - LUTOUT129 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130_SHIFT (2U)
/*! LUTOUT130 - LUTOUT130 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131_SHIFT (3U)
/*! LUTOUT131 - LUTOUT131 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132_SHIFT (4U)
/*! LUTOUT132 - LUTOUT132 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133_SHIFT (5U)
/*! LUTOUT133 - LUTOUT133 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134_SHIFT (6U)
/*! LUTOUT134 - LUTOUT134 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135_SHIFT (7U)
/*! LUTOUT135 - LUTOUT135 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136_SHIFT (8U)
/*! LUTOUT136 - LUTOUT136 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137_SHIFT (9U)
/*! LUTOUT137 - LUTOUT137 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138_SHIFT (10U)
/*! LUTOUT138 - LUTOUT138 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139_SHIFT (11U)
/*! LUTOUT139 - LUTOUT139 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140_SHIFT (12U)
/*! LUTOUT140 - LUTOUT140 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141_SHIFT (13U)
/*! LUTOUT141 - LUTOUT141 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142_SHIFT (14U)
/*! LUTOUT142 - LUTOUT142 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143_SHIFT (15U)
/*! LUTOUT143 - LUTOUT143 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144_SHIFT (16U)
/*! LUTOUT144 - LUTOUT144 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145_SHIFT (17U)
/*! LUTOUT145 - LUTOUT145 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146_SHIFT (18U)
/*! LUTOUT146 - LUTOUT146 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147_SHIFT (19U)
/*! LUTOUT147 - LUTOUT147 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148_SHIFT (20U)
/*! LUTOUT148 - LUTOUT148 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149_SHIFT (21U)
/*! LUTOUT149 - LUTOUT149 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150_SHIFT (22U)
/*! LUTOUT150 - LUTOUT150 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151_SHIFT (23U)
/*! LUTOUT151 - LUTOUT151 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152_SHIFT (24U)
/*! LUTOUT152 - LUTOUT152 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153_SHIFT (25U)
/*! LUTOUT153 - LUTOUT153 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154_SHIFT (26U)
/*! LUTOUT154 - LUTOUT154 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155_SHIFT (27U)
/*! LUTOUT155 - LUTOUT155 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156_SHIFT (28U)
/*! LUTOUT156 - LUTOUT156 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157_SHIFT (29U)
/*! LUTOUT157 - LUTOUT157 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158_SHIFT (30U)
/*! LUTOUT158 - LUTOUT158 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159_SHIFT (31U)
/*! LUTOUT159 - LUTOUT159 */
#define PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT3_5 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160_SHIFT (0U)
/*! LUTOUT160 - LUTOUT160 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161_SHIFT (1U)
/*! LUTOUT161 - LUTOUT161 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162_SHIFT (2U)
/*! LUTOUT162 - LUTOUT162 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163_SHIFT (3U)
/*! LUTOUT163 - LUTOUT163 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164_SHIFT (4U)
/*! LUTOUT164 - LUTOUT164 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165_SHIFT (5U)
/*! LUTOUT165 - LUTOUT165 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166_SHIFT (6U)
/*! LUTOUT166 - LUTOUT166 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167_SHIFT (7U)
/*! LUTOUT167 - LUTOUT167 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168_SHIFT (8U)
/*! LUTOUT168 - LUTOUT168 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169_SHIFT (9U)
/*! LUTOUT169 - LUTOUT169 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170_SHIFT (10U)
/*! LUTOUT170 - LUTOUT170 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171_SHIFT (11U)
/*! LUTOUT171 - LUTOUT171 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172_SHIFT (12U)
/*! LUTOUT172 - LUTOUT172 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173_SHIFT (13U)
/*! LUTOUT173 - LUTOUT173 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174_SHIFT (14U)
/*! LUTOUT174 - LUTOUT174 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175_SHIFT (15U)
/*! LUTOUT175 - LUTOUT175 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176_SHIFT (16U)
/*! LUTOUT176 - LUTOUT176 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177_SHIFT (17U)
/*! LUTOUT177 - LUTOUT177 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178_SHIFT (18U)
/*! LUTOUT178 - LUTOUT178 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179_SHIFT (19U)
/*! LUTOUT179 - LUTOUT179 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180_SHIFT (20U)
/*! LUTOUT180 - LUTOUT180 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181_SHIFT (21U)
/*! LUTOUT181 - LUTOUT181 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182_SHIFT (22U)
/*! LUTOUT182 - LUTOUT182 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183_SHIFT (23U)
/*! LUTOUT183 - LUTOUT183 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184_SHIFT (24U)
/*! LUTOUT184 - LUTOUT184 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185_SHIFT (25U)
/*! LUTOUT185 - LUTOUT185 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186_SHIFT (26U)
/*! LUTOUT186 - LUTOUT186 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187_SHIFT (27U)
/*! LUTOUT187 - LUTOUT187 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188_SHIFT (28U)
/*! LUTOUT188 - LUTOUT188 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189_SHIFT (29U)
/*! LUTOUT189 - LUTOUT189 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190_SHIFT (30U)
/*! LUTOUT190 - LUTOUT190 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191_SHIFT (31U)
/*! LUTOUT191 - LUTOUT191 */
#define PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT3_6 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192_SHIFT (0U)
/*! LUTOUT192 - LUTOUT192 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193_SHIFT (1U)
/*! LUTOUT193 - LUTOUT193 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194_SHIFT (2U)
/*! LUTOUT194 - LUTOUT194 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195_SHIFT (3U)
/*! LUTOUT195 - LUTOUT195 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196_SHIFT (4U)
/*! LUTOUT196 - LUTOUT196 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197_SHIFT (5U)
/*! LUTOUT197 - LUTOUT197 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198_SHIFT (6U)
/*! LUTOUT198 - LUTOUT198 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199_SHIFT (7U)
/*! LUTOUT199 - LUTOUT199 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200_SHIFT (8U)
/*! LUTOUT200 - LUTOUT200 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201_SHIFT (9U)
/*! LUTOUT201 - LUTOUT201 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202_SHIFT (10U)
/*! LUTOUT202 - LUTOUT202 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203_SHIFT (11U)
/*! LUTOUT203 - LUTOUT203 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204_SHIFT (12U)
/*! LUTOUT204 - LUTOUT204 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205_SHIFT (13U)
/*! LUTOUT205 - LUTOUT205 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206_SHIFT (14U)
/*! LUTOUT206 - LUTOUT206 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207_SHIFT (15U)
/*! LUTOUT207 - LUTOUT207 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208_SHIFT (16U)
/*! LUTOUT208 - LUTOUT208 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209_SHIFT (17U)
/*! LUTOUT209 - LUTOUT209 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210_SHIFT (18U)
/*! LUTOUT210 - LUTOUT210 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211_SHIFT (19U)
/*! LUTOUT211 - LUTOUT211 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212_SHIFT (20U)
/*! LUTOUT212 - LUTOUT212 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213_SHIFT (21U)
/*! LUTOUT213 - LUTOUT213 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214_SHIFT (22U)
/*! LUTOUT214 - LUTOUT214 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215_SHIFT (23U)
/*! LUTOUT215 - LUTOUT215 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216_SHIFT (24U)
/*! LUTOUT216 - LUTOUT216 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217_SHIFT (25U)
/*! LUTOUT217 - LUTOUT217 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218_SHIFT (26U)
/*! LUTOUT218 - LUTOUT218 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219_SHIFT (27U)
/*! LUTOUT219 - LUTOUT219 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220_SHIFT (28U)
/*! LUTOUT220 - LUTOUT220 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221_SHIFT (29U)
/*! LUTOUT221 - LUTOUT221 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222_SHIFT (30U)
/*! LUTOUT222 - LUTOUT222 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223_SHIFT (31U)
/*! LUTOUT223 - LUTOUT223 */
#define PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223_MASK)
/*! @} */

/*! @name WFE_A_STG1_8X1_OUT3_7 -  */
/*! @{ */

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224_MASK (0x1U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224_SHIFT (0U)
/*! LUTOUT224 - LUTOUT224 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225_MASK (0x2U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225_SHIFT (1U)
/*! LUTOUT225 - LUTOUT225 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226_MASK (0x4U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226_SHIFT (2U)
/*! LUTOUT226 - LUTOUT226 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227_MASK (0x8U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227_SHIFT (3U)
/*! LUTOUT227 - LUTOUT227 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228_MASK (0x10U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228_SHIFT (4U)
/*! LUTOUT228 - LUTOUT228 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229_MASK (0x20U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229_SHIFT (5U)
/*! LUTOUT229 - LUTOUT229 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230_MASK (0x40U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230_SHIFT (6U)
/*! LUTOUT230 - LUTOUT230 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231_MASK (0x80U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231_SHIFT (7U)
/*! LUTOUT231 - LUTOUT231 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232_MASK (0x100U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232_SHIFT (8U)
/*! LUTOUT232 - LUTOUT232 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233_MASK (0x200U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233_SHIFT (9U)
/*! LUTOUT233 - LUTOUT233 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234_MASK (0x400U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234_SHIFT (10U)
/*! LUTOUT234 - LUTOUT234 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235_MASK (0x800U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235_SHIFT (11U)
/*! LUTOUT235 - LUTOUT235 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236_MASK (0x1000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236_SHIFT (12U)
/*! LUTOUT236 - LUTOUT236 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237_MASK (0x2000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237_SHIFT (13U)
/*! LUTOUT237 - LUTOUT237 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238_MASK (0x4000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238_SHIFT (14U)
/*! LUTOUT238 - LUTOUT238 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239_MASK (0x8000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239_SHIFT (15U)
/*! LUTOUT239 - LUTOUT239 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240_MASK (0x10000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240_SHIFT (16U)
/*! LUTOUT240 - LUTOUT240 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241_MASK (0x20000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241_SHIFT (17U)
/*! LUTOUT241 - LUTOUT241 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242_MASK (0x40000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242_SHIFT (18U)
/*! LUTOUT242 - LUTOUT242 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243_MASK (0x80000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243_SHIFT (19U)
/*! LUTOUT243 - LUTOUT243 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244_MASK (0x100000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244_SHIFT (20U)
/*! LUTOUT244 - LUTOUT244 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245_MASK (0x200000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245_SHIFT (21U)
/*! LUTOUT245 - LUTOUT245 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246_MASK (0x400000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246_SHIFT (22U)
/*! LUTOUT246 - LUTOUT246 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247_MASK (0x800000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247_SHIFT (23U)
/*! LUTOUT247 - LUTOUT247 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248_MASK (0x1000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248_SHIFT (24U)
/*! LUTOUT248 - LUTOUT248 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249_MASK (0x2000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249_SHIFT (25U)
/*! LUTOUT249 - LUTOUT249 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250_MASK (0x4000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250_SHIFT (26U)
/*! LUTOUT250 - LUTOUT250 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251_MASK (0x8000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251_SHIFT (27U)
/*! LUTOUT251 - LUTOUT251 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252_MASK (0x10000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252_SHIFT (28U)
/*! LUTOUT252 - LUTOUT252 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253_MASK (0x20000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253_SHIFT (29U)
/*! LUTOUT253 - LUTOUT253 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254_MASK (0x40000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254_SHIFT (30U)
/*! LUTOUT254 - LUTOUT254 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254_MASK)

#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255_MASK (0x80000000U)
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255_SHIFT (31U)
/*! LUTOUT255 - LUTOUT255 */
#define PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255_SHIFT)) & PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT0_0 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0_MASK   (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1_MASK   (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1_SHIFT  (8U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2_MASK   (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2_SHIFT  (16U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3_MASK   (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3_SHIFT  (24U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT0_1 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4_MASK   (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4_SHIFT  (0U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5_MASK   (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5_SHIFT  (8U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6_MASK   (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6_SHIFT  (16U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7_MASK   (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7_SHIFT  (24U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT0_2 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8_MASK   (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8_SHIFT  (0U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9_MASK   (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9_SHIFT  (8U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10_SHIFT (16U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11_SHIFT (24U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT0_3 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12_SHIFT (0U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13_SHIFT (8U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14_SHIFT (16U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15_SHIFT (24U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT0_4 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16_SHIFT (0U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17_SHIFT (8U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18_SHIFT (16U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19_SHIFT (24U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT0_5 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20_SHIFT (0U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21_SHIFT (8U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22_SHIFT (16U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23_SHIFT (24U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT0_6 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24_SHIFT (0U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25_SHIFT (8U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26_SHIFT (16U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27_SHIFT (24U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT0_7 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28_SHIFT (0U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29_SHIFT (8U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30_SHIFT (16U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31_SHIFT (24U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31_MASK)

#define PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT1_0 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0_MASK   (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1_MASK   (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1_SHIFT  (8U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2_MASK   (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2_SHIFT  (16U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3_MASK   (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3_SHIFT  (24U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT1_1 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4_MASK   (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4_SHIFT  (0U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5_MASK   (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5_SHIFT  (8U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6_MASK   (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6_SHIFT  (16U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7_MASK   (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7_SHIFT  (24U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT1_2 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8_MASK   (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8_SHIFT  (0U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9_MASK   (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9_SHIFT  (8U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10_SHIFT (16U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11_SHIFT (24U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT1_3 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12_SHIFT (0U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13_SHIFT (8U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14_SHIFT (16U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15_SHIFT (24U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT1_4 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16_SHIFT (0U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17_SHIFT (8U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18_SHIFT (16U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19_SHIFT (24U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT1_5 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20_SHIFT (0U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21_SHIFT (8U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22_SHIFT (16U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23_SHIFT (24U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT1_6 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24_SHIFT (0U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25_SHIFT (8U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26_SHIFT (16U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27_SHIFT (24U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT1_7 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28_SHIFT (0U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29_SHIFT (8U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30_SHIFT (16U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31_SHIFT (24U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31_MASK)

#define PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT2_0 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0_MASK   (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1_MASK   (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1_SHIFT  (8U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2_MASK   (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2_SHIFT  (16U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3_MASK   (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3_SHIFT  (24U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT2_1 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4_MASK   (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4_SHIFT  (0U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5_MASK   (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5_SHIFT  (8U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6_MASK   (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6_SHIFT  (16U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7_MASK   (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7_SHIFT  (24U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT2_2 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8_MASK   (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8_SHIFT  (0U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9_MASK   (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9_SHIFT  (8U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10_SHIFT (16U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11_SHIFT (24U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT2_3 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12_SHIFT (0U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13_SHIFT (8U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14_SHIFT (16U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15_SHIFT (24U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT2_4 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16_SHIFT (0U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17_SHIFT (8U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18_SHIFT (16U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19_SHIFT (24U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT2_5 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20_SHIFT (0U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21_SHIFT (8U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22_SHIFT (16U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23_SHIFT (24U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT2_6 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24_SHIFT (0U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25_SHIFT (8U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26_SHIFT (16U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27_SHIFT (24U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT2_7 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28_SHIFT (0U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29_SHIFT (8U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30_SHIFT (16U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31_SHIFT (24U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31_MASK)

#define PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT3_0 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0_MASK   (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1_MASK   (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1_SHIFT  (8U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2_MASK   (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2_SHIFT  (16U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3_MASK   (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3_SHIFT  (24U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT3_1 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4_MASK   (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4_SHIFT  (0U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5_MASK   (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5_SHIFT  (8U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6_MASK   (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6_SHIFT  (16U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7_MASK   (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7_SHIFT  (24U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT3_2 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8_MASK   (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8_SHIFT  (0U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9_MASK   (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9_SHIFT  (8U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10_SHIFT (16U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11_SHIFT (24U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT3_3 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12_SHIFT (0U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13_SHIFT (8U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14_SHIFT (16U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15_SHIFT (24U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT3_4 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16_SHIFT (0U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17_SHIFT (8U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18_SHIFT (16U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19_SHIFT (24U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT3_5 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20_SHIFT (0U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21_SHIFT (8U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22_SHIFT (16U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23_SHIFT (24U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT3_6 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24_SHIFT (0U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25_SHIFT (8U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26_SHIFT (16U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27_SHIFT (24U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X6_OUT3_7 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28_MASK  (0x3FU)
#define PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28_SHIFT (0U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3_MASK     (0xC0U)
#define PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29_MASK  (0x3F00U)
#define PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29_SHIFT (8U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2_MASK     (0xC000U)
#define PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30_MASK  (0x3F0000U)
#define PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30_SHIFT (16U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31_MASK  (0x3F000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31_SHIFT (24U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31_MASK)

#define PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_5X6_MASKS_0 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0_MASK  (0x1FU)
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0_SHIFT (0U)
/*! MASK0 - MASK0 */
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0_SHIFT)) & PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0_MASK)

#define PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3_MASK  (0xE0U)
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1_MASK  (0x1F00U)
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1_SHIFT (8U)
/*! MASK1 - MASK1 */
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1_SHIFT)) & PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1_MASK)

#define PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2_MASK  (0xE000U)
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2_MASK  (0x1F0000U)
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2_SHIFT (16U)
/*! MASK2 - MASK2 */
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2_SHIFT)) & PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2_MASK)

#define PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1_MASK  (0xE00000U)
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1_SHIFT (21U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3_MASK  (0x1F000000U)
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3_SHIFT (24U)
/*! MASK3 - MASK3 */
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3_SHIFT)) & PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3_MASK)

#define PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0_MASK  (0xE0000000U)
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0_SHIFT (29U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STAGE2_5X6_ADDR_0 -  */
/*! @{ */

#define PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0_MASK (0x3FU)
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0_SHIFT (0U)
/*! MUXADDR0 - MUXADDR0 */
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0_SHIFT)) & PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0_MASK)

#define PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3_MASK   (0xC0U)
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3_SHIFT  (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3_SHIFT)) & PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3_MASK)

#define PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1_MASK (0x3F00U)
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1_SHIFT (8U)
/*! MUXADDR1 - MUXADDR1 */
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1_SHIFT)) & PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1_MASK)

#define PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2_MASK   (0xC000U)
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2_SHIFT  (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2_SHIFT)) & PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2_MASK)

#define PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2_MASK (0x3F0000U)
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2_SHIFT (16U)
/*! MUXADDR2 - MUXADDR2 */
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2_SHIFT)) & PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2_MASK)

#define PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1_MASK   (0xC00000U)
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1_SHIFT  (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1_SHIFT)) & PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1_MASK)

#define PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3_MASK (0x3F000000U)
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3_SHIFT (24U)
/*! MUXADDR3 - MUXADDR3 */
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3_SHIFT)) & PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3_MASK)

#define PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0_MASK   (0xC0000000U)
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0_SHIFT  (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0_SHIFT)) & PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X1_OUT0 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0_MASK     (0x1U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0_SHIFT    (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1_MASK     (0x2U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1_SHIFT    (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2_MASK     (0x4U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2_SHIFT    (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3_MASK     (0x8U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3_SHIFT    (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4_MASK     (0x10U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4_SHIFT    (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5_MASK     (0x20U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5_SHIFT    (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6_MASK     (0x40U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6_SHIFT    (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7_MASK     (0x80U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7_SHIFT    (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8_MASK     (0x100U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8_SHIFT    (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9_MASK     (0x200U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9_SHIFT    (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10_MASK    (0x400U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10_SHIFT   (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11_MASK    (0x800U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11_SHIFT   (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12_MASK    (0x1000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12_SHIFT   (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13_MASK    (0x2000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13_SHIFT   (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14_MASK    (0x4000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14_SHIFT   (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15_MASK    (0x8000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15_SHIFT   (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16_MASK    (0x10000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16_SHIFT   (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17_MASK    (0x20000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17_SHIFT   (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18_MASK    (0x40000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18_SHIFT   (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19_MASK    (0x80000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19_SHIFT   (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20_MASK    (0x100000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20_SHIFT   (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21_MASK    (0x200000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21_SHIFT   (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22_MASK    (0x400000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22_SHIFT   (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23_MASK    (0x800000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23_SHIFT   (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24_MASK    (0x1000000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24_SHIFT   (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25_MASK    (0x2000000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25_SHIFT   (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26_MASK    (0x4000000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26_SHIFT   (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27_MASK    (0x8000000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27_SHIFT   (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28_MASK    (0x10000000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28_SHIFT   (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29_MASK    (0x20000000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29_SHIFT   (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30_MASK    (0x40000000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30_SHIFT   (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30_MASK)

#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31_MASK    (0x80000000U)
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31_SHIFT   (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X1_OUT1 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0_MASK     (0x1U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0_SHIFT    (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1_MASK     (0x2U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1_SHIFT    (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2_MASK     (0x4U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2_SHIFT    (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3_MASK     (0x8U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3_SHIFT    (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4_MASK     (0x10U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4_SHIFT    (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5_MASK     (0x20U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5_SHIFT    (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6_MASK     (0x40U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6_SHIFT    (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7_MASK     (0x80U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7_SHIFT    (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8_MASK     (0x100U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8_SHIFT    (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9_MASK     (0x200U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9_SHIFT    (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10_MASK    (0x400U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10_SHIFT   (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11_MASK    (0x800U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11_SHIFT   (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12_MASK    (0x1000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12_SHIFT   (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13_MASK    (0x2000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13_SHIFT   (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14_MASK    (0x4000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14_SHIFT   (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15_MASK    (0x8000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15_SHIFT   (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16_MASK    (0x10000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16_SHIFT   (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17_MASK    (0x20000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17_SHIFT   (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18_MASK    (0x40000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18_SHIFT   (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19_MASK    (0x80000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19_SHIFT   (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20_MASK    (0x100000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20_SHIFT   (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21_MASK    (0x200000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21_SHIFT   (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22_MASK    (0x400000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22_SHIFT   (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23_MASK    (0x800000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23_SHIFT   (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24_MASK    (0x1000000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24_SHIFT   (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25_MASK    (0x2000000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25_SHIFT   (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26_MASK    (0x4000000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26_SHIFT   (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27_MASK    (0x8000000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27_SHIFT   (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28_MASK    (0x10000000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28_SHIFT   (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29_MASK    (0x20000000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29_SHIFT   (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30_MASK    (0x40000000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30_SHIFT   (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30_MASK)

#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31_MASK    (0x80000000U)
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31_SHIFT   (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X1_OUT2 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0_MASK     (0x1U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0_SHIFT    (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1_MASK     (0x2U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1_SHIFT    (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2_MASK     (0x4U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2_SHIFT    (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3_MASK     (0x8U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3_SHIFT    (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4_MASK     (0x10U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4_SHIFT    (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5_MASK     (0x20U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5_SHIFT    (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6_MASK     (0x40U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6_SHIFT    (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7_MASK     (0x80U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7_SHIFT    (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8_MASK     (0x100U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8_SHIFT    (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9_MASK     (0x200U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9_SHIFT    (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10_MASK    (0x400U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10_SHIFT   (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11_MASK    (0x800U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11_SHIFT   (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12_MASK    (0x1000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12_SHIFT   (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13_MASK    (0x2000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13_SHIFT   (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14_MASK    (0x4000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14_SHIFT   (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15_MASK    (0x8000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15_SHIFT   (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16_MASK    (0x10000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16_SHIFT   (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17_MASK    (0x20000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17_SHIFT   (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18_MASK    (0x40000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18_SHIFT   (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19_MASK    (0x80000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19_SHIFT   (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20_MASK    (0x100000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20_SHIFT   (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21_MASK    (0x200000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21_SHIFT   (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22_MASK    (0x400000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22_SHIFT   (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23_MASK    (0x800000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23_SHIFT   (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24_MASK    (0x1000000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24_SHIFT   (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25_MASK    (0x2000000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25_SHIFT   (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26_MASK    (0x4000000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26_SHIFT   (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27_MASK    (0x8000000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27_SHIFT   (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28_MASK    (0x10000000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28_SHIFT   (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29_MASK    (0x20000000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29_SHIFT   (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30_MASK    (0x40000000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30_SHIFT   (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30_MASK)

#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31_MASK    (0x80000000U)
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31_SHIFT   (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X1_OUT3 -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0_MASK     (0x1U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0_SHIFT    (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1_MASK     (0x2U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1_SHIFT    (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2_MASK     (0x4U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2_SHIFT    (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3_MASK     (0x8U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3_SHIFT    (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4_MASK     (0x10U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4_SHIFT    (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5_MASK     (0x20U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5_SHIFT    (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6_MASK     (0x40U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6_SHIFT    (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7_MASK     (0x80U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7_SHIFT    (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8_MASK     (0x100U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8_SHIFT    (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9_MASK     (0x200U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9_SHIFT    (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10_MASK    (0x400U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10_SHIFT   (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11_MASK    (0x800U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11_SHIFT   (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12_MASK    (0x1000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12_SHIFT   (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13_MASK    (0x2000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13_SHIFT   (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14_MASK    (0x4000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14_SHIFT   (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15_MASK    (0x8000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15_SHIFT   (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16_MASK    (0x10000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16_SHIFT   (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17_MASK    (0x20000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17_SHIFT   (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18_MASK    (0x40000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18_SHIFT   (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19_MASK    (0x80000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19_SHIFT   (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20_MASK    (0x100000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20_SHIFT   (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21_MASK    (0x200000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21_SHIFT   (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22_MASK    (0x400000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22_SHIFT   (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23_MASK    (0x800000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23_SHIFT   (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24_MASK    (0x1000000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24_SHIFT   (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25_MASK    (0x2000000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25_SHIFT   (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26_MASK    (0x4000000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26_SHIFT   (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27_MASK    (0x8000000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27_SHIFT   (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28_MASK    (0x10000000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28_SHIFT   (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29_MASK    (0x20000000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29_SHIFT   (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30_MASK    (0x40000000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30_SHIFT   (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30_MASK)

#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31_MASK    (0x80000000U)
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31_SHIFT   (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31_SHIFT)) & PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_A_STG2_5X1_MASKS -  */
/*! @{ */

#define PXP_WFE_A_STG2_5X1_MASKS_MASK0_MASK      (0x1FU)
#define PXP_WFE_A_STG2_5X1_MASKS_MASK0_SHIFT     (0U)
/*! MASK0 - MASK0 */
#define PXP_WFE_A_STG2_5X1_MASKS_MASK0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_MASKS_MASK0_SHIFT)) & PXP_WFE_A_STG2_5X1_MASKS_MASK0_MASK)

#define PXP_WFE_A_STG2_5X1_MASKS_RSVD0_MASK      (0xE0U)
#define PXP_WFE_A_STG2_5X1_MASKS_RSVD0_SHIFT     (5U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_A_STG2_5X1_MASKS_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_MASKS_RSVD0_SHIFT)) & PXP_WFE_A_STG2_5X1_MASKS_RSVD0_MASK)

#define PXP_WFE_A_STG2_5X1_MASKS_MASK1_MASK      (0x1F00U)
#define PXP_WFE_A_STG2_5X1_MASKS_MASK1_SHIFT     (8U)
/*! MASK1 - MASK1 */
#define PXP_WFE_A_STG2_5X1_MASKS_MASK1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_MASKS_MASK1_SHIFT)) & PXP_WFE_A_STG2_5X1_MASKS_MASK1_MASK)

#define PXP_WFE_A_STG2_5X1_MASKS_RSVD1_MASK      (0xE000U)
#define PXP_WFE_A_STG2_5X1_MASKS_RSVD1_SHIFT     (13U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_A_STG2_5X1_MASKS_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_MASKS_RSVD1_SHIFT)) & PXP_WFE_A_STG2_5X1_MASKS_RSVD1_MASK)

#define PXP_WFE_A_STG2_5X1_MASKS_MASK2_MASK      (0x1F0000U)
#define PXP_WFE_A_STG2_5X1_MASKS_MASK2_SHIFT     (16U)
/*! MASK2 - MASK2 */
#define PXP_WFE_A_STG2_5X1_MASKS_MASK2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_MASKS_MASK2_SHIFT)) & PXP_WFE_A_STG2_5X1_MASKS_MASK2_MASK)

#define PXP_WFE_A_STG2_5X1_MASKS_RSVD2_MASK      (0xE00000U)
#define PXP_WFE_A_STG2_5X1_MASKS_RSVD2_SHIFT     (21U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_A_STG2_5X1_MASKS_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_MASKS_RSVD2_SHIFT)) & PXP_WFE_A_STG2_5X1_MASKS_RSVD2_MASK)

#define PXP_WFE_A_STG2_5X1_MASKS_MASK3_MASK      (0x1F000000U)
#define PXP_WFE_A_STG2_5X1_MASKS_MASK3_SHIFT     (24U)
/*! MASK3 - MASK3 */
#define PXP_WFE_A_STG2_5X1_MASKS_MASK3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_MASKS_MASK3_SHIFT)) & PXP_WFE_A_STG2_5X1_MASKS_MASK3_MASK)

#define PXP_WFE_A_STG2_5X1_MASKS_RSVD3_MASK      (0xE0000000U)
#define PXP_WFE_A_STG2_5X1_MASKS_RSVD3_SHIFT     (29U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_A_STG2_5X1_MASKS_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_A_STG2_5X1_MASKS_RSVD3_SHIFT)) & PXP_WFE_A_STG2_5X1_MASKS_RSVD3_MASK)
/*! @} */

/*! @name WFE_B_CTRL -  */
/*! @{ */

#define PXP_WFE_B_CTRL_ENABLE_MASK               (0x1U)
#define PXP_WFE_B_CTRL_ENABLE_SHIFT              (0U)
/*! ENABLE - ENABLE
 *  0b0..Disabled, the WFE B sub-block will not process any frames
 *  0b1..The WFE B sub-block is on and ready for processing.
 */
#define PXP_WFE_B_CTRL_ENABLE(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_ENABLE_MASK)

#define PXP_WFE_B_CTRL_RSVD1_MASK                (0x2U)
#define PXP_WFE_B_CTRL_RSVD1_SHIFT               (1U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_CTRL_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_RSVD1_SHIFT)) & PXP_WFE_B_CTRL_RSVD1_MASK)

#define PXP_WFE_B_CTRL_SW_RESET_MASK             (0x4U)
#define PXP_WFE_B_CTRL_SW_RESET_SHIFT            (2U)
/*! SW_RESET - SW_RESET */
#define PXP_WFE_B_CTRL_SW_RESET(x)               (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_SW_RESET_MASK)

#define PXP_WFE_B_CTRL_ALU_REGISTER_ENABLE_MASK  (0x8U)
#define PXP_WFE_B_CTRL_ALU_REGISTER_ENABLE_SHIFT (3U)
/*! ALU_REGISTER_ENABLE - ALU_REGISTER_ENABLE
 *  0b0..Disabled, the WFE will use the output of alu inside directly.
 *  0b1..Enable, the WFE will use the register output of alu inside.
 */
#define PXP_WFE_B_CTRL_ALU_REGISTER_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_ALU_REGISTER_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_ALU_REGISTER_ENABLE_MASK)

#define PXP_WFE_B_CTRL_RSVD0_MASK                (0x7FFFFFF0U)
#define PXP_WFE_B_CTRL_RSVD0_SHIFT               (4U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_CTRL_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_RSVD0_SHIFT)) & PXP_WFE_B_CTRL_RSVD0_MASK)

#define PXP_WFE_B_CTRL_DONE_MASK                 (0x80000000U)
#define PXP_WFE_B_CTRL_DONE_SHIFT                (31U)
/*! DONE - DONE */
#define PXP_WFE_B_CTRL_DONE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_DONE_SHIFT)) & PXP_WFE_B_CTRL_DONE_MASK)
/*! @} */

/*! @name WFE_B_CTRL_SET -  */
/*! @{ */

#define PXP_WFE_B_CTRL_SET_ENABLE_MASK           (0x1U)
#define PXP_WFE_B_CTRL_SET_ENABLE_SHIFT          (0U)
/*! ENABLE - ENABLE */
#define PXP_WFE_B_CTRL_SET_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_SET_ENABLE_MASK)

#define PXP_WFE_B_CTRL_SET_RSVD1_MASK            (0x2U)
#define PXP_WFE_B_CTRL_SET_RSVD1_SHIFT           (1U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_CTRL_SET_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_RSVD1_SHIFT)) & PXP_WFE_B_CTRL_SET_RSVD1_MASK)

#define PXP_WFE_B_CTRL_SET_SW_RESET_MASK         (0x4U)
#define PXP_WFE_B_CTRL_SET_SW_RESET_SHIFT        (2U)
/*! SW_RESET - SW_RESET */
#define PXP_WFE_B_CTRL_SET_SW_RESET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_SET_SW_RESET_MASK)

#define PXP_WFE_B_CTRL_SET_ALU_REGISTER_ENABLE_MASK (0x8U)
#define PXP_WFE_B_CTRL_SET_ALU_REGISTER_ENABLE_SHIFT (3U)
/*! ALU_REGISTER_ENABLE - ALU_REGISTER_ENABLE */
#define PXP_WFE_B_CTRL_SET_ALU_REGISTER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_ALU_REGISTER_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_SET_ALU_REGISTER_ENABLE_MASK)

#define PXP_WFE_B_CTRL_SET_RSVD0_MASK            (0x7FFFFFF0U)
#define PXP_WFE_B_CTRL_SET_RSVD0_SHIFT           (4U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_CTRL_SET_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_RSVD0_SHIFT)) & PXP_WFE_B_CTRL_SET_RSVD0_MASK)

#define PXP_WFE_B_CTRL_SET_DONE_MASK             (0x80000000U)
#define PXP_WFE_B_CTRL_SET_DONE_SHIFT            (31U)
/*! DONE - DONE */
#define PXP_WFE_B_CTRL_SET_DONE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_DONE_SHIFT)) & PXP_WFE_B_CTRL_SET_DONE_MASK)
/*! @} */

/*! @name WFE_B_CTRL_CLR -  */
/*! @{ */

#define PXP_WFE_B_CTRL_CLR_ENABLE_MASK           (0x1U)
#define PXP_WFE_B_CTRL_CLR_ENABLE_SHIFT          (0U)
/*! ENABLE - ENABLE */
#define PXP_WFE_B_CTRL_CLR_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_CLR_ENABLE_MASK)

#define PXP_WFE_B_CTRL_CLR_RSVD1_MASK            (0x2U)
#define PXP_WFE_B_CTRL_CLR_RSVD1_SHIFT           (1U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_CTRL_CLR_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_RSVD1_SHIFT)) & PXP_WFE_B_CTRL_CLR_RSVD1_MASK)

#define PXP_WFE_B_CTRL_CLR_SW_RESET_MASK         (0x4U)
#define PXP_WFE_B_CTRL_CLR_SW_RESET_SHIFT        (2U)
/*! SW_RESET - SW_RESET */
#define PXP_WFE_B_CTRL_CLR_SW_RESET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_CLR_SW_RESET_MASK)

#define PXP_WFE_B_CTRL_CLR_ALU_REGISTER_ENABLE_MASK (0x8U)
#define PXP_WFE_B_CTRL_CLR_ALU_REGISTER_ENABLE_SHIFT (3U)
/*! ALU_REGISTER_ENABLE - ALU_REGISTER_ENABLE */
#define PXP_WFE_B_CTRL_CLR_ALU_REGISTER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_ALU_REGISTER_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_CLR_ALU_REGISTER_ENABLE_MASK)

#define PXP_WFE_B_CTRL_CLR_RSVD0_MASK            (0x7FFFFFF0U)
#define PXP_WFE_B_CTRL_CLR_RSVD0_SHIFT           (4U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_CTRL_CLR_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_RSVD0_SHIFT)) & PXP_WFE_B_CTRL_CLR_RSVD0_MASK)

#define PXP_WFE_B_CTRL_CLR_DONE_MASK             (0x80000000U)
#define PXP_WFE_B_CTRL_CLR_DONE_SHIFT            (31U)
/*! DONE - DONE */
#define PXP_WFE_B_CTRL_CLR_DONE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_DONE_SHIFT)) & PXP_WFE_B_CTRL_CLR_DONE_MASK)
/*! @} */

/*! @name WFE_B_CTRL_TOG -  */
/*! @{ */

#define PXP_WFE_B_CTRL_TOG_ENABLE_MASK           (0x1U)
#define PXP_WFE_B_CTRL_TOG_ENABLE_SHIFT          (0U)
/*! ENABLE - ENABLE */
#define PXP_WFE_B_CTRL_TOG_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_TOG_ENABLE_MASK)

#define PXP_WFE_B_CTRL_TOG_RSVD1_MASK            (0x2U)
#define PXP_WFE_B_CTRL_TOG_RSVD1_SHIFT           (1U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_CTRL_TOG_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_RSVD1_SHIFT)) & PXP_WFE_B_CTRL_TOG_RSVD1_MASK)

#define PXP_WFE_B_CTRL_TOG_SW_RESET_MASK         (0x4U)
#define PXP_WFE_B_CTRL_TOG_SW_RESET_SHIFT        (2U)
/*! SW_RESET - SW_RESET */
#define PXP_WFE_B_CTRL_TOG_SW_RESET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_TOG_SW_RESET_MASK)

#define PXP_WFE_B_CTRL_TOG_ALU_REGISTER_ENABLE_MASK (0x8U)
#define PXP_WFE_B_CTRL_TOG_ALU_REGISTER_ENABLE_SHIFT (3U)
/*! ALU_REGISTER_ENABLE - ALU_REGISTER_ENABLE */
#define PXP_WFE_B_CTRL_TOG_ALU_REGISTER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_ALU_REGISTER_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_TOG_ALU_REGISTER_ENABLE_MASK)

#define PXP_WFE_B_CTRL_TOG_RSVD0_MASK            (0x7FFFFFF0U)
#define PXP_WFE_B_CTRL_TOG_RSVD0_SHIFT           (4U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_CTRL_TOG_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_RSVD0_SHIFT)) & PXP_WFE_B_CTRL_TOG_RSVD0_MASK)

#define PXP_WFE_B_CTRL_TOG_DONE_MASK             (0x80000000U)
#define PXP_WFE_B_CTRL_TOG_DONE_SHIFT            (31U)
/*! DONE - DONE */
#define PXP_WFE_B_CTRL_TOG_DONE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_DONE_SHIFT)) & PXP_WFE_B_CTRL_TOG_DONE_MASK)
/*! @} */

/*! @name WFE_B_DIMENSIONS -  */
/*! @{ */

#define PXP_WFE_B_DIMENSIONS_WIDTH_MASK          (0x1FFFU)
#define PXP_WFE_B_DIMENSIONS_WIDTH_SHIFT         (0U)
/*! WIDTH - WIDTH */
#define PXP_WFE_B_DIMENSIONS_WIDTH(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_DIMENSIONS_WIDTH_SHIFT)) & PXP_WFE_B_DIMENSIONS_WIDTH_MASK)

#define PXP_WFE_B_DIMENSIONS_RSVD1_MASK          (0xE000U)
#define PXP_WFE_B_DIMENSIONS_RSVD1_SHIFT         (13U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_DIMENSIONS_RSVD1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_DIMENSIONS_RSVD1_SHIFT)) & PXP_WFE_B_DIMENSIONS_RSVD1_MASK)

#define PXP_WFE_B_DIMENSIONS_HEIGHT_MASK         (0x1FFF0000U)
#define PXP_WFE_B_DIMENSIONS_HEIGHT_SHIFT        (16U)
/*! HEIGHT - HEIGHT */
#define PXP_WFE_B_DIMENSIONS_HEIGHT(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_DIMENSIONS_HEIGHT_SHIFT)) & PXP_WFE_B_DIMENSIONS_HEIGHT_MASK)

#define PXP_WFE_B_DIMENSIONS_RSVD0_MASK          (0xE0000000U)
#define PXP_WFE_B_DIMENSIONS_RSVD0_SHIFT         (29U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_DIMENSIONS_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_DIMENSIONS_RSVD0_SHIFT)) & PXP_WFE_B_DIMENSIONS_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_OFFSET -  */
/*! @{ */

#define PXP_WFE_B_OFFSET_X_OFFSET_MASK           (0x1FFFU)
#define PXP_WFE_B_OFFSET_X_OFFSET_SHIFT          (0U)
/*! X_OFFSET - X_OFFSET */
#define PXP_WFE_B_OFFSET_X_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_OFFSET_X_OFFSET_SHIFT)) & PXP_WFE_B_OFFSET_X_OFFSET_MASK)

#define PXP_WFE_B_OFFSET_RSVD1_MASK              (0xE000U)
#define PXP_WFE_B_OFFSET_RSVD1_SHIFT             (13U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_OFFSET_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_OFFSET_RSVD1_SHIFT)) & PXP_WFE_B_OFFSET_RSVD1_MASK)

#define PXP_WFE_B_OFFSET_Y_OFFSET_MASK           (0x1FFF0000U)
#define PXP_WFE_B_OFFSET_Y_OFFSET_SHIFT          (16U)
/*! Y_OFFSET - Y_OFFSET */
#define PXP_WFE_B_OFFSET_Y_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_OFFSET_Y_OFFSET_SHIFT)) & PXP_WFE_B_OFFSET_Y_OFFSET_MASK)

#define PXP_WFE_B_OFFSET_RSVD0_MASK              (0xE0000000U)
#define PXP_WFE_B_OFFSET_RSVD0_SHIFT             (29U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_OFFSET_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_OFFSET_RSVD0_SHIFT)) & PXP_WFE_B_OFFSET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_SW_DATA_REGS -  */
/*! @{ */

#define PXP_WFE_B_SW_DATA_REGS_VAL0_MASK         (0xFFU)
#define PXP_WFE_B_SW_DATA_REGS_VAL0_SHIFT        (0U)
/*! VAL0 - VAL0 */
#define PXP_WFE_B_SW_DATA_REGS_VAL0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL0_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL0_MASK)

#define PXP_WFE_B_SW_DATA_REGS_VAL1_MASK         (0xFF00U)
#define PXP_WFE_B_SW_DATA_REGS_VAL1_SHIFT        (8U)
/*! VAL1 - VAL1 */
#define PXP_WFE_B_SW_DATA_REGS_VAL1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL1_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL1_MASK)

#define PXP_WFE_B_SW_DATA_REGS_VAL2_MASK         (0xFF0000U)
#define PXP_WFE_B_SW_DATA_REGS_VAL2_SHIFT        (16U)
/*! VAL2 - VAL2 */
#define PXP_WFE_B_SW_DATA_REGS_VAL2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL2_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL2_MASK)

#define PXP_WFE_B_SW_DATA_REGS_VAL3_MASK         (0xFF000000U)
#define PXP_WFE_B_SW_DATA_REGS_VAL3_SHIFT        (24U)
/*! VAL3 - VAL3 */
#define PXP_WFE_B_SW_DATA_REGS_VAL3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL3_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL3_MASK)
/*! @} */

/*! @name WFE_B_SW_FLAG_REGS -  */
/*! @{ */

#define PXP_WFE_B_SW_FLAG_REGS_VAL0_MASK         (0x1U)
#define PXP_WFE_B_SW_FLAG_REGS_VAL0_SHIFT        (0U)
/*! VAL0 - VAL0 */
#define PXP_WFE_B_SW_FLAG_REGS_VAL0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL0_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL0_MASK)

#define PXP_WFE_B_SW_FLAG_REGS_VAL1_MASK         (0x2U)
#define PXP_WFE_B_SW_FLAG_REGS_VAL1_SHIFT        (1U)
/*! VAL1 - VAL1 */
#define PXP_WFE_B_SW_FLAG_REGS_VAL1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL1_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL1_MASK)

#define PXP_WFE_B_SW_FLAG_REGS_VAL2_MASK         (0x4U)
#define PXP_WFE_B_SW_FLAG_REGS_VAL2_SHIFT        (2U)
/*! VAL2 - VAL2 */
#define PXP_WFE_B_SW_FLAG_REGS_VAL2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL2_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL2_MASK)

#define PXP_WFE_B_SW_FLAG_REGS_VAL3_MASK         (0x8U)
#define PXP_WFE_B_SW_FLAG_REGS_VAL3_SHIFT        (3U)
/*! VAL3 - VAL3 */
#define PXP_WFE_B_SW_FLAG_REGS_VAL3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL3_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL3_MASK)

#define PXP_WFE_B_SW_FLAG_REGS_RSVD_MASK         (0xFFFFFFF0U)
#define PXP_WFE_B_SW_FLAG_REGS_RSVD_SHIFT        (4U)
/*! RSVD - RSVD */
#define PXP_WFE_B_SW_FLAG_REGS_RSVD(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_RSVD_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_RSVD_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX0 -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX0_MUX0_MASK          (0x3FU)
#define PXP_WFE_B_STAGE1_MUX0_MUX0_SHIFT         (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_B_STAGE1_MUX0_MUX0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX0_MASK)

#define PXP_WFE_B_STAGE1_MUX0_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE1_MUX0_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX0_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX0_MUX1_MASK          (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX0_MUX1_SHIFT         (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_B_STAGE1_MUX0_MUX1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX1_MASK)

#define PXP_WFE_B_STAGE1_MUX0_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE1_MUX0_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX0_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX0_MUX2_MASK          (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX0_MUX2_SHIFT         (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_B_STAGE1_MUX0_MUX2(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX2_MASK)

#define PXP_WFE_B_STAGE1_MUX0_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX0_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX0_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX0_MUX3_MASK          (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX0_MUX3_SHIFT         (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_B_STAGE1_MUX0_MUX3(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX3_MASK)

#define PXP_WFE_B_STAGE1_MUX0_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX0_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX0_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX0_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0_MASK      (0x3FU)
#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX0_MASK)

#define PXP_WFE_B_STAGE1_MUX0_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX0_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX0_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX1_MASK)

#define PXP_WFE_B_STAGE1_MUX0_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX0_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX0_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX2_MASK)

#define PXP_WFE_B_STAGE1_MUX0_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX0_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX0_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX3_MASK)

#define PXP_WFE_B_STAGE1_MUX0_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX0_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX0_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX0_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_MASK      (0x3FU)
#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_MASK)

#define PXP_WFE_B_STAGE1_MUX0_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX0_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX0_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_MASK)

#define PXP_WFE_B_STAGE1_MUX0_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX0_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX0_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_MASK)

#define PXP_WFE_B_STAGE1_MUX0_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX0_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX0_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_MASK)

#define PXP_WFE_B_STAGE1_MUX0_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX0_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX0_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX0_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_MASK      (0x3FU)
#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_MASK)

#define PXP_WFE_B_STAGE1_MUX0_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX0_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX0_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_MASK)

#define PXP_WFE_B_STAGE1_MUX0_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX0_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX0_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_MASK)

#define PXP_WFE_B_STAGE1_MUX0_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX0_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX0_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_MASK)

#define PXP_WFE_B_STAGE1_MUX0_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX0_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX0_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX1 -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX1_MUX4_MASK          (0x3FU)
#define PXP_WFE_B_STAGE1_MUX1_MUX4_SHIFT         (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_B_STAGE1_MUX1_MUX4(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX4_MASK)

#define PXP_WFE_B_STAGE1_MUX1_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE1_MUX1_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX1_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX1_MUX5_MASK          (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX1_MUX5_SHIFT         (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_B_STAGE1_MUX1_MUX5(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX5_MASK)

#define PXP_WFE_B_STAGE1_MUX1_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE1_MUX1_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX1_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX1_MUX6_MASK          (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX1_MUX6_SHIFT         (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_B_STAGE1_MUX1_MUX6(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX6_MASK)

#define PXP_WFE_B_STAGE1_MUX1_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX1_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX1_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX1_MUX7_MASK          (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX1_MUX7_SHIFT         (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_B_STAGE1_MUX1_MUX7(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX7_MASK)

#define PXP_WFE_B_STAGE1_MUX1_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX1_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX1_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX1_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4_MASK      (0x3FU)
#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX4_MASK)

#define PXP_WFE_B_STAGE1_MUX1_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX1_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX1_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX5_MASK)

#define PXP_WFE_B_STAGE1_MUX1_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX1_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX1_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX6_MASK)

#define PXP_WFE_B_STAGE1_MUX1_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX1_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX1_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX7_MASK)

#define PXP_WFE_B_STAGE1_MUX1_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX1_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX1_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX1_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_MASK      (0x3FU)
#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_MASK)

#define PXP_WFE_B_STAGE1_MUX1_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX1_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX1_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_MASK)

#define PXP_WFE_B_STAGE1_MUX1_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX1_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX1_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_MASK)

#define PXP_WFE_B_STAGE1_MUX1_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX1_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX1_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_MASK)

#define PXP_WFE_B_STAGE1_MUX1_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX1_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX1_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX1_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_MASK      (0x3FU)
#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_MASK)

#define PXP_WFE_B_STAGE1_MUX1_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX1_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX1_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_MASK)

#define PXP_WFE_B_STAGE1_MUX1_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX1_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX1_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_MASK)

#define PXP_WFE_B_STAGE1_MUX1_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX1_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX1_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_MASK)

#define PXP_WFE_B_STAGE1_MUX1_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX1_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX1_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX2 -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX2_MUX8_MASK          (0x3FU)
#define PXP_WFE_B_STAGE1_MUX2_MUX8_SHIFT         (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_B_STAGE1_MUX2_MUX8(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX8_MASK)

#define PXP_WFE_B_STAGE1_MUX2_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE1_MUX2_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX2_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX2_MUX9_MASK          (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX2_MUX9_SHIFT         (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_B_STAGE1_MUX2_MUX9(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX9_MASK)

#define PXP_WFE_B_STAGE1_MUX2_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE1_MUX2_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX2_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX2_MUX10_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX2_MUX10_SHIFT        (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_B_STAGE1_MUX2_MUX10(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX10_MASK)

#define PXP_WFE_B_STAGE1_MUX2_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX2_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX2_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX2_MUX11_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX2_MUX11_SHIFT        (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_B_STAGE1_MUX2_MUX11(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX11_MASK)

#define PXP_WFE_B_STAGE1_MUX2_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX2_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX2_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX2_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8_MASK      (0x3FU)
#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX8_MASK)

#define PXP_WFE_B_STAGE1_MUX2_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX2_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX2_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX9_MASK)

#define PXP_WFE_B_STAGE1_MUX2_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX2_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX2_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX10_MASK)

#define PXP_WFE_B_STAGE1_MUX2_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX2_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX2_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX11_MASK)

#define PXP_WFE_B_STAGE1_MUX2_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX2_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX2_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX2_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_MASK      (0x3FU)
#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_MASK)

#define PXP_WFE_B_STAGE1_MUX2_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX2_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX2_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_MASK)

#define PXP_WFE_B_STAGE1_MUX2_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX2_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX2_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_MASK)

#define PXP_WFE_B_STAGE1_MUX2_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX2_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX2_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_MASK)

#define PXP_WFE_B_STAGE1_MUX2_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX2_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX2_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX2_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_MASK      (0x3FU)
#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_MASK)

#define PXP_WFE_B_STAGE1_MUX2_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX2_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX2_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_MASK)

#define PXP_WFE_B_STAGE1_MUX2_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX2_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX2_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_MASK)

#define PXP_WFE_B_STAGE1_MUX2_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX2_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX2_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_MASK)

#define PXP_WFE_B_STAGE1_MUX2_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX2_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX2_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX3 -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX3_MUX12_MASK         (0x3FU)
#define PXP_WFE_B_STAGE1_MUX3_MUX12_SHIFT        (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_B_STAGE1_MUX3_MUX12(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX12_MASK)

#define PXP_WFE_B_STAGE1_MUX3_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE1_MUX3_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX3_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX3_MUX13_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX3_MUX13_SHIFT        (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_B_STAGE1_MUX3_MUX13(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX13_MASK)

#define PXP_WFE_B_STAGE1_MUX3_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE1_MUX3_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX3_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX3_MUX14_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX3_MUX14_SHIFT        (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_B_STAGE1_MUX3_MUX14(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX14_MASK)

#define PXP_WFE_B_STAGE1_MUX3_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX3_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX3_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX3_MUX15_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX3_MUX15_SHIFT        (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_B_STAGE1_MUX3_MUX15(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX15_MASK)

#define PXP_WFE_B_STAGE1_MUX3_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX3_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX3_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX3_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX12_MASK)

#define PXP_WFE_B_STAGE1_MUX3_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX3_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX3_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX13_MASK)

#define PXP_WFE_B_STAGE1_MUX3_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX3_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX3_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX14_MASK)

#define PXP_WFE_B_STAGE1_MUX3_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX3_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX3_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX15_MASK)

#define PXP_WFE_B_STAGE1_MUX3_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX3_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX3_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX3_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_MASK)

#define PXP_WFE_B_STAGE1_MUX3_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX3_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX3_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_MASK)

#define PXP_WFE_B_STAGE1_MUX3_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX3_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX3_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_MASK)

#define PXP_WFE_B_STAGE1_MUX3_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX3_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX3_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_MASK)

#define PXP_WFE_B_STAGE1_MUX3_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX3_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX3_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX3_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_MASK)

#define PXP_WFE_B_STAGE1_MUX3_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX3_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX3_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_MASK)

#define PXP_WFE_B_STAGE1_MUX3_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX3_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX3_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_MASK)

#define PXP_WFE_B_STAGE1_MUX3_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX3_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX3_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_MASK)

#define PXP_WFE_B_STAGE1_MUX3_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX3_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX3_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX4 -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX4_MUX16_MASK         (0x3FU)
#define PXP_WFE_B_STAGE1_MUX4_MUX16_SHIFT        (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_B_STAGE1_MUX4_MUX16(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX16_MASK)

#define PXP_WFE_B_STAGE1_MUX4_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE1_MUX4_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX4_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX4_MUX17_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX4_MUX17_SHIFT        (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_B_STAGE1_MUX4_MUX17(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX17_MASK)

#define PXP_WFE_B_STAGE1_MUX4_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE1_MUX4_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX4_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX4_MUX18_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX4_MUX18_SHIFT        (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_B_STAGE1_MUX4_MUX18(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX18_MASK)

#define PXP_WFE_B_STAGE1_MUX4_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX4_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX4_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX4_MUX19_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX4_MUX19_SHIFT        (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_B_STAGE1_MUX4_MUX19(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX19_MASK)

#define PXP_WFE_B_STAGE1_MUX4_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX4_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX4_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX4_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX16_MASK)

#define PXP_WFE_B_STAGE1_MUX4_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX4_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX4_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX17_MASK)

#define PXP_WFE_B_STAGE1_MUX4_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX4_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX4_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18_SHIFT    (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX18_MASK)

#define PXP_WFE_B_STAGE1_MUX4_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX4_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX4_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19_SHIFT    (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX19_MASK)

#define PXP_WFE_B_STAGE1_MUX4_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX4_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX4_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX4_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_MASK)

#define PXP_WFE_B_STAGE1_MUX4_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX4_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX4_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_MASK)

#define PXP_WFE_B_STAGE1_MUX4_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX4_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX4_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_SHIFT    (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_MASK)

#define PXP_WFE_B_STAGE1_MUX4_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX4_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX4_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_SHIFT    (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_MASK)

#define PXP_WFE_B_STAGE1_MUX4_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX4_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX4_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX4_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_MASK)

#define PXP_WFE_B_STAGE1_MUX4_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX4_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX4_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_MASK)

#define PXP_WFE_B_STAGE1_MUX4_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX4_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX4_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_SHIFT    (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_MASK)

#define PXP_WFE_B_STAGE1_MUX4_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX4_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX4_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_SHIFT    (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_MASK)

#define PXP_WFE_B_STAGE1_MUX4_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX4_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX4_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX5 -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX5_MUX20_MASK         (0x3FU)
#define PXP_WFE_B_STAGE1_MUX5_MUX20_SHIFT        (0U)
/*! MUX20 - MUX20
 *  0b000000..INC : Increment operation.
 *  0b000001..DEC : Decrement operation.
 *  0b000010..ADD : Addition operation.
 *  0b000011..MINUS : Subtraction operation.
 *  0b000100..AND : Bitwise AND operation. A AND B.
 *  0b000101..OR : Bitwise OR operation. A OR B.
 *  0b000110..XOR : Bitwise XOR operation. A XOR B.
 *  0b000111..SHIFTLEFT : Shift A operand left by B operand places.
 *  0b001000..SHIFTRIGHT : Shift A operand right by B operand places.
 *  0b001001..BIT_AND : Reduction AND operation on A operand.
 *  0b001010..BIT_OR : Reduction OR operation on A operand.
 *  0b001011..BIT_CMP : Compare A and B operands and set equal flag if A and B are equal. All other output is 0.
 *  0b001100..NOP : No operation. All outputs are 0.
 */
#define PXP_WFE_B_STAGE1_MUX5_MUX20(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX20_MASK)

#define PXP_WFE_B_STAGE1_MUX5_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE1_MUX5_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX5_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX5_MUX21_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX5_MUX21_SHIFT        (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_B_STAGE1_MUX5_MUX21(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX21_MASK)

#define PXP_WFE_B_STAGE1_MUX5_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE1_MUX5_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX5_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX5_MUX22_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX5_MUX22_SHIFT        (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_B_STAGE1_MUX5_MUX22(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX22_MASK)

#define PXP_WFE_B_STAGE1_MUX5_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX5_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX5_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX5_MUX23_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX5_MUX23_SHIFT        (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_B_STAGE1_MUX5_MUX23(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX23_MASK)

#define PXP_WFE_B_STAGE1_MUX5_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX5_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX5_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX5_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20_SHIFT    (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX20_MASK)

#define PXP_WFE_B_STAGE1_MUX5_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX5_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX5_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21_SHIFT    (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX21_MASK)

#define PXP_WFE_B_STAGE1_MUX5_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX5_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX5_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22_SHIFT    (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX22_MASK)

#define PXP_WFE_B_STAGE1_MUX5_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX5_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX5_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23_SHIFT    (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX23_MASK)

#define PXP_WFE_B_STAGE1_MUX5_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX5_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX5_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX5_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_SHIFT    (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_MASK)

#define PXP_WFE_B_STAGE1_MUX5_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX5_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX5_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_SHIFT    (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_MASK)

#define PXP_WFE_B_STAGE1_MUX5_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX5_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX5_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_SHIFT    (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_MASK)

#define PXP_WFE_B_STAGE1_MUX5_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX5_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX5_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_SHIFT    (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_MASK)

#define PXP_WFE_B_STAGE1_MUX5_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX5_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX5_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX5_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_SHIFT    (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_MASK)

#define PXP_WFE_B_STAGE1_MUX5_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX5_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX5_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_SHIFT    (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_MASK)

#define PXP_WFE_B_STAGE1_MUX5_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX5_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX5_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_SHIFT    (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_MASK)

#define PXP_WFE_B_STAGE1_MUX5_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX5_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX5_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_SHIFT    (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_MASK)

#define PXP_WFE_B_STAGE1_MUX5_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX5_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX5_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX6 -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX6_MUX24_MASK         (0x3FU)
#define PXP_WFE_B_STAGE1_MUX6_MUX24_SHIFT        (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_B_STAGE1_MUX6_MUX24(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX24_MASK)

#define PXP_WFE_B_STAGE1_MUX6_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE1_MUX6_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX6_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX6_MUX25_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX6_MUX25_SHIFT        (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_B_STAGE1_MUX6_MUX25(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX25_MASK)

#define PXP_WFE_B_STAGE1_MUX6_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE1_MUX6_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX6_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX6_MUX26_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX6_MUX26_SHIFT        (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_B_STAGE1_MUX6_MUX26(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX26_MASK)

#define PXP_WFE_B_STAGE1_MUX6_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX6_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX6_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX6_MUX27_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX6_MUX27_SHIFT        (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_B_STAGE1_MUX6_MUX27(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX27_MASK)

#define PXP_WFE_B_STAGE1_MUX6_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX6_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX6_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX6_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24_SHIFT    (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX24_MASK)

#define PXP_WFE_B_STAGE1_MUX6_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX6_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX6_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25_SHIFT    (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX25_MASK)

#define PXP_WFE_B_STAGE1_MUX6_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX6_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX6_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26_SHIFT    (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX26_MASK)

#define PXP_WFE_B_STAGE1_MUX6_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX6_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX6_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27_SHIFT    (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX27_MASK)

#define PXP_WFE_B_STAGE1_MUX6_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX6_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX6_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX6_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_SHIFT    (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_MASK)

#define PXP_WFE_B_STAGE1_MUX6_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX6_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX6_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_SHIFT    (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_MASK)

#define PXP_WFE_B_STAGE1_MUX6_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX6_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX6_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_SHIFT    (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_MASK)

#define PXP_WFE_B_STAGE1_MUX6_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX6_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX6_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_SHIFT    (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_MASK)

#define PXP_WFE_B_STAGE1_MUX6_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX6_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX6_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX6_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_SHIFT    (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_MASK)

#define PXP_WFE_B_STAGE1_MUX6_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX6_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX6_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_SHIFT    (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_MASK)

#define PXP_WFE_B_STAGE1_MUX6_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX6_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX6_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_SHIFT    (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_MASK)

#define PXP_WFE_B_STAGE1_MUX6_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX6_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX6_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_SHIFT    (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_MASK)

#define PXP_WFE_B_STAGE1_MUX6_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX6_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX6_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX7 -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX7_MUX28_MASK         (0x3FU)
#define PXP_WFE_B_STAGE1_MUX7_MUX28_SHIFT        (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_B_STAGE1_MUX7_MUX28(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX28_MASK)

#define PXP_WFE_B_STAGE1_MUX7_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE1_MUX7_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX7_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX7_MUX29_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX7_MUX29_SHIFT        (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_B_STAGE1_MUX7_MUX29(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX29_MASK)

#define PXP_WFE_B_STAGE1_MUX7_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE1_MUX7_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX7_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX7_MUX30_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX7_MUX30_SHIFT        (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_B_STAGE1_MUX7_MUX30(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX30_MASK)

#define PXP_WFE_B_STAGE1_MUX7_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX7_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX7_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX7_MUX31_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX7_MUX31_SHIFT        (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_B_STAGE1_MUX7_MUX31(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX31_MASK)

#define PXP_WFE_B_STAGE1_MUX7_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX7_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX7_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX7_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28_SHIFT    (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX28_MASK)

#define PXP_WFE_B_STAGE1_MUX7_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX7_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX7_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29_SHIFT    (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX29_MASK)

#define PXP_WFE_B_STAGE1_MUX7_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX7_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX7_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30_SHIFT    (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX30_MASK)

#define PXP_WFE_B_STAGE1_MUX7_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX7_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX7_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31_SHIFT    (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX31_MASK)

#define PXP_WFE_B_STAGE1_MUX7_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX7_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX7_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX7_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_SHIFT    (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_MASK)

#define PXP_WFE_B_STAGE1_MUX7_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX7_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX7_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_SHIFT    (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_MASK)

#define PXP_WFE_B_STAGE1_MUX7_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX7_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX7_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_SHIFT    (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_MASK)

#define PXP_WFE_B_STAGE1_MUX7_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX7_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX7_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_SHIFT    (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_MASK)

#define PXP_WFE_B_STAGE1_MUX7_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX7_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX7_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX7_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_SHIFT    (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_MASK)

#define PXP_WFE_B_STAGE1_MUX7_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE1_MUX7_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_MUX7_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_SHIFT    (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_MASK)

#define PXP_WFE_B_STAGE1_MUX7_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE1_MUX7_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_MUX7_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_SHIFT    (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_MASK)

#define PXP_WFE_B_STAGE1_MUX7_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE1_MUX7_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE1_MUX7_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_SHIFT    (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_MASK)

#define PXP_WFE_B_STAGE1_MUX7_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE1_MUX7_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX7_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX8 -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX8_MUX32_MASK         (0x3FU)
#define PXP_WFE_B_STAGE1_MUX8_MUX32_SHIFT        (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_B_STAGE1_MUX8_MUX32(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_MUX32_MASK)

#define PXP_WFE_B_STAGE1_MUX8_RSVD0_MASK         (0xFFFFFFC0U)
#define PXP_WFE_B_STAGE1_MUX8_RSVD0_SHIFT        (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX8_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX8_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32_SHIFT    (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_SET_MUX32_MASK)

#define PXP_WFE_B_STAGE1_MUX8_SET_RSVD0_MASK     (0xFFFFFFC0U)
#define PXP_WFE_B_STAGE1_MUX8_SET_RSVD0_SHIFT    (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX8_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX8_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_SHIFT    (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_MASK)

#define PXP_WFE_B_STAGE1_MUX8_CLR_RSVD0_MASK     (0xFFFFFFC0U)
#define PXP_WFE_B_STAGE1_MUX8_CLR_RSVD0_SHIFT    (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX8_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_MUX8_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_MASK     (0x3FU)
#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_SHIFT    (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_MASK)

#define PXP_WFE_B_STAGE1_MUX8_TOG_RSVD0_MASK     (0xFFFFFFC0U)
#define PXP_WFE_B_STAGE1_MUX8_TOG_RSVD0_SHIFT    (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE1_MUX8_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX0 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX0_MUX0_MASK          (0x3FU)
#define PXP_WFE_B_STAGE2_MUX0_MUX0_SHIFT         (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_B_STAGE2_MUX0_MUX0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX0_MASK)

#define PXP_WFE_B_STAGE2_MUX0_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE2_MUX0_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX0_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX0_MUX1_MASK          (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX0_MUX1_SHIFT         (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_B_STAGE2_MUX0_MUX1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX1_MASK)

#define PXP_WFE_B_STAGE2_MUX0_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE2_MUX0_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX0_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX0_MUX2_MASK          (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX0_MUX2_SHIFT         (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_B_STAGE2_MUX0_MUX2(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX2_MASK)

#define PXP_WFE_B_STAGE2_MUX0_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX0_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX0_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX0_MUX3_MASK          (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX0_MUX3_SHIFT         (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_B_STAGE2_MUX0_MUX3(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX3_MASK)

#define PXP_WFE_B_STAGE2_MUX0_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX0_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX0_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX0_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0_MASK      (0x3FU)
#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX0_MASK)

#define PXP_WFE_B_STAGE2_MUX0_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX0_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX0_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX1_MASK)

#define PXP_WFE_B_STAGE2_MUX0_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX0_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX0_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX2_MASK)

#define PXP_WFE_B_STAGE2_MUX0_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX0_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX0_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX3_MASK)

#define PXP_WFE_B_STAGE2_MUX0_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX0_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX0_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX0_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_MASK      (0x3FU)
#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_MASK)

#define PXP_WFE_B_STAGE2_MUX0_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX0_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX0_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_MASK)

#define PXP_WFE_B_STAGE2_MUX0_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX0_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX0_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_MASK)

#define PXP_WFE_B_STAGE2_MUX0_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX0_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX0_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_MASK)

#define PXP_WFE_B_STAGE2_MUX0_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX0_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX0_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX0_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_MASK      (0x3FU)
#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_MASK)

#define PXP_WFE_B_STAGE2_MUX0_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX0_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX0_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_MASK)

#define PXP_WFE_B_STAGE2_MUX0_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX0_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX0_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_MASK)

#define PXP_WFE_B_STAGE2_MUX0_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX0_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX0_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_MASK)

#define PXP_WFE_B_STAGE2_MUX0_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX0_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX0_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX1 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX1_MUX4_MASK          (0x3FU)
#define PXP_WFE_B_STAGE2_MUX1_MUX4_SHIFT         (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_B_STAGE2_MUX1_MUX4(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX4_MASK)

#define PXP_WFE_B_STAGE2_MUX1_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE2_MUX1_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX1_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX1_MUX5_MASK          (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX1_MUX5_SHIFT         (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_B_STAGE2_MUX1_MUX5(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX5_MASK)

#define PXP_WFE_B_STAGE2_MUX1_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE2_MUX1_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX1_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX1_MUX6_MASK          (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX1_MUX6_SHIFT         (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_B_STAGE2_MUX1_MUX6(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX6_MASK)

#define PXP_WFE_B_STAGE2_MUX1_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX1_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX1_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX1_MUX7_MASK          (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX1_MUX7_SHIFT         (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_B_STAGE2_MUX1_MUX7(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX7_MASK)

#define PXP_WFE_B_STAGE2_MUX1_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX1_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX1_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX1_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4_MASK      (0x3FU)
#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX4_MASK)

#define PXP_WFE_B_STAGE2_MUX1_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX1_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX1_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX5_MASK)

#define PXP_WFE_B_STAGE2_MUX1_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX1_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX1_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX6_MASK)

#define PXP_WFE_B_STAGE2_MUX1_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX1_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX1_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX7_MASK)

#define PXP_WFE_B_STAGE2_MUX1_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX1_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX1_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX1_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_MASK      (0x3FU)
#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_MASK)

#define PXP_WFE_B_STAGE2_MUX1_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX1_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX1_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_MASK)

#define PXP_WFE_B_STAGE2_MUX1_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX1_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX1_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_MASK)

#define PXP_WFE_B_STAGE2_MUX1_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX1_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX1_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_MASK)

#define PXP_WFE_B_STAGE2_MUX1_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX1_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX1_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX1_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_MASK      (0x3FU)
#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_MASK)

#define PXP_WFE_B_STAGE2_MUX1_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX1_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX1_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_MASK)

#define PXP_WFE_B_STAGE2_MUX1_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX1_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX1_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_MASK)

#define PXP_WFE_B_STAGE2_MUX1_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX1_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX1_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_MASK)

#define PXP_WFE_B_STAGE2_MUX1_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX1_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX1_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX2 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX2_MUX8_MASK          (0x3FU)
#define PXP_WFE_B_STAGE2_MUX2_MUX8_SHIFT         (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_B_STAGE2_MUX2_MUX8(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX8_MASK)

#define PXP_WFE_B_STAGE2_MUX2_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE2_MUX2_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX2_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX2_MUX9_MASK          (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX2_MUX9_SHIFT         (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_B_STAGE2_MUX2_MUX9(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX9_MASK)

#define PXP_WFE_B_STAGE2_MUX2_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE2_MUX2_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX2_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX2_MUX10_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX2_MUX10_SHIFT        (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_B_STAGE2_MUX2_MUX10(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX10_MASK)

#define PXP_WFE_B_STAGE2_MUX2_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX2_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX2_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX2_MUX11_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX2_MUX11_SHIFT        (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_B_STAGE2_MUX2_MUX11(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX11_MASK)

#define PXP_WFE_B_STAGE2_MUX2_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX2_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX2_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX2_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8_MASK      (0x3FU)
#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX8_MASK)

#define PXP_WFE_B_STAGE2_MUX2_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX2_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX2_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX9_MASK)

#define PXP_WFE_B_STAGE2_MUX2_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX2_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX2_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX10_MASK)

#define PXP_WFE_B_STAGE2_MUX2_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX2_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX2_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX11_MASK)

#define PXP_WFE_B_STAGE2_MUX2_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX2_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX2_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX2_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_MASK      (0x3FU)
#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_MASK)

#define PXP_WFE_B_STAGE2_MUX2_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX2_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX2_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_MASK)

#define PXP_WFE_B_STAGE2_MUX2_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX2_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX2_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_MASK)

#define PXP_WFE_B_STAGE2_MUX2_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX2_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX2_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_MASK)

#define PXP_WFE_B_STAGE2_MUX2_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX2_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX2_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX2_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_MASK      (0x3FU)
#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_MASK)

#define PXP_WFE_B_STAGE2_MUX2_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX2_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX2_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_MASK)

#define PXP_WFE_B_STAGE2_MUX2_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX2_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX2_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_MASK)

#define PXP_WFE_B_STAGE2_MUX2_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX2_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX2_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_MASK)

#define PXP_WFE_B_STAGE2_MUX2_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX2_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX2_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX3 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX3_MUX12_MASK         (0x3FU)
#define PXP_WFE_B_STAGE2_MUX3_MUX12_SHIFT        (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_B_STAGE2_MUX3_MUX12(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX12_MASK)

#define PXP_WFE_B_STAGE2_MUX3_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE2_MUX3_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX3_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX3_MUX13_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX3_MUX13_SHIFT        (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_B_STAGE2_MUX3_MUX13(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX13_MASK)

#define PXP_WFE_B_STAGE2_MUX3_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE2_MUX3_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX3_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX3_MUX14_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX3_MUX14_SHIFT        (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_B_STAGE2_MUX3_MUX14(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX14_MASK)

#define PXP_WFE_B_STAGE2_MUX3_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX3_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX3_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX3_MUX15_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX3_MUX15_SHIFT        (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_B_STAGE2_MUX3_MUX15(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX15_MASK)

#define PXP_WFE_B_STAGE2_MUX3_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX3_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX3_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX3_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX12_MASK)

#define PXP_WFE_B_STAGE2_MUX3_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX3_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX3_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX13_MASK)

#define PXP_WFE_B_STAGE2_MUX3_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX3_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX3_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX14_MASK)

#define PXP_WFE_B_STAGE2_MUX3_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX3_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX3_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX15_MASK)

#define PXP_WFE_B_STAGE2_MUX3_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX3_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX3_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX3_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_MASK)

#define PXP_WFE_B_STAGE2_MUX3_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX3_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX3_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_MASK)

#define PXP_WFE_B_STAGE2_MUX3_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX3_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX3_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_MASK)

#define PXP_WFE_B_STAGE2_MUX3_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX3_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX3_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_MASK)

#define PXP_WFE_B_STAGE2_MUX3_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX3_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX3_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX3_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_MASK)

#define PXP_WFE_B_STAGE2_MUX3_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX3_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX3_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_MASK)

#define PXP_WFE_B_STAGE2_MUX3_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX3_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX3_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_MASK)

#define PXP_WFE_B_STAGE2_MUX3_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX3_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX3_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_MASK)

#define PXP_WFE_B_STAGE2_MUX3_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX3_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX3_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX4 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX4_MUX16_MASK         (0x3FU)
#define PXP_WFE_B_STAGE2_MUX4_MUX16_SHIFT        (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_B_STAGE2_MUX4_MUX16(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX16_MASK)

#define PXP_WFE_B_STAGE2_MUX4_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE2_MUX4_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX4_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX4_MUX17_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX4_MUX17_SHIFT        (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_B_STAGE2_MUX4_MUX17(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX17_MASK)

#define PXP_WFE_B_STAGE2_MUX4_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE2_MUX4_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX4_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX4_MUX18_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX4_MUX18_SHIFT        (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_B_STAGE2_MUX4_MUX18(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX18_MASK)

#define PXP_WFE_B_STAGE2_MUX4_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX4_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX4_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX4_MUX19_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX4_MUX19_SHIFT        (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_B_STAGE2_MUX4_MUX19(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX19_MASK)

#define PXP_WFE_B_STAGE2_MUX4_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX4_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX4_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX4_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX16_MASK)

#define PXP_WFE_B_STAGE2_MUX4_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX4_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX4_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX17_MASK)

#define PXP_WFE_B_STAGE2_MUX4_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX4_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX4_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18_SHIFT    (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX18_MASK)

#define PXP_WFE_B_STAGE2_MUX4_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX4_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX4_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19_SHIFT    (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX19_MASK)

#define PXP_WFE_B_STAGE2_MUX4_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX4_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX4_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX4_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_MASK)

#define PXP_WFE_B_STAGE2_MUX4_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX4_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX4_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_MASK)

#define PXP_WFE_B_STAGE2_MUX4_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX4_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX4_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_SHIFT    (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_MASK)

#define PXP_WFE_B_STAGE2_MUX4_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX4_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX4_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_SHIFT    (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_MASK)

#define PXP_WFE_B_STAGE2_MUX4_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX4_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX4_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX4_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_MASK)

#define PXP_WFE_B_STAGE2_MUX4_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX4_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX4_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_MASK)

#define PXP_WFE_B_STAGE2_MUX4_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX4_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX4_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_SHIFT    (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_MASK)

#define PXP_WFE_B_STAGE2_MUX4_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX4_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX4_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_SHIFT    (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_MASK)

#define PXP_WFE_B_STAGE2_MUX4_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX4_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX4_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX5 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX5_MUX20_MASK         (0x3FU)
#define PXP_WFE_B_STAGE2_MUX5_MUX20_SHIFT        (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_B_STAGE2_MUX5_MUX20(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX20_MASK)

#define PXP_WFE_B_STAGE2_MUX5_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE2_MUX5_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX5_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX5_MUX21_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX5_MUX21_SHIFT        (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_B_STAGE2_MUX5_MUX21(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX21_MASK)

#define PXP_WFE_B_STAGE2_MUX5_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE2_MUX5_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX5_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX5_MUX22_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX5_MUX22_SHIFT        (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_B_STAGE2_MUX5_MUX22(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX22_MASK)

#define PXP_WFE_B_STAGE2_MUX5_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX5_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX5_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX5_MUX23_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX5_MUX23_SHIFT        (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_B_STAGE2_MUX5_MUX23(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX23_MASK)

#define PXP_WFE_B_STAGE2_MUX5_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX5_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX5_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX5_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20_SHIFT    (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX20_MASK)

#define PXP_WFE_B_STAGE2_MUX5_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX5_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX5_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21_SHIFT    (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX21_MASK)

#define PXP_WFE_B_STAGE2_MUX5_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX5_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX5_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22_SHIFT    (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX22_MASK)

#define PXP_WFE_B_STAGE2_MUX5_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX5_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX5_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23_SHIFT    (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX23_MASK)

#define PXP_WFE_B_STAGE2_MUX5_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX5_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX5_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX5_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_SHIFT    (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_MASK)

#define PXP_WFE_B_STAGE2_MUX5_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX5_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX5_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_SHIFT    (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_MASK)

#define PXP_WFE_B_STAGE2_MUX5_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX5_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX5_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_SHIFT    (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_MASK)

#define PXP_WFE_B_STAGE2_MUX5_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX5_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX5_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_SHIFT    (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_MASK)

#define PXP_WFE_B_STAGE2_MUX5_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX5_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX5_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX5_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_SHIFT    (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_MASK)

#define PXP_WFE_B_STAGE2_MUX5_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX5_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX5_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_SHIFT    (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_MASK)

#define PXP_WFE_B_STAGE2_MUX5_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX5_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX5_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_SHIFT    (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_MASK)

#define PXP_WFE_B_STAGE2_MUX5_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX5_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX5_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_SHIFT    (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_MASK)

#define PXP_WFE_B_STAGE2_MUX5_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX5_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX5_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX6 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX6_MUX24_MASK         (0x3FU)
#define PXP_WFE_B_STAGE2_MUX6_MUX24_SHIFT        (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_B_STAGE2_MUX6_MUX24(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX24_MASK)

#define PXP_WFE_B_STAGE2_MUX6_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE2_MUX6_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX6_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX6_MUX25_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX6_MUX25_SHIFT        (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_B_STAGE2_MUX6_MUX25(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX25_MASK)

#define PXP_WFE_B_STAGE2_MUX6_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE2_MUX6_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX6_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX6_MUX26_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX6_MUX26_SHIFT        (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_B_STAGE2_MUX6_MUX26(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX26_MASK)

#define PXP_WFE_B_STAGE2_MUX6_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX6_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX6_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX6_MUX27_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX6_MUX27_SHIFT        (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_B_STAGE2_MUX6_MUX27(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX27_MASK)

#define PXP_WFE_B_STAGE2_MUX6_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX6_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX6_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX6_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24_SHIFT    (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX24_MASK)

#define PXP_WFE_B_STAGE2_MUX6_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX6_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX6_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25_SHIFT    (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX25_MASK)

#define PXP_WFE_B_STAGE2_MUX6_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX6_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX6_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26_SHIFT    (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX26_MASK)

#define PXP_WFE_B_STAGE2_MUX6_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX6_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX6_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27_SHIFT    (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX27_MASK)

#define PXP_WFE_B_STAGE2_MUX6_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX6_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX6_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX6_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_SHIFT    (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_MASK)

#define PXP_WFE_B_STAGE2_MUX6_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX6_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX6_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_SHIFT    (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_MASK)

#define PXP_WFE_B_STAGE2_MUX6_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX6_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX6_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_SHIFT    (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_MASK)

#define PXP_WFE_B_STAGE2_MUX6_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX6_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX6_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_SHIFT    (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_MASK)

#define PXP_WFE_B_STAGE2_MUX6_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX6_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX6_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX6_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_SHIFT    (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_MASK)

#define PXP_WFE_B_STAGE2_MUX6_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX6_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX6_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_SHIFT    (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_MASK)

#define PXP_WFE_B_STAGE2_MUX6_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX6_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX6_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_SHIFT    (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_MASK)

#define PXP_WFE_B_STAGE2_MUX6_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX6_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX6_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_SHIFT    (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_MASK)

#define PXP_WFE_B_STAGE2_MUX6_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX6_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX6_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX7 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX7_MUX28_MASK         (0x3FU)
#define PXP_WFE_B_STAGE2_MUX7_MUX28_SHIFT        (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_B_STAGE2_MUX7_MUX28(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX28_MASK)

#define PXP_WFE_B_STAGE2_MUX7_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE2_MUX7_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX7_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX7_MUX29_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX7_MUX29_SHIFT        (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_B_STAGE2_MUX7_MUX29(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX29_MASK)

#define PXP_WFE_B_STAGE2_MUX7_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE2_MUX7_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX7_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX7_MUX30_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX7_MUX30_SHIFT        (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_B_STAGE2_MUX7_MUX30(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX30_MASK)

#define PXP_WFE_B_STAGE2_MUX7_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX7_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX7_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX7_MUX31_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX7_MUX31_SHIFT        (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_B_STAGE2_MUX7_MUX31(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX31_MASK)

#define PXP_WFE_B_STAGE2_MUX7_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX7_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX7_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX7_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28_SHIFT    (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX28_MASK)

#define PXP_WFE_B_STAGE2_MUX7_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX7_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX7_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29_SHIFT    (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX29_MASK)

#define PXP_WFE_B_STAGE2_MUX7_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX7_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX7_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30_SHIFT    (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX30_MASK)

#define PXP_WFE_B_STAGE2_MUX7_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX7_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX7_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31_SHIFT    (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX31_MASK)

#define PXP_WFE_B_STAGE2_MUX7_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX7_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX7_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX7_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_SHIFT    (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_MASK)

#define PXP_WFE_B_STAGE2_MUX7_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX7_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX7_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_SHIFT    (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_MASK)

#define PXP_WFE_B_STAGE2_MUX7_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX7_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX7_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_SHIFT    (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_MASK)

#define PXP_WFE_B_STAGE2_MUX7_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX7_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX7_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_SHIFT    (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_MASK)

#define PXP_WFE_B_STAGE2_MUX7_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX7_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX7_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX7_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_SHIFT    (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_MASK)

#define PXP_WFE_B_STAGE2_MUX7_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX7_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX7_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_SHIFT    (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_MASK)

#define PXP_WFE_B_STAGE2_MUX7_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX7_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX7_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_SHIFT    (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_MASK)

#define PXP_WFE_B_STAGE2_MUX7_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX7_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX7_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_SHIFT    (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_MASK)

#define PXP_WFE_B_STAGE2_MUX7_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX7_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX7_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX8 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX8_MUX32_MASK         (0x3FU)
#define PXP_WFE_B_STAGE2_MUX8_MUX32_SHIFT        (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_B_STAGE2_MUX8_MUX32(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX32_MASK)

#define PXP_WFE_B_STAGE2_MUX8_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE2_MUX8_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX8_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX8_MUX33_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX8_MUX33_SHIFT        (8U)
/*! MUX33 - MUX33 */
#define PXP_WFE_B_STAGE2_MUX8_MUX33(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX33_MASK)

#define PXP_WFE_B_STAGE2_MUX8_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE2_MUX8_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX8_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX8_MUX34_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX8_MUX34_SHIFT        (16U)
/*! MUX34 - MUX34 */
#define PXP_WFE_B_STAGE2_MUX8_MUX34(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX34_MASK)

#define PXP_WFE_B_STAGE2_MUX8_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX8_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX8_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX8_MUX35_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX8_MUX35_SHIFT        (24U)
/*! MUX35 - MUX35 */
#define PXP_WFE_B_STAGE2_MUX8_MUX35(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX35_MASK)

#define PXP_WFE_B_STAGE2_MUX8_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX8_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX8_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX8_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32_SHIFT    (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX32_MASK)

#define PXP_WFE_B_STAGE2_MUX8_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX8_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX8_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33_SHIFT    (8U)
/*! MUX33 - MUX33 */
#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX33_MASK)

#define PXP_WFE_B_STAGE2_MUX8_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX8_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX8_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34_SHIFT    (16U)
/*! MUX34 - MUX34 */
#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX34_MASK)

#define PXP_WFE_B_STAGE2_MUX8_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX8_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX8_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35_SHIFT    (24U)
/*! MUX35 - MUX35 */
#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX35_MASK)

#define PXP_WFE_B_STAGE2_MUX8_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX8_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX8_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX8_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_SHIFT    (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_MASK)

#define PXP_WFE_B_STAGE2_MUX8_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX8_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX8_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_SHIFT    (8U)
/*! MUX33 - MUX33 */
#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_MASK)

#define PXP_WFE_B_STAGE2_MUX8_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX8_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX8_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_SHIFT    (16U)
/*! MUX34 - MUX34 */
#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_MASK)

#define PXP_WFE_B_STAGE2_MUX8_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX8_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX8_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_SHIFT    (24U)
/*! MUX35 - MUX35 */
#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_MASK)

#define PXP_WFE_B_STAGE2_MUX8_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX8_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX8_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX8_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_SHIFT    (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_MASK)

#define PXP_WFE_B_STAGE2_MUX8_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX8_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX8_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_SHIFT    (8U)
/*! MUX33 - MUX33 */
#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_MASK)

#define PXP_WFE_B_STAGE2_MUX8_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX8_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX8_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_SHIFT    (16U)
/*! MUX34 - MUX34 */
#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_MASK)

#define PXP_WFE_B_STAGE2_MUX8_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX8_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX8_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_SHIFT    (24U)
/*! MUX35 - MUX35 */
#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_MASK)

#define PXP_WFE_B_STAGE2_MUX8_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX8_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX8_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX9 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX9_MUX36_MASK         (0x3FU)
#define PXP_WFE_B_STAGE2_MUX9_MUX36_SHIFT        (0U)
/*! MUX36 - MUX36 */
#define PXP_WFE_B_STAGE2_MUX9_MUX36(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX36_MASK)

#define PXP_WFE_B_STAGE2_MUX9_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE2_MUX9_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX9_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX9_MUX37_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX9_MUX37_SHIFT        (8U)
/*! MUX37 - MUX37 */
#define PXP_WFE_B_STAGE2_MUX9_MUX37(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX37_MASK)

#define PXP_WFE_B_STAGE2_MUX9_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE2_MUX9_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX9_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX9_MUX38_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX9_MUX38_SHIFT        (16U)
/*! MUX38 - MUX38 */
#define PXP_WFE_B_STAGE2_MUX9_MUX38(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX38_MASK)

#define PXP_WFE_B_STAGE2_MUX9_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX9_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX9_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX9_MUX39_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX9_MUX39_SHIFT        (24U)
/*! MUX39 - MUX39 */
#define PXP_WFE_B_STAGE2_MUX9_MUX39(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX39_MASK)

#define PXP_WFE_B_STAGE2_MUX9_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX9_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX9_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX9_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36_SHIFT    (0U)
/*! MUX36 - MUX36 */
#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX36_MASK)

#define PXP_WFE_B_STAGE2_MUX9_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX9_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX9_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37_SHIFT    (8U)
/*! MUX37 - MUX37 */
#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX37_MASK)

#define PXP_WFE_B_STAGE2_MUX9_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX9_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX9_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38_SHIFT    (16U)
/*! MUX38 - MUX38 */
#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX38_MASK)

#define PXP_WFE_B_STAGE2_MUX9_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX9_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX9_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39_SHIFT    (24U)
/*! MUX39 - MUX39 */
#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX39_MASK)

#define PXP_WFE_B_STAGE2_MUX9_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX9_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX9_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX9_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_SHIFT    (0U)
/*! MUX36 - MUX36 */
#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_MASK)

#define PXP_WFE_B_STAGE2_MUX9_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX9_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX9_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_SHIFT    (8U)
/*! MUX37 - MUX37 */
#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_MASK)

#define PXP_WFE_B_STAGE2_MUX9_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX9_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX9_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_SHIFT    (16U)
/*! MUX38 - MUX38 */
#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_MASK)

#define PXP_WFE_B_STAGE2_MUX9_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX9_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX9_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_SHIFT    (24U)
/*! MUX39 - MUX39 */
#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_MASK)

#define PXP_WFE_B_STAGE2_MUX9_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX9_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX9_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX9_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_MASK     (0x3FU)
#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_SHIFT    (0U)
/*! MUX36 - MUX36 */
#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_MASK)

#define PXP_WFE_B_STAGE2_MUX9_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE2_MUX9_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX9_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_SHIFT    (8U)
/*! MUX37 - MUX37 */
#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_MASK)

#define PXP_WFE_B_STAGE2_MUX9_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE2_MUX9_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX9_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_SHIFT    (16U)
/*! MUX38 - MUX38 */
#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_MASK)

#define PXP_WFE_B_STAGE2_MUX9_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX9_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX9_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_SHIFT    (24U)
/*! MUX39 - MUX39 */
#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_MASK)

#define PXP_WFE_B_STAGE2_MUX9_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX9_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX9_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX10 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX10_MUX40_MASK        (0x3FU)
#define PXP_WFE_B_STAGE2_MUX10_MUX40_SHIFT       (0U)
/*! MUX40 - MUX40
 *  0b000000..INC : Increment operation.
 *  0b000001..DEC : Decrement operation.
 *  0b000010..ADD : Addition operation.
 *  0b000011..MINUS : Subtraction operation.
 *  0b000100..AND : Bitwise AND operation. A AND B.
 *  0b000101..OR : Bitwise OR operation. A OR B.
 *  0b000110..XOR : Bitwise XOR operation. A XOR B.
 *  0b000111..SHIFTLEFT : Shift A operand left by B operand places.
 *  0b001000..SHIFTRIGHT : Shift A operand right by B operand places.
 *  0b001001..BIT_AND : Reduction AND operation on A operand.
 *  0b001010..BIT_OR : Reduction OR operation on A operand.
 *  0b001011..BIT_CMP : Compare A and B operands and set equal flag if A and B are equal. All other output is 0.
 *  0b001100..NOP : No operation. All outputs are 0.
 */
#define PXP_WFE_B_STAGE2_MUX10_MUX40(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX40_MASK)

#define PXP_WFE_B_STAGE2_MUX10_RSVD3_MASK        (0xC0U)
#define PXP_WFE_B_STAGE2_MUX10_RSVD3_SHIFT       (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX10_RSVD3(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX10_MUX41_MASK        (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX10_MUX41_SHIFT       (8U)
/*! MUX41 - MUX41 */
#define PXP_WFE_B_STAGE2_MUX10_MUX41(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX41_MASK)

#define PXP_WFE_B_STAGE2_MUX10_RSVD2_MASK        (0xC000U)
#define PXP_WFE_B_STAGE2_MUX10_RSVD2_SHIFT       (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX10_RSVD2(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX10_MUX42_MASK        (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX10_MUX42_SHIFT       (16U)
/*! MUX42 - MUX42 */
#define PXP_WFE_B_STAGE2_MUX10_MUX42(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX42_MASK)

#define PXP_WFE_B_STAGE2_MUX10_RSVD1_MASK        (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX10_RSVD1_SHIFT       (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX10_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX10_MUX43_MASK        (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX10_MUX43_SHIFT       (24U)
/*! MUX43 - MUX43 */
#define PXP_WFE_B_STAGE2_MUX10_MUX43(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX43_MASK)

#define PXP_WFE_B_STAGE2_MUX10_RSVD0_MASK        (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX10_RSVD0_SHIFT       (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX10_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX10_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40_MASK    (0x3FU)
#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40_SHIFT   (0U)
/*! MUX40 - MUX40 */
#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX40_MASK)

#define PXP_WFE_B_STAGE2_MUX10_SET_RSVD3_MASK    (0xC0U)
#define PXP_WFE_B_STAGE2_MUX10_SET_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX10_SET_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41_MASK    (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41_SHIFT   (8U)
/*! MUX41 - MUX41 */
#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX41_MASK)

#define PXP_WFE_B_STAGE2_MUX10_SET_RSVD2_MASK    (0xC000U)
#define PXP_WFE_B_STAGE2_MUX10_SET_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX10_SET_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42_MASK    (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42_SHIFT   (16U)
/*! MUX42 - MUX42 */
#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX42_MASK)

#define PXP_WFE_B_STAGE2_MUX10_SET_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX10_SET_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX10_SET_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43_MASK    (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43_SHIFT   (24U)
/*! MUX43 - MUX43 */
#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX43_MASK)

#define PXP_WFE_B_STAGE2_MUX10_SET_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX10_SET_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX10_SET_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX10_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_MASK    (0x3FU)
#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_SHIFT   (0U)
/*! MUX40 - MUX40 */
#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_MASK)

#define PXP_WFE_B_STAGE2_MUX10_CLR_RSVD3_MASK    (0xC0U)
#define PXP_WFE_B_STAGE2_MUX10_CLR_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX10_CLR_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_MASK    (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_SHIFT   (8U)
/*! MUX41 - MUX41 */
#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_MASK)

#define PXP_WFE_B_STAGE2_MUX10_CLR_RSVD2_MASK    (0xC000U)
#define PXP_WFE_B_STAGE2_MUX10_CLR_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX10_CLR_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_MASK    (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_SHIFT   (16U)
/*! MUX42 - MUX42 */
#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_MASK)

#define PXP_WFE_B_STAGE2_MUX10_CLR_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX10_CLR_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX10_CLR_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_MASK    (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_SHIFT   (24U)
/*! MUX43 - MUX43 */
#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_MASK)

#define PXP_WFE_B_STAGE2_MUX10_CLR_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX10_CLR_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX10_CLR_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX10_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_MASK    (0x3FU)
#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_SHIFT   (0U)
/*! MUX40 - MUX40 */
#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_MASK)

#define PXP_WFE_B_STAGE2_MUX10_TOG_RSVD3_MASK    (0xC0U)
#define PXP_WFE_B_STAGE2_MUX10_TOG_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX10_TOG_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_MASK    (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_SHIFT   (8U)
/*! MUX41 - MUX41 */
#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_MASK)

#define PXP_WFE_B_STAGE2_MUX10_TOG_RSVD2_MASK    (0xC000U)
#define PXP_WFE_B_STAGE2_MUX10_TOG_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX10_TOG_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_MASK    (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_SHIFT   (16U)
/*! MUX42 - MUX42 */
#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_MASK)

#define PXP_WFE_B_STAGE2_MUX10_TOG_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX10_TOG_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX10_TOG_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_MASK    (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_SHIFT   (24U)
/*! MUX43 - MUX43 */
#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_MASK)

#define PXP_WFE_B_STAGE2_MUX10_TOG_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX10_TOG_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX10_TOG_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX11 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX11_MUX44_MASK        (0x3FU)
#define PXP_WFE_B_STAGE2_MUX11_MUX44_SHIFT       (0U)
/*! MUX44 - MUX44 */
#define PXP_WFE_B_STAGE2_MUX11_MUX44(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX44_MASK)

#define PXP_WFE_B_STAGE2_MUX11_RSVD3_MASK        (0xC0U)
#define PXP_WFE_B_STAGE2_MUX11_RSVD3_SHIFT       (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX11_RSVD3(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX11_MUX45_MASK        (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX11_MUX45_SHIFT       (8U)
/*! MUX45 - MUX45 */
#define PXP_WFE_B_STAGE2_MUX11_MUX45(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX45_MASK)

#define PXP_WFE_B_STAGE2_MUX11_RSVD2_MASK        (0xC000U)
#define PXP_WFE_B_STAGE2_MUX11_RSVD2_SHIFT       (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX11_RSVD2(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX11_MUX46_MASK        (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX11_MUX46_SHIFT       (16U)
/*! MUX46 - MUX46 */
#define PXP_WFE_B_STAGE2_MUX11_MUX46(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX46_MASK)

#define PXP_WFE_B_STAGE2_MUX11_RSVD1_MASK        (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX11_RSVD1_SHIFT       (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX11_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX11_MUX47_MASK        (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX11_MUX47_SHIFT       (24U)
/*! MUX47 - MUX47 */
#define PXP_WFE_B_STAGE2_MUX11_MUX47(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX47_MASK)

#define PXP_WFE_B_STAGE2_MUX11_RSVD0_MASK        (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX11_RSVD0_SHIFT       (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX11_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX11_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44_MASK    (0x3FU)
#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44_SHIFT   (0U)
/*! MUX44 - MUX44 */
#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX44_MASK)

#define PXP_WFE_B_STAGE2_MUX11_SET_RSVD3_MASK    (0xC0U)
#define PXP_WFE_B_STAGE2_MUX11_SET_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX11_SET_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45_MASK    (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45_SHIFT   (8U)
/*! MUX45 - MUX45 */
#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX45_MASK)

#define PXP_WFE_B_STAGE2_MUX11_SET_RSVD2_MASK    (0xC000U)
#define PXP_WFE_B_STAGE2_MUX11_SET_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX11_SET_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46_MASK    (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46_SHIFT   (16U)
/*! MUX46 - MUX46 */
#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX46_MASK)

#define PXP_WFE_B_STAGE2_MUX11_SET_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX11_SET_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX11_SET_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47_MASK    (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47_SHIFT   (24U)
/*! MUX47 - MUX47 */
#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX47_MASK)

#define PXP_WFE_B_STAGE2_MUX11_SET_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX11_SET_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX11_SET_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX11_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_MASK    (0x3FU)
#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_SHIFT   (0U)
/*! MUX44 - MUX44 */
#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_MASK)

#define PXP_WFE_B_STAGE2_MUX11_CLR_RSVD3_MASK    (0xC0U)
#define PXP_WFE_B_STAGE2_MUX11_CLR_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX11_CLR_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_MASK    (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_SHIFT   (8U)
/*! MUX45 - MUX45 */
#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_MASK)

#define PXP_WFE_B_STAGE2_MUX11_CLR_RSVD2_MASK    (0xC000U)
#define PXP_WFE_B_STAGE2_MUX11_CLR_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX11_CLR_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_MASK    (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_SHIFT   (16U)
/*! MUX46 - MUX46 */
#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_MASK)

#define PXP_WFE_B_STAGE2_MUX11_CLR_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX11_CLR_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX11_CLR_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_MASK    (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_SHIFT   (24U)
/*! MUX47 - MUX47 */
#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_MASK)

#define PXP_WFE_B_STAGE2_MUX11_CLR_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX11_CLR_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX11_CLR_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX11_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_MASK    (0x3FU)
#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_SHIFT   (0U)
/*! MUX44 - MUX44 */
#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_MASK)

#define PXP_WFE_B_STAGE2_MUX11_TOG_RSVD3_MASK    (0xC0U)
#define PXP_WFE_B_STAGE2_MUX11_TOG_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_MUX11_TOG_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_MASK    (0x3F00U)
#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_SHIFT   (8U)
/*! MUX45 - MUX45 */
#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_MASK)

#define PXP_WFE_B_STAGE2_MUX11_TOG_RSVD2_MASK    (0xC000U)
#define PXP_WFE_B_STAGE2_MUX11_TOG_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_MUX11_TOG_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_MASK    (0x3F0000U)
#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_SHIFT   (16U)
/*! MUX46 - MUX46 */
#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_MASK)

#define PXP_WFE_B_STAGE2_MUX11_TOG_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_B_STAGE2_MUX11_TOG_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_MUX11_TOG_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_MASK    (0x3F000000U)
#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_SHIFT   (24U)
/*! MUX47 - MUX47 */
#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_MASK)

#define PXP_WFE_B_STAGE2_MUX11_TOG_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_B_STAGE2_MUX11_TOG_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX11_TOG_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX12 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX12_MUX48_MASK        (0x3FU)
#define PXP_WFE_B_STAGE2_MUX12_MUX48_SHIFT       (0U)
/*! MUX48 - MUX48 */
#define PXP_WFE_B_STAGE2_MUX12_MUX48(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_MUX48_MASK)

#define PXP_WFE_B_STAGE2_MUX12_RSVD0_MASK        (0xFFFFFFC0U)
#define PXP_WFE_B_STAGE2_MUX12_RSVD0_SHIFT       (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX12_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX12_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48_MASK    (0x3FU)
#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48_SHIFT   (0U)
/*! MUX48 - MUX48 */
#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_SET_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_SET_MUX48_MASK)

#define PXP_WFE_B_STAGE2_MUX12_SET_RSVD0_MASK    (0xFFFFFFC0U)
#define PXP_WFE_B_STAGE2_MUX12_SET_RSVD0_SHIFT   (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX12_SET_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX12_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_MASK    (0x3FU)
#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_SHIFT   (0U)
/*! MUX48 - MUX48 */
#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_MASK)

#define PXP_WFE_B_STAGE2_MUX12_CLR_RSVD0_MASK    (0xFFFFFFC0U)
#define PXP_WFE_B_STAGE2_MUX12_CLR_RSVD0_SHIFT   (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX12_CLR_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_MUX12_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_MASK    (0x3FU)
#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_SHIFT   (0U)
/*! MUX48 - MUX48 */
#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_MASK)

#define PXP_WFE_B_STAGE2_MUX12_TOG_RSVD0_MASK    (0xFFFFFFC0U)
#define PXP_WFE_B_STAGE2_MUX12_TOG_RSVD0_SHIFT   (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_MUX12_TOG_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX0 -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX0_MUX0_MASK          (0x3FU)
#define PXP_WFE_B_STAGE3_MUX0_MUX0_SHIFT         (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_B_STAGE3_MUX0_MUX0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX0_MASK)

#define PXP_WFE_B_STAGE3_MUX0_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE3_MUX0_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX0_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX0_MUX1_MASK          (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX0_MUX1_SHIFT         (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_B_STAGE3_MUX0_MUX1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX1_MASK)

#define PXP_WFE_B_STAGE3_MUX0_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE3_MUX0_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX0_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX0_MUX2_MASK          (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX0_MUX2_SHIFT         (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_B_STAGE3_MUX0_MUX2(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX2_MASK)

#define PXP_WFE_B_STAGE3_MUX0_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX0_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX0_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX0_MUX3_MASK          (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX0_MUX3_SHIFT         (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_B_STAGE3_MUX0_MUX3(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX3_MASK)

#define PXP_WFE_B_STAGE3_MUX0_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX0_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX0_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX0_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0_MASK      (0x3FU)
#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX0_MASK)

#define PXP_WFE_B_STAGE3_MUX0_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX0_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX0_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX1_MASK)

#define PXP_WFE_B_STAGE3_MUX0_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX0_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX0_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX2_MASK)

#define PXP_WFE_B_STAGE3_MUX0_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX0_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX0_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX3_MASK)

#define PXP_WFE_B_STAGE3_MUX0_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX0_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX0_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX0_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_MASK      (0x3FU)
#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_MASK)

#define PXP_WFE_B_STAGE3_MUX0_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX0_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX0_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_MASK)

#define PXP_WFE_B_STAGE3_MUX0_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX0_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX0_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_MASK)

#define PXP_WFE_B_STAGE3_MUX0_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX0_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX0_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_MASK)

#define PXP_WFE_B_STAGE3_MUX0_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX0_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX0_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX0_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_MASK      (0x3FU)
#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_SHIFT     (0U)
/*! MUX0 - MUX0 */
#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_MASK)

#define PXP_WFE_B_STAGE3_MUX0_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX0_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX0_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_SHIFT     (8U)
/*! MUX1 - MUX1 */
#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_MASK)

#define PXP_WFE_B_STAGE3_MUX0_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX0_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX0_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_SHIFT     (16U)
/*! MUX2 - MUX2 */
#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_MASK)

#define PXP_WFE_B_STAGE3_MUX0_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX0_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX0_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_SHIFT     (24U)
/*! MUX3 - MUX3 */
#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_MASK)

#define PXP_WFE_B_STAGE3_MUX0_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX0_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX0_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX1 -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX1_MUX4_MASK          (0x3FU)
#define PXP_WFE_B_STAGE3_MUX1_MUX4_SHIFT         (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_B_STAGE3_MUX1_MUX4(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX4_MASK)

#define PXP_WFE_B_STAGE3_MUX1_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE3_MUX1_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX1_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX1_MUX5_MASK          (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX1_MUX5_SHIFT         (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_B_STAGE3_MUX1_MUX5(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX5_MASK)

#define PXP_WFE_B_STAGE3_MUX1_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE3_MUX1_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX1_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX1_MUX6_MASK          (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX1_MUX6_SHIFT         (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_B_STAGE3_MUX1_MUX6(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX6_MASK)

#define PXP_WFE_B_STAGE3_MUX1_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX1_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX1_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX1_MUX7_MASK          (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX1_MUX7_SHIFT         (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_B_STAGE3_MUX1_MUX7(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX7_MASK)

#define PXP_WFE_B_STAGE3_MUX1_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX1_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX1_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX1_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4_MASK      (0x3FU)
#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX4_MASK)

#define PXP_WFE_B_STAGE3_MUX1_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX1_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX1_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX5_MASK)

#define PXP_WFE_B_STAGE3_MUX1_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX1_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX1_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX6_MASK)

#define PXP_WFE_B_STAGE3_MUX1_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX1_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX1_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX7_MASK)

#define PXP_WFE_B_STAGE3_MUX1_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX1_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX1_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX1_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_MASK      (0x3FU)
#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_MASK)

#define PXP_WFE_B_STAGE3_MUX1_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX1_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX1_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_MASK)

#define PXP_WFE_B_STAGE3_MUX1_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX1_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX1_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_MASK)

#define PXP_WFE_B_STAGE3_MUX1_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX1_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX1_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_MASK)

#define PXP_WFE_B_STAGE3_MUX1_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX1_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX1_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX1_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_MASK      (0x3FU)
#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_SHIFT     (0U)
/*! MUX4 - MUX4 */
#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_MASK)

#define PXP_WFE_B_STAGE3_MUX1_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX1_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX1_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_SHIFT     (8U)
/*! MUX5 - MUX5 */
#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_MASK)

#define PXP_WFE_B_STAGE3_MUX1_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX1_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX1_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_MASK      (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_SHIFT     (16U)
/*! MUX6 - MUX6 */
#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_MASK)

#define PXP_WFE_B_STAGE3_MUX1_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX1_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX1_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_MASK      (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_SHIFT     (24U)
/*! MUX7 - MUX7 */
#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_MASK)

#define PXP_WFE_B_STAGE3_MUX1_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX1_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX1_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX2 -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX2_MUX8_MASK          (0x3FU)
#define PXP_WFE_B_STAGE3_MUX2_MUX8_SHIFT         (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_B_STAGE3_MUX2_MUX8(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX8_MASK)

#define PXP_WFE_B_STAGE3_MUX2_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE3_MUX2_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX2_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX2_MUX9_MASK          (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX2_MUX9_SHIFT         (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_B_STAGE3_MUX2_MUX9(x)            (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX9_MASK)

#define PXP_WFE_B_STAGE3_MUX2_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE3_MUX2_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX2_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX2_MUX10_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX2_MUX10_SHIFT        (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_B_STAGE3_MUX2_MUX10(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX10_MASK)

#define PXP_WFE_B_STAGE3_MUX2_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX2_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX2_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX2_MUX11_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX2_MUX11_SHIFT        (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_B_STAGE3_MUX2_MUX11(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX11_MASK)

#define PXP_WFE_B_STAGE3_MUX2_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX2_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX2_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX2_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8_MASK      (0x3FU)
#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX8_MASK)

#define PXP_WFE_B_STAGE3_MUX2_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX2_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX2_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX9_MASK)

#define PXP_WFE_B_STAGE3_MUX2_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX2_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX2_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX10_MASK)

#define PXP_WFE_B_STAGE3_MUX2_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX2_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX2_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX11_MASK)

#define PXP_WFE_B_STAGE3_MUX2_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX2_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX2_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX2_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_MASK      (0x3FU)
#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_MASK)

#define PXP_WFE_B_STAGE3_MUX2_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX2_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX2_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_MASK)

#define PXP_WFE_B_STAGE3_MUX2_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX2_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX2_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_MASK)

#define PXP_WFE_B_STAGE3_MUX2_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX2_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX2_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_MASK)

#define PXP_WFE_B_STAGE3_MUX2_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX2_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX2_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX2_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_MASK      (0x3FU)
#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_SHIFT     (0U)
/*! MUX8 - MUX8 */
#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_MASK)

#define PXP_WFE_B_STAGE3_MUX2_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX2_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX2_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_MASK      (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_SHIFT     (8U)
/*! MUX9 - MUX9 */
#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_MASK)

#define PXP_WFE_B_STAGE3_MUX2_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX2_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX2_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_SHIFT    (16U)
/*! MUX10 - MUX10 */
#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_MASK)

#define PXP_WFE_B_STAGE3_MUX2_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX2_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX2_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_SHIFT    (24U)
/*! MUX11 - MUX11 */
#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_MASK)

#define PXP_WFE_B_STAGE3_MUX2_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX2_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX2_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX3 -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX3_MUX12_MASK         (0x3FU)
#define PXP_WFE_B_STAGE3_MUX3_MUX12_SHIFT        (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_B_STAGE3_MUX3_MUX12(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX12_MASK)

#define PXP_WFE_B_STAGE3_MUX3_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE3_MUX3_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX3_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX3_MUX13_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX3_MUX13_SHIFT        (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_B_STAGE3_MUX3_MUX13(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX13_MASK)

#define PXP_WFE_B_STAGE3_MUX3_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE3_MUX3_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX3_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX3_MUX14_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX3_MUX14_SHIFT        (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_B_STAGE3_MUX3_MUX14(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX14_MASK)

#define PXP_WFE_B_STAGE3_MUX3_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX3_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX3_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX3_MUX15_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX3_MUX15_SHIFT        (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_B_STAGE3_MUX3_MUX15(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX15_MASK)

#define PXP_WFE_B_STAGE3_MUX3_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX3_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX3_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX3_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX12_MASK)

#define PXP_WFE_B_STAGE3_MUX3_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX3_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX3_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX13_MASK)

#define PXP_WFE_B_STAGE3_MUX3_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX3_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX3_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX14_MASK)

#define PXP_WFE_B_STAGE3_MUX3_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX3_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX3_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX15_MASK)

#define PXP_WFE_B_STAGE3_MUX3_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX3_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX3_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX3_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_MASK)

#define PXP_WFE_B_STAGE3_MUX3_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX3_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX3_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_MASK)

#define PXP_WFE_B_STAGE3_MUX3_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX3_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX3_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_MASK)

#define PXP_WFE_B_STAGE3_MUX3_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX3_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX3_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_MASK)

#define PXP_WFE_B_STAGE3_MUX3_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX3_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX3_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX3_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_SHIFT    (0U)
/*! MUX12 - MUX12 */
#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_MASK)

#define PXP_WFE_B_STAGE3_MUX3_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX3_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX3_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_SHIFT    (8U)
/*! MUX13 - MUX13 */
#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_MASK)

#define PXP_WFE_B_STAGE3_MUX3_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX3_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX3_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_SHIFT    (16U)
/*! MUX14 - MUX14 */
#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_MASK)

#define PXP_WFE_B_STAGE3_MUX3_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX3_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX3_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_SHIFT    (24U)
/*! MUX15 - MUX15 */
#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_MASK)

#define PXP_WFE_B_STAGE3_MUX3_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX3_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX3_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX4 -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX4_MUX16_MASK         (0x3FU)
#define PXP_WFE_B_STAGE3_MUX4_MUX16_SHIFT        (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_B_STAGE3_MUX4_MUX16(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX16_MASK)

#define PXP_WFE_B_STAGE3_MUX4_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE3_MUX4_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX4_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX4_MUX17_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX4_MUX17_SHIFT        (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_B_STAGE3_MUX4_MUX17(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX17_MASK)

#define PXP_WFE_B_STAGE3_MUX4_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE3_MUX4_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX4_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX4_MUX18_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX4_MUX18_SHIFT        (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_B_STAGE3_MUX4_MUX18(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX18_MASK)

#define PXP_WFE_B_STAGE3_MUX4_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX4_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX4_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX4_MUX19_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX4_MUX19_SHIFT        (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_B_STAGE3_MUX4_MUX19(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX19_MASK)

#define PXP_WFE_B_STAGE3_MUX4_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX4_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX4_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX4_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX16_MASK)

#define PXP_WFE_B_STAGE3_MUX4_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX4_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX4_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX17_MASK)

#define PXP_WFE_B_STAGE3_MUX4_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX4_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX4_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18_SHIFT    (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX18_MASK)

#define PXP_WFE_B_STAGE3_MUX4_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX4_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX4_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19_SHIFT    (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX19_MASK)

#define PXP_WFE_B_STAGE3_MUX4_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX4_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX4_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX4_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_MASK)

#define PXP_WFE_B_STAGE3_MUX4_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX4_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX4_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_MASK)

#define PXP_WFE_B_STAGE3_MUX4_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX4_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX4_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_SHIFT    (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_MASK)

#define PXP_WFE_B_STAGE3_MUX4_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX4_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX4_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_SHIFT    (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_MASK)

#define PXP_WFE_B_STAGE3_MUX4_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX4_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX4_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX4_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_SHIFT    (0U)
/*! MUX16 - MUX16 */
#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_MASK)

#define PXP_WFE_B_STAGE3_MUX4_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX4_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX4_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_SHIFT    (8U)
/*! MUX17 - MUX17 */
#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_MASK)

#define PXP_WFE_B_STAGE3_MUX4_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX4_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX4_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_SHIFT    (16U)
/*! MUX18 - MUX18 */
#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_MASK)

#define PXP_WFE_B_STAGE3_MUX4_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX4_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX4_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_SHIFT    (24U)
/*! MUX19 - MUX19 */
#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_MASK)

#define PXP_WFE_B_STAGE3_MUX4_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX4_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX4_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX5 -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX5_MUX20_MASK         (0x3FU)
#define PXP_WFE_B_STAGE3_MUX5_MUX20_SHIFT        (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_B_STAGE3_MUX5_MUX20(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX20_MASK)

#define PXP_WFE_B_STAGE3_MUX5_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE3_MUX5_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX5_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX5_MUX21_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX5_MUX21_SHIFT        (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_B_STAGE3_MUX5_MUX21(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX21_MASK)

#define PXP_WFE_B_STAGE3_MUX5_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE3_MUX5_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX5_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX5_MUX22_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX5_MUX22_SHIFT        (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_B_STAGE3_MUX5_MUX22(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX22_MASK)

#define PXP_WFE_B_STAGE3_MUX5_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX5_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX5_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX5_MUX23_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX5_MUX23_SHIFT        (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_B_STAGE3_MUX5_MUX23(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX23_MASK)

#define PXP_WFE_B_STAGE3_MUX5_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX5_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX5_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX5_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20_SHIFT    (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX20_MASK)

#define PXP_WFE_B_STAGE3_MUX5_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX5_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX5_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21_SHIFT    (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX21_MASK)

#define PXP_WFE_B_STAGE3_MUX5_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX5_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX5_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22_SHIFT    (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX22_MASK)

#define PXP_WFE_B_STAGE3_MUX5_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX5_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX5_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23_SHIFT    (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX23_MASK)

#define PXP_WFE_B_STAGE3_MUX5_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX5_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX5_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX5_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_SHIFT    (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_MASK)

#define PXP_WFE_B_STAGE3_MUX5_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX5_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX5_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_SHIFT    (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_MASK)

#define PXP_WFE_B_STAGE3_MUX5_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX5_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX5_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_SHIFT    (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_MASK)

#define PXP_WFE_B_STAGE3_MUX5_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX5_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX5_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_SHIFT    (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_MASK)

#define PXP_WFE_B_STAGE3_MUX5_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX5_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX5_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX5_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_SHIFT    (0U)
/*! MUX20 - MUX20 */
#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_MASK)

#define PXP_WFE_B_STAGE3_MUX5_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX5_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX5_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_SHIFT    (8U)
/*! MUX21 - MUX21 */
#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_MASK)

#define PXP_WFE_B_STAGE3_MUX5_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX5_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX5_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_SHIFT    (16U)
/*! MUX22 - MUX22 */
#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_MASK)

#define PXP_WFE_B_STAGE3_MUX5_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX5_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX5_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_SHIFT    (24U)
/*! MUX23 - MUX23 */
#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_MASK)

#define PXP_WFE_B_STAGE3_MUX5_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX5_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX5_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX6 -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX6_MUX24_MASK         (0x3FU)
#define PXP_WFE_B_STAGE3_MUX6_MUX24_SHIFT        (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_B_STAGE3_MUX6_MUX24(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX24_MASK)

#define PXP_WFE_B_STAGE3_MUX6_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE3_MUX6_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX6_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX6_MUX25_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX6_MUX25_SHIFT        (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_B_STAGE3_MUX6_MUX25(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX25_MASK)

#define PXP_WFE_B_STAGE3_MUX6_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE3_MUX6_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX6_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX6_MUX26_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX6_MUX26_SHIFT        (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_B_STAGE3_MUX6_MUX26(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX26_MASK)

#define PXP_WFE_B_STAGE3_MUX6_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX6_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX6_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX6_MUX27_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX6_MUX27_SHIFT        (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_B_STAGE3_MUX6_MUX27(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX27_MASK)

#define PXP_WFE_B_STAGE3_MUX6_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX6_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX6_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX6_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24_SHIFT    (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX24_MASK)

#define PXP_WFE_B_STAGE3_MUX6_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX6_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX6_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25_SHIFT    (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX25_MASK)

#define PXP_WFE_B_STAGE3_MUX6_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX6_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX6_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26_SHIFT    (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX26_MASK)

#define PXP_WFE_B_STAGE3_MUX6_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX6_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX6_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27_SHIFT    (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX27_MASK)

#define PXP_WFE_B_STAGE3_MUX6_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX6_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX6_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX6_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_SHIFT    (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_MASK)

#define PXP_WFE_B_STAGE3_MUX6_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX6_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX6_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_SHIFT    (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_MASK)

#define PXP_WFE_B_STAGE3_MUX6_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX6_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX6_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_SHIFT    (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_MASK)

#define PXP_WFE_B_STAGE3_MUX6_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX6_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX6_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_SHIFT    (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_MASK)

#define PXP_WFE_B_STAGE3_MUX6_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX6_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX6_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX6_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_SHIFT    (0U)
/*! MUX24 - MUX24 */
#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_MASK)

#define PXP_WFE_B_STAGE3_MUX6_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX6_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX6_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_SHIFT    (8U)
/*! MUX25 - MUX25 */
#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_MASK)

#define PXP_WFE_B_STAGE3_MUX6_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX6_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX6_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_SHIFT    (16U)
/*! MUX26 - MUX26 */
#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_MASK)

#define PXP_WFE_B_STAGE3_MUX6_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX6_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX6_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_SHIFT    (24U)
/*! MUX27 - MUX27 */
#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_MASK)

#define PXP_WFE_B_STAGE3_MUX6_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX6_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX6_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX7 -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX7_MUX28_MASK         (0x3FU)
#define PXP_WFE_B_STAGE3_MUX7_MUX28_SHIFT        (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_B_STAGE3_MUX7_MUX28(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX28_MASK)

#define PXP_WFE_B_STAGE3_MUX7_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE3_MUX7_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX7_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX7_MUX29_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX7_MUX29_SHIFT        (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_B_STAGE3_MUX7_MUX29(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX29_MASK)

#define PXP_WFE_B_STAGE3_MUX7_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE3_MUX7_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX7_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX7_MUX30_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX7_MUX30_SHIFT        (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_B_STAGE3_MUX7_MUX30(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX30_MASK)

#define PXP_WFE_B_STAGE3_MUX7_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX7_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX7_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX7_MUX31_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX7_MUX31_SHIFT        (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_B_STAGE3_MUX7_MUX31(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX31_MASK)

#define PXP_WFE_B_STAGE3_MUX7_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX7_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX7_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX7_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28_SHIFT    (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX28_MASK)

#define PXP_WFE_B_STAGE3_MUX7_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX7_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX7_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29_SHIFT    (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX29_MASK)

#define PXP_WFE_B_STAGE3_MUX7_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX7_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX7_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30_SHIFT    (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX30_MASK)

#define PXP_WFE_B_STAGE3_MUX7_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX7_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX7_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31_SHIFT    (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX31_MASK)

#define PXP_WFE_B_STAGE3_MUX7_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX7_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX7_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX7_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_SHIFT    (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_MASK)

#define PXP_WFE_B_STAGE3_MUX7_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX7_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX7_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_SHIFT    (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_MASK)

#define PXP_WFE_B_STAGE3_MUX7_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX7_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX7_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_SHIFT    (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_MASK)

#define PXP_WFE_B_STAGE3_MUX7_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX7_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX7_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_SHIFT    (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_MASK)

#define PXP_WFE_B_STAGE3_MUX7_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX7_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX7_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX7_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_SHIFT    (0U)
/*! MUX28 - MUX28 */
#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_MASK)

#define PXP_WFE_B_STAGE3_MUX7_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX7_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX7_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_SHIFT    (8U)
/*! MUX29 - MUX29 */
#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_MASK)

#define PXP_WFE_B_STAGE3_MUX7_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX7_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX7_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_SHIFT    (16U)
/*! MUX30 - MUX30 */
#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_MASK)

#define PXP_WFE_B_STAGE3_MUX7_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX7_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX7_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_SHIFT    (24U)
/*! MUX31 - MUX31 */
#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_MASK)

#define PXP_WFE_B_STAGE3_MUX7_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX7_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX7_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX8 -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX8_MUX32_MASK         (0x3FU)
#define PXP_WFE_B_STAGE3_MUX8_MUX32_SHIFT        (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_B_STAGE3_MUX8_MUX32(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX32_MASK)

#define PXP_WFE_B_STAGE3_MUX8_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE3_MUX8_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX8_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX8_MUX33_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX8_MUX33_SHIFT        (8U)
/*! MUX33 - MUX33 */
#define PXP_WFE_B_STAGE3_MUX8_MUX33(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX33_MASK)

#define PXP_WFE_B_STAGE3_MUX8_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE3_MUX8_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX8_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX8_MUX34_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX8_MUX34_SHIFT        (16U)
/*! MUX34 - MUX34 */
#define PXP_WFE_B_STAGE3_MUX8_MUX34(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX34_MASK)

#define PXP_WFE_B_STAGE3_MUX8_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX8_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX8_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX8_MUX35_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX8_MUX35_SHIFT        (24U)
/*! MUX35 - MUX35 */
#define PXP_WFE_B_STAGE3_MUX8_MUX35(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX35_MASK)

#define PXP_WFE_B_STAGE3_MUX8_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX8_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX8_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX8_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32_SHIFT    (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX32_MASK)

#define PXP_WFE_B_STAGE3_MUX8_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX8_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX8_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33_SHIFT    (8U)
/*! MUX33 - MUX33 */
#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX33_MASK)

#define PXP_WFE_B_STAGE3_MUX8_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX8_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX8_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34_SHIFT    (16U)
/*! MUX34 - MUX34 */
#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX34_MASK)

#define PXP_WFE_B_STAGE3_MUX8_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX8_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX8_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35_SHIFT    (24U)
/*! MUX35 - MUX35 */
#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX35_MASK)

#define PXP_WFE_B_STAGE3_MUX8_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX8_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX8_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX8_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_SHIFT    (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_MASK)

#define PXP_WFE_B_STAGE3_MUX8_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX8_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX8_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_SHIFT    (8U)
/*! MUX33 - MUX33 */
#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_MASK)

#define PXP_WFE_B_STAGE3_MUX8_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX8_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX8_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_SHIFT    (16U)
/*! MUX34 - MUX34 */
#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_MASK)

#define PXP_WFE_B_STAGE3_MUX8_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX8_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX8_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_SHIFT    (24U)
/*! MUX35 - MUX35 */
#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_MASK)

#define PXP_WFE_B_STAGE3_MUX8_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX8_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX8_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX8_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_SHIFT    (0U)
/*! MUX32 - MUX32 */
#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_MASK)

#define PXP_WFE_B_STAGE3_MUX8_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX8_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX8_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_SHIFT    (8U)
/*! MUX33 - MUX33 */
#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_MASK)

#define PXP_WFE_B_STAGE3_MUX8_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX8_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX8_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_SHIFT    (16U)
/*! MUX34 - MUX34 */
#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_MASK)

#define PXP_WFE_B_STAGE3_MUX8_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX8_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX8_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_SHIFT    (24U)
/*! MUX35 - MUX35 */
#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_MASK)

#define PXP_WFE_B_STAGE3_MUX8_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX8_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX8_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX9 -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX9_MUX36_MASK         (0x3FU)
#define PXP_WFE_B_STAGE3_MUX9_MUX36_SHIFT        (0U)
/*! MUX36 - MUX36 */
#define PXP_WFE_B_STAGE3_MUX9_MUX36(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX36_MASK)

#define PXP_WFE_B_STAGE3_MUX9_RSVD3_MASK         (0xC0U)
#define PXP_WFE_B_STAGE3_MUX9_RSVD3_SHIFT        (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX9_RSVD3(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX9_MUX37_MASK         (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX9_MUX37_SHIFT        (8U)
/*! MUX37 - MUX37 */
#define PXP_WFE_B_STAGE3_MUX9_MUX37(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX37_MASK)

#define PXP_WFE_B_STAGE3_MUX9_RSVD2_MASK         (0xC000U)
#define PXP_WFE_B_STAGE3_MUX9_RSVD2_SHIFT        (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX9_RSVD2(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX9_MUX38_MASK         (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX9_MUX38_SHIFT        (16U)
/*! MUX38 - MUX38 */
#define PXP_WFE_B_STAGE3_MUX9_MUX38(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX38_MASK)

#define PXP_WFE_B_STAGE3_MUX9_RSVD1_MASK         (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX9_RSVD1_SHIFT        (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX9_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX9_MUX39_MASK         (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX9_MUX39_SHIFT        (24U)
/*! MUX39 - MUX39 */
#define PXP_WFE_B_STAGE3_MUX9_MUX39(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX39_MASK)

#define PXP_WFE_B_STAGE3_MUX9_RSVD0_MASK         (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX9_RSVD0_SHIFT        (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX9_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX9_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36_SHIFT    (0U)
/*! MUX36 - MUX36 */
#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX36_MASK)

#define PXP_WFE_B_STAGE3_MUX9_SET_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX9_SET_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX9_SET_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37_SHIFT    (8U)
/*! MUX37 - MUX37 */
#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX37_MASK)

#define PXP_WFE_B_STAGE3_MUX9_SET_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX9_SET_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX9_SET_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38_SHIFT    (16U)
/*! MUX38 - MUX38 */
#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX38_MASK)

#define PXP_WFE_B_STAGE3_MUX9_SET_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX9_SET_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX9_SET_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39_SHIFT    (24U)
/*! MUX39 - MUX39 */
#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX39_MASK)

#define PXP_WFE_B_STAGE3_MUX9_SET_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX9_SET_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX9_SET_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX9_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_SHIFT    (0U)
/*! MUX36 - MUX36 */
#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_MASK)

#define PXP_WFE_B_STAGE3_MUX9_CLR_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX9_CLR_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX9_CLR_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_SHIFT    (8U)
/*! MUX37 - MUX37 */
#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_MASK)

#define PXP_WFE_B_STAGE3_MUX9_CLR_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX9_CLR_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX9_CLR_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_SHIFT    (16U)
/*! MUX38 - MUX38 */
#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_MASK)

#define PXP_WFE_B_STAGE3_MUX9_CLR_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX9_CLR_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX9_CLR_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_SHIFT    (24U)
/*! MUX39 - MUX39 */
#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_MASK)

#define PXP_WFE_B_STAGE3_MUX9_CLR_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX9_CLR_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX9_CLR_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX9_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_MASK     (0x3FU)
#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_SHIFT    (0U)
/*! MUX36 - MUX36 */
#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_MASK)

#define PXP_WFE_B_STAGE3_MUX9_TOG_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STAGE3_MUX9_TOG_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX9_TOG_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_MASK     (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_SHIFT    (8U)
/*! MUX37 - MUX37 */
#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_MASK)

#define PXP_WFE_B_STAGE3_MUX9_TOG_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STAGE3_MUX9_TOG_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX9_TOG_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_MASK     (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_SHIFT    (16U)
/*! MUX38 - MUX38 */
#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_MASK)

#define PXP_WFE_B_STAGE3_MUX9_TOG_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX9_TOG_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX9_TOG_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_MASK     (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_SHIFT    (24U)
/*! MUX39 - MUX39 */
#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_MASK)

#define PXP_WFE_B_STAGE3_MUX9_TOG_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX9_TOG_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX9_TOG_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX10 -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX10_MUX40_MASK        (0x3FU)
#define PXP_WFE_B_STAGE3_MUX10_MUX40_SHIFT       (0U)
/*! MUX40 - MUX40 */
#define PXP_WFE_B_STAGE3_MUX10_MUX40(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX40_MASK)

#define PXP_WFE_B_STAGE3_MUX10_RSVD3_MASK        (0xC0U)
#define PXP_WFE_B_STAGE3_MUX10_RSVD3_SHIFT       (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX10_RSVD3(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX10_MUX41_MASK        (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX10_MUX41_SHIFT       (8U)
/*! MUX41 - MUX41 */
#define PXP_WFE_B_STAGE3_MUX10_MUX41(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX41_MASK)

#define PXP_WFE_B_STAGE3_MUX10_RSVD2_MASK        (0xC000U)
#define PXP_WFE_B_STAGE3_MUX10_RSVD2_SHIFT       (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX10_RSVD2(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX10_MUX42_MASK        (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX10_MUX42_SHIFT       (16U)
/*! MUX42 - MUX42 */
#define PXP_WFE_B_STAGE3_MUX10_MUX42(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX42_MASK)

#define PXP_WFE_B_STAGE3_MUX10_RSVD1_MASK        (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX10_RSVD1_SHIFT       (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX10_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX10_MUX43_MASK        (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX10_MUX43_SHIFT       (24U)
/*! MUX43 - MUX43 */
#define PXP_WFE_B_STAGE3_MUX10_MUX43(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX43_MASK)

#define PXP_WFE_B_STAGE3_MUX10_RSVD0_MASK        (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX10_RSVD0_SHIFT       (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX10_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX10_SET -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40_MASK    (0x3FU)
#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40_SHIFT   (0U)
/*! MUX40 - MUX40 */
#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX40_MASK)

#define PXP_WFE_B_STAGE3_MUX10_SET_RSVD3_MASK    (0xC0U)
#define PXP_WFE_B_STAGE3_MUX10_SET_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX10_SET_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41_MASK    (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41_SHIFT   (8U)
/*! MUX41 - MUX41 */
#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX41_MASK)

#define PXP_WFE_B_STAGE3_MUX10_SET_RSVD2_MASK    (0xC000U)
#define PXP_WFE_B_STAGE3_MUX10_SET_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX10_SET_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42_MASK    (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42_SHIFT   (16U)
/*! MUX42 - MUX42 */
#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX42_MASK)

#define PXP_WFE_B_STAGE3_MUX10_SET_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX10_SET_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX10_SET_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43_MASK    (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43_SHIFT   (24U)
/*! MUX43 - MUX43 */
#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX43_MASK)

#define PXP_WFE_B_STAGE3_MUX10_SET_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX10_SET_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX10_SET_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX10_CLR -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_MASK    (0x3FU)
#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_SHIFT   (0U)
/*! MUX40 - MUX40 */
#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_MASK)

#define PXP_WFE_B_STAGE3_MUX10_CLR_RSVD3_MASK    (0xC0U)
#define PXP_WFE_B_STAGE3_MUX10_CLR_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX10_CLR_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_MASK    (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_SHIFT   (8U)
/*! MUX41 - MUX41 */
#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_MASK)

#define PXP_WFE_B_STAGE3_MUX10_CLR_RSVD2_MASK    (0xC000U)
#define PXP_WFE_B_STAGE3_MUX10_CLR_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX10_CLR_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_MASK    (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_SHIFT   (16U)
/*! MUX42 - MUX42 */
#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_MASK)

#define PXP_WFE_B_STAGE3_MUX10_CLR_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX10_CLR_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX10_CLR_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_MASK    (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_SHIFT   (24U)
/*! MUX43 - MUX43 */
#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_MASK)

#define PXP_WFE_B_STAGE3_MUX10_CLR_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX10_CLR_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX10_CLR_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE3_MUX10_TOG -  */
/*! @{ */

#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_MASK    (0x3FU)
#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_SHIFT   (0U)
/*! MUX40 - MUX40 */
#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_MASK)

#define PXP_WFE_B_STAGE3_MUX10_TOG_RSVD3_MASK    (0xC0U)
#define PXP_WFE_B_STAGE3_MUX10_TOG_RSVD3_SHIFT   (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE3_MUX10_TOG_RSVD3(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_RSVD3_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_RSVD3_MASK)

#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_MASK    (0x3F00U)
#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_SHIFT   (8U)
/*! MUX41 - MUX41 */
#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_MASK)

#define PXP_WFE_B_STAGE3_MUX10_TOG_RSVD2_MASK    (0xC000U)
#define PXP_WFE_B_STAGE3_MUX10_TOG_RSVD2_SHIFT   (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE3_MUX10_TOG_RSVD2(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_RSVD2_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_RSVD2_MASK)

#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_MASK    (0x3F0000U)
#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_SHIFT   (16U)
/*! MUX42 - MUX42 */
#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_MASK)

#define PXP_WFE_B_STAGE3_MUX10_TOG_RSVD1_MASK    (0xC00000U)
#define PXP_WFE_B_STAGE3_MUX10_TOG_RSVD1_SHIFT   (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE3_MUX10_TOG_RSVD1(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_RSVD1_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_RSVD1_MASK)

#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_MASK    (0x3F000000U)
#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_SHIFT   (24U)
/*! MUX43 - MUX43 */
#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_MASK)

#define PXP_WFE_B_STAGE3_MUX10_TOG_RSVD0_MASK    (0xC0000000U)
#define PXP_WFE_B_STAGE3_MUX10_TOG_RSVD0_SHIFT   (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE3_MUX10_TOG_RSVD0(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_RSVD0_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT0_0 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_MASK   (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_MASK   (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_SHIFT  (8U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_MASK   (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_SHIFT  (16U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_MASK   (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_SHIFT  (24U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT0_1 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_MASK   (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_SHIFT  (0U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_MASK   (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_SHIFT  (8U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_MASK   (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_SHIFT  (16U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_MASK   (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_SHIFT  (24U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT0_2 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_MASK   (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_SHIFT  (0U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_MASK   (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_SHIFT  (8U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_MASK  (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_SHIFT (16U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_MASK  (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_SHIFT (24U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT0_3 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_MASK  (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_SHIFT (0U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_MASK  (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_SHIFT (8U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_MASK  (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_SHIFT (16U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_MASK  (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_SHIFT (24U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT0_4 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_MASK  (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_SHIFT (0U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_MASK  (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_SHIFT (8U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_MASK  (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_SHIFT (16U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_MASK  (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_SHIFT (24U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT0_5 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_MASK  (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_SHIFT (0U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_MASK  (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_SHIFT (8U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_MASK  (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_SHIFT (16U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_MASK  (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_SHIFT (24U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT0_6 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_MASK  (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_SHIFT (0U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_MASK  (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_SHIFT (8U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_MASK  (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_SHIFT (16U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_MASK  (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_SHIFT (24U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT0_7 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_MASK  (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_SHIFT (0U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_MASK  (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_SHIFT (8U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_MASK  (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_SHIFT (16U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_MASK)

#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_MASK  (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_SHIFT (24U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT1_0 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_MASK   (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_MASK   (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_SHIFT  (8U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_MASK   (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_SHIFT  (16U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_MASK   (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_SHIFT  (24U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT1_1 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_MASK   (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_SHIFT  (0U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_MASK   (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_SHIFT  (8U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_MASK   (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_SHIFT  (16U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_MASK   (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_SHIFT  (24U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT1_2 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_MASK   (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_SHIFT  (0U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_MASK   (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_SHIFT  (8U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_MASK  (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_SHIFT (16U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_MASK  (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_SHIFT (24U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT1_3 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_MASK  (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_SHIFT (0U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_MASK  (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_SHIFT (8U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_MASK  (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_SHIFT (16U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_MASK  (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_SHIFT (24U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT1_4 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_MASK  (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_SHIFT (0U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_MASK  (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_SHIFT (8U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_MASK  (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_SHIFT (16U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_MASK  (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_SHIFT (24U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT1_5 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_MASK  (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_SHIFT (0U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_MASK  (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_SHIFT (8U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_MASK  (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_SHIFT (16U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_MASK  (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_SHIFT (24U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT1_6 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_MASK  (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_SHIFT (0U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_MASK  (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_SHIFT (8U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_MASK  (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_SHIFT (16U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_MASK  (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_SHIFT (24U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X8_OUT1_7 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_MASK  (0xFFU)
#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_SHIFT (0U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_MASK  (0xFF00U)
#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_SHIFT (8U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_MASK  (0xFF0000U)
#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_SHIFT (16U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_MASK)

#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_MASK  (0xFF000000U)
#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_SHIFT (24U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STAGE1_5X8_MASKS_0 -  */
/*! @{ */

#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_MASK  (0x1FU)
#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_SHIFT (0U)
/*! MASK0 - MASK0 */
#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_SHIFT)) & PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_MASK)

#define PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3_MASK  (0xE0U)
#define PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3_SHIFT (5U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3_SHIFT)) & PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3_MASK)

#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_MASK  (0x1F00U)
#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_SHIFT (8U)
/*! MASK1 - MASK1 */
#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_SHIFT)) & PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_MASK)

#define PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2_MASK  (0xFFFFE000U)
#define PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2_SHIFT (13U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2_SHIFT)) & PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X1_OUT0 -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_MASK     (0x1U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_SHIFT    (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_MASK     (0x2U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_SHIFT    (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_MASK     (0x4U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_SHIFT    (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_MASK     (0x8U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_SHIFT    (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_MASK     (0x10U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_SHIFT    (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_MASK     (0x20U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_SHIFT    (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_MASK     (0x40U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_SHIFT    (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_MASK     (0x80U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_SHIFT    (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_MASK     (0x100U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_SHIFT    (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_MASK     (0x200U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_SHIFT    (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_MASK    (0x400U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_SHIFT   (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_MASK    (0x800U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_SHIFT   (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_MASK    (0x1000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_SHIFT   (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_MASK    (0x2000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_SHIFT   (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_MASK    (0x4000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_SHIFT   (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_MASK    (0x8000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_SHIFT   (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_MASK    (0x10000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_SHIFT   (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_MASK    (0x20000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_SHIFT   (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_MASK    (0x40000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_SHIFT   (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_MASK    (0x80000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_SHIFT   (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_MASK    (0x100000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_SHIFT   (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_MASK    (0x200000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_SHIFT   (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_MASK    (0x400000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_SHIFT   (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_MASK    (0x800000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_SHIFT   (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_MASK    (0x1000000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_SHIFT   (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_MASK    (0x2000000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_SHIFT   (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_MASK    (0x4000000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_SHIFT   (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_MASK    (0x8000000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_SHIFT   (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_MASK    (0x10000000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_SHIFT   (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_MASK    (0x20000000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_SHIFT   (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_MASK    (0x40000000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_SHIFT   (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_MASK)

#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_MASK    (0x80000000U)
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_SHIFT   (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG1_5X1_MASKS -  */
/*! @{ */

#define PXP_WFE_B_STG1_5X1_MASKS_MASK0_MASK      (0x1FU)
#define PXP_WFE_B_STG1_5X1_MASKS_MASK0_SHIFT     (0U)
/*! MASK0 - MASK0 */
#define PXP_WFE_B_STG1_5X1_MASKS_MASK0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG1_5X1_MASKS_MASK0_MASK)

#define PXP_WFE_B_STG1_5X1_MASKS_RSVD0_MASK      (0xFFFFFFE0U)
#define PXP_WFE_B_STG1_5X1_MASKS_RSVD0_SHIFT     (5U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG1_5X1_MASKS_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_MASKS_RSVD0_SHIFT)) & PXP_WFE_B_STG1_5X1_MASKS_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT0_0 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_MASK   (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_MASK   (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_SHIFT  (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_MASK   (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_SHIFT  (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_MASK   (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_SHIFT  (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_MASK   (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_SHIFT  (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_MASK   (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_SHIFT  (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_MASK   (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_SHIFT  (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_MASK   (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_SHIFT  (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_MASK   (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_SHIFT  (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_MASK   (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_SHIFT  (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_SHIFT (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_SHIFT (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_SHIFT (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_SHIFT (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_SHIFT (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_SHIFT (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_SHIFT (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_SHIFT (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_SHIFT (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_SHIFT (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_SHIFT (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_SHIFT (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_SHIFT (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_SHIFT (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_SHIFT (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_SHIFT (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_SHIFT (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_SHIFT (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_SHIFT (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_SHIFT (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_SHIFT (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_SHIFT (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT0_1 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_SHIFT (0U)
/*! LUTOUT32 - LUTOUT32 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_SHIFT (1U)
/*! LUTOUT33 - LUTOUT33 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_SHIFT (2U)
/*! LUTOUT34 - LUTOUT34 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_SHIFT (3U)
/*! LUTOUT35 - LUTOUT35 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_MASK  (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_SHIFT (4U)
/*! LUTOUT36 - LUTOUT36 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_MASK  (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_SHIFT (5U)
/*! LUTOUT37 - LUTOUT37 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_MASK  (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_SHIFT (6U)
/*! LUTOUT38 - LUTOUT38 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_MASK  (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_SHIFT (7U)
/*! LUTOUT39 - LUTOUT39 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_MASK  (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_SHIFT (8U)
/*! LUTOUT40 - LUTOUT40 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_MASK  (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_SHIFT (9U)
/*! LUTOUT41 - LUTOUT41 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_SHIFT (10U)
/*! LUTOUT42 - LUTOUT42 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_SHIFT (11U)
/*! LUTOUT43 - LUTOUT43 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_SHIFT (12U)
/*! LUTOUT44 - LUTOUT44 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_SHIFT (13U)
/*! LUTOUT45 - LUTOUT45 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_SHIFT (14U)
/*! LUTOUT46 - LUTOUT46 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_SHIFT (15U)
/*! LUTOUT47 - LUTOUT47 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_SHIFT (16U)
/*! LUTOUT48 - LUTOUT48 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_SHIFT (17U)
/*! LUTOUT49 - LUTOUT49 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_SHIFT (18U)
/*! LUTOUT50 - LUTOUT50 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_SHIFT (19U)
/*! LUTOUT51 - LUTOUT51 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_SHIFT (20U)
/*! LUTOUT52 - LUTOUT52 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_SHIFT (21U)
/*! LUTOUT53 - LUTOUT53 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_SHIFT (22U)
/*! LUTOUT54 - LUTOUT54 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_SHIFT (23U)
/*! LUTOUT55 - LUTOUT55 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_SHIFT (24U)
/*! LUTOUT56 - LUTOUT56 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_SHIFT (25U)
/*! LUTOUT57 - LUTOUT57 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_SHIFT (26U)
/*! LUTOUT58 - LUTOUT58 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_SHIFT (27U)
/*! LUTOUT59 - LUTOUT59 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_SHIFT (28U)
/*! LUTOUT60 - LUTOUT60 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_SHIFT (29U)
/*! LUTOUT61 - LUTOUT61 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_SHIFT (30U)
/*! LUTOUT62 - LUTOUT62 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_SHIFT (31U)
/*! LUTOUT63 - LUTOUT63 */
#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT0_2 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_SHIFT (0U)
/*! LUTOUT64 - LUTOUT64 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_SHIFT (1U)
/*! LUTOUT65 - LUTOUT65 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_SHIFT (2U)
/*! LUTOUT66 - LUTOUT66 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_SHIFT (3U)
/*! LUTOUT67 - LUTOUT67 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_MASK  (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_SHIFT (4U)
/*! LUTOUT68 - LUTOUT68 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_MASK  (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_SHIFT (5U)
/*! LUTOUT69 - LUTOUT69 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_MASK  (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_SHIFT (6U)
/*! LUTOUT70 - LUTOUT70 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_MASK  (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_SHIFT (7U)
/*! LUTOUT71 - LUTOUT71 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_MASK  (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_SHIFT (8U)
/*! LUTOUT72 - LUTOUT72 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_MASK  (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_SHIFT (9U)
/*! LUTOUT73 - LUTOUT73 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_SHIFT (10U)
/*! LUTOUT74 - LUTOUT74 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_SHIFT (11U)
/*! LUTOUT75 - LUTOUT75 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_SHIFT (12U)
/*! LUTOUT76 - LUTOUT76 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_SHIFT (13U)
/*! LUTOUT77 - LUTOUT77 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_SHIFT (14U)
/*! LUTOUT78 - LUTOUT78 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_SHIFT (15U)
/*! LUTOUT79 - LUTOUT79 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_SHIFT (16U)
/*! LUTOUT80 - LUTOUT80 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_SHIFT (17U)
/*! LUTOUT81 - LUTOUT81 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_SHIFT (18U)
/*! LUTOUT82 - LUTOUT82 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_SHIFT (19U)
/*! LUTOUT83 - LUTOUT83 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_SHIFT (20U)
/*! LUTOUT84 - LUTOUT84 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_SHIFT (21U)
/*! LUTOUT85 - LUTOUT85 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_SHIFT (22U)
/*! LUTOUT86 - LUTOUT86 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_SHIFT (23U)
/*! LUTOUT87 - LUTOUT87 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_SHIFT (24U)
/*! LUTOUT88 - LUTOUT88 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_SHIFT (25U)
/*! LUTOUT89 - LUTOUT89 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_SHIFT (26U)
/*! LUTOUT90 - LUTOUT90 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_SHIFT (27U)
/*! LUTOUT91 - LUTOUT91 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_SHIFT (28U)
/*! LUTOUT92 - LUTOUT92 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_SHIFT (29U)
/*! LUTOUT93 - LUTOUT93 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_SHIFT (30U)
/*! LUTOUT94 - LUTOUT94 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_SHIFT (31U)
/*! LUTOUT95 - LUTOUT95 */
#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT0_3 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_SHIFT (0U)
/*! LUTOUT96 - LUTOUT96 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_SHIFT (1U)
/*! LUTOUT97 - LUTOUT97 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_SHIFT (2U)
/*! LUTOUT98 - LUTOUT98 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_SHIFT (3U)
/*! LUTOUT99 - LUTOUT99 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_SHIFT (4U)
/*! LUTOUT100 - LUTOUT100 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_SHIFT (5U)
/*! LUTOUT101 - LUTOUT101 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_SHIFT (6U)
/*! LUTOUT102 - LUTOUT102 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_SHIFT (7U)
/*! LUTOUT103 - LUTOUT103 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_SHIFT (8U)
/*! LUTOUT104 - LUTOUT104 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_SHIFT (9U)
/*! LUTOUT105 - LUTOUT105 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_SHIFT (10U)
/*! LUTOUT106 - LUTOUT106 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_SHIFT (11U)
/*! LUTOUT107 - LUTOUT107 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_SHIFT (12U)
/*! LUTOUT108 - LUTOUT108 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_SHIFT (13U)
/*! LUTOUT109 - LUTOUT109 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_SHIFT (14U)
/*! LUTOUT110 - LUTOUT110 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_SHIFT (15U)
/*! LUTOUT111 - LUTOUT111 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_SHIFT (16U)
/*! LUTOUT112 - LUTOUT112 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_SHIFT (17U)
/*! LUTOUT113 - LUTOUT113 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_SHIFT (18U)
/*! LUTOUT114 - LUTOUT114 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_SHIFT (19U)
/*! LUTOUT115 - LUTOUT115 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_SHIFT (20U)
/*! LUTOUT116 - LUTOUT116 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_SHIFT (21U)
/*! LUTOUT117 - LUTOUT117 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_SHIFT (22U)
/*! LUTOUT118 - LUTOUT118 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_SHIFT (23U)
/*! LUTOUT119 - LUTOUT119 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_SHIFT (24U)
/*! LUTOUT120 - LUTOUT120 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_SHIFT (25U)
/*! LUTOUT121 - LUTOUT121 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_SHIFT (26U)
/*! LUTOUT122 - LUTOUT122 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_SHIFT (27U)
/*! LUTOUT123 - LUTOUT123 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_SHIFT (28U)
/*! LUTOUT124 - LUTOUT124 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_SHIFT (29U)
/*! LUTOUT125 - LUTOUT125 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_SHIFT (30U)
/*! LUTOUT126 - LUTOUT126 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_SHIFT (31U)
/*! LUTOUT127 - LUTOUT127 */
#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT0_4 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_SHIFT (0U)
/*! LUTOUT128 - LUTOUT128 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_SHIFT (1U)
/*! LUTOUT129 - LUTOUT129 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_SHIFT (2U)
/*! LUTOUT130 - LUTOUT130 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_SHIFT (3U)
/*! LUTOUT131 - LUTOUT131 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_SHIFT (4U)
/*! LUTOUT132 - LUTOUT132 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_SHIFT (5U)
/*! LUTOUT133 - LUTOUT133 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_SHIFT (6U)
/*! LUTOUT134 - LUTOUT134 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_SHIFT (7U)
/*! LUTOUT135 - LUTOUT135 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_SHIFT (8U)
/*! LUTOUT136 - LUTOUT136 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_SHIFT (9U)
/*! LUTOUT137 - LUTOUT137 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_SHIFT (10U)
/*! LUTOUT138 - LUTOUT138 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_SHIFT (11U)
/*! LUTOUT139 - LUTOUT139 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_SHIFT (12U)
/*! LUTOUT140 - LUTOUT140 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_SHIFT (13U)
/*! LUTOUT141 - LUTOUT141 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_SHIFT (14U)
/*! LUTOUT142 - LUTOUT142 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_SHIFT (15U)
/*! LUTOUT143 - LUTOUT143 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_SHIFT (16U)
/*! LUTOUT144 - LUTOUT144 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_SHIFT (17U)
/*! LUTOUT145 - LUTOUT145 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_SHIFT (18U)
/*! LUTOUT146 - LUTOUT146 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_SHIFT (19U)
/*! LUTOUT147 - LUTOUT147 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_SHIFT (20U)
/*! LUTOUT148 - LUTOUT148 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_SHIFT (21U)
/*! LUTOUT149 - LUTOUT149 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_SHIFT (22U)
/*! LUTOUT150 - LUTOUT150 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_SHIFT (23U)
/*! LUTOUT151 - LUTOUT151 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_SHIFT (24U)
/*! LUTOUT152 - LUTOUT152 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_SHIFT (25U)
/*! LUTOUT153 - LUTOUT153 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_SHIFT (26U)
/*! LUTOUT154 - LUTOUT154 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_SHIFT (27U)
/*! LUTOUT155 - LUTOUT155 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_SHIFT (28U)
/*! LUTOUT156 - LUTOUT156 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_SHIFT (29U)
/*! LUTOUT157 - LUTOUT157 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_SHIFT (30U)
/*! LUTOUT158 - LUTOUT158 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_SHIFT (31U)
/*! LUTOUT159 - LUTOUT159 */
#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT0_5 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_SHIFT (0U)
/*! LUTOUT160 - LUTOUT160 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_SHIFT (1U)
/*! LUTOUT161 - LUTOUT161 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_SHIFT (2U)
/*! LUTOUT162 - LUTOUT162 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_SHIFT (3U)
/*! LUTOUT163 - LUTOUT163 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_SHIFT (4U)
/*! LUTOUT164 - LUTOUT164 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_SHIFT (5U)
/*! LUTOUT165 - LUTOUT165 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_SHIFT (6U)
/*! LUTOUT166 - LUTOUT166 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_SHIFT (7U)
/*! LUTOUT167 - LUTOUT167 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_SHIFT (8U)
/*! LUTOUT168 - LUTOUT168 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_SHIFT (9U)
/*! LUTOUT169 - LUTOUT169 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_SHIFT (10U)
/*! LUTOUT170 - LUTOUT170 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_SHIFT (11U)
/*! LUTOUT171 - LUTOUT171 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_SHIFT (12U)
/*! LUTOUT172 - LUTOUT172 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_SHIFT (13U)
/*! LUTOUT173 - LUTOUT173 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_SHIFT (14U)
/*! LUTOUT174 - LUTOUT174 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_SHIFT (15U)
/*! LUTOUT175 - LUTOUT175 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_SHIFT (16U)
/*! LUTOUT176 - LUTOUT176 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_SHIFT (17U)
/*! LUTOUT177 - LUTOUT177 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_SHIFT (18U)
/*! LUTOUT178 - LUTOUT178 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_SHIFT (19U)
/*! LUTOUT179 - LUTOUT179 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_SHIFT (20U)
/*! LUTOUT180 - LUTOUT180 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_SHIFT (21U)
/*! LUTOUT181 - LUTOUT181 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_SHIFT (22U)
/*! LUTOUT182 - LUTOUT182 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_SHIFT (23U)
/*! LUTOUT183 - LUTOUT183 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_SHIFT (24U)
/*! LUTOUT184 - LUTOUT184 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_SHIFT (25U)
/*! LUTOUT185 - LUTOUT185 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_SHIFT (26U)
/*! LUTOUT186 - LUTOUT186 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_SHIFT (27U)
/*! LUTOUT187 - LUTOUT187 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_SHIFT (28U)
/*! LUTOUT188 - LUTOUT188 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_SHIFT (29U)
/*! LUTOUT189 - LUTOUT189 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_SHIFT (30U)
/*! LUTOUT190 - LUTOUT190 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_SHIFT (31U)
/*! LUTOUT191 - LUTOUT191 */
#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT0_6 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_SHIFT (0U)
/*! LUTOUT192 - LUTOUT192 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_SHIFT (1U)
/*! LUTOUT193 - LUTOUT193 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_SHIFT (2U)
/*! LUTOUT194 - LUTOUT194 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_SHIFT (3U)
/*! LUTOUT195 - LUTOUT195 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_SHIFT (4U)
/*! LUTOUT196 - LUTOUT196 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_SHIFT (5U)
/*! LUTOUT197 - LUTOUT197 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_SHIFT (6U)
/*! LUTOUT198 - LUTOUT198 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_SHIFT (7U)
/*! LUTOUT199 - LUTOUT199 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_SHIFT (8U)
/*! LUTOUT200 - LUTOUT200 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_SHIFT (9U)
/*! LUTOUT201 - LUTOUT201 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_SHIFT (10U)
/*! LUTOUT202 - LUTOUT202 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_SHIFT (11U)
/*! LUTOUT203 - LUTOUT203 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_SHIFT (12U)
/*! LUTOUT204 - LUTOUT204 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_SHIFT (13U)
/*! LUTOUT205 - LUTOUT205 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_SHIFT (14U)
/*! LUTOUT206 - LUTOUT206 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_SHIFT (15U)
/*! LUTOUT207 - LUTOUT207 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_SHIFT (16U)
/*! LUTOUT208 - LUTOUT208 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_SHIFT (17U)
/*! LUTOUT209 - LUTOUT209 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_SHIFT (18U)
/*! LUTOUT210 - LUTOUT210 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_SHIFT (19U)
/*! LUTOUT211 - LUTOUT211 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_SHIFT (20U)
/*! LUTOUT212 - LUTOUT212 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_SHIFT (21U)
/*! LUTOUT213 - LUTOUT213 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_SHIFT (22U)
/*! LUTOUT214 - LUTOUT214 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_SHIFT (23U)
/*! LUTOUT215 - LUTOUT215 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_SHIFT (24U)
/*! LUTOUT216 - LUTOUT216 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_SHIFT (25U)
/*! LUTOUT217 - LUTOUT217 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_SHIFT (26U)
/*! LUTOUT218 - LUTOUT218 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_SHIFT (27U)
/*! LUTOUT219 - LUTOUT219 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_SHIFT (28U)
/*! LUTOUT220 - LUTOUT220 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_SHIFT (29U)
/*! LUTOUT221 - LUTOUT221 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_SHIFT (30U)
/*! LUTOUT222 - LUTOUT222 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_SHIFT (31U)
/*! LUTOUT223 - LUTOUT223 */
#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT0_7 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_SHIFT (0U)
/*! LUTOUT224 - LUTOUT224 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_SHIFT (1U)
/*! LUTOUT225 - LUTOUT225 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_SHIFT (2U)
/*! LUTOUT226 - LUTOUT226 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_SHIFT (3U)
/*! LUTOUT227 - LUTOUT227 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_SHIFT (4U)
/*! LUTOUT228 - LUTOUT228 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_SHIFT (5U)
/*! LUTOUT229 - LUTOUT229 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_SHIFT (6U)
/*! LUTOUT230 - LUTOUT230 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_SHIFT (7U)
/*! LUTOUT231 - LUTOUT231 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_SHIFT (8U)
/*! LUTOUT232 - LUTOUT232 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_SHIFT (9U)
/*! LUTOUT233 - LUTOUT233 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_SHIFT (10U)
/*! LUTOUT234 - LUTOUT234 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_SHIFT (11U)
/*! LUTOUT235 - LUTOUT235 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_SHIFT (12U)
/*! LUTOUT236 - LUTOUT236 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_SHIFT (13U)
/*! LUTOUT237 - LUTOUT237 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_SHIFT (14U)
/*! LUTOUT238 - LUTOUT238 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_SHIFT (15U)
/*! LUTOUT239 - LUTOUT239 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_SHIFT (16U)
/*! LUTOUT240 - LUTOUT240 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_SHIFT (17U)
/*! LUTOUT241 - LUTOUT241 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_SHIFT (18U)
/*! LUTOUT242 - LUTOUT242 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_SHIFT (19U)
/*! LUTOUT243 - LUTOUT243 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_SHIFT (20U)
/*! LUTOUT244 - LUTOUT244 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_SHIFT (21U)
/*! LUTOUT245 - LUTOUT245 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_SHIFT (22U)
/*! LUTOUT246 - LUTOUT246 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_SHIFT (23U)
/*! LUTOUT247 - LUTOUT247 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_SHIFT (24U)
/*! LUTOUT248 - LUTOUT248 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_SHIFT (25U)
/*! LUTOUT249 - LUTOUT249 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_SHIFT (26U)
/*! LUTOUT250 - LUTOUT250 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_SHIFT (27U)
/*! LUTOUT251 - LUTOUT251 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_SHIFT (28U)
/*! LUTOUT252 - LUTOUT252 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_SHIFT (29U)
/*! LUTOUT253 - LUTOUT253 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_SHIFT (30U)
/*! LUTOUT254 - LUTOUT254 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_MASK)

#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_SHIFT (31U)
/*! LUTOUT255 - LUTOUT255 */
#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT1_0 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_MASK   (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_MASK   (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_SHIFT  (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_MASK   (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_SHIFT  (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_MASK   (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_SHIFT  (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_MASK   (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_SHIFT  (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_MASK   (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_SHIFT  (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_MASK   (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_SHIFT  (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_MASK   (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_SHIFT  (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_MASK   (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_SHIFT  (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_MASK   (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_SHIFT  (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_SHIFT (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_SHIFT (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_SHIFT (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_SHIFT (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_SHIFT (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_SHIFT (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_SHIFT (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_SHIFT (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_SHIFT (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_SHIFT (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_SHIFT (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_SHIFT (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_SHIFT (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_SHIFT (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_SHIFT (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_SHIFT (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_SHIFT (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_SHIFT (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_SHIFT (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_SHIFT (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_SHIFT (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_SHIFT (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT1_1 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_SHIFT (0U)
/*! LUTOUT32 - LUTOUT32 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_SHIFT (1U)
/*! LUTOUT33 - LUTOUT33 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_SHIFT (2U)
/*! LUTOUT34 - LUTOUT34 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_SHIFT (3U)
/*! LUTOUT35 - LUTOUT35 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_MASK  (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_SHIFT (4U)
/*! LUTOUT36 - LUTOUT36 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_MASK  (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_SHIFT (5U)
/*! LUTOUT37 - LUTOUT37 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_MASK  (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_SHIFT (6U)
/*! LUTOUT38 - LUTOUT38 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_MASK  (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_SHIFT (7U)
/*! LUTOUT39 - LUTOUT39 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_MASK  (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_SHIFT (8U)
/*! LUTOUT40 - LUTOUT40 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_MASK  (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_SHIFT (9U)
/*! LUTOUT41 - LUTOUT41 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_SHIFT (10U)
/*! LUTOUT42 - LUTOUT42 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_SHIFT (11U)
/*! LUTOUT43 - LUTOUT43 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_SHIFT (12U)
/*! LUTOUT44 - LUTOUT44 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_SHIFT (13U)
/*! LUTOUT45 - LUTOUT45 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_SHIFT (14U)
/*! LUTOUT46 - LUTOUT46 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_SHIFT (15U)
/*! LUTOUT47 - LUTOUT47 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_SHIFT (16U)
/*! LUTOUT48 - LUTOUT48 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_SHIFT (17U)
/*! LUTOUT49 - LUTOUT49 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_SHIFT (18U)
/*! LUTOUT50 - LUTOUT50 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_SHIFT (19U)
/*! LUTOUT51 - LUTOUT51 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_SHIFT (20U)
/*! LUTOUT52 - LUTOUT52 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_SHIFT (21U)
/*! LUTOUT53 - LUTOUT53 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_SHIFT (22U)
/*! LUTOUT54 - LUTOUT54 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_SHIFT (23U)
/*! LUTOUT55 - LUTOUT55 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_SHIFT (24U)
/*! LUTOUT56 - LUTOUT56 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_SHIFT (25U)
/*! LUTOUT57 - LUTOUT57 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_SHIFT (26U)
/*! LUTOUT58 - LUTOUT58 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_SHIFT (27U)
/*! LUTOUT59 - LUTOUT59 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_SHIFT (28U)
/*! LUTOUT60 - LUTOUT60 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_SHIFT (29U)
/*! LUTOUT61 - LUTOUT61 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_SHIFT (30U)
/*! LUTOUT62 - LUTOUT62 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_SHIFT (31U)
/*! LUTOUT63 - LUTOUT63 */
#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT1_2 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_SHIFT (0U)
/*! LUTOUT64 - LUTOUT64 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_SHIFT (1U)
/*! LUTOUT65 - LUTOUT65 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_SHIFT (2U)
/*! LUTOUT66 - LUTOUT66 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_SHIFT (3U)
/*! LUTOUT67 - LUTOUT67 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_MASK  (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_SHIFT (4U)
/*! LUTOUT68 - LUTOUT68 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_MASK  (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_SHIFT (5U)
/*! LUTOUT69 - LUTOUT69 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_MASK  (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_SHIFT (6U)
/*! LUTOUT70 - LUTOUT70 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_MASK  (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_SHIFT (7U)
/*! LUTOUT71 - LUTOUT71 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_MASK  (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_SHIFT (8U)
/*! LUTOUT72 - LUTOUT72 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_MASK  (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_SHIFT (9U)
/*! LUTOUT73 - LUTOUT73 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_SHIFT (10U)
/*! LUTOUT74 - LUTOUT74 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_SHIFT (11U)
/*! LUTOUT75 - LUTOUT75 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_SHIFT (12U)
/*! LUTOUT76 - LUTOUT76 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_SHIFT (13U)
/*! LUTOUT77 - LUTOUT77 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_SHIFT (14U)
/*! LUTOUT78 - LUTOUT78 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_SHIFT (15U)
/*! LUTOUT79 - LUTOUT79 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_SHIFT (16U)
/*! LUTOUT80 - LUTOUT80 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_SHIFT (17U)
/*! LUTOUT81 - LUTOUT81 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_SHIFT (18U)
/*! LUTOUT82 - LUTOUT82 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_SHIFT (19U)
/*! LUTOUT83 - LUTOUT83 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_SHIFT (20U)
/*! LUTOUT84 - LUTOUT84 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_SHIFT (21U)
/*! LUTOUT85 - LUTOUT85 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_SHIFT (22U)
/*! LUTOUT86 - LUTOUT86 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_SHIFT (23U)
/*! LUTOUT87 - LUTOUT87 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_SHIFT (24U)
/*! LUTOUT88 - LUTOUT88 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_SHIFT (25U)
/*! LUTOUT89 - LUTOUT89 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_SHIFT (26U)
/*! LUTOUT90 - LUTOUT90 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_SHIFT (27U)
/*! LUTOUT91 - LUTOUT91 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_SHIFT (28U)
/*! LUTOUT92 - LUTOUT92 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_SHIFT (29U)
/*! LUTOUT93 - LUTOUT93 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_SHIFT (30U)
/*! LUTOUT94 - LUTOUT94 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_SHIFT (31U)
/*! LUTOUT95 - LUTOUT95 */
#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT1_3 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_SHIFT (0U)
/*! LUTOUT96 - LUTOUT96 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_SHIFT (1U)
/*! LUTOUT97 - LUTOUT97 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_SHIFT (2U)
/*! LUTOUT98 - LUTOUT98 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_SHIFT (3U)
/*! LUTOUT99 - LUTOUT99 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_SHIFT (4U)
/*! LUTOUT100 - LUTOUT100 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_SHIFT (5U)
/*! LUTOUT101 - LUTOUT101 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_SHIFT (6U)
/*! LUTOUT102 - LUTOUT102 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_SHIFT (7U)
/*! LUTOUT103 - LUTOUT103 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_SHIFT (8U)
/*! LUTOUT104 - LUTOUT104 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_SHIFT (9U)
/*! LUTOUT105 - LUTOUT105 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_SHIFT (10U)
/*! LUTOUT106 - LUTOUT106 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_SHIFT (11U)
/*! LUTOUT107 - LUTOUT107 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_SHIFT (12U)
/*! LUTOUT108 - LUTOUT108 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_SHIFT (13U)
/*! LUTOUT109 - LUTOUT109 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_SHIFT (14U)
/*! LUTOUT110 - LUTOUT110 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_SHIFT (15U)
/*! LUTOUT111 - LUTOUT111 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_SHIFT (16U)
/*! LUTOUT112 - LUTOUT112 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_SHIFT (17U)
/*! LUTOUT113 - LUTOUT113 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_SHIFT (18U)
/*! LUTOUT114 - LUTOUT114 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_SHIFT (19U)
/*! LUTOUT115 - LUTOUT115 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_SHIFT (20U)
/*! LUTOUT116 - LUTOUT116 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_SHIFT (21U)
/*! LUTOUT117 - LUTOUT117 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_SHIFT (22U)
/*! LUTOUT118 - LUTOUT118 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_SHIFT (23U)
/*! LUTOUT119 - LUTOUT119 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_SHIFT (24U)
/*! LUTOUT120 - LUTOUT120 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_SHIFT (25U)
/*! LUTOUT121 - LUTOUT121 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_SHIFT (26U)
/*! LUTOUT122 - LUTOUT122 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_SHIFT (27U)
/*! LUTOUT123 - LUTOUT123 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_SHIFT (28U)
/*! LUTOUT124 - LUTOUT124 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_SHIFT (29U)
/*! LUTOUT125 - LUTOUT125 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_SHIFT (30U)
/*! LUTOUT126 - LUTOUT126 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_SHIFT (31U)
/*! LUTOUT127 - LUTOUT127 */
#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT1_4 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_SHIFT (0U)
/*! LUTOUT128 - LUTOUT128 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_SHIFT (1U)
/*! LUTOUT129 - LUTOUT129 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_SHIFT (2U)
/*! LUTOUT130 - LUTOUT130 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_SHIFT (3U)
/*! LUTOUT131 - LUTOUT131 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_SHIFT (4U)
/*! LUTOUT132 - LUTOUT132 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_SHIFT (5U)
/*! LUTOUT133 - LUTOUT133 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_SHIFT (6U)
/*! LUTOUT134 - LUTOUT134 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_SHIFT (7U)
/*! LUTOUT135 - LUTOUT135 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_SHIFT (8U)
/*! LUTOUT136 - LUTOUT136 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_SHIFT (9U)
/*! LUTOUT137 - LUTOUT137 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_SHIFT (10U)
/*! LUTOUT138 - LUTOUT138 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_SHIFT (11U)
/*! LUTOUT139 - LUTOUT139 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_SHIFT (12U)
/*! LUTOUT140 - LUTOUT140 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_SHIFT (13U)
/*! LUTOUT141 - LUTOUT141 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_SHIFT (14U)
/*! LUTOUT142 - LUTOUT142 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_SHIFT (15U)
/*! LUTOUT143 - LUTOUT143 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_SHIFT (16U)
/*! LUTOUT144 - LUTOUT144 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_SHIFT (17U)
/*! LUTOUT145 - LUTOUT145 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_SHIFT (18U)
/*! LUTOUT146 - LUTOUT146 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_SHIFT (19U)
/*! LUTOUT147 - LUTOUT147 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_SHIFT (20U)
/*! LUTOUT148 - LUTOUT148 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_SHIFT (21U)
/*! LUTOUT149 - LUTOUT149 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_SHIFT (22U)
/*! LUTOUT150 - LUTOUT150 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_SHIFT (23U)
/*! LUTOUT151 - LUTOUT151 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_SHIFT (24U)
/*! LUTOUT152 - LUTOUT152 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_SHIFT (25U)
/*! LUTOUT153 - LUTOUT153 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_SHIFT (26U)
/*! LUTOUT154 - LUTOUT154 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_SHIFT (27U)
/*! LUTOUT155 - LUTOUT155 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_SHIFT (28U)
/*! LUTOUT156 - LUTOUT156 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_SHIFT (29U)
/*! LUTOUT157 - LUTOUT157 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_SHIFT (30U)
/*! LUTOUT158 - LUTOUT158 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_SHIFT (31U)
/*! LUTOUT159 - LUTOUT159 */
#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT1_5 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_SHIFT (0U)
/*! LUTOUT160 - LUTOUT160 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_SHIFT (1U)
/*! LUTOUT161 - LUTOUT161 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_SHIFT (2U)
/*! LUTOUT162 - LUTOUT162 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_SHIFT (3U)
/*! LUTOUT163 - LUTOUT163 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_SHIFT (4U)
/*! LUTOUT164 - LUTOUT164 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_SHIFT (5U)
/*! LUTOUT165 - LUTOUT165 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_SHIFT (6U)
/*! LUTOUT166 - LUTOUT166 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_SHIFT (7U)
/*! LUTOUT167 - LUTOUT167 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_SHIFT (8U)
/*! LUTOUT168 - LUTOUT168 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_SHIFT (9U)
/*! LUTOUT169 - LUTOUT169 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_SHIFT (10U)
/*! LUTOUT170 - LUTOUT170 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_SHIFT (11U)
/*! LUTOUT171 - LUTOUT171 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_SHIFT (12U)
/*! LUTOUT172 - LUTOUT172 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_SHIFT (13U)
/*! LUTOUT173 - LUTOUT173 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_SHIFT (14U)
/*! LUTOUT174 - LUTOUT174 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_SHIFT (15U)
/*! LUTOUT175 - LUTOUT175 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_SHIFT (16U)
/*! LUTOUT176 - LUTOUT176 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_SHIFT (17U)
/*! LUTOUT177 - LUTOUT177 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_SHIFT (18U)
/*! LUTOUT178 - LUTOUT178 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_SHIFT (19U)
/*! LUTOUT179 - LUTOUT179 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_SHIFT (20U)
/*! LUTOUT180 - LUTOUT180 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_SHIFT (21U)
/*! LUTOUT181 - LUTOUT181 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_SHIFT (22U)
/*! LUTOUT182 - LUTOUT182 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_SHIFT (23U)
/*! LUTOUT183 - LUTOUT183 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_SHIFT (24U)
/*! LUTOUT184 - LUTOUT184 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_SHIFT (25U)
/*! LUTOUT185 - LUTOUT185 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_SHIFT (26U)
/*! LUTOUT186 - LUTOUT186 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_SHIFT (27U)
/*! LUTOUT187 - LUTOUT187 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_SHIFT (28U)
/*! LUTOUT188 - LUTOUT188 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_SHIFT (29U)
/*! LUTOUT189 - LUTOUT189 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_SHIFT (30U)
/*! LUTOUT190 - LUTOUT190 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_SHIFT (31U)
/*! LUTOUT191 - LUTOUT191 */
#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT1_6 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_SHIFT (0U)
/*! LUTOUT192 - LUTOUT192 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_SHIFT (1U)
/*! LUTOUT193 - LUTOUT193 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_SHIFT (2U)
/*! LUTOUT194 - LUTOUT194 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_SHIFT (3U)
/*! LUTOUT195 - LUTOUT195 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_SHIFT (4U)
/*! LUTOUT196 - LUTOUT196 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_SHIFT (5U)
/*! LUTOUT197 - LUTOUT197 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_SHIFT (6U)
/*! LUTOUT198 - LUTOUT198 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_SHIFT (7U)
/*! LUTOUT199 - LUTOUT199 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_SHIFT (8U)
/*! LUTOUT200 - LUTOUT200 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_SHIFT (9U)
/*! LUTOUT201 - LUTOUT201 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_SHIFT (10U)
/*! LUTOUT202 - LUTOUT202 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_SHIFT (11U)
/*! LUTOUT203 - LUTOUT203 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_SHIFT (12U)
/*! LUTOUT204 - LUTOUT204 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_SHIFT (13U)
/*! LUTOUT205 - LUTOUT205 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_SHIFT (14U)
/*! LUTOUT206 - LUTOUT206 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_SHIFT (15U)
/*! LUTOUT207 - LUTOUT207 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_SHIFT (16U)
/*! LUTOUT208 - LUTOUT208 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_SHIFT (17U)
/*! LUTOUT209 - LUTOUT209 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_SHIFT (18U)
/*! LUTOUT210 - LUTOUT210 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_SHIFT (19U)
/*! LUTOUT211 - LUTOUT211 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_SHIFT (20U)
/*! LUTOUT212 - LUTOUT212 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_SHIFT (21U)
/*! LUTOUT213 - LUTOUT213 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_SHIFT (22U)
/*! LUTOUT214 - LUTOUT214 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_SHIFT (23U)
/*! LUTOUT215 - LUTOUT215 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_SHIFT (24U)
/*! LUTOUT216 - LUTOUT216 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_SHIFT (25U)
/*! LUTOUT217 - LUTOUT217 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_SHIFT (26U)
/*! LUTOUT218 - LUTOUT218 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_SHIFT (27U)
/*! LUTOUT219 - LUTOUT219 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_SHIFT (28U)
/*! LUTOUT220 - LUTOUT220 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_SHIFT (29U)
/*! LUTOUT221 - LUTOUT221 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_SHIFT (30U)
/*! LUTOUT222 - LUTOUT222 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_SHIFT (31U)
/*! LUTOUT223 - LUTOUT223 */
#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT1_7 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_SHIFT (0U)
/*! LUTOUT224 - LUTOUT224 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_SHIFT (1U)
/*! LUTOUT225 - LUTOUT225 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_SHIFT (2U)
/*! LUTOUT226 - LUTOUT226 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_SHIFT (3U)
/*! LUTOUT227 - LUTOUT227 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_SHIFT (4U)
/*! LUTOUT228 - LUTOUT228 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_SHIFT (5U)
/*! LUTOUT229 - LUTOUT229 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_SHIFT (6U)
/*! LUTOUT230 - LUTOUT230 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_SHIFT (7U)
/*! LUTOUT231 - LUTOUT231 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_SHIFT (8U)
/*! LUTOUT232 - LUTOUT232 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_SHIFT (9U)
/*! LUTOUT233 - LUTOUT233 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_SHIFT (10U)
/*! LUTOUT234 - LUTOUT234 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_SHIFT (11U)
/*! LUTOUT235 - LUTOUT235 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_SHIFT (12U)
/*! LUTOUT236 - LUTOUT236 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_SHIFT (13U)
/*! LUTOUT237 - LUTOUT237 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_SHIFT (14U)
/*! LUTOUT238 - LUTOUT238 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_SHIFT (15U)
/*! LUTOUT239 - LUTOUT239 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_SHIFT (16U)
/*! LUTOUT240 - LUTOUT240 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_SHIFT (17U)
/*! LUTOUT241 - LUTOUT241 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_SHIFT (18U)
/*! LUTOUT242 - LUTOUT242 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_SHIFT (19U)
/*! LUTOUT243 - LUTOUT243 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_SHIFT (20U)
/*! LUTOUT244 - LUTOUT244 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_SHIFT (21U)
/*! LUTOUT245 - LUTOUT245 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_SHIFT (22U)
/*! LUTOUT246 - LUTOUT246 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_SHIFT (23U)
/*! LUTOUT247 - LUTOUT247 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_SHIFT (24U)
/*! LUTOUT248 - LUTOUT248 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_SHIFT (25U)
/*! LUTOUT249 - LUTOUT249 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_SHIFT (26U)
/*! LUTOUT250 - LUTOUT250 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_SHIFT (27U)
/*! LUTOUT251 - LUTOUT251 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_SHIFT (28U)
/*! LUTOUT252 - LUTOUT252 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_SHIFT (29U)
/*! LUTOUT253 - LUTOUT253 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_SHIFT (30U)
/*! LUTOUT254 - LUTOUT254 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_MASK)

#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_SHIFT (31U)
/*! LUTOUT255 - LUTOUT255 */
#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT2_0 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_MASK   (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_MASK   (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_SHIFT  (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_MASK   (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_SHIFT  (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_MASK   (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_SHIFT  (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_MASK   (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_SHIFT  (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_MASK   (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_SHIFT  (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_MASK   (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_SHIFT  (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_MASK   (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_SHIFT  (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_MASK   (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_SHIFT  (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_MASK   (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_SHIFT  (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_SHIFT (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_SHIFT (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_SHIFT (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_SHIFT (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_SHIFT (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_SHIFT (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_SHIFT (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_SHIFT (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_SHIFT (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_SHIFT (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_SHIFT (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_SHIFT (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_SHIFT (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_SHIFT (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_SHIFT (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_SHIFT (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_SHIFT (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_SHIFT (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_SHIFT (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_SHIFT (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_SHIFT (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_SHIFT (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT2_1 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_SHIFT (0U)
/*! LUTOUT32 - LUTOUT32 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_SHIFT (1U)
/*! LUTOUT33 - LUTOUT33 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_SHIFT (2U)
/*! LUTOUT34 - LUTOUT34 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_SHIFT (3U)
/*! LUTOUT35 - LUTOUT35 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_MASK  (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_SHIFT (4U)
/*! LUTOUT36 - LUTOUT36 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_MASK  (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_SHIFT (5U)
/*! LUTOUT37 - LUTOUT37 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_MASK  (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_SHIFT (6U)
/*! LUTOUT38 - LUTOUT38 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_MASK  (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_SHIFT (7U)
/*! LUTOUT39 - LUTOUT39 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_MASK  (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_SHIFT (8U)
/*! LUTOUT40 - LUTOUT40 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_MASK  (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_SHIFT (9U)
/*! LUTOUT41 - LUTOUT41 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_SHIFT (10U)
/*! LUTOUT42 - LUTOUT42 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_SHIFT (11U)
/*! LUTOUT43 - LUTOUT43 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_SHIFT (12U)
/*! LUTOUT44 - LUTOUT44 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_SHIFT (13U)
/*! LUTOUT45 - LUTOUT45 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_SHIFT (14U)
/*! LUTOUT46 - LUTOUT46 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_SHIFT (15U)
/*! LUTOUT47 - LUTOUT47 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_SHIFT (16U)
/*! LUTOUT48 - LUTOUT48 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_SHIFT (17U)
/*! LUTOUT49 - LUTOUT49 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_SHIFT (18U)
/*! LUTOUT50 - LUTOUT50 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_SHIFT (19U)
/*! LUTOUT51 - LUTOUT51 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_SHIFT (20U)
/*! LUTOUT52 - LUTOUT52 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_SHIFT (21U)
/*! LUTOUT53 - LUTOUT53 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_SHIFT (22U)
/*! LUTOUT54 - LUTOUT54 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_SHIFT (23U)
/*! LUTOUT55 - LUTOUT55 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_SHIFT (24U)
/*! LUTOUT56 - LUTOUT56 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_SHIFT (25U)
/*! LUTOUT57 - LUTOUT57 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_SHIFT (26U)
/*! LUTOUT58 - LUTOUT58 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_SHIFT (27U)
/*! LUTOUT59 - LUTOUT59 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_SHIFT (28U)
/*! LUTOUT60 - LUTOUT60 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_SHIFT (29U)
/*! LUTOUT61 - LUTOUT61 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_SHIFT (30U)
/*! LUTOUT62 - LUTOUT62 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_SHIFT (31U)
/*! LUTOUT63 - LUTOUT63 */
#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT2_2 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_SHIFT (0U)
/*! LUTOUT64 - LUTOUT64 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_SHIFT (1U)
/*! LUTOUT65 - LUTOUT65 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_SHIFT (2U)
/*! LUTOUT66 - LUTOUT66 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_SHIFT (3U)
/*! LUTOUT67 - LUTOUT67 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_MASK  (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_SHIFT (4U)
/*! LUTOUT68 - LUTOUT68 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_MASK  (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_SHIFT (5U)
/*! LUTOUT69 - LUTOUT69 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_MASK  (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_SHIFT (6U)
/*! LUTOUT70 - LUTOUT70 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_MASK  (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_SHIFT (7U)
/*! LUTOUT71 - LUTOUT71 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_MASK  (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_SHIFT (8U)
/*! LUTOUT72 - LUTOUT72 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_MASK  (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_SHIFT (9U)
/*! LUTOUT73 - LUTOUT73 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_SHIFT (10U)
/*! LUTOUT74 - LUTOUT74 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_SHIFT (11U)
/*! LUTOUT75 - LUTOUT75 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_SHIFT (12U)
/*! LUTOUT76 - LUTOUT76 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_SHIFT (13U)
/*! LUTOUT77 - LUTOUT77 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_SHIFT (14U)
/*! LUTOUT78 - LUTOUT78 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_SHIFT (15U)
/*! LUTOUT79 - LUTOUT79 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_SHIFT (16U)
/*! LUTOUT80 - LUTOUT80 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_SHIFT (17U)
/*! LUTOUT81 - LUTOUT81 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_SHIFT (18U)
/*! LUTOUT82 - LUTOUT82 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_SHIFT (19U)
/*! LUTOUT83 - LUTOUT83 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_SHIFT (20U)
/*! LUTOUT84 - LUTOUT84 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_SHIFT (21U)
/*! LUTOUT85 - LUTOUT85 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_SHIFT (22U)
/*! LUTOUT86 - LUTOUT86 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_SHIFT (23U)
/*! LUTOUT87 - LUTOUT87 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_SHIFT (24U)
/*! LUTOUT88 - LUTOUT88 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_SHIFT (25U)
/*! LUTOUT89 - LUTOUT89 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_SHIFT (26U)
/*! LUTOUT90 - LUTOUT90 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_SHIFT (27U)
/*! LUTOUT91 - LUTOUT91 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_SHIFT (28U)
/*! LUTOUT92 - LUTOUT92 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_SHIFT (29U)
/*! LUTOUT93 - LUTOUT93 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_SHIFT (30U)
/*! LUTOUT94 - LUTOUT94 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_SHIFT (31U)
/*! LUTOUT95 - LUTOUT95 */
#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT2_3 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_SHIFT (0U)
/*! LUTOUT96 - LUTOUT96 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_SHIFT (1U)
/*! LUTOUT97 - LUTOUT97 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_SHIFT (2U)
/*! LUTOUT98 - LUTOUT98 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_SHIFT (3U)
/*! LUTOUT99 - LUTOUT99 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_SHIFT (4U)
/*! LUTOUT100 - LUTOUT100 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_SHIFT (5U)
/*! LUTOUT101 - LUTOUT101 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_SHIFT (6U)
/*! LUTOUT102 - LUTOUT102 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_SHIFT (7U)
/*! LUTOUT103 - LUTOUT103 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_SHIFT (8U)
/*! LUTOUT104 - LUTOUT104 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_SHIFT (9U)
/*! LUTOUT105 - LUTOUT105 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_SHIFT (10U)
/*! LUTOUT106 - LUTOUT106 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_SHIFT (11U)
/*! LUTOUT107 - LUTOUT107 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_SHIFT (12U)
/*! LUTOUT108 - LUTOUT108 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_SHIFT (13U)
/*! LUTOUT109 - LUTOUT109 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_SHIFT (14U)
/*! LUTOUT110 - LUTOUT110 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_SHIFT (15U)
/*! LUTOUT111 - LUTOUT111 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_SHIFT (16U)
/*! LUTOUT112 - LUTOUT112 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_SHIFT (17U)
/*! LUTOUT113 - LUTOUT113 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_SHIFT (18U)
/*! LUTOUT114 - LUTOUT114 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_SHIFT (19U)
/*! LUTOUT115 - LUTOUT115 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_SHIFT (20U)
/*! LUTOUT116 - LUTOUT116 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_SHIFT (21U)
/*! LUTOUT117 - LUTOUT117 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_SHIFT (22U)
/*! LUTOUT118 - LUTOUT118 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_SHIFT (23U)
/*! LUTOUT119 - LUTOUT119 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_SHIFT (24U)
/*! LUTOUT120 - LUTOUT120 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_SHIFT (25U)
/*! LUTOUT121 - LUTOUT121 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_SHIFT (26U)
/*! LUTOUT122 - LUTOUT122 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_SHIFT (27U)
/*! LUTOUT123 - LUTOUT123 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_SHIFT (28U)
/*! LUTOUT124 - LUTOUT124 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_SHIFT (29U)
/*! LUTOUT125 - LUTOUT125 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_SHIFT (30U)
/*! LUTOUT126 - LUTOUT126 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_SHIFT (31U)
/*! LUTOUT127 - LUTOUT127 */
#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT2_4 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_SHIFT (0U)
/*! LUTOUT128 - LUTOUT128 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_SHIFT (1U)
/*! LUTOUT129 - LUTOUT129 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_SHIFT (2U)
/*! LUTOUT130 - LUTOUT130 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_SHIFT (3U)
/*! LUTOUT131 - LUTOUT131 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_SHIFT (4U)
/*! LUTOUT132 - LUTOUT132 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_SHIFT (5U)
/*! LUTOUT133 - LUTOUT133 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_SHIFT (6U)
/*! LUTOUT134 - LUTOUT134 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_SHIFT (7U)
/*! LUTOUT135 - LUTOUT135 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_SHIFT (8U)
/*! LUTOUT136 - LUTOUT136 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_SHIFT (9U)
/*! LUTOUT137 - LUTOUT137 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_SHIFT (10U)
/*! LUTOUT138 - LUTOUT138 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_SHIFT (11U)
/*! LUTOUT139 - LUTOUT139 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_SHIFT (12U)
/*! LUTOUT140 - LUTOUT140 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_SHIFT (13U)
/*! LUTOUT141 - LUTOUT141 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_SHIFT (14U)
/*! LUTOUT142 - LUTOUT142 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_SHIFT (15U)
/*! LUTOUT143 - LUTOUT143 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_SHIFT (16U)
/*! LUTOUT144 - LUTOUT144 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_SHIFT (17U)
/*! LUTOUT145 - LUTOUT145 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_SHIFT (18U)
/*! LUTOUT146 - LUTOUT146 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_SHIFT (19U)
/*! LUTOUT147 - LUTOUT147 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_SHIFT (20U)
/*! LUTOUT148 - LUTOUT148 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_SHIFT (21U)
/*! LUTOUT149 - LUTOUT149 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_SHIFT (22U)
/*! LUTOUT150 - LUTOUT150 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_SHIFT (23U)
/*! LUTOUT151 - LUTOUT151 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_SHIFT (24U)
/*! LUTOUT152 - LUTOUT152 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_SHIFT (25U)
/*! LUTOUT153 - LUTOUT153 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_SHIFT (26U)
/*! LUTOUT154 - LUTOUT154 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_SHIFT (27U)
/*! LUTOUT155 - LUTOUT155 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_SHIFT (28U)
/*! LUTOUT156 - LUTOUT156 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_SHIFT (29U)
/*! LUTOUT157 - LUTOUT157 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_SHIFT (30U)
/*! LUTOUT158 - LUTOUT158 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_SHIFT (31U)
/*! LUTOUT159 - LUTOUT159 */
#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT2_5 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_SHIFT (0U)
/*! LUTOUT160 - LUTOUT160 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_SHIFT (1U)
/*! LUTOUT161 - LUTOUT161 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_SHIFT (2U)
/*! LUTOUT162 - LUTOUT162 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_SHIFT (3U)
/*! LUTOUT163 - LUTOUT163 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_SHIFT (4U)
/*! LUTOUT164 - LUTOUT164 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_SHIFT (5U)
/*! LUTOUT165 - LUTOUT165 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_SHIFT (6U)
/*! LUTOUT166 - LUTOUT166 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_SHIFT (7U)
/*! LUTOUT167 - LUTOUT167 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_SHIFT (8U)
/*! LUTOUT168 - LUTOUT168 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_SHIFT (9U)
/*! LUTOUT169 - LUTOUT169 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_SHIFT (10U)
/*! LUTOUT170 - LUTOUT170 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_SHIFT (11U)
/*! LUTOUT171 - LUTOUT171 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_SHIFT (12U)
/*! LUTOUT172 - LUTOUT172 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_SHIFT (13U)
/*! LUTOUT173 - LUTOUT173 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_SHIFT (14U)
/*! LUTOUT174 - LUTOUT174 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_SHIFT (15U)
/*! LUTOUT175 - LUTOUT175 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_SHIFT (16U)
/*! LUTOUT176 - LUTOUT176 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_SHIFT (17U)
/*! LUTOUT177 - LUTOUT177 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_SHIFT (18U)
/*! LUTOUT178 - LUTOUT178 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_SHIFT (19U)
/*! LUTOUT179 - LUTOUT179 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_SHIFT (20U)
/*! LUTOUT180 - LUTOUT180 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_SHIFT (21U)
/*! LUTOUT181 - LUTOUT181 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_SHIFT (22U)
/*! LUTOUT182 - LUTOUT182 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_SHIFT (23U)
/*! LUTOUT183 - LUTOUT183 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_SHIFT (24U)
/*! LUTOUT184 - LUTOUT184 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_SHIFT (25U)
/*! LUTOUT185 - LUTOUT185 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_SHIFT (26U)
/*! LUTOUT186 - LUTOUT186 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_SHIFT (27U)
/*! LUTOUT187 - LUTOUT187 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_SHIFT (28U)
/*! LUTOUT188 - LUTOUT188 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_SHIFT (29U)
/*! LUTOUT189 - LUTOUT189 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_SHIFT (30U)
/*! LUTOUT190 - LUTOUT190 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_SHIFT (31U)
/*! LUTOUT191 - LUTOUT191 */
#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT2_6 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_SHIFT (0U)
/*! LUTOUT192 - LUTOUT192 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_SHIFT (1U)
/*! LUTOUT193 - LUTOUT193 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_SHIFT (2U)
/*! LUTOUT194 - LUTOUT194 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_SHIFT (3U)
/*! LUTOUT195 - LUTOUT195 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_SHIFT (4U)
/*! LUTOUT196 - LUTOUT196 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_SHIFT (5U)
/*! LUTOUT197 - LUTOUT197 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_SHIFT (6U)
/*! LUTOUT198 - LUTOUT198 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_SHIFT (7U)
/*! LUTOUT199 - LUTOUT199 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_SHIFT (8U)
/*! LUTOUT200 - LUTOUT200 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_SHIFT (9U)
/*! LUTOUT201 - LUTOUT201 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_SHIFT (10U)
/*! LUTOUT202 - LUTOUT202 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_SHIFT (11U)
/*! LUTOUT203 - LUTOUT203 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_SHIFT (12U)
/*! LUTOUT204 - LUTOUT204 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_SHIFT (13U)
/*! LUTOUT205 - LUTOUT205 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_SHIFT (14U)
/*! LUTOUT206 - LUTOUT206 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_SHIFT (15U)
/*! LUTOUT207 - LUTOUT207 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_SHIFT (16U)
/*! LUTOUT208 - LUTOUT208 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_SHIFT (17U)
/*! LUTOUT209 - LUTOUT209 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_SHIFT (18U)
/*! LUTOUT210 - LUTOUT210 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_SHIFT (19U)
/*! LUTOUT211 - LUTOUT211 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_SHIFT (20U)
/*! LUTOUT212 - LUTOUT212 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_SHIFT (21U)
/*! LUTOUT213 - LUTOUT213 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_SHIFT (22U)
/*! LUTOUT214 - LUTOUT214 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_SHIFT (23U)
/*! LUTOUT215 - LUTOUT215 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_SHIFT (24U)
/*! LUTOUT216 - LUTOUT216 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_SHIFT (25U)
/*! LUTOUT217 - LUTOUT217 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_SHIFT (26U)
/*! LUTOUT218 - LUTOUT218 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_SHIFT (27U)
/*! LUTOUT219 - LUTOUT219 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_SHIFT (28U)
/*! LUTOUT220 - LUTOUT220 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_SHIFT (29U)
/*! LUTOUT221 - LUTOUT221 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_SHIFT (30U)
/*! LUTOUT222 - LUTOUT222 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_SHIFT (31U)
/*! LUTOUT223 - LUTOUT223 */
#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT2_7 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_SHIFT (0U)
/*! LUTOUT224 - LUTOUT224 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_SHIFT (1U)
/*! LUTOUT225 - LUTOUT225 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_SHIFT (2U)
/*! LUTOUT226 - LUTOUT226 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_SHIFT (3U)
/*! LUTOUT227 - LUTOUT227 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_SHIFT (4U)
/*! LUTOUT228 - LUTOUT228 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_SHIFT (5U)
/*! LUTOUT229 - LUTOUT229 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_SHIFT (6U)
/*! LUTOUT230 - LUTOUT230 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_SHIFT (7U)
/*! LUTOUT231 - LUTOUT231 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_SHIFT (8U)
/*! LUTOUT232 - LUTOUT232 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_SHIFT (9U)
/*! LUTOUT233 - LUTOUT233 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_SHIFT (10U)
/*! LUTOUT234 - LUTOUT234 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_SHIFT (11U)
/*! LUTOUT235 - LUTOUT235 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_SHIFT (12U)
/*! LUTOUT236 - LUTOUT236 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_SHIFT (13U)
/*! LUTOUT237 - LUTOUT237 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_SHIFT (14U)
/*! LUTOUT238 - LUTOUT238 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_SHIFT (15U)
/*! LUTOUT239 - LUTOUT239 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_SHIFT (16U)
/*! LUTOUT240 - LUTOUT240 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_SHIFT (17U)
/*! LUTOUT241 - LUTOUT241 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_SHIFT (18U)
/*! LUTOUT242 - LUTOUT242 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_SHIFT (19U)
/*! LUTOUT243 - LUTOUT243 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_SHIFT (20U)
/*! LUTOUT244 - LUTOUT244 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_SHIFT (21U)
/*! LUTOUT245 - LUTOUT245 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_SHIFT (22U)
/*! LUTOUT246 - LUTOUT246 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_SHIFT (23U)
/*! LUTOUT247 - LUTOUT247 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_SHIFT (24U)
/*! LUTOUT248 - LUTOUT248 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_SHIFT (25U)
/*! LUTOUT249 - LUTOUT249 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_SHIFT (26U)
/*! LUTOUT250 - LUTOUT250 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_SHIFT (27U)
/*! LUTOUT251 - LUTOUT251 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_SHIFT (28U)
/*! LUTOUT252 - LUTOUT252 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_SHIFT (29U)
/*! LUTOUT253 - LUTOUT253 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_SHIFT (30U)
/*! LUTOUT254 - LUTOUT254 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_MASK)

#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_SHIFT (31U)
/*! LUTOUT255 - LUTOUT255 */
#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT3_0 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_MASK   (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_MASK   (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_SHIFT  (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_MASK   (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_SHIFT  (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_MASK   (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_SHIFT  (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_MASK   (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_SHIFT  (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_MASK   (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_SHIFT  (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_MASK   (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_SHIFT  (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_MASK   (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_SHIFT  (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_MASK   (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_SHIFT  (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_MASK   (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_SHIFT  (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_SHIFT (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_SHIFT (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_SHIFT (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_SHIFT (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_SHIFT (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_SHIFT (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_SHIFT (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_SHIFT (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_SHIFT (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_SHIFT (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_SHIFT (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_SHIFT (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_SHIFT (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_SHIFT (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_SHIFT (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_SHIFT (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_SHIFT (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_SHIFT (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_SHIFT (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_SHIFT (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_SHIFT (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_SHIFT (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT3_1 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_SHIFT (0U)
/*! LUTOUT32 - LUTOUT32 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_SHIFT (1U)
/*! LUTOUT33 - LUTOUT33 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_SHIFT (2U)
/*! LUTOUT34 - LUTOUT34 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_SHIFT (3U)
/*! LUTOUT35 - LUTOUT35 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_MASK  (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_SHIFT (4U)
/*! LUTOUT36 - LUTOUT36 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_MASK  (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_SHIFT (5U)
/*! LUTOUT37 - LUTOUT37 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_MASK  (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_SHIFT (6U)
/*! LUTOUT38 - LUTOUT38 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_MASK  (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_SHIFT (7U)
/*! LUTOUT39 - LUTOUT39 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_MASK  (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_SHIFT (8U)
/*! LUTOUT40 - LUTOUT40 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_MASK  (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_SHIFT (9U)
/*! LUTOUT41 - LUTOUT41 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_SHIFT (10U)
/*! LUTOUT42 - LUTOUT42 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_SHIFT (11U)
/*! LUTOUT43 - LUTOUT43 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_SHIFT (12U)
/*! LUTOUT44 - LUTOUT44 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_SHIFT (13U)
/*! LUTOUT45 - LUTOUT45 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_SHIFT (14U)
/*! LUTOUT46 - LUTOUT46 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_SHIFT (15U)
/*! LUTOUT47 - LUTOUT47 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_SHIFT (16U)
/*! LUTOUT48 - LUTOUT48 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_SHIFT (17U)
/*! LUTOUT49 - LUTOUT49 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_SHIFT (18U)
/*! LUTOUT50 - LUTOUT50 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_SHIFT (19U)
/*! LUTOUT51 - LUTOUT51 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_SHIFT (20U)
/*! LUTOUT52 - LUTOUT52 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_SHIFT (21U)
/*! LUTOUT53 - LUTOUT53 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_SHIFT (22U)
/*! LUTOUT54 - LUTOUT54 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_SHIFT (23U)
/*! LUTOUT55 - LUTOUT55 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_SHIFT (24U)
/*! LUTOUT56 - LUTOUT56 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_SHIFT (25U)
/*! LUTOUT57 - LUTOUT57 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_SHIFT (26U)
/*! LUTOUT58 - LUTOUT58 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_SHIFT (27U)
/*! LUTOUT59 - LUTOUT59 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_SHIFT (28U)
/*! LUTOUT60 - LUTOUT60 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_SHIFT (29U)
/*! LUTOUT61 - LUTOUT61 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_SHIFT (30U)
/*! LUTOUT62 - LUTOUT62 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_SHIFT (31U)
/*! LUTOUT63 - LUTOUT63 */
#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT3_2 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_SHIFT (0U)
/*! LUTOUT64 - LUTOUT64 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_SHIFT (1U)
/*! LUTOUT65 - LUTOUT65 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_SHIFT (2U)
/*! LUTOUT66 - LUTOUT66 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_SHIFT (3U)
/*! LUTOUT67 - LUTOUT67 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_MASK  (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_SHIFT (4U)
/*! LUTOUT68 - LUTOUT68 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_MASK  (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_SHIFT (5U)
/*! LUTOUT69 - LUTOUT69 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_MASK  (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_SHIFT (6U)
/*! LUTOUT70 - LUTOUT70 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_MASK  (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_SHIFT (7U)
/*! LUTOUT71 - LUTOUT71 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_MASK  (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_SHIFT (8U)
/*! LUTOUT72 - LUTOUT72 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_MASK  (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_SHIFT (9U)
/*! LUTOUT73 - LUTOUT73 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_SHIFT (10U)
/*! LUTOUT74 - LUTOUT74 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_SHIFT (11U)
/*! LUTOUT75 - LUTOUT75 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_SHIFT (12U)
/*! LUTOUT76 - LUTOUT76 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_SHIFT (13U)
/*! LUTOUT77 - LUTOUT77 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_SHIFT (14U)
/*! LUTOUT78 - LUTOUT78 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_SHIFT (15U)
/*! LUTOUT79 - LUTOUT79 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_SHIFT (16U)
/*! LUTOUT80 - LUTOUT80 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_SHIFT (17U)
/*! LUTOUT81 - LUTOUT81 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_SHIFT (18U)
/*! LUTOUT82 - LUTOUT82 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_SHIFT (19U)
/*! LUTOUT83 - LUTOUT83 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_SHIFT (20U)
/*! LUTOUT84 - LUTOUT84 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_SHIFT (21U)
/*! LUTOUT85 - LUTOUT85 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_SHIFT (22U)
/*! LUTOUT86 - LUTOUT86 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_SHIFT (23U)
/*! LUTOUT87 - LUTOUT87 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_SHIFT (24U)
/*! LUTOUT88 - LUTOUT88 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_SHIFT (25U)
/*! LUTOUT89 - LUTOUT89 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_SHIFT (26U)
/*! LUTOUT90 - LUTOUT90 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_SHIFT (27U)
/*! LUTOUT91 - LUTOUT91 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_SHIFT (28U)
/*! LUTOUT92 - LUTOUT92 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_SHIFT (29U)
/*! LUTOUT93 - LUTOUT93 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_SHIFT (30U)
/*! LUTOUT94 - LUTOUT94 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_SHIFT (31U)
/*! LUTOUT95 - LUTOUT95 */
#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT3_3 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_SHIFT (0U)
/*! LUTOUT96 - LUTOUT96 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_SHIFT (1U)
/*! LUTOUT97 - LUTOUT97 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_SHIFT (2U)
/*! LUTOUT98 - LUTOUT98 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_SHIFT (3U)
/*! LUTOUT99 - LUTOUT99 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_SHIFT (4U)
/*! LUTOUT100 - LUTOUT100 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_SHIFT (5U)
/*! LUTOUT101 - LUTOUT101 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_SHIFT (6U)
/*! LUTOUT102 - LUTOUT102 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_SHIFT (7U)
/*! LUTOUT103 - LUTOUT103 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_SHIFT (8U)
/*! LUTOUT104 - LUTOUT104 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_SHIFT (9U)
/*! LUTOUT105 - LUTOUT105 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_SHIFT (10U)
/*! LUTOUT106 - LUTOUT106 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_SHIFT (11U)
/*! LUTOUT107 - LUTOUT107 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_SHIFT (12U)
/*! LUTOUT108 - LUTOUT108 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_SHIFT (13U)
/*! LUTOUT109 - LUTOUT109 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_SHIFT (14U)
/*! LUTOUT110 - LUTOUT110 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_SHIFT (15U)
/*! LUTOUT111 - LUTOUT111 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_SHIFT (16U)
/*! LUTOUT112 - LUTOUT112 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_SHIFT (17U)
/*! LUTOUT113 - LUTOUT113 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_SHIFT (18U)
/*! LUTOUT114 - LUTOUT114 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_SHIFT (19U)
/*! LUTOUT115 - LUTOUT115 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_SHIFT (20U)
/*! LUTOUT116 - LUTOUT116 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_SHIFT (21U)
/*! LUTOUT117 - LUTOUT117 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_SHIFT (22U)
/*! LUTOUT118 - LUTOUT118 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_SHIFT (23U)
/*! LUTOUT119 - LUTOUT119 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_SHIFT (24U)
/*! LUTOUT120 - LUTOUT120 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_SHIFT (25U)
/*! LUTOUT121 - LUTOUT121 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_SHIFT (26U)
/*! LUTOUT122 - LUTOUT122 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_SHIFT (27U)
/*! LUTOUT123 - LUTOUT123 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_SHIFT (28U)
/*! LUTOUT124 - LUTOUT124 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_SHIFT (29U)
/*! LUTOUT125 - LUTOUT125 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_SHIFT (30U)
/*! LUTOUT126 - LUTOUT126 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_SHIFT (31U)
/*! LUTOUT127 - LUTOUT127 */
#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT3_4 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_SHIFT (0U)
/*! LUTOUT128 - LUTOUT128 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_SHIFT (1U)
/*! LUTOUT129 - LUTOUT129 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_SHIFT (2U)
/*! LUTOUT130 - LUTOUT130 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_SHIFT (3U)
/*! LUTOUT131 - LUTOUT131 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_SHIFT (4U)
/*! LUTOUT132 - LUTOUT132 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_SHIFT (5U)
/*! LUTOUT133 - LUTOUT133 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_SHIFT (6U)
/*! LUTOUT134 - LUTOUT134 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_SHIFT (7U)
/*! LUTOUT135 - LUTOUT135 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_SHIFT (8U)
/*! LUTOUT136 - LUTOUT136 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_SHIFT (9U)
/*! LUTOUT137 - LUTOUT137 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_SHIFT (10U)
/*! LUTOUT138 - LUTOUT138 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_SHIFT (11U)
/*! LUTOUT139 - LUTOUT139 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_SHIFT (12U)
/*! LUTOUT140 - LUTOUT140 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_SHIFT (13U)
/*! LUTOUT141 - LUTOUT141 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_SHIFT (14U)
/*! LUTOUT142 - LUTOUT142 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_SHIFT (15U)
/*! LUTOUT143 - LUTOUT143 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_SHIFT (16U)
/*! LUTOUT144 - LUTOUT144 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_SHIFT (17U)
/*! LUTOUT145 - LUTOUT145 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_SHIFT (18U)
/*! LUTOUT146 - LUTOUT146 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_SHIFT (19U)
/*! LUTOUT147 - LUTOUT147 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_SHIFT (20U)
/*! LUTOUT148 - LUTOUT148 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_SHIFT (21U)
/*! LUTOUT149 - LUTOUT149 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_SHIFT (22U)
/*! LUTOUT150 - LUTOUT150 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_SHIFT (23U)
/*! LUTOUT151 - LUTOUT151 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_SHIFT (24U)
/*! LUTOUT152 - LUTOUT152 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_SHIFT (25U)
/*! LUTOUT153 - LUTOUT153 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_SHIFT (26U)
/*! LUTOUT154 - LUTOUT154 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_SHIFT (27U)
/*! LUTOUT155 - LUTOUT155 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_SHIFT (28U)
/*! LUTOUT156 - LUTOUT156 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_SHIFT (29U)
/*! LUTOUT157 - LUTOUT157 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_SHIFT (30U)
/*! LUTOUT158 - LUTOUT158 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_SHIFT (31U)
/*! LUTOUT159 - LUTOUT159 */
#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT3_5 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_SHIFT (0U)
/*! LUTOUT160 - LUTOUT160 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_SHIFT (1U)
/*! LUTOUT161 - LUTOUT161 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_SHIFT (2U)
/*! LUTOUT162 - LUTOUT162 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_SHIFT (3U)
/*! LUTOUT163 - LUTOUT163 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_SHIFT (4U)
/*! LUTOUT164 - LUTOUT164 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_SHIFT (5U)
/*! LUTOUT165 - LUTOUT165 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_SHIFT (6U)
/*! LUTOUT166 - LUTOUT166 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_SHIFT (7U)
/*! LUTOUT167 - LUTOUT167 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_SHIFT (8U)
/*! LUTOUT168 - LUTOUT168 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_SHIFT (9U)
/*! LUTOUT169 - LUTOUT169 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_SHIFT (10U)
/*! LUTOUT170 - LUTOUT170 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_SHIFT (11U)
/*! LUTOUT171 - LUTOUT171 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_SHIFT (12U)
/*! LUTOUT172 - LUTOUT172 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_SHIFT (13U)
/*! LUTOUT173 - LUTOUT173 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_SHIFT (14U)
/*! LUTOUT174 - LUTOUT174 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_SHIFT (15U)
/*! LUTOUT175 - LUTOUT175 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_SHIFT (16U)
/*! LUTOUT176 - LUTOUT176 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_SHIFT (17U)
/*! LUTOUT177 - LUTOUT177 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_SHIFT (18U)
/*! LUTOUT178 - LUTOUT178 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_SHIFT (19U)
/*! LUTOUT179 - LUTOUT179 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_SHIFT (20U)
/*! LUTOUT180 - LUTOUT180 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_SHIFT (21U)
/*! LUTOUT181 - LUTOUT181 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_SHIFT (22U)
/*! LUTOUT182 - LUTOUT182 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_SHIFT (23U)
/*! LUTOUT183 - LUTOUT183 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_SHIFT (24U)
/*! LUTOUT184 - LUTOUT184 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_SHIFT (25U)
/*! LUTOUT185 - LUTOUT185 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_SHIFT (26U)
/*! LUTOUT186 - LUTOUT186 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_SHIFT (27U)
/*! LUTOUT187 - LUTOUT187 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_SHIFT (28U)
/*! LUTOUT188 - LUTOUT188 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_SHIFT (29U)
/*! LUTOUT189 - LUTOUT189 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_SHIFT (30U)
/*! LUTOUT190 - LUTOUT190 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_SHIFT (31U)
/*! LUTOUT191 - LUTOUT191 */
#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT3_6 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_SHIFT (0U)
/*! LUTOUT192 - LUTOUT192 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_SHIFT (1U)
/*! LUTOUT193 - LUTOUT193 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_SHIFT (2U)
/*! LUTOUT194 - LUTOUT194 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_SHIFT (3U)
/*! LUTOUT195 - LUTOUT195 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_SHIFT (4U)
/*! LUTOUT196 - LUTOUT196 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_SHIFT (5U)
/*! LUTOUT197 - LUTOUT197 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_SHIFT (6U)
/*! LUTOUT198 - LUTOUT198 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_SHIFT (7U)
/*! LUTOUT199 - LUTOUT199 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_SHIFT (8U)
/*! LUTOUT200 - LUTOUT200 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_SHIFT (9U)
/*! LUTOUT201 - LUTOUT201 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_SHIFT (10U)
/*! LUTOUT202 - LUTOUT202 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_SHIFT (11U)
/*! LUTOUT203 - LUTOUT203 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_SHIFT (12U)
/*! LUTOUT204 - LUTOUT204 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_SHIFT (13U)
/*! LUTOUT205 - LUTOUT205 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_SHIFT (14U)
/*! LUTOUT206 - LUTOUT206 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_SHIFT (15U)
/*! LUTOUT207 - LUTOUT207 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_SHIFT (16U)
/*! LUTOUT208 - LUTOUT208 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_SHIFT (17U)
/*! LUTOUT209 - LUTOUT209 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_SHIFT (18U)
/*! LUTOUT210 - LUTOUT210 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_SHIFT (19U)
/*! LUTOUT211 - LUTOUT211 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_SHIFT (20U)
/*! LUTOUT212 - LUTOUT212 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_SHIFT (21U)
/*! LUTOUT213 - LUTOUT213 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_SHIFT (22U)
/*! LUTOUT214 - LUTOUT214 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_SHIFT (23U)
/*! LUTOUT215 - LUTOUT215 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_SHIFT (24U)
/*! LUTOUT216 - LUTOUT216 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_SHIFT (25U)
/*! LUTOUT217 - LUTOUT217 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_SHIFT (26U)
/*! LUTOUT218 - LUTOUT218 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_SHIFT (27U)
/*! LUTOUT219 - LUTOUT219 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_SHIFT (28U)
/*! LUTOUT220 - LUTOUT220 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_SHIFT (29U)
/*! LUTOUT221 - LUTOUT221 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_SHIFT (30U)
/*! LUTOUT222 - LUTOUT222 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_SHIFT (31U)
/*! LUTOUT223 - LUTOUT223 */
#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT3_7 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_SHIFT (0U)
/*! LUTOUT224 - LUTOUT224 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_SHIFT (1U)
/*! LUTOUT225 - LUTOUT225 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_SHIFT (2U)
/*! LUTOUT226 - LUTOUT226 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_SHIFT (3U)
/*! LUTOUT227 - LUTOUT227 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_SHIFT (4U)
/*! LUTOUT228 - LUTOUT228 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_SHIFT (5U)
/*! LUTOUT229 - LUTOUT229 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_SHIFT (6U)
/*! LUTOUT230 - LUTOUT230 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_SHIFT (7U)
/*! LUTOUT231 - LUTOUT231 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_SHIFT (8U)
/*! LUTOUT232 - LUTOUT232 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_SHIFT (9U)
/*! LUTOUT233 - LUTOUT233 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_SHIFT (10U)
/*! LUTOUT234 - LUTOUT234 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_SHIFT (11U)
/*! LUTOUT235 - LUTOUT235 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_SHIFT (12U)
/*! LUTOUT236 - LUTOUT236 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_SHIFT (13U)
/*! LUTOUT237 - LUTOUT237 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_SHIFT (14U)
/*! LUTOUT238 - LUTOUT238 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_SHIFT (15U)
/*! LUTOUT239 - LUTOUT239 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_SHIFT (16U)
/*! LUTOUT240 - LUTOUT240 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_SHIFT (17U)
/*! LUTOUT241 - LUTOUT241 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_SHIFT (18U)
/*! LUTOUT242 - LUTOUT242 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_SHIFT (19U)
/*! LUTOUT243 - LUTOUT243 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_SHIFT (20U)
/*! LUTOUT244 - LUTOUT244 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_SHIFT (21U)
/*! LUTOUT245 - LUTOUT245 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_SHIFT (22U)
/*! LUTOUT246 - LUTOUT246 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_SHIFT (23U)
/*! LUTOUT247 - LUTOUT247 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_SHIFT (24U)
/*! LUTOUT248 - LUTOUT248 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_SHIFT (25U)
/*! LUTOUT249 - LUTOUT249 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_SHIFT (26U)
/*! LUTOUT250 - LUTOUT250 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_SHIFT (27U)
/*! LUTOUT251 - LUTOUT251 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_SHIFT (28U)
/*! LUTOUT252 - LUTOUT252 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_SHIFT (29U)
/*! LUTOUT253 - LUTOUT253 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_SHIFT (30U)
/*! LUTOUT254 - LUTOUT254 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_MASK)

#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_SHIFT (31U)
/*! LUTOUT255 - LUTOUT255 */
#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT4_0 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_MASK   (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_MASK   (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_SHIFT  (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_MASK   (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_SHIFT  (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_MASK   (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_SHIFT  (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_MASK   (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_SHIFT  (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_MASK   (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_SHIFT  (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_MASK   (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_SHIFT  (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_MASK   (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_SHIFT  (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_MASK   (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_SHIFT  (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_MASK   (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_SHIFT  (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_SHIFT (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_SHIFT (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_SHIFT (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_SHIFT (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_SHIFT (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_SHIFT (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_SHIFT (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_SHIFT (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_SHIFT (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_SHIFT (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_SHIFT (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_SHIFT (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_SHIFT (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_SHIFT (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_SHIFT (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_SHIFT (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_SHIFT (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_SHIFT (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_SHIFT (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_SHIFT (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_SHIFT (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_SHIFT (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT4_1 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_SHIFT (0U)
/*! LUTOUT32 - LUTOUT32 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_SHIFT (1U)
/*! LUTOUT33 - LUTOUT33 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_SHIFT (2U)
/*! LUTOUT34 - LUTOUT34 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_SHIFT (3U)
/*! LUTOUT35 - LUTOUT35 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_MASK  (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_SHIFT (4U)
/*! LUTOUT36 - LUTOUT36 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_MASK  (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_SHIFT (5U)
/*! LUTOUT37 - LUTOUT37 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_MASK  (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_SHIFT (6U)
/*! LUTOUT38 - LUTOUT38 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_MASK  (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_SHIFT (7U)
/*! LUTOUT39 - LUTOUT39 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_MASK  (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_SHIFT (8U)
/*! LUTOUT40 - LUTOUT40 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_MASK  (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_SHIFT (9U)
/*! LUTOUT41 - LUTOUT41 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_SHIFT (10U)
/*! LUTOUT42 - LUTOUT42 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_SHIFT (11U)
/*! LUTOUT43 - LUTOUT43 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_SHIFT (12U)
/*! LUTOUT44 - LUTOUT44 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_SHIFT (13U)
/*! LUTOUT45 - LUTOUT45 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_SHIFT (14U)
/*! LUTOUT46 - LUTOUT46 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_SHIFT (15U)
/*! LUTOUT47 - LUTOUT47 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_SHIFT (16U)
/*! LUTOUT48 - LUTOUT48 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_SHIFT (17U)
/*! LUTOUT49 - LUTOUT49 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_SHIFT (18U)
/*! LUTOUT50 - LUTOUT50 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_SHIFT (19U)
/*! LUTOUT51 - LUTOUT51 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_SHIFT (20U)
/*! LUTOUT52 - LUTOUT52 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_SHIFT (21U)
/*! LUTOUT53 - LUTOUT53 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_SHIFT (22U)
/*! LUTOUT54 - LUTOUT54 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_SHIFT (23U)
/*! LUTOUT55 - LUTOUT55 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_SHIFT (24U)
/*! LUTOUT56 - LUTOUT56 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_SHIFT (25U)
/*! LUTOUT57 - LUTOUT57 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_SHIFT (26U)
/*! LUTOUT58 - LUTOUT58 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_SHIFT (27U)
/*! LUTOUT59 - LUTOUT59 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_SHIFT (28U)
/*! LUTOUT60 - LUTOUT60 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_SHIFT (29U)
/*! LUTOUT61 - LUTOUT61 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_SHIFT (30U)
/*! LUTOUT62 - LUTOUT62 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_SHIFT (31U)
/*! LUTOUT63 - LUTOUT63 */
#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT4_2 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_SHIFT (0U)
/*! LUTOUT64 - LUTOUT64 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_SHIFT (1U)
/*! LUTOUT65 - LUTOUT65 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_SHIFT (2U)
/*! LUTOUT66 - LUTOUT66 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_SHIFT (3U)
/*! LUTOUT67 - LUTOUT67 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_MASK  (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_SHIFT (4U)
/*! LUTOUT68 - LUTOUT68 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_MASK  (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_SHIFT (5U)
/*! LUTOUT69 - LUTOUT69 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_MASK  (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_SHIFT (6U)
/*! LUTOUT70 - LUTOUT70 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_MASK  (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_SHIFT (7U)
/*! LUTOUT71 - LUTOUT71 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_MASK  (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_SHIFT (8U)
/*! LUTOUT72 - LUTOUT72 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_MASK  (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_SHIFT (9U)
/*! LUTOUT73 - LUTOUT73 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_MASK  (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_SHIFT (10U)
/*! LUTOUT74 - LUTOUT74 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_MASK  (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_SHIFT (11U)
/*! LUTOUT75 - LUTOUT75 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_MASK  (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_SHIFT (12U)
/*! LUTOUT76 - LUTOUT76 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_MASK  (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_SHIFT (13U)
/*! LUTOUT77 - LUTOUT77 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_MASK  (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_SHIFT (14U)
/*! LUTOUT78 - LUTOUT78 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_MASK  (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_SHIFT (15U)
/*! LUTOUT79 - LUTOUT79 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_MASK  (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_SHIFT (16U)
/*! LUTOUT80 - LUTOUT80 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_MASK  (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_SHIFT (17U)
/*! LUTOUT81 - LUTOUT81 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_MASK  (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_SHIFT (18U)
/*! LUTOUT82 - LUTOUT82 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_MASK  (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_SHIFT (19U)
/*! LUTOUT83 - LUTOUT83 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_MASK  (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_SHIFT (20U)
/*! LUTOUT84 - LUTOUT84 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_MASK  (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_SHIFT (21U)
/*! LUTOUT85 - LUTOUT85 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_MASK  (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_SHIFT (22U)
/*! LUTOUT86 - LUTOUT86 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_MASK  (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_SHIFT (23U)
/*! LUTOUT87 - LUTOUT87 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_MASK  (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_SHIFT (24U)
/*! LUTOUT88 - LUTOUT88 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_MASK  (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_SHIFT (25U)
/*! LUTOUT89 - LUTOUT89 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_MASK  (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_SHIFT (26U)
/*! LUTOUT90 - LUTOUT90 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_MASK  (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_SHIFT (27U)
/*! LUTOUT91 - LUTOUT91 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_MASK  (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_SHIFT (28U)
/*! LUTOUT92 - LUTOUT92 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_MASK  (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_SHIFT (29U)
/*! LUTOUT93 - LUTOUT93 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_MASK  (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_SHIFT (30U)
/*! LUTOUT94 - LUTOUT94 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_MASK  (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_SHIFT (31U)
/*! LUTOUT95 - LUTOUT95 */
#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT4_3 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_MASK  (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_SHIFT (0U)
/*! LUTOUT96 - LUTOUT96 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_MASK  (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_SHIFT (1U)
/*! LUTOUT97 - LUTOUT97 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_MASK  (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_SHIFT (2U)
/*! LUTOUT98 - LUTOUT98 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_MASK  (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_SHIFT (3U)
/*! LUTOUT99 - LUTOUT99 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_SHIFT (4U)
/*! LUTOUT100 - LUTOUT100 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_SHIFT (5U)
/*! LUTOUT101 - LUTOUT101 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_SHIFT (6U)
/*! LUTOUT102 - LUTOUT102 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_SHIFT (7U)
/*! LUTOUT103 - LUTOUT103 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_SHIFT (8U)
/*! LUTOUT104 - LUTOUT104 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_SHIFT (9U)
/*! LUTOUT105 - LUTOUT105 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_SHIFT (10U)
/*! LUTOUT106 - LUTOUT106 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_SHIFT (11U)
/*! LUTOUT107 - LUTOUT107 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_SHIFT (12U)
/*! LUTOUT108 - LUTOUT108 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_SHIFT (13U)
/*! LUTOUT109 - LUTOUT109 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_SHIFT (14U)
/*! LUTOUT110 - LUTOUT110 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_SHIFT (15U)
/*! LUTOUT111 - LUTOUT111 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_SHIFT (16U)
/*! LUTOUT112 - LUTOUT112 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_SHIFT (17U)
/*! LUTOUT113 - LUTOUT113 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_SHIFT (18U)
/*! LUTOUT114 - LUTOUT114 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_SHIFT (19U)
/*! LUTOUT115 - LUTOUT115 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_SHIFT (20U)
/*! LUTOUT116 - LUTOUT116 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_SHIFT (21U)
/*! LUTOUT117 - LUTOUT117 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_SHIFT (22U)
/*! LUTOUT118 - LUTOUT118 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_SHIFT (23U)
/*! LUTOUT119 - LUTOUT119 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_SHIFT (24U)
/*! LUTOUT120 - LUTOUT120 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_SHIFT (25U)
/*! LUTOUT121 - LUTOUT121 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_SHIFT (26U)
/*! LUTOUT122 - LUTOUT122 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_SHIFT (27U)
/*! LUTOUT123 - LUTOUT123 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_SHIFT (28U)
/*! LUTOUT124 - LUTOUT124 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_SHIFT (29U)
/*! LUTOUT125 - LUTOUT125 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_SHIFT (30U)
/*! LUTOUT126 - LUTOUT126 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_SHIFT (31U)
/*! LUTOUT127 - LUTOUT127 */
#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT4_4 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_SHIFT (0U)
/*! LUTOUT128 - LUTOUT128 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_SHIFT (1U)
/*! LUTOUT129 - LUTOUT129 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_SHIFT (2U)
/*! LUTOUT130 - LUTOUT130 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_SHIFT (3U)
/*! LUTOUT131 - LUTOUT131 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_SHIFT (4U)
/*! LUTOUT132 - LUTOUT132 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_SHIFT (5U)
/*! LUTOUT133 - LUTOUT133 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_SHIFT (6U)
/*! LUTOUT134 - LUTOUT134 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_SHIFT (7U)
/*! LUTOUT135 - LUTOUT135 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_SHIFT (8U)
/*! LUTOUT136 - LUTOUT136 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_SHIFT (9U)
/*! LUTOUT137 - LUTOUT137 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_SHIFT (10U)
/*! LUTOUT138 - LUTOUT138 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_SHIFT (11U)
/*! LUTOUT139 - LUTOUT139 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_SHIFT (12U)
/*! LUTOUT140 - LUTOUT140 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_SHIFT (13U)
/*! LUTOUT141 - LUTOUT141 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_SHIFT (14U)
/*! LUTOUT142 - LUTOUT142 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_SHIFT (15U)
/*! LUTOUT143 - LUTOUT143 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_SHIFT (16U)
/*! LUTOUT144 - LUTOUT144 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_SHIFT (17U)
/*! LUTOUT145 - LUTOUT145 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_SHIFT (18U)
/*! LUTOUT146 - LUTOUT146 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_SHIFT (19U)
/*! LUTOUT147 - LUTOUT147 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_SHIFT (20U)
/*! LUTOUT148 - LUTOUT148 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_SHIFT (21U)
/*! LUTOUT149 - LUTOUT149 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_SHIFT (22U)
/*! LUTOUT150 - LUTOUT150 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_SHIFT (23U)
/*! LUTOUT151 - LUTOUT151 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_SHIFT (24U)
/*! LUTOUT152 - LUTOUT152 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_SHIFT (25U)
/*! LUTOUT153 - LUTOUT153 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_SHIFT (26U)
/*! LUTOUT154 - LUTOUT154 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_SHIFT (27U)
/*! LUTOUT155 - LUTOUT155 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_SHIFT (28U)
/*! LUTOUT156 - LUTOUT156 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_SHIFT (29U)
/*! LUTOUT157 - LUTOUT157 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_SHIFT (30U)
/*! LUTOUT158 - LUTOUT158 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_SHIFT (31U)
/*! LUTOUT159 - LUTOUT159 */
#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT4_5 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_SHIFT (0U)
/*! LUTOUT160 - LUTOUT160 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_SHIFT (1U)
/*! LUTOUT161 - LUTOUT161 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_SHIFT (2U)
/*! LUTOUT162 - LUTOUT162 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_SHIFT (3U)
/*! LUTOUT163 - LUTOUT163 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_SHIFT (4U)
/*! LUTOUT164 - LUTOUT164 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_SHIFT (5U)
/*! LUTOUT165 - LUTOUT165 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_SHIFT (6U)
/*! LUTOUT166 - LUTOUT166 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_SHIFT (7U)
/*! LUTOUT167 - LUTOUT167 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_SHIFT (8U)
/*! LUTOUT168 - LUTOUT168 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_SHIFT (9U)
/*! LUTOUT169 - LUTOUT169 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_SHIFT (10U)
/*! LUTOUT170 - LUTOUT170 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_SHIFT (11U)
/*! LUTOUT171 - LUTOUT171 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_SHIFT (12U)
/*! LUTOUT172 - LUTOUT172 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_SHIFT (13U)
/*! LUTOUT173 - LUTOUT173 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_SHIFT (14U)
/*! LUTOUT174 - LUTOUT174 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_SHIFT (15U)
/*! LUTOUT175 - LUTOUT175 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_SHIFT (16U)
/*! LUTOUT176 - LUTOUT176 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_SHIFT (17U)
/*! LUTOUT177 - LUTOUT177 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_SHIFT (18U)
/*! LUTOUT178 - LUTOUT178 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_SHIFT (19U)
/*! LUTOUT179 - LUTOUT179 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_SHIFT (20U)
/*! LUTOUT180 - LUTOUT180 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_SHIFT (21U)
/*! LUTOUT181 - LUTOUT181 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_SHIFT (22U)
/*! LUTOUT182 - LUTOUT182 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_SHIFT (23U)
/*! LUTOUT183 - LUTOUT183 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_SHIFT (24U)
/*! LUTOUT184 - LUTOUT184 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_SHIFT (25U)
/*! LUTOUT185 - LUTOUT185 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_SHIFT (26U)
/*! LUTOUT186 - LUTOUT186 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_SHIFT (27U)
/*! LUTOUT187 - LUTOUT187 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_SHIFT (28U)
/*! LUTOUT188 - LUTOUT188 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_SHIFT (29U)
/*! LUTOUT189 - LUTOUT189 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_SHIFT (30U)
/*! LUTOUT190 - LUTOUT190 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_SHIFT (31U)
/*! LUTOUT191 - LUTOUT191 */
#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT4_6 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_SHIFT (0U)
/*! LUTOUT192 - LUTOUT192 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_SHIFT (1U)
/*! LUTOUT193 - LUTOUT193 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_SHIFT (2U)
/*! LUTOUT194 - LUTOUT194 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_SHIFT (3U)
/*! LUTOUT195 - LUTOUT195 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_SHIFT (4U)
/*! LUTOUT196 - LUTOUT196 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_SHIFT (5U)
/*! LUTOUT197 - LUTOUT197 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_SHIFT (6U)
/*! LUTOUT198 - LUTOUT198 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_SHIFT (7U)
/*! LUTOUT199 - LUTOUT199 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_SHIFT (8U)
/*! LUTOUT200 - LUTOUT200 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_SHIFT (9U)
/*! LUTOUT201 - LUTOUT201 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_SHIFT (10U)
/*! LUTOUT202 - LUTOUT202 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_SHIFT (11U)
/*! LUTOUT203 - LUTOUT203 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_SHIFT (12U)
/*! LUTOUT204 - LUTOUT204 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_SHIFT (13U)
/*! LUTOUT205 - LUTOUT205 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_SHIFT (14U)
/*! LUTOUT206 - LUTOUT206 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_SHIFT (15U)
/*! LUTOUT207 - LUTOUT207 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_SHIFT (16U)
/*! LUTOUT208 - LUTOUT208 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_SHIFT (17U)
/*! LUTOUT209 - LUTOUT209 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_SHIFT (18U)
/*! LUTOUT210 - LUTOUT210 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_SHIFT (19U)
/*! LUTOUT211 - LUTOUT211 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_SHIFT (20U)
/*! LUTOUT212 - LUTOUT212 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_SHIFT (21U)
/*! LUTOUT213 - LUTOUT213 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_SHIFT (22U)
/*! LUTOUT214 - LUTOUT214 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_SHIFT (23U)
/*! LUTOUT215 - LUTOUT215 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_SHIFT (24U)
/*! LUTOUT216 - LUTOUT216 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_SHIFT (25U)
/*! LUTOUT217 - LUTOUT217 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_SHIFT (26U)
/*! LUTOUT218 - LUTOUT218 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_SHIFT (27U)
/*! LUTOUT219 - LUTOUT219 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_SHIFT (28U)
/*! LUTOUT220 - LUTOUT220 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_SHIFT (29U)
/*! LUTOUT221 - LUTOUT221 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_SHIFT (30U)
/*! LUTOUT222 - LUTOUT222 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_SHIFT (31U)
/*! LUTOUT223 - LUTOUT223 */
#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_MASK)
/*! @} */

/*! @name WFE_B_STG1_8X1_OUT4_7 -  */
/*! @{ */

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_MASK (0x1U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_SHIFT (0U)
/*! LUTOUT224 - LUTOUT224 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_MASK (0x2U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_SHIFT (1U)
/*! LUTOUT225 - LUTOUT225 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_MASK (0x4U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_SHIFT (2U)
/*! LUTOUT226 - LUTOUT226 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_MASK (0x8U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_SHIFT (3U)
/*! LUTOUT227 - LUTOUT227 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_MASK (0x10U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_SHIFT (4U)
/*! LUTOUT228 - LUTOUT228 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_MASK (0x20U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_SHIFT (5U)
/*! LUTOUT229 - LUTOUT229 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_MASK (0x40U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_SHIFT (6U)
/*! LUTOUT230 - LUTOUT230 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_MASK (0x80U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_SHIFT (7U)
/*! LUTOUT231 - LUTOUT231 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_MASK (0x100U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_SHIFT (8U)
/*! LUTOUT232 - LUTOUT232 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_MASK (0x200U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_SHIFT (9U)
/*! LUTOUT233 - LUTOUT233 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_MASK (0x400U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_SHIFT (10U)
/*! LUTOUT234 - LUTOUT234 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_MASK (0x800U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_SHIFT (11U)
/*! LUTOUT235 - LUTOUT235 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_MASK (0x1000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_SHIFT (12U)
/*! LUTOUT236 - LUTOUT236 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_MASK (0x2000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_SHIFT (13U)
/*! LUTOUT237 - LUTOUT237 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_MASK (0x4000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_SHIFT (14U)
/*! LUTOUT238 - LUTOUT238 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_MASK (0x8000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_SHIFT (15U)
/*! LUTOUT239 - LUTOUT239 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_MASK (0x10000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_SHIFT (16U)
/*! LUTOUT240 - LUTOUT240 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_MASK (0x20000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_SHIFT (17U)
/*! LUTOUT241 - LUTOUT241 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_MASK (0x40000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_SHIFT (18U)
/*! LUTOUT242 - LUTOUT242 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_MASK (0x80000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_SHIFT (19U)
/*! LUTOUT243 - LUTOUT243 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_MASK (0x100000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_SHIFT (20U)
/*! LUTOUT244 - LUTOUT244 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_MASK (0x200000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_SHIFT (21U)
/*! LUTOUT245 - LUTOUT245 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_MASK (0x400000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_SHIFT (22U)
/*! LUTOUT246 - LUTOUT246 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_MASK (0x800000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_SHIFT (23U)
/*! LUTOUT247 - LUTOUT247 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_MASK (0x1000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_SHIFT (24U)
/*! LUTOUT248 - LUTOUT248 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_MASK (0x2000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_SHIFT (25U)
/*! LUTOUT249 - LUTOUT249 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_MASK (0x4000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_SHIFT (26U)
/*! LUTOUT250 - LUTOUT250 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_MASK (0x8000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_SHIFT (27U)
/*! LUTOUT251 - LUTOUT251 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_MASK (0x10000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_SHIFT (28U)
/*! LUTOUT252 - LUTOUT252 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_MASK (0x20000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_SHIFT (29U)
/*! LUTOUT253 - LUTOUT253 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_MASK (0x40000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_SHIFT (30U)
/*! LUTOUT254 - LUTOUT254 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_MASK)

#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_MASK (0x80000000U)
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_SHIFT (31U)
/*! LUTOUT255 - LUTOUT255 */
#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT0_0 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_MASK   (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_MASK   (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_SHIFT  (8U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_MASK   (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_SHIFT  (16U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_MASK   (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_SHIFT  (24U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT0_1 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_MASK   (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_SHIFT  (0U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_MASK   (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_SHIFT  (8U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_MASK   (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_SHIFT  (16U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_MASK   (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_SHIFT  (24U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT0_2 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_MASK   (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_SHIFT  (0U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_MASK   (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_SHIFT  (8U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_SHIFT (16U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_SHIFT (24U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT0_3 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_SHIFT (0U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_SHIFT (8U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_SHIFT (16U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_SHIFT (24U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT0_4 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_SHIFT (0U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_SHIFT (8U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_SHIFT (16U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_SHIFT (24U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT0_5 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_SHIFT (0U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_SHIFT (8U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_SHIFT (16U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_SHIFT (24U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT0_6 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_SHIFT (0U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_SHIFT (8U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_SHIFT (16U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_SHIFT (24U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT0_7 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_SHIFT (0U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_SHIFT (8U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_SHIFT (16U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_SHIFT (24U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_MASK)

#define PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT1_0 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_MASK   (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_MASK   (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_SHIFT  (8U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_MASK   (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_SHIFT  (16U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_MASK   (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_SHIFT  (24U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT1_1 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_MASK   (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_SHIFT  (0U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_MASK   (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_SHIFT  (8U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_MASK   (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_SHIFT  (16U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_MASK   (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_SHIFT  (24U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT1_2 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_MASK   (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_SHIFT  (0U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_MASK   (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_SHIFT  (8U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_SHIFT (16U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_SHIFT (24U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT1_3 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_SHIFT (0U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_SHIFT (8U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_SHIFT (16U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_SHIFT (24U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT1_4 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_SHIFT (0U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_SHIFT (8U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_SHIFT (16U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_SHIFT (24U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT1_5 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_SHIFT (0U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_SHIFT (8U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_SHIFT (16U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_SHIFT (24U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT1_6 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_SHIFT (0U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_SHIFT (8U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_SHIFT (16U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_SHIFT (24U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT1_7 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_SHIFT (0U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_SHIFT (8U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_SHIFT (16U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_SHIFT (24U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_MASK)

#define PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT2_0 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_MASK   (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_MASK   (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_SHIFT  (8U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_MASK   (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_SHIFT  (16U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_MASK   (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_SHIFT  (24U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT2_1 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_MASK   (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_SHIFT  (0U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_MASK   (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_SHIFT  (8U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_MASK   (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_SHIFT  (16U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_MASK   (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_SHIFT  (24U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT2_2 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_MASK   (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_SHIFT  (0U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_MASK   (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_SHIFT  (8U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_SHIFT (16U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_SHIFT (24U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT2_3 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_SHIFT (0U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_SHIFT (8U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_SHIFT (16U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_SHIFT (24U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT2_4 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_SHIFT (0U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_SHIFT (8U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_SHIFT (16U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_SHIFT (24U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT2_5 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_SHIFT (0U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_SHIFT (8U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_SHIFT (16U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_SHIFT (24U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT2_6 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_SHIFT (0U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_SHIFT (8U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_SHIFT (16U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_SHIFT (24U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT2_7 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_SHIFT (0U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_SHIFT (8U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_SHIFT (16U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_SHIFT (24U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_MASK)

#define PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT3_0 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_MASK   (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_SHIFT  (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_MASK   (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_SHIFT  (8U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_MASK   (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_SHIFT  (16U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_MASK   (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_SHIFT  (24U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT3_1 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_MASK   (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_SHIFT  (0U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_MASK   (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_SHIFT  (8U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_MASK   (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_SHIFT  (16U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_MASK   (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_SHIFT  (24U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT3_2 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_MASK   (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_SHIFT  (0U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_MASK   (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_SHIFT  (8U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_SHIFT (16U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_SHIFT (24U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT3_3 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_SHIFT (0U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_SHIFT (8U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_SHIFT (16U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_SHIFT (24U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT3_4 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_SHIFT (0U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_SHIFT (8U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_SHIFT (16U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_SHIFT (24U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT3_5 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_SHIFT (0U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_SHIFT (8U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_SHIFT (16U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_SHIFT (24U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT3_6 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_SHIFT (0U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_SHIFT (8U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_SHIFT (16U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_SHIFT (24U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X6_OUT3_7 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_MASK  (0x3FU)
#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_SHIFT (0U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3_MASK     (0xC0U)
#define PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3_SHIFT    (6U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_MASK  (0x3F00U)
#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_SHIFT (8U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2_MASK     (0xC000U)
#define PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2_SHIFT    (14U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_MASK  (0x3F0000U)
#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_SHIFT (16U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1_MASK     (0xC00000U)
#define PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1_SHIFT    (22U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_MASK  (0x3F000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_SHIFT (24U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_MASK)

#define PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0_MASK     (0xC0000000U)
#define PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0_SHIFT    (30U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_5X6_MASKS_0 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_MASK  (0x1FU)
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_SHIFT (0U)
/*! MASK0 - MASK0 */
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_MASK)

#define PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0_MASK  (0xE0U)
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0_SHIFT (5U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0_MASK)

#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_MASK  (0x1F00U)
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_SHIFT (8U)
/*! MASK1 - MASK1 */
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_MASK)

#define PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1_MASK  (0xE000U)
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1_SHIFT (13U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_MASK  (0x1F0000U)
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_SHIFT (16U)
/*! MASK2 - MASK2 */
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_MASK)

#define PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2_MASK  (0xE00000U)
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2_SHIFT (21U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_MASK  (0x1F000000U)
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_SHIFT (24U)
/*! MASK3 - MASK3 */
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_MASK)

#define PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3_MASK  (0xE0000000U)
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3_SHIFT (29U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3_MASK)
/*! @} */

/*! @name WFE_B_STAGE2_5X6_ADDR_0 -  */
/*! @{ */

#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_MASK (0x3FU)
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_SHIFT (0U)
/*! MUXADDR0 - MUXADDR0 */
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_MASK)

#define PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0_MASK   (0xC0U)
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0_SHIFT  (6U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0_MASK)

#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_MASK (0x3F00U)
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_SHIFT (8U)
/*! MUXADDR1 - MUXADDR1 */
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_MASK)

#define PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1_MASK   (0xC000U)
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1_SHIFT  (14U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1_MASK)

#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_MASK (0x3F0000U)
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_SHIFT (16U)
/*! MUXADDR2 - MUXADDR2 */
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_MASK)

#define PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2_MASK   (0xC00000U)
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2_SHIFT  (22U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2_MASK)

#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_MASK (0x3F000000U)
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_SHIFT (24U)
/*! MUXADDR3 - MUXADDR3 */
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_MASK)

#define PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3_MASK   (0xC0000000U)
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3_SHIFT  (30U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3(x)     (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X1_OUT0 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_MASK     (0x1U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_SHIFT    (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_MASK     (0x2U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_SHIFT    (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_MASK     (0x4U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_SHIFT    (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_MASK     (0x8U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_SHIFT    (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_MASK     (0x10U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_SHIFT    (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_MASK     (0x20U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_SHIFT    (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_MASK     (0x40U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_SHIFT    (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_MASK     (0x80U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_SHIFT    (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_MASK     (0x100U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_SHIFT    (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_MASK     (0x200U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_SHIFT    (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_MASK    (0x400U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_SHIFT   (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_MASK    (0x800U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_SHIFT   (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_MASK    (0x1000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_SHIFT   (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_MASK    (0x2000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_SHIFT   (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_MASK    (0x4000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_SHIFT   (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_MASK    (0x8000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_SHIFT   (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_MASK    (0x10000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_SHIFT   (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_MASK    (0x20000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_SHIFT   (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_MASK    (0x40000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_SHIFT   (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_MASK    (0x80000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_SHIFT   (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_MASK    (0x100000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_SHIFT   (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_MASK    (0x200000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_SHIFT   (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_MASK    (0x400000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_SHIFT   (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_MASK    (0x800000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_SHIFT   (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_MASK    (0x1000000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_SHIFT   (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_MASK    (0x2000000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_SHIFT   (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_MASK    (0x4000000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_SHIFT   (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_MASK    (0x8000000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_SHIFT   (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_MASK    (0x10000000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_SHIFT   (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_MASK    (0x20000000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_SHIFT   (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_MASK    (0x40000000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_SHIFT   (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_MASK)

#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_MASK    (0x80000000U)
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_SHIFT   (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X1_OUT1 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_MASK     (0x1U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_SHIFT    (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_MASK     (0x2U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_SHIFT    (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_MASK     (0x4U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_SHIFT    (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_MASK     (0x8U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_SHIFT    (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_MASK     (0x10U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_SHIFT    (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_MASK     (0x20U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_SHIFT    (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_MASK     (0x40U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_SHIFT    (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_MASK     (0x80U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_SHIFT    (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_MASK     (0x100U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_SHIFT    (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_MASK     (0x200U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_SHIFT    (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_MASK    (0x400U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_SHIFT   (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_MASK    (0x800U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_SHIFT   (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_MASK    (0x1000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_SHIFT   (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_MASK    (0x2000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_SHIFT   (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_MASK    (0x4000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_SHIFT   (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_MASK    (0x8000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_SHIFT   (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_MASK    (0x10000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_SHIFT   (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_MASK    (0x20000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_SHIFT   (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_MASK    (0x40000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_SHIFT   (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_MASK    (0x80000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_SHIFT   (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_MASK    (0x100000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_SHIFT   (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_MASK    (0x200000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_SHIFT   (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_MASK    (0x400000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_SHIFT   (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_MASK    (0x800000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_SHIFT   (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_MASK    (0x1000000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_SHIFT   (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_MASK    (0x2000000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_SHIFT   (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_MASK    (0x4000000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_SHIFT   (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_MASK    (0x8000000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_SHIFT   (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_MASK    (0x10000000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_SHIFT   (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_MASK    (0x20000000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_SHIFT   (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_MASK    (0x40000000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_SHIFT   (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_MASK)

#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_MASK    (0x80000000U)
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_SHIFT   (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X1_OUT2 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_MASK     (0x1U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_SHIFT    (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_MASK     (0x2U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_SHIFT    (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_MASK     (0x4U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_SHIFT    (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_MASK     (0x8U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_SHIFT    (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_MASK     (0x10U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_SHIFT    (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_MASK     (0x20U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_SHIFT    (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_MASK     (0x40U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_SHIFT    (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_MASK     (0x80U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_SHIFT    (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_MASK     (0x100U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_SHIFT    (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_MASK     (0x200U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_SHIFT    (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_MASK    (0x400U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_SHIFT   (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_MASK    (0x800U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_SHIFT   (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_MASK    (0x1000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_SHIFT   (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_MASK    (0x2000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_SHIFT   (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_MASK    (0x4000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_SHIFT   (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_MASK    (0x8000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_SHIFT   (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_MASK    (0x10000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_SHIFT   (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_MASK    (0x20000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_SHIFT   (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_MASK    (0x40000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_SHIFT   (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_MASK    (0x80000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_SHIFT   (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_MASK    (0x100000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_SHIFT   (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_MASK    (0x200000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_SHIFT   (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_MASK    (0x400000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_SHIFT   (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_MASK    (0x800000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_SHIFT   (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_MASK    (0x1000000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_SHIFT   (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_MASK    (0x2000000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_SHIFT   (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_MASK    (0x4000000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_SHIFT   (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_MASK    (0x8000000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_SHIFT   (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_MASK    (0x10000000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_SHIFT   (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_MASK    (0x20000000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_SHIFT   (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_MASK    (0x40000000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_SHIFT   (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_MASK)

#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_MASK    (0x80000000U)
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_SHIFT   (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X1_OUT3 -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_MASK     (0x1U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_SHIFT    (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_MASK     (0x2U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_SHIFT    (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_MASK     (0x4U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_SHIFT    (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_MASK     (0x8U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_SHIFT    (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_MASK     (0x10U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_SHIFT    (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_MASK     (0x20U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_SHIFT    (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_MASK     (0x40U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_SHIFT    (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_MASK     (0x80U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_SHIFT    (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_MASK     (0x100U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_SHIFT    (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_MASK     (0x200U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_SHIFT    (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_MASK    (0x400U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_SHIFT   (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_MASK    (0x800U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_SHIFT   (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_MASK    (0x1000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_SHIFT   (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_MASK    (0x2000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_SHIFT   (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_MASK    (0x4000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_SHIFT   (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_MASK    (0x8000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_SHIFT   (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_MASK    (0x10000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_SHIFT   (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_MASK    (0x20000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_SHIFT   (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_MASK    (0x40000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_SHIFT   (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_MASK    (0x80000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_SHIFT   (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_MASK    (0x100000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_SHIFT   (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_MASK    (0x200000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_SHIFT   (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_MASK    (0x400000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_SHIFT   (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_MASK    (0x800000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_SHIFT   (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_MASK    (0x1000000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_SHIFT   (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_MASK    (0x2000000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_SHIFT   (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_MASK    (0x4000000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_SHIFT   (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_MASK    (0x8000000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_SHIFT   (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_MASK    (0x10000000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_SHIFT   (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_MASK    (0x20000000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_SHIFT   (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_MASK    (0x40000000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_SHIFT   (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_MASK)

#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_MASK    (0x80000000U)
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_SHIFT   (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31(x)      (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG2_5X1_MASKS -  */
/*! @{ */

#define PXP_WFE_B_STG2_5X1_MASKS_MASK0_MASK      (0x1FU)
#define PXP_WFE_B_STG2_5X1_MASKS_MASK0_SHIFT     (0U)
/*! MASK0 - MASK0 */
#define PXP_WFE_B_STG2_5X1_MASKS_MASK0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK0_MASK)

#define PXP_WFE_B_STG2_5X1_MASKS_RSVD0_MASK      (0xE0U)
#define PXP_WFE_B_STG2_5X1_MASKS_RSVD0_SHIFT     (5U)
/*! RSVD0 - RSVD0 */
#define PXP_WFE_B_STG2_5X1_MASKS_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_RSVD0_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_RSVD0_MASK)

#define PXP_WFE_B_STG2_5X1_MASKS_MASK1_MASK      (0x1F00U)
#define PXP_WFE_B_STG2_5X1_MASKS_MASK1_SHIFT     (8U)
/*! MASK1 - MASK1 */
#define PXP_WFE_B_STG2_5X1_MASKS_MASK1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK1_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK1_MASK)

#define PXP_WFE_B_STG2_5X1_MASKS_RSVD1_MASK      (0xE000U)
#define PXP_WFE_B_STG2_5X1_MASKS_RSVD1_SHIFT     (13U)
/*! RSVD1 - RSVD1 */
#define PXP_WFE_B_STG2_5X1_MASKS_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_RSVD1_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_RSVD1_MASK)

#define PXP_WFE_B_STG2_5X1_MASKS_MASK2_MASK      (0x1F0000U)
#define PXP_WFE_B_STG2_5X1_MASKS_MASK2_SHIFT     (16U)
/*! MASK2 - MASK2 */
#define PXP_WFE_B_STG2_5X1_MASKS_MASK2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK2_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK2_MASK)

#define PXP_WFE_B_STG2_5X1_MASKS_RSVD2_MASK      (0xE00000U)
#define PXP_WFE_B_STG2_5X1_MASKS_RSVD2_SHIFT     (21U)
/*! RSVD2 - RSVD2 */
#define PXP_WFE_B_STG2_5X1_MASKS_RSVD2(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_RSVD2_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_RSVD2_MASK)

#define PXP_WFE_B_STG2_5X1_MASKS_MASK3_MASK      (0x1F000000U)
#define PXP_WFE_B_STG2_5X1_MASKS_MASK3_SHIFT     (24U)
/*! MASK3 - MASK3 */
#define PXP_WFE_B_STG2_5X1_MASKS_MASK3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK3_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK3_MASK)

#define PXP_WFE_B_STG2_5X1_MASKS_RSVD3_MASK      (0xE0000000U)
#define PXP_WFE_B_STG2_5X1_MASKS_RSVD3_SHIFT     (29U)
/*! RSVD3 - RSVD3 */
#define PXP_WFE_B_STG2_5X1_MASKS_RSVD3(x)        (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_RSVD3_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_RSVD3_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT0_0 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_MASK  (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_SHIFT (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_MASK  (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_SHIFT (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_MASK  (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_SHIFT (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_MASK  (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_SHIFT (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_MASK  (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_SHIFT (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_MASK  (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_SHIFT (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_MASK  (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_SHIFT (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_MASK  (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_SHIFT (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_MASK  (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_SHIFT (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_MASK  (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_SHIFT (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_SHIFT (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_SHIFT (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_SHIFT (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_SHIFT (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_SHIFT (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_SHIFT (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_SHIFT (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_SHIFT (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_SHIFT (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_SHIFT (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_SHIFT (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_SHIFT (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_SHIFT (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_SHIFT (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_SHIFT (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_SHIFT (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_SHIFT (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_SHIFT (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_SHIFT (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_SHIFT (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_SHIFT (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_SHIFT (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT0_1 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_SHIFT (0U)
/*! LUTOUT32 - LUTOUT32 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_SHIFT (1U)
/*! LUTOUT33 - LUTOUT33 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_SHIFT (2U)
/*! LUTOUT34 - LUTOUT34 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_SHIFT (3U)
/*! LUTOUT35 - LUTOUT35 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_SHIFT (4U)
/*! LUTOUT36 - LUTOUT36 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_SHIFT (5U)
/*! LUTOUT37 - LUTOUT37 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_SHIFT (6U)
/*! LUTOUT38 - LUTOUT38 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_SHIFT (7U)
/*! LUTOUT39 - LUTOUT39 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_SHIFT (8U)
/*! LUTOUT40 - LUTOUT40 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_SHIFT (9U)
/*! LUTOUT41 - LUTOUT41 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_SHIFT (10U)
/*! LUTOUT42 - LUTOUT42 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_SHIFT (11U)
/*! LUTOUT43 - LUTOUT43 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_SHIFT (12U)
/*! LUTOUT44 - LUTOUT44 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_SHIFT (13U)
/*! LUTOUT45 - LUTOUT45 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_SHIFT (14U)
/*! LUTOUT46 - LUTOUT46 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_SHIFT (15U)
/*! LUTOUT47 - LUTOUT47 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_SHIFT (16U)
/*! LUTOUT48 - LUTOUT48 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_SHIFT (17U)
/*! LUTOUT49 - LUTOUT49 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_SHIFT (18U)
/*! LUTOUT50 - LUTOUT50 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_SHIFT (19U)
/*! LUTOUT51 - LUTOUT51 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_SHIFT (20U)
/*! LUTOUT52 - LUTOUT52 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_SHIFT (21U)
/*! LUTOUT53 - LUTOUT53 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_SHIFT (22U)
/*! LUTOUT54 - LUTOUT54 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_SHIFT (23U)
/*! LUTOUT55 - LUTOUT55 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_SHIFT (24U)
/*! LUTOUT56 - LUTOUT56 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_SHIFT (25U)
/*! LUTOUT57 - LUTOUT57 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_SHIFT (26U)
/*! LUTOUT58 - LUTOUT58 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_SHIFT (27U)
/*! LUTOUT59 - LUTOUT59 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_SHIFT (28U)
/*! LUTOUT60 - LUTOUT60 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_SHIFT (29U)
/*! LUTOUT61 - LUTOUT61 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_SHIFT (30U)
/*! LUTOUT62 - LUTOUT62 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_SHIFT (31U)
/*! LUTOUT63 - LUTOUT63 */
#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT0_2 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_SHIFT (0U)
/*! LUTOUT64 - LUTOUT64 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_SHIFT (1U)
/*! LUTOUT65 - LUTOUT65 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_SHIFT (2U)
/*! LUTOUT66 - LUTOUT66 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_SHIFT (3U)
/*! LUTOUT67 - LUTOUT67 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_SHIFT (4U)
/*! LUTOUT68 - LUTOUT68 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_SHIFT (5U)
/*! LUTOUT69 - LUTOUT69 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_SHIFT (6U)
/*! LUTOUT70 - LUTOUT70 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_SHIFT (7U)
/*! LUTOUT71 - LUTOUT71 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_SHIFT (8U)
/*! LUTOUT72 - LUTOUT72 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_SHIFT (9U)
/*! LUTOUT73 - LUTOUT73 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_SHIFT (10U)
/*! LUTOUT74 - LUTOUT74 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_SHIFT (11U)
/*! LUTOUT75 - LUTOUT75 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_SHIFT (12U)
/*! LUTOUT76 - LUTOUT76 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_SHIFT (13U)
/*! LUTOUT77 - LUTOUT77 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_SHIFT (14U)
/*! LUTOUT78 - LUTOUT78 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_SHIFT (15U)
/*! LUTOUT79 - LUTOUT79 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_SHIFT (16U)
/*! LUTOUT80 - LUTOUT80 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_SHIFT (17U)
/*! LUTOUT81 - LUTOUT81 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_SHIFT (18U)
/*! LUTOUT82 - LUTOUT82 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_SHIFT (19U)
/*! LUTOUT83 - LUTOUT83 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_SHIFT (20U)
/*! LUTOUT84 - LUTOUT84 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_SHIFT (21U)
/*! LUTOUT85 - LUTOUT85 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_SHIFT (22U)
/*! LUTOUT86 - LUTOUT86 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_SHIFT (23U)
/*! LUTOUT87 - LUTOUT87 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_SHIFT (24U)
/*! LUTOUT88 - LUTOUT88 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_SHIFT (25U)
/*! LUTOUT89 - LUTOUT89 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_SHIFT (26U)
/*! LUTOUT90 - LUTOUT90 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_SHIFT (27U)
/*! LUTOUT91 - LUTOUT91 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_SHIFT (28U)
/*! LUTOUT92 - LUTOUT92 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_SHIFT (29U)
/*! LUTOUT93 - LUTOUT93 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_SHIFT (30U)
/*! LUTOUT94 - LUTOUT94 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_SHIFT (31U)
/*! LUTOUT95 - LUTOUT95 */
#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT0_3 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_SHIFT (0U)
/*! LUTOUT96 - LUTOUT96 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_SHIFT (1U)
/*! LUTOUT97 - LUTOUT97 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_SHIFT (2U)
/*! LUTOUT98 - LUTOUT98 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_SHIFT (3U)
/*! LUTOUT99 - LUTOUT99 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_SHIFT (4U)
/*! LUTOUT100 - LUTOUT100 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_SHIFT (5U)
/*! LUTOUT101 - LUTOUT101 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_SHIFT (6U)
/*! LUTOUT102 - LUTOUT102 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_SHIFT (7U)
/*! LUTOUT103 - LUTOUT103 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_SHIFT (8U)
/*! LUTOUT104 - LUTOUT104 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_SHIFT (9U)
/*! LUTOUT105 - LUTOUT105 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_SHIFT (10U)
/*! LUTOUT106 - LUTOUT106 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_SHIFT (11U)
/*! LUTOUT107 - LUTOUT107 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_SHIFT (12U)
/*! LUTOUT108 - LUTOUT108 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_SHIFT (13U)
/*! LUTOUT109 - LUTOUT109 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_SHIFT (14U)
/*! LUTOUT110 - LUTOUT110 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_SHIFT (15U)
/*! LUTOUT111 - LUTOUT111 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_SHIFT (16U)
/*! LUTOUT112 - LUTOUT112 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_SHIFT (17U)
/*! LUTOUT113 - LUTOUT113 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_SHIFT (18U)
/*! LUTOUT114 - LUTOUT114 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_SHIFT (19U)
/*! LUTOUT115 - LUTOUT115 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_SHIFT (20U)
/*! LUTOUT116 - LUTOUT116 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_SHIFT (21U)
/*! LUTOUT117 - LUTOUT117 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_SHIFT (22U)
/*! LUTOUT118 - LUTOUT118 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_SHIFT (23U)
/*! LUTOUT119 - LUTOUT119 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_SHIFT (24U)
/*! LUTOUT120 - LUTOUT120 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_SHIFT (25U)
/*! LUTOUT121 - LUTOUT121 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_SHIFT (26U)
/*! LUTOUT122 - LUTOUT122 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_SHIFT (27U)
/*! LUTOUT123 - LUTOUT123 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_SHIFT (28U)
/*! LUTOUT124 - LUTOUT124 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_SHIFT (29U)
/*! LUTOUT125 - LUTOUT125 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_SHIFT (30U)
/*! LUTOUT126 - LUTOUT126 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_SHIFT (31U)
/*! LUTOUT127 - LUTOUT127 */
#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT0_4 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_SHIFT (0U)
/*! LUTOUT128 - LUTOUT128 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_SHIFT (1U)
/*! LUTOUT129 - LUTOUT129 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_SHIFT (2U)
/*! LUTOUT130 - LUTOUT130 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_SHIFT (3U)
/*! LUTOUT131 - LUTOUT131 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_SHIFT (4U)
/*! LUTOUT132 - LUTOUT132 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_SHIFT (5U)
/*! LUTOUT133 - LUTOUT133 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_SHIFT (6U)
/*! LUTOUT134 - LUTOUT134 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_SHIFT (7U)
/*! LUTOUT135 - LUTOUT135 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_SHIFT (8U)
/*! LUTOUT136 - LUTOUT136 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_SHIFT (9U)
/*! LUTOUT137 - LUTOUT137 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_SHIFT (10U)
/*! LUTOUT138 - LUTOUT138 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_SHIFT (11U)
/*! LUTOUT139 - LUTOUT139 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_SHIFT (12U)
/*! LUTOUT140 - LUTOUT140 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_SHIFT (13U)
/*! LUTOUT141 - LUTOUT141 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_SHIFT (14U)
/*! LUTOUT142 - LUTOUT142 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_SHIFT (15U)
/*! LUTOUT143 - LUTOUT143 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_SHIFT (16U)
/*! LUTOUT144 - LUTOUT144 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_SHIFT (17U)
/*! LUTOUT145 - LUTOUT145 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_SHIFT (18U)
/*! LUTOUT146 - LUTOUT146 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_SHIFT (19U)
/*! LUTOUT147 - LUTOUT147 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_SHIFT (20U)
/*! LUTOUT148 - LUTOUT148 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_SHIFT (21U)
/*! LUTOUT149 - LUTOUT149 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_SHIFT (22U)
/*! LUTOUT150 - LUTOUT150 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_SHIFT (23U)
/*! LUTOUT151 - LUTOUT151 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_SHIFT (24U)
/*! LUTOUT152 - LUTOUT152 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_SHIFT (25U)
/*! LUTOUT153 - LUTOUT153 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_SHIFT (26U)
/*! LUTOUT154 - LUTOUT154 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_SHIFT (27U)
/*! LUTOUT155 - LUTOUT155 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_SHIFT (28U)
/*! LUTOUT156 - LUTOUT156 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_SHIFT (29U)
/*! LUTOUT157 - LUTOUT157 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_SHIFT (30U)
/*! LUTOUT158 - LUTOUT158 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_SHIFT (31U)
/*! LUTOUT159 - LUTOUT159 */
#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT0_5 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_SHIFT (0U)
/*! LUTOUT160 - LUTOUT160 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_SHIFT (1U)
/*! LUTOUT161 - LUTOUT161 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_SHIFT (2U)
/*! LUTOUT162 - LUTOUT162 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_SHIFT (3U)
/*! LUTOUT163 - LUTOUT163 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_SHIFT (4U)
/*! LUTOUT164 - LUTOUT164 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_SHIFT (5U)
/*! LUTOUT165 - LUTOUT165 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_SHIFT (6U)
/*! LUTOUT166 - LUTOUT166 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_SHIFT (7U)
/*! LUTOUT167 - LUTOUT167 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_SHIFT (8U)
/*! LUTOUT168 - LUTOUT168 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_SHIFT (9U)
/*! LUTOUT169 - LUTOUT169 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_SHIFT (10U)
/*! LUTOUT170 - LUTOUT170 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_SHIFT (11U)
/*! LUTOUT171 - LUTOUT171 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_SHIFT (12U)
/*! LUTOUT172 - LUTOUT172 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_SHIFT (13U)
/*! LUTOUT173 - LUTOUT173 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_SHIFT (14U)
/*! LUTOUT174 - LUTOUT174 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_SHIFT (15U)
/*! LUTOUT175 - LUTOUT175 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_SHIFT (16U)
/*! LUTOUT176 - LUTOUT176 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_SHIFT (17U)
/*! LUTOUT177 - LUTOUT177 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_SHIFT (18U)
/*! LUTOUT178 - LUTOUT178 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_SHIFT (19U)
/*! LUTOUT179 - LUTOUT179 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_SHIFT (20U)
/*! LUTOUT180 - LUTOUT180 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_SHIFT (21U)
/*! LUTOUT181 - LUTOUT181 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_SHIFT (22U)
/*! LUTOUT182 - LUTOUT182 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_SHIFT (23U)
/*! LUTOUT183 - LUTOUT183 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_SHIFT (24U)
/*! LUTOUT184 - LUTOUT184 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_SHIFT (25U)
/*! LUTOUT185 - LUTOUT185 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_SHIFT (26U)
/*! LUTOUT186 - LUTOUT186 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_SHIFT (27U)
/*! LUTOUT187 - LUTOUT187 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_SHIFT (28U)
/*! LUTOUT188 - LUTOUT188 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_SHIFT (29U)
/*! LUTOUT189 - LUTOUT189 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_SHIFT (30U)
/*! LUTOUT190 - LUTOUT190 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_SHIFT (31U)
/*! LUTOUT191 - LUTOUT191 */
#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT0_6 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_SHIFT (0U)
/*! LUTOUT192 - LUTOUT192 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_SHIFT (1U)
/*! LUTOUT193 - LUTOUT193 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_SHIFT (2U)
/*! LUTOUT194 - LUTOUT194 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_SHIFT (3U)
/*! LUTOUT195 - LUTOUT195 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_SHIFT (4U)
/*! LUTOUT196 - LUTOUT196 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_SHIFT (5U)
/*! LUTOUT197 - LUTOUT197 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_SHIFT (6U)
/*! LUTOUT198 - LUTOUT198 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_SHIFT (7U)
/*! LUTOUT199 - LUTOUT199 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_SHIFT (8U)
/*! LUTOUT200 - LUTOUT200 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_SHIFT (9U)
/*! LUTOUT201 - LUTOUT201 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_SHIFT (10U)
/*! LUTOUT202 - LUTOUT202 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_SHIFT (11U)
/*! LUTOUT203 - LUTOUT203 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_SHIFT (12U)
/*! LUTOUT204 - LUTOUT204 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_SHIFT (13U)
/*! LUTOUT205 - LUTOUT205 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_SHIFT (14U)
/*! LUTOUT206 - LUTOUT206 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_SHIFT (15U)
/*! LUTOUT207 - LUTOUT207 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_SHIFT (16U)
/*! LUTOUT208 - LUTOUT208 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_SHIFT (17U)
/*! LUTOUT209 - LUTOUT209 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_SHIFT (18U)
/*! LUTOUT210 - LUTOUT210 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_SHIFT (19U)
/*! LUTOUT211 - LUTOUT211 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_SHIFT (20U)
/*! LUTOUT212 - LUTOUT212 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_SHIFT (21U)
/*! LUTOUT213 - LUTOUT213 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_SHIFT (22U)
/*! LUTOUT214 - LUTOUT214 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_SHIFT (23U)
/*! LUTOUT215 - LUTOUT215 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_SHIFT (24U)
/*! LUTOUT216 - LUTOUT216 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_SHIFT (25U)
/*! LUTOUT217 - LUTOUT217 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_SHIFT (26U)
/*! LUTOUT218 - LUTOUT218 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_SHIFT (27U)
/*! LUTOUT219 - LUTOUT219 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_SHIFT (28U)
/*! LUTOUT220 - LUTOUT220 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_SHIFT (29U)
/*! LUTOUT221 - LUTOUT221 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_SHIFT (30U)
/*! LUTOUT222 - LUTOUT222 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_SHIFT (31U)
/*! LUTOUT223 - LUTOUT223 */
#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT0_7 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_SHIFT (0U)
/*! LUTOUT224 - LUTOUT224 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_SHIFT (1U)
/*! LUTOUT225 - LUTOUT225 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_SHIFT (2U)
/*! LUTOUT226 - LUTOUT226 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_SHIFT (3U)
/*! LUTOUT227 - LUTOUT227 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_SHIFT (4U)
/*! LUTOUT228 - LUTOUT228 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_SHIFT (5U)
/*! LUTOUT229 - LUTOUT229 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_SHIFT (6U)
/*! LUTOUT230 - LUTOUT230 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_SHIFT (7U)
/*! LUTOUT231 - LUTOUT231 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_SHIFT (8U)
/*! LUTOUT232 - LUTOUT232 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_SHIFT (9U)
/*! LUTOUT233 - LUTOUT233 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_SHIFT (10U)
/*! LUTOUT234 - LUTOUT234 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_SHIFT (11U)
/*! LUTOUT235 - LUTOUT235 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_SHIFT (12U)
/*! LUTOUT236 - LUTOUT236 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_SHIFT (13U)
/*! LUTOUT237 - LUTOUT237 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_SHIFT (14U)
/*! LUTOUT238 - LUTOUT238 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_SHIFT (15U)
/*! LUTOUT239 - LUTOUT239 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_SHIFT (16U)
/*! LUTOUT240 - LUTOUT240 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_SHIFT (17U)
/*! LUTOUT241 - LUTOUT241 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_SHIFT (18U)
/*! LUTOUT242 - LUTOUT242 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_SHIFT (19U)
/*! LUTOUT243 - LUTOUT243 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_SHIFT (20U)
/*! LUTOUT244 - LUTOUT244 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_SHIFT (21U)
/*! LUTOUT245 - LUTOUT245 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_SHIFT (22U)
/*! LUTOUT246 - LUTOUT246 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_SHIFT (23U)
/*! LUTOUT247 - LUTOUT247 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_SHIFT (24U)
/*! LUTOUT248 - LUTOUT248 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_SHIFT (25U)
/*! LUTOUT249 - LUTOUT249 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_SHIFT (26U)
/*! LUTOUT250 - LUTOUT250 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_SHIFT (27U)
/*! LUTOUT251 - LUTOUT251 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_SHIFT (28U)
/*! LUTOUT252 - LUTOUT252 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_SHIFT (29U)
/*! LUTOUT253 - LUTOUT253 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_SHIFT (30U)
/*! LUTOUT254 - LUTOUT254 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_SHIFT (31U)
/*! LUTOUT255 - LUTOUT255 */
#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT1_0 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_MASK  (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_SHIFT (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_MASK  (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_SHIFT (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_MASK  (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_SHIFT (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_MASK  (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_SHIFT (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_MASK  (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_SHIFT (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_MASK  (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_SHIFT (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_MASK  (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_SHIFT (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_MASK  (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_SHIFT (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_MASK  (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_SHIFT (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_MASK  (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_SHIFT (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_SHIFT (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_SHIFT (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_SHIFT (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_SHIFT (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_SHIFT (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_SHIFT (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_SHIFT (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_SHIFT (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_SHIFT (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_SHIFT (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_SHIFT (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_SHIFT (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_SHIFT (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_SHIFT (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_SHIFT (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_SHIFT (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_SHIFT (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_SHIFT (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_SHIFT (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_SHIFT (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_SHIFT (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_SHIFT (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT1_1 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_SHIFT (0U)
/*! LUTOUT32 - LUTOUT32 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_SHIFT (1U)
/*! LUTOUT33 - LUTOUT33 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_SHIFT (2U)
/*! LUTOUT34 - LUTOUT34 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_SHIFT (3U)
/*! LUTOUT35 - LUTOUT35 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_SHIFT (4U)
/*! LUTOUT36 - LUTOUT36 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_SHIFT (5U)
/*! LUTOUT37 - LUTOUT37 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_SHIFT (6U)
/*! LUTOUT38 - LUTOUT38 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_SHIFT (7U)
/*! LUTOUT39 - LUTOUT39 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_SHIFT (8U)
/*! LUTOUT40 - LUTOUT40 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_SHIFT (9U)
/*! LUTOUT41 - LUTOUT41 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_SHIFT (10U)
/*! LUTOUT42 - LUTOUT42 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_SHIFT (11U)
/*! LUTOUT43 - LUTOUT43 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_SHIFT (12U)
/*! LUTOUT44 - LUTOUT44 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_SHIFT (13U)
/*! LUTOUT45 - LUTOUT45 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_SHIFT (14U)
/*! LUTOUT46 - LUTOUT46 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_SHIFT (15U)
/*! LUTOUT47 - LUTOUT47 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_SHIFT (16U)
/*! LUTOUT48 - LUTOUT48 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_SHIFT (17U)
/*! LUTOUT49 - LUTOUT49 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_SHIFT (18U)
/*! LUTOUT50 - LUTOUT50 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_SHIFT (19U)
/*! LUTOUT51 - LUTOUT51 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_SHIFT (20U)
/*! LUTOUT52 - LUTOUT52 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_SHIFT (21U)
/*! LUTOUT53 - LUTOUT53 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_SHIFT (22U)
/*! LUTOUT54 - LUTOUT54 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_SHIFT (23U)
/*! LUTOUT55 - LUTOUT55 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_SHIFT (24U)
/*! LUTOUT56 - LUTOUT56 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_SHIFT (25U)
/*! LUTOUT57 - LUTOUT57 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_SHIFT (26U)
/*! LUTOUT58 - LUTOUT58 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_SHIFT (27U)
/*! LUTOUT59 - LUTOUT59 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_SHIFT (28U)
/*! LUTOUT60 - LUTOUT60 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_SHIFT (29U)
/*! LUTOUT61 - LUTOUT61 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_SHIFT (30U)
/*! LUTOUT62 - LUTOUT62 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_SHIFT (31U)
/*! LUTOUT63 - LUTOUT63 */
#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT1_2 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_SHIFT (0U)
/*! LUTOUT64 - LUTOUT64 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_SHIFT (1U)
/*! LUTOUT65 - LUTOUT65 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_SHIFT (2U)
/*! LUTOUT66 - LUTOUT66 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_SHIFT (3U)
/*! LUTOUT67 - LUTOUT67 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_SHIFT (4U)
/*! LUTOUT68 - LUTOUT68 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_SHIFT (5U)
/*! LUTOUT69 - LUTOUT69 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_SHIFT (6U)
/*! LUTOUT70 - LUTOUT70 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_SHIFT (7U)
/*! LUTOUT71 - LUTOUT71 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_SHIFT (8U)
/*! LUTOUT72 - LUTOUT72 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_SHIFT (9U)
/*! LUTOUT73 - LUTOUT73 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_SHIFT (10U)
/*! LUTOUT74 - LUTOUT74 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_SHIFT (11U)
/*! LUTOUT75 - LUTOUT75 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_SHIFT (12U)
/*! LUTOUT76 - LUTOUT76 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_SHIFT (13U)
/*! LUTOUT77 - LUTOUT77 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_SHIFT (14U)
/*! LUTOUT78 - LUTOUT78 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_SHIFT (15U)
/*! LUTOUT79 - LUTOUT79 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_SHIFT (16U)
/*! LUTOUT80 - LUTOUT80 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_SHIFT (17U)
/*! LUTOUT81 - LUTOUT81 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_SHIFT (18U)
/*! LUTOUT82 - LUTOUT82 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_SHIFT (19U)
/*! LUTOUT83 - LUTOUT83 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_SHIFT (20U)
/*! LUTOUT84 - LUTOUT84 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_SHIFT (21U)
/*! LUTOUT85 - LUTOUT85 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_SHIFT (22U)
/*! LUTOUT86 - LUTOUT86 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_SHIFT (23U)
/*! LUTOUT87 - LUTOUT87 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_SHIFT (24U)
/*! LUTOUT88 - LUTOUT88 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_SHIFT (25U)
/*! LUTOUT89 - LUTOUT89 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_SHIFT (26U)
/*! LUTOUT90 - LUTOUT90 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_SHIFT (27U)
/*! LUTOUT91 - LUTOUT91 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_SHIFT (28U)
/*! LUTOUT92 - LUTOUT92 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_SHIFT (29U)
/*! LUTOUT93 - LUTOUT93 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_SHIFT (30U)
/*! LUTOUT94 - LUTOUT94 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_SHIFT (31U)
/*! LUTOUT95 - LUTOUT95 */
#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT1_3 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_SHIFT (0U)
/*! LUTOUT96 - LUTOUT96 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_SHIFT (1U)
/*! LUTOUT97 - LUTOUT97 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_SHIFT (2U)
/*! LUTOUT98 - LUTOUT98 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_SHIFT (3U)
/*! LUTOUT99 - LUTOUT99 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_SHIFT (4U)
/*! LUTOUT100 - LUTOUT100 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_SHIFT (5U)
/*! LUTOUT101 - LUTOUT101 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_SHIFT (6U)
/*! LUTOUT102 - LUTOUT102 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_SHIFT (7U)
/*! LUTOUT103 - LUTOUT103 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_SHIFT (8U)
/*! LUTOUT104 - LUTOUT104 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_SHIFT (9U)
/*! LUTOUT105 - LUTOUT105 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_SHIFT (10U)
/*! LUTOUT106 - LUTOUT106 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_SHIFT (11U)
/*! LUTOUT107 - LUTOUT107 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_SHIFT (12U)
/*! LUTOUT108 - LUTOUT108 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_SHIFT (13U)
/*! LUTOUT109 - LUTOUT109 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_SHIFT (14U)
/*! LUTOUT110 - LUTOUT110 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_SHIFT (15U)
/*! LUTOUT111 - LUTOUT111 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_SHIFT (16U)
/*! LUTOUT112 - LUTOUT112 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_SHIFT (17U)
/*! LUTOUT113 - LUTOUT113 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_SHIFT (18U)
/*! LUTOUT114 - LUTOUT114 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_SHIFT (19U)
/*! LUTOUT115 - LUTOUT115 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_SHIFT (20U)
/*! LUTOUT116 - LUTOUT116 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_SHIFT (21U)
/*! LUTOUT117 - LUTOUT117 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_SHIFT (22U)
/*! LUTOUT118 - LUTOUT118 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_SHIFT (23U)
/*! LUTOUT119 - LUTOUT119 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_SHIFT (24U)
/*! LUTOUT120 - LUTOUT120 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_SHIFT (25U)
/*! LUTOUT121 - LUTOUT121 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_SHIFT (26U)
/*! LUTOUT122 - LUTOUT122 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_SHIFT (27U)
/*! LUTOUT123 - LUTOUT123 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_SHIFT (28U)
/*! LUTOUT124 - LUTOUT124 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_SHIFT (29U)
/*! LUTOUT125 - LUTOUT125 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_SHIFT (30U)
/*! LUTOUT126 - LUTOUT126 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_SHIFT (31U)
/*! LUTOUT127 - LUTOUT127 */
#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT1_4 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_SHIFT (0U)
/*! LUTOUT128 - LUTOUT128 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_SHIFT (1U)
/*! LUTOUT129 - LUTOUT129 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_SHIFT (2U)
/*! LUTOUT130 - LUTOUT130 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_SHIFT (3U)
/*! LUTOUT131 - LUTOUT131 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_SHIFT (4U)
/*! LUTOUT132 - LUTOUT132 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_SHIFT (5U)
/*! LUTOUT133 - LUTOUT133 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_SHIFT (6U)
/*! LUTOUT134 - LUTOUT134 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_SHIFT (7U)
/*! LUTOUT135 - LUTOUT135 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_SHIFT (8U)
/*! LUTOUT136 - LUTOUT136 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_SHIFT (9U)
/*! LUTOUT137 - LUTOUT137 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_SHIFT (10U)
/*! LUTOUT138 - LUTOUT138 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_SHIFT (11U)
/*! LUTOUT139 - LUTOUT139 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_SHIFT (12U)
/*! LUTOUT140 - LUTOUT140 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_SHIFT (13U)
/*! LUTOUT141 - LUTOUT141 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_SHIFT (14U)
/*! LUTOUT142 - LUTOUT142 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_SHIFT (15U)
/*! LUTOUT143 - LUTOUT143 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_SHIFT (16U)
/*! LUTOUT144 - LUTOUT144 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_SHIFT (17U)
/*! LUTOUT145 - LUTOUT145 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_SHIFT (18U)
/*! LUTOUT146 - LUTOUT146 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_SHIFT (19U)
/*! LUTOUT147 - LUTOUT147 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_SHIFT (20U)
/*! LUTOUT148 - LUTOUT148 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_SHIFT (21U)
/*! LUTOUT149 - LUTOUT149 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_SHIFT (22U)
/*! LUTOUT150 - LUTOUT150 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_SHIFT (23U)
/*! LUTOUT151 - LUTOUT151 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_SHIFT (24U)
/*! LUTOUT152 - LUTOUT152 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_SHIFT (25U)
/*! LUTOUT153 - LUTOUT153 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_SHIFT (26U)
/*! LUTOUT154 - LUTOUT154 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_SHIFT (27U)
/*! LUTOUT155 - LUTOUT155 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_SHIFT (28U)
/*! LUTOUT156 - LUTOUT156 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_SHIFT (29U)
/*! LUTOUT157 - LUTOUT157 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_SHIFT (30U)
/*! LUTOUT158 - LUTOUT158 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_SHIFT (31U)
/*! LUTOUT159 - LUTOUT159 */
#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT1_5 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_SHIFT (0U)
/*! LUTOUT160 - LUTOUT160 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_SHIFT (1U)
/*! LUTOUT161 - LUTOUT161 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_SHIFT (2U)
/*! LUTOUT162 - LUTOUT162 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_SHIFT (3U)
/*! LUTOUT163 - LUTOUT163 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_SHIFT (4U)
/*! LUTOUT164 - LUTOUT164 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_SHIFT (5U)
/*! LUTOUT165 - LUTOUT165 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_SHIFT (6U)
/*! LUTOUT166 - LUTOUT166 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_SHIFT (7U)
/*! LUTOUT167 - LUTOUT167 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_SHIFT (8U)
/*! LUTOUT168 - LUTOUT168 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_SHIFT (9U)
/*! LUTOUT169 - LUTOUT169 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_SHIFT (10U)
/*! LUTOUT170 - LUTOUT170 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_SHIFT (11U)
/*! LUTOUT171 - LUTOUT171 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_SHIFT (12U)
/*! LUTOUT172 - LUTOUT172 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_SHIFT (13U)
/*! LUTOUT173 - LUTOUT173 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_SHIFT (14U)
/*! LUTOUT174 - LUTOUT174 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_SHIFT (15U)
/*! LUTOUT175 - LUTOUT175 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_SHIFT (16U)
/*! LUTOUT176 - LUTOUT176 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_SHIFT (17U)
/*! LUTOUT177 - LUTOUT177 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_SHIFT (18U)
/*! LUTOUT178 - LUTOUT178 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_SHIFT (19U)
/*! LUTOUT179 - LUTOUT179 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_SHIFT (20U)
/*! LUTOUT180 - LUTOUT180 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_SHIFT (21U)
/*! LUTOUT181 - LUTOUT181 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_SHIFT (22U)
/*! LUTOUT182 - LUTOUT182 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_SHIFT (23U)
/*! LUTOUT183 - LUTOUT183 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_SHIFT (24U)
/*! LUTOUT184 - LUTOUT184 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_SHIFT (25U)
/*! LUTOUT185 - LUTOUT185 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_SHIFT (26U)
/*! LUTOUT186 - LUTOUT186 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_SHIFT (27U)
/*! LUTOUT187 - LUTOUT187 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_SHIFT (28U)
/*! LUTOUT188 - LUTOUT188 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_SHIFT (29U)
/*! LUTOUT189 - LUTOUT189 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_SHIFT (30U)
/*! LUTOUT190 - LUTOUT190 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_SHIFT (31U)
/*! LUTOUT191 - LUTOUT191 */
#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT1_6 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_SHIFT (0U)
/*! LUTOUT192 - LUTOUT192 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_SHIFT (1U)
/*! LUTOUT193 - LUTOUT193 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_SHIFT (2U)
/*! LUTOUT194 - LUTOUT194 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_SHIFT (3U)
/*! LUTOUT195 - LUTOUT195 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_SHIFT (4U)
/*! LUTOUT196 - LUTOUT196 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_SHIFT (5U)
/*! LUTOUT197 - LUTOUT197 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_SHIFT (6U)
/*! LUTOUT198 - LUTOUT198 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_SHIFT (7U)
/*! LUTOUT199 - LUTOUT199 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_SHIFT (8U)
/*! LUTOUT200 - LUTOUT200 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_SHIFT (9U)
/*! LUTOUT201 - LUTOUT201 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_SHIFT (10U)
/*! LUTOUT202 - LUTOUT202 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_SHIFT (11U)
/*! LUTOUT203 - LUTOUT203 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_SHIFT (12U)
/*! LUTOUT204 - LUTOUT204 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_SHIFT (13U)
/*! LUTOUT205 - LUTOUT205 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_SHIFT (14U)
/*! LUTOUT206 - LUTOUT206 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_SHIFT (15U)
/*! LUTOUT207 - LUTOUT207 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_SHIFT (16U)
/*! LUTOUT208 - LUTOUT208 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_SHIFT (17U)
/*! LUTOUT209 - LUTOUT209 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_SHIFT (18U)
/*! LUTOUT210 - LUTOUT210 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_SHIFT (19U)
/*! LUTOUT211 - LUTOUT211 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_SHIFT (20U)
/*! LUTOUT212 - LUTOUT212 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_SHIFT (21U)
/*! LUTOUT213 - LUTOUT213 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_SHIFT (22U)
/*! LUTOUT214 - LUTOUT214 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_SHIFT (23U)
/*! LUTOUT215 - LUTOUT215 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_SHIFT (24U)
/*! LUTOUT216 - LUTOUT216 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_SHIFT (25U)
/*! LUTOUT217 - LUTOUT217 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_SHIFT (26U)
/*! LUTOUT218 - LUTOUT218 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_SHIFT (27U)
/*! LUTOUT219 - LUTOUT219 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_SHIFT (28U)
/*! LUTOUT220 - LUTOUT220 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_SHIFT (29U)
/*! LUTOUT221 - LUTOUT221 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_SHIFT (30U)
/*! LUTOUT222 - LUTOUT222 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_SHIFT (31U)
/*! LUTOUT223 - LUTOUT223 */
#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT1_7 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_SHIFT (0U)
/*! LUTOUT224 - LUTOUT224 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_SHIFT (1U)
/*! LUTOUT225 - LUTOUT225 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_SHIFT (2U)
/*! LUTOUT226 - LUTOUT226 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_SHIFT (3U)
/*! LUTOUT227 - LUTOUT227 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_SHIFT (4U)
/*! LUTOUT228 - LUTOUT228 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_SHIFT (5U)
/*! LUTOUT229 - LUTOUT229 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_SHIFT (6U)
/*! LUTOUT230 - LUTOUT230 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_SHIFT (7U)
/*! LUTOUT231 - LUTOUT231 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_SHIFT (8U)
/*! LUTOUT232 - LUTOUT232 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_SHIFT (9U)
/*! LUTOUT233 - LUTOUT233 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_SHIFT (10U)
/*! LUTOUT234 - LUTOUT234 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_SHIFT (11U)
/*! LUTOUT235 - LUTOUT235 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_SHIFT (12U)
/*! LUTOUT236 - LUTOUT236 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_SHIFT (13U)
/*! LUTOUT237 - LUTOUT237 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_SHIFT (14U)
/*! LUTOUT238 - LUTOUT238 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_SHIFT (15U)
/*! LUTOUT239 - LUTOUT239 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_SHIFT (16U)
/*! LUTOUT240 - LUTOUT240 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_SHIFT (17U)
/*! LUTOUT241 - LUTOUT241 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_SHIFT (18U)
/*! LUTOUT242 - LUTOUT242 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_SHIFT (19U)
/*! LUTOUT243 - LUTOUT243 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_SHIFT (20U)
/*! LUTOUT244 - LUTOUT244 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_SHIFT (21U)
/*! LUTOUT245 - LUTOUT245 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_SHIFT (22U)
/*! LUTOUT246 - LUTOUT246 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_SHIFT (23U)
/*! LUTOUT247 - LUTOUT247 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_SHIFT (24U)
/*! LUTOUT248 - LUTOUT248 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_SHIFT (25U)
/*! LUTOUT249 - LUTOUT249 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_SHIFT (26U)
/*! LUTOUT250 - LUTOUT250 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_SHIFT (27U)
/*! LUTOUT251 - LUTOUT251 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_SHIFT (28U)
/*! LUTOUT252 - LUTOUT252 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_SHIFT (29U)
/*! LUTOUT253 - LUTOUT253 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_SHIFT (30U)
/*! LUTOUT254 - LUTOUT254 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_SHIFT (31U)
/*! LUTOUT255 - LUTOUT255 */
#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT2_0 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_MASK  (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_SHIFT (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_MASK  (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_SHIFT (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_MASK  (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_SHIFT (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_MASK  (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_SHIFT (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_MASK  (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_SHIFT (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_MASK  (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_SHIFT (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_MASK  (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_SHIFT (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_MASK  (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_SHIFT (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_MASK  (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_SHIFT (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_MASK  (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_SHIFT (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_SHIFT (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_SHIFT (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_SHIFT (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_SHIFT (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_SHIFT (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_SHIFT (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_SHIFT (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_SHIFT (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_SHIFT (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_SHIFT (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_SHIFT (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_SHIFT (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_SHIFT (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_SHIFT (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_SHIFT (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_SHIFT (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_SHIFT (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_SHIFT (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_SHIFT (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_SHIFT (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_SHIFT (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_SHIFT (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT2_1 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_SHIFT (0U)
/*! LUTOUT32 - LUTOUT32 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_SHIFT (1U)
/*! LUTOUT33 - LUTOUT33 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_SHIFT (2U)
/*! LUTOUT34 - LUTOUT34 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_SHIFT (3U)
/*! LUTOUT35 - LUTOUT35 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_SHIFT (4U)
/*! LUTOUT36 - LUTOUT36 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_SHIFT (5U)
/*! LUTOUT37 - LUTOUT37 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_SHIFT (6U)
/*! LUTOUT38 - LUTOUT38 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_SHIFT (7U)
/*! LUTOUT39 - LUTOUT39 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_SHIFT (8U)
/*! LUTOUT40 - LUTOUT40 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_SHIFT (9U)
/*! LUTOUT41 - LUTOUT41 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_SHIFT (10U)
/*! LUTOUT42 - LUTOUT42 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_SHIFT (11U)
/*! LUTOUT43 - LUTOUT43 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_SHIFT (12U)
/*! LUTOUT44 - LUTOUT44 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_SHIFT (13U)
/*! LUTOUT45 - LUTOUT45 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_SHIFT (14U)
/*! LUTOUT46 - LUTOUT46 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_SHIFT (15U)
/*! LUTOUT47 - LUTOUT47 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_SHIFT (16U)
/*! LUTOUT48 - LUTOUT48 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_SHIFT (17U)
/*! LUTOUT49 - LUTOUT49 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_SHIFT (18U)
/*! LUTOUT50 - LUTOUT50 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_SHIFT (19U)
/*! LUTOUT51 - LUTOUT51 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_SHIFT (20U)
/*! LUTOUT52 - LUTOUT52 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_SHIFT (21U)
/*! LUTOUT53 - LUTOUT53 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_SHIFT (22U)
/*! LUTOUT54 - LUTOUT54 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_SHIFT (23U)
/*! LUTOUT55 - LUTOUT55 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_SHIFT (24U)
/*! LUTOUT56 - LUTOUT56 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_SHIFT (25U)
/*! LUTOUT57 - LUTOUT57 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_SHIFT (26U)
/*! LUTOUT58 - LUTOUT58 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_SHIFT (27U)
/*! LUTOUT59 - LUTOUT59 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_SHIFT (28U)
/*! LUTOUT60 - LUTOUT60 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_SHIFT (29U)
/*! LUTOUT61 - LUTOUT61 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_SHIFT (30U)
/*! LUTOUT62 - LUTOUT62 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_SHIFT (31U)
/*! LUTOUT63 - LUTOUT63 */
#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT2_2 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_SHIFT (0U)
/*! LUTOUT64 - LUTOUT64 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_SHIFT (1U)
/*! LUTOUT65 - LUTOUT65 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_SHIFT (2U)
/*! LUTOUT66 - LUTOUT66 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_SHIFT (3U)
/*! LUTOUT67 - LUTOUT67 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_SHIFT (4U)
/*! LUTOUT68 - LUTOUT68 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_SHIFT (5U)
/*! LUTOUT69 - LUTOUT69 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_SHIFT (6U)
/*! LUTOUT70 - LUTOUT70 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_SHIFT (7U)
/*! LUTOUT71 - LUTOUT71 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_SHIFT (8U)
/*! LUTOUT72 - LUTOUT72 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_SHIFT (9U)
/*! LUTOUT73 - LUTOUT73 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_SHIFT (10U)
/*! LUTOUT74 - LUTOUT74 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_SHIFT (11U)
/*! LUTOUT75 - LUTOUT75 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_SHIFT (12U)
/*! LUTOUT76 - LUTOUT76 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_SHIFT (13U)
/*! LUTOUT77 - LUTOUT77 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_SHIFT (14U)
/*! LUTOUT78 - LUTOUT78 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_SHIFT (15U)
/*! LUTOUT79 - LUTOUT79 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_SHIFT (16U)
/*! LUTOUT80 - LUTOUT80 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_SHIFT (17U)
/*! LUTOUT81 - LUTOUT81 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_SHIFT (18U)
/*! LUTOUT82 - LUTOUT82 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_SHIFT (19U)
/*! LUTOUT83 - LUTOUT83 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_SHIFT (20U)
/*! LUTOUT84 - LUTOUT84 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_SHIFT (21U)
/*! LUTOUT85 - LUTOUT85 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_SHIFT (22U)
/*! LUTOUT86 - LUTOUT86 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_SHIFT (23U)
/*! LUTOUT87 - LUTOUT87 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_SHIFT (24U)
/*! LUTOUT88 - LUTOUT88 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_SHIFT (25U)
/*! LUTOUT89 - LUTOUT89 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_SHIFT (26U)
/*! LUTOUT90 - LUTOUT90 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_SHIFT (27U)
/*! LUTOUT91 - LUTOUT91 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_SHIFT (28U)
/*! LUTOUT92 - LUTOUT92 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_SHIFT (29U)
/*! LUTOUT93 - LUTOUT93 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_SHIFT (30U)
/*! LUTOUT94 - LUTOUT94 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_SHIFT (31U)
/*! LUTOUT95 - LUTOUT95 */
#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT2_3 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_SHIFT (0U)
/*! LUTOUT96 - LUTOUT96 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_SHIFT (1U)
/*! LUTOUT97 - LUTOUT97 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_SHIFT (2U)
/*! LUTOUT98 - LUTOUT98 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_SHIFT (3U)
/*! LUTOUT99 - LUTOUT99 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_SHIFT (4U)
/*! LUTOUT100 - LUTOUT100 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_SHIFT (5U)
/*! LUTOUT101 - LUTOUT101 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_SHIFT (6U)
/*! LUTOUT102 - LUTOUT102 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_SHIFT (7U)
/*! LUTOUT103 - LUTOUT103 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_SHIFT (8U)
/*! LUTOUT104 - LUTOUT104 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_SHIFT (9U)
/*! LUTOUT105 - LUTOUT105 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_SHIFT (10U)
/*! LUTOUT106 - LUTOUT106 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_SHIFT (11U)
/*! LUTOUT107 - LUTOUT107 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_SHIFT (12U)
/*! LUTOUT108 - LUTOUT108 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_SHIFT (13U)
/*! LUTOUT109 - LUTOUT109 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_SHIFT (14U)
/*! LUTOUT110 - LUTOUT110 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_SHIFT (15U)
/*! LUTOUT111 - LUTOUT111 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_SHIFT (16U)
/*! LUTOUT112 - LUTOUT112 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_SHIFT (17U)
/*! LUTOUT113 - LUTOUT113 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_SHIFT (18U)
/*! LUTOUT114 - LUTOUT114 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_SHIFT (19U)
/*! LUTOUT115 - LUTOUT115 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_SHIFT (20U)
/*! LUTOUT116 - LUTOUT116 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_SHIFT (21U)
/*! LUTOUT117 - LUTOUT117 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_SHIFT (22U)
/*! LUTOUT118 - LUTOUT118 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_SHIFT (23U)
/*! LUTOUT119 - LUTOUT119 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_SHIFT (24U)
/*! LUTOUT120 - LUTOUT120 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_SHIFT (25U)
/*! LUTOUT121 - LUTOUT121 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_SHIFT (26U)
/*! LUTOUT122 - LUTOUT122 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_SHIFT (27U)
/*! LUTOUT123 - LUTOUT123 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_SHIFT (28U)
/*! LUTOUT124 - LUTOUT124 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_SHIFT (29U)
/*! LUTOUT125 - LUTOUT125 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_SHIFT (30U)
/*! LUTOUT126 - LUTOUT126 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_SHIFT (31U)
/*! LUTOUT127 - LUTOUT127 */
#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT2_4 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_SHIFT (0U)
/*! LUTOUT128 - LUTOUT128 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_SHIFT (1U)
/*! LUTOUT129 - LUTOUT129 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_SHIFT (2U)
/*! LUTOUT130 - LUTOUT130 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_SHIFT (3U)
/*! LUTOUT131 - LUTOUT131 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_SHIFT (4U)
/*! LUTOUT132 - LUTOUT132 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_SHIFT (5U)
/*! LUTOUT133 - LUTOUT133 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_SHIFT (6U)
/*! LUTOUT134 - LUTOUT134 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_SHIFT (7U)
/*! LUTOUT135 - LUTOUT135 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_SHIFT (8U)
/*! LUTOUT136 - LUTOUT136 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_SHIFT (9U)
/*! LUTOUT137 - LUTOUT137 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_SHIFT (10U)
/*! LUTOUT138 - LUTOUT138 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_SHIFT (11U)
/*! LUTOUT139 - LUTOUT139 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_SHIFT (12U)
/*! LUTOUT140 - LUTOUT140 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_SHIFT (13U)
/*! LUTOUT141 - LUTOUT141 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_SHIFT (14U)
/*! LUTOUT142 - LUTOUT142 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_SHIFT (15U)
/*! LUTOUT143 - LUTOUT143 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_SHIFT (16U)
/*! LUTOUT144 - LUTOUT144 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_SHIFT (17U)
/*! LUTOUT145 - LUTOUT145 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_SHIFT (18U)
/*! LUTOUT146 - LUTOUT146 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_SHIFT (19U)
/*! LUTOUT147 - LUTOUT147 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_SHIFT (20U)
/*! LUTOUT148 - LUTOUT148 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_SHIFT (21U)
/*! LUTOUT149 - LUTOUT149 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_SHIFT (22U)
/*! LUTOUT150 - LUTOUT150 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_SHIFT (23U)
/*! LUTOUT151 - LUTOUT151 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_SHIFT (24U)
/*! LUTOUT152 - LUTOUT152 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_SHIFT (25U)
/*! LUTOUT153 - LUTOUT153 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_SHIFT (26U)
/*! LUTOUT154 - LUTOUT154 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_SHIFT (27U)
/*! LUTOUT155 - LUTOUT155 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_SHIFT (28U)
/*! LUTOUT156 - LUTOUT156 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_SHIFT (29U)
/*! LUTOUT157 - LUTOUT157 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_SHIFT (30U)
/*! LUTOUT158 - LUTOUT158 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_SHIFT (31U)
/*! LUTOUT159 - LUTOUT159 */
#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT2_5 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_SHIFT (0U)
/*! LUTOUT160 - LUTOUT160 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_SHIFT (1U)
/*! LUTOUT161 - LUTOUT161 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_SHIFT (2U)
/*! LUTOUT162 - LUTOUT162 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_SHIFT (3U)
/*! LUTOUT163 - LUTOUT163 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_SHIFT (4U)
/*! LUTOUT164 - LUTOUT164 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_SHIFT (5U)
/*! LUTOUT165 - LUTOUT165 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_SHIFT (6U)
/*! LUTOUT166 - LUTOUT166 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_SHIFT (7U)
/*! LUTOUT167 - LUTOUT167 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_SHIFT (8U)
/*! LUTOUT168 - LUTOUT168 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_SHIFT (9U)
/*! LUTOUT169 - LUTOUT169 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_SHIFT (10U)
/*! LUTOUT170 - LUTOUT170 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_SHIFT (11U)
/*! LUTOUT171 - LUTOUT171 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_SHIFT (12U)
/*! LUTOUT172 - LUTOUT172 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_SHIFT (13U)
/*! LUTOUT173 - LUTOUT173 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_SHIFT (14U)
/*! LUTOUT174 - LUTOUT174 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_SHIFT (15U)
/*! LUTOUT175 - LUTOUT175 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_SHIFT (16U)
/*! LUTOUT176 - LUTOUT176 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_SHIFT (17U)
/*! LUTOUT177 - LUTOUT177 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_SHIFT (18U)
/*! LUTOUT178 - LUTOUT178 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_SHIFT (19U)
/*! LUTOUT179 - LUTOUT179 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_SHIFT (20U)
/*! LUTOUT180 - LUTOUT180 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_SHIFT (21U)
/*! LUTOUT181 - LUTOUT181 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_SHIFT (22U)
/*! LUTOUT182 - LUTOUT182 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_SHIFT (23U)
/*! LUTOUT183 - LUTOUT183 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_SHIFT (24U)
/*! LUTOUT184 - LUTOUT184 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_SHIFT (25U)
/*! LUTOUT185 - LUTOUT185 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_SHIFT (26U)
/*! LUTOUT186 - LUTOUT186 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_SHIFT (27U)
/*! LUTOUT187 - LUTOUT187 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_SHIFT (28U)
/*! LUTOUT188 - LUTOUT188 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_SHIFT (29U)
/*! LUTOUT189 - LUTOUT189 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_SHIFT (30U)
/*! LUTOUT190 - LUTOUT190 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_SHIFT (31U)
/*! LUTOUT191 - LUTOUT191 */
#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT2_6 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_SHIFT (0U)
/*! LUTOUT192 - LUTOUT192 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_SHIFT (1U)
/*! LUTOUT193 - LUTOUT193 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_SHIFT (2U)
/*! LUTOUT194 - LUTOUT194 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_SHIFT (3U)
/*! LUTOUT195 - LUTOUT195 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_SHIFT (4U)
/*! LUTOUT196 - LUTOUT196 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_SHIFT (5U)
/*! LUTOUT197 - LUTOUT197 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_SHIFT (6U)
/*! LUTOUT198 - LUTOUT198 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_SHIFT (7U)
/*! LUTOUT199 - LUTOUT199 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_SHIFT (8U)
/*! LUTOUT200 - LUTOUT200 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_SHIFT (9U)
/*! LUTOUT201 - LUTOUT201 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_SHIFT (10U)
/*! LUTOUT202 - LUTOUT202 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_SHIFT (11U)
/*! LUTOUT203 - LUTOUT203 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_SHIFT (12U)
/*! LUTOUT204 - LUTOUT204 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_SHIFT (13U)
/*! LUTOUT205 - LUTOUT205 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_SHIFT (14U)
/*! LUTOUT206 - LUTOUT206 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_SHIFT (15U)
/*! LUTOUT207 - LUTOUT207 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_SHIFT (16U)
/*! LUTOUT208 - LUTOUT208 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_SHIFT (17U)
/*! LUTOUT209 - LUTOUT209 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_SHIFT (18U)
/*! LUTOUT210 - LUTOUT210 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_SHIFT (19U)
/*! LUTOUT211 - LUTOUT211 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_SHIFT (20U)
/*! LUTOUT212 - LUTOUT212 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_SHIFT (21U)
/*! LUTOUT213 - LUTOUT213 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_SHIFT (22U)
/*! LUTOUT214 - LUTOUT214 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_SHIFT (23U)
/*! LUTOUT215 - LUTOUT215 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_SHIFT (24U)
/*! LUTOUT216 - LUTOUT216 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_SHIFT (25U)
/*! LUTOUT217 - LUTOUT217 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_SHIFT (26U)
/*! LUTOUT218 - LUTOUT218 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_SHIFT (27U)
/*! LUTOUT219 - LUTOUT219 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_SHIFT (28U)
/*! LUTOUT220 - LUTOUT220 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_SHIFT (29U)
/*! LUTOUT221 - LUTOUT221 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_SHIFT (30U)
/*! LUTOUT222 - LUTOUT222 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_SHIFT (31U)
/*! LUTOUT223 - LUTOUT223 */
#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT2_7 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_SHIFT (0U)
/*! LUTOUT224 - LUTOUT224 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_SHIFT (1U)
/*! LUTOUT225 - LUTOUT225 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_SHIFT (2U)
/*! LUTOUT226 - LUTOUT226 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_SHIFT (3U)
/*! LUTOUT227 - LUTOUT227 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_SHIFT (4U)
/*! LUTOUT228 - LUTOUT228 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_SHIFT (5U)
/*! LUTOUT229 - LUTOUT229 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_SHIFT (6U)
/*! LUTOUT230 - LUTOUT230 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_SHIFT (7U)
/*! LUTOUT231 - LUTOUT231 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_SHIFT (8U)
/*! LUTOUT232 - LUTOUT232 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_SHIFT (9U)
/*! LUTOUT233 - LUTOUT233 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_SHIFT (10U)
/*! LUTOUT234 - LUTOUT234 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_SHIFT (11U)
/*! LUTOUT235 - LUTOUT235 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_SHIFT (12U)
/*! LUTOUT236 - LUTOUT236 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_SHIFT (13U)
/*! LUTOUT237 - LUTOUT237 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_SHIFT (14U)
/*! LUTOUT238 - LUTOUT238 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_SHIFT (15U)
/*! LUTOUT239 - LUTOUT239 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_SHIFT (16U)
/*! LUTOUT240 - LUTOUT240 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_SHIFT (17U)
/*! LUTOUT241 - LUTOUT241 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_SHIFT (18U)
/*! LUTOUT242 - LUTOUT242 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_SHIFT (19U)
/*! LUTOUT243 - LUTOUT243 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_SHIFT (20U)
/*! LUTOUT244 - LUTOUT244 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_SHIFT (21U)
/*! LUTOUT245 - LUTOUT245 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_SHIFT (22U)
/*! LUTOUT246 - LUTOUT246 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_SHIFT (23U)
/*! LUTOUT247 - LUTOUT247 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_SHIFT (24U)
/*! LUTOUT248 - LUTOUT248 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_SHIFT (25U)
/*! LUTOUT249 - LUTOUT249 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_SHIFT (26U)
/*! LUTOUT250 - LUTOUT250 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_SHIFT (27U)
/*! LUTOUT251 - LUTOUT251 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_SHIFT (28U)
/*! LUTOUT252 - LUTOUT252 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_SHIFT (29U)
/*! LUTOUT253 - LUTOUT253 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_SHIFT (30U)
/*! LUTOUT254 - LUTOUT254 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_SHIFT (31U)
/*! LUTOUT255 - LUTOUT255 */
#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT3_0 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_MASK  (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_SHIFT (0U)
/*! LUTOUT0 - LUTOUT0 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_MASK  (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_SHIFT (1U)
/*! LUTOUT1 - LUTOUT1 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_MASK  (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_SHIFT (2U)
/*! LUTOUT2 - LUTOUT2 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_MASK  (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_SHIFT (3U)
/*! LUTOUT3 - LUTOUT3 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_MASK  (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_SHIFT (4U)
/*! LUTOUT4 - LUTOUT4 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_MASK  (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_SHIFT (5U)
/*! LUTOUT5 - LUTOUT5 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_MASK  (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_SHIFT (6U)
/*! LUTOUT6 - LUTOUT6 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_MASK  (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_SHIFT (7U)
/*! LUTOUT7 - LUTOUT7 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_MASK  (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_SHIFT (8U)
/*! LUTOUT8 - LUTOUT8 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_MASK  (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_SHIFT (9U)
/*! LUTOUT9 - LUTOUT9 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9(x)    (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_SHIFT (10U)
/*! LUTOUT10 - LUTOUT10 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_SHIFT (11U)
/*! LUTOUT11 - LUTOUT11 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_SHIFT (12U)
/*! LUTOUT12 - LUTOUT12 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_SHIFT (13U)
/*! LUTOUT13 - LUTOUT13 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_SHIFT (14U)
/*! LUTOUT14 - LUTOUT14 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_SHIFT (15U)
/*! LUTOUT15 - LUTOUT15 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_SHIFT (16U)
/*! LUTOUT16 - LUTOUT16 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_SHIFT (17U)
/*! LUTOUT17 - LUTOUT17 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_SHIFT (18U)
/*! LUTOUT18 - LUTOUT18 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_SHIFT (19U)
/*! LUTOUT19 - LUTOUT19 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_SHIFT (20U)
/*! LUTOUT20 - LUTOUT20 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_SHIFT (21U)
/*! LUTOUT21 - LUTOUT21 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_SHIFT (22U)
/*! LUTOUT22 - LUTOUT22 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_SHIFT (23U)
/*! LUTOUT23 - LUTOUT23 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_SHIFT (24U)
/*! LUTOUT24 - LUTOUT24 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_SHIFT (25U)
/*! LUTOUT25 - LUTOUT25 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_SHIFT (26U)
/*! LUTOUT26 - LUTOUT26 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_SHIFT (27U)
/*! LUTOUT27 - LUTOUT27 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_SHIFT (28U)
/*! LUTOUT28 - LUTOUT28 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_SHIFT (29U)
/*! LUTOUT29 - LUTOUT29 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_SHIFT (30U)
/*! LUTOUT30 - LUTOUT30 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_SHIFT (31U)
/*! LUTOUT31 - LUTOUT31 */
#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT3_1 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_SHIFT (0U)
/*! LUTOUT32 - LUTOUT32 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_SHIFT (1U)
/*! LUTOUT33 - LUTOUT33 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_SHIFT (2U)
/*! LUTOUT34 - LUTOUT34 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_SHIFT (3U)
/*! LUTOUT35 - LUTOUT35 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_SHIFT (4U)
/*! LUTOUT36 - LUTOUT36 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_SHIFT (5U)
/*! LUTOUT37 - LUTOUT37 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_SHIFT (6U)
/*! LUTOUT38 - LUTOUT38 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_SHIFT (7U)
/*! LUTOUT39 - LUTOUT39 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_SHIFT (8U)
/*! LUTOUT40 - LUTOUT40 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_SHIFT (9U)
/*! LUTOUT41 - LUTOUT41 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_SHIFT (10U)
/*! LUTOUT42 - LUTOUT42 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_SHIFT (11U)
/*! LUTOUT43 - LUTOUT43 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_SHIFT (12U)
/*! LUTOUT44 - LUTOUT44 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_SHIFT (13U)
/*! LUTOUT45 - LUTOUT45 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_SHIFT (14U)
/*! LUTOUT46 - LUTOUT46 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_SHIFT (15U)
/*! LUTOUT47 - LUTOUT47 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_SHIFT (16U)
/*! LUTOUT48 - LUTOUT48 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_SHIFT (17U)
/*! LUTOUT49 - LUTOUT49 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_SHIFT (18U)
/*! LUTOUT50 - LUTOUT50 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_SHIFT (19U)
/*! LUTOUT51 - LUTOUT51 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_SHIFT (20U)
/*! LUTOUT52 - LUTOUT52 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_SHIFT (21U)
/*! LUTOUT53 - LUTOUT53 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_SHIFT (22U)
/*! LUTOUT54 - LUTOUT54 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_SHIFT (23U)
/*! LUTOUT55 - LUTOUT55 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_SHIFT (24U)
/*! LUTOUT56 - LUTOUT56 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_SHIFT (25U)
/*! LUTOUT57 - LUTOUT57 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_SHIFT (26U)
/*! LUTOUT58 - LUTOUT58 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_SHIFT (27U)
/*! LUTOUT59 - LUTOUT59 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_SHIFT (28U)
/*! LUTOUT60 - LUTOUT60 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_SHIFT (29U)
/*! LUTOUT61 - LUTOUT61 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_SHIFT (30U)
/*! LUTOUT62 - LUTOUT62 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_SHIFT (31U)
/*! LUTOUT63 - LUTOUT63 */
#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT3_2 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_SHIFT (0U)
/*! LUTOUT64 - LUTOUT64 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_SHIFT (1U)
/*! LUTOUT65 - LUTOUT65 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_SHIFT (2U)
/*! LUTOUT66 - LUTOUT66 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_SHIFT (3U)
/*! LUTOUT67 - LUTOUT67 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_SHIFT (4U)
/*! LUTOUT68 - LUTOUT68 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_SHIFT (5U)
/*! LUTOUT69 - LUTOUT69 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_SHIFT (6U)
/*! LUTOUT70 - LUTOUT70 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_SHIFT (7U)
/*! LUTOUT71 - LUTOUT71 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_SHIFT (8U)
/*! LUTOUT72 - LUTOUT72 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_SHIFT (9U)
/*! LUTOUT73 - LUTOUT73 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_SHIFT (10U)
/*! LUTOUT74 - LUTOUT74 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_SHIFT (11U)
/*! LUTOUT75 - LUTOUT75 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_SHIFT (12U)
/*! LUTOUT76 - LUTOUT76 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_SHIFT (13U)
/*! LUTOUT77 - LUTOUT77 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_SHIFT (14U)
/*! LUTOUT78 - LUTOUT78 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_SHIFT (15U)
/*! LUTOUT79 - LUTOUT79 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_SHIFT (16U)
/*! LUTOUT80 - LUTOUT80 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_SHIFT (17U)
/*! LUTOUT81 - LUTOUT81 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_SHIFT (18U)
/*! LUTOUT82 - LUTOUT82 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_SHIFT (19U)
/*! LUTOUT83 - LUTOUT83 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_SHIFT (20U)
/*! LUTOUT84 - LUTOUT84 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_SHIFT (21U)
/*! LUTOUT85 - LUTOUT85 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_SHIFT (22U)
/*! LUTOUT86 - LUTOUT86 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_SHIFT (23U)
/*! LUTOUT87 - LUTOUT87 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_SHIFT (24U)
/*! LUTOUT88 - LUTOUT88 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_SHIFT (25U)
/*! LUTOUT89 - LUTOUT89 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_SHIFT (26U)
/*! LUTOUT90 - LUTOUT90 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_SHIFT (27U)
/*! LUTOUT91 - LUTOUT91 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_SHIFT (28U)
/*! LUTOUT92 - LUTOUT92 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_SHIFT (29U)
/*! LUTOUT93 - LUTOUT93 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_SHIFT (30U)
/*! LUTOUT94 - LUTOUT94 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_SHIFT (31U)
/*! LUTOUT95 - LUTOUT95 */
#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT3_3 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_SHIFT (0U)
/*! LUTOUT96 - LUTOUT96 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_SHIFT (1U)
/*! LUTOUT97 - LUTOUT97 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_SHIFT (2U)
/*! LUTOUT98 - LUTOUT98 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_SHIFT (3U)
/*! LUTOUT99 - LUTOUT99 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99(x)   (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_SHIFT (4U)
/*! LUTOUT100 - LUTOUT100 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_SHIFT (5U)
/*! LUTOUT101 - LUTOUT101 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_SHIFT (6U)
/*! LUTOUT102 - LUTOUT102 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_SHIFT (7U)
/*! LUTOUT103 - LUTOUT103 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_SHIFT (8U)
/*! LUTOUT104 - LUTOUT104 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_SHIFT (9U)
/*! LUTOUT105 - LUTOUT105 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_SHIFT (10U)
/*! LUTOUT106 - LUTOUT106 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_SHIFT (11U)
/*! LUTOUT107 - LUTOUT107 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_SHIFT (12U)
/*! LUTOUT108 - LUTOUT108 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_SHIFT (13U)
/*! LUTOUT109 - LUTOUT109 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_SHIFT (14U)
/*! LUTOUT110 - LUTOUT110 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_SHIFT (15U)
/*! LUTOUT111 - LUTOUT111 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_SHIFT (16U)
/*! LUTOUT112 - LUTOUT112 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_SHIFT (17U)
/*! LUTOUT113 - LUTOUT113 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_SHIFT (18U)
/*! LUTOUT114 - LUTOUT114 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_SHIFT (19U)
/*! LUTOUT115 - LUTOUT115 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_SHIFT (20U)
/*! LUTOUT116 - LUTOUT116 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_SHIFT (21U)
/*! LUTOUT117 - LUTOUT117 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_SHIFT (22U)
/*! LUTOUT118 - LUTOUT118 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_SHIFT (23U)
/*! LUTOUT119 - LUTOUT119 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_SHIFT (24U)
/*! LUTOUT120 - LUTOUT120 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_SHIFT (25U)
/*! LUTOUT121 - LUTOUT121 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_SHIFT (26U)
/*! LUTOUT122 - LUTOUT122 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_SHIFT (27U)
/*! LUTOUT123 - LUTOUT123 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_SHIFT (28U)
/*! LUTOUT124 - LUTOUT124 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_SHIFT (29U)
/*! LUTOUT125 - LUTOUT125 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_SHIFT (30U)
/*! LUTOUT126 - LUTOUT126 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_SHIFT (31U)
/*! LUTOUT127 - LUTOUT127 */
#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT3_4 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_SHIFT (0U)
/*! LUTOUT128 - LUTOUT128 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_SHIFT (1U)
/*! LUTOUT129 - LUTOUT129 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_SHIFT (2U)
/*! LUTOUT130 - LUTOUT130 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_SHIFT (3U)
/*! LUTOUT131 - LUTOUT131 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_SHIFT (4U)
/*! LUTOUT132 - LUTOUT132 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_SHIFT (5U)
/*! LUTOUT133 - LUTOUT133 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_SHIFT (6U)
/*! LUTOUT134 - LUTOUT134 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_SHIFT (7U)
/*! LUTOUT135 - LUTOUT135 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_SHIFT (8U)
/*! LUTOUT136 - LUTOUT136 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_SHIFT (9U)
/*! LUTOUT137 - LUTOUT137 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_SHIFT (10U)
/*! LUTOUT138 - LUTOUT138 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_SHIFT (11U)
/*! LUTOUT139 - LUTOUT139 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_SHIFT (12U)
/*! LUTOUT140 - LUTOUT140 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_SHIFT (13U)
/*! LUTOUT141 - LUTOUT141 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_SHIFT (14U)
/*! LUTOUT142 - LUTOUT142 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_SHIFT (15U)
/*! LUTOUT143 - LUTOUT143 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_SHIFT (16U)
/*! LUTOUT144 - LUTOUT144 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_SHIFT (17U)
/*! LUTOUT145 - LUTOUT145 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_SHIFT (18U)
/*! LUTOUT146 - LUTOUT146 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_SHIFT (19U)
/*! LUTOUT147 - LUTOUT147 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_SHIFT (20U)
/*! LUTOUT148 - LUTOUT148 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_SHIFT (21U)
/*! LUTOUT149 - LUTOUT149 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_SHIFT (22U)
/*! LUTOUT150 - LUTOUT150 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_SHIFT (23U)
/*! LUTOUT151 - LUTOUT151 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_SHIFT (24U)
/*! LUTOUT152 - LUTOUT152 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_SHIFT (25U)
/*! LUTOUT153 - LUTOUT153 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_SHIFT (26U)
/*! LUTOUT154 - LUTOUT154 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_SHIFT (27U)
/*! LUTOUT155 - LUTOUT155 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_SHIFT (28U)
/*! LUTOUT156 - LUTOUT156 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_SHIFT (29U)
/*! LUTOUT157 - LUTOUT157 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_SHIFT (30U)
/*! LUTOUT158 - LUTOUT158 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_SHIFT (31U)
/*! LUTOUT159 - LUTOUT159 */
#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT3_5 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_SHIFT (0U)
/*! LUTOUT160 - LUTOUT160 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_SHIFT (1U)
/*! LUTOUT161 - LUTOUT161 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_SHIFT (2U)
/*! LUTOUT162 - LUTOUT162 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_SHIFT (3U)
/*! LUTOUT163 - LUTOUT163 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_SHIFT (4U)
/*! LUTOUT164 - LUTOUT164 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_SHIFT (5U)
/*! LUTOUT165 - LUTOUT165 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_SHIFT (6U)
/*! LUTOUT166 - LUTOUT166 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_SHIFT (7U)
/*! LUTOUT167 - LUTOUT167 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_SHIFT (8U)
/*! LUTOUT168 - LUTOUT168 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_SHIFT (9U)
/*! LUTOUT169 - LUTOUT169 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_SHIFT (10U)
/*! LUTOUT170 - LUTOUT170 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_SHIFT (11U)
/*! LUTOUT171 - LUTOUT171 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_SHIFT (12U)
/*! LUTOUT172 - LUTOUT172 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_SHIFT (13U)
/*! LUTOUT173 - LUTOUT173 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_SHIFT (14U)
/*! LUTOUT174 - LUTOUT174 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_SHIFT (15U)
/*! LUTOUT175 - LUTOUT175 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_SHIFT (16U)
/*! LUTOUT176 - LUTOUT176 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_SHIFT (17U)
/*! LUTOUT177 - LUTOUT177 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_SHIFT (18U)
/*! LUTOUT178 - LUTOUT178 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_SHIFT (19U)
/*! LUTOUT179 - LUTOUT179 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_SHIFT (20U)
/*! LUTOUT180 - LUTOUT180 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_SHIFT (21U)
/*! LUTOUT181 - LUTOUT181 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_SHIFT (22U)
/*! LUTOUT182 - LUTOUT182 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_SHIFT (23U)
/*! LUTOUT183 - LUTOUT183 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_SHIFT (24U)
/*! LUTOUT184 - LUTOUT184 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_SHIFT (25U)
/*! LUTOUT185 - LUTOUT185 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_SHIFT (26U)
/*! LUTOUT186 - LUTOUT186 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_SHIFT (27U)
/*! LUTOUT187 - LUTOUT187 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_SHIFT (28U)
/*! LUTOUT188 - LUTOUT188 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_SHIFT (29U)
/*! LUTOUT189 - LUTOUT189 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_SHIFT (30U)
/*! LUTOUT190 - LUTOUT190 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_SHIFT (31U)
/*! LUTOUT191 - LUTOUT191 */
#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT3_6 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_SHIFT (0U)
/*! LUTOUT192 - LUTOUT192 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_SHIFT (1U)
/*! LUTOUT193 - LUTOUT193 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_SHIFT (2U)
/*! LUTOUT194 - LUTOUT194 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_SHIFT (3U)
/*! LUTOUT195 - LUTOUT195 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_SHIFT (4U)
/*! LUTOUT196 - LUTOUT196 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_SHIFT (5U)
/*! LUTOUT197 - LUTOUT197 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_SHIFT (6U)
/*! LUTOUT198 - LUTOUT198 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_SHIFT (7U)
/*! LUTOUT199 - LUTOUT199 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_SHIFT (8U)
/*! LUTOUT200 - LUTOUT200 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_SHIFT (9U)
/*! LUTOUT201 - LUTOUT201 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_SHIFT (10U)
/*! LUTOUT202 - LUTOUT202 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_SHIFT (11U)
/*! LUTOUT203 - LUTOUT203 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_SHIFT (12U)
/*! LUTOUT204 - LUTOUT204 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_SHIFT (13U)
/*! LUTOUT205 - LUTOUT205 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_SHIFT (14U)
/*! LUTOUT206 - LUTOUT206 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_SHIFT (15U)
/*! LUTOUT207 - LUTOUT207 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_SHIFT (16U)
/*! LUTOUT208 - LUTOUT208 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_SHIFT (17U)
/*! LUTOUT209 - LUTOUT209 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_SHIFT (18U)
/*! LUTOUT210 - LUTOUT210 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_SHIFT (19U)
/*! LUTOUT211 - LUTOUT211 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_SHIFT (20U)
/*! LUTOUT212 - LUTOUT212 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_SHIFT (21U)
/*! LUTOUT213 - LUTOUT213 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_SHIFT (22U)
/*! LUTOUT214 - LUTOUT214 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_SHIFT (23U)
/*! LUTOUT215 - LUTOUT215 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_SHIFT (24U)
/*! LUTOUT216 - LUTOUT216 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_SHIFT (25U)
/*! LUTOUT217 - LUTOUT217 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_SHIFT (26U)
/*! LUTOUT218 - LUTOUT218 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_SHIFT (27U)
/*! LUTOUT219 - LUTOUT219 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_SHIFT (28U)
/*! LUTOUT220 - LUTOUT220 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_SHIFT (29U)
/*! LUTOUT221 - LUTOUT221 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_SHIFT (30U)
/*! LUTOUT222 - LUTOUT222 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_SHIFT (31U)
/*! LUTOUT223 - LUTOUT223 */
#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_OUT3_7 -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_MASK (0x1U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_SHIFT (0U)
/*! LUTOUT224 - LUTOUT224 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_MASK (0x2U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_SHIFT (1U)
/*! LUTOUT225 - LUTOUT225 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_MASK (0x4U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_SHIFT (2U)
/*! LUTOUT226 - LUTOUT226 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_MASK (0x8U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_SHIFT (3U)
/*! LUTOUT227 - LUTOUT227 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_MASK (0x10U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_SHIFT (4U)
/*! LUTOUT228 - LUTOUT228 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_MASK (0x20U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_SHIFT (5U)
/*! LUTOUT229 - LUTOUT229 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_MASK (0x40U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_SHIFT (6U)
/*! LUTOUT230 - LUTOUT230 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_MASK (0x80U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_SHIFT (7U)
/*! LUTOUT231 - LUTOUT231 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_MASK (0x100U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_SHIFT (8U)
/*! LUTOUT232 - LUTOUT232 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_MASK (0x200U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_SHIFT (9U)
/*! LUTOUT233 - LUTOUT233 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_MASK (0x400U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_SHIFT (10U)
/*! LUTOUT234 - LUTOUT234 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_MASK (0x800U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_SHIFT (11U)
/*! LUTOUT235 - LUTOUT235 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_MASK (0x1000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_SHIFT (12U)
/*! LUTOUT236 - LUTOUT236 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_MASK (0x2000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_SHIFT (13U)
/*! LUTOUT237 - LUTOUT237 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_MASK (0x4000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_SHIFT (14U)
/*! LUTOUT238 - LUTOUT238 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_MASK (0x8000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_SHIFT (15U)
/*! LUTOUT239 - LUTOUT239 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_MASK (0x10000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_SHIFT (16U)
/*! LUTOUT240 - LUTOUT240 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_MASK (0x20000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_SHIFT (17U)
/*! LUTOUT241 - LUTOUT241 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_MASK (0x40000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_SHIFT (18U)
/*! LUTOUT242 - LUTOUT242 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_MASK (0x80000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_SHIFT (19U)
/*! LUTOUT243 - LUTOUT243 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_MASK (0x100000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_SHIFT (20U)
/*! LUTOUT244 - LUTOUT244 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_MASK (0x200000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_SHIFT (21U)
/*! LUTOUT245 - LUTOUT245 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_MASK (0x400000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_SHIFT (22U)
/*! LUTOUT246 - LUTOUT246 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_MASK (0x800000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_SHIFT (23U)
/*! LUTOUT247 - LUTOUT247 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_MASK (0x1000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_SHIFT (24U)
/*! LUTOUT248 - LUTOUT248 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_MASK (0x2000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_SHIFT (25U)
/*! LUTOUT249 - LUTOUT249 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_MASK (0x4000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_SHIFT (26U)
/*! LUTOUT250 - LUTOUT250 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_MASK (0x8000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_SHIFT (27U)
/*! LUTOUT251 - LUTOUT251 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_MASK (0x10000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_SHIFT (28U)
/*! LUTOUT252 - LUTOUT252 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_MASK (0x20000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_SHIFT (29U)
/*! LUTOUT253 - LUTOUT253 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_MASK (0x40000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_SHIFT (30U)
/*! LUTOUT254 - LUTOUT254 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_MASK)

#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_MASK (0x80000000U)
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_SHIFT (31U)
/*! LUTOUT255 - LUTOUT255 */
#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255(x)  (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_MASK)
/*! @} */

/*! @name WFE_B_STG3_F8X1_MASKS -  */
/*! @{ */

#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0_MASK     (0xFFU)
#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0_SHIFT    (0U)
/*! MASK0 - MASK0 */
#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK0_MASK)

#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1_MASK     (0xFF00U)
#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1_SHIFT    (8U)
/*! MASK1 - MASK1 */
#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK1_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK1_MASK)

#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2_MASK     (0xFF0000U)
#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2_SHIFT    (16U)
/*! MASK2 - MASK2 */
#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK2_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK2_MASK)

#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3_MASK     (0xFF000000U)
#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3_SHIFT    (24U)
/*! MASK3 - MASK3 */
#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3(x)       (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK3_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK3_MASK)
/*! @} */

/*! @name ALU_A_CTRL -  */
/*! @{ */

#define PXP_ALU_A_CTRL_ENABLE_MASK               (0x1U)
#define PXP_ALU_A_CTRL_ENABLE_SHIFT              (0U)
/*! ENABLE - ENABLE
 *  0b0..Disable ALU
 *  0b1..Enable ALU
 */
#define PXP_ALU_A_CTRL_ENABLE(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_ENABLE_SHIFT)) & PXP_ALU_A_CTRL_ENABLE_MASK)

#define PXP_ALU_A_CTRL_RSVD6_MASK                (0xEU)
#define PXP_ALU_A_CTRL_RSVD6_SHIFT               (1U)
/*! RSVD6 - RSVD6 */
#define PXP_ALU_A_CTRL_RSVD6(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_RSVD6_SHIFT)) & PXP_ALU_A_CTRL_RSVD6_MASK)

#define PXP_ALU_A_CTRL_START_MASK                (0x10U)
#define PXP_ALU_A_CTRL_START_SHIFT               (4U)
/*! START - START */
#define PXP_ALU_A_CTRL_START(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_START_SHIFT)) & PXP_ALU_A_CTRL_START_MASK)

#define PXP_ALU_A_CTRL_RSVD5_MASK                (0xE0U)
#define PXP_ALU_A_CTRL_RSVD5_SHIFT               (5U)
/*! RSVD5 - RSVD5 */
#define PXP_ALU_A_CTRL_RSVD5(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_RSVD5_SHIFT)) & PXP_ALU_A_CTRL_RSVD5_MASK)

#define PXP_ALU_A_CTRL_SW_RESET_MASK             (0x100U)
#define PXP_ALU_A_CTRL_SW_RESET_SHIFT            (8U)
/*! SW_RESET - SW_RESET */
#define PXP_ALU_A_CTRL_SW_RESET(x)               (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SW_RESET_SHIFT)) & PXP_ALU_A_CTRL_SW_RESET_MASK)

#define PXP_ALU_A_CTRL_RSVD4_MASK                (0xE00U)
#define PXP_ALU_A_CTRL_RSVD4_SHIFT               (9U)
/*! RSVD4 - RSVD4 */
#define PXP_ALU_A_CTRL_RSVD4(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_RSVD4_SHIFT)) & PXP_ALU_A_CTRL_RSVD4_MASK)

#define PXP_ALU_A_CTRL_BYPASS_MASK               (0x1000U)
#define PXP_ALU_A_CTRL_BYPASS_SHIFT              (12U)
/*! BYPASS - BYPASS
 *  0b0..Normal Operation
 *  0b1..Bypass the ALU
 */
#define PXP_ALU_A_CTRL_BYPASS(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_BYPASS_SHIFT)) & PXP_ALU_A_CTRL_BYPASS_MASK)

#define PXP_ALU_A_CTRL_RSVD3_MASK                (0xE000U)
#define PXP_ALU_A_CTRL_RSVD3_SHIFT               (13U)
/*! RSVD3 - RSVD3 */
#define PXP_ALU_A_CTRL_RSVD3(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_RSVD3_SHIFT)) & PXP_ALU_A_CTRL_RSVD3_MASK)

#define PXP_ALU_A_CTRL_DONE_IRQ_FLAG_MASK        (0x10000U)
#define PXP_ALU_A_CTRL_DONE_IRQ_FLAG_SHIFT       (16U)
/*! DONE_IRQ_FLAG - DONE_IRQ_FLAG */
#define PXP_ALU_A_CTRL_DONE_IRQ_FLAG(x)          (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_A_CTRL_DONE_IRQ_FLAG_MASK)

#define PXP_ALU_A_CTRL_RSVD2_MASK                (0xE0000U)
#define PXP_ALU_A_CTRL_RSVD2_SHIFT               (17U)
/*! RSVD2 - RSVD2 */
#define PXP_ALU_A_CTRL_RSVD2(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_RSVD2_SHIFT)) & PXP_ALU_A_CTRL_RSVD2_MASK)

#define PXP_ALU_A_CTRL_DONE_IRQ_EN_MASK          (0x100000U)
#define PXP_ALU_A_CTRL_DONE_IRQ_EN_SHIFT         (20U)
/*! DONE_IRQ_EN - DONE_IRQ_EN */
#define PXP_ALU_A_CTRL_DONE_IRQ_EN(x)            (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_DONE_IRQ_EN_SHIFT)) & PXP_ALU_A_CTRL_DONE_IRQ_EN_MASK)

#define PXP_ALU_A_CTRL_RSVD1_MASK                (0xFE00000U)
#define PXP_ALU_A_CTRL_RSVD1_SHIFT               (21U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_A_CTRL_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_RSVD1_SHIFT)) & PXP_ALU_A_CTRL_RSVD1_MASK)

#define PXP_ALU_A_CTRL_DONE_MASK                 (0x10000000U)
#define PXP_ALU_A_CTRL_DONE_SHIFT                (28U)
/*! DONE - DONE */
#define PXP_ALU_A_CTRL_DONE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_DONE_SHIFT)) & PXP_ALU_A_CTRL_DONE_MASK)

#define PXP_ALU_A_CTRL_RSVD0_MASK                (0xE0000000U)
#define PXP_ALU_A_CTRL_RSVD0_SHIFT               (29U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_A_CTRL_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_RSVD0_SHIFT)) & PXP_ALU_A_CTRL_RSVD0_MASK)
/*! @} */

/*! @name ALU_A_CTRL_SET -  */
/*! @{ */

#define PXP_ALU_A_CTRL_SET_ENABLE_MASK           (0x1U)
#define PXP_ALU_A_CTRL_SET_ENABLE_SHIFT          (0U)
/*! ENABLE - ENABLE */
#define PXP_ALU_A_CTRL_SET_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_ENABLE_SHIFT)) & PXP_ALU_A_CTRL_SET_ENABLE_MASK)

#define PXP_ALU_A_CTRL_SET_RSVD6_MASK            (0xEU)
#define PXP_ALU_A_CTRL_SET_RSVD6_SHIFT           (1U)
/*! RSVD6 - RSVD6 */
#define PXP_ALU_A_CTRL_SET_RSVD6(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_RSVD6_SHIFT)) & PXP_ALU_A_CTRL_SET_RSVD6_MASK)

#define PXP_ALU_A_CTRL_SET_START_MASK            (0x10U)
#define PXP_ALU_A_CTRL_SET_START_SHIFT           (4U)
/*! START - START */
#define PXP_ALU_A_CTRL_SET_START(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_START_SHIFT)) & PXP_ALU_A_CTRL_SET_START_MASK)

#define PXP_ALU_A_CTRL_SET_RSVD5_MASK            (0xE0U)
#define PXP_ALU_A_CTRL_SET_RSVD5_SHIFT           (5U)
/*! RSVD5 - RSVD5 */
#define PXP_ALU_A_CTRL_SET_RSVD5(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_RSVD5_SHIFT)) & PXP_ALU_A_CTRL_SET_RSVD5_MASK)

#define PXP_ALU_A_CTRL_SET_SW_RESET_MASK         (0x100U)
#define PXP_ALU_A_CTRL_SET_SW_RESET_SHIFT        (8U)
/*! SW_RESET - SW_RESET */
#define PXP_ALU_A_CTRL_SET_SW_RESET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_SW_RESET_SHIFT)) & PXP_ALU_A_CTRL_SET_SW_RESET_MASK)

#define PXP_ALU_A_CTRL_SET_RSVD4_MASK            (0xE00U)
#define PXP_ALU_A_CTRL_SET_RSVD4_SHIFT           (9U)
/*! RSVD4 - RSVD4 */
#define PXP_ALU_A_CTRL_SET_RSVD4(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_RSVD4_SHIFT)) & PXP_ALU_A_CTRL_SET_RSVD4_MASK)

#define PXP_ALU_A_CTRL_SET_BYPASS_MASK           (0x1000U)
#define PXP_ALU_A_CTRL_SET_BYPASS_SHIFT          (12U)
/*! BYPASS - BYPASS */
#define PXP_ALU_A_CTRL_SET_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_BYPASS_SHIFT)) & PXP_ALU_A_CTRL_SET_BYPASS_MASK)

#define PXP_ALU_A_CTRL_SET_RSVD3_MASK            (0xE000U)
#define PXP_ALU_A_CTRL_SET_RSVD3_SHIFT           (13U)
/*! RSVD3 - RSVD3 */
#define PXP_ALU_A_CTRL_SET_RSVD3(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_RSVD3_SHIFT)) & PXP_ALU_A_CTRL_SET_RSVD3_MASK)

#define PXP_ALU_A_CTRL_SET_DONE_IRQ_FLAG_MASK    (0x10000U)
#define PXP_ALU_A_CTRL_SET_DONE_IRQ_FLAG_SHIFT   (16U)
/*! DONE_IRQ_FLAG - DONE_IRQ_FLAG */
#define PXP_ALU_A_CTRL_SET_DONE_IRQ_FLAG(x)      (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_A_CTRL_SET_DONE_IRQ_FLAG_MASK)

#define PXP_ALU_A_CTRL_SET_RSVD2_MASK            (0xE0000U)
#define PXP_ALU_A_CTRL_SET_RSVD2_SHIFT           (17U)
/*! RSVD2 - RSVD2 */
#define PXP_ALU_A_CTRL_SET_RSVD2(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_RSVD2_SHIFT)) & PXP_ALU_A_CTRL_SET_RSVD2_MASK)

#define PXP_ALU_A_CTRL_SET_DONE_IRQ_EN_MASK      (0x100000U)
#define PXP_ALU_A_CTRL_SET_DONE_IRQ_EN_SHIFT     (20U)
/*! DONE_IRQ_EN - DONE_IRQ_EN */
#define PXP_ALU_A_CTRL_SET_DONE_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_DONE_IRQ_EN_SHIFT)) & PXP_ALU_A_CTRL_SET_DONE_IRQ_EN_MASK)

#define PXP_ALU_A_CTRL_SET_RSVD1_MASK            (0xFE00000U)
#define PXP_ALU_A_CTRL_SET_RSVD1_SHIFT           (21U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_A_CTRL_SET_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_RSVD1_SHIFT)) & PXP_ALU_A_CTRL_SET_RSVD1_MASK)

#define PXP_ALU_A_CTRL_SET_DONE_MASK             (0x10000000U)
#define PXP_ALU_A_CTRL_SET_DONE_SHIFT            (28U)
/*! DONE - DONE */
#define PXP_ALU_A_CTRL_SET_DONE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_DONE_SHIFT)) & PXP_ALU_A_CTRL_SET_DONE_MASK)

#define PXP_ALU_A_CTRL_SET_RSVD0_MASK            (0xE0000000U)
#define PXP_ALU_A_CTRL_SET_RSVD0_SHIFT           (29U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_A_CTRL_SET_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_SET_RSVD0_SHIFT)) & PXP_ALU_A_CTRL_SET_RSVD0_MASK)
/*! @} */

/*! @name ALU_A_CTRL_CLR -  */
/*! @{ */

#define PXP_ALU_A_CTRL_CLR_ENABLE_MASK           (0x1U)
#define PXP_ALU_A_CTRL_CLR_ENABLE_SHIFT          (0U)
/*! ENABLE - ENABLE */
#define PXP_ALU_A_CTRL_CLR_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_ENABLE_SHIFT)) & PXP_ALU_A_CTRL_CLR_ENABLE_MASK)

#define PXP_ALU_A_CTRL_CLR_RSVD6_MASK            (0xEU)
#define PXP_ALU_A_CTRL_CLR_RSVD6_SHIFT           (1U)
/*! RSVD6 - RSVD6 */
#define PXP_ALU_A_CTRL_CLR_RSVD6(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_RSVD6_SHIFT)) & PXP_ALU_A_CTRL_CLR_RSVD6_MASK)

#define PXP_ALU_A_CTRL_CLR_START_MASK            (0x10U)
#define PXP_ALU_A_CTRL_CLR_START_SHIFT           (4U)
/*! START - START */
#define PXP_ALU_A_CTRL_CLR_START(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_START_SHIFT)) & PXP_ALU_A_CTRL_CLR_START_MASK)

#define PXP_ALU_A_CTRL_CLR_RSVD5_MASK            (0xE0U)
#define PXP_ALU_A_CTRL_CLR_RSVD5_SHIFT           (5U)
/*! RSVD5 - RSVD5 */
#define PXP_ALU_A_CTRL_CLR_RSVD5(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_RSVD5_SHIFT)) & PXP_ALU_A_CTRL_CLR_RSVD5_MASK)

#define PXP_ALU_A_CTRL_CLR_SW_RESET_MASK         (0x100U)
#define PXP_ALU_A_CTRL_CLR_SW_RESET_SHIFT        (8U)
/*! SW_RESET - SW_RESET */
#define PXP_ALU_A_CTRL_CLR_SW_RESET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_SW_RESET_SHIFT)) & PXP_ALU_A_CTRL_CLR_SW_RESET_MASK)

#define PXP_ALU_A_CTRL_CLR_RSVD4_MASK            (0xE00U)
#define PXP_ALU_A_CTRL_CLR_RSVD4_SHIFT           (9U)
/*! RSVD4 - RSVD4 */
#define PXP_ALU_A_CTRL_CLR_RSVD4(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_RSVD4_SHIFT)) & PXP_ALU_A_CTRL_CLR_RSVD4_MASK)

#define PXP_ALU_A_CTRL_CLR_BYPASS_MASK           (0x1000U)
#define PXP_ALU_A_CTRL_CLR_BYPASS_SHIFT          (12U)
/*! BYPASS - BYPASS */
#define PXP_ALU_A_CTRL_CLR_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_BYPASS_SHIFT)) & PXP_ALU_A_CTRL_CLR_BYPASS_MASK)

#define PXP_ALU_A_CTRL_CLR_RSVD3_MASK            (0xE000U)
#define PXP_ALU_A_CTRL_CLR_RSVD3_SHIFT           (13U)
/*! RSVD3 - RSVD3 */
#define PXP_ALU_A_CTRL_CLR_RSVD3(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_RSVD3_SHIFT)) & PXP_ALU_A_CTRL_CLR_RSVD3_MASK)

#define PXP_ALU_A_CTRL_CLR_DONE_IRQ_FLAG_MASK    (0x10000U)
#define PXP_ALU_A_CTRL_CLR_DONE_IRQ_FLAG_SHIFT   (16U)
/*! DONE_IRQ_FLAG - DONE_IRQ_FLAG */
#define PXP_ALU_A_CTRL_CLR_DONE_IRQ_FLAG(x)      (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_A_CTRL_CLR_DONE_IRQ_FLAG_MASK)

#define PXP_ALU_A_CTRL_CLR_RSVD2_MASK            (0xE0000U)
#define PXP_ALU_A_CTRL_CLR_RSVD2_SHIFT           (17U)
/*! RSVD2 - RSVD2 */
#define PXP_ALU_A_CTRL_CLR_RSVD2(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_RSVD2_SHIFT)) & PXP_ALU_A_CTRL_CLR_RSVD2_MASK)

#define PXP_ALU_A_CTRL_CLR_DONE_IRQ_EN_MASK      (0x100000U)
#define PXP_ALU_A_CTRL_CLR_DONE_IRQ_EN_SHIFT     (20U)
/*! DONE_IRQ_EN - DONE_IRQ_EN */
#define PXP_ALU_A_CTRL_CLR_DONE_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_DONE_IRQ_EN_SHIFT)) & PXP_ALU_A_CTRL_CLR_DONE_IRQ_EN_MASK)

#define PXP_ALU_A_CTRL_CLR_RSVD1_MASK            (0xFE00000U)
#define PXP_ALU_A_CTRL_CLR_RSVD1_SHIFT           (21U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_A_CTRL_CLR_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_RSVD1_SHIFT)) & PXP_ALU_A_CTRL_CLR_RSVD1_MASK)

#define PXP_ALU_A_CTRL_CLR_DONE_MASK             (0x10000000U)
#define PXP_ALU_A_CTRL_CLR_DONE_SHIFT            (28U)
/*! DONE - DONE */
#define PXP_ALU_A_CTRL_CLR_DONE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_DONE_SHIFT)) & PXP_ALU_A_CTRL_CLR_DONE_MASK)

#define PXP_ALU_A_CTRL_CLR_RSVD0_MASK            (0xE0000000U)
#define PXP_ALU_A_CTRL_CLR_RSVD0_SHIFT           (29U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_A_CTRL_CLR_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_CLR_RSVD0_SHIFT)) & PXP_ALU_A_CTRL_CLR_RSVD0_MASK)
/*! @} */

/*! @name ALU_A_CTRL_TOG -  */
/*! @{ */

#define PXP_ALU_A_CTRL_TOG_ENABLE_MASK           (0x1U)
#define PXP_ALU_A_CTRL_TOG_ENABLE_SHIFT          (0U)
/*! ENABLE - ENABLE */
#define PXP_ALU_A_CTRL_TOG_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_ENABLE_SHIFT)) & PXP_ALU_A_CTRL_TOG_ENABLE_MASK)

#define PXP_ALU_A_CTRL_TOG_RSVD6_MASK            (0xEU)
#define PXP_ALU_A_CTRL_TOG_RSVD6_SHIFT           (1U)
/*! RSVD6 - RSVD6 */
#define PXP_ALU_A_CTRL_TOG_RSVD6(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_RSVD6_SHIFT)) & PXP_ALU_A_CTRL_TOG_RSVD6_MASK)

#define PXP_ALU_A_CTRL_TOG_START_MASK            (0x10U)
#define PXP_ALU_A_CTRL_TOG_START_SHIFT           (4U)
/*! START - START */
#define PXP_ALU_A_CTRL_TOG_START(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_START_SHIFT)) & PXP_ALU_A_CTRL_TOG_START_MASK)

#define PXP_ALU_A_CTRL_TOG_RSVD5_MASK            (0xE0U)
#define PXP_ALU_A_CTRL_TOG_RSVD5_SHIFT           (5U)
/*! RSVD5 - RSVD5 */
#define PXP_ALU_A_CTRL_TOG_RSVD5(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_RSVD5_SHIFT)) & PXP_ALU_A_CTRL_TOG_RSVD5_MASK)

#define PXP_ALU_A_CTRL_TOG_SW_RESET_MASK         (0x100U)
#define PXP_ALU_A_CTRL_TOG_SW_RESET_SHIFT        (8U)
/*! SW_RESET - SW_RESET */
#define PXP_ALU_A_CTRL_TOG_SW_RESET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_SW_RESET_SHIFT)) & PXP_ALU_A_CTRL_TOG_SW_RESET_MASK)

#define PXP_ALU_A_CTRL_TOG_RSVD4_MASK            (0xE00U)
#define PXP_ALU_A_CTRL_TOG_RSVD4_SHIFT           (9U)
/*! RSVD4 - RSVD4 */
#define PXP_ALU_A_CTRL_TOG_RSVD4(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_RSVD4_SHIFT)) & PXP_ALU_A_CTRL_TOG_RSVD4_MASK)

#define PXP_ALU_A_CTRL_TOG_BYPASS_MASK           (0x1000U)
#define PXP_ALU_A_CTRL_TOG_BYPASS_SHIFT          (12U)
/*! BYPASS - BYPASS */
#define PXP_ALU_A_CTRL_TOG_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_BYPASS_SHIFT)) & PXP_ALU_A_CTRL_TOG_BYPASS_MASK)

#define PXP_ALU_A_CTRL_TOG_RSVD3_MASK            (0xE000U)
#define PXP_ALU_A_CTRL_TOG_RSVD3_SHIFT           (13U)
/*! RSVD3 - RSVD3 */
#define PXP_ALU_A_CTRL_TOG_RSVD3(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_RSVD3_SHIFT)) & PXP_ALU_A_CTRL_TOG_RSVD3_MASK)

#define PXP_ALU_A_CTRL_TOG_DONE_IRQ_FLAG_MASK    (0x10000U)
#define PXP_ALU_A_CTRL_TOG_DONE_IRQ_FLAG_SHIFT   (16U)
/*! DONE_IRQ_FLAG - DONE_IRQ_FLAG */
#define PXP_ALU_A_CTRL_TOG_DONE_IRQ_FLAG(x)      (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_A_CTRL_TOG_DONE_IRQ_FLAG_MASK)

#define PXP_ALU_A_CTRL_TOG_RSVD2_MASK            (0xE0000U)
#define PXP_ALU_A_CTRL_TOG_RSVD2_SHIFT           (17U)
/*! RSVD2 - RSVD2 */
#define PXP_ALU_A_CTRL_TOG_RSVD2(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_RSVD2_SHIFT)) & PXP_ALU_A_CTRL_TOG_RSVD2_MASK)

#define PXP_ALU_A_CTRL_TOG_DONE_IRQ_EN_MASK      (0x100000U)
#define PXP_ALU_A_CTRL_TOG_DONE_IRQ_EN_SHIFT     (20U)
/*! DONE_IRQ_EN - DONE_IRQ_EN */
#define PXP_ALU_A_CTRL_TOG_DONE_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_DONE_IRQ_EN_SHIFT)) & PXP_ALU_A_CTRL_TOG_DONE_IRQ_EN_MASK)

#define PXP_ALU_A_CTRL_TOG_RSVD1_MASK            (0xFE00000U)
#define PXP_ALU_A_CTRL_TOG_RSVD1_SHIFT           (21U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_A_CTRL_TOG_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_RSVD1_SHIFT)) & PXP_ALU_A_CTRL_TOG_RSVD1_MASK)

#define PXP_ALU_A_CTRL_TOG_DONE_MASK             (0x10000000U)
#define PXP_ALU_A_CTRL_TOG_DONE_SHIFT            (28U)
/*! DONE - DONE */
#define PXP_ALU_A_CTRL_TOG_DONE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_DONE_SHIFT)) & PXP_ALU_A_CTRL_TOG_DONE_MASK)

#define PXP_ALU_A_CTRL_TOG_RSVD0_MASK            (0xE0000000U)
#define PXP_ALU_A_CTRL_TOG_RSVD0_SHIFT           (29U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_A_CTRL_TOG_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CTRL_TOG_RSVD0_SHIFT)) & PXP_ALU_A_CTRL_TOG_RSVD0_MASK)
/*! @} */

/*! @name ALU_A_BUF_SIZE -  */
/*! @{ */

#define PXP_ALU_A_BUF_SIZE_BUF_WIDTH_MASK        (0x1FFFU)
#define PXP_ALU_A_BUF_SIZE_BUF_WIDTH_SHIFT       (0U)
/*! BUF_WIDTH - BUF_WIDTH */
#define PXP_ALU_A_BUF_SIZE_BUF_WIDTH(x)          (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_BUF_SIZE_BUF_WIDTH_SHIFT)) & PXP_ALU_A_BUF_SIZE_BUF_WIDTH_MASK)

#define PXP_ALU_A_BUF_SIZE_RSVD1_MASK            (0xE000U)
#define PXP_ALU_A_BUF_SIZE_RSVD1_SHIFT           (13U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_A_BUF_SIZE_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_BUF_SIZE_RSVD1_SHIFT)) & PXP_ALU_A_BUF_SIZE_RSVD1_MASK)

#define PXP_ALU_A_BUF_SIZE_BUF_HEIGHT_MASK       (0x1FFF0000U)
#define PXP_ALU_A_BUF_SIZE_BUF_HEIGHT_SHIFT      (16U)
/*! BUF_HEIGHT - BUF_HEIGHT */
#define PXP_ALU_A_BUF_SIZE_BUF_HEIGHT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_BUF_SIZE_BUF_HEIGHT_SHIFT)) & PXP_ALU_A_BUF_SIZE_BUF_HEIGHT_MASK)

#define PXP_ALU_A_BUF_SIZE_RSVD0_MASK            (0xE0000000U)
#define PXP_ALU_A_BUF_SIZE_RSVD0_SHIFT           (29U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_A_BUF_SIZE_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_BUF_SIZE_RSVD0_SHIFT)) & PXP_ALU_A_BUF_SIZE_RSVD0_MASK)
/*! @} */

/*! @name ALU_A_INST_ENTRY -  */
/*! @{ */

#define PXP_ALU_A_INST_ENTRY_ENTRY_ADDR_MASK     (0xFFFFU)
#define PXP_ALU_A_INST_ENTRY_ENTRY_ADDR_SHIFT    (0U)
/*! ENTRY_ADDR - ENTRY_ADDR */
#define PXP_ALU_A_INST_ENTRY_ENTRY_ADDR(x)       (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_INST_ENTRY_ENTRY_ADDR_SHIFT)) & PXP_ALU_A_INST_ENTRY_ENTRY_ADDR_MASK)

#define PXP_ALU_A_INST_ENTRY_RSVD0_MASK          (0xFFFF0000U)
#define PXP_ALU_A_INST_ENTRY_RSVD0_SHIFT         (16U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_A_INST_ENTRY_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_INST_ENTRY_RSVD0_SHIFT)) & PXP_ALU_A_INST_ENTRY_RSVD0_MASK)
/*! @} */

/*! @name ALU_A_PARAM -  */
/*! @{ */

#define PXP_ALU_A_PARAM_PARAM0_MASK              (0xFFU)
#define PXP_ALU_A_PARAM_PARAM0_SHIFT             (0U)
/*! PARAM0 - PARAM0 */
#define PXP_ALU_A_PARAM_PARAM0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_PARAM_PARAM0_SHIFT)) & PXP_ALU_A_PARAM_PARAM0_MASK)

#define PXP_ALU_A_PARAM_PARAM1_MASK              (0xFF00U)
#define PXP_ALU_A_PARAM_PARAM1_SHIFT             (8U)
/*! PARAM1 - PARAM1 */
#define PXP_ALU_A_PARAM_PARAM1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_PARAM_PARAM1_SHIFT)) & PXP_ALU_A_PARAM_PARAM1_MASK)

#define PXP_ALU_A_PARAM_RSVD0_MASK               (0xFFFF0000U)
#define PXP_ALU_A_PARAM_RSVD0_SHIFT              (16U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_A_PARAM_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_PARAM_RSVD0_SHIFT)) & PXP_ALU_A_PARAM_RSVD0_MASK)
/*! @} */

/*! @name ALU_A_CONFIG -  */
/*! @{ */

#define PXP_ALU_A_CONFIG_BUF_ADDR_MASK           (0xFFFFFFFFU)
#define PXP_ALU_A_CONFIG_BUF_ADDR_SHIFT          (0U)
/*! BUF_ADDR - BUF_ADDR */
#define PXP_ALU_A_CONFIG_BUF_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_CONFIG_BUF_ADDR_SHIFT)) & PXP_ALU_A_CONFIG_BUF_ADDR_MASK)
/*! @} */

/*! @name ALU_A_LUT_CONFIG -  */
/*! @{ */

#define PXP_ALU_A_LUT_CONFIG_EN_MASK             (0x1U)
#define PXP_ALU_A_LUT_CONFIG_EN_SHIFT            (0U)
/*! EN - EN */
#define PXP_ALU_A_LUT_CONFIG_EN(x)               (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_EN_SHIFT)) & PXP_ALU_A_LUT_CONFIG_EN_MASK)

#define PXP_ALU_A_LUT_CONFIG_RSVD1_MASK          (0xEU)
#define PXP_ALU_A_LUT_CONFIG_RSVD1_SHIFT         (1U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_A_LUT_CONFIG_RSVD1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_RSVD1_SHIFT)) & PXP_ALU_A_LUT_CONFIG_RSVD1_MASK)

#define PXP_ALU_A_LUT_CONFIG_MODE_MASK           (0x30U)
#define PXP_ALU_A_LUT_CONFIG_MODE_SHIFT          (4U)
/*! MODE - MODE
 *  0b00..Reserved
 *  0b01..6-bit mode
 *  0b10..5-bit mode
 *  0b11..4-bit mode
 */
#define PXP_ALU_A_LUT_CONFIG_MODE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_MODE_SHIFT)) & PXP_ALU_A_LUT_CONFIG_MODE_MASK)

#define PXP_ALU_A_LUT_CONFIG_RSVD0_MASK          (0xFFFFFFC0U)
#define PXP_ALU_A_LUT_CONFIG_RSVD0_SHIFT         (6U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_A_LUT_CONFIG_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_RSVD0_SHIFT)) & PXP_ALU_A_LUT_CONFIG_RSVD0_MASK)
/*! @} */

/*! @name ALU_A_LUT_CONFIG_SET -  */
/*! @{ */

#define PXP_ALU_A_LUT_CONFIG_SET_EN_MASK         (0x1U)
#define PXP_ALU_A_LUT_CONFIG_SET_EN_SHIFT        (0U)
/*! EN - EN */
#define PXP_ALU_A_LUT_CONFIG_SET_EN(x)           (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_SET_EN_SHIFT)) & PXP_ALU_A_LUT_CONFIG_SET_EN_MASK)

#define PXP_ALU_A_LUT_CONFIG_SET_RSVD1_MASK      (0xEU)
#define PXP_ALU_A_LUT_CONFIG_SET_RSVD1_SHIFT     (1U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_A_LUT_CONFIG_SET_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_SET_RSVD1_SHIFT)) & PXP_ALU_A_LUT_CONFIG_SET_RSVD1_MASK)

#define PXP_ALU_A_LUT_CONFIG_SET_MODE_MASK       (0x30U)
#define PXP_ALU_A_LUT_CONFIG_SET_MODE_SHIFT      (4U)
/*! MODE - MODE */
#define PXP_ALU_A_LUT_CONFIG_SET_MODE(x)         (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_SET_MODE_SHIFT)) & PXP_ALU_A_LUT_CONFIG_SET_MODE_MASK)

#define PXP_ALU_A_LUT_CONFIG_SET_RSVD0_MASK      (0xFFFFFFC0U)
#define PXP_ALU_A_LUT_CONFIG_SET_RSVD0_SHIFT     (6U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_A_LUT_CONFIG_SET_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_SET_RSVD0_SHIFT)) & PXP_ALU_A_LUT_CONFIG_SET_RSVD0_MASK)
/*! @} */

/*! @name ALU_A_LUT_CONFIG_CLR -  */
/*! @{ */

#define PXP_ALU_A_LUT_CONFIG_CLR_EN_MASK         (0x1U)
#define PXP_ALU_A_LUT_CONFIG_CLR_EN_SHIFT        (0U)
/*! EN - EN */
#define PXP_ALU_A_LUT_CONFIG_CLR_EN(x)           (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_CLR_EN_SHIFT)) & PXP_ALU_A_LUT_CONFIG_CLR_EN_MASK)

#define PXP_ALU_A_LUT_CONFIG_CLR_RSVD1_MASK      (0xEU)
#define PXP_ALU_A_LUT_CONFIG_CLR_RSVD1_SHIFT     (1U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_A_LUT_CONFIG_CLR_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_CLR_RSVD1_SHIFT)) & PXP_ALU_A_LUT_CONFIG_CLR_RSVD1_MASK)

#define PXP_ALU_A_LUT_CONFIG_CLR_MODE_MASK       (0x30U)
#define PXP_ALU_A_LUT_CONFIG_CLR_MODE_SHIFT      (4U)
/*! MODE - MODE */
#define PXP_ALU_A_LUT_CONFIG_CLR_MODE(x)         (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_CLR_MODE_SHIFT)) & PXP_ALU_A_LUT_CONFIG_CLR_MODE_MASK)

#define PXP_ALU_A_LUT_CONFIG_CLR_RSVD0_MASK      (0xFFFFFFC0U)
#define PXP_ALU_A_LUT_CONFIG_CLR_RSVD0_SHIFT     (6U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_A_LUT_CONFIG_CLR_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_CLR_RSVD0_SHIFT)) & PXP_ALU_A_LUT_CONFIG_CLR_RSVD0_MASK)
/*! @} */

/*! @name ALU_A_LUT_CONFIG_TOG -  */
/*! @{ */

#define PXP_ALU_A_LUT_CONFIG_TOG_EN_MASK         (0x1U)
#define PXP_ALU_A_LUT_CONFIG_TOG_EN_SHIFT        (0U)
/*! EN - EN */
#define PXP_ALU_A_LUT_CONFIG_TOG_EN(x)           (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_TOG_EN_SHIFT)) & PXP_ALU_A_LUT_CONFIG_TOG_EN_MASK)

#define PXP_ALU_A_LUT_CONFIG_TOG_RSVD1_MASK      (0xEU)
#define PXP_ALU_A_LUT_CONFIG_TOG_RSVD1_SHIFT     (1U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_A_LUT_CONFIG_TOG_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_TOG_RSVD1_SHIFT)) & PXP_ALU_A_LUT_CONFIG_TOG_RSVD1_MASK)

#define PXP_ALU_A_LUT_CONFIG_TOG_MODE_MASK       (0x30U)
#define PXP_ALU_A_LUT_CONFIG_TOG_MODE_SHIFT      (4U)
/*! MODE - MODE */
#define PXP_ALU_A_LUT_CONFIG_TOG_MODE(x)         (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_TOG_MODE_SHIFT)) & PXP_ALU_A_LUT_CONFIG_TOG_MODE_MASK)

#define PXP_ALU_A_LUT_CONFIG_TOG_RSVD0_MASK      (0xFFFFFFC0U)
#define PXP_ALU_A_LUT_CONFIG_TOG_RSVD0_SHIFT     (6U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_A_LUT_CONFIG_TOG_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_CONFIG_TOG_RSVD0_SHIFT)) & PXP_ALU_A_LUT_CONFIG_TOG_RSVD0_MASK)
/*! @} */

/*! @name ALU_A_LUT_DATA0 -  */
/*! @{ */

#define PXP_ALU_A_LUT_DATA0_LUT_DATA_L_MASK      (0xFFFFFFFFU)
#define PXP_ALU_A_LUT_DATA0_LUT_DATA_L_SHIFT     (0U)
/*! LUT_DATA_L - LUT_DATA_L */
#define PXP_ALU_A_LUT_DATA0_LUT_DATA_L(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_DATA0_LUT_DATA_L_SHIFT)) & PXP_ALU_A_LUT_DATA0_LUT_DATA_L_MASK)
/*! @} */

/*! @name ALU_A_LUT_DATA1 -  */
/*! @{ */

#define PXP_ALU_A_LUT_DATA1_LUT_DATA_H_MASK      (0xFFFFFFFFU)
#define PXP_ALU_A_LUT_DATA1_LUT_DATA_H_SHIFT     (0U)
/*! LUT_DATA_H - LUT_DATA_H */
#define PXP_ALU_A_LUT_DATA1_LUT_DATA_H(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_LUT_DATA1_LUT_DATA_H_SHIFT)) & PXP_ALU_A_LUT_DATA1_LUT_DATA_H_MASK)
/*! @} */

/*! @name ALU_A_DBG -  */
/*! @{ */

#define PXP_ALU_A_DBG_DEBUG_VALUE_MASK           (0xFFFFFFU)
#define PXP_ALU_A_DBG_DEBUG_VALUE_SHIFT          (0U)
/*! DEBUG_VALUE - DEBUG_VALUE */
#define PXP_ALU_A_DBG_DEBUG_VALUE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_DBG_DEBUG_VALUE_SHIFT)) & PXP_ALU_A_DBG_DEBUG_VALUE_MASK)

#define PXP_ALU_A_DBG_DEBUG_SEL_MASK             (0xFF000000U)
#define PXP_ALU_A_DBG_DEBUG_SEL_SHIFT            (24U)
/*! DEBUG_SEL - DEBUG_SEL */
#define PXP_ALU_A_DBG_DEBUG_SEL(x)               (((uint32_t)(((uint32_t)(x)) << PXP_ALU_A_DBG_DEBUG_SEL_SHIFT)) & PXP_ALU_A_DBG_DEBUG_SEL_MASK)
/*! @} */

/*! @name ALU_B_CTRL -  */
/*! @{ */

#define PXP_ALU_B_CTRL_ENABLE_MASK               (0x1U)
#define PXP_ALU_B_CTRL_ENABLE_SHIFT              (0U)
/*! ENABLE - ENABLE
 *  0b0..Disable ALU
 *  0b1..Enable ALU
 */
#define PXP_ALU_B_CTRL_ENABLE(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_ENABLE_MASK)

#define PXP_ALU_B_CTRL_RSVD6_MASK                (0xEU)
#define PXP_ALU_B_CTRL_RSVD6_SHIFT               (1U)
/*! RSVD6 - RSVD6 */
#define PXP_ALU_B_CTRL_RSVD6(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_RSVD6_SHIFT)) & PXP_ALU_B_CTRL_RSVD6_MASK)

#define PXP_ALU_B_CTRL_START_MASK                (0x10U)
#define PXP_ALU_B_CTRL_START_SHIFT               (4U)
/*! START - START */
#define PXP_ALU_B_CTRL_START(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_START_SHIFT)) & PXP_ALU_B_CTRL_START_MASK)

#define PXP_ALU_B_CTRL_RSVD5_MASK                (0xE0U)
#define PXP_ALU_B_CTRL_RSVD5_SHIFT               (5U)
/*! RSVD5 - RSVD5 */
#define PXP_ALU_B_CTRL_RSVD5(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_RSVD5_SHIFT)) & PXP_ALU_B_CTRL_RSVD5_MASK)

#define PXP_ALU_B_CTRL_SW_RESET_MASK             (0x100U)
#define PXP_ALU_B_CTRL_SW_RESET_SHIFT            (8U)
/*! SW_RESET - SW_RESET */
#define PXP_ALU_B_CTRL_SW_RESET(x)               (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_SW_RESET_MASK)

#define PXP_ALU_B_CTRL_RSVD4_MASK                (0xE00U)
#define PXP_ALU_B_CTRL_RSVD4_SHIFT               (9U)
/*! RSVD4 - RSVD4 */
#define PXP_ALU_B_CTRL_RSVD4(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_RSVD4_SHIFT)) & PXP_ALU_B_CTRL_RSVD4_MASK)

#define PXP_ALU_B_CTRL_BYPASS_MASK               (0x1000U)
#define PXP_ALU_B_CTRL_BYPASS_SHIFT              (12U)
/*! BYPASS - BYPASS
 *  0b0..Normal Operation
 *  0b1..Bypass the ALU
 */
#define PXP_ALU_B_CTRL_BYPASS(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_BYPASS_MASK)

#define PXP_ALU_B_CTRL_RSVD3_MASK                (0xE000U)
#define PXP_ALU_B_CTRL_RSVD3_SHIFT               (13U)
/*! RSVD3 - RSVD3 */
#define PXP_ALU_B_CTRL_RSVD3(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_RSVD3_SHIFT)) & PXP_ALU_B_CTRL_RSVD3_MASK)

#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG_MASK        (0x10000U)
#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG_SHIFT       (16U)
/*! DONE_IRQ_FLAG - DONE_IRQ_FLAG */
#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG(x)          (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_DONE_IRQ_FLAG_MASK)

#define PXP_ALU_B_CTRL_RSVD2_MASK                (0xE0000U)
#define PXP_ALU_B_CTRL_RSVD2_SHIFT               (17U)
/*! RSVD2 - RSVD2 */
#define PXP_ALU_B_CTRL_RSVD2(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_RSVD2_SHIFT)) & PXP_ALU_B_CTRL_RSVD2_MASK)

#define PXP_ALU_B_CTRL_DONE_IRQ_EN_MASK          (0x100000U)
#define PXP_ALU_B_CTRL_DONE_IRQ_EN_SHIFT         (20U)
/*! DONE_IRQ_EN - DONE_IRQ_EN */
#define PXP_ALU_B_CTRL_DONE_IRQ_EN(x)            (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_DONE_IRQ_EN_MASK)

#define PXP_ALU_B_CTRL_RSVD1_MASK                (0xFE00000U)
#define PXP_ALU_B_CTRL_RSVD1_SHIFT               (21U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_B_CTRL_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_RSVD1_SHIFT)) & PXP_ALU_B_CTRL_RSVD1_MASK)

#define PXP_ALU_B_CTRL_DONE_MASK                 (0x10000000U)
#define PXP_ALU_B_CTRL_DONE_SHIFT                (28U)
/*! DONE - DONE */
#define PXP_ALU_B_CTRL_DONE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_SHIFT)) & PXP_ALU_B_CTRL_DONE_MASK)

#define PXP_ALU_B_CTRL_RSVD0_MASK                (0xE0000000U)
#define PXP_ALU_B_CTRL_RSVD0_SHIFT               (29U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_B_CTRL_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_RSVD0_SHIFT)) & PXP_ALU_B_CTRL_RSVD0_MASK)
/*! @} */

/*! @name ALU_B_CTRL_SET -  */
/*! @{ */

#define PXP_ALU_B_CTRL_SET_ENABLE_MASK           (0x1U)
#define PXP_ALU_B_CTRL_SET_ENABLE_SHIFT          (0U)
/*! ENABLE - ENABLE */
#define PXP_ALU_B_CTRL_SET_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_SET_ENABLE_MASK)

#define PXP_ALU_B_CTRL_SET_RSVD6_MASK            (0xEU)
#define PXP_ALU_B_CTRL_SET_RSVD6_SHIFT           (1U)
/*! RSVD6 - RSVD6 */
#define PXP_ALU_B_CTRL_SET_RSVD6(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_RSVD6_SHIFT)) & PXP_ALU_B_CTRL_SET_RSVD6_MASK)

#define PXP_ALU_B_CTRL_SET_START_MASK            (0x10U)
#define PXP_ALU_B_CTRL_SET_START_SHIFT           (4U)
/*! START - START */
#define PXP_ALU_B_CTRL_SET_START(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_START_SHIFT)) & PXP_ALU_B_CTRL_SET_START_MASK)

#define PXP_ALU_B_CTRL_SET_RSVD5_MASK            (0xE0U)
#define PXP_ALU_B_CTRL_SET_RSVD5_SHIFT           (5U)
/*! RSVD5 - RSVD5 */
#define PXP_ALU_B_CTRL_SET_RSVD5(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_RSVD5_SHIFT)) & PXP_ALU_B_CTRL_SET_RSVD5_MASK)

#define PXP_ALU_B_CTRL_SET_SW_RESET_MASK         (0x100U)
#define PXP_ALU_B_CTRL_SET_SW_RESET_SHIFT        (8U)
/*! SW_RESET - SW_RESET */
#define PXP_ALU_B_CTRL_SET_SW_RESET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_SET_SW_RESET_MASK)

#define PXP_ALU_B_CTRL_SET_RSVD4_MASK            (0xE00U)
#define PXP_ALU_B_CTRL_SET_RSVD4_SHIFT           (9U)
/*! RSVD4 - RSVD4 */
#define PXP_ALU_B_CTRL_SET_RSVD4(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_RSVD4_SHIFT)) & PXP_ALU_B_CTRL_SET_RSVD4_MASK)

#define PXP_ALU_B_CTRL_SET_BYPASS_MASK           (0x1000U)
#define PXP_ALU_B_CTRL_SET_BYPASS_SHIFT          (12U)
/*! BYPASS - BYPASS */
#define PXP_ALU_B_CTRL_SET_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_SET_BYPASS_MASK)

#define PXP_ALU_B_CTRL_SET_RSVD3_MASK            (0xE000U)
#define PXP_ALU_B_CTRL_SET_RSVD3_SHIFT           (13U)
/*! RSVD3 - RSVD3 */
#define PXP_ALU_B_CTRL_SET_RSVD3(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_RSVD3_SHIFT)) & PXP_ALU_B_CTRL_SET_RSVD3_MASK)

#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_MASK    (0x10000U)
#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_SHIFT   (16U)
/*! DONE_IRQ_FLAG - DONE_IRQ_FLAG */
#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG(x)      (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_MASK)

#define PXP_ALU_B_CTRL_SET_RSVD2_MASK            (0xE0000U)
#define PXP_ALU_B_CTRL_SET_RSVD2_SHIFT           (17U)
/*! RSVD2 - RSVD2 */
#define PXP_ALU_B_CTRL_SET_RSVD2(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_RSVD2_SHIFT)) & PXP_ALU_B_CTRL_SET_RSVD2_MASK)

#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_MASK      (0x100000U)
#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_SHIFT     (20U)
/*! DONE_IRQ_EN - DONE_IRQ_EN */
#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_MASK)

#define PXP_ALU_B_CTRL_SET_RSVD1_MASK            (0xFE00000U)
#define PXP_ALU_B_CTRL_SET_RSVD1_SHIFT           (21U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_B_CTRL_SET_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_RSVD1_SHIFT)) & PXP_ALU_B_CTRL_SET_RSVD1_MASK)

#define PXP_ALU_B_CTRL_SET_DONE_MASK             (0x10000000U)
#define PXP_ALU_B_CTRL_SET_DONE_SHIFT            (28U)
/*! DONE - DONE */
#define PXP_ALU_B_CTRL_SET_DONE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_MASK)

#define PXP_ALU_B_CTRL_SET_RSVD0_MASK            (0xE0000000U)
#define PXP_ALU_B_CTRL_SET_RSVD0_SHIFT           (29U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_B_CTRL_SET_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_RSVD0_SHIFT)) & PXP_ALU_B_CTRL_SET_RSVD0_MASK)
/*! @} */

/*! @name ALU_B_CTRL_CLR -  */
/*! @{ */

#define PXP_ALU_B_CTRL_CLR_ENABLE_MASK           (0x1U)
#define PXP_ALU_B_CTRL_CLR_ENABLE_SHIFT          (0U)
/*! ENABLE - ENABLE */
#define PXP_ALU_B_CTRL_CLR_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_CLR_ENABLE_MASK)

#define PXP_ALU_B_CTRL_CLR_RSVD6_MASK            (0xEU)
#define PXP_ALU_B_CTRL_CLR_RSVD6_SHIFT           (1U)
/*! RSVD6 - RSVD6 */
#define PXP_ALU_B_CTRL_CLR_RSVD6(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_RSVD6_SHIFT)) & PXP_ALU_B_CTRL_CLR_RSVD6_MASK)

#define PXP_ALU_B_CTRL_CLR_START_MASK            (0x10U)
#define PXP_ALU_B_CTRL_CLR_START_SHIFT           (4U)
/*! START - START */
#define PXP_ALU_B_CTRL_CLR_START(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_START_SHIFT)) & PXP_ALU_B_CTRL_CLR_START_MASK)

#define PXP_ALU_B_CTRL_CLR_RSVD5_MASK            (0xE0U)
#define PXP_ALU_B_CTRL_CLR_RSVD5_SHIFT           (5U)
/*! RSVD5 - RSVD5 */
#define PXP_ALU_B_CTRL_CLR_RSVD5(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_RSVD5_SHIFT)) & PXP_ALU_B_CTRL_CLR_RSVD5_MASK)

#define PXP_ALU_B_CTRL_CLR_SW_RESET_MASK         (0x100U)
#define PXP_ALU_B_CTRL_CLR_SW_RESET_SHIFT        (8U)
/*! SW_RESET - SW_RESET */
#define PXP_ALU_B_CTRL_CLR_SW_RESET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_CLR_SW_RESET_MASK)

#define PXP_ALU_B_CTRL_CLR_RSVD4_MASK            (0xE00U)
#define PXP_ALU_B_CTRL_CLR_RSVD4_SHIFT           (9U)
/*! RSVD4 - RSVD4 */
#define PXP_ALU_B_CTRL_CLR_RSVD4(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_RSVD4_SHIFT)) & PXP_ALU_B_CTRL_CLR_RSVD4_MASK)

#define PXP_ALU_B_CTRL_CLR_BYPASS_MASK           (0x1000U)
#define PXP_ALU_B_CTRL_CLR_BYPASS_SHIFT          (12U)
/*! BYPASS - BYPASS */
#define PXP_ALU_B_CTRL_CLR_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_CLR_BYPASS_MASK)

#define PXP_ALU_B_CTRL_CLR_RSVD3_MASK            (0xE000U)
#define PXP_ALU_B_CTRL_CLR_RSVD3_SHIFT           (13U)
/*! RSVD3 - RSVD3 */
#define PXP_ALU_B_CTRL_CLR_RSVD3(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_RSVD3_SHIFT)) & PXP_ALU_B_CTRL_CLR_RSVD3_MASK)

#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_MASK    (0x10000U)
#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_SHIFT   (16U)
/*! DONE_IRQ_FLAG - DONE_IRQ_FLAG */
#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG(x)      (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_MASK)

#define PXP_ALU_B_CTRL_CLR_RSVD2_MASK            (0xE0000U)
#define PXP_ALU_B_CTRL_CLR_RSVD2_SHIFT           (17U)
/*! RSVD2 - RSVD2 */
#define PXP_ALU_B_CTRL_CLR_RSVD2(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_RSVD2_SHIFT)) & PXP_ALU_B_CTRL_CLR_RSVD2_MASK)

#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_MASK      (0x100000U)
#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_SHIFT     (20U)
/*! DONE_IRQ_EN - DONE_IRQ_EN */
#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_MASK)

#define PXP_ALU_B_CTRL_CLR_RSVD1_MASK            (0xFE00000U)
#define PXP_ALU_B_CTRL_CLR_RSVD1_SHIFT           (21U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_B_CTRL_CLR_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_RSVD1_SHIFT)) & PXP_ALU_B_CTRL_CLR_RSVD1_MASK)

#define PXP_ALU_B_CTRL_CLR_DONE_MASK             (0x10000000U)
#define PXP_ALU_B_CTRL_CLR_DONE_SHIFT            (28U)
/*! DONE - DONE */
#define PXP_ALU_B_CTRL_CLR_DONE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_MASK)

#define PXP_ALU_B_CTRL_CLR_RSVD0_MASK            (0xE0000000U)
#define PXP_ALU_B_CTRL_CLR_RSVD0_SHIFT           (29U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_B_CTRL_CLR_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_RSVD0_SHIFT)) & PXP_ALU_B_CTRL_CLR_RSVD0_MASK)
/*! @} */

/*! @name ALU_B_CTRL_TOG -  */
/*! @{ */

#define PXP_ALU_B_CTRL_TOG_ENABLE_MASK           (0x1U)
#define PXP_ALU_B_CTRL_TOG_ENABLE_SHIFT          (0U)
/*! ENABLE - ENABLE */
#define PXP_ALU_B_CTRL_TOG_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_TOG_ENABLE_MASK)

#define PXP_ALU_B_CTRL_TOG_RSVD6_MASK            (0xEU)
#define PXP_ALU_B_CTRL_TOG_RSVD6_SHIFT           (1U)
/*! RSVD6 - RSVD6 */
#define PXP_ALU_B_CTRL_TOG_RSVD6(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_RSVD6_SHIFT)) & PXP_ALU_B_CTRL_TOG_RSVD6_MASK)

#define PXP_ALU_B_CTRL_TOG_START_MASK            (0x10U)
#define PXP_ALU_B_CTRL_TOG_START_SHIFT           (4U)
/*! START - START */
#define PXP_ALU_B_CTRL_TOG_START(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_START_SHIFT)) & PXP_ALU_B_CTRL_TOG_START_MASK)

#define PXP_ALU_B_CTRL_TOG_RSVD5_MASK            (0xE0U)
#define PXP_ALU_B_CTRL_TOG_RSVD5_SHIFT           (5U)
/*! RSVD5 - RSVD5 */
#define PXP_ALU_B_CTRL_TOG_RSVD5(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_RSVD5_SHIFT)) & PXP_ALU_B_CTRL_TOG_RSVD5_MASK)

#define PXP_ALU_B_CTRL_TOG_SW_RESET_MASK         (0x100U)
#define PXP_ALU_B_CTRL_TOG_SW_RESET_SHIFT        (8U)
/*! SW_RESET - SW_RESET */
#define PXP_ALU_B_CTRL_TOG_SW_RESET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_TOG_SW_RESET_MASK)

#define PXP_ALU_B_CTRL_TOG_RSVD4_MASK            (0xE00U)
#define PXP_ALU_B_CTRL_TOG_RSVD4_SHIFT           (9U)
/*! RSVD4 - RSVD4 */
#define PXP_ALU_B_CTRL_TOG_RSVD4(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_RSVD4_SHIFT)) & PXP_ALU_B_CTRL_TOG_RSVD4_MASK)

#define PXP_ALU_B_CTRL_TOG_BYPASS_MASK           (0x1000U)
#define PXP_ALU_B_CTRL_TOG_BYPASS_SHIFT          (12U)
/*! BYPASS - BYPASS */
#define PXP_ALU_B_CTRL_TOG_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_TOG_BYPASS_MASK)

#define PXP_ALU_B_CTRL_TOG_RSVD3_MASK            (0xE000U)
#define PXP_ALU_B_CTRL_TOG_RSVD3_SHIFT           (13U)
/*! RSVD3 - RSVD3 */
#define PXP_ALU_B_CTRL_TOG_RSVD3(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_RSVD3_SHIFT)) & PXP_ALU_B_CTRL_TOG_RSVD3_MASK)

#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_MASK    (0x10000U)
#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_SHIFT   (16U)
/*! DONE_IRQ_FLAG - DONE_IRQ_FLAG */
#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG(x)      (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_MASK)

#define PXP_ALU_B_CTRL_TOG_RSVD2_MASK            (0xE0000U)
#define PXP_ALU_B_CTRL_TOG_RSVD2_SHIFT           (17U)
/*! RSVD2 - RSVD2 */
#define PXP_ALU_B_CTRL_TOG_RSVD2(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_RSVD2_SHIFT)) & PXP_ALU_B_CTRL_TOG_RSVD2_MASK)

#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_MASK      (0x100000U)
#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_SHIFT     (20U)
/*! DONE_IRQ_EN - DONE_IRQ_EN */
#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_MASK)

#define PXP_ALU_B_CTRL_TOG_RSVD1_MASK            (0xFE00000U)
#define PXP_ALU_B_CTRL_TOG_RSVD1_SHIFT           (21U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_B_CTRL_TOG_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_RSVD1_SHIFT)) & PXP_ALU_B_CTRL_TOG_RSVD1_MASK)

#define PXP_ALU_B_CTRL_TOG_DONE_MASK             (0x10000000U)
#define PXP_ALU_B_CTRL_TOG_DONE_SHIFT            (28U)
/*! DONE - DONE */
#define PXP_ALU_B_CTRL_TOG_DONE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_MASK)

#define PXP_ALU_B_CTRL_TOG_RSVD0_MASK            (0xE0000000U)
#define PXP_ALU_B_CTRL_TOG_RSVD0_SHIFT           (29U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_B_CTRL_TOG_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_RSVD0_SHIFT)) & PXP_ALU_B_CTRL_TOG_RSVD0_MASK)
/*! @} */

/*! @name ALU_B_BUF_SIZE -  */
/*! @{ */

#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH_MASK        (0x1FFFU)
#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH_SHIFT       (0U)
/*! BUF_WIDTH - BUF_WIDTH */
#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH(x)          (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_BUF_SIZE_BUF_WIDTH_SHIFT)) & PXP_ALU_B_BUF_SIZE_BUF_WIDTH_MASK)

#define PXP_ALU_B_BUF_SIZE_RSVD1_MASK            (0xE000U)
#define PXP_ALU_B_BUF_SIZE_RSVD1_SHIFT           (13U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_B_BUF_SIZE_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_BUF_SIZE_RSVD1_SHIFT)) & PXP_ALU_B_BUF_SIZE_RSVD1_MASK)

#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_MASK       (0x1FFF0000U)
#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_SHIFT      (16U)
/*! BUF_HEIGHT - BUF_HEIGHT */
#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_SHIFT)) & PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_MASK)

#define PXP_ALU_B_BUF_SIZE_RSVD0_MASK            (0xE0000000U)
#define PXP_ALU_B_BUF_SIZE_RSVD0_SHIFT           (29U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_B_BUF_SIZE_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_BUF_SIZE_RSVD0_SHIFT)) & PXP_ALU_B_BUF_SIZE_RSVD0_MASK)
/*! @} */

/*! @name ALU_B_INST_ENTRY -  */
/*! @{ */

#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_MASK     (0xFFFFU)
#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_SHIFT    (0U)
/*! ENTRY_ADDR - ENTRY_ADDR */
#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(x)       (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_SHIFT)) & PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_MASK)

#define PXP_ALU_B_INST_ENTRY_RSVD0_MASK          (0xFFFF0000U)
#define PXP_ALU_B_INST_ENTRY_RSVD0_SHIFT         (16U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_B_INST_ENTRY_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_INST_ENTRY_RSVD0_SHIFT)) & PXP_ALU_B_INST_ENTRY_RSVD0_MASK)
/*! @} */

/*! @name ALU_B_PARAM -  */
/*! @{ */

#define PXP_ALU_B_PARAM_PARAM0_MASK              (0xFFU)
#define PXP_ALU_B_PARAM_PARAM0_SHIFT             (0U)
/*! PARAM0 - PARAM0 */
#define PXP_ALU_B_PARAM_PARAM0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_PARAM_PARAM0_SHIFT)) & PXP_ALU_B_PARAM_PARAM0_MASK)

#define PXP_ALU_B_PARAM_PARAM1_MASK              (0xFF00U)
#define PXP_ALU_B_PARAM_PARAM1_SHIFT             (8U)
/*! PARAM1 - PARAM1 */
#define PXP_ALU_B_PARAM_PARAM1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_PARAM_PARAM1_SHIFT)) & PXP_ALU_B_PARAM_PARAM1_MASK)

#define PXP_ALU_B_PARAM_RSVD0_MASK               (0xFFFF0000U)
#define PXP_ALU_B_PARAM_RSVD0_SHIFT              (16U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_B_PARAM_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_PARAM_RSVD0_SHIFT)) & PXP_ALU_B_PARAM_RSVD0_MASK)
/*! @} */

/*! @name ALU_B_CONFIG -  */
/*! @{ */

#define PXP_ALU_B_CONFIG_BUF_ADDR_MASK           (0xFFFFFFFFU)
#define PXP_ALU_B_CONFIG_BUF_ADDR_SHIFT          (0U)
/*! BUF_ADDR - BUF_ADDR */
#define PXP_ALU_B_CONFIG_BUF_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CONFIG_BUF_ADDR_SHIFT)) & PXP_ALU_B_CONFIG_BUF_ADDR_MASK)
/*! @} */

/*! @name ALU_B_LUT_CONFIG -  */
/*! @{ */

#define PXP_ALU_B_LUT_CONFIG_EN_MASK             (0x1U)
#define PXP_ALU_B_LUT_CONFIG_EN_SHIFT            (0U)
/*! EN - EN */
#define PXP_ALU_B_LUT_CONFIG_EN(x)               (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_EN_MASK)

#define PXP_ALU_B_LUT_CONFIG_RSVD1_MASK          (0xEU)
#define PXP_ALU_B_LUT_CONFIG_RSVD1_SHIFT         (1U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_B_LUT_CONFIG_RSVD1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_RSVD1_SHIFT)) & PXP_ALU_B_LUT_CONFIG_RSVD1_MASK)

#define PXP_ALU_B_LUT_CONFIG_MODE_MASK           (0x30U)
#define PXP_ALU_B_LUT_CONFIG_MODE_SHIFT          (4U)
/*! MODE - MODE
 *  0b00..Reserved
 *  0b01..6-bit mode
 *  0b10..5-bit mode
 *  0b11..4-bit mode
 */
#define PXP_ALU_B_LUT_CONFIG_MODE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_MODE_MASK)

#define PXP_ALU_B_LUT_CONFIG_RSVD0_MASK          (0xFFFFFFC0U)
#define PXP_ALU_B_LUT_CONFIG_RSVD0_SHIFT         (6U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_B_LUT_CONFIG_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_RSVD0_SHIFT)) & PXP_ALU_B_LUT_CONFIG_RSVD0_MASK)
/*! @} */

/*! @name ALU_B_LUT_CONFIG_SET -  */
/*! @{ */

#define PXP_ALU_B_LUT_CONFIG_SET_EN_MASK         (0x1U)
#define PXP_ALU_B_LUT_CONFIG_SET_EN_SHIFT        (0U)
/*! EN - EN */
#define PXP_ALU_B_LUT_CONFIG_SET_EN(x)           (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_SET_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_SET_EN_MASK)

#define PXP_ALU_B_LUT_CONFIG_SET_RSVD1_MASK      (0xEU)
#define PXP_ALU_B_LUT_CONFIG_SET_RSVD1_SHIFT     (1U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_B_LUT_CONFIG_SET_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_SET_RSVD1_SHIFT)) & PXP_ALU_B_LUT_CONFIG_SET_RSVD1_MASK)

#define PXP_ALU_B_LUT_CONFIG_SET_MODE_MASK       (0x30U)
#define PXP_ALU_B_LUT_CONFIG_SET_MODE_SHIFT      (4U)
/*! MODE - MODE */
#define PXP_ALU_B_LUT_CONFIG_SET_MODE(x)         (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_SET_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_SET_MODE_MASK)

#define PXP_ALU_B_LUT_CONFIG_SET_RSVD0_MASK      (0xFFFFFFC0U)
#define PXP_ALU_B_LUT_CONFIG_SET_RSVD0_SHIFT     (6U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_B_LUT_CONFIG_SET_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_SET_RSVD0_SHIFT)) & PXP_ALU_B_LUT_CONFIG_SET_RSVD0_MASK)
/*! @} */

/*! @name ALU_B_LUT_CONFIG_CLR -  */
/*! @{ */

#define PXP_ALU_B_LUT_CONFIG_CLR_EN_MASK         (0x1U)
#define PXP_ALU_B_LUT_CONFIG_CLR_EN_SHIFT        (0U)
/*! EN - EN */
#define PXP_ALU_B_LUT_CONFIG_CLR_EN(x)           (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_CLR_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_CLR_EN_MASK)

#define PXP_ALU_B_LUT_CONFIG_CLR_RSVD1_MASK      (0xEU)
#define PXP_ALU_B_LUT_CONFIG_CLR_RSVD1_SHIFT     (1U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_B_LUT_CONFIG_CLR_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_CLR_RSVD1_SHIFT)) & PXP_ALU_B_LUT_CONFIG_CLR_RSVD1_MASK)

#define PXP_ALU_B_LUT_CONFIG_CLR_MODE_MASK       (0x30U)
#define PXP_ALU_B_LUT_CONFIG_CLR_MODE_SHIFT      (4U)
/*! MODE - MODE */
#define PXP_ALU_B_LUT_CONFIG_CLR_MODE(x)         (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_CLR_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_CLR_MODE_MASK)

#define PXP_ALU_B_LUT_CONFIG_CLR_RSVD0_MASK      (0xFFFFFFC0U)
#define PXP_ALU_B_LUT_CONFIG_CLR_RSVD0_SHIFT     (6U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_B_LUT_CONFIG_CLR_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_CLR_RSVD0_SHIFT)) & PXP_ALU_B_LUT_CONFIG_CLR_RSVD0_MASK)
/*! @} */

/*! @name ALU_B_LUT_CONFIG_TOG -  */
/*! @{ */

#define PXP_ALU_B_LUT_CONFIG_TOG_EN_MASK         (0x1U)
#define PXP_ALU_B_LUT_CONFIG_TOG_EN_SHIFT        (0U)
/*! EN - EN */
#define PXP_ALU_B_LUT_CONFIG_TOG_EN(x)           (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_TOG_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_TOG_EN_MASK)

#define PXP_ALU_B_LUT_CONFIG_TOG_RSVD1_MASK      (0xEU)
#define PXP_ALU_B_LUT_CONFIG_TOG_RSVD1_SHIFT     (1U)
/*! RSVD1 - RSVD1 */
#define PXP_ALU_B_LUT_CONFIG_TOG_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_TOG_RSVD1_SHIFT)) & PXP_ALU_B_LUT_CONFIG_TOG_RSVD1_MASK)

#define PXP_ALU_B_LUT_CONFIG_TOG_MODE_MASK       (0x30U)
#define PXP_ALU_B_LUT_CONFIG_TOG_MODE_SHIFT      (4U)
/*! MODE - MODE */
#define PXP_ALU_B_LUT_CONFIG_TOG_MODE(x)         (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_TOG_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_TOG_MODE_MASK)

#define PXP_ALU_B_LUT_CONFIG_TOG_RSVD0_MASK      (0xFFFFFFC0U)
#define PXP_ALU_B_LUT_CONFIG_TOG_RSVD0_SHIFT     (6U)
/*! RSVD0 - RSVD0 */
#define PXP_ALU_B_LUT_CONFIG_TOG_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_TOG_RSVD0_SHIFT)) & PXP_ALU_B_LUT_CONFIG_TOG_RSVD0_MASK)
/*! @} */

/*! @name ALU_B_LUT_DATA0 -  */
/*! @{ */

#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L_MASK      (0xFFFFFFFFU)
#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L_SHIFT     (0U)
/*! LUT_DATA_L - LUT_DATA_L */
#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_DATA0_LUT_DATA_L_SHIFT)) & PXP_ALU_B_LUT_DATA0_LUT_DATA_L_MASK)
/*! @} */

/*! @name ALU_B_LUT_DATA1 -  */
/*! @{ */

#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H_MASK      (0xFFFFFFFFU)
#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H_SHIFT     (0U)
/*! LUT_DATA_H - LUT_DATA_H */
#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H(x)        (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_DATA1_LUT_DATA_H_SHIFT)) & PXP_ALU_B_LUT_DATA1_LUT_DATA_H_MASK)
/*! @} */

/*! @name ALU_B_DBG -  */
/*! @{ */

#define PXP_ALU_B_DBG_DEBUG_VALUE_MASK           (0xFFFFFFU)
#define PXP_ALU_B_DBG_DEBUG_VALUE_SHIFT          (0U)
/*! DEBUG_VALUE - DEBUG_VALUE */
#define PXP_ALU_B_DBG_DEBUG_VALUE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_DBG_DEBUG_VALUE_SHIFT)) & PXP_ALU_B_DBG_DEBUG_VALUE_MASK)

#define PXP_ALU_B_DBG_DEBUG_SEL_MASK             (0xFF000000U)
#define PXP_ALU_B_DBG_DEBUG_SEL_SHIFT            (24U)
/*! DEBUG_SEL - DEBUG_SEL */
#define PXP_ALU_B_DBG_DEBUG_SEL(x)               (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_DBG_DEBUG_SEL_SHIFT)) & PXP_ALU_B_DBG_DEBUG_SEL_MASK)
/*! @} */

/*! @name HIST_A_CTRL - Histogram Control Register. */
/*! @{ */

#define PXP_HIST_A_CTRL_ENABLE_MASK              (0x1U)
#define PXP_HIST_A_CTRL_ENABLE_SHIFT             (0U)
/*! ENABLE - ENABLE */
#define PXP_HIST_A_CTRL_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_ENABLE_SHIFT)) & PXP_HIST_A_CTRL_ENABLE_MASK)

#define PXP_HIST_A_CTRL_RSVD0_MASK               (0xEU)
#define PXP_HIST_A_CTRL_RSVD0_SHIFT              (1U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST_A_CTRL_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_RSVD0_SHIFT)) & PXP_HIST_A_CTRL_RSVD0_MASK)

#define PXP_HIST_A_CTRL_CLEAR_MASK               (0x10U)
#define PXP_HIST_A_CTRL_CLEAR_SHIFT              (4U)
/*! CLEAR - CLEAR */
#define PXP_HIST_A_CTRL_CLEAR(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_CLEAR_SHIFT)) & PXP_HIST_A_CTRL_CLEAR_MASK)

#define PXP_HIST_A_CTRL_RSVD1_MASK               (0xE0U)
#define PXP_HIST_A_CTRL_RSVD1_SHIFT              (5U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST_A_CTRL_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_RSVD1_SHIFT)) & PXP_HIST_A_CTRL_RSVD1_MASK)

#define PXP_HIST_A_CTRL_STATUS_MASK              (0x1F00U)
#define PXP_HIST_A_CTRL_STATUS_SHIFT             (8U)
/*! STATUS - STATUS */
#define PXP_HIST_A_CTRL_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_STATUS_SHIFT)) & PXP_HIST_A_CTRL_STATUS_MASK)

#define PXP_HIST_A_CTRL_RSVD2_MASK               (0xE000U)
#define PXP_HIST_A_CTRL_RSVD2_SHIFT              (13U)
/*! RSVD2 - RSVD2 */
#define PXP_HIST_A_CTRL_RSVD2(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_RSVD2_SHIFT)) & PXP_HIST_A_CTRL_RSVD2_MASK)

#define PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK        (0x7F0000U)
#define PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT       (16U)
/*! PIXEL_OFFSET - PIXEL_OFFSET */
#define PXP_HIST_A_CTRL_PIXEL_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT)) & PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK)

#define PXP_HIST_A_CTRL_RSVD3_MASK               (0x800000U)
#define PXP_HIST_A_CTRL_RSVD3_SHIFT              (23U)
/*! RSVD3 - RSVD3 */
#define PXP_HIST_A_CTRL_RSVD3(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_RSVD3_SHIFT)) & PXP_HIST_A_CTRL_RSVD3_MASK)

#define PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK         (0x7000000U)
#define PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT        (24U)
/*! PIXEL_WIDTH - PIXEL_WIDTH */
#define PXP_HIST_A_CTRL_PIXEL_WIDTH(x)           (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT)) & PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK)

#define PXP_HIST_A_CTRL_RSVD4_MASK               (0xF8000000U)
#define PXP_HIST_A_CTRL_RSVD4_SHIFT              (27U)
/*! RSVD4 - RSVD4 */
#define PXP_HIST_A_CTRL_RSVD4(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_RSVD4_SHIFT)) & PXP_HIST_A_CTRL_RSVD4_MASK)
/*! @} */

/*! @name HIST_A_MASK - Histogram Pixel Mask Register. */
/*! @{ */

#define PXP_HIST_A_MASK_MASK_EN_MASK             (0x1U)
#define PXP_HIST_A_MASK_MASK_EN_SHIFT            (0U)
/*! MASK_EN - MASK_EN */
#define PXP_HIST_A_MASK_MASK_EN(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_EN_SHIFT)) & PXP_HIST_A_MASK_MASK_EN_MASK)

#define PXP_HIST_A_MASK_RSVD0_MASK               (0xEU)
#define PXP_HIST_A_MASK_RSVD0_SHIFT              (1U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST_A_MASK_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_RSVD0_SHIFT)) & PXP_HIST_A_MASK_RSVD0_MASK)

#define PXP_HIST_A_MASK_MASK_MODE_MASK           (0x30U)
#define PXP_HIST_A_MASK_MASK_MODE_SHIFT          (4U)
/*! MASK_MODE - MASK_MODE
 *  0b00..EQUAL : Run histogram for pixels equal to value0
 *  0b01..NOT_EQUAL : Run histogram for pixels not equal to value0
 *  0b10..INSIDE : Run histogram for pixels within the range of value0 to value1
 *  0b11..OUTSIDE : Run histogram for pixels outside of the rang of value0 to value1
 */
#define PXP_HIST_A_MASK_MASK_MODE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_MODE_SHIFT)) & PXP_HIST_A_MASK_MASK_MODE_MASK)

#define PXP_HIST_A_MASK_MASK_OFFSET_MASK         (0x1FC0U)
#define PXP_HIST_A_MASK_MASK_OFFSET_SHIFT        (6U)
/*! MASK_OFFSET - MASK_OFFSET */
#define PXP_HIST_A_MASK_MASK_OFFSET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_OFFSET_SHIFT)) & PXP_HIST_A_MASK_MASK_OFFSET_MASK)

#define PXP_HIST_A_MASK_MASK_WIDTH_MASK          (0xE000U)
#define PXP_HIST_A_MASK_MASK_WIDTH_SHIFT         (13U)
/*! MASK_WIDTH - MASK_WIDTH */
#define PXP_HIST_A_MASK_MASK_WIDTH(x)            (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_WIDTH_SHIFT)) & PXP_HIST_A_MASK_MASK_WIDTH_MASK)

#define PXP_HIST_A_MASK_MASK_VALUE0_MASK         (0xFF0000U)
#define PXP_HIST_A_MASK_MASK_VALUE0_SHIFT        (16U)
/*! MASK_VALUE0 - MASK_VALUE0 */
#define PXP_HIST_A_MASK_MASK_VALUE0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_VALUE0_SHIFT)) & PXP_HIST_A_MASK_MASK_VALUE0_MASK)

#define PXP_HIST_A_MASK_MASK_VALUE1_MASK         (0xFF000000U)
#define PXP_HIST_A_MASK_MASK_VALUE1_SHIFT        (24U)
/*! MASK_VALUE1 - MASK_VALUE1 */
#define PXP_HIST_A_MASK_MASK_VALUE1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_VALUE1_SHIFT)) & PXP_HIST_A_MASK_MASK_VALUE1_MASK)
/*! @} */

/*! @name HIST_A_BUF_SIZE - Histogram Pixel Buffer Size Register. */
/*! @{ */

#define PXP_HIST_A_BUF_SIZE_WIDTH_MASK           (0x1FFFU)
#define PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT          (0U)
/*! WIDTH - WIDTH */
#define PXP_HIST_A_BUF_SIZE_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT)) & PXP_HIST_A_BUF_SIZE_WIDTH_MASK)

#define PXP_HIST_A_BUF_SIZE_RSVD1_MASK           (0xE000U)
#define PXP_HIST_A_BUF_SIZE_RSVD1_SHIFT          (13U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST_A_BUF_SIZE_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_BUF_SIZE_RSVD1_SHIFT)) & PXP_HIST_A_BUF_SIZE_RSVD1_MASK)

#define PXP_HIST_A_BUF_SIZE_HEIGHT_MASK          (0x1FFF0000U)
#define PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT         (16U)
/*! HEIGHT - HEIGHT */
#define PXP_HIST_A_BUF_SIZE_HEIGHT(x)            (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT)) & PXP_HIST_A_BUF_SIZE_HEIGHT_MASK)

#define PXP_HIST_A_BUF_SIZE_RSVD0_MASK           (0xE0000000U)
#define PXP_HIST_A_BUF_SIZE_RSVD0_SHIFT          (29U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST_A_BUF_SIZE_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_BUF_SIZE_RSVD0_SHIFT)) & PXP_HIST_A_BUF_SIZE_RSVD0_MASK)
/*! @} */

/*! @name HIST_A_TOTAL_PIXEL - Total Number of Pixels Used by Histogram Engine. */
/*! @{ */

#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK  (0x3FFFFFFU)
#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT (0U)
/*! TOTAL_PIXEL - TOTAL_PIXEL */
#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL(x)    (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT)) & PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK)

#define PXP_HIST_A_TOTAL_PIXEL_RSVD0_MASK        (0xFC000000U)
#define PXP_HIST_A_TOTAL_PIXEL_RSVD0_SHIFT       (26U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST_A_TOTAL_PIXEL_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_TOTAL_PIXEL_RSVD0_SHIFT)) & PXP_HIST_A_TOTAL_PIXEL_RSVD0_MASK)
/*! @} */

/*! @name HIST_A_ACTIVE_AREA_X - The X Coordinate Offset for Active Area. */
/*! @{ */

#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK (0x1FFFU)
#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT (0U)
/*! MIN_X_OFFSET - MIN_X_OFFSET */
#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK)

#define PXP_HIST_A_ACTIVE_AREA_X_RSVD0_MASK      (0xE000U)
#define PXP_HIST_A_ACTIVE_AREA_X_RSVD0_SHIFT     (13U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST_A_ACTIVE_AREA_X_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_X_RSVD0_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_X_RSVD0_MASK)

#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK (0x1FFF0000U)
#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT (16U)
/*! MAX_X_OFFSET - MAX_X_OFFSET */
#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK)

#define PXP_HIST_A_ACTIVE_AREA_X_RSVD1_MASK      (0xE0000000U)
#define PXP_HIST_A_ACTIVE_AREA_X_RSVD1_SHIFT     (29U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST_A_ACTIVE_AREA_X_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_X_RSVD1_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_X_RSVD1_MASK)
/*! @} */

/*! @name HIST_A_ACTIVE_AREA_Y - The Y Coordinate Offset for Active Area. */
/*! @{ */

#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK (0x1FFFU)
#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT (0U)
/*! MIN_Y_OFFSET - MIN_Y_OFFSET */
#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK)

#define PXP_HIST_A_ACTIVE_AREA_Y_RSVD0_MASK      (0xE000U)
#define PXP_HIST_A_ACTIVE_AREA_Y_RSVD0_SHIFT     (13U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST_A_ACTIVE_AREA_Y_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_Y_RSVD0_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_Y_RSVD0_MASK)

#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK (0x1FFF0000U)
#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT (16U)
/*! MAX_Y_OFFSET - MAX_Y_OFFSET */
#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK)

#define PXP_HIST_A_ACTIVE_AREA_Y_RSVD1_MASK      (0xE0000000U)
#define PXP_HIST_A_ACTIVE_AREA_Y_RSVD1_SHIFT     (29U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST_A_ACTIVE_AREA_Y_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_Y_RSVD1_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_Y_RSVD1_MASK)
/*! @} */

/*! @name HIST_A_RAW_STAT0 - Histogram Result Based on RAW Pixel Value. */
/*! @{ */

#define PXP_HIST_A_RAW_STAT0_STAT0_MASK          (0xFFFFFFFFU)
#define PXP_HIST_A_RAW_STAT0_STAT0_SHIFT         (0U)
/*! STAT0 - STAT0 */
#define PXP_HIST_A_RAW_STAT0_STAT0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_RAW_STAT0_STAT0_SHIFT)) & PXP_HIST_A_RAW_STAT0_STAT0_MASK)
/*! @} */

/*! @name HIST_A_RAW_STAT1 - Histogram Result Based on RAW Pixel Value. */
/*! @{ */

#define PXP_HIST_A_RAW_STAT1_STAT1_MASK          (0xFFFFFFFFU)
#define PXP_HIST_A_RAW_STAT1_STAT1_SHIFT         (0U)
/*! STAT1 - STAT1 */
#define PXP_HIST_A_RAW_STAT1_STAT1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_RAW_STAT1_STAT1_SHIFT)) & PXP_HIST_A_RAW_STAT1_STAT1_MASK)
/*! @} */

/*! @name HIST_B_CTRL - Histogram Control Register. */
/*! @{ */

#define PXP_HIST_B_CTRL_ENABLE_MASK              (0x1U)
#define PXP_HIST_B_CTRL_ENABLE_SHIFT             (0U)
/*! ENABLE - ENABLE */
#define PXP_HIST_B_CTRL_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_ENABLE_SHIFT)) & PXP_HIST_B_CTRL_ENABLE_MASK)

#define PXP_HIST_B_CTRL_RSVD0_MASK               (0xEU)
#define PXP_HIST_B_CTRL_RSVD0_SHIFT              (1U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST_B_CTRL_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_RSVD0_SHIFT)) & PXP_HIST_B_CTRL_RSVD0_MASK)

#define PXP_HIST_B_CTRL_CLEAR_MASK               (0x10U)
#define PXP_HIST_B_CTRL_CLEAR_SHIFT              (4U)
/*! CLEAR - CLEAR */
#define PXP_HIST_B_CTRL_CLEAR(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_CLEAR_SHIFT)) & PXP_HIST_B_CTRL_CLEAR_MASK)

#define PXP_HIST_B_CTRL_RSVD1_MASK               (0xE0U)
#define PXP_HIST_B_CTRL_RSVD1_SHIFT              (5U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST_B_CTRL_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_RSVD1_SHIFT)) & PXP_HIST_B_CTRL_RSVD1_MASK)

#define PXP_HIST_B_CTRL_STATUS_MASK              (0x1F00U)
#define PXP_HIST_B_CTRL_STATUS_SHIFT             (8U)
/*! STATUS - STATUS */
#define PXP_HIST_B_CTRL_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_STATUS_SHIFT)) & PXP_HIST_B_CTRL_STATUS_MASK)

#define PXP_HIST_B_CTRL_RSVD2_MASK               (0xE000U)
#define PXP_HIST_B_CTRL_RSVD2_SHIFT              (13U)
/*! RSVD2 - RSVD2 */
#define PXP_HIST_B_CTRL_RSVD2(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_RSVD2_SHIFT)) & PXP_HIST_B_CTRL_RSVD2_MASK)

#define PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK        (0x7F0000U)
#define PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT       (16U)
/*! PIXEL_OFFSET - PIXEL_OFFSET */
#define PXP_HIST_B_CTRL_PIXEL_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT)) & PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK)

#define PXP_HIST_B_CTRL_RSVD3_MASK               (0x800000U)
#define PXP_HIST_B_CTRL_RSVD3_SHIFT              (23U)
/*! RSVD3 - RSVD3 */
#define PXP_HIST_B_CTRL_RSVD3(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_RSVD3_SHIFT)) & PXP_HIST_B_CTRL_RSVD3_MASK)

#define PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK         (0x7000000U)
#define PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT        (24U)
/*! PIXEL_WIDTH - PIXEL_WIDTH */
#define PXP_HIST_B_CTRL_PIXEL_WIDTH(x)           (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT)) & PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK)

#define PXP_HIST_B_CTRL_RSVD4_MASK               (0xF8000000U)
#define PXP_HIST_B_CTRL_RSVD4_SHIFT              (27U)
/*! RSVD4 - RSVD4 */
#define PXP_HIST_B_CTRL_RSVD4(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_RSVD4_SHIFT)) & PXP_HIST_B_CTRL_RSVD4_MASK)
/*! @} */

/*! @name HIST_B_MASK - Histogram Pixel Mask Register. */
/*! @{ */

#define PXP_HIST_B_MASK_MASK_EN_MASK             (0x1U)
#define PXP_HIST_B_MASK_MASK_EN_SHIFT            (0U)
/*! MASK_EN - MASK_EN */
#define PXP_HIST_B_MASK_MASK_EN(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_EN_SHIFT)) & PXP_HIST_B_MASK_MASK_EN_MASK)

#define PXP_HIST_B_MASK_RSVD0_MASK               (0xEU)
#define PXP_HIST_B_MASK_RSVD0_SHIFT              (1U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST_B_MASK_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_RSVD0_SHIFT)) & PXP_HIST_B_MASK_RSVD0_MASK)

#define PXP_HIST_B_MASK_MASK_MODE_MASK           (0x30U)
#define PXP_HIST_B_MASK_MASK_MODE_SHIFT          (4U)
/*! MASK_MODE - MASK_MODE
 *  0b00..EQUAL : Run histogram for pixels equal to value0
 *  0b01..NOT_EQUAL : Run histogram for pixels not equal to value0
 *  0b10..INSIDE : Run histogram for pixels within the range of value0 to value1
 *  0b11..OUTSIDE : Run histogram for pixels outside of the rang of value0 to value1
 */
#define PXP_HIST_B_MASK_MASK_MODE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_MODE_SHIFT)) & PXP_HIST_B_MASK_MASK_MODE_MASK)

#define PXP_HIST_B_MASK_MASK_OFFSET_MASK         (0x1FC0U)
#define PXP_HIST_B_MASK_MASK_OFFSET_SHIFT        (6U)
/*! MASK_OFFSET - MASK_OFFSET */
#define PXP_HIST_B_MASK_MASK_OFFSET(x)           (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_OFFSET_SHIFT)) & PXP_HIST_B_MASK_MASK_OFFSET_MASK)

#define PXP_HIST_B_MASK_MASK_WIDTH_MASK          (0xE000U)
#define PXP_HIST_B_MASK_MASK_WIDTH_SHIFT         (13U)
/*! MASK_WIDTH - MASK_WIDTH */
#define PXP_HIST_B_MASK_MASK_WIDTH(x)            (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_WIDTH_SHIFT)) & PXP_HIST_B_MASK_MASK_WIDTH_MASK)

#define PXP_HIST_B_MASK_MASK_VALUE0_MASK         (0xFF0000U)
#define PXP_HIST_B_MASK_MASK_VALUE0_SHIFT        (16U)
/*! MASK_VALUE0 - MASK_VALUE0 */
#define PXP_HIST_B_MASK_MASK_VALUE0(x)           (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_VALUE0_SHIFT)) & PXP_HIST_B_MASK_MASK_VALUE0_MASK)

#define PXP_HIST_B_MASK_MASK_VALUE1_MASK         (0xFF000000U)
#define PXP_HIST_B_MASK_MASK_VALUE1_SHIFT        (24U)
/*! MASK_VALUE1 - MASK_VALUE1 */
#define PXP_HIST_B_MASK_MASK_VALUE1(x)           (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_VALUE1_SHIFT)) & PXP_HIST_B_MASK_MASK_VALUE1_MASK)
/*! @} */

/*! @name HIST_B_BUF_SIZE - Histogram Pixel Buffer Size Register. */
/*! @{ */

#define PXP_HIST_B_BUF_SIZE_WIDTH_MASK           (0x1FFFU)
#define PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT          (0U)
/*! WIDTH - WIDTH */
#define PXP_HIST_B_BUF_SIZE_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT)) & PXP_HIST_B_BUF_SIZE_WIDTH_MASK)

#define PXP_HIST_B_BUF_SIZE_RSVD1_MASK           (0xE000U)
#define PXP_HIST_B_BUF_SIZE_RSVD1_SHIFT          (13U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST_B_BUF_SIZE_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_BUF_SIZE_RSVD1_SHIFT)) & PXP_HIST_B_BUF_SIZE_RSVD1_MASK)

#define PXP_HIST_B_BUF_SIZE_HEIGHT_MASK          (0x1FFF0000U)
#define PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT         (16U)
/*! HEIGHT - HEIGHT */
#define PXP_HIST_B_BUF_SIZE_HEIGHT(x)            (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT)) & PXP_HIST_B_BUF_SIZE_HEIGHT_MASK)

#define PXP_HIST_B_BUF_SIZE_RSVD0_MASK           (0xE0000000U)
#define PXP_HIST_B_BUF_SIZE_RSVD0_SHIFT          (29U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST_B_BUF_SIZE_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_BUF_SIZE_RSVD0_SHIFT)) & PXP_HIST_B_BUF_SIZE_RSVD0_MASK)
/*! @} */

/*! @name HIST_B_TOTAL_PIXEL - Total Number of Pixels Used by Histogram Engine. */
/*! @{ */

#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK  (0x3FFFFFFU)
#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT (0U)
/*! TOTAL_PIXEL - TOTAL_PIXEL */
#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL(x)    (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT)) & PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK)

#define PXP_HIST_B_TOTAL_PIXEL_RSVD0_MASK        (0xFC000000U)
#define PXP_HIST_B_TOTAL_PIXEL_RSVD0_SHIFT       (26U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST_B_TOTAL_PIXEL_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_TOTAL_PIXEL_RSVD0_SHIFT)) & PXP_HIST_B_TOTAL_PIXEL_RSVD0_MASK)
/*! @} */

/*! @name HIST_B_ACTIVE_AREA_X - The X Coordinate Offset for Active Area. */
/*! @{ */

#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK (0x1FFFU)
#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT (0U)
/*! MIN_X_OFFSET - MIN_X_OFFSET */
#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK)

#define PXP_HIST_B_ACTIVE_AREA_X_RSVD0_MASK      (0xE000U)
#define PXP_HIST_B_ACTIVE_AREA_X_RSVD0_SHIFT     (13U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST_B_ACTIVE_AREA_X_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_X_RSVD0_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_X_RSVD0_MASK)

#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK (0x1FFF0000U)
#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT (16U)
/*! MAX_X_OFFSET - MAX_X_OFFSET */
#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK)

#define PXP_HIST_B_ACTIVE_AREA_X_RSVD1_MASK      (0xE0000000U)
#define PXP_HIST_B_ACTIVE_AREA_X_RSVD1_SHIFT     (29U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST_B_ACTIVE_AREA_X_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_X_RSVD1_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_X_RSVD1_MASK)
/*! @} */

/*! @name HIST_B_ACTIVE_AREA_Y - The Y Coordinate Offset for Active Area. */
/*! @{ */

#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK (0x1FFFU)
#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT (0U)
/*! MIN_Y_OFFSET - MIN_Y_OFFSET */
#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK)

#define PXP_HIST_B_ACTIVE_AREA_Y_RSVD0_MASK      (0xE000U)
#define PXP_HIST_B_ACTIVE_AREA_Y_RSVD0_SHIFT     (13U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST_B_ACTIVE_AREA_Y_RSVD0(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_Y_RSVD0_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_Y_RSVD0_MASK)

#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK (0x1FFF0000U)
#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT (16U)
/*! MAX_Y_OFFSET - MAX_Y_OFFSET */
#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK)

#define PXP_HIST_B_ACTIVE_AREA_Y_RSVD1_MASK      (0xE0000000U)
#define PXP_HIST_B_ACTIVE_AREA_Y_RSVD1_SHIFT     (29U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST_B_ACTIVE_AREA_Y_RSVD1(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_Y_RSVD1_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_Y_RSVD1_MASK)
/*! @} */

/*! @name HIST_B_RAW_STAT0 - Histogram Result Based on RAW Pixel Value. */
/*! @{ */

#define PXP_HIST_B_RAW_STAT0_STAT0_MASK          (0xFFFFFFFFU)
#define PXP_HIST_B_RAW_STAT0_STAT0_SHIFT         (0U)
/*! STAT0 - STAT0 */
#define PXP_HIST_B_RAW_STAT0_STAT0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_RAW_STAT0_STAT0_SHIFT)) & PXP_HIST_B_RAW_STAT0_STAT0_MASK)
/*! @} */

/*! @name HIST_B_RAW_STAT1 - Histogram Result Based on RAW Pixel Value. */
/*! @{ */

#define PXP_HIST_B_RAW_STAT1_STAT1_MASK          (0xFFFFFFFFU)
#define PXP_HIST_B_RAW_STAT1_STAT1_SHIFT         (0U)
/*! STAT1 - STAT1 */
#define PXP_HIST_B_RAW_STAT1_STAT1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_RAW_STAT1_STAT1_SHIFT)) & PXP_HIST_B_RAW_STAT1_STAT1_MASK)
/*! @} */

/*! @name HIST2_PARAM - 2-level Histogram Parameter Register. */
/*! @{ */

#define PXP_HIST2_PARAM_VALUE0_MASK              (0x3FU)
#define PXP_HIST2_PARAM_VALUE0_SHIFT             (0U)
/*! VALUE0 - VALUE0 */
#define PXP_HIST2_PARAM_VALUE0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST2_PARAM_VALUE0_SHIFT)) & PXP_HIST2_PARAM_VALUE0_MASK)

#define PXP_HIST2_PARAM_RSVD0_MASK               (0xC0U)
#define PXP_HIST2_PARAM_RSVD0_SHIFT              (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST2_PARAM_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST2_PARAM_RSVD0_SHIFT)) & PXP_HIST2_PARAM_RSVD0_MASK)

#define PXP_HIST2_PARAM_VALUE1_MASK              (0x3F00U)
#define PXP_HIST2_PARAM_VALUE1_SHIFT             (8U)
/*! VALUE1 - VALUE1 */
#define PXP_HIST2_PARAM_VALUE1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST2_PARAM_VALUE1_SHIFT)) & PXP_HIST2_PARAM_VALUE1_MASK)

#define PXP_HIST2_PARAM_RSVD1_MASK               (0xC000U)
#define PXP_HIST2_PARAM_RSVD1_SHIFT              (14U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST2_PARAM_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST2_PARAM_RSVD1_SHIFT)) & PXP_HIST2_PARAM_RSVD1_MASK)

#define PXP_HIST2_PARAM_RSVD_MASK                (0xFFFF0000U)
#define PXP_HIST2_PARAM_RSVD_SHIFT               (16U)
/*! RSVD - RSVD */
#define PXP_HIST2_PARAM_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_HIST2_PARAM_RSVD_SHIFT)) & PXP_HIST2_PARAM_RSVD_MASK)
/*! @} */

/*! @name HIST4_PARAM - 4-level Histogram Parameter Register. */
/*! @{ */

#define PXP_HIST4_PARAM_VALUE0_MASK              (0x3FU)
#define PXP_HIST4_PARAM_VALUE0_SHIFT             (0U)
/*! VALUE0 - VALUE0 */
#define PXP_HIST4_PARAM_VALUE0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE0_SHIFT)) & PXP_HIST4_PARAM_VALUE0_MASK)

#define PXP_HIST4_PARAM_RSVD0_MASK               (0xC0U)
#define PXP_HIST4_PARAM_RSVD0_SHIFT              (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST4_PARAM_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_RSVD0_SHIFT)) & PXP_HIST4_PARAM_RSVD0_MASK)

#define PXP_HIST4_PARAM_VALUE1_MASK              (0x3F00U)
#define PXP_HIST4_PARAM_VALUE1_SHIFT             (8U)
/*! VALUE1 - VALUE1 */
#define PXP_HIST4_PARAM_VALUE1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE1_SHIFT)) & PXP_HIST4_PARAM_VALUE1_MASK)

#define PXP_HIST4_PARAM_RSVD1_MASK               (0xC000U)
#define PXP_HIST4_PARAM_RSVD1_SHIFT              (14U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST4_PARAM_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_RSVD1_SHIFT)) & PXP_HIST4_PARAM_RSVD1_MASK)

#define PXP_HIST4_PARAM_VALUE2_MASK              (0x3F0000U)
#define PXP_HIST4_PARAM_VALUE2_SHIFT             (16U)
/*! VALUE2 - VALUE2 */
#define PXP_HIST4_PARAM_VALUE2(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE2_SHIFT)) & PXP_HIST4_PARAM_VALUE2_MASK)

#define PXP_HIST4_PARAM_RSVD2_MASK               (0xC00000U)
#define PXP_HIST4_PARAM_RSVD2_SHIFT              (22U)
/*! RSVD2 - RSVD2 */
#define PXP_HIST4_PARAM_RSVD2(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_RSVD2_SHIFT)) & PXP_HIST4_PARAM_RSVD2_MASK)

#define PXP_HIST4_PARAM_VALUE3_MASK              (0x3F000000U)
#define PXP_HIST4_PARAM_VALUE3_SHIFT             (24U)
/*! VALUE3 - VALUE3 */
#define PXP_HIST4_PARAM_VALUE3(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE3_SHIFT)) & PXP_HIST4_PARAM_VALUE3_MASK)

#define PXP_HIST4_PARAM_RSVD3_MASK               (0xC0000000U)
#define PXP_HIST4_PARAM_RSVD3_SHIFT              (30U)
/*! RSVD3 - RSVD3 */
#define PXP_HIST4_PARAM_RSVD3(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_RSVD3_SHIFT)) & PXP_HIST4_PARAM_RSVD3_MASK)
/*! @} */

/*! @name HIST8_PARAM0 - 8-level Histogram Parameter 0 Register. */
/*! @{ */

#define PXP_HIST8_PARAM0_VALUE0_MASK             (0x3FU)
#define PXP_HIST8_PARAM0_VALUE0_SHIFT            (0U)
/*! VALUE0 - VALUE0 */
#define PXP_HIST8_PARAM0_VALUE0(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE0_SHIFT)) & PXP_HIST8_PARAM0_VALUE0_MASK)

#define PXP_HIST8_PARAM0_RSVD0_MASK              (0xC0U)
#define PXP_HIST8_PARAM0_RSVD0_SHIFT             (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST8_PARAM0_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_RSVD0_SHIFT)) & PXP_HIST8_PARAM0_RSVD0_MASK)

#define PXP_HIST8_PARAM0_VALUE1_MASK             (0x3F00U)
#define PXP_HIST8_PARAM0_VALUE1_SHIFT            (8U)
/*! VALUE1 - VALUE1 */
#define PXP_HIST8_PARAM0_VALUE1(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE1_SHIFT)) & PXP_HIST8_PARAM0_VALUE1_MASK)

#define PXP_HIST8_PARAM0_RSVD1_MASK              (0xC000U)
#define PXP_HIST8_PARAM0_RSVD1_SHIFT             (14U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST8_PARAM0_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_RSVD1_SHIFT)) & PXP_HIST8_PARAM0_RSVD1_MASK)

#define PXP_HIST8_PARAM0_VALUE2_MASK             (0x3F0000U)
#define PXP_HIST8_PARAM0_VALUE2_SHIFT            (16U)
/*! VALUE2 - VALUE2 */
#define PXP_HIST8_PARAM0_VALUE2(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE2_SHIFT)) & PXP_HIST8_PARAM0_VALUE2_MASK)

#define PXP_HIST8_PARAM0_RSVD2_MASK              (0xC00000U)
#define PXP_HIST8_PARAM0_RSVD2_SHIFT             (22U)
/*! RSVD2 - RSVD2 */
#define PXP_HIST8_PARAM0_RSVD2(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_RSVD2_SHIFT)) & PXP_HIST8_PARAM0_RSVD2_MASK)

#define PXP_HIST8_PARAM0_VALUE3_MASK             (0x3F000000U)
#define PXP_HIST8_PARAM0_VALUE3_SHIFT            (24U)
/*! VALUE3 - VALUE3 */
#define PXP_HIST8_PARAM0_VALUE3(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE3_SHIFT)) & PXP_HIST8_PARAM0_VALUE3_MASK)

#define PXP_HIST8_PARAM0_RSVD3_MASK              (0xC0000000U)
#define PXP_HIST8_PARAM0_RSVD3_SHIFT             (30U)
/*! RSVD3 - RSVD3 */
#define PXP_HIST8_PARAM0_RSVD3(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_RSVD3_SHIFT)) & PXP_HIST8_PARAM0_RSVD3_MASK)
/*! @} */

/*! @name HIST8_PARAM1 - 8-level Histogram Parameter 1 Register. */
/*! @{ */

#define PXP_HIST8_PARAM1_VALUE4_MASK             (0x3FU)
#define PXP_HIST8_PARAM1_VALUE4_SHIFT            (0U)
/*! VALUE4 - VALUE4 */
#define PXP_HIST8_PARAM1_VALUE4(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE4_SHIFT)) & PXP_HIST8_PARAM1_VALUE4_MASK)

#define PXP_HIST8_PARAM1_RSVD4_MASK              (0xC0U)
#define PXP_HIST8_PARAM1_RSVD4_SHIFT             (6U)
/*! RSVD4 - RSVD4 */
#define PXP_HIST8_PARAM1_RSVD4(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_RSVD4_SHIFT)) & PXP_HIST8_PARAM1_RSVD4_MASK)

#define PXP_HIST8_PARAM1_VALUE5_MASK             (0x3F00U)
#define PXP_HIST8_PARAM1_VALUE5_SHIFT            (8U)
/*! VALUE5 - VALUE5 */
#define PXP_HIST8_PARAM1_VALUE5(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE5_SHIFT)) & PXP_HIST8_PARAM1_VALUE5_MASK)

#define PXP_HIST8_PARAM1_RSVD5_MASK              (0xC000U)
#define PXP_HIST8_PARAM1_RSVD5_SHIFT             (14U)
/*! RSVD5 - RSVD5 */
#define PXP_HIST8_PARAM1_RSVD5(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_RSVD5_SHIFT)) & PXP_HIST8_PARAM1_RSVD5_MASK)

#define PXP_HIST8_PARAM1_VALUE6_MASK             (0x3F0000U)
#define PXP_HIST8_PARAM1_VALUE6_SHIFT            (16U)
/*! VALUE6 - VALUE6 */
#define PXP_HIST8_PARAM1_VALUE6(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE6_SHIFT)) & PXP_HIST8_PARAM1_VALUE6_MASK)

#define PXP_HIST8_PARAM1_RSVD6_MASK              (0xC00000U)
#define PXP_HIST8_PARAM1_RSVD6_SHIFT             (22U)
/*! RSVD6 - RSVD6 */
#define PXP_HIST8_PARAM1_RSVD6(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_RSVD6_SHIFT)) & PXP_HIST8_PARAM1_RSVD6_MASK)

#define PXP_HIST8_PARAM1_VALUE7_MASK             (0x3F000000U)
#define PXP_HIST8_PARAM1_VALUE7_SHIFT            (24U)
/*! VALUE7 - VALUE7 */
#define PXP_HIST8_PARAM1_VALUE7(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE7_SHIFT)) & PXP_HIST8_PARAM1_VALUE7_MASK)

#define PXP_HIST8_PARAM1_RSVD7_MASK              (0xC0000000U)
#define PXP_HIST8_PARAM1_RSVD7_SHIFT             (30U)
/*! RSVD7 - RSVD7 */
#define PXP_HIST8_PARAM1_RSVD7(x)                (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_RSVD7_SHIFT)) & PXP_HIST8_PARAM1_RSVD7_MASK)
/*! @} */

/*! @name HIST16_PARAM0 - 16-level Histogram Parameter 0 Register. */
/*! @{ */

#define PXP_HIST16_PARAM0_VALUE0_MASK            (0x3FU)
#define PXP_HIST16_PARAM0_VALUE0_SHIFT           (0U)
/*! VALUE0 - VALUE0 */
#define PXP_HIST16_PARAM0_VALUE0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE0_SHIFT)) & PXP_HIST16_PARAM0_VALUE0_MASK)

#define PXP_HIST16_PARAM0_RSVD0_MASK             (0xC0U)
#define PXP_HIST16_PARAM0_RSVD0_SHIFT            (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST16_PARAM0_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_RSVD0_SHIFT)) & PXP_HIST16_PARAM0_RSVD0_MASK)

#define PXP_HIST16_PARAM0_VALUE1_MASK            (0x3F00U)
#define PXP_HIST16_PARAM0_VALUE1_SHIFT           (8U)
/*! VALUE1 - VALUE1 */
#define PXP_HIST16_PARAM0_VALUE1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE1_SHIFT)) & PXP_HIST16_PARAM0_VALUE1_MASK)

#define PXP_HIST16_PARAM0_RSVD1_MASK             (0xC000U)
#define PXP_HIST16_PARAM0_RSVD1_SHIFT            (14U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST16_PARAM0_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_RSVD1_SHIFT)) & PXP_HIST16_PARAM0_RSVD1_MASK)

#define PXP_HIST16_PARAM0_VALUE2_MASK            (0x3F0000U)
#define PXP_HIST16_PARAM0_VALUE2_SHIFT           (16U)
/*! VALUE2 - VALUE2 */
#define PXP_HIST16_PARAM0_VALUE2(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE2_SHIFT)) & PXP_HIST16_PARAM0_VALUE2_MASK)

#define PXP_HIST16_PARAM0_RSVD2_MASK             (0xC00000U)
#define PXP_HIST16_PARAM0_RSVD2_SHIFT            (22U)
/*! RSVD2 - RSVD2 */
#define PXP_HIST16_PARAM0_RSVD2(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_RSVD2_SHIFT)) & PXP_HIST16_PARAM0_RSVD2_MASK)

#define PXP_HIST16_PARAM0_VALUE3_MASK            (0x3F000000U)
#define PXP_HIST16_PARAM0_VALUE3_SHIFT           (24U)
/*! VALUE3 - VALUE3 */
#define PXP_HIST16_PARAM0_VALUE3(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE3_SHIFT)) & PXP_HIST16_PARAM0_VALUE3_MASK)

#define PXP_HIST16_PARAM0_RSVD3_MASK             (0xC0000000U)
#define PXP_HIST16_PARAM0_RSVD3_SHIFT            (30U)
/*! RSVD3 - RSVD3 */
#define PXP_HIST16_PARAM0_RSVD3(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_RSVD3_SHIFT)) & PXP_HIST16_PARAM0_RSVD3_MASK)
/*! @} */

/*! @name HIST16_PARAM1 - 16-level Histogram Parameter 1 Register. */
/*! @{ */

#define PXP_HIST16_PARAM1_VALUE4_MASK            (0x3FU)
#define PXP_HIST16_PARAM1_VALUE4_SHIFT           (0U)
/*! VALUE4 - VALUE4 */
#define PXP_HIST16_PARAM1_VALUE4(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE4_SHIFT)) & PXP_HIST16_PARAM1_VALUE4_MASK)

#define PXP_HIST16_PARAM1_RSVD4_MASK             (0xC0U)
#define PXP_HIST16_PARAM1_RSVD4_SHIFT            (6U)
/*! RSVD4 - RSVD4 */
#define PXP_HIST16_PARAM1_RSVD4(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_RSVD4_SHIFT)) & PXP_HIST16_PARAM1_RSVD4_MASK)

#define PXP_HIST16_PARAM1_VALUE5_MASK            (0x3F00U)
#define PXP_HIST16_PARAM1_VALUE5_SHIFT           (8U)
/*! VALUE5 - VALUE5 */
#define PXP_HIST16_PARAM1_VALUE5(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE5_SHIFT)) & PXP_HIST16_PARAM1_VALUE5_MASK)

#define PXP_HIST16_PARAM1_RSVD5_MASK             (0xC000U)
#define PXP_HIST16_PARAM1_RSVD5_SHIFT            (14U)
/*! RSVD5 - RSVD5 */
#define PXP_HIST16_PARAM1_RSVD5(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_RSVD5_SHIFT)) & PXP_HIST16_PARAM1_RSVD5_MASK)

#define PXP_HIST16_PARAM1_VALUE6_MASK            (0x3F0000U)
#define PXP_HIST16_PARAM1_VALUE6_SHIFT           (16U)
/*! VALUE6 - VALUE6 */
#define PXP_HIST16_PARAM1_VALUE6(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE6_SHIFT)) & PXP_HIST16_PARAM1_VALUE6_MASK)

#define PXP_HIST16_PARAM1_RSVD6_MASK             (0xC00000U)
#define PXP_HIST16_PARAM1_RSVD6_SHIFT            (22U)
/*! RSVD6 - RSVD6 */
#define PXP_HIST16_PARAM1_RSVD6(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_RSVD6_SHIFT)) & PXP_HIST16_PARAM1_RSVD6_MASK)

#define PXP_HIST16_PARAM1_VALUE7_MASK            (0x3F000000U)
#define PXP_HIST16_PARAM1_VALUE7_SHIFT           (24U)
/*! VALUE7 - VALUE7 */
#define PXP_HIST16_PARAM1_VALUE7(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE7_SHIFT)) & PXP_HIST16_PARAM1_VALUE7_MASK)

#define PXP_HIST16_PARAM1_RSVD7_MASK             (0xC0000000U)
#define PXP_HIST16_PARAM1_RSVD7_SHIFT            (30U)
/*! RSVD7 - RSVD7 */
#define PXP_HIST16_PARAM1_RSVD7(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_RSVD7_SHIFT)) & PXP_HIST16_PARAM1_RSVD7_MASK)
/*! @} */

/*! @name HIST16_PARAM2 - 16-level Histogram Parameter 2 Register. */
/*! @{ */

#define PXP_HIST16_PARAM2_VALUE8_MASK            (0x3FU)
#define PXP_HIST16_PARAM2_VALUE8_SHIFT           (0U)
/*! VALUE8 - VALUE8 */
#define PXP_HIST16_PARAM2_VALUE8(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE8_SHIFT)) & PXP_HIST16_PARAM2_VALUE8_MASK)

#define PXP_HIST16_PARAM2_RSVD8_MASK             (0xC0U)
#define PXP_HIST16_PARAM2_RSVD8_SHIFT            (6U)
/*! RSVD8 - RSVD8 */
#define PXP_HIST16_PARAM2_RSVD8(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_RSVD8_SHIFT)) & PXP_HIST16_PARAM2_RSVD8_MASK)

#define PXP_HIST16_PARAM2_VALUE9_MASK            (0x3F00U)
#define PXP_HIST16_PARAM2_VALUE9_SHIFT           (8U)
/*! VALUE9 - VALUE9 */
#define PXP_HIST16_PARAM2_VALUE9(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE9_SHIFT)) & PXP_HIST16_PARAM2_VALUE9_MASK)

#define PXP_HIST16_PARAM2_RSVD9_MASK             (0xC000U)
#define PXP_HIST16_PARAM2_RSVD9_SHIFT            (14U)
/*! RSVD9 - RSVD9 */
#define PXP_HIST16_PARAM2_RSVD9(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_RSVD9_SHIFT)) & PXP_HIST16_PARAM2_RSVD9_MASK)

#define PXP_HIST16_PARAM2_VALUE10_MASK           (0x3F0000U)
#define PXP_HIST16_PARAM2_VALUE10_SHIFT          (16U)
/*! VALUE10 - VALUE10 */
#define PXP_HIST16_PARAM2_VALUE10(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE10_SHIFT)) & PXP_HIST16_PARAM2_VALUE10_MASK)

#define PXP_HIST16_PARAM2_RSVD10_MASK            (0xC00000U)
#define PXP_HIST16_PARAM2_RSVD10_SHIFT           (22U)
/*! RSVD10 - RSVD10 */
#define PXP_HIST16_PARAM2_RSVD10(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_RSVD10_SHIFT)) & PXP_HIST16_PARAM2_RSVD10_MASK)

#define PXP_HIST16_PARAM2_VALUE11_MASK           (0x3F000000U)
#define PXP_HIST16_PARAM2_VALUE11_SHIFT          (24U)
/*! VALUE11 - VALUE11 */
#define PXP_HIST16_PARAM2_VALUE11(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE11_SHIFT)) & PXP_HIST16_PARAM2_VALUE11_MASK)

#define PXP_HIST16_PARAM2_RSVD11_MASK            (0xC0000000U)
#define PXP_HIST16_PARAM2_RSVD11_SHIFT           (30U)
/*! RSVD11 - RSVD11 */
#define PXP_HIST16_PARAM2_RSVD11(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_RSVD11_SHIFT)) & PXP_HIST16_PARAM2_RSVD11_MASK)
/*! @} */

/*! @name HIST16_PARAM3 - 16-level Histogram Parameter 3 Register. */
/*! @{ */

#define PXP_HIST16_PARAM3_VALUE12_MASK           (0x3FU)
#define PXP_HIST16_PARAM3_VALUE12_SHIFT          (0U)
/*! VALUE12 - VALUE12 */
#define PXP_HIST16_PARAM3_VALUE12(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE12_SHIFT)) & PXP_HIST16_PARAM3_VALUE12_MASK)

#define PXP_HIST16_PARAM3_RSVD12_MASK            (0xC0U)
#define PXP_HIST16_PARAM3_RSVD12_SHIFT           (6U)
/*! RSVD12 - RSVD12 */
#define PXP_HIST16_PARAM3_RSVD12(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_RSVD12_SHIFT)) & PXP_HIST16_PARAM3_RSVD12_MASK)

#define PXP_HIST16_PARAM3_VALUE13_MASK           (0x3F00U)
#define PXP_HIST16_PARAM3_VALUE13_SHIFT          (8U)
/*! VALUE13 - VALUE13 */
#define PXP_HIST16_PARAM3_VALUE13(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE13_SHIFT)) & PXP_HIST16_PARAM3_VALUE13_MASK)

#define PXP_HIST16_PARAM3_RSVD13_MASK            (0xC000U)
#define PXP_HIST16_PARAM3_RSVD13_SHIFT           (14U)
/*! RSVD13 - RSVD13 */
#define PXP_HIST16_PARAM3_RSVD13(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_RSVD13_SHIFT)) & PXP_HIST16_PARAM3_RSVD13_MASK)

#define PXP_HIST16_PARAM3_VALUE14_MASK           (0x3F0000U)
#define PXP_HIST16_PARAM3_VALUE14_SHIFT          (16U)
/*! VALUE14 - VALUE14 */
#define PXP_HIST16_PARAM3_VALUE14(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE14_SHIFT)) & PXP_HIST16_PARAM3_VALUE14_MASK)

#define PXP_HIST16_PARAM3_RSVD14_MASK            (0xC00000U)
#define PXP_HIST16_PARAM3_RSVD14_SHIFT           (22U)
/*! RSVD14 - RSVD14 */
#define PXP_HIST16_PARAM3_RSVD14(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_RSVD14_SHIFT)) & PXP_HIST16_PARAM3_RSVD14_MASK)

#define PXP_HIST16_PARAM3_VALUE15_MASK           (0x3F000000U)
#define PXP_HIST16_PARAM3_VALUE15_SHIFT          (24U)
/*! VALUE15 - VALUE15 */
#define PXP_HIST16_PARAM3_VALUE15(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE15_SHIFT)) & PXP_HIST16_PARAM3_VALUE15_MASK)

#define PXP_HIST16_PARAM3_RSVD15_MASK            (0xC0000000U)
#define PXP_HIST16_PARAM3_RSVD15_SHIFT           (30U)
/*! RSVD15 - RSVD15 */
#define PXP_HIST16_PARAM3_RSVD15(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_RSVD15_SHIFT)) & PXP_HIST16_PARAM3_RSVD15_MASK)
/*! @} */

/*! @name HIST32_PARAM0 - 32-level Histogram Parameter 0 Register. */
/*! @{ */

#define PXP_HIST32_PARAM0_VALUE0_MASK            (0x3FU)
#define PXP_HIST32_PARAM0_VALUE0_SHIFT           (0U)
/*! VALUE0 - VALUE0 */
#define PXP_HIST32_PARAM0_VALUE0(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE0_SHIFT)) & PXP_HIST32_PARAM0_VALUE0_MASK)

#define PXP_HIST32_PARAM0_RSVD0_MASK             (0xC0U)
#define PXP_HIST32_PARAM0_RSVD0_SHIFT            (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST32_PARAM0_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_RSVD0_SHIFT)) & PXP_HIST32_PARAM0_RSVD0_MASK)

#define PXP_HIST32_PARAM0_VALUE1_MASK            (0x3F00U)
#define PXP_HIST32_PARAM0_VALUE1_SHIFT           (8U)
/*! VALUE1 - VALUE1 */
#define PXP_HIST32_PARAM0_VALUE1(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE1_SHIFT)) & PXP_HIST32_PARAM0_VALUE1_MASK)

#define PXP_HIST32_PARAM0_RSVD1_MASK             (0xC000U)
#define PXP_HIST32_PARAM0_RSVD1_SHIFT            (14U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST32_PARAM0_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_RSVD1_SHIFT)) & PXP_HIST32_PARAM0_RSVD1_MASK)

#define PXP_HIST32_PARAM0_VALUE2_MASK            (0x3F0000U)
#define PXP_HIST32_PARAM0_VALUE2_SHIFT           (16U)
/*! VALUE2 - VALUE2 */
#define PXP_HIST32_PARAM0_VALUE2(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE2_SHIFT)) & PXP_HIST32_PARAM0_VALUE2_MASK)

#define PXP_HIST32_PARAM0_RSVD2_MASK             (0xC00000U)
#define PXP_HIST32_PARAM0_RSVD2_SHIFT            (22U)
/*! RSVD2 - RSVD2 */
#define PXP_HIST32_PARAM0_RSVD2(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_RSVD2_SHIFT)) & PXP_HIST32_PARAM0_RSVD2_MASK)

#define PXP_HIST32_PARAM0_VALUE3_MASK            (0x3F000000U)
#define PXP_HIST32_PARAM0_VALUE3_SHIFT           (24U)
/*! VALUE3 - VALUE3 */
#define PXP_HIST32_PARAM0_VALUE3(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE3_SHIFT)) & PXP_HIST32_PARAM0_VALUE3_MASK)

#define PXP_HIST32_PARAM0_RSVD3_MASK             (0xC0000000U)
#define PXP_HIST32_PARAM0_RSVD3_SHIFT            (30U)
/*! RSVD3 - RSVD3 */
#define PXP_HIST32_PARAM0_RSVD3(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_RSVD3_SHIFT)) & PXP_HIST32_PARAM0_RSVD3_MASK)
/*! @} */

/*! @name HIST32_PARAM1 - 32-level Histogram Parameter 1 Register. */
/*! @{ */

#define PXP_HIST32_PARAM1_VALUE4_MASK            (0x3FU)
#define PXP_HIST32_PARAM1_VALUE4_SHIFT           (0U)
/*! VALUE4 - VALUE4 */
#define PXP_HIST32_PARAM1_VALUE4(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE4_SHIFT)) & PXP_HIST32_PARAM1_VALUE4_MASK)

#define PXP_HIST32_PARAM1_RSVD4_MASK             (0xC0U)
#define PXP_HIST32_PARAM1_RSVD4_SHIFT            (6U)
/*! RSVD4 - RSVD4 */
#define PXP_HIST32_PARAM1_RSVD4(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_RSVD4_SHIFT)) & PXP_HIST32_PARAM1_RSVD4_MASK)

#define PXP_HIST32_PARAM1_VALUE5_MASK            (0x3F00U)
#define PXP_HIST32_PARAM1_VALUE5_SHIFT           (8U)
/*! VALUE5 - VALUE5 */
#define PXP_HIST32_PARAM1_VALUE5(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE5_SHIFT)) & PXP_HIST32_PARAM1_VALUE5_MASK)

#define PXP_HIST32_PARAM1_RSVD5_MASK             (0xC000U)
#define PXP_HIST32_PARAM1_RSVD5_SHIFT            (14U)
/*! RSVD5 - RSVD5 */
#define PXP_HIST32_PARAM1_RSVD5(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_RSVD5_SHIFT)) & PXP_HIST32_PARAM1_RSVD5_MASK)

#define PXP_HIST32_PARAM1_VALUE6_MASK            (0x3F0000U)
#define PXP_HIST32_PARAM1_VALUE6_SHIFT           (16U)
/*! VALUE6 - VALUE6 */
#define PXP_HIST32_PARAM1_VALUE6(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE6_SHIFT)) & PXP_HIST32_PARAM1_VALUE6_MASK)

#define PXP_HIST32_PARAM1_RSVD6_MASK             (0xC00000U)
#define PXP_HIST32_PARAM1_RSVD6_SHIFT            (22U)
/*! RSVD6 - RSVD6 */
#define PXP_HIST32_PARAM1_RSVD6(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_RSVD6_SHIFT)) & PXP_HIST32_PARAM1_RSVD6_MASK)

#define PXP_HIST32_PARAM1_VALUE7_MASK            (0x3F000000U)
#define PXP_HIST32_PARAM1_VALUE7_SHIFT           (24U)
/*! VALUE7 - VALUE7 */
#define PXP_HIST32_PARAM1_VALUE7(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE7_SHIFT)) & PXP_HIST32_PARAM1_VALUE7_MASK)

#define PXP_HIST32_PARAM1_RSVD7_MASK             (0xC0000000U)
#define PXP_HIST32_PARAM1_RSVD7_SHIFT            (30U)
/*! RSVD7 - RSVD7 */
#define PXP_HIST32_PARAM1_RSVD7(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_RSVD7_SHIFT)) & PXP_HIST32_PARAM1_RSVD7_MASK)
/*! @} */

/*! @name HIST32_PARAM2 - 32-level Histogram Parameter 2 Register. */
/*! @{ */

#define PXP_HIST32_PARAM2_VALUE8_MASK            (0x3FU)
#define PXP_HIST32_PARAM2_VALUE8_SHIFT           (0U)
/*! VALUE8 - VALUE8 */
#define PXP_HIST32_PARAM2_VALUE8(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE8_SHIFT)) & PXP_HIST32_PARAM2_VALUE8_MASK)

#define PXP_HIST32_PARAM2_RSVD8_MASK             (0xC0U)
#define PXP_HIST32_PARAM2_RSVD8_SHIFT            (6U)
/*! RSVD8 - RSVD8 */
#define PXP_HIST32_PARAM2_RSVD8(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_RSVD8_SHIFT)) & PXP_HIST32_PARAM2_RSVD8_MASK)

#define PXP_HIST32_PARAM2_VALUE9_MASK            (0x3F00U)
#define PXP_HIST32_PARAM2_VALUE9_SHIFT           (8U)
/*! VALUE9 - VALUE9 */
#define PXP_HIST32_PARAM2_VALUE9(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE9_SHIFT)) & PXP_HIST32_PARAM2_VALUE9_MASK)

#define PXP_HIST32_PARAM2_RSVD9_MASK             (0xC000U)
#define PXP_HIST32_PARAM2_RSVD9_SHIFT            (14U)
/*! RSVD9 - RSVD9 */
#define PXP_HIST32_PARAM2_RSVD9(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_RSVD9_SHIFT)) & PXP_HIST32_PARAM2_RSVD9_MASK)

#define PXP_HIST32_PARAM2_VALUE10_MASK           (0x3F0000U)
#define PXP_HIST32_PARAM2_VALUE10_SHIFT          (16U)
/*! VALUE10 - VALUE10 */
#define PXP_HIST32_PARAM2_VALUE10(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE10_SHIFT)) & PXP_HIST32_PARAM2_VALUE10_MASK)

#define PXP_HIST32_PARAM2_RSVD10_MASK            (0xC00000U)
#define PXP_HIST32_PARAM2_RSVD10_SHIFT           (22U)
/*! RSVD10 - RSVD10 */
#define PXP_HIST32_PARAM2_RSVD10(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_RSVD10_SHIFT)) & PXP_HIST32_PARAM2_RSVD10_MASK)

#define PXP_HIST32_PARAM2_VALUE11_MASK           (0x3F000000U)
#define PXP_HIST32_PARAM2_VALUE11_SHIFT          (24U)
/*! VALUE11 - VALUE11 */
#define PXP_HIST32_PARAM2_VALUE11(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE11_SHIFT)) & PXP_HIST32_PARAM2_VALUE11_MASK)

#define PXP_HIST32_PARAM2_RSVD11_MASK            (0xC0000000U)
#define PXP_HIST32_PARAM2_RSVD11_SHIFT           (30U)
/*! RSVD11 - RSVD11 */
#define PXP_HIST32_PARAM2_RSVD11(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_RSVD11_SHIFT)) & PXP_HIST32_PARAM2_RSVD11_MASK)
/*! @} */

/*! @name HIST32_PARAM3 - 32-level Histogram Parameter 3 Register. */
/*! @{ */

#define PXP_HIST32_PARAM3_VALUE12_MASK           (0x3FU)
#define PXP_HIST32_PARAM3_VALUE12_SHIFT          (0U)
/*! VALUE12 - VALUE12 */
#define PXP_HIST32_PARAM3_VALUE12(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE12_SHIFT)) & PXP_HIST32_PARAM3_VALUE12_MASK)

#define PXP_HIST32_PARAM3_RSVD12_MASK            (0xC0U)
#define PXP_HIST32_PARAM3_RSVD12_SHIFT           (6U)
/*! RSVD12 - RSVD12 */
#define PXP_HIST32_PARAM3_RSVD12(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_RSVD12_SHIFT)) & PXP_HIST32_PARAM3_RSVD12_MASK)

#define PXP_HIST32_PARAM3_VALUE13_MASK           (0x3F00U)
#define PXP_HIST32_PARAM3_VALUE13_SHIFT          (8U)
/*! VALUE13 - VALUE13 */
#define PXP_HIST32_PARAM3_VALUE13(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE13_SHIFT)) & PXP_HIST32_PARAM3_VALUE13_MASK)

#define PXP_HIST32_PARAM3_RSVD13_MASK            (0xC000U)
#define PXP_HIST32_PARAM3_RSVD13_SHIFT           (14U)
/*! RSVD13 - RSVD13 */
#define PXP_HIST32_PARAM3_RSVD13(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_RSVD13_SHIFT)) & PXP_HIST32_PARAM3_RSVD13_MASK)

#define PXP_HIST32_PARAM3_VALUE14_MASK           (0x3F0000U)
#define PXP_HIST32_PARAM3_VALUE14_SHIFT          (16U)
/*! VALUE14 - VALUE14 */
#define PXP_HIST32_PARAM3_VALUE14(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE14_SHIFT)) & PXP_HIST32_PARAM3_VALUE14_MASK)

#define PXP_HIST32_PARAM3_RSVD14_MASK            (0xC00000U)
#define PXP_HIST32_PARAM3_RSVD14_SHIFT           (22U)
/*! RSVD14 - RSVD14 */
#define PXP_HIST32_PARAM3_RSVD14(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_RSVD14_SHIFT)) & PXP_HIST32_PARAM3_RSVD14_MASK)

#define PXP_HIST32_PARAM3_VALUE15_MASK           (0x3F000000U)
#define PXP_HIST32_PARAM3_VALUE15_SHIFT          (24U)
/*! VALUE15 - VALUE15 */
#define PXP_HIST32_PARAM3_VALUE15(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE15_SHIFT)) & PXP_HIST32_PARAM3_VALUE15_MASK)

#define PXP_HIST32_PARAM3_RSVD15_MASK            (0xC0000000U)
#define PXP_HIST32_PARAM3_RSVD15_SHIFT           (30U)
/*! RSVD15 - RSVD15 */
#define PXP_HIST32_PARAM3_RSVD15(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_RSVD15_SHIFT)) & PXP_HIST32_PARAM3_RSVD15_MASK)
/*! @} */

/*! @name HIST32_PARAM4 - 32-level Histogram Parameter 0 Register. */
/*! @{ */

#define PXP_HIST32_PARAM4_VALUE16_MASK           (0x3FU)
#define PXP_HIST32_PARAM4_VALUE16_SHIFT          (0U)
/*! VALUE16 - VALUE16 */
#define PXP_HIST32_PARAM4_VALUE16(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE16_SHIFT)) & PXP_HIST32_PARAM4_VALUE16_MASK)

#define PXP_HIST32_PARAM4_RSVD0_MASK             (0xC0U)
#define PXP_HIST32_PARAM4_RSVD0_SHIFT            (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HIST32_PARAM4_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_RSVD0_SHIFT)) & PXP_HIST32_PARAM4_RSVD0_MASK)

#define PXP_HIST32_PARAM4_VALUE17_MASK           (0x3F00U)
#define PXP_HIST32_PARAM4_VALUE17_SHIFT          (8U)
/*! VALUE17 - VALUE17 */
#define PXP_HIST32_PARAM4_VALUE17(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE17_SHIFT)) & PXP_HIST32_PARAM4_VALUE17_MASK)

#define PXP_HIST32_PARAM4_RSVD1_MASK             (0xC000U)
#define PXP_HIST32_PARAM4_RSVD1_SHIFT            (14U)
/*! RSVD1 - RSVD1 */
#define PXP_HIST32_PARAM4_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_RSVD1_SHIFT)) & PXP_HIST32_PARAM4_RSVD1_MASK)

#define PXP_HIST32_PARAM4_VALUE18_MASK           (0x3F0000U)
#define PXP_HIST32_PARAM4_VALUE18_SHIFT          (16U)
/*! VALUE18 - VALUE18 */
#define PXP_HIST32_PARAM4_VALUE18(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE18_SHIFT)) & PXP_HIST32_PARAM4_VALUE18_MASK)

#define PXP_HIST32_PARAM4_RSVD2_MASK             (0xC00000U)
#define PXP_HIST32_PARAM4_RSVD2_SHIFT            (22U)
/*! RSVD2 - RSVD2 */
#define PXP_HIST32_PARAM4_RSVD2(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_RSVD2_SHIFT)) & PXP_HIST32_PARAM4_RSVD2_MASK)

#define PXP_HIST32_PARAM4_VALUE19_MASK           (0x3F000000U)
#define PXP_HIST32_PARAM4_VALUE19_SHIFT          (24U)
/*! VALUE19 - VALUE19 */
#define PXP_HIST32_PARAM4_VALUE19(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE19_SHIFT)) & PXP_HIST32_PARAM4_VALUE19_MASK)

#define PXP_HIST32_PARAM4_RSVD3_MASK             (0xC0000000U)
#define PXP_HIST32_PARAM4_RSVD3_SHIFT            (30U)
/*! RSVD3 - RSVD3 */
#define PXP_HIST32_PARAM4_RSVD3(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_RSVD3_SHIFT)) & PXP_HIST32_PARAM4_RSVD3_MASK)
/*! @} */

/*! @name HIST32_PARAM5 - 32-level Histogram Parameter 1 Register. */
/*! @{ */

#define PXP_HIST32_PARAM5_VALUE20_MASK           (0x3FU)
#define PXP_HIST32_PARAM5_VALUE20_SHIFT          (0U)
/*! VALUE20 - VALUE20 */
#define PXP_HIST32_PARAM5_VALUE20(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE20_SHIFT)) & PXP_HIST32_PARAM5_VALUE20_MASK)

#define PXP_HIST32_PARAM5_RSVD4_MASK             (0xC0U)
#define PXP_HIST32_PARAM5_RSVD4_SHIFT            (6U)
/*! RSVD4 - RSVD4 */
#define PXP_HIST32_PARAM5_RSVD4(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_RSVD4_SHIFT)) & PXP_HIST32_PARAM5_RSVD4_MASK)

#define PXP_HIST32_PARAM5_VALUE21_MASK           (0x3F00U)
#define PXP_HIST32_PARAM5_VALUE21_SHIFT          (8U)
/*! VALUE21 - VALUE21 */
#define PXP_HIST32_PARAM5_VALUE21(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE21_SHIFT)) & PXP_HIST32_PARAM5_VALUE21_MASK)

#define PXP_HIST32_PARAM5_RSVD5_MASK             (0xC000U)
#define PXP_HIST32_PARAM5_RSVD5_SHIFT            (14U)
/*! RSVD5 - RSVD5 */
#define PXP_HIST32_PARAM5_RSVD5(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_RSVD5_SHIFT)) & PXP_HIST32_PARAM5_RSVD5_MASK)

#define PXP_HIST32_PARAM5_VALUE22_MASK           (0x3F0000U)
#define PXP_HIST32_PARAM5_VALUE22_SHIFT          (16U)
/*! VALUE22 - VALUE22 */
#define PXP_HIST32_PARAM5_VALUE22(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE22_SHIFT)) & PXP_HIST32_PARAM5_VALUE22_MASK)

#define PXP_HIST32_PARAM5_RSVD6_MASK             (0xC00000U)
#define PXP_HIST32_PARAM5_RSVD6_SHIFT            (22U)
/*! RSVD6 - RSVD6 */
#define PXP_HIST32_PARAM5_RSVD6(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_RSVD6_SHIFT)) & PXP_HIST32_PARAM5_RSVD6_MASK)

#define PXP_HIST32_PARAM5_VALUE23_MASK           (0x3F000000U)
#define PXP_HIST32_PARAM5_VALUE23_SHIFT          (24U)
/*! VALUE23 - VALUE23 */
#define PXP_HIST32_PARAM5_VALUE23(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE23_SHIFT)) & PXP_HIST32_PARAM5_VALUE23_MASK)

#define PXP_HIST32_PARAM5_RSVD7_MASK             (0xC0000000U)
#define PXP_HIST32_PARAM5_RSVD7_SHIFT            (30U)
/*! RSVD7 - RSVD7 */
#define PXP_HIST32_PARAM5_RSVD7(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_RSVD7_SHIFT)) & PXP_HIST32_PARAM5_RSVD7_MASK)
/*! @} */

/*! @name HIST32_PARAM6 - 32-level Histogram Parameter 2 Register. */
/*! @{ */

#define PXP_HIST32_PARAM6_VALUE24_MASK           (0x3FU)
#define PXP_HIST32_PARAM6_VALUE24_SHIFT          (0U)
/*! VALUE24 - VALUE24 */
#define PXP_HIST32_PARAM6_VALUE24(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE24_SHIFT)) & PXP_HIST32_PARAM6_VALUE24_MASK)

#define PXP_HIST32_PARAM6_RSVD8_MASK             (0xC0U)
#define PXP_HIST32_PARAM6_RSVD8_SHIFT            (6U)
/*! RSVD8 - RSVD8 */
#define PXP_HIST32_PARAM6_RSVD8(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_RSVD8_SHIFT)) & PXP_HIST32_PARAM6_RSVD8_MASK)

#define PXP_HIST32_PARAM6_VALUE25_MASK           (0x3F00U)
#define PXP_HIST32_PARAM6_VALUE25_SHIFT          (8U)
/*! VALUE25 - VALUE25 */
#define PXP_HIST32_PARAM6_VALUE25(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE25_SHIFT)) & PXP_HIST32_PARAM6_VALUE25_MASK)

#define PXP_HIST32_PARAM6_RSVD9_MASK             (0xC000U)
#define PXP_HIST32_PARAM6_RSVD9_SHIFT            (14U)
/*! RSVD9 - RSVD9 */
#define PXP_HIST32_PARAM6_RSVD9(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_RSVD9_SHIFT)) & PXP_HIST32_PARAM6_RSVD9_MASK)

#define PXP_HIST32_PARAM6_VALUE26_MASK           (0x3F0000U)
#define PXP_HIST32_PARAM6_VALUE26_SHIFT          (16U)
/*! VALUE26 - VALUE26 */
#define PXP_HIST32_PARAM6_VALUE26(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE26_SHIFT)) & PXP_HIST32_PARAM6_VALUE26_MASK)

#define PXP_HIST32_PARAM6_RSVD10_MASK            (0xC00000U)
#define PXP_HIST32_PARAM6_RSVD10_SHIFT           (22U)
/*! RSVD10 - RSVD10 */
#define PXP_HIST32_PARAM6_RSVD10(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_RSVD10_SHIFT)) & PXP_HIST32_PARAM6_RSVD10_MASK)

#define PXP_HIST32_PARAM6_VALUE27_MASK           (0x3F000000U)
#define PXP_HIST32_PARAM6_VALUE27_SHIFT          (24U)
/*! VALUE27 - VALUE27 */
#define PXP_HIST32_PARAM6_VALUE27(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE27_SHIFT)) & PXP_HIST32_PARAM6_VALUE27_MASK)

#define PXP_HIST32_PARAM6_RSVD11_MASK            (0xC0000000U)
#define PXP_HIST32_PARAM6_RSVD11_SHIFT           (30U)
/*! RSVD11 - RSVD11 */
#define PXP_HIST32_PARAM6_RSVD11(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_RSVD11_SHIFT)) & PXP_HIST32_PARAM6_RSVD11_MASK)
/*! @} */

/*! @name HIST32_PARAM7 - 32-level Histogram Parameter 3 Register. */
/*! @{ */

#define PXP_HIST32_PARAM7_VALUE28_MASK           (0x3FU)
#define PXP_HIST32_PARAM7_VALUE28_SHIFT          (0U)
/*! VALUE28 - VALUE28 */
#define PXP_HIST32_PARAM7_VALUE28(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE28_SHIFT)) & PXP_HIST32_PARAM7_VALUE28_MASK)

#define PXP_HIST32_PARAM7_RSVD2_MASK             (0xC0U)
#define PXP_HIST32_PARAM7_RSVD2_SHIFT            (6U)
/*! RSVD2 - RSVD2 */
#define PXP_HIST32_PARAM7_RSVD2(x)               (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_RSVD2_SHIFT)) & PXP_HIST32_PARAM7_RSVD2_MASK)

#define PXP_HIST32_PARAM7_VALUE29_MASK           (0x3F00U)
#define PXP_HIST32_PARAM7_VALUE29_SHIFT          (8U)
/*! VALUE29 - VALUE29 */
#define PXP_HIST32_PARAM7_VALUE29(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE29_SHIFT)) & PXP_HIST32_PARAM7_VALUE29_MASK)

#define PXP_HIST32_PARAM7_RSVD13_MASK            (0xC000U)
#define PXP_HIST32_PARAM7_RSVD13_SHIFT           (14U)
/*! RSVD13 - RSVD13 */
#define PXP_HIST32_PARAM7_RSVD13(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_RSVD13_SHIFT)) & PXP_HIST32_PARAM7_RSVD13_MASK)

#define PXP_HIST32_PARAM7_VALUE30_MASK           (0x3F0000U)
#define PXP_HIST32_PARAM7_VALUE30_SHIFT          (16U)
/*! VALUE30 - VALUE30 */
#define PXP_HIST32_PARAM7_VALUE30(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE30_SHIFT)) & PXP_HIST32_PARAM7_VALUE30_MASK)

#define PXP_HIST32_PARAM7_RSVD14_MASK            (0xC00000U)
#define PXP_HIST32_PARAM7_RSVD14_SHIFT           (22U)
/*! RSVD14 - RSVD14 */
#define PXP_HIST32_PARAM7_RSVD14(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_RSVD14_SHIFT)) & PXP_HIST32_PARAM7_RSVD14_MASK)

#define PXP_HIST32_PARAM7_VALUE31_MASK           (0x3F000000U)
#define PXP_HIST32_PARAM7_VALUE31_SHIFT          (24U)
/*! VALUE31 - VALUE31 */
#define PXP_HIST32_PARAM7_VALUE31(x)             (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE31_SHIFT)) & PXP_HIST32_PARAM7_VALUE31_MASK)

#define PXP_HIST32_PARAM7_RSVD15_MASK            (0xC0000000U)
#define PXP_HIST32_PARAM7_RSVD15_SHIFT           (30U)
/*! RSVD15 - RSVD15 */
#define PXP_HIST32_PARAM7_RSVD15(x)              (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_RSVD15_SHIFT)) & PXP_HIST32_PARAM7_RSVD15_MASK)
/*! @} */

/*! @name COMP_CTRL -  */
/*! @{ */

#define PXP_COMP_CTRL_START_MASK                 (0x1U)
#define PXP_COMP_CTRL_START_SHIFT                (0U)
/*! START - START */
#define PXP_COMP_CTRL_START(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_START_SHIFT)) & PXP_COMP_CTRL_START_MASK)

#define PXP_COMP_CTRL_RSVD1_MASK                 (0xFEU)
#define PXP_COMP_CTRL_RSVD1_SHIFT                (1U)
/*! RSVD1 - RSVD1 */
#define PXP_COMP_CTRL_RSVD1(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_RSVD1_SHIFT)) & PXP_COMP_CTRL_RSVD1_MASK)

#define PXP_COMP_CTRL_SW_RESET_MASK              (0x100U)
#define PXP_COMP_CTRL_SW_RESET_SHIFT             (8U)
/*! SW_RESET - SW_RESET */
#define PXP_COMP_CTRL_SW_RESET(x)                (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_SW_RESET_SHIFT)) & PXP_COMP_CTRL_SW_RESET_MASK)

#define PXP_COMP_CTRL_RSVD0_MASK                 (0xFFFFFE00U)
#define PXP_COMP_CTRL_RSVD0_SHIFT                (9U)
/*! RSVD0 - RSVD0 */
#define PXP_COMP_CTRL_RSVD0(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_RSVD0_SHIFT)) & PXP_COMP_CTRL_RSVD0_MASK)
/*! @} */

/*! @name COMP_CTRL_SET -  */
/*! @{ */

#define PXP_COMP_CTRL_SET_START_MASK             (0x1U)
#define PXP_COMP_CTRL_SET_START_SHIFT            (0U)
/*! START - START */
#define PXP_COMP_CTRL_SET_START(x)               (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_SET_START_SHIFT)) & PXP_COMP_CTRL_SET_START_MASK)

#define PXP_COMP_CTRL_SET_RSVD1_MASK             (0xFEU)
#define PXP_COMP_CTRL_SET_RSVD1_SHIFT            (1U)
/*! RSVD1 - RSVD1 */
#define PXP_COMP_CTRL_SET_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_SET_RSVD1_SHIFT)) & PXP_COMP_CTRL_SET_RSVD1_MASK)

#define PXP_COMP_CTRL_SET_SW_RESET_MASK          (0x100U)
#define PXP_COMP_CTRL_SET_SW_RESET_SHIFT         (8U)
/*! SW_RESET - SW_RESET */
#define PXP_COMP_CTRL_SET_SW_RESET(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_SET_SW_RESET_SHIFT)) & PXP_COMP_CTRL_SET_SW_RESET_MASK)

#define PXP_COMP_CTRL_SET_RSVD0_MASK             (0xFFFFFE00U)
#define PXP_COMP_CTRL_SET_RSVD0_SHIFT            (9U)
/*! RSVD0 - RSVD0 */
#define PXP_COMP_CTRL_SET_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_SET_RSVD0_SHIFT)) & PXP_COMP_CTRL_SET_RSVD0_MASK)
/*! @} */

/*! @name COMP_CTRL_CLR -  */
/*! @{ */

#define PXP_COMP_CTRL_CLR_START_MASK             (0x1U)
#define PXP_COMP_CTRL_CLR_START_SHIFT            (0U)
/*! START - START */
#define PXP_COMP_CTRL_CLR_START(x)               (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_CLR_START_SHIFT)) & PXP_COMP_CTRL_CLR_START_MASK)

#define PXP_COMP_CTRL_CLR_RSVD1_MASK             (0xFEU)
#define PXP_COMP_CTRL_CLR_RSVD1_SHIFT            (1U)
/*! RSVD1 - RSVD1 */
#define PXP_COMP_CTRL_CLR_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_CLR_RSVD1_SHIFT)) & PXP_COMP_CTRL_CLR_RSVD1_MASK)

#define PXP_COMP_CTRL_CLR_SW_RESET_MASK          (0x100U)
#define PXP_COMP_CTRL_CLR_SW_RESET_SHIFT         (8U)
/*! SW_RESET - SW_RESET */
#define PXP_COMP_CTRL_CLR_SW_RESET(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_CLR_SW_RESET_SHIFT)) & PXP_COMP_CTRL_CLR_SW_RESET_MASK)

#define PXP_COMP_CTRL_CLR_RSVD0_MASK             (0xFFFFFE00U)
#define PXP_COMP_CTRL_CLR_RSVD0_SHIFT            (9U)
/*! RSVD0 - RSVD0 */
#define PXP_COMP_CTRL_CLR_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_CLR_RSVD0_SHIFT)) & PXP_COMP_CTRL_CLR_RSVD0_MASK)
/*! @} */

/*! @name COMP_CTRL_TOG -  */
/*! @{ */

#define PXP_COMP_CTRL_TOG_START_MASK             (0x1U)
#define PXP_COMP_CTRL_TOG_START_SHIFT            (0U)
/*! START - START */
#define PXP_COMP_CTRL_TOG_START(x)               (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_TOG_START_SHIFT)) & PXP_COMP_CTRL_TOG_START_MASK)

#define PXP_COMP_CTRL_TOG_RSVD1_MASK             (0xFEU)
#define PXP_COMP_CTRL_TOG_RSVD1_SHIFT            (1U)
/*! RSVD1 - RSVD1 */
#define PXP_COMP_CTRL_TOG_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_TOG_RSVD1_SHIFT)) & PXP_COMP_CTRL_TOG_RSVD1_MASK)

#define PXP_COMP_CTRL_TOG_SW_RESET_MASK          (0x100U)
#define PXP_COMP_CTRL_TOG_SW_RESET_SHIFT         (8U)
/*! SW_RESET - SW_RESET */
#define PXP_COMP_CTRL_TOG_SW_RESET(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_TOG_SW_RESET_SHIFT)) & PXP_COMP_CTRL_TOG_SW_RESET_MASK)

#define PXP_COMP_CTRL_TOG_RSVD0_MASK             (0xFFFFFE00U)
#define PXP_COMP_CTRL_TOG_RSVD0_SHIFT            (9U)
/*! RSVD0 - RSVD0 */
#define PXP_COMP_CTRL_TOG_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << PXP_COMP_CTRL_TOG_RSVD0_SHIFT)) & PXP_COMP_CTRL_TOG_RSVD0_MASK)
/*! @} */

/*! @name COMP_FORMAT0 -  */
/*! @{ */

#define PXP_COMP_FORMAT0_FLAG_32B_MASK           (0x1U)
#define PXP_COMP_FORMAT0_FLAG_32B_SHIFT          (0U)
/*! FLAG_32B - FLAG_32B */
#define PXP_COMP_FORMAT0_FLAG_32B(x)             (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_FLAG_32B_SHIFT)) & PXP_COMP_FORMAT0_FLAG_32B_MASK)

#define PXP_COMP_FORMAT0_DISABLE_VALID_FIX_MASK  (0x2U)
#define PXP_COMP_FORMAT0_DISABLE_VALID_FIX_SHIFT (1U)
/*! DISABLE_VALID_FIX - DISABLE_VALID_FIX */
#define PXP_COMP_FORMAT0_DISABLE_VALID_FIX(x)    (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_DISABLE_VALID_FIX_SHIFT)) & PXP_COMP_FORMAT0_DISABLE_VALID_FIX_MASK)

#define PXP_COMP_FORMAT0_RSVD3_MASK              (0xCU)
#define PXP_COMP_FORMAT0_RSVD3_SHIFT             (2U)
/*! RSVD3 - RSVD3 */
#define PXP_COMP_FORMAT0_RSVD3(x)                (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_RSVD3_SHIFT)) & PXP_COMP_FORMAT0_RSVD3_MASK)

#define PXP_COMP_FORMAT0_FIELD_NUM_MASK          (0x30U)
#define PXP_COMP_FORMAT0_FIELD_NUM_SHIFT         (4U)
/*! FIELD_NUM - FIELD_NUM */
#define PXP_COMP_FORMAT0_FIELD_NUM(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_FIELD_NUM_SHIFT)) & PXP_COMP_FORMAT0_FIELD_NUM_MASK)

#define PXP_COMP_FORMAT0_RSVD2_MASK              (0xC0U)
#define PXP_COMP_FORMAT0_RSVD2_SHIFT             (6U)
/*! RSVD2 - RSVD2 */
#define PXP_COMP_FORMAT0_RSVD2(x)                (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_RSVD2_SHIFT)) & PXP_COMP_FORMAT0_RSVD2_MASK)

#define PXP_COMP_FORMAT0_MASK_INDEX_MASK         (0x300U)
#define PXP_COMP_FORMAT0_MASK_INDEX_SHIFT        (8U)
/*! MASK_INDEX - MASK_INDEX */
#define PXP_COMP_FORMAT0_MASK_INDEX(x)           (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_MASK_INDEX_SHIFT)) & PXP_COMP_FORMAT0_MASK_INDEX_MASK)

#define PXP_COMP_FORMAT0_RSVD1_MASK              (0xFC00U)
#define PXP_COMP_FORMAT0_RSVD1_SHIFT             (10U)
/*! RSVD1 - RSVD1 */
#define PXP_COMP_FORMAT0_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_RSVD1_SHIFT)) & PXP_COMP_FORMAT0_RSVD1_MASK)

#define PXP_COMP_FORMAT0_PIXEL_PITCH_64B_MASK    (0x3FF0000U)
#define PXP_COMP_FORMAT0_PIXEL_PITCH_64B_SHIFT   (16U)
/*! PIXEL_PITCH_64B - PIXEL_PITCH_64B */
#define PXP_COMP_FORMAT0_PIXEL_PITCH_64B(x)      (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_PIXEL_PITCH_64B_SHIFT)) & PXP_COMP_FORMAT0_PIXEL_PITCH_64B_MASK)

#define PXP_COMP_FORMAT0_ERR_PRONE_MASK          (0x4000000U)
#define PXP_COMP_FORMAT0_ERR_PRONE_SHIFT         (26U)
/*! ERR_PRONE - ERR_PRONE */
#define PXP_COMP_FORMAT0_ERR_PRONE(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_ERR_PRONE_SHIFT)) & PXP_COMP_FORMAT0_ERR_PRONE_MASK)

#define PXP_COMP_FORMAT0_FIFOFULL_MASK           (0x8000000U)
#define PXP_COMP_FORMAT0_FIFOFULL_SHIFT          (27U)
/*! FIFOFULL - FIFOFULL */
#define PXP_COMP_FORMAT0_FIFOFULL(x)             (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_FIFOFULL_SHIFT)) & PXP_COMP_FORMAT0_FIFOFULL_MASK)

#define PXP_COMP_FORMAT0_RSVD0_MASK              (0xF0000000U)
#define PXP_COMP_FORMAT0_RSVD0_SHIFT             (28U)
/*! RSVD0 - RSVD0 */
#define PXP_COMP_FORMAT0_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_RSVD0_SHIFT)) & PXP_COMP_FORMAT0_RSVD0_MASK)
/*! @} */

/*! @name COMP_FORMAT0_SET -  */
/*! @{ */

#define PXP_COMP_FORMAT0_SET_FLAG_32B_MASK       (0x1U)
#define PXP_COMP_FORMAT0_SET_FLAG_32B_SHIFT      (0U)
/*! FLAG_32B - FLAG_32B */
#define PXP_COMP_FORMAT0_SET_FLAG_32B(x)         (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_SET_FLAG_32B_SHIFT)) & PXP_COMP_FORMAT0_SET_FLAG_32B_MASK)

#define PXP_COMP_FORMAT0_SET_DISABLE_VALID_FIX_MASK (0x2U)
#define PXP_COMP_FORMAT0_SET_DISABLE_VALID_FIX_SHIFT (1U)
/*! DISABLE_VALID_FIX - DISABLE_VALID_FIX */
#define PXP_COMP_FORMAT0_SET_DISABLE_VALID_FIX(x) (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_SET_DISABLE_VALID_FIX_SHIFT)) & PXP_COMP_FORMAT0_SET_DISABLE_VALID_FIX_MASK)

#define PXP_COMP_FORMAT0_SET_RSVD3_MASK          (0xCU)
#define PXP_COMP_FORMAT0_SET_RSVD3_SHIFT         (2U)
/*! RSVD3 - RSVD3 */
#define PXP_COMP_FORMAT0_SET_RSVD3(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_SET_RSVD3_SHIFT)) & PXP_COMP_FORMAT0_SET_RSVD3_MASK)

#define PXP_COMP_FORMAT0_SET_FIELD_NUM_MASK      (0x30U)
#define PXP_COMP_FORMAT0_SET_FIELD_NUM_SHIFT     (4U)
/*! FIELD_NUM - FIELD_NUM */
#define PXP_COMP_FORMAT0_SET_FIELD_NUM(x)        (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_SET_FIELD_NUM_SHIFT)) & PXP_COMP_FORMAT0_SET_FIELD_NUM_MASK)

#define PXP_COMP_FORMAT0_SET_RSVD2_MASK          (0xC0U)
#define PXP_COMP_FORMAT0_SET_RSVD2_SHIFT         (6U)
/*! RSVD2 - RSVD2 */
#define PXP_COMP_FORMAT0_SET_RSVD2(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_SET_RSVD2_SHIFT)) & PXP_COMP_FORMAT0_SET_RSVD2_MASK)

#define PXP_COMP_FORMAT0_SET_MASK_INDEX_MASK     (0x300U)
#define PXP_COMP_FORMAT0_SET_MASK_INDEX_SHIFT    (8U)
/*! MASK_INDEX - MASK_INDEX */
#define PXP_COMP_FORMAT0_SET_MASK_INDEX(x)       (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_SET_MASK_INDEX_SHIFT)) & PXP_COMP_FORMAT0_SET_MASK_INDEX_MASK)

#define PXP_COMP_FORMAT0_SET_RSVD1_MASK          (0xFC00U)
#define PXP_COMP_FORMAT0_SET_RSVD1_SHIFT         (10U)
/*! RSVD1 - RSVD1 */
#define PXP_COMP_FORMAT0_SET_RSVD1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_SET_RSVD1_SHIFT)) & PXP_COMP_FORMAT0_SET_RSVD1_MASK)

#define PXP_COMP_FORMAT0_SET_PIXEL_PITCH_64B_MASK (0x3FF0000U)
#define PXP_COMP_FORMAT0_SET_PIXEL_PITCH_64B_SHIFT (16U)
/*! PIXEL_PITCH_64B - PIXEL_PITCH_64B */
#define PXP_COMP_FORMAT0_SET_PIXEL_PITCH_64B(x)  (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_SET_PIXEL_PITCH_64B_SHIFT)) & PXP_COMP_FORMAT0_SET_PIXEL_PITCH_64B_MASK)

#define PXP_COMP_FORMAT0_SET_ERR_PRONE_MASK      (0x4000000U)
#define PXP_COMP_FORMAT0_SET_ERR_PRONE_SHIFT     (26U)
/*! ERR_PRONE - ERR_PRONE */
#define PXP_COMP_FORMAT0_SET_ERR_PRONE(x)        (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_SET_ERR_PRONE_SHIFT)) & PXP_COMP_FORMAT0_SET_ERR_PRONE_MASK)

#define PXP_COMP_FORMAT0_SET_FIFOFULL_MASK       (0x8000000U)
#define PXP_COMP_FORMAT0_SET_FIFOFULL_SHIFT      (27U)
/*! FIFOFULL - FIFOFULL */
#define PXP_COMP_FORMAT0_SET_FIFOFULL(x)         (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_SET_FIFOFULL_SHIFT)) & PXP_COMP_FORMAT0_SET_FIFOFULL_MASK)

#define PXP_COMP_FORMAT0_SET_RSVD0_MASK          (0xF0000000U)
#define PXP_COMP_FORMAT0_SET_RSVD0_SHIFT         (28U)
/*! RSVD0 - RSVD0 */
#define PXP_COMP_FORMAT0_SET_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_SET_RSVD0_SHIFT)) & PXP_COMP_FORMAT0_SET_RSVD0_MASK)
/*! @} */

/*! @name COMP_FORMAT0_CLR -  */
/*! @{ */

#define PXP_COMP_FORMAT0_CLR_FLAG_32B_MASK       (0x1U)
#define PXP_COMP_FORMAT0_CLR_FLAG_32B_SHIFT      (0U)
/*! FLAG_32B - FLAG_32B */
#define PXP_COMP_FORMAT0_CLR_FLAG_32B(x)         (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_CLR_FLAG_32B_SHIFT)) & PXP_COMP_FORMAT0_CLR_FLAG_32B_MASK)

#define PXP_COMP_FORMAT0_CLR_DISABLE_VALID_FIX_MASK (0x2U)
#define PXP_COMP_FORMAT0_CLR_DISABLE_VALID_FIX_SHIFT (1U)
/*! DISABLE_VALID_FIX - DISABLE_VALID_FIX */
#define PXP_COMP_FORMAT0_CLR_DISABLE_VALID_FIX(x) (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_CLR_DISABLE_VALID_FIX_SHIFT)) & PXP_COMP_FORMAT0_CLR_DISABLE_VALID_FIX_MASK)

#define PXP_COMP_FORMAT0_CLR_RSVD3_MASK          (0xCU)
#define PXP_COMP_FORMAT0_CLR_RSVD3_SHIFT         (2U)
/*! RSVD3 - RSVD3 */
#define PXP_COMP_FORMAT0_CLR_RSVD3(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_CLR_RSVD3_SHIFT)) & PXP_COMP_FORMAT0_CLR_RSVD3_MASK)

#define PXP_COMP_FORMAT0_CLR_FIELD_NUM_MASK      (0x30U)
#define PXP_COMP_FORMAT0_CLR_FIELD_NUM_SHIFT     (4U)
/*! FIELD_NUM - FIELD_NUM */
#define PXP_COMP_FORMAT0_CLR_FIELD_NUM(x)        (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_CLR_FIELD_NUM_SHIFT)) & PXP_COMP_FORMAT0_CLR_FIELD_NUM_MASK)

#define PXP_COMP_FORMAT0_CLR_RSVD2_MASK          (0xC0U)
#define PXP_COMP_FORMAT0_CLR_RSVD2_SHIFT         (6U)
/*! RSVD2 - RSVD2 */
#define PXP_COMP_FORMAT0_CLR_RSVD2(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_CLR_RSVD2_SHIFT)) & PXP_COMP_FORMAT0_CLR_RSVD2_MASK)

#define PXP_COMP_FORMAT0_CLR_MASK_INDEX_MASK     (0x300U)
#define PXP_COMP_FORMAT0_CLR_MASK_INDEX_SHIFT    (8U)
/*! MASK_INDEX - MASK_INDEX */
#define PXP_COMP_FORMAT0_CLR_MASK_INDEX(x)       (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_CLR_MASK_INDEX_SHIFT)) & PXP_COMP_FORMAT0_CLR_MASK_INDEX_MASK)

#define PXP_COMP_FORMAT0_CLR_RSVD1_MASK          (0xFC00U)
#define PXP_COMP_FORMAT0_CLR_RSVD1_SHIFT         (10U)
/*! RSVD1 - RSVD1 */
#define PXP_COMP_FORMAT0_CLR_RSVD1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_CLR_RSVD1_SHIFT)) & PXP_COMP_FORMAT0_CLR_RSVD1_MASK)

#define PXP_COMP_FORMAT0_CLR_PIXEL_PITCH_64B_MASK (0x3FF0000U)
#define PXP_COMP_FORMAT0_CLR_PIXEL_PITCH_64B_SHIFT (16U)
/*! PIXEL_PITCH_64B - PIXEL_PITCH_64B */
#define PXP_COMP_FORMAT0_CLR_PIXEL_PITCH_64B(x)  (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_CLR_PIXEL_PITCH_64B_SHIFT)) & PXP_COMP_FORMAT0_CLR_PIXEL_PITCH_64B_MASK)

#define PXP_COMP_FORMAT0_CLR_ERR_PRONE_MASK      (0x4000000U)
#define PXP_COMP_FORMAT0_CLR_ERR_PRONE_SHIFT     (26U)
/*! ERR_PRONE - ERR_PRONE */
#define PXP_COMP_FORMAT0_CLR_ERR_PRONE(x)        (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_CLR_ERR_PRONE_SHIFT)) & PXP_COMP_FORMAT0_CLR_ERR_PRONE_MASK)

#define PXP_COMP_FORMAT0_CLR_FIFOFULL_MASK       (0x8000000U)
#define PXP_COMP_FORMAT0_CLR_FIFOFULL_SHIFT      (27U)
/*! FIFOFULL - FIFOFULL */
#define PXP_COMP_FORMAT0_CLR_FIFOFULL(x)         (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_CLR_FIFOFULL_SHIFT)) & PXP_COMP_FORMAT0_CLR_FIFOFULL_MASK)

#define PXP_COMP_FORMAT0_CLR_RSVD0_MASK          (0xF0000000U)
#define PXP_COMP_FORMAT0_CLR_RSVD0_SHIFT         (28U)
/*! RSVD0 - RSVD0 */
#define PXP_COMP_FORMAT0_CLR_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_CLR_RSVD0_SHIFT)) & PXP_COMP_FORMAT0_CLR_RSVD0_MASK)
/*! @} */

/*! @name COMP_FORMAT0_TOG -  */
/*! @{ */

#define PXP_COMP_FORMAT0_TOG_FLAG_32B_MASK       (0x1U)
#define PXP_COMP_FORMAT0_TOG_FLAG_32B_SHIFT      (0U)
/*! FLAG_32B - FLAG_32B */
#define PXP_COMP_FORMAT0_TOG_FLAG_32B(x)         (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_TOG_FLAG_32B_SHIFT)) & PXP_COMP_FORMAT0_TOG_FLAG_32B_MASK)

#define PXP_COMP_FORMAT0_TOG_DISABLE_VALID_FIX_MASK (0x2U)
#define PXP_COMP_FORMAT0_TOG_DISABLE_VALID_FIX_SHIFT (1U)
/*! DISABLE_VALID_FIX - DISABLE_VALID_FIX */
#define PXP_COMP_FORMAT0_TOG_DISABLE_VALID_FIX(x) (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_TOG_DISABLE_VALID_FIX_SHIFT)) & PXP_COMP_FORMAT0_TOG_DISABLE_VALID_FIX_MASK)

#define PXP_COMP_FORMAT0_TOG_RSVD3_MASK          (0xCU)
#define PXP_COMP_FORMAT0_TOG_RSVD3_SHIFT         (2U)
/*! RSVD3 - RSVD3 */
#define PXP_COMP_FORMAT0_TOG_RSVD3(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_TOG_RSVD3_SHIFT)) & PXP_COMP_FORMAT0_TOG_RSVD3_MASK)

#define PXP_COMP_FORMAT0_TOG_FIELD_NUM_MASK      (0x30U)
#define PXP_COMP_FORMAT0_TOG_FIELD_NUM_SHIFT     (4U)
/*! FIELD_NUM - FIELD_NUM */
#define PXP_COMP_FORMAT0_TOG_FIELD_NUM(x)        (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_TOG_FIELD_NUM_SHIFT)) & PXP_COMP_FORMAT0_TOG_FIELD_NUM_MASK)

#define PXP_COMP_FORMAT0_TOG_RSVD2_MASK          (0xC0U)
#define PXP_COMP_FORMAT0_TOG_RSVD2_SHIFT         (6U)
/*! RSVD2 - RSVD2 */
#define PXP_COMP_FORMAT0_TOG_RSVD2(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_TOG_RSVD2_SHIFT)) & PXP_COMP_FORMAT0_TOG_RSVD2_MASK)

#define PXP_COMP_FORMAT0_TOG_MASK_INDEX_MASK     (0x300U)
#define PXP_COMP_FORMAT0_TOG_MASK_INDEX_SHIFT    (8U)
/*! MASK_INDEX - MASK_INDEX */
#define PXP_COMP_FORMAT0_TOG_MASK_INDEX(x)       (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_TOG_MASK_INDEX_SHIFT)) & PXP_COMP_FORMAT0_TOG_MASK_INDEX_MASK)

#define PXP_COMP_FORMAT0_TOG_RSVD1_MASK          (0xFC00U)
#define PXP_COMP_FORMAT0_TOG_RSVD1_SHIFT         (10U)
/*! RSVD1 - RSVD1 */
#define PXP_COMP_FORMAT0_TOG_RSVD1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_TOG_RSVD1_SHIFT)) & PXP_COMP_FORMAT0_TOG_RSVD1_MASK)

#define PXP_COMP_FORMAT0_TOG_PIXEL_PITCH_64B_MASK (0x3FF0000U)
#define PXP_COMP_FORMAT0_TOG_PIXEL_PITCH_64B_SHIFT (16U)
/*! PIXEL_PITCH_64B - PIXEL_PITCH_64B */
#define PXP_COMP_FORMAT0_TOG_PIXEL_PITCH_64B(x)  (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_TOG_PIXEL_PITCH_64B_SHIFT)) & PXP_COMP_FORMAT0_TOG_PIXEL_PITCH_64B_MASK)

#define PXP_COMP_FORMAT0_TOG_ERR_PRONE_MASK      (0x4000000U)
#define PXP_COMP_FORMAT0_TOG_ERR_PRONE_SHIFT     (26U)
/*! ERR_PRONE - ERR_PRONE */
#define PXP_COMP_FORMAT0_TOG_ERR_PRONE(x)        (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_TOG_ERR_PRONE_SHIFT)) & PXP_COMP_FORMAT0_TOG_ERR_PRONE_MASK)

#define PXP_COMP_FORMAT0_TOG_FIFOFULL_MASK       (0x8000000U)
#define PXP_COMP_FORMAT0_TOG_FIFOFULL_SHIFT      (27U)
/*! FIFOFULL - FIFOFULL */
#define PXP_COMP_FORMAT0_TOG_FIFOFULL(x)         (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_TOG_FIFOFULL_SHIFT)) & PXP_COMP_FORMAT0_TOG_FIFOFULL_MASK)

#define PXP_COMP_FORMAT0_TOG_RSVD0_MASK          (0xF0000000U)
#define PXP_COMP_FORMAT0_TOG_RSVD0_SHIFT         (28U)
/*! RSVD0 - RSVD0 */
#define PXP_COMP_FORMAT0_TOG_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT0_TOG_RSVD0_SHIFT)) & PXP_COMP_FORMAT0_TOG_RSVD0_MASK)
/*! @} */

/*! @name COMP_FORMAT1 -  */
/*! @{ */

#define PXP_COMP_FORMAT1_A_OFFSET_MASK           (0x1FU)
#define PXP_COMP_FORMAT1_A_OFFSET_SHIFT          (0U)
/*! A_OFFSET - A_OFFSET */
#define PXP_COMP_FORMAT1_A_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT1_A_OFFSET_SHIFT)) & PXP_COMP_FORMAT1_A_OFFSET_MASK)

#define PXP_COMP_FORMAT1_A_LEN_MASK              (0xE0U)
#define PXP_COMP_FORMAT1_A_LEN_SHIFT             (5U)
/*! A_LEN - A_LEN */
#define PXP_COMP_FORMAT1_A_LEN(x)                (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT1_A_LEN_SHIFT)) & PXP_COMP_FORMAT1_A_LEN_MASK)

#define PXP_COMP_FORMAT1_B_OFFSET_MASK           (0x1F00U)
#define PXP_COMP_FORMAT1_B_OFFSET_SHIFT          (8U)
/*! B_OFFSET - B_OFFSET */
#define PXP_COMP_FORMAT1_B_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT1_B_OFFSET_SHIFT)) & PXP_COMP_FORMAT1_B_OFFSET_MASK)

#define PXP_COMP_FORMAT1_B_LEN_MASK              (0xE000U)
#define PXP_COMP_FORMAT1_B_LEN_SHIFT             (13U)
/*! B_LEN - B_LEN */
#define PXP_COMP_FORMAT1_B_LEN(x)                (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT1_B_LEN_SHIFT)) & PXP_COMP_FORMAT1_B_LEN_MASK)

#define PXP_COMP_FORMAT1_C_OFFSET_MASK           (0x1F0000U)
#define PXP_COMP_FORMAT1_C_OFFSET_SHIFT          (16U)
/*! C_OFFSET - C_OFFSET */
#define PXP_COMP_FORMAT1_C_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT1_C_OFFSET_SHIFT)) & PXP_COMP_FORMAT1_C_OFFSET_MASK)

#define PXP_COMP_FORMAT1_C_LEN_MASK              (0xE00000U)
#define PXP_COMP_FORMAT1_C_LEN_SHIFT             (21U)
/*! C_LEN - C_LEN */
#define PXP_COMP_FORMAT1_C_LEN(x)                (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT1_C_LEN_SHIFT)) & PXP_COMP_FORMAT1_C_LEN_MASK)

#define PXP_COMP_FORMAT1_D_OFFSET_MASK           (0x1F000000U)
#define PXP_COMP_FORMAT1_D_OFFSET_SHIFT          (24U)
/*! D_OFFSET - D_OFFSET */
#define PXP_COMP_FORMAT1_D_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT1_D_OFFSET_SHIFT)) & PXP_COMP_FORMAT1_D_OFFSET_MASK)

#define PXP_COMP_FORMAT1_D_LEN_MASK              (0xE0000000U)
#define PXP_COMP_FORMAT1_D_LEN_SHIFT             (29U)
/*! D_LEN - D_LEN */
#define PXP_COMP_FORMAT1_D_LEN(x)                (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT1_D_LEN_SHIFT)) & PXP_COMP_FORMAT1_D_LEN_MASK)
/*! @} */

/*! @name COMP_FORMAT2 -  */
/*! @{ */

#define PXP_COMP_FORMAT2_A_RUNLEN_MASK           (0xFU)
#define PXP_COMP_FORMAT2_A_RUNLEN_SHIFT          (0U)
/*! A_RUNLEN - A_RUNLEN */
#define PXP_COMP_FORMAT2_A_RUNLEN(x)             (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT2_A_RUNLEN_SHIFT)) & PXP_COMP_FORMAT2_A_RUNLEN_MASK)

#define PXP_COMP_FORMAT2_B_RUNLEN_MASK           (0xF0U)
#define PXP_COMP_FORMAT2_B_RUNLEN_SHIFT          (4U)
/*! B_RUNLEN - B_RUNLEN */
#define PXP_COMP_FORMAT2_B_RUNLEN(x)             (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT2_B_RUNLEN_SHIFT)) & PXP_COMP_FORMAT2_B_RUNLEN_MASK)

#define PXP_COMP_FORMAT2_C_RUNLEN_MASK           (0xF00U)
#define PXP_COMP_FORMAT2_C_RUNLEN_SHIFT          (8U)
/*! C_RUNLEN - C_RUNLEN */
#define PXP_COMP_FORMAT2_C_RUNLEN(x)             (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT2_C_RUNLEN_SHIFT)) & PXP_COMP_FORMAT2_C_RUNLEN_MASK)

#define PXP_COMP_FORMAT2_D_RUNLEN_MASK           (0xF000U)
#define PXP_COMP_FORMAT2_D_RUNLEN_SHIFT          (12U)
/*! D_RUNLEN - D_RUNLEN */
#define PXP_COMP_FORMAT2_D_RUNLEN(x)             (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT2_D_RUNLEN_SHIFT)) & PXP_COMP_FORMAT2_D_RUNLEN_MASK)

#define PXP_COMP_FORMAT2_RSVD_MASK               (0xFFFF0000U)
#define PXP_COMP_FORMAT2_RSVD_SHIFT              (16U)
/*! RSVD - RSVD */
#define PXP_COMP_FORMAT2_RSVD(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_COMP_FORMAT2_RSVD_SHIFT)) & PXP_COMP_FORMAT2_RSVD_MASK)
/*! @} */

/*! @name COMP_MASK0 -  */
/*! @{ */

#define PXP_COMP_MASK0_VLD_MASK_LOW_MASK         (0xFFFFFFFFU)
#define PXP_COMP_MASK0_VLD_MASK_LOW_SHIFT        (0U)
/*! VLD_MASK_LOW - VLD_MASK_LOW */
#define PXP_COMP_MASK0_VLD_MASK_LOW(x)           (((uint32_t)(((uint32_t)(x)) << PXP_COMP_MASK0_VLD_MASK_LOW_SHIFT)) & PXP_COMP_MASK0_VLD_MASK_LOW_MASK)
/*! @} */

/*! @name COMP_MASK1 -  */
/*! @{ */

#define PXP_COMP_MASK1_VLD_MASK_HIGH_MASK        (0xFFFFFFFFU)
#define PXP_COMP_MASK1_VLD_MASK_HIGH_SHIFT       (0U)
/*! VLD_MASK_HIGH - VLD_MASK_HIGH */
#define PXP_COMP_MASK1_VLD_MASK_HIGH(x)          (((uint32_t)(((uint32_t)(x)) << PXP_COMP_MASK1_VLD_MASK_HIGH_SHIFT)) & PXP_COMP_MASK1_VLD_MASK_HIGH_MASK)
/*! @} */

/*! @name COMP_BUFFER_SIZE -  */
/*! @{ */

#define PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH_MASK   (0x1FFFU)
#define PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH_SHIFT  (0U)
/*! PIXEL_LENGTH - PIXEL_LENGTH */
#define PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH(x)     (((uint32_t)(((uint32_t)(x)) << PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH_SHIFT)) & PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH_MASK)

#define PXP_COMP_BUFFER_SIZE_RSVD1_MASK          (0xE000U)
#define PXP_COMP_BUFFER_SIZE_RSVD1_SHIFT         (13U)
/*! RSVD1 - RSVD1 */
#define PXP_COMP_BUFFER_SIZE_RSVD1(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_BUFFER_SIZE_RSVD1_SHIFT)) & PXP_COMP_BUFFER_SIZE_RSVD1_MASK)

#define PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH_MASK    (0x1FFF0000U)
#define PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH_SHIFT   (16U)
/*! PIXEL_WIDTH - PIXEL_WIDTH */
#define PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH_SHIFT)) & PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH_MASK)

#define PXP_COMP_BUFFER_SIZE_RSVD0_MASK          (0xE0000000U)
#define PXP_COMP_BUFFER_SIZE_RSVD0_SHIFT         (29U)
/*! RSVD0 - RSVD0 */
#define PXP_COMP_BUFFER_SIZE_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_BUFFER_SIZE_RSVD0_SHIFT)) & PXP_COMP_BUFFER_SIZE_RSVD0_MASK)
/*! @} */

/*! @name COMP_SOURCE -  */
/*! @{ */

#define PXP_COMP_SOURCE_SOURCE_ADDR_MASK         (0xFFFFFFFFU)
#define PXP_COMP_SOURCE_SOURCE_ADDR_SHIFT        (0U)
/*! SOURCE_ADDR - SOURCE_ADDR */
#define PXP_COMP_SOURCE_SOURCE_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_COMP_SOURCE_SOURCE_ADDR_SHIFT)) & PXP_COMP_SOURCE_SOURCE_ADDR_MASK)
/*! @} */

/*! @name COMP_TARGET -  */
/*! @{ */

#define PXP_COMP_TARGET_TARGET_ADDR_MASK         (0xFFFFFFFFU)
#define PXP_COMP_TARGET_TARGET_ADDR_SHIFT        (0U)
/*! TARGET_ADDR - TARGET_ADDR */
#define PXP_COMP_TARGET_TARGET_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_COMP_TARGET_TARGET_ADDR_SHIFT)) & PXP_COMP_TARGET_TARGET_ADDR_MASK)
/*! @} */

/*! @name COMP_BUFFER_A -  */
/*! @{ */

#define PXP_COMP_BUFFER_A_A_SRAM_ADDR_MASK       (0xFFFFFFFFU)
#define PXP_COMP_BUFFER_A_A_SRAM_ADDR_SHIFT      (0U)
/*! A_SRAM_ADDR - A_SRAM_ADDR */
#define PXP_COMP_BUFFER_A_A_SRAM_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << PXP_COMP_BUFFER_A_A_SRAM_ADDR_SHIFT)) & PXP_COMP_BUFFER_A_A_SRAM_ADDR_MASK)
/*! @} */

/*! @name COMP_BUFFER_B -  */
/*! @{ */

#define PXP_COMP_BUFFER_B_B_SRAM_ADDR_MASK       (0xFFFFFFFFU)
#define PXP_COMP_BUFFER_B_B_SRAM_ADDR_SHIFT      (0U)
/*! B_SRAM_ADDR - B_SRAM_ADDR */
#define PXP_COMP_BUFFER_B_B_SRAM_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << PXP_COMP_BUFFER_B_B_SRAM_ADDR_SHIFT)) & PXP_COMP_BUFFER_B_B_SRAM_ADDR_MASK)
/*! @} */

/*! @name COMP_BUFFER_C -  */
/*! @{ */

#define PXP_COMP_BUFFER_C_C_SRAM_ADDR_MASK       (0xFFFFFFFFU)
#define PXP_COMP_BUFFER_C_C_SRAM_ADDR_SHIFT      (0U)
/*! C_SRAM_ADDR - C_SRAM_ADDR */
#define PXP_COMP_BUFFER_C_C_SRAM_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << PXP_COMP_BUFFER_C_C_SRAM_ADDR_SHIFT)) & PXP_COMP_BUFFER_C_C_SRAM_ADDR_MASK)
/*! @} */

/*! @name COMP_BUFFER_D -  */
/*! @{ */

#define PXP_COMP_BUFFER_D_D_SRAM_ADDR_MASK       (0xFFFFFFFFU)
#define PXP_COMP_BUFFER_D_D_SRAM_ADDR_SHIFT      (0U)
/*! D_SRAM_ADDR - D_SRAM_ADDR */
#define PXP_COMP_BUFFER_D_D_SRAM_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << PXP_COMP_BUFFER_D_D_SRAM_ADDR_SHIFT)) & PXP_COMP_BUFFER_D_D_SRAM_ADDR_MASK)
/*! @} */

/*! @name COMP_DEBUG -  */
/*! @{ */

#define PXP_COMP_DEBUG_DEBUG_SEL_MASK            (0xFFU)
#define PXP_COMP_DEBUG_DEBUG_SEL_SHIFT           (0U)
/*! DEBUG_SEL - DEBUG_SEL */
#define PXP_COMP_DEBUG_DEBUG_SEL(x)              (((uint32_t)(((uint32_t)(x)) << PXP_COMP_DEBUG_DEBUG_SEL_SHIFT)) & PXP_COMP_DEBUG_DEBUG_SEL_MASK)

#define PXP_COMP_DEBUG_DEBUG_VALUE_MASK          (0xFFFFFF00U)
#define PXP_COMP_DEBUG_DEBUG_VALUE_SHIFT         (8U)
/*! DEBUG_VALUE - DEBUG_VALUE */
#define PXP_COMP_DEBUG_DEBUG_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << PXP_COMP_DEBUG_DEBUG_VALUE_SHIFT)) & PXP_COMP_DEBUG_DEBUG_VALUE_MASK)
/*! @} */

/*! @name BUS_MUX -  */
/*! @{ */

#define PXP_BUS_MUX_RD_SEL_MASK                  (0xFFU)
#define PXP_BUS_MUX_RD_SEL_SHIFT                 (0U)
/*! RD_SEL - RD_SEL */
#define PXP_BUS_MUX_RD_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_BUS_MUX_RD_SEL_SHIFT)) & PXP_BUS_MUX_RD_SEL_MASK)

#define PXP_BUS_MUX_RSVD0_MASK                   (0xFF00U)
#define PXP_BUS_MUX_RSVD0_SHIFT                  (8U)
/*! RSVD0 - RSVD0 */
#define PXP_BUS_MUX_RSVD0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_BUS_MUX_RSVD0_SHIFT)) & PXP_BUS_MUX_RSVD0_MASK)

#define PXP_BUS_MUX_WR_SEL_MASK                  (0xFF0000U)
#define PXP_BUS_MUX_WR_SEL_SHIFT                 (16U)
/*! WR_SEL - WR_SEL */
#define PXP_BUS_MUX_WR_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_BUS_MUX_WR_SEL_SHIFT)) & PXP_BUS_MUX_WR_SEL_MASK)

#define PXP_BUS_MUX_RSVD1_MASK                   (0xFF000000U)
#define PXP_BUS_MUX_RSVD1_SHIFT                  (24U)
/*! RSVD1 - RSVD1 */
#define PXP_BUS_MUX_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_BUS_MUX_RSVD1_SHIFT)) & PXP_BUS_MUX_RSVD1_MASK)
/*! @} */

/*! @name HANDSHAKE_READY_MUX0 -  */
/*! @{ */

#define PXP_HANDSHAKE_READY_MUX0_HSK0_MASK       (0xFU)
#define PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT      (0U)
/*! HSK0 - HSK0 */
#define PXP_HANDSHAKE_READY_MUX0_HSK0(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK0_MASK)

#define PXP_HANDSHAKE_READY_MUX0_HSK1_MASK       (0xF0U)
#define PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT      (4U)
/*! HSK1 - HSK1 */
#define PXP_HANDSHAKE_READY_MUX0_HSK1(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK1_MASK)

#define PXP_HANDSHAKE_READY_MUX0_HSK2_MASK       (0xF00U)
#define PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT      (8U)
/*! HSK2 - HSK2 */
#define PXP_HANDSHAKE_READY_MUX0_HSK2(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK2_MASK)

#define PXP_HANDSHAKE_READY_MUX0_HSK3_MASK       (0xF000U)
#define PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT      (12U)
/*! HSK3 - HSK3 */
#define PXP_HANDSHAKE_READY_MUX0_HSK3(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK3_MASK)

#define PXP_HANDSHAKE_READY_MUX0_HSK4_MASK       (0xF0000U)
#define PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT      (16U)
/*! HSK4 - HSK4 */
#define PXP_HANDSHAKE_READY_MUX0_HSK4(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK4_MASK)

#define PXP_HANDSHAKE_READY_MUX0_HSK5_MASK       (0xF00000U)
#define PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT      (20U)
/*! HSK5 - HSK5 */
#define PXP_HANDSHAKE_READY_MUX0_HSK5(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK5_MASK)

#define PXP_HANDSHAKE_READY_MUX0_HSK6_MASK       (0xF000000U)
#define PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT      (24U)
/*! HSK6 - HSK6 */
#define PXP_HANDSHAKE_READY_MUX0_HSK6(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK6_MASK)

#define PXP_HANDSHAKE_READY_MUX0_HSK7_MASK       (0xF0000000U)
#define PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT      (28U)
/*! HSK7 - HSK7 */
#define PXP_HANDSHAKE_READY_MUX0_HSK7(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK7_MASK)
/*! @} */

/*! @name HANDSHAKE_READY_MUX1 -  */
/*! @{ */

#define PXP_HANDSHAKE_READY_MUX1_HSK8_MASK       (0xFU)
#define PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT      (0U)
/*! HSK8 - HSK8 */
#define PXP_HANDSHAKE_READY_MUX1_HSK8(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK8_MASK)

#define PXP_HANDSHAKE_READY_MUX1_HSK9_MASK       (0xF0U)
#define PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT      (4U)
/*! HSK9 - HSK9 */
#define PXP_HANDSHAKE_READY_MUX1_HSK9(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK9_MASK)

#define PXP_HANDSHAKE_READY_MUX1_HSK10_MASK      (0xF00U)
#define PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT     (8U)
/*! HSK10 - HSK10 */
#define PXP_HANDSHAKE_READY_MUX1_HSK10(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK10_MASK)

#define PXP_HANDSHAKE_READY_MUX1_HSK11_MASK      (0xF000U)
#define PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT     (12U)
/*! HSK11 - HSK11 */
#define PXP_HANDSHAKE_READY_MUX1_HSK11(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK11_MASK)

#define PXP_HANDSHAKE_READY_MUX1_HSK12_MASK      (0xF0000U)
#define PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT     (16U)
/*! HSK12 - HSK12 */
#define PXP_HANDSHAKE_READY_MUX1_HSK12(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK12_MASK)

#define PXP_HANDSHAKE_READY_MUX1_HSK13_MASK      (0xF00000U)
#define PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT     (20U)
/*! HSK13 - HSK13 */
#define PXP_HANDSHAKE_READY_MUX1_HSK13(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK13_MASK)

#define PXP_HANDSHAKE_READY_MUX1_HSK14_MASK      (0xF000000U)
#define PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT     (24U)
/*! HSK14 - HSK14 */
#define PXP_HANDSHAKE_READY_MUX1_HSK14(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK14_MASK)

#define PXP_HANDSHAKE_READY_MUX1_HSK15_MASK      (0xF0000000U)
#define PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT     (28U)
/*! HSK15 - HSK15 */
#define PXP_HANDSHAKE_READY_MUX1_HSK15(x)        (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK15_MASK)
/*! @} */

/*! @name HANDSHAKE_DONE_MUX0 -  */
/*! @{ */

#define PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK        (0xFU)
#define PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT       (0U)
/*! HSK0 - HSK0 */
#define PXP_HANDSHAKE_DONE_MUX0_HSK0(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK)

#define PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK        (0xF0U)
#define PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT       (4U)
/*! HSK1 - HSK1 */
#define PXP_HANDSHAKE_DONE_MUX0_HSK1(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK)

#define PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK        (0xF00U)
#define PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT       (8U)
/*! HSK2 - HSK2 */
#define PXP_HANDSHAKE_DONE_MUX0_HSK2(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK)

#define PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK        (0xF000U)
#define PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT       (12U)
/*! HSK3 - HSK3 */
#define PXP_HANDSHAKE_DONE_MUX0_HSK3(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK)

#define PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK        (0xF0000U)
#define PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT       (16U)
/*! HSK4 - HSK4 */
#define PXP_HANDSHAKE_DONE_MUX0_HSK4(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK)

#define PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK        (0xF00000U)
#define PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT       (20U)
/*! HSK5 - HSK5 */
#define PXP_HANDSHAKE_DONE_MUX0_HSK5(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK)

#define PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK        (0xF000000U)
#define PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT       (24U)
/*! HSK6 - HSK6 */
#define PXP_HANDSHAKE_DONE_MUX0_HSK6(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK)

#define PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK        (0xF0000000U)
#define PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT       (28U)
/*! HSK7 - HSK7 */
#define PXP_HANDSHAKE_DONE_MUX0_HSK7(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK)
/*! @} */

/*! @name HANDSHAKE_DONE_MUX1 -  */
/*! @{ */

#define PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK        (0xFU)
#define PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT       (0U)
/*! HSK8 - HSK8 */
#define PXP_HANDSHAKE_DONE_MUX1_HSK8(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK)

#define PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK        (0xF0U)
#define PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT       (4U)
/*! HSK9 - HSK9 */
#define PXP_HANDSHAKE_DONE_MUX1_HSK9(x)          (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK)

#define PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK       (0xF00U)
#define PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT      (8U)
/*! HSK10 - HSK10 */
#define PXP_HANDSHAKE_DONE_MUX1_HSK10(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK)

#define PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK       (0xF000U)
#define PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT      (12U)
/*! HSK11 - HSK11 */
#define PXP_HANDSHAKE_DONE_MUX1_HSK11(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK)

#define PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK       (0xF0000U)
#define PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT      (16U)
/*! HSK12 - HSK12 */
#define PXP_HANDSHAKE_DONE_MUX1_HSK12(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK)

#define PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK       (0xF00000U)
#define PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT      (20U)
/*! HSK13 - HSK13 */
#define PXP_HANDSHAKE_DONE_MUX1_HSK13(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK)

#define PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK       (0xF000000U)
#define PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT      (24U)
/*! HSK14 - HSK14 */
#define PXP_HANDSHAKE_DONE_MUX1_HSK14(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK)

#define PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK       (0xF0000000U)
#define PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT      (28U)
/*! HSK15 - HSK15 */
#define PXP_HANDSHAKE_DONE_MUX1_HSK15(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK)
/*! @} */

/*! @name HANDSHAKE_CPU_FETCH -  */
/*! @{ */

#define PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY_MASK (0x1U)
#define PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY_SHIFT (0U)
/*! SW0_B0_READY - SW0_B0_READY */
#define PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY(x)  (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY_MASK (0x2U)
#define PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY_SHIFT (1U)
/*! SW0_B1_READY - SW0_B1_READY */
#define PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY(x)  (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE_MASK (0x4U)
#define PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE_SHIFT (2U)
/*! SW0_B0_DONE - SW0_B0_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE_MASK (0x8U)
#define PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE_SHIFT (3U)
/*! SW0_B1_DONE - SW0_B1_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES_MASK (0x30U)
#define PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES_SHIFT (4U)
/*! SW0_BUF_LINES - SW0_BUF_LINES
 *  0b00..LINE_4 : Buffer lines is 4 lines.
 *  0b01..LINE_8 : Buffer lines is 8 lines.
 *  0b10..LINE_16 : Buffer lines is 16 lines.
 */
#define PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_RSVD0_MASK       (0x7FC0U)
#define PXP_HANDSHAKE_CPU_FETCH_RSVD0_SHIFT      (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HANDSHAKE_CPU_FETCH_RSVD0(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_RSVD0_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_RSVD0_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN_MASK  (0x8000U)
#define PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN_SHIFT (15U)
/*! SW0_HSK_EN - SW0_HSK_EN */
#define PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY_MASK (0x10000U)
#define PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY_SHIFT (16U)
/*! SW1_B0_READY - SW1_B0_READY */
#define PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY(x)  (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY_MASK (0x20000U)
#define PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY_SHIFT (17U)
/*! SW1_B1_READY - SW1_B1_READY */
#define PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY(x)  (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE_MASK (0x40000U)
#define PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE_SHIFT (18U)
/*! SW1_B0_DONE - SW1_B0_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE_MASK (0x80000U)
#define PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE_SHIFT (19U)
/*! SW1_B1_DONE - SW1_B1_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES_MASK (0x300000U)
#define PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES_SHIFT (20U)
/*! SW1_BUF_LINES - SW1_BUF_LINES
 *  0b00..LINE_4 : Buffer lines is 4 lines.
 *  0b01..LINE_8 : Buffer lines is 8 lines.
 *  0b10..LINE_16 : Buffer lines is 16 lines.
 */
#define PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_RSVD1_MASK       (0x7FC00000U)
#define PXP_HANDSHAKE_CPU_FETCH_RSVD1_SHIFT      (22U)
/*! RSVD1 - RSVD1 */
#define PXP_HANDSHAKE_CPU_FETCH_RSVD1(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_RSVD1_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_RSVD1_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN_MASK  (0x80000000U)
#define PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN_SHIFT (31U)
/*! SW1_HSK_EN - SW1_HSK_EN */
#define PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN_MASK)
/*! @} */

/*! @name HANDSHAKE_CPU_FETCH_SET -  */
/*! @{ */

#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B0_READY_MASK (0x1U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B0_READY_SHIFT (0U)
/*! SW0_B0_READY - SW0_B0_READY */
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B0_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B1_READY_MASK (0x2U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B1_READY_SHIFT (1U)
/*! SW0_B1_READY - SW0_B1_READY */
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B1_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B0_DONE_MASK (0x4U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B0_DONE_SHIFT (2U)
/*! SW0_B0_DONE - SW0_B0_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B0_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B1_DONE_MASK (0x8U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B1_DONE_SHIFT (3U)
/*! SW0_B1_DONE - SW0_B1_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B1_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_SW0_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_BUF_LINES_MASK (0x30U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_BUF_LINES_SHIFT (4U)
/*! SW0_BUF_LINES - SW0_BUF_LINES */
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_SW0_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_SW0_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SET_RSVD0_MASK   (0x7FC0U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_RSVD0_SHIFT  (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HANDSHAKE_CPU_FETCH_SET_RSVD0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_RSVD0_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_RSVD0_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_HSK_EN_MASK (0x8000U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_HSK_EN_SHIFT (15U)
/*! SW0_HSK_EN - SW0_HSK_EN */
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW0_HSK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_SW0_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_SW0_HSK_EN_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B0_READY_MASK (0x10000U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B0_READY_SHIFT (16U)
/*! SW1_B0_READY - SW1_B0_READY */
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B0_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B1_READY_MASK (0x20000U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B1_READY_SHIFT (17U)
/*! SW1_B1_READY - SW1_B1_READY */
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B1_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B0_DONE_MASK (0x40000U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B0_DONE_SHIFT (18U)
/*! SW1_B0_DONE - SW1_B0_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B0_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B1_DONE_MASK (0x80000U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B1_DONE_SHIFT (19U)
/*! SW1_B1_DONE - SW1_B1_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B1_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_SW1_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_BUF_LINES_MASK (0x300000U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_BUF_LINES_SHIFT (20U)
/*! SW1_BUF_LINES - SW1_BUF_LINES */
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_SW1_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_SW1_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SET_RSVD1_MASK   (0x7FC00000U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_RSVD1_SHIFT  (22U)
/*! RSVD1 - RSVD1 */
#define PXP_HANDSHAKE_CPU_FETCH_SET_RSVD1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_RSVD1_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_RSVD1_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_HSK_EN_MASK (0x80000000U)
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_HSK_EN_SHIFT (31U)
/*! SW1_HSK_EN - SW1_HSK_EN */
#define PXP_HANDSHAKE_CPU_FETCH_SET_SW1_HSK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_SET_SW1_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_SET_SW1_HSK_EN_MASK)
/*! @} */

/*! @name HANDSHAKE_CPU_FETCH_CLR -  */
/*! @{ */

#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B0_READY_MASK (0x1U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B0_READY_SHIFT (0U)
/*! SW0_B0_READY - SW0_B0_READY */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B0_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B1_READY_MASK (0x2U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B1_READY_SHIFT (1U)
/*! SW0_B1_READY - SW0_B1_READY */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B1_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B0_DONE_MASK (0x4U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B0_DONE_SHIFT (2U)
/*! SW0_B0_DONE - SW0_B0_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B0_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B1_DONE_MASK (0x8U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B1_DONE_SHIFT (3U)
/*! SW0_B1_DONE - SW0_B1_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B1_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_BUF_LINES_MASK (0x30U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_BUF_LINES_SHIFT (4U)
/*! SW0_BUF_LINES - SW0_BUF_LINES */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_CLR_RSVD0_MASK   (0x7FC0U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_RSVD0_SHIFT  (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_RSVD0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_RSVD0_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_RSVD0_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_HSK_EN_MASK (0x8000U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_HSK_EN_SHIFT (15U)
/*! SW0_HSK_EN - SW0_HSK_EN */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_HSK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_SW0_HSK_EN_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B0_READY_MASK (0x10000U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B0_READY_SHIFT (16U)
/*! SW1_B0_READY - SW1_B0_READY */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B0_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B1_READY_MASK (0x20000U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B1_READY_SHIFT (17U)
/*! SW1_B1_READY - SW1_B1_READY */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B1_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B0_DONE_MASK (0x40000U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B0_DONE_SHIFT (18U)
/*! SW1_B0_DONE - SW1_B0_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B0_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B1_DONE_MASK (0x80000U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B1_DONE_SHIFT (19U)
/*! SW1_B1_DONE - SW1_B1_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B1_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_BUF_LINES_MASK (0x300000U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_BUF_LINES_SHIFT (20U)
/*! SW1_BUF_LINES - SW1_BUF_LINES */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_CLR_RSVD1_MASK   (0x7FC00000U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_RSVD1_SHIFT  (22U)
/*! RSVD1 - RSVD1 */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_RSVD1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_RSVD1_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_RSVD1_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_HSK_EN_MASK (0x80000000U)
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_HSK_EN_SHIFT (31U)
/*! SW1_HSK_EN - SW1_HSK_EN */
#define PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_HSK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_CLR_SW1_HSK_EN_MASK)
/*! @} */

/*! @name HANDSHAKE_CPU_FETCH_TOG -  */
/*! @{ */

#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B0_READY_MASK (0x1U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B0_READY_SHIFT (0U)
/*! SW0_B0_READY - SW0_B0_READY */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B0_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B1_READY_MASK (0x2U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B1_READY_SHIFT (1U)
/*! SW0_B1_READY - SW0_B1_READY */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B1_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B0_DONE_MASK (0x4U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B0_DONE_SHIFT (2U)
/*! SW0_B0_DONE - SW0_B0_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B0_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B1_DONE_MASK (0x8U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B1_DONE_SHIFT (3U)
/*! SW0_B1_DONE - SW0_B1_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B1_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_BUF_LINES_MASK (0x30U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_BUF_LINES_SHIFT (4U)
/*! SW0_BUF_LINES - SW0_BUF_LINES */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_TOG_RSVD0_MASK   (0x7FC0U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_RSVD0_SHIFT  (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_RSVD0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_RSVD0_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_RSVD0_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_HSK_EN_MASK (0x8000U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_HSK_EN_SHIFT (15U)
/*! SW0_HSK_EN - SW0_HSK_EN */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_HSK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_SW0_HSK_EN_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B0_READY_MASK (0x10000U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B0_READY_SHIFT (16U)
/*! SW1_B0_READY - SW1_B0_READY */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B0_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B1_READY_MASK (0x20000U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B1_READY_SHIFT (17U)
/*! SW1_B1_READY - SW1_B1_READY */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B1_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B0_DONE_MASK (0x40000U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B0_DONE_SHIFT (18U)
/*! SW1_B0_DONE - SW1_B0_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B0_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B1_DONE_MASK (0x80000U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B1_DONE_SHIFT (19U)
/*! SW1_B1_DONE - SW1_B1_DONE */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B1_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_BUF_LINES_MASK (0x300000U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_BUF_LINES_SHIFT (20U)
/*! SW1_BUF_LINES - SW1_BUF_LINES */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_TOG_RSVD1_MASK   (0x7FC00000U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_RSVD1_SHIFT  (22U)
/*! RSVD1 - RSVD1 */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_RSVD1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_RSVD1_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_RSVD1_MASK)

#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_HSK_EN_MASK (0x80000000U)
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_HSK_EN_SHIFT (31U)
/*! SW1_HSK_EN - SW1_HSK_EN */
#define PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_HSK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_FETCH_TOG_SW1_HSK_EN_MASK)
/*! @} */

/*! @name HANDSHAKE_CPU_STORE -  */
/*! @{ */

#define PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY_MASK (0x1U)
#define PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY_SHIFT (0U)
/*! SW0_B0_READY - SW0_B0_READY */
#define PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY(x)  (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY_MASK (0x2U)
#define PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY_SHIFT (1U)
/*! SW0_B1_READY - SW0_B1_READY */
#define PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY(x)  (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE_MASK (0x4U)
#define PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE_SHIFT (2U)
/*! SW0_B0_DONE - SW0_B0_DONE */
#define PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE_MASK (0x8U)
#define PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE_SHIFT (3U)
/*! SW0_B1_DONE - SW0_B1_DONE */
#define PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES_MASK (0x30U)
#define PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES_SHIFT (4U)
/*! SW0_BUF_LINES - SW0_BUF_LINES
 *  0b00..LINE_4 : Buffer lines is 4 lines.
 *  0b01..LINE_8 : Buffer lines is 8 lines.
 *  0b10..LINE_16 : Buffer lines is 16 lines.
 */
#define PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_STORE_RSVD0_MASK       (0x7FC0U)
#define PXP_HANDSHAKE_CPU_STORE_RSVD0_SHIFT      (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HANDSHAKE_CPU_STORE_RSVD0(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_RSVD0_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_RSVD0_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN_MASK  (0x8000U)
#define PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN_SHIFT (15U)
/*! SW0_HSK_EN - SW0_HSK_EN */
#define PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY_MASK (0x10000U)
#define PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY_SHIFT (16U)
/*! SW1_B0_READY - SW1_B0_READY */
#define PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY(x)  (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY_MASK (0x20000U)
#define PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY_SHIFT (17U)
/*! SW1_B1_READY - SW1_B1_READY */
#define PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY(x)  (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE_MASK (0x40000U)
#define PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE_SHIFT (18U)
/*! SW1_B0_DONE - SW1_B0_DONE */
#define PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE_MASK (0x80000U)
#define PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE_SHIFT (19U)
/*! SW1_B1_DONE - SW1_B1_DONE */
#define PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE(x)   (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES_MASK (0x300000U)
#define PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES_SHIFT (20U)
/*! SW1_BUF_LINES - SW1_BUF_LINES
 *  0b00..LINE_4 : Buffer lines is 4 lines.
 *  0b01..LINE_8 : Buffer lines is 8 lines.
 *  0b10..LINE_16 : Buffer lines is 16 lines.
 */
#define PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_STORE_RSVD1_MASK       (0x7FC00000U)
#define PXP_HANDSHAKE_CPU_STORE_RSVD1_SHIFT      (22U)
/*! RSVD1 - RSVD1 */
#define PXP_HANDSHAKE_CPU_STORE_RSVD1(x)         (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_RSVD1_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_RSVD1_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN_MASK  (0x80000000U)
#define PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN_SHIFT (31U)
/*! SW1_HSK_EN - SW1_HSK_EN */
#define PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN(x)    (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN_MASK)
/*! @} */

/*! @name HANDSHAKE_CPU_STORE_SET -  */
/*! @{ */

#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_B0_READY_MASK (0x1U)
#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_B0_READY_SHIFT (0U)
/*! SW0_B0_READY - SW0_B0_READY */
#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_B0_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_SW0_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_SW0_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_B1_READY_MASK (0x2U)
#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_B1_READY_SHIFT (1U)
/*! SW0_B1_READY - SW0_B1_READY */
#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_B1_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_SW0_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_SW0_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_B0_DONE_MASK (0x4U)
#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_B0_DONE_SHIFT (2U)
/*! SW0_B0_DONE - SW0_B0_DONE */
#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_B0_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_SW0_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_SW0_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_B1_DONE_MASK (0x8U)
#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_B1_DONE_SHIFT (3U)
/*! SW0_B1_DONE - SW0_B1_DONE */
#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_B1_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_SW0_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_SW0_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_BUF_LINES_MASK (0x30U)
#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_BUF_LINES_SHIFT (4U)
/*! SW0_BUF_LINES - SW0_BUF_LINES */
#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_SW0_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_SW0_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SET_RSVD0_MASK   (0x7FC0U)
#define PXP_HANDSHAKE_CPU_STORE_SET_RSVD0_SHIFT  (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HANDSHAKE_CPU_STORE_SET_RSVD0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_RSVD0_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_RSVD0_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_HSK_EN_MASK (0x8000U)
#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_HSK_EN_SHIFT (15U)
/*! SW0_HSK_EN - SW0_HSK_EN */
#define PXP_HANDSHAKE_CPU_STORE_SET_SW0_HSK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_SW0_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_SW0_HSK_EN_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_B0_READY_MASK (0x10000U)
#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_B0_READY_SHIFT (16U)
/*! SW1_B0_READY - SW1_B0_READY */
#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_B0_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_SW1_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_SW1_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_B1_READY_MASK (0x20000U)
#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_B1_READY_SHIFT (17U)
/*! SW1_B1_READY - SW1_B1_READY */
#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_B1_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_SW1_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_SW1_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_B0_DONE_MASK (0x40000U)
#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_B0_DONE_SHIFT (18U)
/*! SW1_B0_DONE - SW1_B0_DONE */
#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_B0_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_SW1_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_SW1_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_B1_DONE_MASK (0x80000U)
#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_B1_DONE_SHIFT (19U)
/*! SW1_B1_DONE - SW1_B1_DONE */
#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_B1_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_SW1_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_SW1_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_BUF_LINES_MASK (0x300000U)
#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_BUF_LINES_SHIFT (20U)
/*! SW1_BUF_LINES - SW1_BUF_LINES */
#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_SW1_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_SW1_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SET_RSVD1_MASK   (0x7FC00000U)
#define PXP_HANDSHAKE_CPU_STORE_SET_RSVD1_SHIFT  (22U)
/*! RSVD1 - RSVD1 */
#define PXP_HANDSHAKE_CPU_STORE_SET_RSVD1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_RSVD1_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_RSVD1_MASK)

#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_HSK_EN_MASK (0x80000000U)
#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_HSK_EN_SHIFT (31U)
/*! SW1_HSK_EN - SW1_HSK_EN */
#define PXP_HANDSHAKE_CPU_STORE_SET_SW1_HSK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_SET_SW1_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_SET_SW1_HSK_EN_MASK)
/*! @} */

/*! @name HANDSHAKE_CPU_STORE_CLR -  */
/*! @{ */

#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B0_READY_MASK (0x1U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B0_READY_SHIFT (0U)
/*! SW0_B0_READY - SW0_B0_READY */
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B0_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B1_READY_MASK (0x2U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B1_READY_SHIFT (1U)
/*! SW0_B1_READY - SW0_B1_READY */
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B1_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B0_DONE_MASK (0x4U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B0_DONE_SHIFT (2U)
/*! SW0_B0_DONE - SW0_B0_DONE */
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B0_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B1_DONE_MASK (0x8U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B1_DONE_SHIFT (3U)
/*! SW0_B1_DONE - SW0_B1_DONE */
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B1_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_SW0_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_BUF_LINES_MASK (0x30U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_BUF_LINES_SHIFT (4U)
/*! SW0_BUF_LINES - SW0_BUF_LINES */
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_SW0_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_SW0_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_STORE_CLR_RSVD0_MASK   (0x7FC0U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_RSVD0_SHIFT  (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HANDSHAKE_CPU_STORE_CLR_RSVD0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_RSVD0_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_RSVD0_MASK)

#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_HSK_EN_MASK (0x8000U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_HSK_EN_SHIFT (15U)
/*! SW0_HSK_EN - SW0_HSK_EN */
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW0_HSK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_SW0_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_SW0_HSK_EN_MASK)

#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B0_READY_MASK (0x10000U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B0_READY_SHIFT (16U)
/*! SW1_B0_READY - SW1_B0_READY */
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B0_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B1_READY_MASK (0x20000U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B1_READY_SHIFT (17U)
/*! SW1_B1_READY - SW1_B1_READY */
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B1_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B0_DONE_MASK (0x40000U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B0_DONE_SHIFT (18U)
/*! SW1_B0_DONE - SW1_B0_DONE */
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B0_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B1_DONE_MASK (0x80000U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B1_DONE_SHIFT (19U)
/*! SW1_B1_DONE - SW1_B1_DONE */
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B1_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_SW1_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_BUF_LINES_MASK (0x300000U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_BUF_LINES_SHIFT (20U)
/*! SW1_BUF_LINES - SW1_BUF_LINES */
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_SW1_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_SW1_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_STORE_CLR_RSVD1_MASK   (0x7FC00000U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_RSVD1_SHIFT  (22U)
/*! RSVD1 - RSVD1 */
#define PXP_HANDSHAKE_CPU_STORE_CLR_RSVD1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_RSVD1_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_RSVD1_MASK)

#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_HSK_EN_MASK (0x80000000U)
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_HSK_EN_SHIFT (31U)
/*! SW1_HSK_EN - SW1_HSK_EN */
#define PXP_HANDSHAKE_CPU_STORE_CLR_SW1_HSK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_CLR_SW1_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_CLR_SW1_HSK_EN_MASK)
/*! @} */

/*! @name HANDSHAKE_CPU_STORE_TOG -  */
/*! @{ */

#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B0_READY_MASK (0x1U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B0_READY_SHIFT (0U)
/*! SW0_B0_READY - SW0_B0_READY */
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B0_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B1_READY_MASK (0x2U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B1_READY_SHIFT (1U)
/*! SW0_B1_READY - SW0_B1_READY */
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B1_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B0_DONE_MASK (0x4U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B0_DONE_SHIFT (2U)
/*! SW0_B0_DONE - SW0_B0_DONE */
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B0_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B1_DONE_MASK (0x8U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B1_DONE_SHIFT (3U)
/*! SW0_B1_DONE - SW0_B1_DONE */
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B1_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_SW0_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_BUF_LINES_MASK (0x30U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_BUF_LINES_SHIFT (4U)
/*! SW0_BUF_LINES - SW0_BUF_LINES */
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_SW0_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_SW0_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_STORE_TOG_RSVD0_MASK   (0x7FC0U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_RSVD0_SHIFT  (6U)
/*! RSVD0 - RSVD0 */
#define PXP_HANDSHAKE_CPU_STORE_TOG_RSVD0(x)     (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_RSVD0_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_RSVD0_MASK)

#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_HSK_EN_MASK (0x8000U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_HSK_EN_SHIFT (15U)
/*! SW0_HSK_EN - SW0_HSK_EN */
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW0_HSK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_SW0_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_SW0_HSK_EN_MASK)

#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B0_READY_MASK (0x10000U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B0_READY_SHIFT (16U)
/*! SW1_B0_READY - SW1_B0_READY */
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B0_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B0_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B0_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B1_READY_MASK (0x20000U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B1_READY_SHIFT (17U)
/*! SW1_B1_READY - SW1_B1_READY */
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B1_READY(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B1_READY_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B1_READY_MASK)

#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B0_DONE_MASK (0x40000U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B0_DONE_SHIFT (18U)
/*! SW1_B0_DONE - SW1_B0_DONE */
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B0_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B0_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B0_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B1_DONE_MASK (0x80000U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B1_DONE_SHIFT (19U)
/*! SW1_B1_DONE - SW1_B1_DONE */
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B1_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B1_DONE_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_SW1_B1_DONE_MASK)

#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_BUF_LINES_MASK (0x300000U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_BUF_LINES_SHIFT (20U)
/*! SW1_BUF_LINES - SW1_BUF_LINES */
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_BUF_LINES(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_SW1_BUF_LINES_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_SW1_BUF_LINES_MASK)

#define PXP_HANDSHAKE_CPU_STORE_TOG_RSVD1_MASK   (0x7FC00000U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_RSVD1_SHIFT  (22U)
/*! RSVD1 - RSVD1 */
#define PXP_HANDSHAKE_CPU_STORE_TOG_RSVD1(x)     (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_RSVD1_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_RSVD1_MASK)

#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_HSK_EN_MASK (0x80000000U)
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_HSK_EN_SHIFT (31U)
/*! SW1_HSK_EN - SW1_HSK_EN */
#define PXP_HANDSHAKE_CPU_STORE_TOG_SW1_HSK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_CPU_STORE_TOG_SW1_HSK_EN_SHIFT)) & PXP_HANDSHAKE_CPU_STORE_TOG_SW1_HSK_EN_MASK)
/*! @} */

/*! @name CFA_CTRL - CFA RGB format control */
/*! @{ */

#define PXP_CFA_CTRL_CFA_ARRAY_HSIZE_MASK        (0xFU)
#define PXP_CFA_CTRL_CFA_ARRAY_HSIZE_SHIFT       (0U)
/*! CFA_ARRAY_HSIZE - CFA array horizontal size in pixels */
#define PXP_CFA_CTRL_CFA_ARRAY_HSIZE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_CFA_ARRAY_HSIZE_SHIFT)) & PXP_CFA_CTRL_CFA_ARRAY_HSIZE_MASK)

#define PXP_CFA_CTRL_CFA_ARRAY_VSIZE_MASK        (0xF0U)
#define PXP_CFA_CTRL_CFA_ARRAY_VSIZE_SHIFT       (4U)
/*! CFA_ARRAY_VSIZE - CFA array vertical size in pixels */
#define PXP_CFA_CTRL_CFA_ARRAY_VSIZE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_CFA_ARRAY_VSIZE_SHIFT)) & PXP_CFA_CTRL_CFA_ARRAY_VSIZE_MASK)

#define PXP_CFA_CTRL_RSVD1_MASK                  (0x3FFFFF00U)
#define PXP_CFA_CTRL_RSVD1_SHIFT                 (8U)
/*! RSVD1 - RSVD1 */
#define PXP_CFA_CTRL_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_RSVD1_SHIFT)) & PXP_CFA_CTRL_RSVD1_MASK)

#define PXP_CFA_CTRL_CFA_IN_RGB444_MASK          (0x40000000U)
#define PXP_CFA_CTRL_CFA_IN_RGB444_SHIFT         (30U)
/*! CFA_IN_RGB444 - CFA_IN_RGB444
 *  0b0..CFA input is RGB888 format
 *  0b1..CFA input is RGB444 format
 */
#define PXP_CFA_CTRL_CFA_IN_RGB444(x)            (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_CFA_IN_RGB444_SHIFT)) & PXP_CFA_CTRL_CFA_IN_RGB444_MASK)

#define PXP_CFA_CTRL_CFA_BYPASS_MASK             (0x80000000U)
#define PXP_CFA_CTRL_CFA_BYPASS_SHIFT            (31U)
/*! CFA_BYPASS - CFA_BYPASS */
#define PXP_CFA_CTRL_CFA_BYPASS(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_CFA_BYPASS_SHIFT)) & PXP_CFA_CTRL_CFA_BYPASS_MASK)
/*! @} */

/*! @name CFA_CTRL_SET - CFA RGB format control */
/*! @{ */

#define PXP_CFA_CTRL_SET_CFA_ARRAY_HSIZE_MASK    (0xFU)
#define PXP_CFA_CTRL_SET_CFA_ARRAY_HSIZE_SHIFT   (0U)
/*! CFA_ARRAY_HSIZE - CFA array horizontal size in pixels */
#define PXP_CFA_CTRL_SET_CFA_ARRAY_HSIZE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_SET_CFA_ARRAY_HSIZE_SHIFT)) & PXP_CFA_CTRL_SET_CFA_ARRAY_HSIZE_MASK)

#define PXP_CFA_CTRL_SET_CFA_ARRAY_VSIZE_MASK    (0xF0U)
#define PXP_CFA_CTRL_SET_CFA_ARRAY_VSIZE_SHIFT   (4U)
/*! CFA_ARRAY_VSIZE - CFA array vertical size in pixels */
#define PXP_CFA_CTRL_SET_CFA_ARRAY_VSIZE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_SET_CFA_ARRAY_VSIZE_SHIFT)) & PXP_CFA_CTRL_SET_CFA_ARRAY_VSIZE_MASK)

#define PXP_CFA_CTRL_SET_RSVD1_MASK              (0x3FFFFF00U)
#define PXP_CFA_CTRL_SET_RSVD1_SHIFT             (8U)
/*! RSVD1 - RSVD1 */
#define PXP_CFA_CTRL_SET_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_SET_RSVD1_SHIFT)) & PXP_CFA_CTRL_SET_RSVD1_MASK)

#define PXP_CFA_CTRL_SET_CFA_IN_RGB444_MASK      (0x40000000U)
#define PXP_CFA_CTRL_SET_CFA_IN_RGB444_SHIFT     (30U)
/*! CFA_IN_RGB444 - CFA_IN_RGB444 */
#define PXP_CFA_CTRL_SET_CFA_IN_RGB444(x)        (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_SET_CFA_IN_RGB444_SHIFT)) & PXP_CFA_CTRL_SET_CFA_IN_RGB444_MASK)

#define PXP_CFA_CTRL_SET_CFA_BYPASS_MASK         (0x80000000U)
#define PXP_CFA_CTRL_SET_CFA_BYPASS_SHIFT        (31U)
/*! CFA_BYPASS - CFA_BYPASS */
#define PXP_CFA_CTRL_SET_CFA_BYPASS(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_SET_CFA_BYPASS_SHIFT)) & PXP_CFA_CTRL_SET_CFA_BYPASS_MASK)
/*! @} */

/*! @name CFA_CTRL_CLR - CFA RGB format control */
/*! @{ */

#define PXP_CFA_CTRL_CLR_CFA_ARRAY_HSIZE_MASK    (0xFU)
#define PXP_CFA_CTRL_CLR_CFA_ARRAY_HSIZE_SHIFT   (0U)
/*! CFA_ARRAY_HSIZE - CFA array horizontal size in pixels */
#define PXP_CFA_CTRL_CLR_CFA_ARRAY_HSIZE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_CLR_CFA_ARRAY_HSIZE_SHIFT)) & PXP_CFA_CTRL_CLR_CFA_ARRAY_HSIZE_MASK)

#define PXP_CFA_CTRL_CLR_CFA_ARRAY_VSIZE_MASK    (0xF0U)
#define PXP_CFA_CTRL_CLR_CFA_ARRAY_VSIZE_SHIFT   (4U)
/*! CFA_ARRAY_VSIZE - CFA array vertical size in pixels */
#define PXP_CFA_CTRL_CLR_CFA_ARRAY_VSIZE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_CLR_CFA_ARRAY_VSIZE_SHIFT)) & PXP_CFA_CTRL_CLR_CFA_ARRAY_VSIZE_MASK)

#define PXP_CFA_CTRL_CLR_RSVD1_MASK              (0x3FFFFF00U)
#define PXP_CFA_CTRL_CLR_RSVD1_SHIFT             (8U)
/*! RSVD1 - RSVD1 */
#define PXP_CFA_CTRL_CLR_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_CLR_RSVD1_SHIFT)) & PXP_CFA_CTRL_CLR_RSVD1_MASK)

#define PXP_CFA_CTRL_CLR_CFA_IN_RGB444_MASK      (0x40000000U)
#define PXP_CFA_CTRL_CLR_CFA_IN_RGB444_SHIFT     (30U)
/*! CFA_IN_RGB444 - CFA_IN_RGB444 */
#define PXP_CFA_CTRL_CLR_CFA_IN_RGB444(x)        (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_CLR_CFA_IN_RGB444_SHIFT)) & PXP_CFA_CTRL_CLR_CFA_IN_RGB444_MASK)

#define PXP_CFA_CTRL_CLR_CFA_BYPASS_MASK         (0x80000000U)
#define PXP_CFA_CTRL_CLR_CFA_BYPASS_SHIFT        (31U)
/*! CFA_BYPASS - CFA_BYPASS */
#define PXP_CFA_CTRL_CLR_CFA_BYPASS(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_CLR_CFA_BYPASS_SHIFT)) & PXP_CFA_CTRL_CLR_CFA_BYPASS_MASK)
/*! @} */

/*! @name CFA_CTRL_TOG - CFA RGB format control */
/*! @{ */

#define PXP_CFA_CTRL_TOG_CFA_ARRAY_HSIZE_MASK    (0xFU)
#define PXP_CFA_CTRL_TOG_CFA_ARRAY_HSIZE_SHIFT   (0U)
/*! CFA_ARRAY_HSIZE - CFA array horizontal size in pixels */
#define PXP_CFA_CTRL_TOG_CFA_ARRAY_HSIZE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_TOG_CFA_ARRAY_HSIZE_SHIFT)) & PXP_CFA_CTRL_TOG_CFA_ARRAY_HSIZE_MASK)

#define PXP_CFA_CTRL_TOG_CFA_ARRAY_VSIZE_MASK    (0xF0U)
#define PXP_CFA_CTRL_TOG_CFA_ARRAY_VSIZE_SHIFT   (4U)
/*! CFA_ARRAY_VSIZE - CFA array vertical size in pixels */
#define PXP_CFA_CTRL_TOG_CFA_ARRAY_VSIZE(x)      (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_TOG_CFA_ARRAY_VSIZE_SHIFT)) & PXP_CFA_CTRL_TOG_CFA_ARRAY_VSIZE_MASK)

#define PXP_CFA_CTRL_TOG_RSVD1_MASK              (0x3FFFFF00U)
#define PXP_CFA_CTRL_TOG_RSVD1_SHIFT             (8U)
/*! RSVD1 - RSVD1 */
#define PXP_CFA_CTRL_TOG_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_TOG_RSVD1_SHIFT)) & PXP_CFA_CTRL_TOG_RSVD1_MASK)

#define PXP_CFA_CTRL_TOG_CFA_IN_RGB444_MASK      (0x40000000U)
#define PXP_CFA_CTRL_TOG_CFA_IN_RGB444_SHIFT     (30U)
/*! CFA_IN_RGB444 - CFA_IN_RGB444 */
#define PXP_CFA_CTRL_TOG_CFA_IN_RGB444(x)        (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_TOG_CFA_IN_RGB444_SHIFT)) & PXP_CFA_CTRL_TOG_CFA_IN_RGB444_MASK)

#define PXP_CFA_CTRL_TOG_CFA_BYPASS_MASK         (0x80000000U)
#define PXP_CFA_CTRL_TOG_CFA_BYPASS_SHIFT        (31U)
/*! CFA_BYPASS - CFA_BYPASS */
#define PXP_CFA_CTRL_TOG_CFA_BYPASS(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CFA_CTRL_TOG_CFA_BYPASS_SHIFT)) & PXP_CFA_CTRL_TOG_CFA_BYPASS_MASK)
/*! @} */

/*! @name CFA_SIZE - CFA_SIZE */
/*! @{ */

#define PXP_CFA_SIZE_CFA_VSIZE_MASK              (0xFFFFU)
#define PXP_CFA_SIZE_CFA_VSIZE_SHIFT             (0U)
/*! CFA_VSIZE - CFA vertical size in pixels */
#define PXP_CFA_SIZE_CFA_VSIZE(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CFA_SIZE_CFA_VSIZE_SHIFT)) & PXP_CFA_SIZE_CFA_VSIZE_MASK)

#define PXP_CFA_SIZE_CFA_HSIZE_MASK              (0xFFFF0000U)
#define PXP_CFA_SIZE_CFA_HSIZE_SHIFT             (16U)
/*! CFA_HSIZE - CFA horizontal size in pixels */
#define PXP_CFA_SIZE_CFA_HSIZE(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CFA_SIZE_CFA_HSIZE_SHIFT)) & PXP_CFA_SIZE_CFA_HSIZE_MASK)
/*! @} */

/*! @name CFA_ARRAY0 - CFA_ARRAY0 */
/*! @{ */

#define PXP_CFA_ARRAY0_CFA_ARRAY0_MASK           (0xFFFFFFFFU)
#define PXP_CFA_ARRAY0_CFA_ARRAY0_SHIFT          (0U)
/*! CFA_ARRAY0 - CFA array value */
#define PXP_CFA_ARRAY0_CFA_ARRAY0(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY0_CFA_ARRAY0_SHIFT)) & PXP_CFA_ARRAY0_CFA_ARRAY0_MASK)
/*! @} */

/*! @name CFA_ARRAY1 - CFA_ARRAY1 */
/*! @{ */

#define PXP_CFA_ARRAY1_CFA_ARRAY1_MASK           (0xFFFFFFFFU)
#define PXP_CFA_ARRAY1_CFA_ARRAY1_SHIFT          (0U)
/*! CFA_ARRAY1 - CFA array value */
#define PXP_CFA_ARRAY1_CFA_ARRAY1(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY1_CFA_ARRAY1_SHIFT)) & PXP_CFA_ARRAY1_CFA_ARRAY1_MASK)
/*! @} */

/*! @name CFA_ARRAY2 - CFA_ARRAY2 */
/*! @{ */

#define PXP_CFA_ARRAY2_CFA_ARRAY2_MASK           (0xFFFFFFFFU)
#define PXP_CFA_ARRAY2_CFA_ARRAY2_SHIFT          (0U)
/*! CFA_ARRAY2 - CFA array value */
#define PXP_CFA_ARRAY2_CFA_ARRAY2(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY2_CFA_ARRAY2_SHIFT)) & PXP_CFA_ARRAY2_CFA_ARRAY2_MASK)
/*! @} */

/*! @name CFA_ARRAY3 - CFA_ARRAY3 */
/*! @{ */

#define PXP_CFA_ARRAY3_CFA_ARRAY3_MASK           (0xFFFFFFFFU)
#define PXP_CFA_ARRAY3_CFA_ARRAY3_SHIFT          (0U)
/*! CFA_ARRAY3 - CFA array value */
#define PXP_CFA_ARRAY3_CFA_ARRAY3(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY3_CFA_ARRAY3_SHIFT)) & PXP_CFA_ARRAY3_CFA_ARRAY3_MASK)
/*! @} */

/*! @name CFA_ARRAY4 - CFA_ARRAY4 */
/*! @{ */

#define PXP_CFA_ARRAY4_CFA_ARRAY4_MASK           (0xFFFFFFFFU)
#define PXP_CFA_ARRAY4_CFA_ARRAY4_SHIFT          (0U)
/*! CFA_ARRAY4 - CFA array value */
#define PXP_CFA_ARRAY4_CFA_ARRAY4(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY4_CFA_ARRAY4_SHIFT)) & PXP_CFA_ARRAY4_CFA_ARRAY4_MASK)
/*! @} */

/*! @name CFA_ARRAY5 - CFA_ARRAY5 */
/*! @{ */

#define PXP_CFA_ARRAY5_CFA_ARRAY5_MASK           (0xFFFFFFFFU)
#define PXP_CFA_ARRAY5_CFA_ARRAY5_SHIFT          (0U)
/*! CFA_ARRAY5 - CFA array value */
#define PXP_CFA_ARRAY5_CFA_ARRAY5(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY5_CFA_ARRAY5_SHIFT)) & PXP_CFA_ARRAY5_CFA_ARRAY5_MASK)
/*! @} */

/*! @name CFA_ARRAY6 - CFA_ARRAY6 */
/*! @{ */

#define PXP_CFA_ARRAY6_CFA_ARRAY6_MASK           (0xFFFFFFFFU)
#define PXP_CFA_ARRAY6_CFA_ARRAY6_SHIFT          (0U)
/*! CFA_ARRAY6 - CFA array value */
#define PXP_CFA_ARRAY6_CFA_ARRAY6(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY6_CFA_ARRAY6_SHIFT)) & PXP_CFA_ARRAY6_CFA_ARRAY6_MASK)
/*! @} */

/*! @name CFA_ARRAY7 - CFA_ARRAY7 */
/*! @{ */

#define PXP_CFA_ARRAY7_CFA_ARRAY7_MASK           (0xFFFFFFFFU)
#define PXP_CFA_ARRAY7_CFA_ARRAY7_SHIFT          (0U)
/*! CFA_ARRAY7 - CFA array value */
#define PXP_CFA_ARRAY7_CFA_ARRAY7(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY7_CFA_ARRAY7_SHIFT)) & PXP_CFA_ARRAY7_CFA_ARRAY7_MASK)
/*! @} */

/*! @name CFA_ARRAY8 - CFA_ARRAY8 */
/*! @{ */

#define PXP_CFA_ARRAY8_CFA_ARRAY8_MASK           (0xFFFFFFFFU)
#define PXP_CFA_ARRAY8_CFA_ARRAY8_SHIFT          (0U)
/*! CFA_ARRAY8 - CFA array value */
#define PXP_CFA_ARRAY8_CFA_ARRAY8(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY8_CFA_ARRAY8_SHIFT)) & PXP_CFA_ARRAY8_CFA_ARRAY8_MASK)
/*! @} */

/*! @name CFA_ARRAY9 - CFA_ARRAY9 */
/*! @{ */

#define PXP_CFA_ARRAY9_CFA_ARRAY9_MASK           (0xFFFFFFFFU)
#define PXP_CFA_ARRAY9_CFA_ARRAY9_SHIFT          (0U)
/*! CFA_ARRAY9 - CFA array value */
#define PXP_CFA_ARRAY9_CFA_ARRAY9(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY9_CFA_ARRAY9_SHIFT)) & PXP_CFA_ARRAY9_CFA_ARRAY9_MASK)
/*! @} */

/*! @name CFA_ARRAY10 - CFA_ARRAY10 */
/*! @{ */

#define PXP_CFA_ARRAY10_CFA_ARRAY10_MASK         (0xFFFFFFFFU)
#define PXP_CFA_ARRAY10_CFA_ARRAY10_SHIFT        (0U)
/*! CFA_ARRAY10 - CFA array value */
#define PXP_CFA_ARRAY10_CFA_ARRAY10(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY10_CFA_ARRAY10_SHIFT)) & PXP_CFA_ARRAY10_CFA_ARRAY10_MASK)
/*! @} */

/*! @name CFA_ARRAY11 - CFA_ARRAY11 */
/*! @{ */

#define PXP_CFA_ARRAY11_CFA_ARRAY11_MASK         (0xFFFFFFFFU)
#define PXP_CFA_ARRAY11_CFA_ARRAY11_SHIFT        (0U)
/*! CFA_ARRAY11 - CFA array value */
#define PXP_CFA_ARRAY11_CFA_ARRAY11(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY11_CFA_ARRAY11_SHIFT)) & PXP_CFA_ARRAY11_CFA_ARRAY11_MASK)
/*! @} */

/*! @name CFA_ARRAY12 - CFA_ARRAY12 */
/*! @{ */

#define PXP_CFA_ARRAY12_CFA_ARRAY12_MASK         (0xFFFFFFFFU)
#define PXP_CFA_ARRAY12_CFA_ARRAY12_SHIFT        (0U)
/*! CFA_ARRAY12 - CFA array value */
#define PXP_CFA_ARRAY12_CFA_ARRAY12(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY12_CFA_ARRAY12_SHIFT)) & PXP_CFA_ARRAY12_CFA_ARRAY12_MASK)
/*! @} */

/*! @name CFA_ARRAY13 - CFA_ARRAY13 */
/*! @{ */

#define PXP_CFA_ARRAY13_CFA_ARRAY13_MASK         (0xFFFFFFFFU)
#define PXP_CFA_ARRAY13_CFA_ARRAY13_SHIFT        (0U)
/*! CFA_ARRAY13 - CFA array value */
#define PXP_CFA_ARRAY13_CFA_ARRAY13(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY13_CFA_ARRAY13_SHIFT)) & PXP_CFA_ARRAY13_CFA_ARRAY13_MASK)
/*! @} */

/*! @name CFA_ARRAY14 - CFA_ARRAY14 */
/*! @{ */

#define PXP_CFA_ARRAY14_CFA_ARRAY14_MASK         (0xFFFFFFFFU)
#define PXP_CFA_ARRAY14_CFA_ARRAY14_SHIFT        (0U)
/*! CFA_ARRAY14 - CFA array value */
#define PXP_CFA_ARRAY14_CFA_ARRAY14(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY14_CFA_ARRAY14_SHIFT)) & PXP_CFA_ARRAY14_CFA_ARRAY14_MASK)
/*! @} */

/*! @name CFA_ARRAY15 - CFA_ARRAY15 */
/*! @{ */

#define PXP_CFA_ARRAY15_CFA_ARRAY15_MASK         (0xFFFFFFFFU)
#define PXP_CFA_ARRAY15_CFA_ARRAY15_SHIFT        (0U)
/*! CFA_ARRAY15 - CFA array value */
#define PXP_CFA_ARRAY15_CFA_ARRAY15(x)           (((uint32_t)(((uint32_t)(x)) << PXP_CFA_ARRAY15_CFA_ARRAY15_SHIFT)) & PXP_CFA_ARRAY15_CFA_ARRAY15_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PXP_Register_Masks */


/* PXP - Peripheral instance base addresses */
/** Peripheral PXP base address */
#define PXP_BASE                                 (0x2DB40000u)
/** Peripheral PXP base pointer */
#define PXP                                      ((PXP_Type *)PXP_BASE)
/** Array initializer of PXP peripheral base addresses */
#define PXP_BASE_ADDRS                           { PXP_BASE }
/** Array initializer of PXP peripheral base pointers */
#define PXP_BASE_PTRS                            { PXP }

/*!
 * @}
 */ /* end of group PXP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RGPIO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RGPIO_Peripheral_Access_Layer RGPIO Peripheral Access Layer
 * @{
 */

/** RGPIO - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
       uint8_t RESERVED_0[4];
  __IO uint32_t LOCK;                              /**< Lock Register, offset: 0xC */
  __IO uint32_t PCNS;                              /**< Pin Control Non-Secure, offset: 0x10 */
  __IO uint32_t ICNS;                              /**< Interrupt Control Non-Secure, offset: 0x14 */
  __IO uint32_t PCNP;                              /**< Pin Control Non-Privilege, offset: 0x18 */
  __IO uint32_t ICNP;                              /**< Interrupt Control Non-Privilege, offset: 0x1C */
       uint8_t RESERVED_1[32];
  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x40 */
  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x44 */
  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x48 */
  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0x4C */
  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x50 */
  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x54 */
  __IO uint32_t PIDR;                              /**< Port Input Disable Register, offset: 0x58 */
       uint8_t RESERVED_2[4];
  __IO uint8_t PDR[32];                            /**< Pin Data Register a, array offset: 0x60, array step: 0x1 */
  __IO uint32_t ICR[32];                           /**< Interrupt Control Register 0..Interrupt Control Register 31, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */
  __O  uint32_t GICLR;                             /**< Global Interrupt Control Low Register, offset: 0x100 */
  __O  uint32_t GICHR;                             /**< Global Interrupt Control High Register, offset: 0x104 */
       uint8_t RESERVED_3[24];
  __IO uint32_t ISFR[4];                           /**< Interrupt Status Flag Register, array offset: 0x120, array step: 0x4 */
} RGPIO_Type;

/* ----------------------------------------------------------------------------
   -- RGPIO Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RGPIO_Register_Masks RGPIO Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define RGPIO_VERID_FEATURE_MASK                 (0xFFFFU)
#define RGPIO_VERID_FEATURE_SHIFT                (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000000..Basic implementation.
 *  0b0000000000000001..Protection registers implemented.
 */
#define RGPIO_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_FEATURE_SHIFT)) & RGPIO_VERID_FEATURE_MASK)

#define RGPIO_VERID_MINOR_MASK                   (0xFF0000U)
#define RGPIO_VERID_MINOR_SHIFT                  (16U)
/*! MINOR - Minor Version Number */
#define RGPIO_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_MINOR_SHIFT)) & RGPIO_VERID_MINOR_MASK)

#define RGPIO_VERID_MAJOR_MASK                   (0xFF000000U)
#define RGPIO_VERID_MAJOR_SHIFT                  (24U)
/*! MAJOR - Major Version Number */
#define RGPIO_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_MAJOR_SHIFT)) & RGPIO_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define RGPIO_PARAM_IRQNUM_MASK                  (0xFU)
#define RGPIO_PARAM_IRQNUM_SHIFT                 (0U)
/*! IRQNUM - Interrupt Number */
#define RGPIO_PARAM_IRQNUM(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_PARAM_IRQNUM_SHIFT)) & RGPIO_PARAM_IRQNUM_MASK)
/*! @} */

/*! @name LOCK - Lock Register */
/*! @{ */

#define RGPIO_LOCK_PCNS_MASK                     (0x1U)
#define RGPIO_LOCK_PCNS_SHIFT                    (0U)
/*! PCNS - Lock PCNS
 *  0b0..PCNS register is writable by software in secure-privilege state.
 *  0b1..PCNS register is not writable until the next reset.
 */
#define RGPIO_LOCK_PCNS(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_PCNS_SHIFT)) & RGPIO_LOCK_PCNS_MASK)

#define RGPIO_LOCK_ICNS_MASK                     (0x2U)
#define RGPIO_LOCK_ICNS_SHIFT                    (1U)
/*! ICNS - Lock ICNS
 *  0b0..ICNS register is writable by software in secure-privilege state.
 *  0b1..ICNS register is not writable until the next reset.
 */
#define RGPIO_LOCK_ICNS(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_ICNS_SHIFT)) & RGPIO_LOCK_ICNS_MASK)

#define RGPIO_LOCK_PCNP_MASK                     (0x4U)
#define RGPIO_LOCK_PCNP_SHIFT                    (2U)
/*! PCNP - Lock PCNP
 *  0b0..PCNP register is writable by software in secure-privilege state.
 *  0b1..PCNP register is not writable until the next reset.
 */
#define RGPIO_LOCK_PCNP(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_PCNP_SHIFT)) & RGPIO_LOCK_PCNP_MASK)

#define RGPIO_LOCK_ICNP_MASK                     (0x8U)
#define RGPIO_LOCK_ICNP_SHIFT                    (3U)
/*! ICNP - Lock ICNP
 *  0b0..ICNP register is writable by software in secure-privilege state.
 *  0b1..ICNP register is not writable until the next reset.
 */
#define RGPIO_LOCK_ICNP(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_ICNP_SHIFT)) & RGPIO_LOCK_ICNP_MASK)
/*! @} */

/*! @name PCNS - Pin Control Non-Secure */
/*! @{ */

#define RGPIO_PCNS_NSE0_MASK                     (0x1U)
#define RGPIO_PCNS_NSE0_SHIFT                    (0U)
/*! NSE0 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE0_SHIFT)) & RGPIO_PCNS_NSE0_MASK)

#define RGPIO_PCNS_NSE1_MASK                     (0x2U)
#define RGPIO_PCNS_NSE1_SHIFT                    (1U)
/*! NSE1 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE1_SHIFT)) & RGPIO_PCNS_NSE1_MASK)

#define RGPIO_PCNS_NSE2_MASK                     (0x4U)
#define RGPIO_PCNS_NSE2_SHIFT                    (2U)
/*! NSE2 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE2_SHIFT)) & RGPIO_PCNS_NSE2_MASK)

#define RGPIO_PCNS_NSE3_MASK                     (0x8U)
#define RGPIO_PCNS_NSE3_SHIFT                    (3U)
/*! NSE3 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE3_SHIFT)) & RGPIO_PCNS_NSE3_MASK)

#define RGPIO_PCNS_NSE4_MASK                     (0x10U)
#define RGPIO_PCNS_NSE4_SHIFT                    (4U)
/*! NSE4 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE4_SHIFT)) & RGPIO_PCNS_NSE4_MASK)

#define RGPIO_PCNS_NSE5_MASK                     (0x20U)
#define RGPIO_PCNS_NSE5_SHIFT                    (5U)
/*! NSE5 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE5_SHIFT)) & RGPIO_PCNS_NSE5_MASK)

#define RGPIO_PCNS_NSE6_MASK                     (0x40U)
#define RGPIO_PCNS_NSE6_SHIFT                    (6U)
/*! NSE6 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE6_SHIFT)) & RGPIO_PCNS_NSE6_MASK)

#define RGPIO_PCNS_NSE7_MASK                     (0x80U)
#define RGPIO_PCNS_NSE7_SHIFT                    (7U)
/*! NSE7 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE7_SHIFT)) & RGPIO_PCNS_NSE7_MASK)

#define RGPIO_PCNS_NSE8_MASK                     (0x100U)
#define RGPIO_PCNS_NSE8_SHIFT                    (8U)
/*! NSE8 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE8_SHIFT)) & RGPIO_PCNS_NSE8_MASK)

#define RGPIO_PCNS_NSE9_MASK                     (0x200U)
#define RGPIO_PCNS_NSE9_SHIFT                    (9U)
/*! NSE9 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE9_SHIFT)) & RGPIO_PCNS_NSE9_MASK)

#define RGPIO_PCNS_NSE10_MASK                    (0x400U)
#define RGPIO_PCNS_NSE10_SHIFT                   (10U)
/*! NSE10 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE10_SHIFT)) & RGPIO_PCNS_NSE10_MASK)

#define RGPIO_PCNS_NSE11_MASK                    (0x800U)
#define RGPIO_PCNS_NSE11_SHIFT                   (11U)
/*! NSE11 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE11_SHIFT)) & RGPIO_PCNS_NSE11_MASK)

#define RGPIO_PCNS_NSE12_MASK                    (0x1000U)
#define RGPIO_PCNS_NSE12_SHIFT                   (12U)
/*! NSE12 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE12_SHIFT)) & RGPIO_PCNS_NSE12_MASK)

#define RGPIO_PCNS_NSE13_MASK                    (0x2000U)
#define RGPIO_PCNS_NSE13_SHIFT                   (13U)
/*! NSE13 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE13_SHIFT)) & RGPIO_PCNS_NSE13_MASK)

#define RGPIO_PCNS_NSE14_MASK                    (0x4000U)
#define RGPIO_PCNS_NSE14_SHIFT                   (14U)
/*! NSE14 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE14_SHIFT)) & RGPIO_PCNS_NSE14_MASK)

#define RGPIO_PCNS_NSE15_MASK                    (0x8000U)
#define RGPIO_PCNS_NSE15_SHIFT                   (15U)
/*! NSE15 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE15_SHIFT)) & RGPIO_PCNS_NSE15_MASK)

#define RGPIO_PCNS_NSE16_MASK                    (0x10000U)
#define RGPIO_PCNS_NSE16_SHIFT                   (16U)
/*! NSE16 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE16_SHIFT)) & RGPIO_PCNS_NSE16_MASK)

#define RGPIO_PCNS_NSE17_MASK                    (0x20000U)
#define RGPIO_PCNS_NSE17_SHIFT                   (17U)
/*! NSE17 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE17_SHIFT)) & RGPIO_PCNS_NSE17_MASK)

#define RGPIO_PCNS_NSE18_MASK                    (0x40000U)
#define RGPIO_PCNS_NSE18_SHIFT                   (18U)
/*! NSE18 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE18_SHIFT)) & RGPIO_PCNS_NSE18_MASK)

#define RGPIO_PCNS_NSE19_MASK                    (0x80000U)
#define RGPIO_PCNS_NSE19_SHIFT                   (19U)
/*! NSE19 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE19_SHIFT)) & RGPIO_PCNS_NSE19_MASK)

#define RGPIO_PCNS_NSE20_MASK                    (0x100000U)
#define RGPIO_PCNS_NSE20_SHIFT                   (20U)
/*! NSE20 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE20_SHIFT)) & RGPIO_PCNS_NSE20_MASK)

#define RGPIO_PCNS_NSE21_MASK                    (0x200000U)
#define RGPIO_PCNS_NSE21_SHIFT                   (21U)
/*! NSE21 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE21_SHIFT)) & RGPIO_PCNS_NSE21_MASK)

#define RGPIO_PCNS_NSE22_MASK                    (0x400000U)
#define RGPIO_PCNS_NSE22_SHIFT                   (22U)
/*! NSE22 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE22_SHIFT)) & RGPIO_PCNS_NSE22_MASK)

#define RGPIO_PCNS_NSE23_MASK                    (0x800000U)
#define RGPIO_PCNS_NSE23_SHIFT                   (23U)
/*! NSE23 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE23_SHIFT)) & RGPIO_PCNS_NSE23_MASK)

#define RGPIO_PCNS_NSE24_MASK                    (0x1000000U)
#define RGPIO_PCNS_NSE24_SHIFT                   (24U)
/*! NSE24 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE24_SHIFT)) & RGPIO_PCNS_NSE24_MASK)

#define RGPIO_PCNS_NSE25_MASK                    (0x2000000U)
#define RGPIO_PCNS_NSE25_SHIFT                   (25U)
/*! NSE25 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE25_SHIFT)) & RGPIO_PCNS_NSE25_MASK)

#define RGPIO_PCNS_NSE26_MASK                    (0x4000000U)
#define RGPIO_PCNS_NSE26_SHIFT                   (26U)
/*! NSE26 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE26_SHIFT)) & RGPIO_PCNS_NSE26_MASK)

#define RGPIO_PCNS_NSE27_MASK                    (0x8000000U)
#define RGPIO_PCNS_NSE27_SHIFT                   (27U)
/*! NSE27 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE27_SHIFT)) & RGPIO_PCNS_NSE27_MASK)

#define RGPIO_PCNS_NSE28_MASK                    (0x10000000U)
#define RGPIO_PCNS_NSE28_SHIFT                   (28U)
/*! NSE28 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE28_SHIFT)) & RGPIO_PCNS_NSE28_MASK)

#define RGPIO_PCNS_NSE29_MASK                    (0x20000000U)
#define RGPIO_PCNS_NSE29_SHIFT                   (29U)
/*! NSE29 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE29_SHIFT)) & RGPIO_PCNS_NSE29_MASK)

#define RGPIO_PCNS_NSE30_MASK                    (0x40000000U)
#define RGPIO_PCNS_NSE30_SHIFT                   (30U)
/*! NSE30 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE30_SHIFT)) & RGPIO_PCNS_NSE30_MASK)

#define RGPIO_PCNS_NSE31_MASK                    (0x80000000U)
#define RGPIO_PCNS_NSE31_SHIFT                   (31U)
/*! NSE31 - Non-Secure Enable
 *  0b0..The pin is configured for secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in secure state. When the corresponding pin's registers is accessed
 *       by software in non-secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for non-secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in non-secure state. When the corresponding pin's registers is
 *       accessed by software in secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define RGPIO_PCNS_NSE31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE31_SHIFT)) & RGPIO_PCNS_NSE31_MASK)
/*! @} */

/*! @name ICNS - Interrupt Control Non-Secure */
/*! @{ */

#define RGPIO_ICNS_NSE0_MASK                     (0x1U)
#define RGPIO_ICNS_NSE0_SHIFT                    (0U)
/*! NSE0 - Non-Secure Enable
 *  0b0..The interrupt/DMA request/trigger output is configured for secure access. Only software in secure state
 *       can configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a pin that
 *       is already configured to use the corresponding interrupt/DMA request/trigger output.
 *  0b1..The interrupt/DMA request/trigger output is configured for non-secure access. Only software in non-secure
 *       state can configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a
 *       pin that is already configured to use the corresponding interrupt/DMA request/trigger output.
 */
#define RGPIO_ICNS_NSE0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNS_NSE0_SHIFT)) & RGPIO_ICNS_NSE0_MASK)

#define RGPIO_ICNS_NSE1_MASK                     (0x2U)
#define RGPIO_ICNS_NSE1_SHIFT                    (1U)
/*! NSE1 - Non-Secure Enable
 *  0b0..The interrupt/DMA request/trigger output is configured for secure access. Only software in secure state
 *       can configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a pin that
 *       is already configured to use the corresponding interrupt/DMA request/trigger output.
 *  0b1..The interrupt/DMA request/trigger output is configured for non-secure access. Only software in non-secure
 *       state can configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a
 *       pin that is already configured to use the corresponding interrupt/DMA request/trigger output.
 */
#define RGPIO_ICNS_NSE1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNS_NSE1_SHIFT)) & RGPIO_ICNS_NSE1_MASK)

#define RGPIO_ICNS_NSE2_MASK                     (0x4U)
#define RGPIO_ICNS_NSE2_SHIFT                    (2U)
/*! NSE2 - Non-Secure Enable
 *  0b0..The interrupt/DMA request/trigger output is configured for secure access. Only software in secure state
 *       can configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a pin that
 *       is already configured to use the corresponding interrupt/DMA request/trigger output.
 *  0b1..The interrupt/DMA request/trigger output is configured for non-secure access. Only software in non-secure
 *       state can configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a
 *       pin that is already configured to use the corresponding interrupt/DMA request/trigger output.
 */
#define RGPIO_ICNS_NSE2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNS_NSE2_SHIFT)) & RGPIO_ICNS_NSE2_MASK)

#define RGPIO_ICNS_NSE3_MASK                     (0x8U)
#define RGPIO_ICNS_NSE3_SHIFT                    (3U)
/*! NSE3 - Non-Secure Enable
 *  0b0..The interrupt/DMA request/trigger output is configured for secure access. Only software in secure state
 *       can configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a pin that
 *       is already configured to use the corresponding interrupt/DMA request/trigger output.
 *  0b1..The interrupt/DMA request/trigger output is configured for non-secure access. Only software in non-secure
 *       state can configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a
 *       pin that is already configured to use the corresponding interrupt/DMA request/trigger output.
 */
#define RGPIO_ICNS_NSE3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNS_NSE3_SHIFT)) & RGPIO_ICNS_NSE3_MASK)
/*! @} */

/*! @name PCNP - Pin Control Non-Privilege */
/*! @{ */

#define RGPIO_PCNP_NPE0_MASK                     (0x1U)
#define RGPIO_PCNP_NPE0_SHIFT                    (0U)
/*! NPE0 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE0_SHIFT)) & RGPIO_PCNP_NPE0_MASK)

#define RGPIO_PCNP_NPE1_MASK                     (0x2U)
#define RGPIO_PCNP_NPE1_SHIFT                    (1U)
/*! NPE1 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE1_SHIFT)) & RGPIO_PCNP_NPE1_MASK)

#define RGPIO_PCNP_NPE2_MASK                     (0x4U)
#define RGPIO_PCNP_NPE2_SHIFT                    (2U)
/*! NPE2 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE2_SHIFT)) & RGPIO_PCNP_NPE2_MASK)

#define RGPIO_PCNP_NPE3_MASK                     (0x8U)
#define RGPIO_PCNP_NPE3_SHIFT                    (3U)
/*! NPE3 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE3_SHIFT)) & RGPIO_PCNP_NPE3_MASK)

#define RGPIO_PCNP_NPE4_MASK                     (0x10U)
#define RGPIO_PCNP_NPE4_SHIFT                    (4U)
/*! NPE4 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE4_SHIFT)) & RGPIO_PCNP_NPE4_MASK)

#define RGPIO_PCNP_NPE5_MASK                     (0x20U)
#define RGPIO_PCNP_NPE5_SHIFT                    (5U)
/*! NPE5 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE5_SHIFT)) & RGPIO_PCNP_NPE5_MASK)

#define RGPIO_PCNP_NPE6_MASK                     (0x40U)
#define RGPIO_PCNP_NPE6_SHIFT                    (6U)
/*! NPE6 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE6_SHIFT)) & RGPIO_PCNP_NPE6_MASK)

#define RGPIO_PCNP_NPE7_MASK                     (0x80U)
#define RGPIO_PCNP_NPE7_SHIFT                    (7U)
/*! NPE7 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE7_SHIFT)) & RGPIO_PCNP_NPE7_MASK)

#define RGPIO_PCNP_NPE8_MASK                     (0x100U)
#define RGPIO_PCNP_NPE8_SHIFT                    (8U)
/*! NPE8 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE8_SHIFT)) & RGPIO_PCNP_NPE8_MASK)

#define RGPIO_PCNP_NPE9_MASK                     (0x200U)
#define RGPIO_PCNP_NPE9_SHIFT                    (9U)
/*! NPE9 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE9_SHIFT)) & RGPIO_PCNP_NPE9_MASK)

#define RGPIO_PCNP_NPE10_MASK                    (0x400U)
#define RGPIO_PCNP_NPE10_SHIFT                   (10U)
/*! NPE10 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE10_SHIFT)) & RGPIO_PCNP_NPE10_MASK)

#define RGPIO_PCNP_NPE11_MASK                    (0x800U)
#define RGPIO_PCNP_NPE11_SHIFT                   (11U)
/*! NPE11 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE11_SHIFT)) & RGPIO_PCNP_NPE11_MASK)

#define RGPIO_PCNP_NPE12_MASK                    (0x1000U)
#define RGPIO_PCNP_NPE12_SHIFT                   (12U)
/*! NPE12 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE12_SHIFT)) & RGPIO_PCNP_NPE12_MASK)

#define RGPIO_PCNP_NPE13_MASK                    (0x2000U)
#define RGPIO_PCNP_NPE13_SHIFT                   (13U)
/*! NPE13 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE13_SHIFT)) & RGPIO_PCNP_NPE13_MASK)

#define RGPIO_PCNP_NPE14_MASK                    (0x4000U)
#define RGPIO_PCNP_NPE14_SHIFT                   (14U)
/*! NPE14 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE14_SHIFT)) & RGPIO_PCNP_NPE14_MASK)

#define RGPIO_PCNP_NPE15_MASK                    (0x8000U)
#define RGPIO_PCNP_NPE15_SHIFT                   (15U)
/*! NPE15 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE15_SHIFT)) & RGPIO_PCNP_NPE15_MASK)

#define RGPIO_PCNP_NPE16_MASK                    (0x10000U)
#define RGPIO_PCNP_NPE16_SHIFT                   (16U)
/*! NPE16 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE16_SHIFT)) & RGPIO_PCNP_NPE16_MASK)

#define RGPIO_PCNP_NPE17_MASK                    (0x20000U)
#define RGPIO_PCNP_NPE17_SHIFT                   (17U)
/*! NPE17 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE17_SHIFT)) & RGPIO_PCNP_NPE17_MASK)

#define RGPIO_PCNP_NPE18_MASK                    (0x40000U)
#define RGPIO_PCNP_NPE18_SHIFT                   (18U)
/*! NPE18 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE18_SHIFT)) & RGPIO_PCNP_NPE18_MASK)

#define RGPIO_PCNP_NPE19_MASK                    (0x80000U)
#define RGPIO_PCNP_NPE19_SHIFT                   (19U)
/*! NPE19 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE19_SHIFT)) & RGPIO_PCNP_NPE19_MASK)

#define RGPIO_PCNP_NPE20_MASK                    (0x100000U)
#define RGPIO_PCNP_NPE20_SHIFT                   (20U)
/*! NPE20 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE20_SHIFT)) & RGPIO_PCNP_NPE20_MASK)

#define RGPIO_PCNP_NPE21_MASK                    (0x200000U)
#define RGPIO_PCNP_NPE21_SHIFT                   (21U)
/*! NPE21 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE21_SHIFT)) & RGPIO_PCNP_NPE21_MASK)

#define RGPIO_PCNP_NPE22_MASK                    (0x400000U)
#define RGPIO_PCNP_NPE22_SHIFT                   (22U)
/*! NPE22 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE22_SHIFT)) & RGPIO_PCNP_NPE22_MASK)

#define RGPIO_PCNP_NPE23_MASK                    (0x800000U)
#define RGPIO_PCNP_NPE23_SHIFT                   (23U)
/*! NPE23 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE23_SHIFT)) & RGPIO_PCNP_NPE23_MASK)

#define RGPIO_PCNP_NPE24_MASK                    (0x1000000U)
#define RGPIO_PCNP_NPE24_SHIFT                   (24U)
/*! NPE24 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE24_SHIFT)) & RGPIO_PCNP_NPE24_MASK)

#define RGPIO_PCNP_NPE25_MASK                    (0x2000000U)
#define RGPIO_PCNP_NPE25_SHIFT                   (25U)
/*! NPE25 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE25_SHIFT)) & RGPIO_PCNP_NPE25_MASK)

#define RGPIO_PCNP_NPE26_MASK                    (0x4000000U)
#define RGPIO_PCNP_NPE26_SHIFT                   (26U)
/*! NPE26 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE26_SHIFT)) & RGPIO_PCNP_NPE26_MASK)

#define RGPIO_PCNP_NPE27_MASK                    (0x8000000U)
#define RGPIO_PCNP_NPE27_SHIFT                   (27U)
/*! NPE27 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE27_SHIFT)) & RGPIO_PCNP_NPE27_MASK)

#define RGPIO_PCNP_NPE28_MASK                    (0x10000000U)
#define RGPIO_PCNP_NPE28_SHIFT                   (28U)
/*! NPE28 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE28_SHIFT)) & RGPIO_PCNP_NPE28_MASK)

#define RGPIO_PCNP_NPE29_MASK                    (0x20000000U)
#define RGPIO_PCNP_NPE29_SHIFT                   (29U)
/*! NPE29 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE29_SHIFT)) & RGPIO_PCNP_NPE29_MASK)

#define RGPIO_PCNP_NPE30_MASK                    (0x40000000U)
#define RGPIO_PCNP_NPE30_SHIFT                   (30U)
/*! NPE30 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE30_SHIFT)) & RGPIO_PCNP_NPE30_MASK)

#define RGPIO_PCNP_NPE31_MASK                    (0x80000000U)
#define RGPIO_PCNP_NPE31_SHIFT                   (31U)
/*! NPE31 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in non-privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for non-privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both privilege or non-privilege state.
 */
#define RGPIO_PCNP_NPE31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE31_SHIFT)) & RGPIO_PCNP_NPE31_MASK)
/*! @} */

/*! @name ICNP - Interrupt Control Non-Privilege */
/*! @{ */

#define RGPIO_ICNP_NPE0_MASK                     (0x1U)
#define RGPIO_ICNP_NPE0_SHIFT                    (0U)
/*! NPE0 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Only software in privilege state can configure a pin to use
 *       the corresponding interrupt/DMA request/trigger output or reconfigure a pin that is already configured to
 *       use the corresponding interrupt/DMA request/trigger output.
 *  0b1..The pin is configured for non-privilege access. Software in either privilege or non-privilege state can
 *       configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a pin that is
 *       already configured to use the corresponding interrupt/DMA request/trigger output.
 */
#define RGPIO_ICNP_NPE0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNP_NPE0_SHIFT)) & RGPIO_ICNP_NPE0_MASK)

#define RGPIO_ICNP_NPE1_MASK                     (0x2U)
#define RGPIO_ICNP_NPE1_SHIFT                    (1U)
/*! NPE1 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Only software in privilege state can configure a pin to use
 *       the corresponding interrupt/DMA request/trigger output or reconfigure a pin that is already configured to
 *       use the corresponding interrupt/DMA request/trigger output.
 *  0b1..The pin is configured for non-privilege access. Software in either privilege or non-privilege state can
 *       configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a pin that is
 *       already configured to use the corresponding interrupt/DMA request/trigger output.
 */
#define RGPIO_ICNP_NPE1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNP_NPE1_SHIFT)) & RGPIO_ICNP_NPE1_MASK)

#define RGPIO_ICNP_NPE2_MASK                     (0x4U)
#define RGPIO_ICNP_NPE2_SHIFT                    (2U)
/*! NPE2 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Only software in privilege state can configure a pin to use
 *       the corresponding interrupt/DMA request/trigger output or reconfigure a pin that is already configured to
 *       use the corresponding interrupt/DMA request/trigger output.
 *  0b1..The pin is configured for non-privilege access. Software in either privilege or non-privilege state can
 *       configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a pin that is
 *       already configured to use the corresponding interrupt/DMA request/trigger output.
 */
#define RGPIO_ICNP_NPE2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNP_NPE2_SHIFT)) & RGPIO_ICNP_NPE2_MASK)

#define RGPIO_ICNP_NPE3_MASK                     (0x8U)
#define RGPIO_ICNP_NPE3_SHIFT                    (3U)
/*! NPE3 - Non-Privilege Enable
 *  0b0..The pin is configured for privilege access. Only software in privilege state can configure a pin to use
 *       the corresponding interrupt/DMA request/trigger output or reconfigure a pin that is already configured to
 *       use the corresponding interrupt/DMA request/trigger output.
 *  0b1..The pin is configured for non-privilege access. Software in either privilege or non-privilege state can
 *       configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a pin that is
 *       already configured to use the corresponding interrupt/DMA request/trigger output.
 */
#define RGPIO_ICNP_NPE3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNP_NPE3_SHIFT)) & RGPIO_ICNP_NPE3_MASK)
/*! @} */

/*! @name PDOR - Port Data Output Register */
/*! @{ */

#define RGPIO_PDOR_PDO0_MASK                     (0x1U)
#define RGPIO_PDOR_PDO0_SHIFT                    (0U)
/*! PDO0 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO0_SHIFT)) & RGPIO_PDOR_PDO0_MASK)

#define RGPIO_PDOR_PDO1_MASK                     (0x2U)
#define RGPIO_PDOR_PDO1_SHIFT                    (1U)
/*! PDO1 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO1_SHIFT)) & RGPIO_PDOR_PDO1_MASK)

#define RGPIO_PDOR_PDO2_MASK                     (0x4U)
#define RGPIO_PDOR_PDO2_SHIFT                    (2U)
/*! PDO2 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO2_SHIFT)) & RGPIO_PDOR_PDO2_MASK)

#define RGPIO_PDOR_PDO3_MASK                     (0x8U)
#define RGPIO_PDOR_PDO3_SHIFT                    (3U)
/*! PDO3 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO3_SHIFT)) & RGPIO_PDOR_PDO3_MASK)

#define RGPIO_PDOR_PDO4_MASK                     (0x10U)
#define RGPIO_PDOR_PDO4_SHIFT                    (4U)
/*! PDO4 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO4_SHIFT)) & RGPIO_PDOR_PDO4_MASK)

#define RGPIO_PDOR_PDO5_MASK                     (0x20U)
#define RGPIO_PDOR_PDO5_SHIFT                    (5U)
/*! PDO5 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO5_SHIFT)) & RGPIO_PDOR_PDO5_MASK)

#define RGPIO_PDOR_PDO6_MASK                     (0x40U)
#define RGPIO_PDOR_PDO6_SHIFT                    (6U)
/*! PDO6 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO6_SHIFT)) & RGPIO_PDOR_PDO6_MASK)

#define RGPIO_PDOR_PDO7_MASK                     (0x80U)
#define RGPIO_PDOR_PDO7_SHIFT                    (7U)
/*! PDO7 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO7_SHIFT)) & RGPIO_PDOR_PDO7_MASK)

#define RGPIO_PDOR_PDO8_MASK                     (0x100U)
#define RGPIO_PDOR_PDO8_SHIFT                    (8U)
/*! PDO8 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO8_SHIFT)) & RGPIO_PDOR_PDO8_MASK)

#define RGPIO_PDOR_PDO9_MASK                     (0x200U)
#define RGPIO_PDOR_PDO9_SHIFT                    (9U)
/*! PDO9 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO9_SHIFT)) & RGPIO_PDOR_PDO9_MASK)

#define RGPIO_PDOR_PDO10_MASK                    (0x400U)
#define RGPIO_PDOR_PDO10_SHIFT                   (10U)
/*! PDO10 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO10_SHIFT)) & RGPIO_PDOR_PDO10_MASK)

#define RGPIO_PDOR_PDO11_MASK                    (0x800U)
#define RGPIO_PDOR_PDO11_SHIFT                   (11U)
/*! PDO11 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO11_SHIFT)) & RGPIO_PDOR_PDO11_MASK)

#define RGPIO_PDOR_PDO12_MASK                    (0x1000U)
#define RGPIO_PDOR_PDO12_SHIFT                   (12U)
/*! PDO12 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO12_SHIFT)) & RGPIO_PDOR_PDO12_MASK)

#define RGPIO_PDOR_PDO13_MASK                    (0x2000U)
#define RGPIO_PDOR_PDO13_SHIFT                   (13U)
/*! PDO13 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO13_SHIFT)) & RGPIO_PDOR_PDO13_MASK)

#define RGPIO_PDOR_PDO14_MASK                    (0x4000U)
#define RGPIO_PDOR_PDO14_SHIFT                   (14U)
/*! PDO14 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO14_SHIFT)) & RGPIO_PDOR_PDO14_MASK)

#define RGPIO_PDOR_PDO15_MASK                    (0x8000U)
#define RGPIO_PDOR_PDO15_SHIFT                   (15U)
/*! PDO15 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO15_SHIFT)) & RGPIO_PDOR_PDO15_MASK)

#define RGPIO_PDOR_PDO16_MASK                    (0x10000U)
#define RGPIO_PDOR_PDO16_SHIFT                   (16U)
/*! PDO16 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO16_SHIFT)) & RGPIO_PDOR_PDO16_MASK)

#define RGPIO_PDOR_PDO17_MASK                    (0x20000U)
#define RGPIO_PDOR_PDO17_SHIFT                   (17U)
/*! PDO17 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO17_SHIFT)) & RGPIO_PDOR_PDO17_MASK)

#define RGPIO_PDOR_PDO18_MASK                    (0x40000U)
#define RGPIO_PDOR_PDO18_SHIFT                   (18U)
/*! PDO18 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO18_SHIFT)) & RGPIO_PDOR_PDO18_MASK)

#define RGPIO_PDOR_PDO19_MASK                    (0x80000U)
#define RGPIO_PDOR_PDO19_SHIFT                   (19U)
/*! PDO19 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO19_SHIFT)) & RGPIO_PDOR_PDO19_MASK)

#define RGPIO_PDOR_PDO20_MASK                    (0x100000U)
#define RGPIO_PDOR_PDO20_SHIFT                   (20U)
/*! PDO20 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO20_SHIFT)) & RGPIO_PDOR_PDO20_MASK)

#define RGPIO_PDOR_PDO21_MASK                    (0x200000U)
#define RGPIO_PDOR_PDO21_SHIFT                   (21U)
/*! PDO21 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO21_SHIFT)) & RGPIO_PDOR_PDO21_MASK)

#define RGPIO_PDOR_PDO22_MASK                    (0x400000U)
#define RGPIO_PDOR_PDO22_SHIFT                   (22U)
/*! PDO22 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO22_SHIFT)) & RGPIO_PDOR_PDO22_MASK)

#define RGPIO_PDOR_PDO23_MASK                    (0x800000U)
#define RGPIO_PDOR_PDO23_SHIFT                   (23U)
/*! PDO23 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO23_SHIFT)) & RGPIO_PDOR_PDO23_MASK)

#define RGPIO_PDOR_PDO24_MASK                    (0x1000000U)
#define RGPIO_PDOR_PDO24_SHIFT                   (24U)
/*! PDO24 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO24_SHIFT)) & RGPIO_PDOR_PDO24_MASK)

#define RGPIO_PDOR_PDO25_MASK                    (0x2000000U)
#define RGPIO_PDOR_PDO25_SHIFT                   (25U)
/*! PDO25 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO25_SHIFT)) & RGPIO_PDOR_PDO25_MASK)

#define RGPIO_PDOR_PDO26_MASK                    (0x4000000U)
#define RGPIO_PDOR_PDO26_SHIFT                   (26U)
/*! PDO26 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO26_SHIFT)) & RGPIO_PDOR_PDO26_MASK)

#define RGPIO_PDOR_PDO27_MASK                    (0x8000000U)
#define RGPIO_PDOR_PDO27_SHIFT                   (27U)
/*! PDO27 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO27_SHIFT)) & RGPIO_PDOR_PDO27_MASK)

#define RGPIO_PDOR_PDO28_MASK                    (0x10000000U)
#define RGPIO_PDOR_PDO28_SHIFT                   (28U)
/*! PDO28 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO28_SHIFT)) & RGPIO_PDOR_PDO28_MASK)

#define RGPIO_PDOR_PDO29_MASK                    (0x20000000U)
#define RGPIO_PDOR_PDO29_SHIFT                   (29U)
/*! PDO29 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO29_SHIFT)) & RGPIO_PDOR_PDO29_MASK)

#define RGPIO_PDOR_PDO30_MASK                    (0x40000000U)
#define RGPIO_PDOR_PDO30_SHIFT                   (30U)
/*! PDO30 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO30_SHIFT)) & RGPIO_PDOR_PDO30_MASK)

#define RGPIO_PDOR_PDO31_MASK                    (0x80000000U)
#define RGPIO_PDOR_PDO31_SHIFT                   (31U)
/*! PDO31 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define RGPIO_PDOR_PDO31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO31_SHIFT)) & RGPIO_PDOR_PDO31_MASK)
/*! @} */

/*! @name PSOR - Port Set Output Register */
/*! @{ */

#define RGPIO_PSOR_PTSO0_MASK                    (0x1U)
#define RGPIO_PSOR_PTSO0_SHIFT                   (0U)
/*! PTSO0 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO0(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO0_SHIFT)) & RGPIO_PSOR_PTSO0_MASK)

#define RGPIO_PSOR_PTSO1_MASK                    (0x2U)
#define RGPIO_PSOR_PTSO1_SHIFT                   (1U)
/*! PTSO1 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO1(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO1_SHIFT)) & RGPIO_PSOR_PTSO1_MASK)

#define RGPIO_PSOR_PTSO2_MASK                    (0x4U)
#define RGPIO_PSOR_PTSO2_SHIFT                   (2U)
/*! PTSO2 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO2(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO2_SHIFT)) & RGPIO_PSOR_PTSO2_MASK)

#define RGPIO_PSOR_PTSO3_MASK                    (0x8U)
#define RGPIO_PSOR_PTSO3_SHIFT                   (3U)
/*! PTSO3 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO3(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO3_SHIFT)) & RGPIO_PSOR_PTSO3_MASK)

#define RGPIO_PSOR_PTSO4_MASK                    (0x10U)
#define RGPIO_PSOR_PTSO4_SHIFT                   (4U)
/*! PTSO4 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO4(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO4_SHIFT)) & RGPIO_PSOR_PTSO4_MASK)

#define RGPIO_PSOR_PTSO5_MASK                    (0x20U)
#define RGPIO_PSOR_PTSO5_SHIFT                   (5U)
/*! PTSO5 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO5(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO5_SHIFT)) & RGPIO_PSOR_PTSO5_MASK)

#define RGPIO_PSOR_PTSO6_MASK                    (0x40U)
#define RGPIO_PSOR_PTSO6_SHIFT                   (6U)
/*! PTSO6 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO6(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO6_SHIFT)) & RGPIO_PSOR_PTSO6_MASK)

#define RGPIO_PSOR_PTSO7_MASK                    (0x80U)
#define RGPIO_PSOR_PTSO7_SHIFT                   (7U)
/*! PTSO7 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO7(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO7_SHIFT)) & RGPIO_PSOR_PTSO7_MASK)

#define RGPIO_PSOR_PTSO8_MASK                    (0x100U)
#define RGPIO_PSOR_PTSO8_SHIFT                   (8U)
/*! PTSO8 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO8(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO8_SHIFT)) & RGPIO_PSOR_PTSO8_MASK)

#define RGPIO_PSOR_PTSO9_MASK                    (0x200U)
#define RGPIO_PSOR_PTSO9_SHIFT                   (9U)
/*! PTSO9 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO9(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO9_SHIFT)) & RGPIO_PSOR_PTSO9_MASK)

#define RGPIO_PSOR_PTSO10_MASK                   (0x400U)
#define RGPIO_PSOR_PTSO10_SHIFT                  (10U)
/*! PTSO10 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO10(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO10_SHIFT)) & RGPIO_PSOR_PTSO10_MASK)

#define RGPIO_PSOR_PTSO11_MASK                   (0x800U)
#define RGPIO_PSOR_PTSO11_SHIFT                  (11U)
/*! PTSO11 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO11(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO11_SHIFT)) & RGPIO_PSOR_PTSO11_MASK)

#define RGPIO_PSOR_PTSO12_MASK                   (0x1000U)
#define RGPIO_PSOR_PTSO12_SHIFT                  (12U)
/*! PTSO12 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO12(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO12_SHIFT)) & RGPIO_PSOR_PTSO12_MASK)

#define RGPIO_PSOR_PTSO13_MASK                   (0x2000U)
#define RGPIO_PSOR_PTSO13_SHIFT                  (13U)
/*! PTSO13 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO13(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO13_SHIFT)) & RGPIO_PSOR_PTSO13_MASK)

#define RGPIO_PSOR_PTSO14_MASK                   (0x4000U)
#define RGPIO_PSOR_PTSO14_SHIFT                  (14U)
/*! PTSO14 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO14(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO14_SHIFT)) & RGPIO_PSOR_PTSO14_MASK)

#define RGPIO_PSOR_PTSO15_MASK                   (0x8000U)
#define RGPIO_PSOR_PTSO15_SHIFT                  (15U)
/*! PTSO15 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO15(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO15_SHIFT)) & RGPIO_PSOR_PTSO15_MASK)

#define RGPIO_PSOR_PTSO16_MASK                   (0x10000U)
#define RGPIO_PSOR_PTSO16_SHIFT                  (16U)
/*! PTSO16 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO16(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO16_SHIFT)) & RGPIO_PSOR_PTSO16_MASK)

#define RGPIO_PSOR_PTSO17_MASK                   (0x20000U)
#define RGPIO_PSOR_PTSO17_SHIFT                  (17U)
/*! PTSO17 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO17(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO17_SHIFT)) & RGPIO_PSOR_PTSO17_MASK)

#define RGPIO_PSOR_PTSO18_MASK                   (0x40000U)
#define RGPIO_PSOR_PTSO18_SHIFT                  (18U)
/*! PTSO18 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO18(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO18_SHIFT)) & RGPIO_PSOR_PTSO18_MASK)

#define RGPIO_PSOR_PTSO19_MASK                   (0x80000U)
#define RGPIO_PSOR_PTSO19_SHIFT                  (19U)
/*! PTSO19 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO19(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO19_SHIFT)) & RGPIO_PSOR_PTSO19_MASK)

#define RGPIO_PSOR_PTSO20_MASK                   (0x100000U)
#define RGPIO_PSOR_PTSO20_SHIFT                  (20U)
/*! PTSO20 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO20(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO20_SHIFT)) & RGPIO_PSOR_PTSO20_MASK)

#define RGPIO_PSOR_PTSO21_MASK                   (0x200000U)
#define RGPIO_PSOR_PTSO21_SHIFT                  (21U)
/*! PTSO21 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO21(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO21_SHIFT)) & RGPIO_PSOR_PTSO21_MASK)

#define RGPIO_PSOR_PTSO22_MASK                   (0x400000U)
#define RGPIO_PSOR_PTSO22_SHIFT                  (22U)
/*! PTSO22 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO22(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO22_SHIFT)) & RGPIO_PSOR_PTSO22_MASK)

#define RGPIO_PSOR_PTSO23_MASK                   (0x800000U)
#define RGPIO_PSOR_PTSO23_SHIFT                  (23U)
/*! PTSO23 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO23(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO23_SHIFT)) & RGPIO_PSOR_PTSO23_MASK)

#define RGPIO_PSOR_PTSO24_MASK                   (0x1000000U)
#define RGPIO_PSOR_PTSO24_SHIFT                  (24U)
/*! PTSO24 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO24(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO24_SHIFT)) & RGPIO_PSOR_PTSO24_MASK)

#define RGPIO_PSOR_PTSO25_MASK                   (0x2000000U)
#define RGPIO_PSOR_PTSO25_SHIFT                  (25U)
/*! PTSO25 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO25(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO25_SHIFT)) & RGPIO_PSOR_PTSO25_MASK)

#define RGPIO_PSOR_PTSO26_MASK                   (0x4000000U)
#define RGPIO_PSOR_PTSO26_SHIFT                  (26U)
/*! PTSO26 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO26(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO26_SHIFT)) & RGPIO_PSOR_PTSO26_MASK)

#define RGPIO_PSOR_PTSO27_MASK                   (0x8000000U)
#define RGPIO_PSOR_PTSO27_SHIFT                  (27U)
/*! PTSO27 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO27(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO27_SHIFT)) & RGPIO_PSOR_PTSO27_MASK)

#define RGPIO_PSOR_PTSO28_MASK                   (0x10000000U)
#define RGPIO_PSOR_PTSO28_SHIFT                  (28U)
/*! PTSO28 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO28(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO28_SHIFT)) & RGPIO_PSOR_PTSO28_MASK)

#define RGPIO_PSOR_PTSO29_MASK                   (0x20000000U)
#define RGPIO_PSOR_PTSO29_SHIFT                  (29U)
/*! PTSO29 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO29(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO29_SHIFT)) & RGPIO_PSOR_PTSO29_MASK)

#define RGPIO_PSOR_PTSO30_MASK                   (0x40000000U)
#define RGPIO_PSOR_PTSO30_SHIFT                  (30U)
/*! PTSO30 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO30(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO30_SHIFT)) & RGPIO_PSOR_PTSO30_MASK)

#define RGPIO_PSOR_PTSO31_MASK                   (0x80000000U)
#define RGPIO_PSOR_PTSO31_SHIFT                  (31U)
/*! PTSO31 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define RGPIO_PSOR_PTSO31(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO31_SHIFT)) & RGPIO_PSOR_PTSO31_MASK)
/*! @} */

/*! @name PCOR - Port Clear Output Register */
/*! @{ */

#define RGPIO_PCOR_PTCO0_MASK                    (0x1U)
#define RGPIO_PCOR_PTCO0_SHIFT                   (0U)
/*! PTCO0 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO0(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO0_SHIFT)) & RGPIO_PCOR_PTCO0_MASK)

#define RGPIO_PCOR_PTCO1_MASK                    (0x2U)
#define RGPIO_PCOR_PTCO1_SHIFT                   (1U)
/*! PTCO1 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO1(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO1_SHIFT)) & RGPIO_PCOR_PTCO1_MASK)

#define RGPIO_PCOR_PTCO2_MASK                    (0x4U)
#define RGPIO_PCOR_PTCO2_SHIFT                   (2U)
/*! PTCO2 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO2(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO2_SHIFT)) & RGPIO_PCOR_PTCO2_MASK)

#define RGPIO_PCOR_PTCO3_MASK                    (0x8U)
#define RGPIO_PCOR_PTCO3_SHIFT                   (3U)
/*! PTCO3 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO3(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO3_SHIFT)) & RGPIO_PCOR_PTCO3_MASK)

#define RGPIO_PCOR_PTCO4_MASK                    (0x10U)
#define RGPIO_PCOR_PTCO4_SHIFT                   (4U)
/*! PTCO4 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO4(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO4_SHIFT)) & RGPIO_PCOR_PTCO4_MASK)

#define RGPIO_PCOR_PTCO5_MASK                    (0x20U)
#define RGPIO_PCOR_PTCO5_SHIFT                   (5U)
/*! PTCO5 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO5(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO5_SHIFT)) & RGPIO_PCOR_PTCO5_MASK)

#define RGPIO_PCOR_PTCO6_MASK                    (0x40U)
#define RGPIO_PCOR_PTCO6_SHIFT                   (6U)
/*! PTCO6 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO6(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO6_SHIFT)) & RGPIO_PCOR_PTCO6_MASK)

#define RGPIO_PCOR_PTCO7_MASK                    (0x80U)
#define RGPIO_PCOR_PTCO7_SHIFT                   (7U)
/*! PTCO7 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO7(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO7_SHIFT)) & RGPIO_PCOR_PTCO7_MASK)

#define RGPIO_PCOR_PTCO8_MASK                    (0x100U)
#define RGPIO_PCOR_PTCO8_SHIFT                   (8U)
/*! PTCO8 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO8(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO8_SHIFT)) & RGPIO_PCOR_PTCO8_MASK)

#define RGPIO_PCOR_PTCO9_MASK                    (0x200U)
#define RGPIO_PCOR_PTCO9_SHIFT                   (9U)
/*! PTCO9 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO9(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO9_SHIFT)) & RGPIO_PCOR_PTCO9_MASK)

#define RGPIO_PCOR_PTCO10_MASK                   (0x400U)
#define RGPIO_PCOR_PTCO10_SHIFT                  (10U)
/*! PTCO10 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO10(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO10_SHIFT)) & RGPIO_PCOR_PTCO10_MASK)

#define RGPIO_PCOR_PTCO11_MASK                   (0x800U)
#define RGPIO_PCOR_PTCO11_SHIFT                  (11U)
/*! PTCO11 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO11(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO11_SHIFT)) & RGPIO_PCOR_PTCO11_MASK)

#define RGPIO_PCOR_PTCO12_MASK                   (0x1000U)
#define RGPIO_PCOR_PTCO12_SHIFT                  (12U)
/*! PTCO12 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO12(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO12_SHIFT)) & RGPIO_PCOR_PTCO12_MASK)

#define RGPIO_PCOR_PTCO13_MASK                   (0x2000U)
#define RGPIO_PCOR_PTCO13_SHIFT                  (13U)
/*! PTCO13 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO13(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO13_SHIFT)) & RGPIO_PCOR_PTCO13_MASK)

#define RGPIO_PCOR_PTCO14_MASK                   (0x4000U)
#define RGPIO_PCOR_PTCO14_SHIFT                  (14U)
/*! PTCO14 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO14(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO14_SHIFT)) & RGPIO_PCOR_PTCO14_MASK)

#define RGPIO_PCOR_PTCO15_MASK                   (0x8000U)
#define RGPIO_PCOR_PTCO15_SHIFT                  (15U)
/*! PTCO15 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO15(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO15_SHIFT)) & RGPIO_PCOR_PTCO15_MASK)

#define RGPIO_PCOR_PTCO16_MASK                   (0x10000U)
#define RGPIO_PCOR_PTCO16_SHIFT                  (16U)
/*! PTCO16 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO16(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO16_SHIFT)) & RGPIO_PCOR_PTCO16_MASK)

#define RGPIO_PCOR_PTCO17_MASK                   (0x20000U)
#define RGPIO_PCOR_PTCO17_SHIFT                  (17U)
/*! PTCO17 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO17(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO17_SHIFT)) & RGPIO_PCOR_PTCO17_MASK)

#define RGPIO_PCOR_PTCO18_MASK                   (0x40000U)
#define RGPIO_PCOR_PTCO18_SHIFT                  (18U)
/*! PTCO18 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO18(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO18_SHIFT)) & RGPIO_PCOR_PTCO18_MASK)

#define RGPIO_PCOR_PTCO19_MASK                   (0x80000U)
#define RGPIO_PCOR_PTCO19_SHIFT                  (19U)
/*! PTCO19 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO19(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO19_SHIFT)) & RGPIO_PCOR_PTCO19_MASK)

#define RGPIO_PCOR_PTCO20_MASK                   (0x100000U)
#define RGPIO_PCOR_PTCO20_SHIFT                  (20U)
/*! PTCO20 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO20(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO20_SHIFT)) & RGPIO_PCOR_PTCO20_MASK)

#define RGPIO_PCOR_PTCO21_MASK                   (0x200000U)
#define RGPIO_PCOR_PTCO21_SHIFT                  (21U)
/*! PTCO21 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO21(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO21_SHIFT)) & RGPIO_PCOR_PTCO21_MASK)

#define RGPIO_PCOR_PTCO22_MASK                   (0x400000U)
#define RGPIO_PCOR_PTCO22_SHIFT                  (22U)
/*! PTCO22 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO22(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO22_SHIFT)) & RGPIO_PCOR_PTCO22_MASK)

#define RGPIO_PCOR_PTCO23_MASK                   (0x800000U)
#define RGPIO_PCOR_PTCO23_SHIFT                  (23U)
/*! PTCO23 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO23(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO23_SHIFT)) & RGPIO_PCOR_PTCO23_MASK)

#define RGPIO_PCOR_PTCO24_MASK                   (0x1000000U)
#define RGPIO_PCOR_PTCO24_SHIFT                  (24U)
/*! PTCO24 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO24(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO24_SHIFT)) & RGPIO_PCOR_PTCO24_MASK)

#define RGPIO_PCOR_PTCO25_MASK                   (0x2000000U)
#define RGPIO_PCOR_PTCO25_SHIFT                  (25U)
/*! PTCO25 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO25(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO25_SHIFT)) & RGPIO_PCOR_PTCO25_MASK)

#define RGPIO_PCOR_PTCO26_MASK                   (0x4000000U)
#define RGPIO_PCOR_PTCO26_SHIFT                  (26U)
/*! PTCO26 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO26(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO26_SHIFT)) & RGPIO_PCOR_PTCO26_MASK)

#define RGPIO_PCOR_PTCO27_MASK                   (0x8000000U)
#define RGPIO_PCOR_PTCO27_SHIFT                  (27U)
/*! PTCO27 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO27(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO27_SHIFT)) & RGPIO_PCOR_PTCO27_MASK)

#define RGPIO_PCOR_PTCO28_MASK                   (0x10000000U)
#define RGPIO_PCOR_PTCO28_SHIFT                  (28U)
/*! PTCO28 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO28(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO28_SHIFT)) & RGPIO_PCOR_PTCO28_MASK)

#define RGPIO_PCOR_PTCO29_MASK                   (0x20000000U)
#define RGPIO_PCOR_PTCO29_SHIFT                  (29U)
/*! PTCO29 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO29(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO29_SHIFT)) & RGPIO_PCOR_PTCO29_MASK)

#define RGPIO_PCOR_PTCO30_MASK                   (0x40000000U)
#define RGPIO_PCOR_PTCO30_SHIFT                  (30U)
/*! PTCO30 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO30(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO30_SHIFT)) & RGPIO_PCOR_PTCO30_MASK)

#define RGPIO_PCOR_PTCO31_MASK                   (0x80000000U)
#define RGPIO_PCOR_PTCO31_SHIFT                  (31U)
/*! PTCO31 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define RGPIO_PCOR_PTCO31(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO31_SHIFT)) & RGPIO_PCOR_PTCO31_MASK)
/*! @} */

/*! @name PTOR - Port Toggle Output Register */
/*! @{ */

#define RGPIO_PTOR_PTTO0_MASK                    (0x1U)
#define RGPIO_PTOR_PTTO0_SHIFT                   (0U)
/*! PTTO0 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO0(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO0_SHIFT)) & RGPIO_PTOR_PTTO0_MASK)

#define RGPIO_PTOR_PTTO1_MASK                    (0x2U)
#define RGPIO_PTOR_PTTO1_SHIFT                   (1U)
/*! PTTO1 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO1(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO1_SHIFT)) & RGPIO_PTOR_PTTO1_MASK)

#define RGPIO_PTOR_PTTO2_MASK                    (0x4U)
#define RGPIO_PTOR_PTTO2_SHIFT                   (2U)
/*! PTTO2 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO2(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO2_SHIFT)) & RGPIO_PTOR_PTTO2_MASK)

#define RGPIO_PTOR_PTTO3_MASK                    (0x8U)
#define RGPIO_PTOR_PTTO3_SHIFT                   (3U)
/*! PTTO3 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO3(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO3_SHIFT)) & RGPIO_PTOR_PTTO3_MASK)

#define RGPIO_PTOR_PTTO4_MASK                    (0x10U)
#define RGPIO_PTOR_PTTO4_SHIFT                   (4U)
/*! PTTO4 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO4(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO4_SHIFT)) & RGPIO_PTOR_PTTO4_MASK)

#define RGPIO_PTOR_PTTO5_MASK                    (0x20U)
#define RGPIO_PTOR_PTTO5_SHIFT                   (5U)
/*! PTTO5 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO5(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO5_SHIFT)) & RGPIO_PTOR_PTTO5_MASK)

#define RGPIO_PTOR_PTTO6_MASK                    (0x40U)
#define RGPIO_PTOR_PTTO6_SHIFT                   (6U)
/*! PTTO6 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO6(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO6_SHIFT)) & RGPIO_PTOR_PTTO6_MASK)

#define RGPIO_PTOR_PTTO7_MASK                    (0x80U)
#define RGPIO_PTOR_PTTO7_SHIFT                   (7U)
/*! PTTO7 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO7(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO7_SHIFT)) & RGPIO_PTOR_PTTO7_MASK)

#define RGPIO_PTOR_PTTO8_MASK                    (0x100U)
#define RGPIO_PTOR_PTTO8_SHIFT                   (8U)
/*! PTTO8 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO8(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO8_SHIFT)) & RGPIO_PTOR_PTTO8_MASK)

#define RGPIO_PTOR_PTTO9_MASK                    (0x200U)
#define RGPIO_PTOR_PTTO9_SHIFT                   (9U)
/*! PTTO9 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO9(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO9_SHIFT)) & RGPIO_PTOR_PTTO9_MASK)

#define RGPIO_PTOR_PTTO10_MASK                   (0x400U)
#define RGPIO_PTOR_PTTO10_SHIFT                  (10U)
/*! PTTO10 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO10(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO10_SHIFT)) & RGPIO_PTOR_PTTO10_MASK)

#define RGPIO_PTOR_PTTO11_MASK                   (0x800U)
#define RGPIO_PTOR_PTTO11_SHIFT                  (11U)
/*! PTTO11 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO11(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO11_SHIFT)) & RGPIO_PTOR_PTTO11_MASK)

#define RGPIO_PTOR_PTTO12_MASK                   (0x1000U)
#define RGPIO_PTOR_PTTO12_SHIFT                  (12U)
/*! PTTO12 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO12(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO12_SHIFT)) & RGPIO_PTOR_PTTO12_MASK)

#define RGPIO_PTOR_PTTO13_MASK                   (0x2000U)
#define RGPIO_PTOR_PTTO13_SHIFT                  (13U)
/*! PTTO13 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO13(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO13_SHIFT)) & RGPIO_PTOR_PTTO13_MASK)

#define RGPIO_PTOR_PTTO14_MASK                   (0x4000U)
#define RGPIO_PTOR_PTTO14_SHIFT                  (14U)
/*! PTTO14 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO14(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO14_SHIFT)) & RGPIO_PTOR_PTTO14_MASK)

#define RGPIO_PTOR_PTTO15_MASK                   (0x8000U)
#define RGPIO_PTOR_PTTO15_SHIFT                  (15U)
/*! PTTO15 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO15(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO15_SHIFT)) & RGPIO_PTOR_PTTO15_MASK)

#define RGPIO_PTOR_PTTO16_MASK                   (0x10000U)
#define RGPIO_PTOR_PTTO16_SHIFT                  (16U)
/*! PTTO16 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO16(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO16_SHIFT)) & RGPIO_PTOR_PTTO16_MASK)

#define RGPIO_PTOR_PTTO17_MASK                   (0x20000U)
#define RGPIO_PTOR_PTTO17_SHIFT                  (17U)
/*! PTTO17 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO17(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO17_SHIFT)) & RGPIO_PTOR_PTTO17_MASK)

#define RGPIO_PTOR_PTTO18_MASK                   (0x40000U)
#define RGPIO_PTOR_PTTO18_SHIFT                  (18U)
/*! PTTO18 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO18(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO18_SHIFT)) & RGPIO_PTOR_PTTO18_MASK)

#define RGPIO_PTOR_PTTO19_MASK                   (0x80000U)
#define RGPIO_PTOR_PTTO19_SHIFT                  (19U)
/*! PTTO19 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO19(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO19_SHIFT)) & RGPIO_PTOR_PTTO19_MASK)

#define RGPIO_PTOR_PTTO20_MASK                   (0x100000U)
#define RGPIO_PTOR_PTTO20_SHIFT                  (20U)
/*! PTTO20 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO20(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO20_SHIFT)) & RGPIO_PTOR_PTTO20_MASK)

#define RGPIO_PTOR_PTTO21_MASK                   (0x200000U)
#define RGPIO_PTOR_PTTO21_SHIFT                  (21U)
/*! PTTO21 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO21(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO21_SHIFT)) & RGPIO_PTOR_PTTO21_MASK)

#define RGPIO_PTOR_PTTO22_MASK                   (0x400000U)
#define RGPIO_PTOR_PTTO22_SHIFT                  (22U)
/*! PTTO22 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO22(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO22_SHIFT)) & RGPIO_PTOR_PTTO22_MASK)

#define RGPIO_PTOR_PTTO23_MASK                   (0x800000U)
#define RGPIO_PTOR_PTTO23_SHIFT                  (23U)
/*! PTTO23 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO23(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO23_SHIFT)) & RGPIO_PTOR_PTTO23_MASK)

#define RGPIO_PTOR_PTTO24_MASK                   (0x1000000U)
#define RGPIO_PTOR_PTTO24_SHIFT                  (24U)
/*! PTTO24 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO24(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO24_SHIFT)) & RGPIO_PTOR_PTTO24_MASK)

#define RGPIO_PTOR_PTTO25_MASK                   (0x2000000U)
#define RGPIO_PTOR_PTTO25_SHIFT                  (25U)
/*! PTTO25 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO25(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO25_SHIFT)) & RGPIO_PTOR_PTTO25_MASK)

#define RGPIO_PTOR_PTTO26_MASK                   (0x4000000U)
#define RGPIO_PTOR_PTTO26_SHIFT                  (26U)
/*! PTTO26 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO26(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO26_SHIFT)) & RGPIO_PTOR_PTTO26_MASK)

#define RGPIO_PTOR_PTTO27_MASK                   (0x8000000U)
#define RGPIO_PTOR_PTTO27_SHIFT                  (27U)
/*! PTTO27 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO27(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO27_SHIFT)) & RGPIO_PTOR_PTTO27_MASK)

#define RGPIO_PTOR_PTTO28_MASK                   (0x10000000U)
#define RGPIO_PTOR_PTTO28_SHIFT                  (28U)
/*! PTTO28 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO28(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO28_SHIFT)) & RGPIO_PTOR_PTTO28_MASK)

#define RGPIO_PTOR_PTTO29_MASK                   (0x20000000U)
#define RGPIO_PTOR_PTTO29_SHIFT                  (29U)
/*! PTTO29 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO29(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO29_SHIFT)) & RGPIO_PTOR_PTTO29_MASK)

#define RGPIO_PTOR_PTTO30_MASK                   (0x40000000U)
#define RGPIO_PTOR_PTTO30_SHIFT                  (30U)
/*! PTTO30 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO30(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO30_SHIFT)) & RGPIO_PTOR_PTTO30_MASK)

#define RGPIO_PTOR_PTTO31_MASK                   (0x80000000U)
#define RGPIO_PTOR_PTTO31_SHIFT                  (31U)
/*! PTTO31 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its existing logic state.
 */
#define RGPIO_PTOR_PTTO31(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO31_SHIFT)) & RGPIO_PTOR_PTTO31_MASK)
/*! @} */

/*! @name PDIR - Port Data Input Register */
/*! @{ */

#define RGPIO_PDIR_PDI0_MASK                     (0x1U)
#define RGPIO_PDIR_PDI0_SHIFT                    (0U)
/*! PDI0 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI0_SHIFT)) & RGPIO_PDIR_PDI0_MASK)

#define RGPIO_PDIR_PDI1_MASK                     (0x2U)
#define RGPIO_PDIR_PDI1_SHIFT                    (1U)
/*! PDI1 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI1_SHIFT)) & RGPIO_PDIR_PDI1_MASK)

#define RGPIO_PDIR_PDI2_MASK                     (0x4U)
#define RGPIO_PDIR_PDI2_SHIFT                    (2U)
/*! PDI2 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI2_SHIFT)) & RGPIO_PDIR_PDI2_MASK)

#define RGPIO_PDIR_PDI3_MASK                     (0x8U)
#define RGPIO_PDIR_PDI3_SHIFT                    (3U)
/*! PDI3 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI3_SHIFT)) & RGPIO_PDIR_PDI3_MASK)

#define RGPIO_PDIR_PDI4_MASK                     (0x10U)
#define RGPIO_PDIR_PDI4_SHIFT                    (4U)
/*! PDI4 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI4_SHIFT)) & RGPIO_PDIR_PDI4_MASK)

#define RGPIO_PDIR_PDI5_MASK                     (0x20U)
#define RGPIO_PDIR_PDI5_SHIFT                    (5U)
/*! PDI5 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI5_SHIFT)) & RGPIO_PDIR_PDI5_MASK)

#define RGPIO_PDIR_PDI6_MASK                     (0x40U)
#define RGPIO_PDIR_PDI6_SHIFT                    (6U)
/*! PDI6 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI6_SHIFT)) & RGPIO_PDIR_PDI6_MASK)

#define RGPIO_PDIR_PDI7_MASK                     (0x80U)
#define RGPIO_PDIR_PDI7_SHIFT                    (7U)
/*! PDI7 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI7_SHIFT)) & RGPIO_PDIR_PDI7_MASK)

#define RGPIO_PDIR_PDI8_MASK                     (0x100U)
#define RGPIO_PDIR_PDI8_SHIFT                    (8U)
/*! PDI8 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI8_SHIFT)) & RGPIO_PDIR_PDI8_MASK)

#define RGPIO_PDIR_PDI9_MASK                     (0x200U)
#define RGPIO_PDIR_PDI9_SHIFT                    (9U)
/*! PDI9 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI9_SHIFT)) & RGPIO_PDIR_PDI9_MASK)

#define RGPIO_PDIR_PDI10_MASK                    (0x400U)
#define RGPIO_PDIR_PDI10_SHIFT                   (10U)
/*! PDI10 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI10_SHIFT)) & RGPIO_PDIR_PDI10_MASK)

#define RGPIO_PDIR_PDI11_MASK                    (0x800U)
#define RGPIO_PDIR_PDI11_SHIFT                   (11U)
/*! PDI11 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI11_SHIFT)) & RGPIO_PDIR_PDI11_MASK)

#define RGPIO_PDIR_PDI12_MASK                    (0x1000U)
#define RGPIO_PDIR_PDI12_SHIFT                   (12U)
/*! PDI12 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI12_SHIFT)) & RGPIO_PDIR_PDI12_MASK)

#define RGPIO_PDIR_PDI13_MASK                    (0x2000U)
#define RGPIO_PDIR_PDI13_SHIFT                   (13U)
/*! PDI13 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI13_SHIFT)) & RGPIO_PDIR_PDI13_MASK)

#define RGPIO_PDIR_PDI14_MASK                    (0x4000U)
#define RGPIO_PDIR_PDI14_SHIFT                   (14U)
/*! PDI14 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI14_SHIFT)) & RGPIO_PDIR_PDI14_MASK)

#define RGPIO_PDIR_PDI15_MASK                    (0x8000U)
#define RGPIO_PDIR_PDI15_SHIFT                   (15U)
/*! PDI15 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI15_SHIFT)) & RGPIO_PDIR_PDI15_MASK)

#define RGPIO_PDIR_PDI16_MASK                    (0x10000U)
#define RGPIO_PDIR_PDI16_SHIFT                   (16U)
/*! PDI16 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI16_SHIFT)) & RGPIO_PDIR_PDI16_MASK)

#define RGPIO_PDIR_PDI17_MASK                    (0x20000U)
#define RGPIO_PDIR_PDI17_SHIFT                   (17U)
/*! PDI17 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI17_SHIFT)) & RGPIO_PDIR_PDI17_MASK)

#define RGPIO_PDIR_PDI18_MASK                    (0x40000U)
#define RGPIO_PDIR_PDI18_SHIFT                   (18U)
/*! PDI18 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI18_SHIFT)) & RGPIO_PDIR_PDI18_MASK)

#define RGPIO_PDIR_PDI19_MASK                    (0x80000U)
#define RGPIO_PDIR_PDI19_SHIFT                   (19U)
/*! PDI19 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI19_SHIFT)) & RGPIO_PDIR_PDI19_MASK)

#define RGPIO_PDIR_PDI20_MASK                    (0x100000U)
#define RGPIO_PDIR_PDI20_SHIFT                   (20U)
/*! PDI20 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI20_SHIFT)) & RGPIO_PDIR_PDI20_MASK)

#define RGPIO_PDIR_PDI21_MASK                    (0x200000U)
#define RGPIO_PDIR_PDI21_SHIFT                   (21U)
/*! PDI21 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI21_SHIFT)) & RGPIO_PDIR_PDI21_MASK)

#define RGPIO_PDIR_PDI22_MASK                    (0x400000U)
#define RGPIO_PDIR_PDI22_SHIFT                   (22U)
/*! PDI22 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI22_SHIFT)) & RGPIO_PDIR_PDI22_MASK)

#define RGPIO_PDIR_PDI23_MASK                    (0x800000U)
#define RGPIO_PDIR_PDI23_SHIFT                   (23U)
/*! PDI23 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI23_SHIFT)) & RGPIO_PDIR_PDI23_MASK)

#define RGPIO_PDIR_PDI24_MASK                    (0x1000000U)
#define RGPIO_PDIR_PDI24_SHIFT                   (24U)
/*! PDI24 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI24_SHIFT)) & RGPIO_PDIR_PDI24_MASK)

#define RGPIO_PDIR_PDI25_MASK                    (0x2000000U)
#define RGPIO_PDIR_PDI25_SHIFT                   (25U)
/*! PDI25 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI25_SHIFT)) & RGPIO_PDIR_PDI25_MASK)

#define RGPIO_PDIR_PDI26_MASK                    (0x4000000U)
#define RGPIO_PDIR_PDI26_SHIFT                   (26U)
/*! PDI26 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI26_SHIFT)) & RGPIO_PDIR_PDI26_MASK)

#define RGPIO_PDIR_PDI27_MASK                    (0x8000000U)
#define RGPIO_PDIR_PDI27_SHIFT                   (27U)
/*! PDI27 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI27_SHIFT)) & RGPIO_PDIR_PDI27_MASK)

#define RGPIO_PDIR_PDI28_MASK                    (0x10000000U)
#define RGPIO_PDIR_PDI28_SHIFT                   (28U)
/*! PDI28 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI28_SHIFT)) & RGPIO_PDIR_PDI28_MASK)

#define RGPIO_PDIR_PDI29_MASK                    (0x20000000U)
#define RGPIO_PDIR_PDI29_SHIFT                   (29U)
/*! PDI29 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI29_SHIFT)) & RGPIO_PDIR_PDI29_MASK)

#define RGPIO_PDIR_PDI30_MASK                    (0x40000000U)
#define RGPIO_PDIR_PDI30_SHIFT                   (30U)
/*! PDI30 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI30_SHIFT)) & RGPIO_PDIR_PDI30_MASK)

#define RGPIO_PDIR_PDI31_MASK                    (0x80000000U)
#define RGPIO_PDIR_PDI31_SHIFT                   (31U)
/*! PDI31 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define RGPIO_PDIR_PDI31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI31_SHIFT)) & RGPIO_PDIR_PDI31_MASK)
/*! @} */

/*! @name PDDR - Port Data Direction Register */
/*! @{ */

#define RGPIO_PDDR_PDD0_MASK                     (0x1U)
#define RGPIO_PDDR_PDD0_SHIFT                    (0U)
/*! PDD0 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD0_SHIFT)) & RGPIO_PDDR_PDD0_MASK)

#define RGPIO_PDDR_PDD1_MASK                     (0x2U)
#define RGPIO_PDDR_PDD1_SHIFT                    (1U)
/*! PDD1 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD1_SHIFT)) & RGPIO_PDDR_PDD1_MASK)

#define RGPIO_PDDR_PDD2_MASK                     (0x4U)
#define RGPIO_PDDR_PDD2_SHIFT                    (2U)
/*! PDD2 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD2_SHIFT)) & RGPIO_PDDR_PDD2_MASK)

#define RGPIO_PDDR_PDD3_MASK                     (0x8U)
#define RGPIO_PDDR_PDD3_SHIFT                    (3U)
/*! PDD3 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD3_SHIFT)) & RGPIO_PDDR_PDD3_MASK)

#define RGPIO_PDDR_PDD4_MASK                     (0x10U)
#define RGPIO_PDDR_PDD4_SHIFT                    (4U)
/*! PDD4 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD4_SHIFT)) & RGPIO_PDDR_PDD4_MASK)

#define RGPIO_PDDR_PDD5_MASK                     (0x20U)
#define RGPIO_PDDR_PDD5_SHIFT                    (5U)
/*! PDD5 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD5_SHIFT)) & RGPIO_PDDR_PDD5_MASK)

#define RGPIO_PDDR_PDD6_MASK                     (0x40U)
#define RGPIO_PDDR_PDD6_SHIFT                    (6U)
/*! PDD6 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD6_SHIFT)) & RGPIO_PDDR_PDD6_MASK)

#define RGPIO_PDDR_PDD7_MASK                     (0x80U)
#define RGPIO_PDDR_PDD7_SHIFT                    (7U)
/*! PDD7 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD7_SHIFT)) & RGPIO_PDDR_PDD7_MASK)

#define RGPIO_PDDR_PDD8_MASK                     (0x100U)
#define RGPIO_PDDR_PDD8_SHIFT                    (8U)
/*! PDD8 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD8_SHIFT)) & RGPIO_PDDR_PDD8_MASK)

#define RGPIO_PDDR_PDD9_MASK                     (0x200U)
#define RGPIO_PDDR_PDD9_SHIFT                    (9U)
/*! PDD9 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD9_SHIFT)) & RGPIO_PDDR_PDD9_MASK)

#define RGPIO_PDDR_PDD10_MASK                    (0x400U)
#define RGPIO_PDDR_PDD10_SHIFT                   (10U)
/*! PDD10 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD10_SHIFT)) & RGPIO_PDDR_PDD10_MASK)

#define RGPIO_PDDR_PDD11_MASK                    (0x800U)
#define RGPIO_PDDR_PDD11_SHIFT                   (11U)
/*! PDD11 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD11_SHIFT)) & RGPIO_PDDR_PDD11_MASK)

#define RGPIO_PDDR_PDD12_MASK                    (0x1000U)
#define RGPIO_PDDR_PDD12_SHIFT                   (12U)
/*! PDD12 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD12_SHIFT)) & RGPIO_PDDR_PDD12_MASK)

#define RGPIO_PDDR_PDD13_MASK                    (0x2000U)
#define RGPIO_PDDR_PDD13_SHIFT                   (13U)
/*! PDD13 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD13_SHIFT)) & RGPIO_PDDR_PDD13_MASK)

#define RGPIO_PDDR_PDD14_MASK                    (0x4000U)
#define RGPIO_PDDR_PDD14_SHIFT                   (14U)
/*! PDD14 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD14_SHIFT)) & RGPIO_PDDR_PDD14_MASK)

#define RGPIO_PDDR_PDD15_MASK                    (0x8000U)
#define RGPIO_PDDR_PDD15_SHIFT                   (15U)
/*! PDD15 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD15_SHIFT)) & RGPIO_PDDR_PDD15_MASK)

#define RGPIO_PDDR_PDD16_MASK                    (0x10000U)
#define RGPIO_PDDR_PDD16_SHIFT                   (16U)
/*! PDD16 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD16_SHIFT)) & RGPIO_PDDR_PDD16_MASK)

#define RGPIO_PDDR_PDD17_MASK                    (0x20000U)
#define RGPIO_PDDR_PDD17_SHIFT                   (17U)
/*! PDD17 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD17_SHIFT)) & RGPIO_PDDR_PDD17_MASK)

#define RGPIO_PDDR_PDD18_MASK                    (0x40000U)
#define RGPIO_PDDR_PDD18_SHIFT                   (18U)
/*! PDD18 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD18_SHIFT)) & RGPIO_PDDR_PDD18_MASK)

#define RGPIO_PDDR_PDD19_MASK                    (0x80000U)
#define RGPIO_PDDR_PDD19_SHIFT                   (19U)
/*! PDD19 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD19_SHIFT)) & RGPIO_PDDR_PDD19_MASK)

#define RGPIO_PDDR_PDD20_MASK                    (0x100000U)
#define RGPIO_PDDR_PDD20_SHIFT                   (20U)
/*! PDD20 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD20_SHIFT)) & RGPIO_PDDR_PDD20_MASK)

#define RGPIO_PDDR_PDD21_MASK                    (0x200000U)
#define RGPIO_PDDR_PDD21_SHIFT                   (21U)
/*! PDD21 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD21_SHIFT)) & RGPIO_PDDR_PDD21_MASK)

#define RGPIO_PDDR_PDD22_MASK                    (0x400000U)
#define RGPIO_PDDR_PDD22_SHIFT                   (22U)
/*! PDD22 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD22_SHIFT)) & RGPIO_PDDR_PDD22_MASK)

#define RGPIO_PDDR_PDD23_MASK                    (0x800000U)
#define RGPIO_PDDR_PDD23_SHIFT                   (23U)
/*! PDD23 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD23_SHIFT)) & RGPIO_PDDR_PDD23_MASK)

#define RGPIO_PDDR_PDD24_MASK                    (0x1000000U)
#define RGPIO_PDDR_PDD24_SHIFT                   (24U)
/*! PDD24 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD24_SHIFT)) & RGPIO_PDDR_PDD24_MASK)

#define RGPIO_PDDR_PDD25_MASK                    (0x2000000U)
#define RGPIO_PDDR_PDD25_SHIFT                   (25U)
/*! PDD25 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD25_SHIFT)) & RGPIO_PDDR_PDD25_MASK)

#define RGPIO_PDDR_PDD26_MASK                    (0x4000000U)
#define RGPIO_PDDR_PDD26_SHIFT                   (26U)
/*! PDD26 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD26_SHIFT)) & RGPIO_PDDR_PDD26_MASK)

#define RGPIO_PDDR_PDD27_MASK                    (0x8000000U)
#define RGPIO_PDDR_PDD27_SHIFT                   (27U)
/*! PDD27 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD27_SHIFT)) & RGPIO_PDDR_PDD27_MASK)

#define RGPIO_PDDR_PDD28_MASK                    (0x10000000U)
#define RGPIO_PDDR_PDD28_SHIFT                   (28U)
/*! PDD28 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD28_SHIFT)) & RGPIO_PDDR_PDD28_MASK)

#define RGPIO_PDDR_PDD29_MASK                    (0x20000000U)
#define RGPIO_PDDR_PDD29_SHIFT                   (29U)
/*! PDD29 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD29_SHIFT)) & RGPIO_PDDR_PDD29_MASK)

#define RGPIO_PDDR_PDD30_MASK                    (0x40000000U)
#define RGPIO_PDDR_PDD30_SHIFT                   (30U)
/*! PDD30 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD30_SHIFT)) & RGPIO_PDDR_PDD30_MASK)

#define RGPIO_PDDR_PDD31_MASK                    (0x80000000U)
#define RGPIO_PDDR_PDD31_SHIFT                   (31U)
/*! PDD31 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input, for the GPIO function.
 *  0b1..Pin is configured as general-purpose output, for the GPIO function.
 */
#define RGPIO_PDDR_PDD31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD31_SHIFT)) & RGPIO_PDDR_PDD31_MASK)
/*! @} */

/*! @name PIDR - Port Input Disable Register */
/*! @{ */

#define RGPIO_PIDR_PID0_MASK                     (0x1U)
#define RGPIO_PIDR_PID0_SHIFT                    (0U)
/*! PID0 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID0_SHIFT)) & RGPIO_PIDR_PID0_MASK)

#define RGPIO_PIDR_PID1_MASK                     (0x2U)
#define RGPIO_PIDR_PID1_SHIFT                    (1U)
/*! PID1 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID1_SHIFT)) & RGPIO_PIDR_PID1_MASK)

#define RGPIO_PIDR_PID2_MASK                     (0x4U)
#define RGPIO_PIDR_PID2_SHIFT                    (2U)
/*! PID2 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID2_SHIFT)) & RGPIO_PIDR_PID2_MASK)

#define RGPIO_PIDR_PID3_MASK                     (0x8U)
#define RGPIO_PIDR_PID3_SHIFT                    (3U)
/*! PID3 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID3_SHIFT)) & RGPIO_PIDR_PID3_MASK)

#define RGPIO_PIDR_PID4_MASK                     (0x10U)
#define RGPIO_PIDR_PID4_SHIFT                    (4U)
/*! PID4 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID4_SHIFT)) & RGPIO_PIDR_PID4_MASK)

#define RGPIO_PIDR_PID5_MASK                     (0x20U)
#define RGPIO_PIDR_PID5_SHIFT                    (5U)
/*! PID5 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID5_SHIFT)) & RGPIO_PIDR_PID5_MASK)

#define RGPIO_PIDR_PID6_MASK                     (0x40U)
#define RGPIO_PIDR_PID6_SHIFT                    (6U)
/*! PID6 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID6_SHIFT)) & RGPIO_PIDR_PID6_MASK)

#define RGPIO_PIDR_PID7_MASK                     (0x80U)
#define RGPIO_PIDR_PID7_SHIFT                    (7U)
/*! PID7 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID7_SHIFT)) & RGPIO_PIDR_PID7_MASK)

#define RGPIO_PIDR_PID8_MASK                     (0x100U)
#define RGPIO_PIDR_PID8_SHIFT                    (8U)
/*! PID8 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID8_SHIFT)) & RGPIO_PIDR_PID8_MASK)

#define RGPIO_PIDR_PID9_MASK                     (0x200U)
#define RGPIO_PIDR_PID9_SHIFT                    (9U)
/*! PID9 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID9_SHIFT)) & RGPIO_PIDR_PID9_MASK)

#define RGPIO_PIDR_PID10_MASK                    (0x400U)
#define RGPIO_PIDR_PID10_SHIFT                   (10U)
/*! PID10 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID10_SHIFT)) & RGPIO_PIDR_PID10_MASK)

#define RGPIO_PIDR_PID11_MASK                    (0x800U)
#define RGPIO_PIDR_PID11_SHIFT                   (11U)
/*! PID11 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID11_SHIFT)) & RGPIO_PIDR_PID11_MASK)

#define RGPIO_PIDR_PID12_MASK                    (0x1000U)
#define RGPIO_PIDR_PID12_SHIFT                   (12U)
/*! PID12 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID12_SHIFT)) & RGPIO_PIDR_PID12_MASK)

#define RGPIO_PIDR_PID13_MASK                    (0x2000U)
#define RGPIO_PIDR_PID13_SHIFT                   (13U)
/*! PID13 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID13_SHIFT)) & RGPIO_PIDR_PID13_MASK)

#define RGPIO_PIDR_PID14_MASK                    (0x4000U)
#define RGPIO_PIDR_PID14_SHIFT                   (14U)
/*! PID14 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID14_SHIFT)) & RGPIO_PIDR_PID14_MASK)

#define RGPIO_PIDR_PID15_MASK                    (0x8000U)
#define RGPIO_PIDR_PID15_SHIFT                   (15U)
/*! PID15 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID15_SHIFT)) & RGPIO_PIDR_PID15_MASK)

#define RGPIO_PIDR_PID16_MASK                    (0x10000U)
#define RGPIO_PIDR_PID16_SHIFT                   (16U)
/*! PID16 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID16_SHIFT)) & RGPIO_PIDR_PID16_MASK)

#define RGPIO_PIDR_PID17_MASK                    (0x20000U)
#define RGPIO_PIDR_PID17_SHIFT                   (17U)
/*! PID17 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID17_SHIFT)) & RGPIO_PIDR_PID17_MASK)

#define RGPIO_PIDR_PID18_MASK                    (0x40000U)
#define RGPIO_PIDR_PID18_SHIFT                   (18U)
/*! PID18 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID18_SHIFT)) & RGPIO_PIDR_PID18_MASK)

#define RGPIO_PIDR_PID19_MASK                    (0x80000U)
#define RGPIO_PIDR_PID19_SHIFT                   (19U)
/*! PID19 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID19_SHIFT)) & RGPIO_PIDR_PID19_MASK)

#define RGPIO_PIDR_PID20_MASK                    (0x100000U)
#define RGPIO_PIDR_PID20_SHIFT                   (20U)
/*! PID20 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID20_SHIFT)) & RGPIO_PIDR_PID20_MASK)

#define RGPIO_PIDR_PID21_MASK                    (0x200000U)
#define RGPIO_PIDR_PID21_SHIFT                   (21U)
/*! PID21 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID21_SHIFT)) & RGPIO_PIDR_PID21_MASK)

#define RGPIO_PIDR_PID22_MASK                    (0x400000U)
#define RGPIO_PIDR_PID22_SHIFT                   (22U)
/*! PID22 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID22_SHIFT)) & RGPIO_PIDR_PID22_MASK)

#define RGPIO_PIDR_PID23_MASK                    (0x800000U)
#define RGPIO_PIDR_PID23_SHIFT                   (23U)
/*! PID23 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID23_SHIFT)) & RGPIO_PIDR_PID23_MASK)

#define RGPIO_PIDR_PID24_MASK                    (0x1000000U)
#define RGPIO_PIDR_PID24_SHIFT                   (24U)
/*! PID24 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID24_SHIFT)) & RGPIO_PIDR_PID24_MASK)

#define RGPIO_PIDR_PID25_MASK                    (0x2000000U)
#define RGPIO_PIDR_PID25_SHIFT                   (25U)
/*! PID25 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID25_SHIFT)) & RGPIO_PIDR_PID25_MASK)

#define RGPIO_PIDR_PID26_MASK                    (0x4000000U)
#define RGPIO_PIDR_PID26_SHIFT                   (26U)
/*! PID26 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID26_SHIFT)) & RGPIO_PIDR_PID26_MASK)

#define RGPIO_PIDR_PID27_MASK                    (0x8000000U)
#define RGPIO_PIDR_PID27_SHIFT                   (27U)
/*! PID27 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID27_SHIFT)) & RGPIO_PIDR_PID27_MASK)

#define RGPIO_PIDR_PID28_MASK                    (0x10000000U)
#define RGPIO_PIDR_PID28_SHIFT                   (28U)
/*! PID28 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID28_SHIFT)) & RGPIO_PIDR_PID28_MASK)

#define RGPIO_PIDR_PID29_MASK                    (0x20000000U)
#define RGPIO_PIDR_PID29_SHIFT                   (29U)
/*! PID29 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID29_SHIFT)) & RGPIO_PIDR_PID29_MASK)

#define RGPIO_PIDR_PID30_MASK                    (0x40000000U)
#define RGPIO_PIDR_PID30_SHIFT                   (30U)
/*! PID30 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID30_SHIFT)) & RGPIO_PIDR_PID30_MASK)

#define RGPIO_PIDR_PID31_MASK                    (0x80000000U)
#define RGPIO_PIDR_PID31_SHIFT                   (31U)
/*! PID31 - Port Input Disable
 *  0b0..Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
 *  0b1..Pin is disabled for General Purpose Input.
 */
#define RGPIO_PIDR_PID31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID31_SHIFT)) & RGPIO_PIDR_PID31_MASK)
/*! @} */

/*! @name PDR - Pin Data Register a */
/*! @{ */

#define RGPIO_PDR_PD_MASK                        (0x1U)
#define RGPIO_PDR_PD_SHIFT                       (0U)
/*! PD - Pin Data
 *  0b0..Pin logic level is logic zero or not configured for use by digital function.
 *  0b1..Pin logic level is logic one.
 */
#define RGPIO_PDR_PD(x)                          (((uint8_t)(((uint8_t)(x)) << RGPIO_PDR_PD_SHIFT)) & RGPIO_PDR_PD_MASK)
/*! @} */

/* The count of RGPIO_PDR */
#define RGPIO_PDR_COUNT                          (32U)

/*! @name ICR - Interrupt Control Register 0..Interrupt Control Register 31 */
/*! @{ */

#define RGPIO_ICR_IRQC_MASK                      (0xF0000U)
#define RGPIO_ICR_IRQC_SHIFT                     (16U)
/*! IRQC - Interrupt Configuration
 *  0b0000..Interrupt Status Flag (ISF) is disabled.
 *  0b0001..ISF flag and DMA request on rising edge.
 *  0b0010..ISF flag and DMA request on falling edge.
 *  0b0011..ISF flag and DMA request on either edge.
 *  0b0100..Reserved.
 *  0b0101..ISF flag sets on rising edge.
 *  0b0110..ISF flag sets on falling edge.
 *  0b0111..ISF flag sets on either edge.
 *  0b1000..ISF flag and Interrupt when logic 0.
 *  0b1001..ISF flag and Interrupt on rising-edge.
 *  0b1010..ISF flag and Interrupt on falling-edge.
 *  0b1011..ISF flag and Interrupt on either edge.
 *  0b1100..ISF flag and Interrupt when logic 1.
 *  0b1101..Enable active high trigger output, ISF flag on rising edge. Pin state is ORed with other enabled
 *          triggers to generate the output trigger, for use by other peripherals.
 *  0b1110..Enable active low trigger output, ISF flag on falling edge. Pin state is inverted and ORed with other
 *          enabled triggers to generate the output trigger, for use by other peripherals.
 *  0b1111..Reserved.
 */
#define RGPIO_ICR_IRQC(x)                        (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_IRQC_SHIFT)) & RGPIO_ICR_IRQC_MASK)

#define RGPIO_ICR_IRQS_MASK                      (0x300000U)
#define RGPIO_ICR_IRQS_SHIFT                     (20U)
/*! IRQS - Interrupt Select
 *  0b00..Interrupt/DMA request/trigger output 0.
 *  0b01..Interrupt/DMA request/trigger output 1.
 *  0b10..Interrupt/DMA request/trigger output 2.
 *  0b11..Interrupt/DMA request/trigger output 3.
 */
#define RGPIO_ICR_IRQS(x)                        (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_IRQS_SHIFT)) & RGPIO_ICR_IRQS_MASK)

#define RGPIO_ICR_LK_MASK                        (0x800000U)
#define RGPIO_ICR_LK_SHIFT                       (23U)
/*! LK - Lock Register
 *  0b0..Interrupt configuration by ICR[23:0] is not locked and can be updated.
 *  0b1..Interrupt configuration by ICR[23:0] is locked and cannot be updated until next system reset.
 */
#define RGPIO_ICR_LK(x)                          (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_LK_SHIFT)) & RGPIO_ICR_LK_MASK)

#define RGPIO_ICR_ISF_MASK                       (0x1000000U)
#define RGPIO_ICR_ISF_SHIFT                      (24U)
/*! ISF - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected.
 *  0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
 *       corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the
 *       flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive
 *       interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
 */
#define RGPIO_ICR_ISF(x)                         (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_ISF_SHIFT)) & RGPIO_ICR_ISF_MASK)
/*! @} */

/* The count of RGPIO_ICR */
#define RGPIO_ICR_COUNT                          (32U)

/*! @name GICLR - Global Interrupt Control Low Register */
/*! @{ */

#define RGPIO_GICLR_GIWE0_MASK                   (0x1U)
#define RGPIO_GICLR_GIWE0_SHIFT                  (0U)
/*! GIWE0 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE0(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE0_SHIFT)) & RGPIO_GICLR_GIWE0_MASK)

#define RGPIO_GICLR_GIWE1_MASK                   (0x2U)
#define RGPIO_GICLR_GIWE1_SHIFT                  (1U)
/*! GIWE1 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE1(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE1_SHIFT)) & RGPIO_GICLR_GIWE1_MASK)

#define RGPIO_GICLR_GIWE2_MASK                   (0x4U)
#define RGPIO_GICLR_GIWE2_SHIFT                  (2U)
/*! GIWE2 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE2(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE2_SHIFT)) & RGPIO_GICLR_GIWE2_MASK)

#define RGPIO_GICLR_GIWE3_MASK                   (0x8U)
#define RGPIO_GICLR_GIWE3_SHIFT                  (3U)
/*! GIWE3 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE3(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE3_SHIFT)) & RGPIO_GICLR_GIWE3_MASK)

#define RGPIO_GICLR_GIWE4_MASK                   (0x10U)
#define RGPIO_GICLR_GIWE4_SHIFT                  (4U)
/*! GIWE4 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE4(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE4_SHIFT)) & RGPIO_GICLR_GIWE4_MASK)

#define RGPIO_GICLR_GIWE5_MASK                   (0x20U)
#define RGPIO_GICLR_GIWE5_SHIFT                  (5U)
/*! GIWE5 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE5(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE5_SHIFT)) & RGPIO_GICLR_GIWE5_MASK)

#define RGPIO_GICLR_GIWE6_MASK                   (0x40U)
#define RGPIO_GICLR_GIWE6_SHIFT                  (6U)
/*! GIWE6 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE6(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE6_SHIFT)) & RGPIO_GICLR_GIWE6_MASK)

#define RGPIO_GICLR_GIWE7_MASK                   (0x80U)
#define RGPIO_GICLR_GIWE7_SHIFT                  (7U)
/*! GIWE7 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE7(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE7_SHIFT)) & RGPIO_GICLR_GIWE7_MASK)

#define RGPIO_GICLR_GIWE8_MASK                   (0x100U)
#define RGPIO_GICLR_GIWE8_SHIFT                  (8U)
/*! GIWE8 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE8(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE8_SHIFT)) & RGPIO_GICLR_GIWE8_MASK)

#define RGPIO_GICLR_GIWE9_MASK                   (0x200U)
#define RGPIO_GICLR_GIWE9_SHIFT                  (9U)
/*! GIWE9 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE9(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE9_SHIFT)) & RGPIO_GICLR_GIWE9_MASK)

#define RGPIO_GICLR_GIWE10_MASK                  (0x400U)
#define RGPIO_GICLR_GIWE10_SHIFT                 (10U)
/*! GIWE10 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE10(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE10_SHIFT)) & RGPIO_GICLR_GIWE10_MASK)

#define RGPIO_GICLR_GIWE11_MASK                  (0x800U)
#define RGPIO_GICLR_GIWE11_SHIFT                 (11U)
/*! GIWE11 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE11(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE11_SHIFT)) & RGPIO_GICLR_GIWE11_MASK)

#define RGPIO_GICLR_GIWE12_MASK                  (0x1000U)
#define RGPIO_GICLR_GIWE12_SHIFT                 (12U)
/*! GIWE12 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE12(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE12_SHIFT)) & RGPIO_GICLR_GIWE12_MASK)

#define RGPIO_GICLR_GIWE13_MASK                  (0x2000U)
#define RGPIO_GICLR_GIWE13_SHIFT                 (13U)
/*! GIWE13 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE13(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE13_SHIFT)) & RGPIO_GICLR_GIWE13_MASK)

#define RGPIO_GICLR_GIWE14_MASK                  (0x4000U)
#define RGPIO_GICLR_GIWE14_SHIFT                 (14U)
/*! GIWE14 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE14(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE14_SHIFT)) & RGPIO_GICLR_GIWE14_MASK)

#define RGPIO_GICLR_GIWE15_MASK                  (0x8000U)
#define RGPIO_GICLR_GIWE15_SHIFT                 (15U)
/*! GIWE15 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICLR_GIWE15(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE15_SHIFT)) & RGPIO_GICLR_GIWE15_MASK)

#define RGPIO_GICLR_GIWD_MASK                    (0xFFFF0000U)
#define RGPIO_GICLR_GIWD_SHIFT                   (16U)
/*! GIWD - Global Interrupt Write Data */
#define RGPIO_GICLR_GIWD(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWD_SHIFT)) & RGPIO_GICLR_GIWD_MASK)
/*! @} */

/*! @name GICHR - Global Interrupt Control High Register */
/*! @{ */

#define RGPIO_GICHR_GIWE16_MASK                  (0x1U)
#define RGPIO_GICHR_GIWE16_SHIFT                 (0U)
/*! GIWE16 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE16(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE16_SHIFT)) & RGPIO_GICHR_GIWE16_MASK)

#define RGPIO_GICHR_GIWE17_MASK                  (0x2U)
#define RGPIO_GICHR_GIWE17_SHIFT                 (1U)
/*! GIWE17 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE17(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE17_SHIFT)) & RGPIO_GICHR_GIWE17_MASK)

#define RGPIO_GICHR_GIWE18_MASK                  (0x4U)
#define RGPIO_GICHR_GIWE18_SHIFT                 (2U)
/*! GIWE18 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE18(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE18_SHIFT)) & RGPIO_GICHR_GIWE18_MASK)

#define RGPIO_GICHR_GIWE19_MASK                  (0x8U)
#define RGPIO_GICHR_GIWE19_SHIFT                 (3U)
/*! GIWE19 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE19(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE19_SHIFT)) & RGPIO_GICHR_GIWE19_MASK)

#define RGPIO_GICHR_GIWE20_MASK                  (0x10U)
#define RGPIO_GICHR_GIWE20_SHIFT                 (4U)
/*! GIWE20 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE20(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE20_SHIFT)) & RGPIO_GICHR_GIWE20_MASK)

#define RGPIO_GICHR_GIWE21_MASK                  (0x20U)
#define RGPIO_GICHR_GIWE21_SHIFT                 (5U)
/*! GIWE21 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE21(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE21_SHIFT)) & RGPIO_GICHR_GIWE21_MASK)

#define RGPIO_GICHR_GIWE22_MASK                  (0x40U)
#define RGPIO_GICHR_GIWE22_SHIFT                 (6U)
/*! GIWE22 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE22(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE22_SHIFT)) & RGPIO_GICHR_GIWE22_MASK)

#define RGPIO_GICHR_GIWE23_MASK                  (0x80U)
#define RGPIO_GICHR_GIWE23_SHIFT                 (7U)
/*! GIWE23 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE23(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE23_SHIFT)) & RGPIO_GICHR_GIWE23_MASK)

#define RGPIO_GICHR_GIWE24_MASK                  (0x100U)
#define RGPIO_GICHR_GIWE24_SHIFT                 (8U)
/*! GIWE24 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE24(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE24_SHIFT)) & RGPIO_GICHR_GIWE24_MASK)

#define RGPIO_GICHR_GIWE25_MASK                  (0x200U)
#define RGPIO_GICHR_GIWE25_SHIFT                 (9U)
/*! GIWE25 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE25(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE25_SHIFT)) & RGPIO_GICHR_GIWE25_MASK)

#define RGPIO_GICHR_GIWE26_MASK                  (0x400U)
#define RGPIO_GICHR_GIWE26_SHIFT                 (10U)
/*! GIWE26 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE26(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE26_SHIFT)) & RGPIO_GICHR_GIWE26_MASK)

#define RGPIO_GICHR_GIWE27_MASK                  (0x800U)
#define RGPIO_GICHR_GIWE27_SHIFT                 (11U)
/*! GIWE27 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE27(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE27_SHIFT)) & RGPIO_GICHR_GIWE27_MASK)

#define RGPIO_GICHR_GIWE28_MASK                  (0x1000U)
#define RGPIO_GICHR_GIWE28_SHIFT                 (12U)
/*! GIWE28 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE28(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE28_SHIFT)) & RGPIO_GICHR_GIWE28_MASK)

#define RGPIO_GICHR_GIWE29_MASK                  (0x2000U)
#define RGPIO_GICHR_GIWE29_SHIFT                 (13U)
/*! GIWE29 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE29(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE29_SHIFT)) & RGPIO_GICHR_GIWE29_MASK)

#define RGPIO_GICHR_GIWE30_MASK                  (0x4000U)
#define RGPIO_GICHR_GIWE30_SHIFT                 (14U)
/*! GIWE30 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE30(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE30_SHIFT)) & RGPIO_GICHR_GIWE30_MASK)

#define RGPIO_GICHR_GIWE31_MASK                  (0x8000U)
#define RGPIO_GICHR_GIWE31_SHIFT                 (15U)
/*! GIWE31 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define RGPIO_GICHR_GIWE31(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE31_SHIFT)) & RGPIO_GICHR_GIWE31_MASK)

#define RGPIO_GICHR_GIWD_MASK                    (0xFFFF0000U)
#define RGPIO_GICHR_GIWD_SHIFT                   (16U)
/*! GIWD - Global Interrupt Write Data */
#define RGPIO_GICHR_GIWD(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWD_SHIFT)) & RGPIO_GICHR_GIWD_MASK)
/*! @} */

/*! @name ISFR - Interrupt Status Flag Register */
/*! @{ */

#define RGPIO_ISFR_ISF0_MASK                     (0x1U)
#define RGPIO_ISFR_ISF0_SHIFT                    (0U)
/*! ISF0 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF0_SHIFT)) & RGPIO_ISFR_ISF0_MASK)

#define RGPIO_ISFR_ISF1_MASK                     (0x2U)
#define RGPIO_ISFR_ISF1_SHIFT                    (1U)
/*! ISF1 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF1_SHIFT)) & RGPIO_ISFR_ISF1_MASK)

#define RGPIO_ISFR_ISF2_MASK                     (0x4U)
#define RGPIO_ISFR_ISF2_SHIFT                    (2U)
/*! ISF2 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF2_SHIFT)) & RGPIO_ISFR_ISF2_MASK)

#define RGPIO_ISFR_ISF3_MASK                     (0x8U)
#define RGPIO_ISFR_ISF3_SHIFT                    (3U)
/*! ISF3 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF3_SHIFT)) & RGPIO_ISFR_ISF3_MASK)

#define RGPIO_ISFR_ISF4_MASK                     (0x10U)
#define RGPIO_ISFR_ISF4_SHIFT                    (4U)
/*! ISF4 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF4_SHIFT)) & RGPIO_ISFR_ISF4_MASK)

#define RGPIO_ISFR_ISF5_MASK                     (0x20U)
#define RGPIO_ISFR_ISF5_SHIFT                    (5U)
/*! ISF5 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF5_SHIFT)) & RGPIO_ISFR_ISF5_MASK)

#define RGPIO_ISFR_ISF6_MASK                     (0x40U)
#define RGPIO_ISFR_ISF6_SHIFT                    (6U)
/*! ISF6 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF6_SHIFT)) & RGPIO_ISFR_ISF6_MASK)

#define RGPIO_ISFR_ISF7_MASK                     (0x80U)
#define RGPIO_ISFR_ISF7_SHIFT                    (7U)
/*! ISF7 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF7_SHIFT)) & RGPIO_ISFR_ISF7_MASK)

#define RGPIO_ISFR_ISF8_MASK                     (0x100U)
#define RGPIO_ISFR_ISF8_SHIFT                    (8U)
/*! ISF8 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF8_SHIFT)) & RGPIO_ISFR_ISF8_MASK)

#define RGPIO_ISFR_ISF9_MASK                     (0x200U)
#define RGPIO_ISFR_ISF9_SHIFT                    (9U)
/*! ISF9 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF9_SHIFT)) & RGPIO_ISFR_ISF9_MASK)

#define RGPIO_ISFR_ISF10_MASK                    (0x400U)
#define RGPIO_ISFR_ISF10_SHIFT                   (10U)
/*! ISF10 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF10_SHIFT)) & RGPIO_ISFR_ISF10_MASK)

#define RGPIO_ISFR_ISF11_MASK                    (0x800U)
#define RGPIO_ISFR_ISF11_SHIFT                   (11U)
/*! ISF11 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF11_SHIFT)) & RGPIO_ISFR_ISF11_MASK)

#define RGPIO_ISFR_ISF12_MASK                    (0x1000U)
#define RGPIO_ISFR_ISF12_SHIFT                   (12U)
/*! ISF12 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF12_SHIFT)) & RGPIO_ISFR_ISF12_MASK)

#define RGPIO_ISFR_ISF13_MASK                    (0x2000U)
#define RGPIO_ISFR_ISF13_SHIFT                   (13U)
/*! ISF13 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF13_SHIFT)) & RGPIO_ISFR_ISF13_MASK)

#define RGPIO_ISFR_ISF14_MASK                    (0x4000U)
#define RGPIO_ISFR_ISF14_SHIFT                   (14U)
/*! ISF14 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF14_SHIFT)) & RGPIO_ISFR_ISF14_MASK)

#define RGPIO_ISFR_ISF15_MASK                    (0x8000U)
#define RGPIO_ISFR_ISF15_SHIFT                   (15U)
/*! ISF15 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF15_SHIFT)) & RGPIO_ISFR_ISF15_MASK)

#define RGPIO_ISFR_ISF16_MASK                    (0x10000U)
#define RGPIO_ISFR_ISF16_SHIFT                   (16U)
/*! ISF16 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF16_SHIFT)) & RGPIO_ISFR_ISF16_MASK)

#define RGPIO_ISFR_ISF17_MASK                    (0x20000U)
#define RGPIO_ISFR_ISF17_SHIFT                   (17U)
/*! ISF17 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF17_SHIFT)) & RGPIO_ISFR_ISF17_MASK)

#define RGPIO_ISFR_ISF18_MASK                    (0x40000U)
#define RGPIO_ISFR_ISF18_SHIFT                   (18U)
/*! ISF18 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF18_SHIFT)) & RGPIO_ISFR_ISF18_MASK)

#define RGPIO_ISFR_ISF19_MASK                    (0x80000U)
#define RGPIO_ISFR_ISF19_SHIFT                   (19U)
/*! ISF19 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF19_SHIFT)) & RGPIO_ISFR_ISF19_MASK)

#define RGPIO_ISFR_ISF20_MASK                    (0x100000U)
#define RGPIO_ISFR_ISF20_SHIFT                   (20U)
/*! ISF20 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF20_SHIFT)) & RGPIO_ISFR_ISF20_MASK)

#define RGPIO_ISFR_ISF21_MASK                    (0x200000U)
#define RGPIO_ISFR_ISF21_SHIFT                   (21U)
/*! ISF21 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF21_SHIFT)) & RGPIO_ISFR_ISF21_MASK)

#define RGPIO_ISFR_ISF22_MASK                    (0x400000U)
#define RGPIO_ISFR_ISF22_SHIFT                   (22U)
/*! ISF22 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF22_SHIFT)) & RGPIO_ISFR_ISF22_MASK)

#define RGPIO_ISFR_ISF23_MASK                    (0x800000U)
#define RGPIO_ISFR_ISF23_SHIFT                   (23U)
/*! ISF23 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF23_SHIFT)) & RGPIO_ISFR_ISF23_MASK)

#define RGPIO_ISFR_ISF24_MASK                    (0x1000000U)
#define RGPIO_ISFR_ISF24_SHIFT                   (24U)
/*! ISF24 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF24_SHIFT)) & RGPIO_ISFR_ISF24_MASK)

#define RGPIO_ISFR_ISF25_MASK                    (0x2000000U)
#define RGPIO_ISFR_ISF25_SHIFT                   (25U)
/*! ISF25 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF25_SHIFT)) & RGPIO_ISFR_ISF25_MASK)

#define RGPIO_ISFR_ISF26_MASK                    (0x4000000U)
#define RGPIO_ISFR_ISF26_SHIFT                   (26U)
/*! ISF26 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF26_SHIFT)) & RGPIO_ISFR_ISF26_MASK)

#define RGPIO_ISFR_ISF27_MASK                    (0x8000000U)
#define RGPIO_ISFR_ISF27_SHIFT                   (27U)
/*! ISF27 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF27_SHIFT)) & RGPIO_ISFR_ISF27_MASK)

#define RGPIO_ISFR_ISF28_MASK                    (0x10000000U)
#define RGPIO_ISFR_ISF28_SHIFT                   (28U)
/*! ISF28 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF28_SHIFT)) & RGPIO_ISFR_ISF28_MASK)

#define RGPIO_ISFR_ISF29_MASK                    (0x20000000U)
#define RGPIO_ISFR_ISF29_SHIFT                   (29U)
/*! ISF29 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF29_SHIFT)) & RGPIO_ISFR_ISF29_MASK)

#define RGPIO_ISFR_ISF30_MASK                    (0x40000000U)
#define RGPIO_ISFR_ISF30_SHIFT                   (30U)
/*! ISF30 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF30_SHIFT)) & RGPIO_ISFR_ISF30_MASK)

#define RGPIO_ISFR_ISF31_MASK                    (0x80000000U)
#define RGPIO_ISFR_ISF31_SHIFT                   (31U)
/*! ISF31 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define RGPIO_ISFR_ISF31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF31_SHIFT)) & RGPIO_ISFR_ISF31_MASK)
/*! @} */

/* The count of RGPIO_ISFR */
#define RGPIO_ISFR_COUNT                         (4U)


/*!
 * @}
 */ /* end of group RGPIO_Register_Masks */


/* RGPIO - Peripheral instance base addresses */
/** Peripheral GPIOA base address */
#define GPIOA_BASE                               (0x28800000u)
/** Peripheral GPIOA base pointer */
#define GPIOA                                    ((RGPIO_Type *)GPIOA_BASE)
/** Peripheral GPIOB base address */
#define GPIOB_BASE                               (0x28810000u)
/** Peripheral GPIOB base pointer */
#define GPIOB                                    ((RGPIO_Type *)GPIOB_BASE)
/** Peripheral GPIOC base address */
#define GPIOC_BASE                               (0x28820000u)
/** Peripheral GPIOC base pointer */
#define GPIOC                                    ((RGPIO_Type *)GPIOC_BASE)
/** Peripheral GPIOD base address */
#define GPIOD_BASE                               (0x2E200000u)
/** Peripheral GPIOD base pointer */
#define GPIOD                                    ((RGPIO_Type *)GPIOD_BASE)
/** Peripheral GPIOE base address */
#define GPIOE_BASE                               (0x2D000000u)
/** Peripheral GPIOE base pointer */
#define GPIOE                                    ((RGPIO_Type *)GPIOE_BASE)
/** Peripheral GPIOF base address */
#define GPIOF_BASE                               (0x2D010000u)
/** Peripheral GPIOF base pointer */
#define GPIOF                                    ((RGPIO_Type *)GPIOF_BASE)
/** Array initializer of RGPIO peripheral base addresses */
#define RGPIO_BASE_ADDRS                         { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE, GPIOF_BASE }
/** Array initializer of RGPIO peripheral base pointers */
#define RGPIO_BASE_PTRS                          { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF }

/*!
 * @}
 */ /* end of group RGPIO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SEMA42 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer
 * @{
 */

/** SEMA42 - Register Layout Typedef */
typedef struct {
  __IO uint8_t GATE3;                              /**< Gate Register, offset: 0x0 */
  __IO uint8_t GATE2;                              /**< Gate Register, offset: 0x1 */
  __IO uint8_t GATE1;                              /**< Gate Register, offset: 0x2 */
  __IO uint8_t GATE0;                              /**< Gate Register, offset: 0x3 */
  __IO uint8_t GATE7;                              /**< Gate Register, offset: 0x4 */
  __IO uint8_t GATE6;                              /**< Gate Register, offset: 0x5 */
  __IO uint8_t GATE5;                              /**< Gate Register, offset: 0x6 */
  __IO uint8_t GATE4;                              /**< Gate Register, offset: 0x7 */
  __IO uint8_t GATE11;                             /**< Gate Register, offset: 0x8 */
  __IO uint8_t GATE10;                             /**< Gate Register, offset: 0x9 */
  __IO uint8_t GATE9;                              /**< Gate Register, offset: 0xA */
  __IO uint8_t GATE8;                              /**< Gate Register, offset: 0xB */
  __IO uint8_t GATE15;                             /**< Gate Register, offset: 0xC */
  __IO uint8_t GATE14;                             /**< Gate Register, offset: 0xD */
  __IO uint8_t GATE13;                             /**< Gate Register, offset: 0xE */
  __IO uint8_t GATE12;                             /**< Gate Register, offset: 0xF */
       uint8_t RESERVED_0[50];
  union {                                          /* offset: 0x42 */
    __I  uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
    __O  uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
  };
} SEMA42_Type;

/* ----------------------------------------------------------------------------
   -- SEMA42 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks
 * @{
 */

/*! @name GATE3 - Gate Register */
/*! @{ */

#define SEMA42_GATE3_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE3_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE3_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK)
/*! @} */

/*! @name GATE2 - Gate Register */
/*! @{ */

#define SEMA42_GATE2_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE2_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE2_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK)
/*! @} */

/*! @name GATE1 - Gate Register */
/*! @{ */

#define SEMA42_GATE1_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE1_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE1_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK)
/*! @} */

/*! @name GATE0 - Gate Register */
/*! @{ */

#define SEMA42_GATE0_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE0_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE0_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK)
/*! @} */

/*! @name GATE7 - Gate Register */
/*! @{ */

#define SEMA42_GATE7_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE7_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE7_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK)
/*! @} */

/*! @name GATE6 - Gate Register */
/*! @{ */

#define SEMA42_GATE6_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE6_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE6_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK)
/*! @} */

/*! @name GATE5 - Gate Register */
/*! @{ */

#define SEMA42_GATE5_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE5_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE5_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK)
/*! @} */

/*! @name GATE4 - Gate Register */
/*! @{ */

#define SEMA42_GATE4_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE4_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE4_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK)
/*! @} */

/*! @name GATE11 - Gate Register */
/*! @{ */

#define SEMA42_GATE11_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE11_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE11_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK)
/*! @} */

/*! @name GATE10 - Gate Register */
/*! @{ */

#define SEMA42_GATE10_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE10_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE10_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK)
/*! @} */

/*! @name GATE9 - Gate Register */
/*! @{ */

#define SEMA42_GATE9_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE9_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE9_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK)
/*! @} */

/*! @name GATE8 - Gate Register */
/*! @{ */

#define SEMA42_GATE8_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE8_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE8_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK)
/*! @} */

/*! @name GATE15 - Gate Register */
/*! @{ */

#define SEMA42_GATE15_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE15_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE15_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK)
/*! @} */

/*! @name GATE14 - Gate Register */
/*! @{ */

#define SEMA42_GATE14_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE14_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE14_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK)
/*! @} */

/*! @name GATE13 - Gate Register */
/*! @{ */

#define SEMA42_GATE13_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE13_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE13_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK)
/*! @} */

/*! @name GATE12 - Gate Register */
/*! @{ */

#define SEMA42_GATE12_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE12_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE12_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK)
/*! @} */

/*! @name RSTGT_R - Reset Gate Read */
/*! @{ */

#define SEMA42_RSTGT_R_RSTGTN_MASK               (0xFFU)
#define SEMA42_RSTGT_R_RSTGTN_SHIFT              (0U)
/*! RSTGTN - Reset gate number */
#define SEMA42_RSTGT_R_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK)

#define SEMA42_RSTGT_R_RSTGMS_MASK               (0xF00U)
#define SEMA42_RSTGT_R_RSTGMS_SHIFT              (8U)
/*! RSTGMS - Reset gate domain */
#define SEMA42_RSTGT_R_RSTGMS(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)

#define SEMA42_RSTGT_R_RSTGSM_MASK               (0x3000U)
#define SEMA42_RSTGT_R_RSTGSM_SHIFT              (12U)
/*! RSTGSM - Reset gate finite state machine
 *  0b00..Idle, waiting for the first data pattern write.
 *  0b01..Waiting for the second data pattern write
 *  0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
 *        this machine returns to the idle (waiting for first data pattern write) state.
 *  0b11..This state encoding is never used and therefore reserved.
 */
#define SEMA42_RSTGT_R_RSTGSM(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK)

#define SEMA42_RSTGT_R_ROZ_MASK                  (0xC000U)
#define SEMA42_RSTGT_R_ROZ_SHIFT                 (14U)
/*! ROZ - ROZ */
#define SEMA42_RSTGT_R_ROZ(x)                    (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_ROZ_SHIFT)) & SEMA42_RSTGT_R_ROZ_MASK)
/*! @} */

/*! @name RSTGT_W - Reset Gate Write */
/*! @{ */

#define SEMA42_RSTGT_W_RSTGTN_MASK               (0xFFU)
#define SEMA42_RSTGT_W_RSTGTN_SHIFT              (0U)
/*! RSTGTN - Reset gate number */
#define SEMA42_RSTGT_W_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK)

#define SEMA42_RSTGT_W_RSTGDP_MASK               (0xFF00U)
#define SEMA42_RSTGT_W_RSTGDP_SHIFT              (8U)
/*! RSTGDP - Reset gate data pattern */
#define SEMA42_RSTGT_W_RSTGDP(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SEMA42_Register_Masks */


/* SEMA42 - Peripheral instance base addresses */
/** Peripheral SEMA42_0 base address */
#define SEMA42_0_BASE                            (0x28037000u)
/** Peripheral SEMA42_0 base pointer */
#define SEMA42_0                                 ((SEMA42_Type *)SEMA42_0_BASE)
/** Peripheral SEMA42_1 base address */
#define SEMA42_1_BASE                            (0x29300000u)
/** Peripheral SEMA42_1 base pointer */
#define SEMA42_1                                 ((SEMA42_Type *)SEMA42_1_BASE)
/** Peripheral SEMA42_2 base address */
#define SEMA42_2_BASE                            (0x2DA30000u)
/** Peripheral SEMA42_2 base pointer */
#define SEMA42_2                                 ((SEMA42_Type *)SEMA42_2_BASE)
/** Array initializer of SEMA42 peripheral base addresses */
#define SEMA42_BASE_ADDRS                        { SEMA42_0_BASE, SEMA42_1_BASE, SEMA42_2_BASE }
/** Array initializer of SEMA42 peripheral base pointers */
#define SEMA42_BASE_PTRS                         { SEMA42_0, SEMA42_1, SEMA42_2 }

/*!
 * @}
 */ /* end of group SEMA42_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SIM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
 * @{
 */

/** SIM - Register Layout Typedef */
typedef struct {
       uint32_t GPR0;                              /**< HW RTD_SIM General Purpose Register 0, offset: 0x0 */
       uint32_t GPR1;                              /**< HW RTD_SIM General Purpose Register 1, offset: 0x4 */
  __IO uint32_t SYSCTRL0;                          /**< Realtime Domains System Control Register 0, offset: 0x8 */
       uint32_t SYSCTRL1;                          /**< Realtime Domains System Control Register 0, offset: 0xC */
  __I  uint32_t JTAG_ID_REG;                       /**< Mirror of JTAG ID Register, offset: 0x10 */
       uint8_t RESERVED_0[8];
  __IO uint32_t SSRAM_SAVE_POWER;                  /**< System Shared RAM Access Disable Register, offset: 0x1C */
  __IO uint32_t PTC_COMPCELL;                      /**< Configures PTC Pads Compensation Cell operation, offset: 0x20 */
  __IO uint32_t MQS0_CF;                           /**< Medium Quality Sound Configuration Register, offset: 0x24 */
  __IO uint32_t M33_CFGNSSTCALIB;                  /**< Non-Secure SysTick Calibration Configuration, offset: 0x28 */
       uint8_t RESERVED_1[44];
  __IO uint32_t SAI_MULTISYNC_ENABLE_SELECTOR;     /**< SAI 0 to 3 Transmitter/Receiver Multi-Synchronous Enable Source, offset: 0x58 */
} SIM_Type;

/* ----------------------------------------------------------------------------
   -- SIM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SIM_Register_Masks SIM Register Masks
 * @{
 */

/*! @name SYSCTRL0 - Realtime Domains System Control Register 0 */
/*! @{ */

#define SIM_SYSCTRL0_CM33_RST_ACK_MASK           (0x8U)
#define SIM_SYSCTRL0_CM33_RST_ACK_SHIFT          (3U)
/*! CM33_RST_ACK - CM33 Core is in safe state for reset sequencing */
#define SIM_SYSCTRL0_CM33_RST_ACK(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SYSCTRL0_CM33_RST_ACK_SHIFT)) & SIM_SYSCTRL0_CM33_RST_ACK_MASK)

#define SIM_SYSCTRL0_FLEXCAN_TICK_FREQ_CONFIG_MASK (0x3FF0000U)
#define SIM_SYSCTRL0_FLEXCAN_TICK_FREQ_CONFIG_SHIFT (16U)
/*! FLEXCAN_TICK_FREQ_CONFIG - FlexCAN Timer Frequency Configuration Register */
#define SIM_SYSCTRL0_FLEXCAN_TICK_FREQ_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SYSCTRL0_FLEXCAN_TICK_FREQ_CONFIG_SHIFT)) & SIM_SYSCTRL0_FLEXCAN_TICK_FREQ_CONFIG_MASK)
/*! @} */

/*! @name JTAG_ID_REG - Mirror of JTAG ID Register */
/*! @{ */

#define SIM_JTAG_ID_REG_JTAG_INIT_BIT_MASK       (0x1U)
#define SIM_JTAG_ID_REG_JTAG_INIT_BIT_SHIFT      (0U)
/*! JTAG_INIT_BIT - JTAG ID Initial Bit */
#define SIM_JTAG_ID_REG_JTAG_INIT_BIT(x)         (((uint32_t)(((uint32_t)(x)) << SIM_JTAG_ID_REG_JTAG_INIT_BIT_SHIFT)) & SIM_JTAG_ID_REG_JTAG_INIT_BIT_MASK)

#define SIM_JTAG_ID_REG_COMPANY_IDCODE_MASK      (0xFFEU)
#define SIM_JTAG_ID_REG_COMPANY_IDCODE_SHIFT     (1U)
/*! COMPANY_IDCODE - Company ID Code */
#define SIM_JTAG_ID_REG_COMPANY_IDCODE(x)        (((uint32_t)(((uint32_t)(x)) << SIM_JTAG_ID_REG_COMPANY_IDCODE_SHIFT)) & SIM_JTAG_ID_REG_COMPANY_IDCODE_MASK)

#define SIM_JTAG_ID_REG_PIN_PLUG_MASK            (0x3FF000U)
#define SIM_JTAG_ID_REG_PIN_PLUG_SHIFT           (12U)
/*! PIN_PLUG - Part Identification Number */
#define SIM_JTAG_ID_REG_PIN_PLUG(x)              (((uint32_t)(((uint32_t)(x)) << SIM_JTAG_ID_REG_PIN_PLUG_SHIFT)) & SIM_JTAG_ID_REG_PIN_PLUG_MASK)

#define SIM_JTAG_ID_REG_DESIGN_CENTER_IDCODE_MASK (0xFC00000U)
#define SIM_JTAG_ID_REG_DESIGN_CENTER_IDCODE_SHIFT (22U)
/*! DESIGN_CENTER_IDCODE - Design Center ID Code */
#define SIM_JTAG_ID_REG_DESIGN_CENTER_IDCODE(x)  (((uint32_t)(((uint32_t)(x)) << SIM_JTAG_ID_REG_DESIGN_CENTER_IDCODE_SHIFT)) & SIM_JTAG_ID_REG_DESIGN_CENTER_IDCODE_MASK)

#define SIM_JTAG_ID_REG_PRN_PLUG_MASK            (0xF0000000U)
#define SIM_JTAG_ID_REG_PRN_PLUG_SHIFT           (28U)
/*! PRN_PLUG - Part Revision Number */
#define SIM_JTAG_ID_REG_PRN_PLUG(x)              (((uint32_t)(((uint32_t)(x)) << SIM_JTAG_ID_REG_PRN_PLUG_SHIFT)) & SIM_JTAG_ID_REG_PRN_PLUG_MASK)
/*! @} */

/*! @name SSRAM_SAVE_POWER - System Shared RAM Access Disable Register */
/*! @{ */

#define SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_AUTO_CLOCK_GATING_MASK (0xFFU)
#define SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_AUTO_CLOCK_GATING_SHIFT (0U)
/*! SSRAM_DISABLE_AUTO_CLOCK_GATING - Disable Automatic Clock Gating */
#define SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_AUTO_CLOCK_GATING(x) (((uint32_t)(((uint32_t)(x)) << SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_AUTO_CLOCK_GATING_SHIFT)) & SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_AUTO_CLOCK_GATING_MASK)

#define SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_ARRAYS_INPUTS_MASK (0xFF00U)
#define SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_ARRAYS_INPUTS_SHIFT (8U)
/*! SSRAM_DISABLE_ARRAYS_INPUTS - System Shared RAM Input Gate (IG) Disable */
#define SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_ARRAYS_INPUTS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_ARRAYS_INPUTS_SHIFT)) & SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_ARRAYS_INPUTS_MASK)

#define SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_ARRAYS_WORDLINES_MASK (0xFF0000U)
#define SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_ARRAYS_WORDLINES_SHIFT (16U)
/*! SSRAM_DISABLE_ARRAYS_WORDLINES - System Shared RAM Arrays Wordlines Disable */
#define SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_ARRAYS_WORDLINES(x) (((uint32_t)(((uint32_t)(x)) << SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_ARRAYS_WORDLINES_SHIFT)) & SIM_SSRAM_SAVE_POWER_SSRAM_DISABLE_ARRAYS_WORDLINES_MASK)
/*! @} */

/*! @name PTC_COMPCELL - Configures PTC Pads Compensation Cell operation */
/*! @{ */

#define SIM_PTC_COMPCELL_RASRCN_MASK             (0xFU)
#define SIM_PTC_COMPCELL_RASRCN_SHIFT            (0U)
/*! RASRCN - Defines Pads Driver NMOS transistors Compensation Code */
#define SIM_PTC_COMPCELL_RASRCN(x)               (((uint32_t)(((uint32_t)(x)) << SIM_PTC_COMPCELL_RASRCN_SHIFT)) & SIM_PTC_COMPCELL_RASRCN_MASK)

#define SIM_PTC_COMPCELL_RASRCP_MASK             (0xF0U)
#define SIM_PTC_COMPCELL_RASRCP_SHIFT            (4U)
/*! RASRCP - Defines Pads Driver PMOS Transistors Compensation Code */
#define SIM_PTC_COMPCELL_RASRCP(x)               (((uint32_t)(((uint32_t)(x)) << SIM_PTC_COMPCELL_RASRCP_SHIFT)) & SIM_PTC_COMPCELL_RASRCP_MASK)

#define SIM_PTC_COMPCELL_SLEEP_MASK              (0x800U)
#define SIM_PTC_COMPCELL_SLEEP_SHIFT             (11U)
/*! SLEEP - Enables SLEEP Mode */
#define SIM_PTC_COMPCELL_SLEEP(x)                (((uint32_t)(((uint32_t)(x)) << SIM_PTC_COMPCELL_SLEEP_SHIFT)) & SIM_PTC_COMPCELL_SLEEP_MASK)

#define SIM_PTC_COMPCELL_FASTFREEZE_MASK         (0x1000U)
#define SIM_PTC_COMPCELL_FASTFREEZE_SHIFT        (12U)
/*! FASTFREEZE - Enables Fast Freeze Mode */
#define SIM_PTC_COMPCELL_FASTFREEZE(x)           (((uint32_t)(((uint32_t)(x)) << SIM_PTC_COMPCELL_FASTFREEZE_SHIFT)) & SIM_PTC_COMPCELL_FASTFREEZE_MASK)

#define SIM_PTC_COMPCELL_FREEZE_MASK             (0x2000U)
#define SIM_PTC_COMPCELL_FREEZE_SHIFT            (13U)
/*! FREEZE - Enables Freeze Mode */
#define SIM_PTC_COMPCELL_FREEZE(x)               (((uint32_t)(((uint32_t)(x)) << SIM_PTC_COMPCELL_FREEZE_SHIFT)) & SIM_PTC_COMPCELL_FREEZE_MASK)

#define SIM_PTC_COMPCELL_COMTQ_MASK              (0x4000U)
#define SIM_PTC_COMPCELL_COMTQ_SHIFT             (14U)
/*! COMTQ - Compensation TQ */
#define SIM_PTC_COMPCELL_COMTQ(x)                (((uint32_t)(((uint32_t)(x)) << SIM_PTC_COMPCELL_COMTQ_SHIFT)) & SIM_PTC_COMPCELL_COMTQ_MASK)

#define SIM_PTC_COMPCELL_COMPE_MASK              (0x8000U)
#define SIM_PTC_COMPCELL_COMPE_SHIFT             (15U)
/*! COMPE - Compensation Status */
#define SIM_PTC_COMPCELL_COMPE(x)                (((uint32_t)(((uint32_t)(x)) << SIM_PTC_COMPCELL_COMPE_SHIFT)) & SIM_PTC_COMPCELL_COMPE_MASK)

#define SIM_PTC_COMPCELL_NASRCN_MASK             (0xF0000U)
#define SIM_PTC_COMPCELL_NASRCN_SHIFT            (16U)
/*! NASRCN - Generated Pads Driver NMOS transistors Compensation Code */
#define SIM_PTC_COMPCELL_NASRCN(x)               (((uint32_t)(((uint32_t)(x)) << SIM_PTC_COMPCELL_NASRCN_SHIFT)) & SIM_PTC_COMPCELL_NASRCN_MASK)

#define SIM_PTC_COMPCELL_NASRCP_MASK             (0xF00000U)
#define SIM_PTC_COMPCELL_NASRCP_SHIFT            (20U)
/*! NASRCP - Generated Pads Driver PMOS transistors Compensation Code */
#define SIM_PTC_COMPCELL_NASRCP(x)               (((uint32_t)(((uint32_t)(x)) << SIM_PTC_COMPCELL_NASRCP_SHIFT)) & SIM_PTC_COMPCELL_NASRCP_MASK)

#define SIM_PTC_COMPCELL_COMPOK_MASK             (0x80000000U)
#define SIM_PTC_COMPCELL_COMPOK_SHIFT            (31U)
/*! COMPOK - Compensation OK */
#define SIM_PTC_COMPCELL_COMPOK(x)               (((uint32_t)(((uint32_t)(x)) << SIM_PTC_COMPCELL_COMPOK_SHIFT)) & SIM_PTC_COMPCELL_COMPOK_MASK)
/*! @} */

/*! @name MQS0_CF - Medium Quality Sound Configuration Register */
/*! @{ */

#define SIM_MQS0_CF_MQS0_CLK_DIV_MASK            (0xFF0000U)
#define SIM_MQS0_CF_MQS0_CLK_DIV_SHIFT           (16U)
/*! MQS0_CLK_DIV - Divider Ration Control for MCLK from HMCLK. */
#define SIM_MQS0_CF_MQS0_CLK_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SIM_MQS0_CF_MQS0_CLK_DIV_SHIFT)) & SIM_MQS0_CF_MQS0_CLK_DIV_MASK)

#define SIM_MQS0_CF_MQS0_SW_RST_MASK             (0x1000000U)
#define SIM_MQS0_CF_MQS0_SW_RST_SHIFT            (24U)
/*! MQS0_SW_RST - MQS Software Reset */
#define SIM_MQS0_CF_MQS0_SW_RST(x)               (((uint32_t)(((uint32_t)(x)) << SIM_MQS0_CF_MQS0_SW_RST_SHIFT)) & SIM_MQS0_CF_MQS0_SW_RST_MASK)

#define SIM_MQS0_CF_MQS0_EN_MASK                 (0x2000000U)
#define SIM_MQS0_CF_MQS0_EN_SHIFT                (25U)
/*! MQS0_EN - Enables MQS */
#define SIM_MQS0_CF_MQS0_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_MQS0_CF_MQS0_EN_SHIFT)) & SIM_MQS0_CF_MQS0_EN_MASK)

#define SIM_MQS0_CF_MQS0_OVERSAMPLE_MASK         (0x4000000U)
#define SIM_MQS0_CF_MQS0_OVERSAMPLE_SHIFT        (26U)
/*! MQS0_OVERSAMPLE - PWM Oversampling Rate Selection */
#define SIM_MQS0_CF_MQS0_OVERSAMPLE(x)           (((uint32_t)(((uint32_t)(x)) << SIM_MQS0_CF_MQS0_OVERSAMPLE_SHIFT)) & SIM_MQS0_CF_MQS0_OVERSAMPLE_MASK)

#define SIM_MQS0_CF_MQS0_SDATA_SOURCE_MASK       (0x8000000U)
#define SIM_MQS0_CF_MQS0_SDATA_SOURCE_SHIFT      (27U)
/*! MQS0_SDATA_SOURCE - MQS1s Sdata Input Source Selection */
#define SIM_MQS0_CF_MQS0_SDATA_SOURCE(x)         (((uint32_t)(((uint32_t)(x)) << SIM_MQS0_CF_MQS0_SDATA_SOURCE_SHIFT)) & SIM_MQS0_CF_MQS0_SDATA_SOURCE_MASK)
/*! @} */

/*! @name M33_CFGNSSTCALIB - Non-Secure SysTick Calibration Configuration */
/*! @{ */

#define SIM_M33_CFGNSSTCALIB_CFGNSSTCALIB_MASK   (0x3FFFFFFU)
#define SIM_M33_CFGNSSTCALIB_CFGNSSTCALIB_SHIFT  (0U)
/*! CFGNSSTCALIB - Non-Secure SysTick Calibration Configuration */
#define SIM_M33_CFGNSSTCALIB_CFGNSSTCALIB(x)     (((uint32_t)(((uint32_t)(x)) << SIM_M33_CFGNSSTCALIB_CFGNSSTCALIB_SHIFT)) & SIM_M33_CFGNSSTCALIB_CFGNSSTCALIB_MASK)
/*! @} */

/*! @name SAI_MULTISYNC_ENABLE_SELECTOR - SAI 0 to 3 Transmitter/Receiver Multi-Synchronous Enable Source */
/*! @{ */

#define SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI0_MULTISYNC_ENABLE_SELECTOR_MASK (0x7U)
#define SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI0_MULTISYNC_ENABLE_SELECTOR_SHIFT (0U)
/*! SAI0_MULTISYNC_ENABLE_SELECTOR - SAI0 Multi-sync Enable Source */
#define SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI0_MULTISYNC_ENABLE_SELECTOR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI0_MULTISYNC_ENABLE_SELECTOR_SHIFT)) & SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI0_MULTISYNC_ENABLE_SELECTOR_MASK)

#define SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI1_MULTISYNC_ENABLE_SELECTOR_MASK (0x700U)
#define SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI1_MULTISYNC_ENABLE_SELECTOR_SHIFT (8U)
/*! SAI1_MULTISYNC_ENABLE_SELECTOR - SAI1 Multi-Sync Enable Source */
#define SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI1_MULTISYNC_ENABLE_SELECTOR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI1_MULTISYNC_ENABLE_SELECTOR_SHIFT)) & SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI1_MULTISYNC_ENABLE_SELECTOR_MASK)

#define SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI2_MULTISYNC_ENABLE_SELECTOR_MASK (0x70000U)
#define SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI2_MULTISYNC_ENABLE_SELECTOR_SHIFT (16U)
/*! SAI2_MULTISYNC_ENABLE_SELECTOR - SAI2 Multi-Sync Enable Source */
#define SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI2_MULTISYNC_ENABLE_SELECTOR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI2_MULTISYNC_ENABLE_SELECTOR_SHIFT)) & SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI2_MULTISYNC_ENABLE_SELECTOR_MASK)

#define SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI3_MULTISYNC_ENABLE_SELECTOR_MASK (0x7000000U)
#define SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI3_MULTISYNC_ENABLE_SELECTOR_SHIFT (24U)
/*! SAI3_MULTISYNC_ENABLE_SELECTOR - SAI3 Multi-sync Enable Source */
#define SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI3_MULTISYNC_ENABLE_SELECTOR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI3_MULTISYNC_ENABLE_SELECTOR_SHIFT)) & SIM_SAI_MULTISYNC_ENABLE_SELECTOR_SAI3_MULTISYNC_ENABLE_SELECTOR_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SIM_Register_Masks */


/* SIM - Peripheral instance base addresses */
/** Peripheral SIM_RTD base address */
#define SIM_RTD_BASE                             (0x2802A000u)
/** Peripheral SIM_RTD base pointer */
#define SIM_RTD                                  ((SIM_Type *)SIM_RTD_BASE)
/** Array initializer of SIM peripheral base addresses */
#define SIM_BASE_ADDRS                           { SIM_RTD_BASE }
/** Array initializer of SIM peripheral base pointers */
#define SIM_BASE_PTRS                            { SIM_RTD }

/*!
 * @}
 */ /* end of group SIM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SIM_AD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SIM_AD_Peripheral_Access_Layer SIM_AD Peripheral Access Layer
 * @{
 */

/** SIM_AD - Register Layout Typedef */
typedef struct {
       uint32_t GPR0;                              /**< HW General Purpose Register 0, offset: 0x0 */
       uint32_t GPR1;                              /**< HW General Purpose Register 1, offset: 0x4 */
  __IO uint32_t DGO_CTRL0;                         /**< APD SIM DGO Control Register 0, offset: 0x8 */
  __IO uint32_t DGO_CTRL1;                         /**< APD SIM DGO Control Register 1, offset: 0xC */
  __IO uint32_t DGO_GP0;                           /**< APD SIM DGO General Purpose Register 0, offset: 0x10 */
  __IO uint32_t DGO_GP1;                           /**< APD SIM DGO General Purpose Register 1, offset: 0x14 */
  __IO uint32_t DGO_GP2;                           /**< APD SIM DGO General Purpose Register 2, offset: 0x18 */
       uint8_t RESERVED_0[4];
  __IO uint32_t DGO_GP3;                           /**< RESET1_B pad and Filter Configuration, offset: 0x20 */
  __IO uint32_t DGO_GP4;                           /**< PTE Operating Range Control, offset: 0x24 */
  __IO uint32_t DGO_GP5;                           /**< PTF Operating Range Control, offset: 0x28 */
       uint8_t RESERVED_1[4];
  __IO uint32_t SYSCTRL0;                          /**< Application Domain System Control Register 0, offset: 0x30 */
       uint8_t RESERVED_2[8];
  __IO uint32_t WKPU0_WAKEUP_EN;                   /**< WKPU0 Wake-up Enable Register, offset: 0x3C */
  __IO uint32_t WKPU1_WAKEUP_EN;                   /**< WKPU1 Wake-up Enable Register 1, offset: 0x40 */
  __IO uint32_t USB_WAKEUP;                        /**< USB Wake-up Control Register (DGO 10), offset: 0x44 */
  __IO uint32_t PTD_COMPCELL;                      /**< PTD Pads Compensation Cell Configuration Register, offset: 0x48 */
  __IO uint32_t TSTMR_CMP0_VAL_L;                  /**< Lower CA35 TS Timer First Compare Value, offset: 0x4C */
  __IO uint32_t TSTMR_CMP0_VAL_H;                  /**< Upper CA35 TS Timer First Compare Value, offset: 0x50 */
  __IO uint32_t TSTMR_CMP1_VAL_L;                  /**< Lower CA35 TS Timer Second Compare value, offset: 0x54 */
  __IO uint32_t TSTMR_CMP1_VAL_H;                  /**< Upper CA35 TS Timer Second Compare Value, offset: 0x58 */
  __IO uint32_t RVBARADDR0;                        /**< CA35 Core0 Reset Vector Base Address (DGO 8), offset: 0x5C */
  __IO uint32_t RVBARADDR1;                        /**< CA35 Core1 Reset Vector Base Address (DGO 9), offset: 0x60 */
  __IO uint32_t MQS1_CF;                           /**< Medium Quality Sound Configuration Register, offset: 0x64 */
  __IO uint32_t SAI_MULTISYNC_ENABLE_SELECTOR;     /**< SAI 4 and 5 Transmitter/Receiver Multi-Synchronous Enable Source, offset: 0x68 */
  __I  uint32_t CORE0_PMU_EVENT;                   /**< A35 Core0 Performance Monitoring Events, offset: 0x6C */
  __I  uint32_t CORE1_PMU_EVENT;                   /**< A35 Core1 Performance Monitoring Events, offset: 0x70 */
  __IO uint32_t DGO_GP6;                           /**< APD SIM DGO General Purpose Register 6, offset: 0x74 */
  __IO uint32_t DGO_GP7;                           /**< APD SIM DGO General Purpose Register 7, offset: 0x78 */
} SIM_AD_Type;

/* ----------------------------------------------------------------------------
   -- SIM_AD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SIM_AD_Register_Masks SIM_AD Register Masks
 * @{
 */

/*! @name DGO_CTRL0 - APD SIM DGO Control Register 0 */
/*! @{ */

#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP0_MASK     (0x1U)
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP0_SHIFT    (0U)
/*! UPDATE_DGO_GP0 - DGO General Purpose Register 0 Update */
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP0(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_UPDATE_DGO_GP0_SHIFT)) & SIM_AD_DGO_CTRL0_UPDATE_DGO_GP0_MASK)

#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP1_MASK     (0x2U)
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP1_SHIFT    (1U)
/*! UPDATE_DGO_GP1 - DGO General Purpose Register 1 Update */
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP1(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_UPDATE_DGO_GP1_SHIFT)) & SIM_AD_DGO_CTRL0_UPDATE_DGO_GP1_MASK)

#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP2_MASK     (0x4U)
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP2_SHIFT    (2U)
/*! UPDATE_DGO_GP2 - DGO General Purpose Register 2 Update */
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP2(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_UPDATE_DGO_GP2_SHIFT)) & SIM_AD_DGO_CTRL0_UPDATE_DGO_GP2_MASK)

#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP3_MASK     (0x8U)
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP3_SHIFT    (3U)
/*! UPDATE_DGO_GP3 - DGO General Purpose Register 3 Update */
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP3(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_UPDATE_DGO_GP3_SHIFT)) & SIM_AD_DGO_CTRL0_UPDATE_DGO_GP3_MASK)

#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP4_MASK     (0x10U)
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP4_SHIFT    (4U)
/*! UPDATE_DGO_GP4 - DGO General Purpose Register 4 Update */
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP4(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_UPDATE_DGO_GP4_SHIFT)) & SIM_AD_DGO_CTRL0_UPDATE_DGO_GP4_MASK)

#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP5_MASK     (0x20U)
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP5_SHIFT    (5U)
/*! UPDATE_DGO_GP5 - DGO General Purpose Register 5 Update */
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP5(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_UPDATE_DGO_GP5_SHIFT)) & SIM_AD_DGO_CTRL0_UPDATE_DGO_GP5_MASK)

#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP6_MASK     (0x40U)
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP6_SHIFT    (6U)
/*! UPDATE_DGO_GP6 - DGO General Purpose Register 6 Update */
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP6(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_UPDATE_DGO_GP6_SHIFT)) & SIM_AD_DGO_CTRL0_UPDATE_DGO_GP6_MASK)

#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP7_MASK     (0x80U)
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP7_SHIFT    (7U)
/*! UPDATE_DGO_GP7 - DGO General Purpose Register 7 Update */
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP7(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_UPDATE_DGO_GP7_SHIFT)) & SIM_AD_DGO_CTRL0_UPDATE_DGO_GP7_MASK)

#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP0_MASK     (0x100U)
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP0_SHIFT    (8U)
/*! WR_ACK_DGO_GP0 - DGO General Purpose Register 0 Write Acknowledge */
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP0(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP0_SHIFT)) & SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP0_MASK)

#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP1_MASK     (0x200U)
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP1_SHIFT    (9U)
/*! WR_ACK_DGO_GP1 - DGO General Purpose Register 1 Write Acknowledge */
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP1(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP1_SHIFT)) & SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP1_MASK)

#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP2_MASK     (0x400U)
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP2_SHIFT    (10U)
/*! WR_ACK_DGO_GP2 - DGO General Purpose Register 2 Write Acknowledge */
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP2(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP2_SHIFT)) & SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP2_MASK)

#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP3_MASK     (0x800U)
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP3_SHIFT    (11U)
/*! WR_ACK_DGO_GP3 - DGO General Purpose Register 3 Write Acknowledge */
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP3(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP3_SHIFT)) & SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP3_MASK)

#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP4_MASK     (0x1000U)
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP4_SHIFT    (12U)
/*! WR_ACK_DGO_GP4 - DGO General Purpose Register 2 Write Acknowledge */
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP4(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP4_SHIFT)) & SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP4_MASK)

#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP5_MASK     (0x2000U)
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP5_SHIFT    (13U)
/*! WR_ACK_DGO_GP5 - DGO General Purpose Register 5 Write Acknowledge */
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP5(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP5_SHIFT)) & SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP5_MASK)

#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP6_MASK     (0x4000U)
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP6_SHIFT    (14U)
/*! WR_ACK_DGO_GP6 - DGO General Purpose Register 6 Write Acknowledge */
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP6(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP6_SHIFT)) & SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP6_MASK)

#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP7_MASK     (0x8000U)
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP7_SHIFT    (15U)
/*! WR_ACK_DGO_GP7 - DGO General Purpose Register 7 Write Acknowledge */
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP7(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP7_SHIFT)) & SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP7_MASK)

#define SIM_AD_DGO_CTRL0_INT_EN_ACK0_MASK        (0x10000U)
#define SIM_AD_DGO_CTRL0_INT_EN_ACK0_SHIFT       (16U)
/*! INT_EN_ACK0 - DGO General Purpose Register 0 Interrupt Acknowledge */
#define SIM_AD_DGO_CTRL0_INT_EN_ACK0(x)          (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_INT_EN_ACK0_SHIFT)) & SIM_AD_DGO_CTRL0_INT_EN_ACK0_MASK)

#define SIM_AD_DGO_CTRL0_INT_EN_ACK1_MASK        (0x20000U)
#define SIM_AD_DGO_CTRL0_INT_EN_ACK1_SHIFT       (17U)
/*! INT_EN_ACK1 - DGO General Purpose Register 1 Interrupt Acknowledge */
#define SIM_AD_DGO_CTRL0_INT_EN_ACK1(x)          (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_INT_EN_ACK1_SHIFT)) & SIM_AD_DGO_CTRL0_INT_EN_ACK1_MASK)

#define SIM_AD_DGO_CTRL0_INT_EN_ACK2_MASK        (0x40000U)
#define SIM_AD_DGO_CTRL0_INT_EN_ACK2_SHIFT       (18U)
/*! INT_EN_ACK2 - DGO General Purpose Register 2 Interrupt Acknowledge */
#define SIM_AD_DGO_CTRL0_INT_EN_ACK2(x)          (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_INT_EN_ACK2_SHIFT)) & SIM_AD_DGO_CTRL0_INT_EN_ACK2_MASK)

#define SIM_AD_DGO_CTRL0_INT_EN_ACK3_MASK        (0x80000U)
#define SIM_AD_DGO_CTRL0_INT_EN_ACK3_SHIFT       (19U)
/*! INT_EN_ACK3 - DGO General Purpose Register 3 Interrupt Acknowledge */
#define SIM_AD_DGO_CTRL0_INT_EN_ACK3(x)          (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_INT_EN_ACK3_SHIFT)) & SIM_AD_DGO_CTRL0_INT_EN_ACK3_MASK)

#define SIM_AD_DGO_CTRL0_INT_EN_ACK4_MASK        (0x100000U)
#define SIM_AD_DGO_CTRL0_INT_EN_ACK4_SHIFT       (20U)
/*! INT_EN_ACK4 - DGO General Purpose Register 4 Interrupt Acknowledge */
#define SIM_AD_DGO_CTRL0_INT_EN_ACK4(x)          (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_INT_EN_ACK4_SHIFT)) & SIM_AD_DGO_CTRL0_INT_EN_ACK4_MASK)

#define SIM_AD_DGO_CTRL0_INT_EN_ACK5_MASK        (0x200000U)
#define SIM_AD_DGO_CTRL0_INT_EN_ACK5_SHIFT       (21U)
/*! INT_EN_ACK5 - DGO General Purpose Register 5 Interrupt Acknowledge */
#define SIM_AD_DGO_CTRL0_INT_EN_ACK5(x)          (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_INT_EN_ACK5_SHIFT)) & SIM_AD_DGO_CTRL0_INT_EN_ACK5_MASK)

#define SIM_AD_DGO_CTRL0_INT_EN_ACK6_MASK        (0x400000U)
#define SIM_AD_DGO_CTRL0_INT_EN_ACK6_SHIFT       (22U)
/*! INT_EN_ACK6 - DGO General Purpose Register 6 Interrupt Acknowledge */
#define SIM_AD_DGO_CTRL0_INT_EN_ACK6(x)          (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_INT_EN_ACK6_SHIFT)) & SIM_AD_DGO_CTRL0_INT_EN_ACK6_MASK)

#define SIM_AD_DGO_CTRL0_INT_EN_ACK7_MASK        (0x800000U)
#define SIM_AD_DGO_CTRL0_INT_EN_ACK7_SHIFT       (23U)
/*! INT_EN_ACK7 - DGO General Purpose Register 7 Interrupt Acknowledge */
#define SIM_AD_DGO_CTRL0_INT_EN_ACK7(x)          (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_INT_EN_ACK7_SHIFT)) & SIM_AD_DGO_CTRL0_INT_EN_ACK7_MASK)

#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP8_MASK     (0x1000000U)
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP8_SHIFT    (24U)
/*! UPDATE_DGO_GP8 - DGO General Purpose Register 8 Update (RVBARADDR0) */
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP8(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_UPDATE_DGO_GP8_SHIFT)) & SIM_AD_DGO_CTRL0_UPDATE_DGO_GP8_MASK)

#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP9_MASK     (0x2000000U)
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP9_SHIFT    (25U)
/*! UPDATE_DGO_GP9 - DGO General Purpose Register 9 Update (RVBARADDR1) */
#define SIM_AD_DGO_CTRL0_UPDATE_DGO_GP9(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_UPDATE_DGO_GP9_SHIFT)) & SIM_AD_DGO_CTRL0_UPDATE_DGO_GP9_MASK)

#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP8_MASK     (0x4000000U)
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP8_SHIFT    (26U)
/*! WR_ACK_DGO_GP8 - DGO General Purpose Register 8 Write Acknowledge (RVBARADDR0) */
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP8(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP8_SHIFT)) & SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP8_MASK)

#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP9_MASK     (0x8000000U)
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP9_SHIFT    (27U)
/*! WR_ACK_DGO_GP9 - DGO General Purpose Register 9 Write Acknowledge (RVBARADDR1) */
#define SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP9(x)       (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP9_SHIFT)) & SIM_AD_DGO_CTRL0_WR_ACK_DGO_GP9_MASK)

#define SIM_AD_DGO_CTRL0_INT_EN_ACK8_MASK        (0x10000000U)
#define SIM_AD_DGO_CTRL0_INT_EN_ACK8_SHIFT       (28U)
/*! INT_EN_ACK8 - DGO General Purpose Register 8 Interrupt Acknowledge (RVBARADDR0) */
#define SIM_AD_DGO_CTRL0_INT_EN_ACK8(x)          (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_INT_EN_ACK8_SHIFT)) & SIM_AD_DGO_CTRL0_INT_EN_ACK8_MASK)

#define SIM_AD_DGO_CTRL0_INT_EN_ACK9_MASK        (0x20000000U)
#define SIM_AD_DGO_CTRL0_INT_EN_ACK9_SHIFT       (29U)
/*! INT_EN_ACK9 - DGO General Purpose Register 9 Interrupt Acknowledge (RVBARADDR1) */
#define SIM_AD_DGO_CTRL0_INT_EN_ACK9(x)          (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL0_INT_EN_ACK9_SHIFT)) & SIM_AD_DGO_CTRL0_INT_EN_ACK9_MASK)
/*! @} */

/*! @name DGO_CTRL1 - APD SIM DGO Control Register 1 */
/*! @{ */

#define SIM_AD_DGO_CTRL1_UPDATE_DGO_GP10_MASK    (0x1U)
#define SIM_AD_DGO_CTRL1_UPDATE_DGO_GP10_SHIFT   (0U)
/*! UPDATE_DGO_GP10 - DGO General Purpose Register 10 Update (USB_WAKEUP) */
#define SIM_AD_DGO_CTRL1_UPDATE_DGO_GP10(x)      (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL1_UPDATE_DGO_GP10_SHIFT)) & SIM_AD_DGO_CTRL1_UPDATE_DGO_GP10_MASK)

#define SIM_AD_DGO_CTRL1_WR_ACK_DGO_GP10_MASK    (0x2U)
#define SIM_AD_DGO_CTRL1_WR_ACK_DGO_GP10_SHIFT   (1U)
/*! WR_ACK_DGO_GP10 - DGO General Purpose Register 10 Write Acknowledge (USB_WAKEUP) */
#define SIM_AD_DGO_CTRL1_WR_ACK_DGO_GP10(x)      (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL1_WR_ACK_DGO_GP10_SHIFT)) & SIM_AD_DGO_CTRL1_WR_ACK_DGO_GP10_MASK)

#define SIM_AD_DGO_CTRL1_INT_EN_ACK10_MASK       (0x4U)
#define SIM_AD_DGO_CTRL1_INT_EN_ACK10_SHIFT      (2U)
/*! INT_EN_ACK10 - DGO General Purpose Register 10 Interrupt Acknowledge (USB_WAKEUP) */
#define SIM_AD_DGO_CTRL1_INT_EN_ACK10(x)         (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_CTRL1_INT_EN_ACK10_SHIFT)) & SIM_AD_DGO_CTRL1_INT_EN_ACK10_MASK)
/*! @} */

/*! @name DGO_GP0 - APD SIM DGO General Purpose Register 0 */
/*! @{ */

#define SIM_AD_DGO_GP0_SIM_DGO_GP0_MASK          (0xFFFFFFFFU)
#define SIM_AD_DGO_GP0_SIM_DGO_GP0_SHIFT         (0U)
/*! SIM_DGO_GP0 - SIM DGO General purpose register 0 */
#define SIM_AD_DGO_GP0_SIM_DGO_GP0(x)            (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP0_SIM_DGO_GP0_SHIFT)) & SIM_AD_DGO_GP0_SIM_DGO_GP0_MASK)
/*! @} */

/*! @name DGO_GP1 - APD SIM DGO General Purpose Register 1 */
/*! @{ */

#define SIM_AD_DGO_GP1_SIM_DGO_GP1_MASK          (0xFFFFFFFFU)
#define SIM_AD_DGO_GP1_SIM_DGO_GP1_SHIFT         (0U)
/*! SIM_DGO_GP1 - SIM DGO General Purpose Register 1 */
#define SIM_AD_DGO_GP1_SIM_DGO_GP1(x)            (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP1_SIM_DGO_GP1_SHIFT)) & SIM_AD_DGO_GP1_SIM_DGO_GP1_MASK)
/*! @} */

/*! @name DGO_GP2 - APD SIM DGO General Purpose Register 2 */
/*! @{ */

#define SIM_AD_DGO_GP2_SIM_DGO_GP2_MASK          (0xFFFFFFFFU)
#define SIM_AD_DGO_GP2_SIM_DGO_GP2_SHIFT         (0U)
/*! SIM_DGO_GP2 - SIM DGO General Purpose Register 2 */
#define SIM_AD_DGO_GP2_SIM_DGO_GP2(x)            (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP2_SIM_DGO_GP2_SHIFT)) & SIM_AD_DGO_GP2_SIM_DGO_GP2_MASK)
/*! @} */

/*! @name DGO_GP3 - RESET1_B pad and Filter Configuration */
/*! @{ */

#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_PS_MASK   (0x1U)
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_PS_SHIFT  (0U)
/*! RESET1_B_CONFIG_PS - Weak Pull Select */
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_PS(x)     (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP3_RESET1_B_CONFIG_PS_SHIFT)) & SIM_AD_DGO_GP3_RESET1_B_CONFIG_PS_MASK)

#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_PE_MASK   (0x2U)
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_PE_SHIFT  (1U)
/*! RESET1_B_CONFIG_PE - Weak Pull Enable */
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_PE(x)     (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP3_RESET1_B_CONFIG_PE_SHIFT)) & SIM_AD_DGO_GP3_RESET1_B_CONFIG_PE_MASK)

#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_SRE_MASK  (0x4U)
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_SRE_SHIFT (2U)
/*! RESET1_B_CONFIG_SRE - Slew Rate Enable */
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_SRE(x)    (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP3_RESET1_B_CONFIG_SRE_SHIFT)) & SIM_AD_DGO_GP3_RESET1_B_CONFIG_SRE_MASK)

#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_PFE_MASK  (0x10U)
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_PFE_SHIFT (4U)
/*! RESET1_B_CONFIG_PFE - Passive Filter Enable */
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_PFE(x)    (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP3_RESET1_B_CONFIG_PFE_SHIFT)) & SIM_AD_DGO_GP3_RESET1_B_CONFIG_PFE_MASK)

#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_ODE_MASK  (0x20U)
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_ODE_SHIFT (5U)
/*! RESET1_B_CONFIG_ODE - Open Drain Enable */
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_ODE(x)    (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP3_RESET1_B_CONFIG_ODE_SHIFT)) & SIM_AD_DGO_GP3_RESET1_B_CONFIG_ODE_MASK)

#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_DSE_MASK  (0x40U)
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_DSE_SHIFT (6U)
/*! RESET1_B_CONFIG_DSE - Drive Strength Enable */
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_DSE(x)    (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP3_RESET1_B_CONFIG_DSE_SHIFT)) & SIM_AD_DGO_GP3_RESET1_B_CONFIG_DSE_MASK)

#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_LK_MASK   (0x8000U)
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_LK_SHIFT  (15U)
/*! RESET1_B_CONFIG_LK - Locks Writes to This Register */
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_LK(x)     (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP3_RESET1_B_CONFIG_LK_SHIFT)) & SIM_AD_DGO_GP3_RESET1_B_CONFIG_LK_MASK)

#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFE_MASK  (0x100000U)
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFE_SHIFT (20U)
/*! RESET1_B_CONFIG_DFE - Digital Filter Enable */
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFE(x)    (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFE_SHIFT)) & SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFE_MASK)

#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFCS_MASK (0x200000U)
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFCS_SHIFT (21U)
/*! RESET1_B_CONFIG_DFCS - Digital Filter Clock Select */
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFCS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFCS_SHIFT)) & SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFCS_MASK)

#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFD_MASK  (0xFC00000U)
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFD_SHIFT (22U)
/*! RESET1_B_CONFIG_DFD - Digital Filter Duration by Defining Deglitch Count */
#define SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFD(x)    (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFD_SHIFT)) & SIM_AD_DGO_GP3_RESET1_B_CONFIG_DFD_MASK)
/*! @} */

/*! @name DGO_GP4 - PTE Operating Range Control */
/*! @{ */

#define SIM_AD_DGO_GP4_PTE_OPERATING_RANGE_MASK  (0x3U)
#define SIM_AD_DGO_GP4_PTE_OPERATING_RANGE_SHIFT (0U)
/*! PTE_OPERATING_RANGE - PTE Operating Range (Write Once) */
#define SIM_AD_DGO_GP4_PTE_OPERATING_RANGE(x)    (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP4_PTE_OPERATING_RANGE_SHIFT)) & SIM_AD_DGO_GP4_PTE_OPERATING_RANGE_MASK)
/*! @} */

/*! @name DGO_GP5 - PTF Operating Range Control */
/*! @{ */

#define SIM_AD_DGO_GP5_PTF_OPERATING_RANGE_MASK  (0x3U)
#define SIM_AD_DGO_GP5_PTF_OPERATING_RANGE_SHIFT (0U)
/*! PTF_OPERATING_RANGE - PTF Operating Range (Write Once) */
#define SIM_AD_DGO_GP5_PTF_OPERATING_RANGE(x)    (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP5_PTF_OPERATING_RANGE_SHIFT)) & SIM_AD_DGO_GP5_PTF_OPERATING_RANGE_MASK)
/*! @} */

/*! @name SYSCTRL0 - Application Domain System Control Register 0 */
/*! @{ */

#define SIM_AD_SYSCTRL0_L2_CACHE_CONTROL_MASK    (0x10U)
#define SIM_AD_SYSCTRL0_L2_CACHE_CONTROL_SHIFT   (4U)
/*! L2_CACHE_CONTROL - L2 Cache Control */
#define SIM_AD_SYSCTRL0_L2_CACHE_CONTROL(x)      (((uint32_t)(((uint32_t)(x)) << SIM_AD_SYSCTRL0_L2_CACHE_CONTROL_SHIFT)) & SIM_AD_SYSCTRL0_L2_CACHE_CONTROL_MASK)

#define SIM_AD_SYSCTRL0_L2_CACHE_RST_DISABLE_MASK (0x20U)
#define SIM_AD_SYSCTRL0_L2_CACHE_RST_DISABLE_SHIFT (5U)
/*! L2_CACHE_RST_DISABLE - L2 Cache Reset Disable */
#define SIM_AD_SYSCTRL0_L2_CACHE_RST_DISABLE(x)  (((uint32_t)(((uint32_t)(x)) << SIM_AD_SYSCTRL0_L2_CACHE_RST_DISABLE_SHIFT)) & SIM_AD_SYSCTRL0_L2_CACHE_RST_DISABLE_MASK)

#define SIM_AD_SYSCTRL0_A35_SMPEN_MASK           (0xC0U)
#define SIM_AD_SYSCTRL0_A35_SMPEN_SHIFT          (6U)
/*! A35_SMPEN - Status Register to Indicate Whether a Core is Taking Part in Coherency. */
#define SIM_AD_SYSCTRL0_A35_SMPEN(x)             (((uint32_t)(((uint32_t)(x)) << SIM_AD_SYSCTRL0_A35_SMPEN_SHIFT)) & SIM_AD_SYSCTRL0_A35_SMPEN_MASK)

#define SIM_AD_SYSCTRL0_WDOG4_RESET_EN_MASK      (0x100U)
#define SIM_AD_SYSCTRL0_WDOG4_RESET_EN_SHIFT     (8U)
/*! WDOG4_RESET_EN - Watchdog 4 Reset Enable */
#define SIM_AD_SYSCTRL0_WDOG4_RESET_EN(x)        (((uint32_t)(((uint32_t)(x)) << SIM_AD_SYSCTRL0_WDOG4_RESET_EN_SHIFT)) & SIM_AD_SYSCTRL0_WDOG4_RESET_EN_MASK)

#define SIM_AD_SYSCTRL0_A35_COLD_RESET_MASK      (0x10000U)
#define SIM_AD_SYSCTRL0_A35_COLD_RESET_SHIFT     (16U)
/*! A35_COLD_RESET - CA35 Cold Reset */
#define SIM_AD_SYSCTRL0_A35_COLD_RESET(x)        (((uint32_t)(((uint32_t)(x)) << SIM_AD_SYSCTRL0_A35_COLD_RESET_SHIFT)) & SIM_AD_SYSCTRL0_A35_COLD_RESET_MASK)

#define SIM_AD_SYSCTRL0_AD_SW_RST_MASK           (0x20000U)
#define SIM_AD_SYSCTRL0_AD_SW_RST_SHIFT          (17U)
/*! AD_SW_RST - Enables Application Domain Software Reset */
#define SIM_AD_SYSCTRL0_AD_SW_RST(x)             (((uint32_t)(((uint32_t)(x)) << SIM_AD_SYSCTRL0_AD_SW_RST_SHIFT)) & SIM_AD_SYSCTRL0_AD_SW_RST_MASK)

#define SIM_AD_SYSCTRL0_TSTMR_SEL_MASK           (0x8000000U)
#define SIM_AD_SYSCTRL0_TSTMR_SEL_SHIFT          (27U)
/*! TSTMR_SEL - CA35 Timer Select */
#define SIM_AD_SYSCTRL0_TSTMR_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SIM_AD_SYSCTRL0_TSTMR_SEL_SHIFT)) & SIM_AD_SYSCTRL0_TSTMR_SEL_MASK)

#define SIM_AD_SYSCTRL0_TSTMR_COMP0_EN_MASK      (0x10000000U)
#define SIM_AD_SYSCTRL0_TSTMR_COMP0_EN_SHIFT     (28U)
/*! TSTMR_COMP0_EN - Enables the Compare of CA35 TS Timer Versus The First Programmed Value. */
#define SIM_AD_SYSCTRL0_TSTMR_COMP0_EN(x)        (((uint32_t)(((uint32_t)(x)) << SIM_AD_SYSCTRL0_TSTMR_COMP0_EN_SHIFT)) & SIM_AD_SYSCTRL0_TSTMR_COMP0_EN_MASK)

#define SIM_AD_SYSCTRL0_TSTMR_COMP0_IRQ_CTRL_MASK (0x20000000U)
#define SIM_AD_SYSCTRL0_TSTMR_COMP0_IRQ_CTRL_SHIFT (29U)
/*! TSTMR_COMP0_IRQ_CTRL - Controls the First Compare of CA35 Reset as IRQ. */
#define SIM_AD_SYSCTRL0_TSTMR_COMP0_IRQ_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SIM_AD_SYSCTRL0_TSTMR_COMP0_IRQ_CTRL_SHIFT)) & SIM_AD_SYSCTRL0_TSTMR_COMP0_IRQ_CTRL_MASK)

#define SIM_AD_SYSCTRL0_TSTMR_COMP1_EN_MASK      (0x40000000U)
#define SIM_AD_SYSCTRL0_TSTMR_COMP1_EN_SHIFT     (30U)
/*! TSTMR_COMP1_EN - Enables the Compare of CA35 TS Timer Versus Second Programmed Value. */
#define SIM_AD_SYSCTRL0_TSTMR_COMP1_EN(x)        (((uint32_t)(((uint32_t)(x)) << SIM_AD_SYSCTRL0_TSTMR_COMP1_EN_SHIFT)) & SIM_AD_SYSCTRL0_TSTMR_COMP1_EN_MASK)

#define SIM_AD_SYSCTRL0_TSTMR_COMP1_IRQ_CTRL_MASK (0x80000000U)
#define SIM_AD_SYSCTRL0_TSTMR_COMP1_IRQ_CTRL_SHIFT (31U)
/*! TSTMR_COMP1_IRQ_CTRL - Controls the Second Compare of CA35 Reset as IRQ. */
#define SIM_AD_SYSCTRL0_TSTMR_COMP1_IRQ_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << SIM_AD_SYSCTRL0_TSTMR_COMP1_IRQ_CTRL_SHIFT)) & SIM_AD_SYSCTRL0_TSTMR_COMP1_IRQ_CTRL_MASK)
/*! @} */

/*! @name WKPU0_WAKEUP_EN - WKPU0 Wake-up Enable Register */
/*! @{ */

#define SIM_AD_WKPU0_WAKEUP_EN_WKPU0_WAKEUP_EN_MASK (0xFFFFFFFFU)
#define SIM_AD_WKPU0_WAKEUP_EN_WKPU0_WAKEUP_EN_SHIFT (0U)
/*! WKPU0_WAKEUP_EN - Wake-up Enable Bits for WKPU0 Channels */
#define SIM_AD_WKPU0_WAKEUP_EN_WKPU0_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_WKPU0_WAKEUP_EN_WKPU0_WAKEUP_EN_SHIFT)) & SIM_AD_WKPU0_WAKEUP_EN_WKPU0_WAKEUP_EN_MASK)
/*! @} */

/*! @name WKPU1_WAKEUP_EN - WKPU1 Wake-up Enable Register 1 */
/*! @{ */

#define SIM_AD_WKPU1_WAKEUP_EN_WKPU1_WAKEUP_EN_MASK (0xFFFFFFFFU)
#define SIM_AD_WKPU1_WAKEUP_EN_WKPU1_WAKEUP_EN_SHIFT (0U)
/*! WKPU1_WAKEUP_EN - Wake-up Enable Bits for WKPU1 Channels */
#define SIM_AD_WKPU1_WAKEUP_EN_WKPU1_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_WKPU1_WAKEUP_EN_WKPU1_WAKEUP_EN_SHIFT)) & SIM_AD_WKPU1_WAKEUP_EN_WKPU1_WAKEUP_EN_MASK)
/*! @} */

/*! @name USB_WAKEUP - USB Wake-up Control Register (DGO 10) */
/*! @{ */

#define SIM_AD_USB_WAKEUP_USB0_PHY_WAKEUP_ISO_DISABLE_MASK (0x1U)
#define SIM_AD_USB_WAKEUP_USB0_PHY_WAKEUP_ISO_DISABLE_SHIFT (0U)
/*! USB0_PHY_WAKEUP_ISO_DISABLE - USB0 Wake-up ISO Disable */
#define SIM_AD_USB_WAKEUP_USB0_PHY_WAKEUP_ISO_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_USB_WAKEUP_USB0_PHY_WAKEUP_ISO_DISABLE_SHIFT)) & SIM_AD_USB_WAKEUP_USB0_PHY_WAKEUP_ISO_DISABLE_MASK)

#define SIM_AD_USB_WAKEUP_USB1_PHY_WAKEUP_ISO_DISABLE_MASK (0x2U)
#define SIM_AD_USB_WAKEUP_USB1_PHY_WAKEUP_ISO_DISABLE_SHIFT (1U)
/*! USB1_PHY_WAKEUP_ISO_DISABLE - USB1 Wake-up ISO Disable */
#define SIM_AD_USB_WAKEUP_USB1_PHY_WAKEUP_ISO_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_USB_WAKEUP_USB1_PHY_WAKEUP_ISO_DISABLE_SHIFT)) & SIM_AD_USB_WAKEUP_USB1_PHY_WAKEUP_ISO_DISABLE_MASK)

#define SIM_AD_USB_WAKEUP_USB0_PHY_NON_DPD_WAKEUP_EN_MASK (0x4U)
#define SIM_AD_USB_WAKEUP_USB0_PHY_NON_DPD_WAKEUP_EN_SHIFT (2U)
/*! USB0_PHY_NON_DPD_WAKEUP_EN - USB0 Non Deep Power Down Wake-up Enable */
#define SIM_AD_USB_WAKEUP_USB0_PHY_NON_DPD_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_USB_WAKEUP_USB0_PHY_NON_DPD_WAKEUP_EN_SHIFT)) & SIM_AD_USB_WAKEUP_USB0_PHY_NON_DPD_WAKEUP_EN_MASK)

#define SIM_AD_USB_WAKEUP_USB1_PHY_NON_DPD_WAKEUP_EN_MASK (0x8U)
#define SIM_AD_USB_WAKEUP_USB1_PHY_NON_DPD_WAKEUP_EN_SHIFT (3U)
/*! USB1_PHY_NON_DPD_WAKEUP_EN - USB1 Non Deep Power Down Wake-up Enable */
#define SIM_AD_USB_WAKEUP_USB1_PHY_NON_DPD_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_USB_WAKEUP_USB1_PHY_NON_DPD_WAKEUP_EN_SHIFT)) & SIM_AD_USB_WAKEUP_USB1_PHY_NON_DPD_WAKEUP_EN_MASK)

#define SIM_AD_USB_WAKEUP_USB0_PHY_DPD_WAKEUP_EN_MASK (0x10U)
#define SIM_AD_USB_WAKEUP_USB0_PHY_DPD_WAKEUP_EN_SHIFT (4U)
/*! USB0_PHY_DPD_WAKEUP_EN - USB0 Deep Power Down Wake-up Enable */
#define SIM_AD_USB_WAKEUP_USB0_PHY_DPD_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_USB_WAKEUP_USB0_PHY_DPD_WAKEUP_EN_SHIFT)) & SIM_AD_USB_WAKEUP_USB0_PHY_DPD_WAKEUP_EN_MASK)

#define SIM_AD_USB_WAKEUP_USB1_PHY_DPD_WAKEUP_EN_MASK (0x20U)
#define SIM_AD_USB_WAKEUP_USB1_PHY_DPD_WAKEUP_EN_SHIFT (5U)
/*! USB1_PHY_DPD_WAKEUP_EN - USB1 Deep Power Down Wake-up Enable */
#define SIM_AD_USB_WAKEUP_USB1_PHY_DPD_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_USB_WAKEUP_USB1_PHY_DPD_WAKEUP_EN_SHIFT)) & SIM_AD_USB_WAKEUP_USB1_PHY_DPD_WAKEUP_EN_MASK)
/*! @} */

/*! @name PTD_COMPCELL - PTD Pads Compensation Cell Configuration Register */
/*! @{ */

#define SIM_AD_PTD_COMPCELL_RASRCN_MASK          (0xFU)
#define SIM_AD_PTD_COMPCELL_RASRCN_SHIFT         (0U)
/*! RASRCN - Defines Pads Driver NMOS Transistors Compensation Code */
#define SIM_AD_PTD_COMPCELL_RASRCN(x)            (((uint32_t)(((uint32_t)(x)) << SIM_AD_PTD_COMPCELL_RASRCN_SHIFT)) & SIM_AD_PTD_COMPCELL_RASRCN_MASK)

#define SIM_AD_PTD_COMPCELL_RASRCP_MASK          (0xF0U)
#define SIM_AD_PTD_COMPCELL_RASRCP_SHIFT         (4U)
/*! RASRCP - Defines Pads Driver PMOS Transistors Compensation Code */
#define SIM_AD_PTD_COMPCELL_RASRCP(x)            (((uint32_t)(((uint32_t)(x)) << SIM_AD_PTD_COMPCELL_RASRCP_SHIFT)) & SIM_AD_PTD_COMPCELL_RASRCP_MASK)

#define SIM_AD_PTD_COMPCELL_SLEEP_MASK           (0x800U)
#define SIM_AD_PTD_COMPCELL_SLEEP_SHIFT          (11U)
/*! SLEEP - Enables SLEEP mode */
#define SIM_AD_PTD_COMPCELL_SLEEP(x)             (((uint32_t)(((uint32_t)(x)) << SIM_AD_PTD_COMPCELL_SLEEP_SHIFT)) & SIM_AD_PTD_COMPCELL_SLEEP_MASK)

#define SIM_AD_PTD_COMPCELL_FASTFREEZE_MASK      (0x1000U)
#define SIM_AD_PTD_COMPCELL_FASTFREEZE_SHIFT     (12U)
/*! FASTFREEZE - Enables Fast Freeze Mode */
#define SIM_AD_PTD_COMPCELL_FASTFREEZE(x)        (((uint32_t)(((uint32_t)(x)) << SIM_AD_PTD_COMPCELL_FASTFREEZE_SHIFT)) & SIM_AD_PTD_COMPCELL_FASTFREEZE_MASK)

#define SIM_AD_PTD_COMPCELL_FREEZE_MASK          (0x2000U)
#define SIM_AD_PTD_COMPCELL_FREEZE_SHIFT         (13U)
/*! FREEZE - Enables Freeze Mode */
#define SIM_AD_PTD_COMPCELL_FREEZE(x)            (((uint32_t)(((uint32_t)(x)) << SIM_AD_PTD_COMPCELL_FREEZE_SHIFT)) & SIM_AD_PTD_COMPCELL_FREEZE_MASK)

#define SIM_AD_PTD_COMPCELL_COMTQ_MASK           (0x4000U)
#define SIM_AD_PTD_COMPCELL_COMTQ_SHIFT          (14U)
/*! COMTQ - Compensation TQ */
#define SIM_AD_PTD_COMPCELL_COMTQ(x)             (((uint32_t)(((uint32_t)(x)) << SIM_AD_PTD_COMPCELL_COMTQ_SHIFT)) & SIM_AD_PTD_COMPCELL_COMTQ_MASK)

#define SIM_AD_PTD_COMPCELL_COMPE_MASK           (0x8000U)
#define SIM_AD_PTD_COMPCELL_COMPE_SHIFT          (15U)
/*! COMPE - Compensation Status */
#define SIM_AD_PTD_COMPCELL_COMPE(x)             (((uint32_t)(((uint32_t)(x)) << SIM_AD_PTD_COMPCELL_COMPE_SHIFT)) & SIM_AD_PTD_COMPCELL_COMPE_MASK)

#define SIM_AD_PTD_COMPCELL_NASRCN_MASK          (0xF0000U)
#define SIM_AD_PTD_COMPCELL_NASRCN_SHIFT         (16U)
/*! NASRCN - Generated Pads Driver NMOS Transistors Compensation Code */
#define SIM_AD_PTD_COMPCELL_NASRCN(x)            (((uint32_t)(((uint32_t)(x)) << SIM_AD_PTD_COMPCELL_NASRCN_SHIFT)) & SIM_AD_PTD_COMPCELL_NASRCN_MASK)

#define SIM_AD_PTD_COMPCELL_NASRCP_MASK          (0xF00000U)
#define SIM_AD_PTD_COMPCELL_NASRCP_SHIFT         (20U)
/*! NASRCP - Generated Pads Driver PMOS Transistors Compensation Code */
#define SIM_AD_PTD_COMPCELL_NASRCP(x)            (((uint32_t)(((uint32_t)(x)) << SIM_AD_PTD_COMPCELL_NASRCP_SHIFT)) & SIM_AD_PTD_COMPCELL_NASRCP_MASK)

#define SIM_AD_PTD_COMPCELL_COMPOK_MASK          (0x80000000U)
#define SIM_AD_PTD_COMPCELL_COMPOK_SHIFT         (31U)
/*! COMPOK - Compensation OK */
#define SIM_AD_PTD_COMPCELL_COMPOK(x)            (((uint32_t)(((uint32_t)(x)) << SIM_AD_PTD_COMPCELL_COMPOK_SHIFT)) & SIM_AD_PTD_COMPCELL_COMPOK_MASK)
/*! @} */

/*! @name TSTMR_CMP0_VAL_L - Lower CA35 TS Timer First Compare Value */
/*! @{ */

#define SIM_AD_TSTMR_CMP0_VAL_L_TSTMR_CMP_VAL_L_MASK (0xFFFFFFFFU)
#define SIM_AD_TSTMR_CMP0_VAL_L_TSTMR_CMP_VAL_L_SHIFT (0U)
/*! TSTMR_CMP_VAL_L - Lower CA35 TS Timer Compare Value */
#define SIM_AD_TSTMR_CMP0_VAL_L_TSTMR_CMP_VAL_L(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_TSTMR_CMP0_VAL_L_TSTMR_CMP_VAL_L_SHIFT)) & SIM_AD_TSTMR_CMP0_VAL_L_TSTMR_CMP_VAL_L_MASK)
/*! @} */

/*! @name TSTMR_CMP0_VAL_H - Upper CA35 TS Timer First Compare Value */
/*! @{ */

#define SIM_AD_TSTMR_CMP0_VAL_H_TSTMR_CMP_VAL_H_MASK (0xFFFFFFFFU)
#define SIM_AD_TSTMR_CMP0_VAL_H_TSTMR_CMP_VAL_H_SHIFT (0U)
/*! TSTMR_CMP_VAL_H - Upper CA35 TS Timer Compare value */
#define SIM_AD_TSTMR_CMP0_VAL_H_TSTMR_CMP_VAL_H(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_TSTMR_CMP0_VAL_H_TSTMR_CMP_VAL_H_SHIFT)) & SIM_AD_TSTMR_CMP0_VAL_H_TSTMR_CMP_VAL_H_MASK)
/*! @} */

/*! @name TSTMR_CMP1_VAL_L - Lower CA35 TS Timer Second Compare value */
/*! @{ */

#define SIM_AD_TSTMR_CMP1_VAL_L_TSTMR_CMP_VAL_L_MASK (0xFFFFFFFFU)
#define SIM_AD_TSTMR_CMP1_VAL_L_TSTMR_CMP_VAL_L_SHIFT (0U)
/*! TSTMR_CMP_VAL_L - Lower CA35 TS Timer Compare Value */
#define SIM_AD_TSTMR_CMP1_VAL_L_TSTMR_CMP_VAL_L(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_TSTMR_CMP1_VAL_L_TSTMR_CMP_VAL_L_SHIFT)) & SIM_AD_TSTMR_CMP1_VAL_L_TSTMR_CMP_VAL_L_MASK)
/*! @} */

/*! @name TSTMR_CMP1_VAL_H - Upper CA35 TS Timer Second Compare Value */
/*! @{ */

#define SIM_AD_TSTMR_CMP1_VAL_H_TSTMR_CMP_VAL_H_MASK (0xFFFFFFFFU)
#define SIM_AD_TSTMR_CMP1_VAL_H_TSTMR_CMP_VAL_H_SHIFT (0U)
/*! TSTMR_CMP_VAL_H - Upper CA35 TS Timer Compare Value */
#define SIM_AD_TSTMR_CMP1_VAL_H_TSTMR_CMP_VAL_H(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_TSTMR_CMP1_VAL_H_TSTMR_CMP_VAL_H_SHIFT)) & SIM_AD_TSTMR_CMP1_VAL_H_TSTMR_CMP_VAL_H_MASK)
/*! @} */

/*! @name RVBARADDR0 - CA35 Core0 Reset Vector Base Address (DGO 8) */
/*! @{ */

#define SIM_AD_RVBARADDR0_RVBARADDR0_MASK        (0xFFFFFFFFU)
#define SIM_AD_RVBARADDR0_RVBARADDR0_SHIFT       (0U)
/*! RVBARADDR0 - CA35 Core0 Reset Vector Base Address */
#define SIM_AD_RVBARADDR0_RVBARADDR0(x)          (((uint32_t)(((uint32_t)(x)) << SIM_AD_RVBARADDR0_RVBARADDR0_SHIFT)) & SIM_AD_RVBARADDR0_RVBARADDR0_MASK)
/*! @} */

/*! @name RVBARADDR1 - CA35 Core1 Reset Vector Base Address (DGO 9) */
/*! @{ */

#define SIM_AD_RVBARADDR1_RVBARADDR1_MASK        (0xFFFFFFFFU)
#define SIM_AD_RVBARADDR1_RVBARADDR1_SHIFT       (0U)
/*! RVBARADDR1 - CA35 Core1 Reset Vector Base Address */
#define SIM_AD_RVBARADDR1_RVBARADDR1(x)          (((uint32_t)(((uint32_t)(x)) << SIM_AD_RVBARADDR1_RVBARADDR1_SHIFT)) & SIM_AD_RVBARADDR1_RVBARADDR1_MASK)
/*! @} */

/*! @name MQS1_CF - Medium Quality Sound Configuration Register */
/*! @{ */

#define SIM_AD_MQS1_CF_MQS1_CLK_DIV_MASK         (0xFF0000U)
#define SIM_AD_MQS1_CF_MQS1_CLK_DIV_SHIFT        (16U)
/*! MQS1_CLK_DIV - Divider Ration Control for mclk from hmclk. */
#define SIM_AD_MQS1_CF_MQS1_CLK_DIV(x)           (((uint32_t)(((uint32_t)(x)) << SIM_AD_MQS1_CF_MQS1_CLK_DIV_SHIFT)) & SIM_AD_MQS1_CF_MQS1_CLK_DIV_MASK)

#define SIM_AD_MQS1_CF_MQS1_SW_RST_MASK          (0x1000000U)
#define SIM_AD_MQS1_CF_MQS1_SW_RST_SHIFT         (24U)
/*! MQS1_SW_RST - MQS Software Reset */
#define SIM_AD_MQS1_CF_MQS1_SW_RST(x)            (((uint32_t)(((uint32_t)(x)) << SIM_AD_MQS1_CF_MQS1_SW_RST_SHIFT)) & SIM_AD_MQS1_CF_MQS1_SW_RST_MASK)

#define SIM_AD_MQS1_CF_MQS1_EN_MASK              (0x2000000U)
#define SIM_AD_MQS1_CF_MQS1_EN_SHIFT             (25U)
/*! MQS1_EN - Enables MQS */
#define SIM_AD_MQS1_CF_MQS1_EN(x)                (((uint32_t)(((uint32_t)(x)) << SIM_AD_MQS1_CF_MQS1_EN_SHIFT)) & SIM_AD_MQS1_CF_MQS1_EN_MASK)

#define SIM_AD_MQS1_CF_MQS1_OVERSAMPLE_MASK      (0x4000000U)
#define SIM_AD_MQS1_CF_MQS1_OVERSAMPLE_SHIFT     (26U)
/*! MQS1_OVERSAMPLE - PWM Oversampling Rate Selection */
#define SIM_AD_MQS1_CF_MQS1_OVERSAMPLE(x)        (((uint32_t)(((uint32_t)(x)) << SIM_AD_MQS1_CF_MQS1_OVERSAMPLE_SHIFT)) & SIM_AD_MQS1_CF_MQS1_OVERSAMPLE_MASK)

#define SIM_AD_MQS1_CF_MQS1_SDATA_SOURCE_MASK    (0x8000000U)
#define SIM_AD_MQS1_CF_MQS1_SDATA_SOURCE_SHIFT   (27U)
/*! MQS1_SDATA_SOURCE - MQS1s sdata Input Source Selection */
#define SIM_AD_MQS1_CF_MQS1_SDATA_SOURCE(x)      (((uint32_t)(((uint32_t)(x)) << SIM_AD_MQS1_CF_MQS1_SDATA_SOURCE_SHIFT)) & SIM_AD_MQS1_CF_MQS1_SDATA_SOURCE_MASK)
/*! @} */

/*! @name SAI_MULTISYNC_ENABLE_SELECTOR - SAI 4 and 5 Transmitter/Receiver Multi-Synchronous Enable Source */
/*! @{ */

#define SIM_AD_SAI_MULTISYNC_ENABLE_SELECTOR_SAI4_MULTISYNC_ENABLE_SELECTOR_MASK (0x3U)
#define SIM_AD_SAI_MULTISYNC_ENABLE_SELECTOR_SAI4_MULTISYNC_ENABLE_SELECTOR_SHIFT (0U)
/*! SAI4_MULTISYNC_ENABLE_SELECTOR - SAI4 Multi-sync Enable Source */
#define SIM_AD_SAI_MULTISYNC_ENABLE_SELECTOR_SAI4_MULTISYNC_ENABLE_SELECTOR(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_SAI_MULTISYNC_ENABLE_SELECTOR_SAI4_MULTISYNC_ENABLE_SELECTOR_SHIFT)) & SIM_AD_SAI_MULTISYNC_ENABLE_SELECTOR_SAI4_MULTISYNC_ENABLE_SELECTOR_MASK)

#define SIM_AD_SAI_MULTISYNC_ENABLE_SELECTOR_SAI5_MULTISYNC_ENABLE_SELECTOR_MASK (0x300U)
#define SIM_AD_SAI_MULTISYNC_ENABLE_SELECTOR_SAI5_MULTISYNC_ENABLE_SELECTOR_SHIFT (8U)
/*! SAI5_MULTISYNC_ENABLE_SELECTOR - SAI5 Multi-sync Enable Source */
#define SIM_AD_SAI_MULTISYNC_ENABLE_SELECTOR_SAI5_MULTISYNC_ENABLE_SELECTOR(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_SAI_MULTISYNC_ENABLE_SELECTOR_SAI5_MULTISYNC_ENABLE_SELECTOR_SHIFT)) & SIM_AD_SAI_MULTISYNC_ENABLE_SELECTOR_SAI5_MULTISYNC_ENABLE_SELECTOR_MASK)
/*! @} */

/*! @name CORE0_PMU_EVENT - A35 Core0 Performance Monitoring Events */
/*! @{ */

#define SIM_AD_CORE0_PMU_EVENT_CORE0_PMU_EVENT_MASK (0x3FFFFFFFU)
#define SIM_AD_CORE0_PMU_EVENT_CORE0_PMU_EVENT_SHIFT (0U)
/*! CORE0_PMU_EVENT - A35 Core0 PMU EVENT */
#define SIM_AD_CORE0_PMU_EVENT_CORE0_PMU_EVENT(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_CORE0_PMU_EVENT_CORE0_PMU_EVENT_SHIFT)) & SIM_AD_CORE0_PMU_EVENT_CORE0_PMU_EVENT_MASK)
/*! @} */

/*! @name CORE1_PMU_EVENT - A35 Core1 Performance Monitoring Events */
/*! @{ */

#define SIM_AD_CORE1_PMU_EVENT_CORE1_PMU_EVENT_MASK (0x3FFFFFFFU)
#define SIM_AD_CORE1_PMU_EVENT_CORE1_PMU_EVENT_SHIFT (0U)
/*! CORE1_PMU_EVENT - A35 Core1 PMU EVENT */
#define SIM_AD_CORE1_PMU_EVENT_CORE1_PMU_EVENT(x) (((uint32_t)(((uint32_t)(x)) << SIM_AD_CORE1_PMU_EVENT_CORE1_PMU_EVENT_SHIFT)) & SIM_AD_CORE1_PMU_EVENT_CORE1_PMU_EVENT_MASK)
/*! @} */

/*! @name DGO_GP6 - APD SIM DGO General Purpose Register 6 */
/*! @{ */

#define SIM_AD_DGO_GP6_SIM_DGO_GP6_MASK          (0xFFFFFFFFU)
#define SIM_AD_DGO_GP6_SIM_DGO_GP6_SHIFT         (0U)
/*! SIM_DGO_GP6 - SIM DGO General purpose register 6 */
#define SIM_AD_DGO_GP6_SIM_DGO_GP6(x)            (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP6_SIM_DGO_GP6_SHIFT)) & SIM_AD_DGO_GP6_SIM_DGO_GP6_MASK)
/*! @} */

/*! @name DGO_GP7 - APD SIM DGO General Purpose Register 7 */
/*! @{ */

#define SIM_AD_DGO_GP7_SIM_DGO_GP7_MASK          (0xFFFFFFFFU)
#define SIM_AD_DGO_GP7_SIM_DGO_GP7_SHIFT         (0U)
/*! SIM_DGO_GP7 - SIM DGO General Purpose Register 7 */
#define SIM_AD_DGO_GP7_SIM_DGO_GP7(x)            (((uint32_t)(((uint32_t)(x)) << SIM_AD_DGO_GP7_SIM_DGO_GP7_SHIFT)) & SIM_AD_DGO_GP7_SIM_DGO_GP7_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SIM_AD_Register_Masks */


/* SIM_AD - Peripheral instance base addresses */
/** Peripheral SIM_AD base address */
#define SIM_AD_BASE                              (0x29290000u)
/** Peripheral SIM_AD base pointer */
#define SIM_AD                                   ((SIM_AD_Type *)SIM_AD_BASE)
/** Array initializer of SIM_AD peripheral base addresses */
#define SIM_AD_BASE_ADDRS                        { SIM_AD_BASE }
/** Array initializer of SIM_AD peripheral base pointers */
#define SIM_AD_BASE_PTRS                         { SIM_AD }

/*!
 * @}
 */ /* end of group SIM_AD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SIM_LPAV Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SIM_LPAV_Peripheral_Access_Layer SIM_LPAV Peripheral Access Layer
 * @{
 */

/** SIM_LPAV - Register Layout Typedef */
typedef struct {
  __IO uint32_t GPR0;                              /**< HW AVD_SIM General Purpose Register 0, offset: 0x0 */
       uint32_t GPR1;                              /**< HW AVD_SIM General Purpose Register 1, offset: 0x4 */
  __IO uint32_t SYSCTRL0;                          /**< Audio-Video Domain System Control Register 0, offset: 0x8 */
       uint8_t RESERVED_0[8];
  __IO uint32_t LPDDR_CTRL;                        /**< LPDDR Control Register, offset: 0x14 */
  __IO uint32_t LPDDR_CTRL2;                       /**< LPDDR Control Register, offset: 0x18 */
  __IO uint32_t DEFAULT_QOS;                       /**< Default Value Register for Quality of Service (QoS), offset: 0x1C */
  __IO uint32_t PANIC_QOS;                         /**< Panic Value Register for Quality of Service (QoS), offset: 0x20 */
  __IO uint32_t SAI_MULTISYNC_ENABLE_SELECTOR;     /**< SAI 6 and 7 Transmitter/Receiver Multi-Synchronous Enable Source, offset: 0x24 */
  __I  uint32_t HIFI4_GPR0;                        /**< HiFi4 DSP General Purpose Register, offset: 0x28 */
  __I  uint32_t HIFI4_GPR1;                        /**< HiFi4 DSP General Purpose Register, offset: 0x2C */
  __I  uint32_t HIFI4_GPR2;                        /**< HiFi4 DSP General Purpose Register, offset: 0x30 */
  __IO uint32_t AXI_CACHE_OVERRIDE;                /**< Audio-Video Domain AXI Cache Override, offset: 0x34 */
} SIM_LPAV_Type;

/* ----------------------------------------------------------------------------
   -- SIM_LPAV Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SIM_LPAV_Register_Masks SIM_LPAV Register Masks
 * @{
 */

/*! @name GPR0 - HW AVD_SIM General Purpose Register 0 */
/*! @{ */

#define SIM_LPAV_GPR0_GPR0_MASK                  (0x1U)
#define SIM_LPAV_GPR0_GPR0_SHIFT                 (0U)
/*! GPR0 - General Purpose Read/Write Register */
#define SIM_LPAV_GPR0_GPR0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_GPR0_GPR0_SHIFT)) & SIM_LPAV_GPR0_GPR0_MASK)
/*! @} */

/*! @name SYSCTRL0 - Audio-Video Domain System Control Register 0 */
/*! @{ */

#define SIM_LPAV_SYSCTRL0_DSI_CM_MASK            (0x2U)
#define SIM_LPAV_SYSCTRL0_DSI_CM_SHIFT           (1U)
/*! DSI_CM - DSI Mode Control */
#define SIM_LPAV_SYSCTRL0_DSI_CM(x)              (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_DSI_CM_SHIFT)) & SIM_LPAV_SYSCTRL0_DSI_CM_MASK)

#define SIM_LPAV_SYSCTRL0_DSI_SD_MASK            (0x4U)
#define SIM_LPAV_SYSCTRL0_DSI_SD_SHIFT           (2U)
/*! DSI_SD - DSI Shutdown Control */
#define SIM_LPAV_SYSCTRL0_DSI_SD(x)              (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_DSI_SD_SHIFT)) & SIM_LPAV_SYSCTRL0_DSI_SD_MASK)

#define SIM_LPAV_SYSCTRL0_DSI_RST_DPI_N_MASK     (0x8U)
#define SIM_LPAV_SYSCTRL0_DSI_RST_DPI_N_SHIFT    (3U)
/*! DSI_RST_DPI_N - DSI Reset DPI */
#define SIM_LPAV_SYSCTRL0_DSI_RST_DPI_N(x)       (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_DSI_RST_DPI_N_SHIFT)) & SIM_LPAV_SYSCTRL0_DSI_RST_DPI_N_MASK)

#define SIM_LPAV_SYSCTRL0_DSI_RST_ESC_N_MASK     (0x10U)
#define SIM_LPAV_SYSCTRL0_DSI_RST_ESC_N_SHIFT    (4U)
/*! DSI_RST_ESC_N - DSI Reset Escape */
#define SIM_LPAV_SYSCTRL0_DSI_RST_ESC_N(x)       (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_DSI_RST_ESC_N_SHIFT)) & SIM_LPAV_SYSCTRL0_DSI_RST_ESC_N_MASK)

#define SIM_LPAV_SYSCTRL0_DSI_RST_BYTE_N_MASK    (0x20U)
#define SIM_LPAV_SYSCTRL0_DSI_RST_BYTE_N_SHIFT   (5U)
/*! DSI_RST_BYTE_N - DSI Reset Byte */
#define SIM_LPAV_SYSCTRL0_DSI_RST_BYTE_N(x)      (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_DSI_RST_BYTE_N_SHIFT)) & SIM_LPAV_SYSCTRL0_DSI_RST_BYTE_N_MASK)

#define SIM_LPAV_SYSCTRL0_DSI_CONT_CLK_MODE_MASK (0x100U)
#define SIM_LPAV_SYSCTRL0_DSI_CONT_CLK_MODE_SHIFT (8U)
/*! DSI_CONT_CLK_MODE - DSI Counter Control Mode */
#define SIM_LPAV_SYSCTRL0_DSI_CONT_CLK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_DSI_CONT_CLK_MODE_SHIFT)) & SIM_LPAV_SYSCTRL0_DSI_CONT_CLK_MODE_MASK)

#define SIM_LPAV_SYSCTRL0_DSI_DPI2_EPDC_DCNANO_MUX_SEL_MASK (0x200U)
#define SIM_LPAV_SYSCTRL0_DSI_DPI2_EPDC_DCNANO_MUX_SEL_SHIFT (9U)
/*! DSI_DPI2_EPDC_DCNANO_MUX_SEL - DSI Source Control */
#define SIM_LPAV_SYSCTRL0_DSI_DPI2_EPDC_DCNANO_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_DSI_DPI2_EPDC_DCNANO_MUX_SEL_SHIFT)) & SIM_LPAV_SYSCTRL0_DSI_DPI2_EPDC_DCNANO_MUX_SEL_MASK)

#define SIM_LPAV_SYSCTRL0_DSI_ALIGN_SW_MASK      (0x1000U)
#define SIM_LPAV_SYSCTRL0_DSI_ALIGN_SW_SHIFT     (12U)
/*! DSI_ALIGN_SW - Configures the DSI-PHY to Enable High Speed Sync Token Alignment */
#define SIM_LPAV_SYSCTRL0_DSI_ALIGN_SW(x)        (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_DSI_ALIGN_SW_SHIFT)) & SIM_LPAV_SYSCTRL0_DSI_ALIGN_SW_MASK)

#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_STALL_MASK   (0x2000U)
#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_STALL_SHIFT  (13U)
/*! HIFI4_DSP_STALL - Stall HIFI4 DSP Execution */
#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_STALL(x)     (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_HIFI4_DSP_STALL_SHIFT)) & SIM_LPAV_SYSCTRL0_HIFI4_DSP_STALL_MASK)

#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_OCD_HALT_MASK (0x4000U)
#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_OCD_HALT_SHIFT (14U)
/*! HIFI4_DSP_OCD_HALT - Halt HiFi4 DSP Execution into OCD Halt Mode when Processor Comes Out of Reset */
#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_OCD_HALT(x)  (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_HIFI4_DSP_OCD_HALT_SHIFT)) & SIM_LPAV_SYSCTRL0_HIFI4_DSP_OCD_HALT_MASK)

#define SIM_LPAV_SYSCTRL0_MIPI_DSI_ULPS_PWRUP_MASK (0x8000U)
#define SIM_LPAV_SYSCTRL0_MIPI_DSI_ULPS_PWRUP_SHIFT (15U)
/*! MIPI_DSI_ULPS_PWRUP - Enables MIPI-DSI to Exit ULPS00 gracefully */
#define SIM_LPAV_SYSCTRL0_MIPI_DSI_ULPS_PWRUP(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_MIPI_DSI_ULPS_PWRUP_SHIFT)) & SIM_LPAV_SYSCTRL0_MIPI_DSI_ULPS_PWRUP_MASK)

#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_RST_MASK     (0x10000U)
#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_RST_SHIFT    (16U)
/*! HIFI4_DSP_RST - Controls the HiFi4 DSP Reset */
#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_RST(x)       (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_HIFI4_DSP_RST_SHIFT)) & SIM_LPAV_SYSCTRL0_HIFI4_DSP_RST_MASK)

#define SIM_LPAV_SYSCTRL0_HIFI4_CLK_EN_MASK      (0x20000U)
#define SIM_LPAV_SYSCTRL0_HIFI4_CLK_EN_SHIFT     (17U)
/*! HIFI4_CLK_EN - HiFi4 Clock Enable */
#define SIM_LPAV_SYSCTRL0_HIFI4_CLK_EN(x)        (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_HIFI4_CLK_EN_SHIFT)) & SIM_LPAV_SYSCTRL0_HIFI4_CLK_EN_MASK)

#define SIM_LPAV_SYSCTRL0_HIFI4_PBCLK_EN_MASK    (0x40000U)
#define SIM_LPAV_SYSCTRL0_HIFI4_PBCLK_EN_SHIFT   (18U)
/*! HIFI4_PBCLK_EN - HiFi4 PBCLK Clock Enable */
#define SIM_LPAV_SYSCTRL0_HIFI4_PBCLK_EN(x)      (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_HIFI4_PBCLK_EN_SHIFT)) & SIM_LPAV_SYSCTRL0_HIFI4_PBCLK_EN_MASK)

#define SIM_LPAV_SYSCTRL0_HIFI4_PLAT_CLK_EN_MASK (0x80000U)
#define SIM_LPAV_SYSCTRL0_HIFI4_PLAT_CLK_EN_SHIFT (19U)
/*! HIFI4_PLAT_CLK_EN - HiFi4 Platform Clock Enable */
#define SIM_LPAV_SYSCTRL0_HIFI4_PLAT_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_HIFI4_PLAT_CLK_EN_SHIFT)) & SIM_LPAV_SYSCTRL0_HIFI4_PLAT_CLK_EN_MASK)

#define SIM_LPAV_SYSCTRL0_LPAV_MODULE_DEBUG_MASK (0xF00000U)
#define SIM_LPAV_SYSCTRL0_LPAV_MODULE_DEBUG_SHIFT (20U)
/*! LPAV_MODULE_DEBUG - Low-Power Audio-Video Mode Debug */
#define SIM_LPAV_SYSCTRL0_LPAV_MODULE_DEBUG(x)   (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_LPAV_MODULE_DEBUG_SHIFT)) & SIM_LPAV_SYSCTRL0_LPAV_MODULE_DEBUG_MASK)

#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_DBG_RST_MASK (0x2000000U)
#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_DBG_RST_SHIFT (25U)
/*! HIFI4_DSP_DBG_RST - Reset HiFi4 DSP Debug Logic */
#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_DBG_RST(x)   (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_HIFI4_DSP_DBG_RST_SHIFT)) & SIM_LPAV_SYSCTRL0_HIFI4_DSP_DBG_RST_MASK)

#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_DBG_MODE_MASK (0x4000000U)
#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_DBG_MODE_SHIFT (26U)
/*! HIFI4_DSP_DBG_MODE - HiFi4 DSP in OCD Halt or Other Debug Mode */
#define SIM_LPAV_SYSCTRL0_HIFI4_DSP_DBG_MODE(x)  (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_HIFI4_DSP_DBG_MODE_SHIFT)) & SIM_LPAV_SYSCTRL0_HIFI4_DSP_DBG_MODE_MASK)

#define SIM_LPAV_SYSCTRL0_MIPI_DSI_ULPS_ACTIVE_MASK (0xF8000000U)
#define SIM_LPAV_SYSCTRL0_MIPI_DSI_ULPS_ACTIVE_SHIFT (27U)
/*! MIPI_DSI_ULPS_ACTIVE - MIPI-DSI ULPS Status Bits */
#define SIM_LPAV_SYSCTRL0_MIPI_DSI_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SYSCTRL0_MIPI_DSI_ULPS_ACTIVE_SHIFT)) & SIM_LPAV_SYSCTRL0_MIPI_DSI_ULPS_ACTIVE_MASK)
/*! @} */

/*! @name LPDDR_CTRL - LPDDR Control Register */
/*! @{ */

#define SIM_LPAV_LPDDR_CTRL_LPDDR_ERROR_MASK     (0xFU)
#define SIM_LPAV_LPDDR_CTRL_LPDDR_ERROR_SHIFT    (0U)
/*! LPDDR_ERROR - LPDDR Error */
#define SIM_LPAV_LPDDR_CTRL_LPDDR_ERROR(x)       (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL_LPDDR_ERROR_SHIFT)) & SIM_LPAV_LPDDR_CTRL_LPDDR_ERROR_MASK)

#define SIM_LPAV_LPDDR_CTRL_LPDDR_DONE_MASK      (0x10U)
#define SIM_LPAV_LPDDR_CTRL_LPDDR_DONE_SHIFT     (4U)
/*! LPDDR_DONE - LPDDR Done */
#define SIM_LPAV_LPDDR_CTRL_LPDDR_DONE(x)        (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL_LPDDR_DONE_SHIFT)) & SIM_LPAV_LPDDR_CTRL_LPDDR_DONE_MASK)

#define SIM_LPAV_LPDDR_CTRL_ENABLE_HSHK_TIMEOUT_MASK (0x20U)
#define SIM_LPAV_LPDDR_CTRL_ENABLE_HSHK_TIMEOUT_SHIFT (5U)
/*! ENABLE_HSHK_TIMEOUT - Enables Internal Timeout Counter to be Active */
#define SIM_LPAV_LPDDR_CTRL_ENABLE_HSHK_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL_ENABLE_HSHK_TIMEOUT_SHIFT)) & SIM_LPAV_LPDDR_CTRL_ENABLE_HSHK_TIMEOUT_MASK)

#define SIM_LPAV_LPDDR_CTRL_SOC_FREQ_CHG_ACK_MASK (0x40U)
#define SIM_LPAV_LPDDR_CTRL_SOC_FREQ_CHG_ACK_SHIFT (6U)
/*! SOC_FREQ_CHG_ACK - LPDDR Frequency Change Acknowledge */
#define SIM_LPAV_LPDDR_CTRL_SOC_FREQ_CHG_ACK(x)  (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL_SOC_FREQ_CHG_ACK_SHIFT)) & SIM_LPAV_LPDDR_CTRL_SOC_FREQ_CHG_ACK_MASK)

#define SIM_LPAV_LPDDR_CTRL_SOC_FREQ_CHG_REQ_MASK (0x80U)
#define SIM_LPAV_LPDDR_CTRL_SOC_FREQ_CHG_REQ_SHIFT (7U)
/*! SOC_FREQ_CHG_REQ - LPDDR Frequency Change Request */
#define SIM_LPAV_LPDDR_CTRL_SOC_FREQ_CHG_REQ(x)  (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL_SOC_FREQ_CHG_REQ_SHIFT)) & SIM_LPAV_LPDDR_CTRL_SOC_FREQ_CHG_REQ_MASK)

#define SIM_LPAV_LPDDR_CTRL_SOC_FREQ_COPY_MASK   (0x600U)
#define SIM_LPAV_LPDDR_CTRL_SOC_FREQ_COPY_SHIFT  (9U)
/*! SOC_FREQ_COPY - SoC Frequency Copy */
#define SIM_LPAV_LPDDR_CTRL_SOC_FREQ_COPY(x)     (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL_SOC_FREQ_COPY_SHIFT)) & SIM_LPAV_LPDDR_CTRL_SOC_FREQ_COPY_MASK)

#define SIM_LPAV_LPDDR_CTRL_SOC_FREQ_REQ_MASK    (0x800U)
#define SIM_LPAV_LPDDR_CTRL_SOC_FREQ_REQ_SHIFT   (11U)
/*! SOC_FREQ_REQ - Frequency Change Request */
#define SIM_LPAV_LPDDR_CTRL_SOC_FREQ_REQ(x)      (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL_SOC_FREQ_REQ_SHIFT)) & SIM_LPAV_LPDDR_CTRL_SOC_FREQ_REQ_MASK)

#define SIM_LPAV_LPDDR_CTRL_SOC_LP_CMD_MASK      (0x1F8000U)
#define SIM_LPAV_LPDDR_CTRL_SOC_LP_CMD_SHIFT     (15U)
/*! SOC_LP_CMD - Low Power Command Code to Send Requests to LPDDR Controller for Low Power or DFS */
#define SIM_LPAV_LPDDR_CTRL_SOC_LP_CMD(x)        (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL_SOC_LP_CMD_SHIFT)) & SIM_LPAV_LPDDR_CTRL_SOC_LP_CMD_MASK)

#define SIM_LPAV_LPDDR_CTRL_LPDDR_AUTO_LP_MODE_DISABLE_MASK (0x1000000U)
#define SIM_LPAV_LPDDR_CTRL_LPDDR_AUTO_LP_MODE_DISABLE_SHIFT (24U)
/*! LPDDR_AUTO_LP_MODE_DISABLE - Automatic Low Power Mode Acknowledge */
#define SIM_LPAV_LPDDR_CTRL_LPDDR_AUTO_LP_MODE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL_LPDDR_AUTO_LP_MODE_DISABLE_SHIFT)) & SIM_LPAV_LPDDR_CTRL_LPDDR_AUTO_LP_MODE_DISABLE_MASK)

#define SIM_LPAV_LPDDR_CTRL_Q_ALMOST_FULL_INT_ENABLE_MASK (0x40000000U)
#define SIM_LPAV_LPDDR_CTRL_Q_ALMOST_FULL_INT_ENABLE_SHIFT (30U)
/*! Q_ALMOST_FULL_INT_ENABLE - Interrupt Enable for Queue Almost Full Threshold */
#define SIM_LPAV_LPDDR_CTRL_Q_ALMOST_FULL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL_Q_ALMOST_FULL_INT_ENABLE_SHIFT)) & SIM_LPAV_LPDDR_CTRL_Q_ALMOST_FULL_INT_ENABLE_MASK)

#define SIM_LPAV_LPDDR_CTRL_Q_ALMOST_FULL_MASK   (0x80000000U)
#define SIM_LPAV_LPDDR_CTRL_Q_ALMOST_FULL_SHIFT  (31U)
/*! Q_ALMOST_FULL - Queue Almost Full Status */
#define SIM_LPAV_LPDDR_CTRL_Q_ALMOST_FULL(x)     (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL_Q_ALMOST_FULL_SHIFT)) & SIM_LPAV_LPDDR_CTRL_Q_ALMOST_FULL_MASK)
/*! @} */

/*! @name LPDDR_CTRL2 - LPDDR Control Register */
/*! @{ */

#define SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_TYPE_MASK  (0x1FU)
#define SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_TYPE_SHIFT (0U)
/*! PHY_FREQ_TYPE - Code for New System LPDDR4/4x Frequency: */
#define SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_TYPE(x)    (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_TYPE_SHIFT)) & SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_TYPE_MASK)

#define SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_CHG_ACK_MASK (0x40U)
#define SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_CHG_ACK_SHIFT (6U)
/*! PHY_FREQ_CHG_ACK - PHY Frequency Change Acknowledge */
#define SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_CHG_ACK(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_CHG_ACK_SHIFT)) & SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_CHG_ACK_MASK)

#define SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_CHG_REQ_MASK (0x80U)
#define SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_CHG_REQ_SHIFT (7U)
/*! PHY_FREQ_CHG_REQ - PHY Frequency Change Request */
#define SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_CHG_REQ(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_CHG_REQ_SHIFT)) & SIM_LPAV_LPDDR_CTRL2_PHY_FREQ_CHG_REQ_MASK)

#define SIM_LPAV_LPDDR_CTRL2_DFS_INT_ENABLE_MASK (0x4000U)
#define SIM_LPAV_LPDDR_CTRL2_DFS_INT_ENABLE_SHIFT (14U)
/*! DFS_INT_ENABLE - Enable Interrupt for The DSF handshake */
#define SIM_LPAV_LPDDR_CTRL2_DFS_INT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL2_DFS_INT_ENABLE_SHIFT)) & SIM_LPAV_LPDDR_CTRL2_DFS_INT_ENABLE_MASK)

#define SIM_LPAV_LPDDR_CTRL2_DFS_INTERRUPT_MASK  (0x8000U)
#define SIM_LPAV_LPDDR_CTRL2_DFS_INTERRUPT_SHIFT (15U)
/*! DFS_INTERRUPT - DFS interrupt */
#define SIM_LPAV_LPDDR_CTRL2_DFS_INTERRUPT(x)    (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL2_DFS_INTERRUPT_SHIFT)) & SIM_LPAV_LPDDR_CTRL2_DFS_INTERRUPT_MASK)

#define SIM_LPAV_LPDDR_CTRL2_LPDDR_MAX_CLKDIV_EN_MASK (0x10000U)
#define SIM_LPAV_LPDDR_CTRL2_LPDDR_MAX_CLKDIV_EN_SHIFT (16U)
/*! LPDDR_MAX_CLKDIV_EN - LPDDR Maximum Clock Divider Enable */
#define SIM_LPAV_LPDDR_CTRL2_LPDDR_MAX_CLKDIV_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL2_LPDDR_MAX_CLKDIV_EN_SHIFT)) & SIM_LPAV_LPDDR_CTRL2_LPDDR_MAX_CLKDIV_EN_MASK)

#define SIM_LPAV_LPDDR_CTRL2_LPDDR_EN_CLKGATE_MASK (0x20000U)
#define SIM_LPAV_LPDDR_CTRL2_LPDDR_EN_CLKGATE_SHIFT (17U)
/*! LPDDR_EN_CLKGATE - LPDDR Enable Clock Gate */
#define SIM_LPAV_LPDDR_CTRL2_LPDDR_EN_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_LPDDR_CTRL2_LPDDR_EN_CLKGATE_SHIFT)) & SIM_LPAV_LPDDR_CTRL2_LPDDR_EN_CLKGATE_MASK)
/*! @} */

/*! @name DEFAULT_QOS - Default Value Register for Quality of Service (QoS) */
/*! @{ */

#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_Y_AR_QOS_MASK (0xFU)
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_Y_AR_QOS_SHIFT (0U)
/*! DEFAULT_ISI_Y_AR_QOS - Default Value Register for Quality of Service (QoS) AXI Read Channel Corresponding to ISI Y Buffer Channel */
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_Y_AR_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_Y_AR_QOS_SHIFT)) & SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_Y_AR_QOS_MASK)

#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_Y_AW_QOS_MASK (0xF0U)
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_Y_AW_QOS_SHIFT (4U)
/*! DEFAULT_ISI_Y_AW_QOS - Default Value Register for Quality of Service (QoS) AXI Write Channel Corresponding to ISI Y Buffer Channel */
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_Y_AW_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_Y_AW_QOS_SHIFT)) & SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_Y_AW_QOS_MASK)

#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_U_AR_QOS_MASK (0xF00U)
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_U_AR_QOS_SHIFT (8U)
/*! DEFAULT_ISI_U_AR_QOS - Default Value Register for Quality of Service (QoS) AXI Read Channel Corresponding to ISI U Buffer Channel */
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_U_AR_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_U_AR_QOS_SHIFT)) & SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_U_AR_QOS_MASK)

#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_U_AW_QOS_MASK (0xF000U)
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_U_AW_QOS_SHIFT (12U)
/*! DEFAULT_ISI_U_AW_QOS - Default Value Register for Quality of Service (QoS) AXI Write Channel Corresponding to ISI U Buffer Channel */
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_U_AW_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_U_AW_QOS_SHIFT)) & SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_U_AW_QOS_MASK)

#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_V_AR_QOS_MASK (0xF0000U)
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_V_AR_QOS_SHIFT (16U)
/*! DEFAULT_ISI_V_AR_QOS - Default Value Register for Quality of Service (QoS) AXI Read Channel Corresponding to ISI V Buffer Channel */
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_V_AR_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_V_AR_QOS_SHIFT)) & SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_V_AR_QOS_MASK)

#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_V_AW_QOS_MASK (0xF00000U)
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_V_AW_QOS_SHIFT (20U)
/*! DEFAULT_ISI_V_AW_QOS - Default Value Register for Quality of Service (QoS) AXI Write Channel Corresponding to ISI V Buffer Channel */
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_V_AW_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_V_AW_QOS_SHIFT)) & SIM_LPAV_DEFAULT_QOS_DEFAULT_ISI_V_AW_QOS_MASK)

#define SIM_LPAV_DEFAULT_QOS_DEFAULT_EPDC_AW_QOS_MASK (0xF000000U)
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_EPDC_AW_QOS_SHIFT (24U)
/*! DEFAULT_EPDC_AW_QOS - EPDC Quality of Service (QoS) AXI Write Channel */
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_EPDC_AW_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_DEFAULT_QOS_DEFAULT_EPDC_AW_QOS_SHIFT)) & SIM_LPAV_DEFAULT_QOS_DEFAULT_EPDC_AW_QOS_MASK)

#define SIM_LPAV_DEFAULT_QOS_DEFAULT_EPDC_AR_QOS_MASK (0xF0000000U)
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_EPDC_AR_QOS_SHIFT (28U)
/*! DEFAULT_EPDC_AR_QOS - EPDC Default Value Register for Quality of Service (QoS) AXI Read Channel */
#define SIM_LPAV_DEFAULT_QOS_DEFAULT_EPDC_AR_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_DEFAULT_QOS_DEFAULT_EPDC_AR_QOS_SHIFT)) & SIM_LPAV_DEFAULT_QOS_DEFAULT_EPDC_AR_QOS_MASK)
/*! @} */

/*! @name PANIC_QOS - Panic Value Register for Quality of Service (QoS) */
/*! @{ */

#define SIM_LPAV_PANIC_QOS_PANIC_ISI_Y_AR_QOS_MASK (0xFU)
#define SIM_LPAV_PANIC_QOS_PANIC_ISI_Y_AR_QOS_SHIFT (0U)
/*! PANIC_ISI_Y_AR_QOS - Panic Value Register for Quality of Service (QoS) AXI Read Channel Corresponding to ISI Y Buffer Channel */
#define SIM_LPAV_PANIC_QOS_PANIC_ISI_Y_AR_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_PANIC_QOS_PANIC_ISI_Y_AR_QOS_SHIFT)) & SIM_LPAV_PANIC_QOS_PANIC_ISI_Y_AR_QOS_MASK)

#define SIM_LPAV_PANIC_QOS_PANIC_ISI_Y_AW_QOS_MASK (0xF0U)
#define SIM_LPAV_PANIC_QOS_PANIC_ISI_Y_AW_QOS_SHIFT (4U)
/*! PANIC_ISI_Y_AW_QOS - Panic Value Register for Quality of Service (QoS) AXI Write Channel Corresponding to ISI Y Buffer Channel */
#define SIM_LPAV_PANIC_QOS_PANIC_ISI_Y_AW_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_PANIC_QOS_PANIC_ISI_Y_AW_QOS_SHIFT)) & SIM_LPAV_PANIC_QOS_PANIC_ISI_Y_AW_QOS_MASK)

#define SIM_LPAV_PANIC_QOS_PANIC_ISI_U_AR_QOS_MASK (0xF00U)
#define SIM_LPAV_PANIC_QOS_PANIC_ISI_U_AR_QOS_SHIFT (8U)
/*! PANIC_ISI_U_AR_QOS - Panic Value Register for Quality of Service (QoS) AXI Read Channel Corresponding to ISI U Buffer Channel */
#define SIM_LPAV_PANIC_QOS_PANIC_ISI_U_AR_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_PANIC_QOS_PANIC_ISI_U_AR_QOS_SHIFT)) & SIM_LPAV_PANIC_QOS_PANIC_ISI_U_AR_QOS_MASK)

#define SIM_LPAV_PANIC_QOS_PANIC_ISI_U_AW_QOS_MASK (0xF000U)
#define SIM_LPAV_PANIC_QOS_PANIC_ISI_U_AW_QOS_SHIFT (12U)
/*! PANIC_ISI_U_AW_QOS - Panic Value Register for Quality of Service (QoS) AXI Write Channel Corresponding to ISI U Buffer Channel */
#define SIM_LPAV_PANIC_QOS_PANIC_ISI_U_AW_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_PANIC_QOS_PANIC_ISI_U_AW_QOS_SHIFT)) & SIM_LPAV_PANIC_QOS_PANIC_ISI_U_AW_QOS_MASK)

#define SIM_LPAV_PANIC_QOS_PANIC_ISI_V_AR_QOS_MASK (0xF0000U)
#define SIM_LPAV_PANIC_QOS_PANIC_ISI_V_AR_QOS_SHIFT (16U)
/*! PANIC_ISI_V_AR_QOS - Panic Value Register for Quality of Service (QoS) AXI Read Channel corresponding to ISI V Buffer Channel */
#define SIM_LPAV_PANIC_QOS_PANIC_ISI_V_AR_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_PANIC_QOS_PANIC_ISI_V_AR_QOS_SHIFT)) & SIM_LPAV_PANIC_QOS_PANIC_ISI_V_AR_QOS_MASK)

#define SIM_LPAV_PANIC_QOS_PANIC_ISI_V_AW_QOS_MASK (0xF00000U)
#define SIM_LPAV_PANIC_QOS_PANIC_ISI_V_AW_QOS_SHIFT (20U)
/*! PANIC_ISI_V_AW_QOS - Panic Value Register for Quality of Service (QoS) AXI Write Channel corresponding to ISI V Buffer Channel */
#define SIM_LPAV_PANIC_QOS_PANIC_ISI_V_AW_QOS(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_PANIC_QOS_PANIC_ISI_V_AW_QOS_SHIFT)) & SIM_LPAV_PANIC_QOS_PANIC_ISI_V_AW_QOS_MASK)

#define SIM_LPAV_PANIC_QOS_PANIC_EPDC_AW_QOS_MASK (0xF000000U)
#define SIM_LPAV_PANIC_QOS_PANIC_EPDC_AW_QOS_SHIFT (24U)
/*! PANIC_EPDC_AW_QOS - EPDC Panic Value Register for Quality of Service (QoS) AXI Write Channel */
#define SIM_LPAV_PANIC_QOS_PANIC_EPDC_AW_QOS(x)  (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_PANIC_QOS_PANIC_EPDC_AW_QOS_SHIFT)) & SIM_LPAV_PANIC_QOS_PANIC_EPDC_AW_QOS_MASK)

#define SIM_LPAV_PANIC_QOS_PANIC_EPDC_AR_QOS_MASK (0xF0000000U)
#define SIM_LPAV_PANIC_QOS_PANIC_EPDC_AR_QOS_SHIFT (28U)
/*! PANIC_EPDC_AR_QOS - EPDC Panic Value Register for Quality of Service (QoS) AXI Read Channel */
#define SIM_LPAV_PANIC_QOS_PANIC_EPDC_AR_QOS(x)  (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_PANIC_QOS_PANIC_EPDC_AR_QOS_SHIFT)) & SIM_LPAV_PANIC_QOS_PANIC_EPDC_AR_QOS_MASK)
/*! @} */

/*! @name SAI_MULTISYNC_ENABLE_SELECTOR - SAI 6 and 7 Transmitter/Receiver Multi-Synchronous Enable Source */
/*! @{ */

#define SIM_LPAV_SAI_MULTISYNC_ENABLE_SELECTOR_SAI6_MULTISYNC_ENABLE_SELECTOR_MASK (0x7U)
#define SIM_LPAV_SAI_MULTISYNC_ENABLE_SELECTOR_SAI6_MULTISYNC_ENABLE_SELECTOR_SHIFT (0U)
/*! SAI6_MULTISYNC_ENABLE_SELECTOR - SAI6 Multi-Sync Enable Source */
#define SIM_LPAV_SAI_MULTISYNC_ENABLE_SELECTOR_SAI6_MULTISYNC_ENABLE_SELECTOR(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SAI_MULTISYNC_ENABLE_SELECTOR_SAI6_MULTISYNC_ENABLE_SELECTOR_SHIFT)) & SIM_LPAV_SAI_MULTISYNC_ENABLE_SELECTOR_SAI6_MULTISYNC_ENABLE_SELECTOR_MASK)

#define SIM_LPAV_SAI_MULTISYNC_ENABLE_SELECTOR_SAI7_MULTISYNC_ENABLE_SELECTOR_MASK (0x700U)
#define SIM_LPAV_SAI_MULTISYNC_ENABLE_SELECTOR_SAI7_MULTISYNC_ENABLE_SELECTOR_SHIFT (8U)
/*! SAI7_MULTISYNC_ENABLE_SELECTOR - SAI7 Multi-Sync Enable Source */
#define SIM_LPAV_SAI_MULTISYNC_ENABLE_SELECTOR_SAI7_MULTISYNC_ENABLE_SELECTOR(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_SAI_MULTISYNC_ENABLE_SELECTOR_SAI7_MULTISYNC_ENABLE_SELECTOR_SHIFT)) & SIM_LPAV_SAI_MULTISYNC_ENABLE_SELECTOR_SAI7_MULTISYNC_ENABLE_SELECTOR_MASK)
/*! @} */

/*! @name HIFI4_GPR0 - HiFi4 DSP General Purpose Register */
/*! @{ */

#define SIM_LPAV_HIFI4_GPR0_DOUBLEEXCEPTIONERROR_MASK (0x10000U)
#define SIM_LPAV_HIFI4_GPR0_DOUBLEEXCEPTIONERROR_SHIFT (16U)
/*! DOUBLEEXCEPTIONERROR - Double Exception Error */
#define SIM_LPAV_HIFI4_GPR0_DOUBLEEXCEPTIONERROR(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_HIFI4_GPR0_DOUBLEEXCEPTIONERROR_SHIFT)) & SIM_LPAV_HIFI4_GPR0_DOUBLEEXCEPTIONERROR_MASK)

#define SIM_LPAV_HIFI4_GPR0_PFATALERROR_MASK     (0x20000U)
#define SIM_LPAV_HIFI4_GPR0_PFATALERROR_SHIFT    (17U)
/*! PFATALERROR - Fatal Error */
#define SIM_LPAV_HIFI4_GPR0_PFATALERROR(x)       (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_HIFI4_GPR0_PFATALERROR_SHIFT)) & SIM_LPAV_HIFI4_GPR0_PFATALERROR_MASK)

#define SIM_LPAV_HIFI4_GPR0_PFAULTINFOVALID_MASK (0x40000U)
#define SIM_LPAV_HIFI4_GPR0_PFAULTINFOVALID_SHIFT (18U)
/*! PFAULTINFOVALID - Fault Information Valid */
#define SIM_LPAV_HIFI4_GPR0_PFAULTINFOVALID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_HIFI4_GPR0_PFAULTINFOVALID_SHIFT)) & SIM_LPAV_HIFI4_GPR0_PFAULTINFOVALID_MASK)
/*! @} */

/*! @name HIFI4_GPR1 - HiFi4 DSP General Purpose Register */
/*! @{ */

#define SIM_LPAV_HIFI4_GPR1_PFAULTINFO_MASK      (0xFFFFFFFFU)
#define SIM_LPAV_HIFI4_GPR1_PFAULTINFO_SHIFT     (0U)
/*! PFAULTINFO - Fault Information Register */
#define SIM_LPAV_HIFI4_GPR1_PFAULTINFO(x)        (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_HIFI4_GPR1_PFAULTINFO_SHIFT)) & SIM_LPAV_HIFI4_GPR1_PFAULTINFO_MASK)
/*! @} */

/*! @name HIFI4_GPR2 - HiFi4 DSP General Purpose Register */
/*! @{ */

#define SIM_LPAV_HIFI4_GPR2_TIE_EXPSTATE_MASK    (0xFFFFFFFFU)
#define SIM_LPAV_HIFI4_GPR2_TIE_EXPSTATE_SHIFT   (0U)
/*! TIE_EXPSTATE - GPIO32 Option TIE Output State */
#define SIM_LPAV_HIFI4_GPR2_TIE_EXPSTATE(x)      (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_HIFI4_GPR2_TIE_EXPSTATE_SHIFT)) & SIM_LPAV_HIFI4_GPR2_TIE_EXPSTATE_MASK)
/*! @} */

/*! @name AXI_CACHE_OVERRIDE - Audio-Video Domain AXI Cache Override */
/*! @{ */

#define SIM_LPAV_AXI_CACHE_OVERRIDE_AXI_CACHE_OVERRIDE_MASK (0xFFFFFFFFU)
#define SIM_LPAV_AXI_CACHE_OVERRIDE_AXI_CACHE_OVERRIDE_SHIFT (0U)
/*! AXI_CACHE_OVERRIDE - Audio-Video Domain AXI Cache Override */
#define SIM_LPAV_AXI_CACHE_OVERRIDE_AXI_CACHE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPAV_AXI_CACHE_OVERRIDE_AXI_CACHE_OVERRIDE_SHIFT)) & SIM_LPAV_AXI_CACHE_OVERRIDE_AXI_CACHE_OVERRIDE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SIM_LPAV_Register_Masks */


/* SIM_LPAV - Peripheral instance base addresses */
/** Peripheral SIM_LPAV base address */
#define SIM_LPAV_BASE                            (0x2DA50000u)
/** Peripheral SIM_LPAV base pointer */
#define SIM_LPAV                                 ((SIM_LPAV_Type *)SIM_LPAV_BASE)
/** Array initializer of SIM_LPAV peripheral base addresses */
#define SIM_LPAV_BASE_ADDRS                      { SIM_LPAV_BASE }
/** Array initializer of SIM_LPAV peripheral base pointers */
#define SIM_LPAV_BASE_PTRS                       { SIM_LPAV }

/*!
 * @}
 */ /* end of group SIM_LPAV_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SIM_SEC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SIM_SEC_Peripheral_Access_Layer SIM_SEC Peripheral Access Layer
 * @{
 */

/** SIM_SEC - Register Layout Typedef */
typedef struct {
  __IO uint32_t GPR0;                              /**< HW RGeneral Purpose Register 0, offset: 0x0 */
       uint32_t GPR1;                              /**< HW General Purpose Register 1, offset: 0x4 */
  __IO uint32_t DGO_CTRL0;                         /**< RTD SIM DGO Control Register 0, offset: 0x8 */
  __IO uint32_t DGO_CTRL1;                         /**< RTD SIM DGO Control Register 0, offset: 0xC */
  __IO uint32_t DGO_GP0;                           /**< RTD SIM DGO General Purpose Register 0, offset: 0x10 */
  __IO uint32_t DGO_GP1;                           /**< RTD SIM DGO General Purpose Register 1, offset: 0x14 */
  __IO uint32_t DGO_GP2;                           /**< RTD SIM DGO General Purpose Register 2, offset: 0x18 */
  __IO uint32_t DGO_GP3;                           /**< RTD SIM DGO General Purpose Register 3, offset: 0x1C */
  __IO uint32_t DGO_GP4;                           /**< RTD SIM DGO General Purpose Register 4, offset: 0x20 */
  __IO uint32_t DGO_GP5;                           /**< RTD SIM DGO General Purpose Register 5, offset: 0x24 */
  __IO uint32_t DGO_GP6;                           /**< RTD SIM DGO General Purpose Register 6, offset: 0x28 */
  __IO uint32_t DGO_GP7;                           /**< RTD SIM DGO General Purpose Register 7, offset: 0x2C */
  __IO uint32_t DGO_GP8;                           /**< RTD SIM DGO General Purpose Register 8, offset: 0x30 */
  __IO uint32_t DGO_GP9;                           /**< RESET0_B Pad and Filter Configuration, offset: 0x34 */
  __IO uint32_t DGO_GP10;                          /**< PTA Operating Range Control, offset: 0x38 */
  __IO uint32_t DGO_GP11;                          /**< PTB Operating Range Control, offset: 0x3C */
  __IO uint32_t DGO_GP12;                          /**< Low Power Debug Mux, offset: 0x40 */
  __IO uint32_t SYSCTRL0;                          /**< Realtime Domains System Control Register 0, offset: 0x44 */
  __IO uint32_t SSRAM_ACCESS_DISABLE;              /**< System Shared RAM Access Disable Register, offset: 0x48 */
  __IO uint32_t LPAV_MASTER_ALLOC_CTRL;            /**< LPAV Master Allocation Control Register, offset: 0x4C */
  __IO uint32_t LPAV_SLAVE_ALLOC_CTRL;             /**< LPAV Slave Allocation Control Register, offset: 0x50 */
  __IO uint32_t LPAV_DMA2_CH_ALLOC_CTRL;           /**< LPAV DMA2 CH Allocation Control Register, offset: 0x54 */
  __IO uint32_t LPAV_DMA2_REQ_ALLOC_CTRL;          /**< LPAV DMA2 Request Allocation Control Register, offset: 0x58 */
  __IO uint32_t M33_CFGSSTCALIB;                   /**< Secure SysTick Calibration Configuration, offset: 0x5C */
  __IO uint32_t FUSION_GPR0;                       /**< Fusion DSP General Purpose Register, offset: 0x60 */
  __I  uint32_t FUSION_GPR1;                       /**< Fusion DSP General Purpose Register, offset: 0x64 */
  __I  uint32_t FUSION_GPR2;                       /**< Fusion DSP General Purpose Register, offset: 0x68 */
  __IO uint32_t RTD_INTERRUPT_MASK0;               /**< Realtime Domain Interrupt Mask 0, offset: 0x6C */
  __IO uint32_t APD_INTERRUPT_MASK0;               /**< Application Domain Interrupt Mask 0, offset: 0x70 */
  __IO uint32_t AVD_INTERRUPT_MASK0;               /**< Audio-Video Domain Interrupt Mask 0, offset: 0x74 */
  __IO uint32_t WRITE_ASSIST_CTRL;                 /**< RTD Memories Write-Assist Control, offset: 0x78 */
  __IO uint32_t SYSCTRL1;                          /**< Realtime Domains System Control Register 1, offset: 0x7C */
  __IO uint32_t SYSCTRL2;                          /**< Realtime Domains System Control Register 2, offset: 0x80 */
  __IO uint32_t SYSCTRL3;                          /**< Realtime Domains System Control Register 3, offset: 0x84 */
  __IO uint32_t SYSCTRL4;                          /**< Realtime Domains System Control Register 4, offset: 0x88 */
} SIM_SEC_Type;

/* ----------------------------------------------------------------------------
   -- SIM_SEC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SIM_SEC_Register_Masks SIM_SEC Register Masks
 * @{
 */

/*! @name GPR0 - HW RGeneral Purpose Register 0 */
/*! @{ */

#define SIM_SEC_GPR0_GPR0_MASK                   (0xFFFFFFFFU)
#define SIM_SEC_GPR0_GPR0_SHIFT                  (0U)
/*! GPR0 - General Purpose Read/Write Register */
#define SIM_SEC_GPR0_GPR0(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SEC_GPR0_GPR0_SHIFT)) & SIM_SEC_GPR0_GPR0_MASK)
/*! @} */

/*! @name DGO_CTRL0 - RTD SIM DGO Control Register 0 */
/*! @{ */

#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP0_MASK    (0x1U)
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP0_SHIFT   (0U)
/*! UPDATE_DGO_GP0 - DGO General Purpose Register 0 Update */
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP0(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP0_SHIFT)) & SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP0_MASK)

#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP1_MASK    (0x2U)
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP1_SHIFT   (1U)
/*! UPDATE_DGO_GP1 - DGO General Purpose Register 1 Update */
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP1(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP1_SHIFT)) & SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP1_MASK)

#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP2_MASK    (0x4U)
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP2_SHIFT   (2U)
/*! UPDATE_DGO_GP2 - DGO General Purpose Register 2 Update */
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP2(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP2_SHIFT)) & SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP2_MASK)

#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP3_MASK    (0x8U)
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP3_SHIFT   (3U)
/*! UPDATE_DGO_GP3 - DGO General Purpose Register 3 Update */
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP3(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP3_SHIFT)) & SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP3_MASK)

#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP4_MASK    (0x10U)
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP4_SHIFT   (4U)
/*! UPDATE_DGO_GP4 - DGO General Purpose Register 4 Update */
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP4(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP4_SHIFT)) & SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP4_MASK)

#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP5_MASK    (0x20U)
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP5_SHIFT   (5U)
/*! UPDATE_DGO_GP5 - DGO General Purpose Register 5 Update */
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP5(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP5_SHIFT)) & SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP5_MASK)

#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP6_MASK    (0x40U)
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP6_SHIFT   (6U)
/*! UPDATE_DGO_GP6 - DGO General Purpose Register 6 Update */
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP6(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP6_SHIFT)) & SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP6_MASK)

#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP7_MASK    (0x80U)
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP7_SHIFT   (7U)
/*! UPDATE_DGO_GP7 - DGO General Purpose Register 7 Update */
#define SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP7(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP7_SHIFT)) & SIM_SEC_DGO_CTRL0_UPDATE_DGO_GP7_MASK)

#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP0_MASK    (0x100U)
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP0_SHIFT   (8U)
/*! WR_ACK_DGO_GP0 - DGO General Purpose Register 0 Write Acknowledge */
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP0(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP0_SHIFT)) & SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP0_MASK)

#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP1_MASK    (0x200U)
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP1_SHIFT   (9U)
/*! WR_ACK_DGO_GP1 - DGO General Purpose Register 1 Write Acknowledge */
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP1(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP1_SHIFT)) & SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP1_MASK)

#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP2_MASK    (0x400U)
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP2_SHIFT   (10U)
/*! WR_ACK_DGO_GP2 - DGO General Purpose Register 2 Write Acknowledge */
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP2(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP2_SHIFT)) & SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP2_MASK)

#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP3_MASK    (0x800U)
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP3_SHIFT   (11U)
/*! WR_ACK_DGO_GP3 - DGO General Purpose Register 3 Write Acknowledge */
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP3(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP3_SHIFT)) & SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP3_MASK)

#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP4_MASK    (0x1000U)
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP4_SHIFT   (12U)
/*! WR_ACK_DGO_GP4 - DGO General Purpose Register 4 Write Acknowledge */
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP4(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP4_SHIFT)) & SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP4_MASK)

#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP5_MASK    (0x2000U)
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP5_SHIFT   (13U)
/*! WR_ACK_DGO_GP5 - DGO General Purpose Register 5 Write Acknowledge */
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP5(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP5_SHIFT)) & SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP5_MASK)

#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP6_MASK    (0x4000U)
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP6_SHIFT   (14U)
/*! WR_ACK_DGO_GP6 - DGO General Purpose Register 6 Write Acknowledge */
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP6(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP6_SHIFT)) & SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP6_MASK)

#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP7_MASK    (0x8000U)
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP7_SHIFT   (15U)
/*! WR_ACK_DGO_GP7 - DGO General Purpose Register 7 Write Acknowledge */
#define SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP7(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP7_SHIFT)) & SIM_SEC_DGO_CTRL0_WR_ACK_DGO_GP7_MASK)

#define SIM_SEC_DGO_CTRL0_INT_EN_ACK0_MASK       (0x10000U)
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK0_SHIFT      (16U)
/*! INT_EN_ACK0 - DGO General Purpose Register 0 Interrupt Acknowledge */
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK0(x)         (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_INT_EN_ACK0_SHIFT)) & SIM_SEC_DGO_CTRL0_INT_EN_ACK0_MASK)

#define SIM_SEC_DGO_CTRL0_INT_EN_ACK1_MASK       (0x20000U)
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK1_SHIFT      (17U)
/*! INT_EN_ACK1 - DGO General Purpose Register 1 Interrupt Acknowledge */
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK1(x)         (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_INT_EN_ACK1_SHIFT)) & SIM_SEC_DGO_CTRL0_INT_EN_ACK1_MASK)

#define SIM_SEC_DGO_CTRL0_INT_EN_ACK2_MASK       (0x40000U)
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK2_SHIFT      (18U)
/*! INT_EN_ACK2 - DGO General Purpose Register 2 Interrupt Acknowledge */
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK2(x)         (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_INT_EN_ACK2_SHIFT)) & SIM_SEC_DGO_CTRL0_INT_EN_ACK2_MASK)

#define SIM_SEC_DGO_CTRL0_INT_EN_ACK3_MASK       (0x80000U)
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK3_SHIFT      (19U)
/*! INT_EN_ACK3 - DGO General Purpose Register 3 Interrupt Acknowledge */
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK3(x)         (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_INT_EN_ACK3_SHIFT)) & SIM_SEC_DGO_CTRL0_INT_EN_ACK3_MASK)

#define SIM_SEC_DGO_CTRL0_INT_EN_ACK4_MASK       (0x100000U)
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK4_SHIFT      (20U)
/*! INT_EN_ACK4 - DGO General Purpose Register 4 Interrupt Acknowledge */
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK4(x)         (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_INT_EN_ACK4_SHIFT)) & SIM_SEC_DGO_CTRL0_INT_EN_ACK4_MASK)

#define SIM_SEC_DGO_CTRL0_INT_EN_ACK5_MASK       (0x200000U)
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK5_SHIFT      (21U)
/*! INT_EN_ACK5 - DGO General Purpose Register 5 Interrupt Acknowledge */
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK5(x)         (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_INT_EN_ACK5_SHIFT)) & SIM_SEC_DGO_CTRL0_INT_EN_ACK5_MASK)

#define SIM_SEC_DGO_CTRL0_INT_EN_ACK6_MASK       (0x400000U)
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK6_SHIFT      (22U)
/*! INT_EN_ACK6 - DGO General Purpose Register 6 Interrupt Acknowledge */
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK6(x)         (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_INT_EN_ACK6_SHIFT)) & SIM_SEC_DGO_CTRL0_INT_EN_ACK6_MASK)

#define SIM_SEC_DGO_CTRL0_INT_EN_ACK7_MASK       (0x800000U)
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK7_SHIFT      (23U)
/*! INT_EN_ACK7 - DGO General Purpose Register 7 Interrupt Acknowledge */
#define SIM_SEC_DGO_CTRL0_INT_EN_ACK7(x)         (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL0_INT_EN_ACK7_SHIFT)) & SIM_SEC_DGO_CTRL0_INT_EN_ACK7_MASK)
/*! @} */

/*! @name DGO_CTRL1 - RTD SIM DGO Control Register 0 */
/*! @{ */

#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP8_MASK    (0x1U)
#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP8_SHIFT   (0U)
/*! UPDATE_DGO_GP8 - DGO General Purpose Register 8 Update */
#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP8(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP8_SHIFT)) & SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP8_MASK)

#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP9_MASK    (0x2U)
#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP9_SHIFT   (1U)
/*! UPDATE_DGO_GP9 - DGO General Purpose Register 9 Update */
#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP9(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP9_SHIFT)) & SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP9_MASK)

#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP10_MASK   (0x4U)
#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP10_SHIFT  (2U)
/*! UPDATE_DGO_GP10 - DGO General Purpose Register 10 Update */
#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP10(x)     (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP10_SHIFT)) & SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP10_MASK)

#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP11_MASK   (0x8U)
#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP11_SHIFT  (3U)
/*! UPDATE_DGO_GP11 - DGO General Purpose Register 11 Update */
#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP11(x)     (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP11_SHIFT)) & SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP11_MASK)

#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP12_MASK   (0x10U)
#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP12_SHIFT  (4U)
/*! UPDATE_DGO_GP12 - DGO General Purpose Register 12 Update */
#define SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP12(x)     (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP12_SHIFT)) & SIM_SEC_DGO_CTRL1_UPDATE_DGO_GP12_MASK)

#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP8_MASK    (0x100U)
#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP8_SHIFT   (8U)
/*! WR_ACK_DGO_GP8 - DGO General Purpose Register 8 Write Acknowledge */
#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP8(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP8_SHIFT)) & SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP8_MASK)

#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP9_MASK    (0x200U)
#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP9_SHIFT   (9U)
/*! WR_ACK_DGO_GP9 - DGO General Purpose Register 9 Write Acknowledge */
#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP9(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP9_SHIFT)) & SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP9_MASK)

#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP10_MASK   (0x400U)
#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP10_SHIFT  (10U)
/*! WR_ACK_DGO_GP10 - DGO General Purpose Register 10 Write Acknowledge */
#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP10(x)     (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP10_SHIFT)) & SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP10_MASK)

#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP11_MASK   (0x800U)
#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP11_SHIFT  (11U)
/*! WR_ACK_DGO_GP11 - DGO General Purpose Register 11 Write Acknowledge */
#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP11(x)     (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP11_SHIFT)) & SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP11_MASK)

#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP12_MASK   (0x1000U)
#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP12_SHIFT  (12U)
/*! WR_ACK_DGO_GP12 - DGO General Purpose Register 12 Write Acknowledge */
#define SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP12(x)     (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP12_SHIFT)) & SIM_SEC_DGO_CTRL1_WR_ACK_DGO_GP12_MASK)

#define SIM_SEC_DGO_CTRL1_INT_EN_ACK8_MASK       (0x10000U)
#define SIM_SEC_DGO_CTRL1_INT_EN_ACK8_SHIFT      (16U)
/*! INT_EN_ACK8 - DGO General Purpose Register 8 Interrupt Acknowledge */
#define SIM_SEC_DGO_CTRL1_INT_EN_ACK8(x)         (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_INT_EN_ACK8_SHIFT)) & SIM_SEC_DGO_CTRL1_INT_EN_ACK8_MASK)

#define SIM_SEC_DGO_CTRL1_INT_EN_ACK9_MASK       (0x20000U)
#define SIM_SEC_DGO_CTRL1_INT_EN_ACK9_SHIFT      (17U)
/*! INT_EN_ACK9 - DGO General Purpose Register 9 Interrupt Acknowledge */
#define SIM_SEC_DGO_CTRL1_INT_EN_ACK9(x)         (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_INT_EN_ACK9_SHIFT)) & SIM_SEC_DGO_CTRL1_INT_EN_ACK9_MASK)

#define SIM_SEC_DGO_CTRL1_INT_EN_ACK10_MASK      (0x40000U)
#define SIM_SEC_DGO_CTRL1_INT_EN_ACK10_SHIFT     (18U)
/*! INT_EN_ACK10 - DGO General Purpose Register 10 Interrupt Acknowledge */
#define SIM_SEC_DGO_CTRL1_INT_EN_ACK10(x)        (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_INT_EN_ACK10_SHIFT)) & SIM_SEC_DGO_CTRL1_INT_EN_ACK10_MASK)

#define SIM_SEC_DGO_CTRL1_INT_EN_ACK11_MASK      (0x80000U)
#define SIM_SEC_DGO_CTRL1_INT_EN_ACK11_SHIFT     (19U)
/*! INT_EN_ACK11 - DGO General Purpose Register 11 Interrupt Acknowledge */
#define SIM_SEC_DGO_CTRL1_INT_EN_ACK11(x)        (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_INT_EN_ACK11_SHIFT)) & SIM_SEC_DGO_CTRL1_INT_EN_ACK11_MASK)

#define SIM_SEC_DGO_CTRL1_INT_EN_ACK12_MASK      (0x100000U)
#define SIM_SEC_DGO_CTRL1_INT_EN_ACK12_SHIFT     (20U)
/*! INT_EN_ACK12 - DGO General Purpose Register 12 Interrupt Acknowledge */
#define SIM_SEC_DGO_CTRL1_INT_EN_ACK12(x)        (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_CTRL1_INT_EN_ACK12_SHIFT)) & SIM_SEC_DGO_CTRL1_INT_EN_ACK12_MASK)
/*! @} */

/*! @name DGO_GP0 - RTD SIM DGO General Purpose Register 0 */
/*! @{ */

#define SIM_SEC_DGO_GP0_SIM_DGO_GP0_MASK         (0xFFFFFFFFU)
#define SIM_SEC_DGO_GP0_SIM_DGO_GP0_SHIFT        (0U)
/*! SIM_DGO_GP0 - SIM DGO General purpose register 0 */
#define SIM_SEC_DGO_GP0_SIM_DGO_GP0(x)           (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP0_SIM_DGO_GP0_SHIFT)) & SIM_SEC_DGO_GP0_SIM_DGO_GP0_MASK)
/*! @} */

/*! @name DGO_GP1 - RTD SIM DGO General Purpose Register 1 */
/*! @{ */

#define SIM_SEC_DGO_GP1_SIM_DGO_GP1_MASK         (0xFFFFFFFFU)
#define SIM_SEC_DGO_GP1_SIM_DGO_GP1_SHIFT        (0U)
/*! SIM_DGO_GP1 - SIM DGO General purpose register 1 */
#define SIM_SEC_DGO_GP1_SIM_DGO_GP1(x)           (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP1_SIM_DGO_GP1_SHIFT)) & SIM_SEC_DGO_GP1_SIM_DGO_GP1_MASK)
/*! @} */

/*! @name DGO_GP2 - RTD SIM DGO General Purpose Register 2 */
/*! @{ */

#define SIM_SEC_DGO_GP2_SIM_DGO_GP2_MASK         (0xFFFFFFFFU)
#define SIM_SEC_DGO_GP2_SIM_DGO_GP2_SHIFT        (0U)
/*! SIM_DGO_GP2 - SIM DGO General purpose register 2 */
#define SIM_SEC_DGO_GP2_SIM_DGO_GP2(x)           (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP2_SIM_DGO_GP2_SHIFT)) & SIM_SEC_DGO_GP2_SIM_DGO_GP2_MASK)
/*! @} */

/*! @name DGO_GP3 - RTD SIM DGO General Purpose Register 3 */
/*! @{ */

#define SIM_SEC_DGO_GP3_SIM_DGO_GP3_MASK         (0xFFFFFFFFU)
#define SIM_SEC_DGO_GP3_SIM_DGO_GP3_SHIFT        (0U)
/*! SIM_DGO_GP3 - SIM DGO General purpose register 3 */
#define SIM_SEC_DGO_GP3_SIM_DGO_GP3(x)           (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP3_SIM_DGO_GP3_SHIFT)) & SIM_SEC_DGO_GP3_SIM_DGO_GP3_MASK)
/*! @} */

/*! @name DGO_GP4 - RTD SIM DGO General Purpose Register 4 */
/*! @{ */

#define SIM_SEC_DGO_GP4_SIM_DGO_GP4_MASK         (0xFFFFFFFFU)
#define SIM_SEC_DGO_GP4_SIM_DGO_GP4_SHIFT        (0U)
/*! SIM_DGO_GP4 - SIM DGO General purpose register 4 */
#define SIM_SEC_DGO_GP4_SIM_DGO_GP4(x)           (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP4_SIM_DGO_GP4_SHIFT)) & SIM_SEC_DGO_GP4_SIM_DGO_GP4_MASK)
/*! @} */

/*! @name DGO_GP5 - RTD SIM DGO General Purpose Register 5 */
/*! @{ */

#define SIM_SEC_DGO_GP5_SIM_DGO_GP5_MASK         (0xFFFFFFFFU)
#define SIM_SEC_DGO_GP5_SIM_DGO_GP5_SHIFT        (0U)
/*! SIM_DGO_GP5 - SIM DGO General purpose register 5 */
#define SIM_SEC_DGO_GP5_SIM_DGO_GP5(x)           (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP5_SIM_DGO_GP5_SHIFT)) & SIM_SEC_DGO_GP5_SIM_DGO_GP5_MASK)
/*! @} */

/*! @name DGO_GP6 - RTD SIM DGO General Purpose Register 6 */
/*! @{ */

#define SIM_SEC_DGO_GP6_SIM_DGO_GP6_MASK         (0xFFFFFFFFU)
#define SIM_SEC_DGO_GP6_SIM_DGO_GP6_SHIFT        (0U)
/*! SIM_DGO_GP6 - SIM DGO General purpose register 6 */
#define SIM_SEC_DGO_GP6_SIM_DGO_GP6(x)           (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP6_SIM_DGO_GP6_SHIFT)) & SIM_SEC_DGO_GP6_SIM_DGO_GP6_MASK)
/*! @} */

/*! @name DGO_GP7 - RTD SIM DGO General Purpose Register 7 */
/*! @{ */

#define SIM_SEC_DGO_GP7_SIM_DGO_GP7_MASK         (0xFFFFFFFFU)
#define SIM_SEC_DGO_GP7_SIM_DGO_GP7_SHIFT        (0U)
/*! SIM_DGO_GP7 - SIM DGO General purpose register 7 */
#define SIM_SEC_DGO_GP7_SIM_DGO_GP7(x)           (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP7_SIM_DGO_GP7_SHIFT)) & SIM_SEC_DGO_GP7_SIM_DGO_GP7_MASK)
/*! @} */

/*! @name DGO_GP8 - RTD SIM DGO General Purpose Register 8 */
/*! @{ */

#define SIM_SEC_DGO_GP8_SIM_DGO_GP8_MASK         (0xFFFFFFFFU)
#define SIM_SEC_DGO_GP8_SIM_DGO_GP8_SHIFT        (0U)
/*! SIM_DGO_GP8 - SIM DGO General purpose register 8 */
#define SIM_SEC_DGO_GP8_SIM_DGO_GP8(x)           (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP8_SIM_DGO_GP8_SHIFT)) & SIM_SEC_DGO_GP8_SIM_DGO_GP8_MASK)
/*! @} */

/*! @name DGO_GP9 - RESET0_B Pad and Filter Configuration */
/*! @{ */

#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PS_MASK  (0x1U)
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PS_SHIFT (0U)
/*! RESET0_B_CONFIG_PS - Weak Pull Select */
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PS(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PS_SHIFT)) & SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PS_MASK)

#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PE_MASK  (0x2U)
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PE_SHIFT (1U)
/*! RESET0_B_CONFIG_PE - Weak Pull Enable */
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PE(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PE_SHIFT)) & SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PE_MASK)

#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_SRE_MASK (0x4U)
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_SRE_SHIFT (2U)
/*! RESET0_B_CONFIG_SRE - Slew Rate Enable */
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_SRE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP9_RESET0_B_CONFIG_SRE_SHIFT)) & SIM_SEC_DGO_GP9_RESET0_B_CONFIG_SRE_MASK)

#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PFE_MASK (0x10U)
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PFE_SHIFT (4U)
/*! RESET0_B_CONFIG_PFE - Passive Filter Enable */
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PFE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PFE_SHIFT)) & SIM_SEC_DGO_GP9_RESET0_B_CONFIG_PFE_MASK)

#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_ODE_MASK (0x20U)
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_ODE_SHIFT (5U)
/*! RESET0_B_CONFIG_ODE - Open Drain Enable */
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_ODE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP9_RESET0_B_CONFIG_ODE_SHIFT)) & SIM_SEC_DGO_GP9_RESET0_B_CONFIG_ODE_MASK)

#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DSE_MASK (0x40U)
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DSE_SHIFT (6U)
/*! RESET0_B_CONFIG_DSE - Drive Strength Enable */
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DSE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DSE_SHIFT)) & SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DSE_MASK)

#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_LK_MASK  (0x8000U)
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_LK_SHIFT (15U)
/*! RESET0_B_CONFIG_LK - Lock: Locks writes to this register */
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_LK(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP9_RESET0_B_CONFIG_LK_SHIFT)) & SIM_SEC_DGO_GP9_RESET0_B_CONFIG_LK_MASK)

#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFE_MASK (0x100000U)
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFE_SHIFT (20U)
/*! RESET0_B_CONFIG_DFE - Digital Filter Enable */
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFE_SHIFT)) & SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFE_MASK)

#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFCS_MASK (0x200000U)
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFCS_SHIFT (21U)
/*! RESET0_B_CONFIG_DFCS - Digital Filter Clock Select */
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFCS(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFCS_SHIFT)) & SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFCS_MASK)

#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFD_MASK (0xFC00000U)
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFD_SHIFT (22U)
/*! RESET0_B_CONFIG_DFD - Digital Filter duration: Defines deglitch count */
#define SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFD_SHIFT)) & SIM_SEC_DGO_GP9_RESET0_B_CONFIG_DFD_MASK)
/*! @} */

/*! @name DGO_GP10 - PTA Operating Range Control */
/*! @{ */

#define SIM_SEC_DGO_GP10_PTA_OPERATING_RANGE_MASK (0x3U)
#define SIM_SEC_DGO_GP10_PTA_OPERATING_RANGE_SHIFT (0U)
/*! PTA_OPERATING_RANGE - PTA Operating Range (Write Once) */
#define SIM_SEC_DGO_GP10_PTA_OPERATING_RANGE(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP10_PTA_OPERATING_RANGE_SHIFT)) & SIM_SEC_DGO_GP10_PTA_OPERATING_RANGE_MASK)
/*! @} */

/*! @name DGO_GP11 - PTB Operating Range Control */
/*! @{ */

#define SIM_SEC_DGO_GP11_PTB_OPERATING_RANGE_MASK (0x1U)
#define SIM_SEC_DGO_GP11_PTB_OPERATING_RANGE_SHIFT (0U)
/*! PTB_OPERATING_RANGE - PTB Operating Range (Write Once) */
#define SIM_SEC_DGO_GP11_PTB_OPERATING_RANGE(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP11_PTB_OPERATING_RANGE_SHIFT)) & SIM_SEC_DGO_GP11_PTB_OPERATING_RANGE_MASK)
/*! @} */

/*! @name DGO_GP12 - Low Power Debug Mux */
/*! @{ */

#define SIM_SEC_DGO_GP12_LP_DEBUG_MUX_LV_SEL_APD_MASK (0xFFU)
#define SIM_SEC_DGO_GP12_LP_DEBUG_MUX_LV_SEL_APD_SHIFT (0U)
/*! LP_DEBUG_MUX_LV_SEL_APD - Low Voltage Select Application Domain */
#define SIM_SEC_DGO_GP12_LP_DEBUG_MUX_LV_SEL_APD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP12_LP_DEBUG_MUX_LV_SEL_APD_SHIFT)) & SIM_SEC_DGO_GP12_LP_DEBUG_MUX_LV_SEL_APD_MASK)

#define SIM_SEC_DGO_GP12_LP_DEBUG_MUX_LV_SEL_RTD_MASK (0xFF00U)
#define SIM_SEC_DGO_GP12_LP_DEBUG_MUX_LV_SEL_RTD_SHIFT (8U)
/*! LP_DEBUG_MUX_LV_SEL_RTD - Low Voltage Select Realtime Domain */
#define SIM_SEC_DGO_GP12_LP_DEBUG_MUX_LV_SEL_RTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP12_LP_DEBUG_MUX_LV_SEL_RTD_SHIFT)) & SIM_SEC_DGO_GP12_LP_DEBUG_MUX_LV_SEL_RTD_MASK)

#define SIM_SEC_DGO_GP12_LP_DEBUG_MUX_HV_SEL_MASK (0x7FF0000U)
#define SIM_SEC_DGO_GP12_LP_DEBUG_MUX_HV_SEL_SHIFT (16U)
/*! LP_DEBUG_MUX_HV_SEL - High Voltage Select */
#define SIM_SEC_DGO_GP12_LP_DEBUG_MUX_HV_SEL(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_DGO_GP12_LP_DEBUG_MUX_HV_SEL_SHIFT)) & SIM_SEC_DGO_GP12_LP_DEBUG_MUX_HV_SEL_MASK)
/*! @} */

/*! @name SYSCTRL0 - Realtime Domains System Control Register 0 */
/*! @{ */

#define SIM_SEC_SYSCTRL0_CM33_RST_REQ_MASK       (0x4U)
#define SIM_SEC_SYSCTRL0_CM33_RST_REQ_SHIFT      (2U)
/*! CM33_RST_REQ - Request to reset CM33 core, CM33 cache controller, watchdog0 and watchdog1 */
#define SIM_SEC_SYSCTRL0_CM33_RST_REQ(x)         (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_CM33_RST_REQ_SHIFT)) & SIM_SEC_SYSCTRL0_CM33_RST_REQ_MASK)

#define SIM_SEC_SYSCTRL0_CM33_RST_ACK_MASK       (0x8U)
#define SIM_SEC_SYSCTRL0_CM33_RST_ACK_SHIFT      (3U)
/*! CM33_RST_ACK - CM33 Core is in safe state for reset sequencing */
#define SIM_SEC_SYSCTRL0_CM33_RST_ACK(x)         (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_CM33_RST_ACK_SHIFT)) & SIM_SEC_SYSCTRL0_CM33_RST_ACK_MASK)

#define SIM_SEC_SYSCTRL0_CAAM_RTIC_MODE_MASK     (0x10U)
#define SIM_SEC_SYSCTRL0_CAAM_RTIC_MODE_SHIFT    (4U)
/*! CAAM_RTIC_MODE - CAAM RTIC Run Time Mode Control */
#define SIM_SEC_SYSCTRL0_CAAM_RTIC_MODE(x)       (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_CAAM_RTIC_MODE_SHIFT)) & SIM_SEC_SYSCTRL0_CAAM_RTIC_MODE_MASK)

#define SIM_SEC_SYSCTRL0_M33_FPU_DISABLE_MASK    (0x20U)
#define SIM_SEC_SYSCTRL0_M33_FPU_DISABLE_SHIFT   (5U)
/*! M33_FPU_DISABLE - M33 FPU Disable */
#define SIM_SEC_SYSCTRL0_M33_FPU_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_M33_FPU_DISABLE_SHIFT)) & SIM_SEC_SYSCTRL0_M33_FPU_DISABLE_MASK)

#define SIM_SEC_SYSCTRL0_M33_DSP_DISABLE_MASK    (0x40U)
#define SIM_SEC_SYSCTRL0_M33_DSP_DISABLE_SHIFT   (6U)
/*! M33_DSP_DISABLE - M33 DSP Disable */
#define SIM_SEC_SYSCTRL0_M33_DSP_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_M33_DSP_DISABLE_SHIFT)) & SIM_SEC_SYSCTRL0_M33_DSP_DISABLE_MASK)

#define SIM_SEC_SYSCTRL0_LPAV_MASTER_CTRL_MASK   (0x80U)
#define SIM_SEC_SYSCTRL0_LPAV_MASTER_CTRL_SHIFT  (7U)
/*! LPAV_MASTER_CTRL - Low-Power Audio-Video Master Control */
#define SIM_SEC_SYSCTRL0_LPAV_MASTER_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_LPAV_MASTER_CTRL_SHIFT)) & SIM_SEC_SYSCTRL0_LPAV_MASTER_CTRL_MASK)

#define SIM_SEC_SYSCTRL0_NSSYSTICK_CLK_SEL_MASK  (0x100U)
#define SIM_SEC_SYSCTRL0_NSSYSTICK_CLK_SEL_SHIFT (8U)
/*! NSSYSTICK_CLK_SEL - Non-Secure Systick Clock Select */
#define SIM_SEC_SYSCTRL0_NSSYSTICK_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_NSSYSTICK_CLK_SEL_SHIFT)) & SIM_SEC_SYSCTRL0_NSSYSTICK_CLK_SEL_MASK)

#define SIM_SEC_SYSCTRL0_SSYSTICK_CLK_SEL_MASK   (0x200U)
#define SIM_SEC_SYSCTRL0_SSYSTICK_CLK_SEL_SHIFT  (9U)
/*! SSYSTICK_CLK_SEL - Secure Systick Clock Select */
#define SIM_SEC_SYSCTRL0_SSYSTICK_CLK_SEL(x)     (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_SSYSTICK_CLK_SEL_SHIFT)) & SIM_SEC_SYSCTRL0_SSYSTICK_CLK_SEL_MASK)

#define SIM_SEC_SYSCTRL0_WDOG1_RESET_EN_MASK     (0x400U)
#define SIM_SEC_SYSCTRL0_WDOG1_RESET_EN_SHIFT    (10U)
/*! WDOG1_RESET_EN - Watchdog 1 reset enable */
#define SIM_SEC_SYSCTRL0_WDOG1_RESET_EN(x)       (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_WDOG1_RESET_EN_SHIFT)) & SIM_SEC_SYSCTRL0_WDOG1_RESET_EN_MASK)

#define SIM_SEC_SYSCTRL0_FUSION_PLAT_HCLK_EN_MASK (0x800U)
#define SIM_SEC_SYSCTRL0_FUSION_PLAT_HCLK_EN_SHIFT (11U)
/*! FUSION_PLAT_HCLK_EN - fusion_plat_hclk Clock Enable */
#define SIM_SEC_SYSCTRL0_FUSION_PLAT_HCLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_FUSION_PLAT_HCLK_EN_SHIFT)) & SIM_SEC_SYSCTRL0_FUSION_PLAT_HCLK_EN_MASK)

#define SIM_SEC_SYSCTRL0_FUSION_CLK_EN_MASK      (0x1000U)
#define SIM_SEC_SYSCTRL0_FUSION_CLK_EN_SHIFT     (12U)
/*! FUSION_CLK_EN - fusion_clk Clock Enable */
#define SIM_SEC_SYSCTRL0_FUSION_CLK_EN(x)        (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_FUSION_CLK_EN_SHIFT)) & SIM_SEC_SYSCTRL0_FUSION_CLK_EN_MASK)

#define SIM_SEC_SYSCTRL0_FUSION_BCLK_EN_MASK     (0x2000U)
#define SIM_SEC_SYSCTRL0_FUSION_BCLK_EN_SHIFT    (13U)
/*! FUSION_BCLK_EN - fusion_bclk Clock Enable */
#define SIM_SEC_SYSCTRL0_FUSION_BCLK_EN(x)       (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_FUSION_BCLK_EN_SHIFT)) & SIM_SEC_SYSCTRL0_FUSION_BCLK_EN_MASK)

#define SIM_SEC_SYSCTRL0_FUSION_PBCLK_EN_MASK    (0x8000U)
#define SIM_SEC_SYSCTRL0_FUSION_PBCLK_EN_SHIFT   (15U)
/*! FUSION_PBCLK_EN - fusion_PBCLK Clock Enable */
#define SIM_SEC_SYSCTRL0_FUSION_PBCLK_EN(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_FUSION_PBCLK_EN_SHIFT)) & SIM_SEC_SYSCTRL0_FUSION_PBCLK_EN_MASK)

#define SIM_SEC_SYSCTRL0_CASPER_RST_MASK         (0x10000U)
#define SIM_SEC_SYSCTRL0_CASPER_RST_SHIFT        (16U)
/*! CASPER_RST - Controls the Casper Co-Processor Reset */
#define SIM_SEC_SYSCTRL0_CASPER_RST(x)           (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_CASPER_RST_SHIFT)) & SIM_SEC_SYSCTRL0_CASPER_RST_MASK)

#define SIM_SEC_SYSCTRL0_POWERQUAD_RST_MASK      (0x20000U)
#define SIM_SEC_SYSCTRL0_POWERQUAD_RST_SHIFT     (17U)
/*! POWERQUAD_RST - Controls the PowerQuad Co-Processor Reset */
#define SIM_SEC_SYSCTRL0_POWERQUAD_RST(x)        (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_POWERQUAD_RST_SHIFT)) & SIM_SEC_SYSCTRL0_POWERQUAD_RST_MASK)

#define SIM_SEC_SYSCTRL0_FUSION_DSP_RST_MASK     (0x40000U)
#define SIM_SEC_SYSCTRL0_FUSION_DSP_RST_SHIFT    (18U)
/*! FUSION_DSP_RST - Controls the Fusion DSP Reset */
#define SIM_SEC_SYSCTRL0_FUSION_DSP_RST(x)       (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_FUSION_DSP_RST_SHIFT)) & SIM_SEC_SYSCTRL0_FUSION_DSP_RST_MASK)

#define SIM_SEC_SYSCTRL0_FUSION_DSP_DBG_MODE_MASK (0x100000U)
#define SIM_SEC_SYSCTRL0_FUSION_DSP_DBG_MODE_SHIFT (20U)
/*! FUSION_DSP_DBG_MODE - Fusion DSP in OCD Halt or Other Debug Mode */
#define SIM_SEC_SYSCTRL0_FUSION_DSP_DBG_MODE(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_FUSION_DSP_DBG_MODE_SHIFT)) & SIM_SEC_SYSCTRL0_FUSION_DSP_DBG_MODE_MASK)

#define SIM_SEC_SYSCTRL0_FUSION_DSP_DBG_RST_MASK (0x200000U)
#define SIM_SEC_SYSCTRL0_FUSION_DSP_DBG_RST_SHIFT (21U)
/*! FUSION_DSP_DBG_RST - Reset Fusion DSP Debug logic */
#define SIM_SEC_SYSCTRL0_FUSION_DSP_DBG_RST(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_FUSION_DSP_DBG_RST_SHIFT)) & SIM_SEC_SYSCTRL0_FUSION_DSP_DBG_RST_MASK)

#define SIM_SEC_SYSCTRL0_FUSION_DSP_OCD_HALT_MASK (0x400000U)
#define SIM_SEC_SYSCTRL0_FUSION_DSP_OCD_HALT_SHIFT (22U)
/*! FUSION_DSP_OCD_HALT - Fusion DSP in OCD Halt or Other Debug Mode */
#define SIM_SEC_SYSCTRL0_FUSION_DSP_OCD_HALT(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_FUSION_DSP_OCD_HALT_SHIFT)) & SIM_SEC_SYSCTRL0_FUSION_DSP_OCD_HALT_MASK)

#define SIM_SEC_SYSCTRL0_FUSION_DSP_STALL_MASK   (0x800000U)
#define SIM_SEC_SYSCTRL0_FUSION_DSP_STALL_SHIFT  (23U)
/*! FUSION_DSP_STALL - Stall Fusion DSP Execution */
#define SIM_SEC_SYSCTRL0_FUSION_DSP_STALL(x)     (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_FUSION_DSP_STALL_SHIFT)) & SIM_SEC_SYSCTRL0_FUSION_DSP_STALL_MASK)

#define SIM_SEC_SYSCTRL0_RGPIOA_TZ_DISABLE_MASK  (0x1000000U)
#define SIM_SEC_SYSCTRL0_RGPIOA_TZ_DISABLE_SHIFT (24U)
/*! RGPIOA_TZ_DISABLE - RGPIOA Trust Zone Disable */
#define SIM_SEC_SYSCTRL0_RGPIOA_TZ_DISABLE(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_RGPIOA_TZ_DISABLE_SHIFT)) & SIM_SEC_SYSCTRL0_RGPIOA_TZ_DISABLE_MASK)

#define SIM_SEC_SYSCTRL0_RGPIOB_TZ_DISABLE_MASK  (0x2000000U)
#define SIM_SEC_SYSCTRL0_RGPIOB_TZ_DISABLE_SHIFT (25U)
/*! RGPIOB_TZ_DISABLE - RGPIOB Trust Zone Disable */
#define SIM_SEC_SYSCTRL0_RGPIOB_TZ_DISABLE(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_RGPIOB_TZ_DISABLE_SHIFT)) & SIM_SEC_SYSCTRL0_RGPIOB_TZ_DISABLE_MASK)

#define SIM_SEC_SYSCTRL0_RGPIOC_TZ_DISABLE_MASK  (0x4000000U)
#define SIM_SEC_SYSCTRL0_RGPIOC_TZ_DISABLE_SHIFT (26U)
/*! RGPIOC_TZ_DISABLE - RGPIOC Trust Zone Disable */
#define SIM_SEC_SYSCTRL0_RGPIOC_TZ_DISABLE(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL0_RGPIOC_TZ_DISABLE_SHIFT)) & SIM_SEC_SYSCTRL0_RGPIOC_TZ_DISABLE_MASK)
/*! @} */

/*! @name SSRAM_ACCESS_DISABLE - System Shared RAM Access Disable Register */
/*! @{ */

#define SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_AHB_ACCESS_DISABLE_MASK (0xFFU)
#define SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_AHB_ACCESS_DISABLE_SHIFT (0U)
/*! SSRAM_AHB_ACCESS_DISABLE - System Shared RAM AHB Access Disable */
#define SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_AHB_ACCESS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_AHB_ACCESS_DISABLE_SHIFT)) & SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_AHB_ACCESS_DISABLE_MASK)

#define SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_AXI_ACCESS_DISABLE_MASK (0xFF00U)
#define SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_AXI_ACCESS_DISABLE_SHIFT (8U)
/*! SSRAM_AXI_ACCESS_DISABLE - System Shared RAM AXI Access Disable */
#define SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_AXI_ACCESS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_AXI_ACCESS_DISABLE_SHIFT)) & SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_AXI_ACCESS_DISABLE_MASK)

#define SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_DSP_ACCESS_DISABLE_MASK (0xFF0000U)
#define SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_DSP_ACCESS_DISABLE_SHIFT (16U)
/*! SSRAM_DSP_ACCESS_DISABLE - System Shared RAM DSP Access Disable */
#define SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_DSP_ACCESS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_DSP_ACCESS_DISABLE_SHIFT)) & SIM_SEC_SSRAM_ACCESS_DISABLE_SSRAM_DSP_ACCESS_DISABLE_MASK)
/*! @} */

/*! @name LPAV_MASTER_ALLOC_CTRL - LPAV Master Allocation Control Register */
/*! @{ */

#define SIM_SEC_LPAV_MASTER_ALLOC_CTRL_DCNANO_MASK (0x8U)
#define SIM_SEC_LPAV_MASTER_ALLOC_CTRL_DCNANO_SHIFT (3U)
/*! DCNANO - DCNANO */
#define SIM_SEC_LPAV_MASTER_ALLOC_CTRL_DCNANO(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_MASTER_ALLOC_CTRL_DCNANO_SHIFT)) & SIM_SEC_LPAV_MASTER_ALLOC_CTRL_DCNANO_MASK)

#define SIM_SEC_LPAV_MASTER_ALLOC_CTRL_MIPI_DSI_MASK (0x10U)
#define SIM_SEC_LPAV_MASTER_ALLOC_CTRL_MIPI_DSI_SHIFT (4U)
/*! MIPI_DSI - MIPI_DSI */
#define SIM_SEC_LPAV_MASTER_ALLOC_CTRL_MIPI_DSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_MASTER_ALLOC_CTRL_MIPI_DSI_SHIFT)) & SIM_SEC_LPAV_MASTER_ALLOC_CTRL_MIPI_DSI_MASK)
/*! @} */

/*! @name LPAV_SLAVE_ALLOC_CTRL - LPAV Slave Allocation Control Register */
/*! @{ */

#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SAI6_MASK  (0x1U)
#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SAI6_SHIFT (0U)
/*! SAI6 - SAI6 */
#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SAI6(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SAI6_SHIFT)) & SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SAI6_MASK)

#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SAI7_MASK  (0x2U)
#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SAI7_SHIFT (1U)
/*! SAI7 - SAI7 */
#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SAI7(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SAI7_SHIFT)) & SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SAI7_MASK)

#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SEMA42_MASK (0x4U)
#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SEMA42_SHIFT (2U)
/*! SEMA42 - SEMA42 */
#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SEMA42(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SEMA42_SHIFT)) & SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SEMA42_MASK)

#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_LPTPM8_MASK (0x8U)
#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_LPTPM8_SHIFT (3U)
/*! LPTPM8 - LPTPM8 */
#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_LPTPM8(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_LPTPM8_SHIFT)) & SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_LPTPM8_MASK)

#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SPDIF_MASK (0x10U)
#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SPDIF_SHIFT (4U)
/*! SPDIF - SPDIF */
#define SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SPDIF(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SPDIF_SHIFT)) & SIM_SEC_LPAV_SLAVE_ALLOC_CTRL_SPDIF_MASK)
/*! @} */

/*! @name LPAV_DMA2_CH_ALLOC_CTRL - LPAV DMA2 CH Allocation Control Register */
/*! @{ */

#define SIM_SEC_LPAV_DMA2_CH_ALLOC_CTRL_LPAV_DMA2_CH_ALLOC_CTRL_MASK (0xFFFFFFFFU)
#define SIM_SEC_LPAV_DMA2_CH_ALLOC_CTRL_LPAV_DMA2_CH_ALLOC_CTRL_SHIFT (0U)
/*! LPAV_DMA2_CH_ALLOC_CTRL - LPAV DMA2 CH Allocation Control Register */
#define SIM_SEC_LPAV_DMA2_CH_ALLOC_CTRL_LPAV_DMA2_CH_ALLOC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_CH_ALLOC_CTRL_LPAV_DMA2_CH_ALLOC_CTRL_SHIFT)) & SIM_SEC_LPAV_DMA2_CH_ALLOC_CTRL_LPAV_DMA2_CH_ALLOC_CTRL_MASK)
/*! @} */

/*! @name LPAV_DMA2_REQ_ALLOC_CTRL - LPAV DMA2 Request Allocation Control Register */
/*! @{ */

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPTPM8_MASK (0x1U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPTPM8_SHIFT (0U)
/*! LPTPM8 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPTPM8(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPTPM8_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPTPM8_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI0_MASK (0x2U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI0_SHIFT (1U)
/*! FLEXSPI0 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI0_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI0_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI1_MASK (0x4U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI1_SHIFT (2U)
/*! FLEXSPI1 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI1_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI1_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI2_MASK (0x8U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI2_SHIFT (3U)
/*! FLEXSPI2 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI2_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXSPI2_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXIO0_MASK (0x10U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXIO0_SHIFT (4U)
/*! FLEXIO0 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXIO0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXIO0_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXIO0_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXIO1_MASK (0x20U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXIO1_SHIFT (5U)
/*! FLEXIO1 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXIO1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXIO1_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_FLEXIO1_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPI2C3_MASK (0x40U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPI2C3_SHIFT (6U)
/*! LPI2C3 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPI2C3_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPI2C3_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPI2C5_MASK (0x80U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPI2C5_SHIFT (7U)
/*! LPI2C5 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPI2C5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPI2C5_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPI2C5_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_I3C1_MASK (0x100U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_I3C1_SHIFT (8U)
/*! I3C1 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_I3C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_I3C1_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_I3C1_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_I3C2_MASK (0x200U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_I3C2_SHIFT (9U)
/*! I3C2 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_I3C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_I3C2_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_I3C2_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPSPI3_MASK (0x400U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPSPI3_SHIFT (10U)
/*! LPSPI3 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPSPI3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPSPI3_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPSPI3_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPSPI5_MASK (0x800U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPSPI5_SHIFT (11U)
/*! LPSPI5 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPSPI5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPSPI5_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPSPI5_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPUART3_MASK (0x1000U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPUART3_SHIFT (12U)
/*! LPUART3 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPUART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPUART3_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPUART3_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPUART5_MASK (0x2000U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPUART5_SHIFT (13U)
/*! LPUART5 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPUART5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPUART5_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_LPUART5_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI0_MASK (0x4000U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI0_SHIFT (14U)
/*! SAI0 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI0_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI0_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI1_MASK (0x8000U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI1_SHIFT (15U)
/*! SAI1 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI1_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI1_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI4_MASK (0x10000U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI4_SHIFT (16U)
/*! SAI4 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI4_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI4_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI5_MASK (0x20000U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI5_SHIFT (17U)
/*! SAI5 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI5_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI5_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI6_MASK (0x40000U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI6_SHIFT (18U)
/*! SAI6 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI6(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI6_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI6_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI7_MASK (0x80000U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI7_SHIFT (19U)
/*! SAI7 - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI7(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI7_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SAI7_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SPDIF_MASK (0x100000U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SPDIF_SHIFT (20U)
/*! SPDIF - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SPDIF_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_SPDIF_MASK)

#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_GPIOD_MASK (0x200000U)
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_GPIOD_SHIFT (21U)
/*! GPIOD - DMA2 Request Allocation */
#define SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_GPIOD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_GPIOD_SHIFT)) & SIM_SEC_LPAV_DMA2_REQ_ALLOC_CTRL_GPIOD_MASK)
/*! @} */

/*! @name M33_CFGSSTCALIB - Secure SysTick Calibration Configuration */
/*! @{ */

#define SIM_SEC_M33_CFGSSTCALIB_CFGSSTCALIB_MASK (0x3FFFFFFU)
#define SIM_SEC_M33_CFGSSTCALIB_CFGSSTCALIB_SHIFT (0U)
/*! CFGSSTCALIB - Secure SysTick calibration configuration */
#define SIM_SEC_M33_CFGSSTCALIB_CFGSSTCALIB(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SEC_M33_CFGSSTCALIB_CFGSSTCALIB_SHIFT)) & SIM_SEC_M33_CFGSSTCALIB_CFGSSTCALIB_MASK)
/*! @} */

/*! @name FUSION_GPR0 - Fusion DSP General Purpose Register */
/*! @{ */

#define SIM_SEC_FUSION_GPR0_VECTOR_REMAP_MASK    (0x1FFFU)
#define SIM_SEC_FUSION_GPR0_VECTOR_REMAP_SHIFT   (0U)
/*! VECTOR_REMAP - Fusion Vector Remap Register
 *  0b0000000000000..For bit [11:0]: The reset vector address is 0
 *  0b0000000000001..For bit [12]: Reserved
 */
#define SIM_SEC_FUSION_GPR0_VECTOR_REMAP(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_FUSION_GPR0_VECTOR_REMAP_SHIFT)) & SIM_SEC_FUSION_GPR0_VECTOR_REMAP_MASK)

#define SIM_SEC_FUSION_GPR0_DOUBLEEXCEPTIONERROR_MASK (0x10000U)
#define SIM_SEC_FUSION_GPR0_DOUBLEEXCEPTIONERROR_SHIFT (16U)
/*! DOUBLEEXCEPTIONERROR - Double Exception Error */
#define SIM_SEC_FUSION_GPR0_DOUBLEEXCEPTIONERROR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_FUSION_GPR0_DOUBLEEXCEPTIONERROR_SHIFT)) & SIM_SEC_FUSION_GPR0_DOUBLEEXCEPTIONERROR_MASK)

#define SIM_SEC_FUSION_GPR0_PFATALERROR_MASK     (0x20000U)
#define SIM_SEC_FUSION_GPR0_PFATALERROR_SHIFT    (17U)
/*! PFATALERROR - Fatal Error */
#define SIM_SEC_FUSION_GPR0_PFATALERROR(x)       (((uint32_t)(((uint32_t)(x)) << SIM_SEC_FUSION_GPR0_PFATALERROR_SHIFT)) & SIM_SEC_FUSION_GPR0_PFATALERROR_MASK)

#define SIM_SEC_FUSION_GPR0_PFAULTINFOVALID_MASK (0x40000U)
#define SIM_SEC_FUSION_GPR0_PFAULTINFOVALID_SHIFT (18U)
/*! PFAULTINFOVALID - Fault Info Valid */
#define SIM_SEC_FUSION_GPR0_PFAULTINFOVALID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SEC_FUSION_GPR0_PFAULTINFOVALID_SHIFT)) & SIM_SEC_FUSION_GPR0_PFAULTINFOVALID_MASK)
/*! @} */

/*! @name FUSION_GPR1 - Fusion DSP General Purpose Register */
/*! @{ */

#define SIM_SEC_FUSION_GPR1_PFAULTINFO_MASK      (0xFFFFFFFFU)
#define SIM_SEC_FUSION_GPR1_PFAULTINFO_SHIFT     (0U)
/*! PFAULTINFO - Fault information Register */
#define SIM_SEC_FUSION_GPR1_PFAULTINFO(x)        (((uint32_t)(((uint32_t)(x)) << SIM_SEC_FUSION_GPR1_PFAULTINFO_SHIFT)) & SIM_SEC_FUSION_GPR1_PFAULTINFO_MASK)
/*! @} */

/*! @name FUSION_GPR2 - Fusion DSP General Purpose Register */
/*! @{ */

#define SIM_SEC_FUSION_GPR2_TIE_EXPSTATE_MASK    (0xFFFFFFFFU)
#define SIM_SEC_FUSION_GPR2_TIE_EXPSTATE_SHIFT   (0U)
/*! TIE_EXPSTATE - GPIO32 option TIE output state */
#define SIM_SEC_FUSION_GPR2_TIE_EXPSTATE(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_FUSION_GPR2_TIE_EXPSTATE_SHIFT)) & SIM_SEC_FUSION_GPR2_TIE_EXPSTATE_MASK)
/*! @} */

/*! @name RTD_INTERRUPT_MASK0 - Realtime Domain Interrupt Mask 0 */
/*! @{ */

#define SIM_SEC_RTD_INTERRUPT_MASK0_EWM_MASK     (0x1U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_EWM_SHIFT    (0U)
/*! EWM - EWM Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_EWM(x)       (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_EWM_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_EWM_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_DMA0_MASK    (0x1FEU)
#define SIM_SEC_RTD_INTERRUPT_MASK0_DMA0_SHIFT   (1U)
/*! DMA0 - DMA0 Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_DMA0(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_DMA0_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_DMA0_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_WUU0_MASK    (0x200U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_WUU0_SHIFT   (9U)
/*! WUU0 - WUU0 Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_WUU0(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_WUU0_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_WUU0_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_WDOG0_MASK   (0x400U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_WDOG0_SHIFT  (10U)
/*! WDOG0 - WDOG0 Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_WDOG0(x)     (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_WDOG0_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_WDOG0_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_WDOG1_MASK   (0x800U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_WDOG1_SHIFT  (11U)
/*! WDOG1 - WDOG1 Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_WDOG1(x)     (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_WDOG1_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_WDOG1_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_POWERSYS_MASK (0x1000U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_POWERSYS_SHIFT (12U)
/*! POWERSYS - POWERSYS Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_POWERSYS(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_POWERSYS_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_POWERSYS_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_CMC0_MASK    (0x2000U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_CMC0_SHIFT   (13U)
/*! CMC0 - CMC0 Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_CMC0(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_CMC0_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_CMC0_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_CGC0_MASK    (0x4000U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_CGC0_SHIFT   (14U)
/*! CGC0 - CGC0 Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_CGC0(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_CGC0_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_CGC0_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_FLEXIO0_MASK (0x8000U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_FLEXIO0_SHIFT (15U)
/*! FLEXIO0 - FlexIO0 Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_FLEXIO0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_FLEXIO0_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_FLEXIO0_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_FLEXSPI0_MASK (0x10000U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_FLEXSPI0_SHIFT (16U)
/*! FLEXSPI0 - FlexSPI0 Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_FLEXSPI0(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_FLEXSPI0_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_FLEXSPI0_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_FLEXSPI1_MASK (0x20000U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_FLEXSPI1_SHIFT (17U)
/*! FLEXSPI1 - FlexSPI1 Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_FLEXSPI1(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_FLEXSPI1_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_FLEXSPI1_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_CMP0_MASK    (0x40000U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_CMP0_SHIFT   (18U)
/*! CMP0 - CMP0 Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_CMP0(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_CMP0_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_CMP0_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_CMP1_MASK    (0x80000U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_CMP1_SHIFT   (19U)
/*! CMP1 - CMP1 Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_CMP1(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_CMP1_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_CMP1_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_LPTMR0_MASK  (0x100000U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_LPTMR0_SHIFT (20U)
/*! LPTMR0 - LPTMR0 Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_LPTMR0(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_LPTMR0_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_LPTMR0_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_LPTMR1_MASK  (0x200000U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_LPTMR1_SHIFT (21U)
/*! LPTMR1 - LPTMR1 Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_LPTMR1(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_LPTMR1_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_LPTMR1_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_TRDC_MASK    (0x400000U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_TRDC_SHIFT   (22U)
/*! TRDC - TRDC Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_TRDC(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_TRDC_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_TRDC_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_BBNSM_MASK   (0x800000U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_BBNSM_SHIFT  (23U)
/*! BBNSM - BBNSM Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_BBNSM(x)     (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_BBNSM_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_BBNSM_MASK)

#define SIM_SEC_RTD_INTERRUPT_MASK0_SE_MASK      (0x7000000U)
#define SIM_SEC_RTD_INTERRUPT_MASK0_SE_SHIFT     (24U)
/*! SE - Secure Enclave Interrupt Mask */
#define SIM_SEC_RTD_INTERRUPT_MASK0_SE(x)        (((uint32_t)(((uint32_t)(x)) << SIM_SEC_RTD_INTERRUPT_MASK0_SE_SHIFT)) & SIM_SEC_RTD_INTERRUPT_MASK0_SE_MASK)
/*! @} */

/*! @name APD_INTERRUPT_MASK0 - Application Domain Interrupt Mask 0 */
/*! @{ */

#define SIM_SEC_APD_INTERRUPT_MASK0_DMA1_MASK    (0xFFU)
#define SIM_SEC_APD_INTERRUPT_MASK0_DMA1_SHIFT   (0U)
/*! DMA1 - DMA1 Interrupt Mask */
#define SIM_SEC_APD_INTERRUPT_MASK0_DMA1(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_APD_INTERRUPT_MASK0_DMA1_SHIFT)) & SIM_SEC_APD_INTERRUPT_MASK0_DMA1_MASK)

#define SIM_SEC_APD_INTERRUPT_MASK0_FLEXIO1_MASK (0x100U)
#define SIM_SEC_APD_INTERRUPT_MASK0_FLEXIO1_SHIFT (8U)
/*! FLEXIO1 - FlexIO1 Interrupt Mask */
#define SIM_SEC_APD_INTERRUPT_MASK0_FLEXIO1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SEC_APD_INTERRUPT_MASK0_FLEXIO1_SHIFT)) & SIM_SEC_APD_INTERRUPT_MASK0_FLEXIO1_MASK)

#define SIM_SEC_APD_INTERRUPT_MASK0_USDHC0_MASK  (0x200U)
#define SIM_SEC_APD_INTERRUPT_MASK0_USDHC0_SHIFT (9U)
/*! USDHC0 - uSDHC0 Interrupt Mask */
#define SIM_SEC_APD_INTERRUPT_MASK0_USDHC0(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_APD_INTERRUPT_MASK0_USDHC0_SHIFT)) & SIM_SEC_APD_INTERRUPT_MASK0_USDHC0_MASK)

#define SIM_SEC_APD_INTERRUPT_MASK0_USDHC1_MASK  (0x400U)
#define SIM_SEC_APD_INTERRUPT_MASK0_USDHC1_SHIFT (10U)
/*! USDHC1 - uSDHC1 Interrupt Mask */
#define SIM_SEC_APD_INTERRUPT_MASK0_USDHC1(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_APD_INTERRUPT_MASK0_USDHC1_SHIFT)) & SIM_SEC_APD_INTERRUPT_MASK0_USDHC1_MASK)

#define SIM_SEC_APD_INTERRUPT_MASK0_USDHC2_MASK  (0x800U)
#define SIM_SEC_APD_INTERRUPT_MASK0_USDHC2_SHIFT (11U)
/*! USDHC2 - uSDHC2 Interrupt Mask */
#define SIM_SEC_APD_INTERRUPT_MASK0_USDHC2(x)    (((uint32_t)(((uint32_t)(x)) << SIM_SEC_APD_INTERRUPT_MASK0_USDHC2_SHIFT)) & SIM_SEC_APD_INTERRUPT_MASK0_USDHC2_MASK)

#define SIM_SEC_APD_INTERRUPT_MASK0_FLEXSPI2_MASK (0x1000U)
#define SIM_SEC_APD_INTERRUPT_MASK0_FLEXSPI2_SHIFT (12U)
/*! FLEXSPI2 - FlexSPI2 Interrupt Mask */
#define SIM_SEC_APD_INTERRUPT_MASK0_FLEXSPI2(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_APD_INTERRUPT_MASK0_FLEXSPI2_SHIFT)) & SIM_SEC_APD_INTERRUPT_MASK0_FLEXSPI2_MASK)

#define SIM_SEC_APD_INTERRUPT_MASK0_XRDC_MASK    (0x2000U)
#define SIM_SEC_APD_INTERRUPT_MASK0_XRDC_SHIFT   (13U)
/*! XRDC - XRDC Interrupt Mask */
#define SIM_SEC_APD_INTERRUPT_MASK0_XRDC(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_APD_INTERRUPT_MASK0_XRDC_SHIFT)) & SIM_SEC_APD_INTERRUPT_MASK0_XRDC_MASK)

#define SIM_SEC_APD_INTERRUPT_MASK0_USB_PHY0_MASK (0x4000U)
#define SIM_SEC_APD_INTERRUPT_MASK0_USB_PHY0_SHIFT (14U)
/*! USB_PHY0 - USB PHY0 Interrupt Mask */
#define SIM_SEC_APD_INTERRUPT_MASK0_USB_PHY0(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_APD_INTERRUPT_MASK0_USB_PHY0_SHIFT)) & SIM_SEC_APD_INTERRUPT_MASK0_USB_PHY0_MASK)

#define SIM_SEC_APD_INTERRUPT_MASK0_USB_PHY1_MASK (0x8000U)
#define SIM_SEC_APD_INTERRUPT_MASK0_USB_PHY1_SHIFT (15U)
/*! USB_PHY1 - USB PHY1 Interrupt Mask */
#define SIM_SEC_APD_INTERRUPT_MASK0_USB_PHY1(x)  (((uint32_t)(((uint32_t)(x)) << SIM_SEC_APD_INTERRUPT_MASK0_USB_PHY1_SHIFT)) & SIM_SEC_APD_INTERRUPT_MASK0_USB_PHY1_MASK)

#define SIM_SEC_APD_INTERRUPT_MASK0_USB0_MASK    (0x10000U)
#define SIM_SEC_APD_INTERRUPT_MASK0_USB0_SHIFT   (16U)
/*! USB0 - USB0 Interrupt Mask */
#define SIM_SEC_APD_INTERRUPT_MASK0_USB0(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_APD_INTERRUPT_MASK0_USB0_SHIFT)) & SIM_SEC_APD_INTERRUPT_MASK0_USB0_MASK)

#define SIM_SEC_APD_INTERRUPT_MASK0_USB1_MASK    (0x20000U)
#define SIM_SEC_APD_INTERRUPT_MASK0_USB1_SHIFT   (17U)
/*! USB1 - USB1 Interrupt Mask */
#define SIM_SEC_APD_INTERRUPT_MASK0_USB1(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_APD_INTERRUPT_MASK0_USB1_SHIFT)) & SIM_SEC_APD_INTERRUPT_MASK0_USB1_MASK)
/*! @} */

/*! @name AVD_INTERRUPT_MASK0 - Audio-Video Domain Interrupt Mask 0 */
/*! @{ */

#define SIM_SEC_AVD_INTERRUPT_MASK0_MDDR_MASK    (0x1U)
#define SIM_SEC_AVD_INTERRUPT_MASK0_MDDR_SHIFT   (0U)
/*! MDDR - MDDR Interrupt Mask */
#define SIM_SEC_AVD_INTERRUPT_MASK0_MDDR(x)      (((uint32_t)(((uint32_t)(x)) << SIM_SEC_AVD_INTERRUPT_MASK0_MDDR_SHIFT)) & SIM_SEC_AVD_INTERRUPT_MASK0_MDDR_MASK)
/*! @} */

/*! @name WRITE_ASSIST_CTRL - RTD Memories Write-Assist Control */
/*! @{ */

#define SIM_SEC_WRITE_ASSIST_CTRL_WR_ASSIST_EN_B_MASK (0x3U)
#define SIM_SEC_WRITE_ASSIST_CTRL_WR_ASSIST_EN_B_SHIFT (0U)
/*! WR_ASSIST_EN_B - Write-Assist Enable */
#define SIM_SEC_WRITE_ASSIST_CTRL_WR_ASSIST_EN_B(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_WRITE_ASSIST_CTRL_WR_ASSIST_EN_B_SHIFT)) & SIM_SEC_WRITE_ASSIST_CTRL_WR_ASSIST_EN_B_MASK)

#define SIM_SEC_WRITE_ASSIST_CTRL_WRAST_MUX_SEL_BELOW_B_MASK (0x4U)
#define SIM_SEC_WRITE_ASSIST_CTRL_WRAST_MUX_SEL_BELOW_B_SHIFT (2U)
/*! WRAST_MUX_SEL_BELOW_B - Write-Assist Mux Select - Memories with Row x Block below threshold */
#define SIM_SEC_WRITE_ASSIST_CTRL_WRAST_MUX_SEL_BELOW_B(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_WRITE_ASSIST_CTRL_WRAST_MUX_SEL_BELOW_B_SHIFT)) & SIM_SEC_WRITE_ASSIST_CTRL_WRAST_MUX_SEL_BELOW_B_MASK)

#define SIM_SEC_WRITE_ASSIST_CTRL_WRAST_MUX_SEL_ABOVE_B_MASK (0x8U)
#define SIM_SEC_WRITE_ASSIST_CTRL_WRAST_MUX_SEL_ABOVE_B_SHIFT (3U)
/*! WRAST_MUX_SEL_ABOVE_B - Write-Assist Mux Select - Memories with Row x Block below threshold */
#define SIM_SEC_WRITE_ASSIST_CTRL_WRAST_MUX_SEL_ABOVE_B(x) (((uint32_t)(((uint32_t)(x)) << SIM_SEC_WRITE_ASSIST_CTRL_WRAST_MUX_SEL_ABOVE_B_SHIFT)) & SIM_SEC_WRITE_ASSIST_CTRL_WRAST_MUX_SEL_ABOVE_B_MASK)
/*! @} */

/*! @name SYSCTRL1 - Realtime Domains System Control Register 1 */
/*! @{ */

#define SIM_SEC_SYSCTRL1_AA64NAA32_MASK          (0x3U)
#define SIM_SEC_SYSCTRL1_AA64NAA32_SHIFT         (0U)
/*! AA64NAA32 - Architecture Mode Select Bits */
#define SIM_SEC_SYSCTRL1_AA64NAA32(x)            (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL1_AA64NAA32_SHIFT)) & SIM_SEC_SYSCTRL1_AA64NAA32_MASK)
/*! @} */

/*! @name SYSCTRL2 - Realtime Domains System Control Register 2 */
/*! @{ */

#define SIM_SEC_SYSCTRL2_TZM_CONTROL_MASK        (0x1U)
#define SIM_SEC_SYSCTRL2_TZM_CONTROL_SHIFT       (0U)
/*! TZM_CONTROL - CM33 Trust Zone Mode Control Bit */
#define SIM_SEC_SYSCTRL2_TZM_CONTROL(x)          (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL2_TZM_CONTROL_SHIFT)) & SIM_SEC_SYSCTRL2_TZM_CONTROL_MASK)
/*! @} */

/*! @name SYSCTRL3 - Realtime Domains System Control Register 3 */
/*! @{ */

#define SIM_SEC_SYSCTRL3_CP15SDISABLE2_MASK      (0x3U)
#define SIM_SEC_SYSCTRL3_CP15SDISABLE2_SHIFT     (0U)
/*! CP15SDISABLE2 - Disable write access to some Secure CP15 registers */
#define SIM_SEC_SYSCTRL3_CP15SDISABLE2(x)        (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL3_CP15SDISABLE2_SHIFT)) & SIM_SEC_SYSCTRL3_CP15SDISABLE2_MASK)
/*! @} */

/*! @name SYSCTRL4 - Realtime Domains System Control Register 4 */
/*! @{ */

#define SIM_SEC_SYSCTRL4_LMDA_RESET_EN_MASK      (0x1U)
#define SIM_SEC_SYSCTRL4_LMDA_RESET_EN_SHIFT     (0U)
/*! LMDA_RESET_EN - Enables LMDA reset source */
#define SIM_SEC_SYSCTRL4_LMDA_RESET_EN(x)        (((uint32_t)(((uint32_t)(x)) << SIM_SEC_SYSCTRL4_LMDA_RESET_EN_SHIFT)) & SIM_SEC_SYSCTRL4_LMDA_RESET_EN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SIM_SEC_Register_Masks */


/* SIM_SEC - Peripheral instance base addresses */
/** Peripheral SIM_SEC base address */
#define SIM_SEC_BASE                             (0x2802B000u)
/** Peripheral SIM_SEC base pointer */
#define SIM_SEC                                  ((SIM_SEC_Type *)SIM_SEC_BASE)
/** Array initializer of SIM_SEC peripheral base addresses */
#define SIM_SEC_BASE_ADDRS                       { SIM_SEC_BASE }
/** Array initializer of SIM_SEC peripheral base pointers */
#define SIM_SEC_BASE_PTRS                        { SIM_SEC }

/*!
 * @}
 */ /* end of group SIM_SEC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SPDIF Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
 * @{
 */

/** SPDIF - Register Layout Typedef */
typedef struct {
  __IO uint32_t SCR;                               /**< SPDIF Configuration Register, offset: 0x0 */
  __IO uint32_t SRCD;                              /**< CDText Control Register, offset: 0x4 */
  __IO uint32_t SRPC;                              /**< PhaseConfig Register, offset: 0x8 */
  __IO uint32_t SIE;                               /**< InterruptEn Register, offset: 0xC */
  __IO uint32_t SIS;                               /**< InterruptStat Register, offset: 0x10 */
  __I  uint32_t SRL;                               /**< SPDIFRxLeft Register, offset: 0x14 */
  __I  uint32_t SRR;                               /**< SPDIFRxRight Register, offset: 0x18 */
  __I  uint32_t SRCSH;                             /**< SPDIFRxCChannel_h Register, offset: 0x1C */
  __I  uint32_t SRCSL;                             /**< SPDIFRxCChannel_l Register, offset: 0x20 */
  __I  uint32_t SRU;                               /**< UchannelRx Register, offset: 0x24 */
  __I  uint32_t SRQ;                               /**< QchannelRx Register, offset: 0x28 */
  __O  uint32_t STL;                               /**< SPDIFTxLeft Register, offset: 0x2C */
  __O  uint32_t STR;                               /**< SPDIFTxRight Register, offset: 0x30 */
  __IO uint32_t STCSCH;                            /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
  __IO uint32_t STCSCL;                            /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
       uint8_t RESERVED_0[8];
  __I  uint32_t SRFM;                              /**< FreqMeas Register, offset: 0x44 */
       uint8_t RESERVED_1[8];
  __IO uint32_t STC;                               /**< SPDIFTxClk Register, offset: 0x50 */
       uint8_t RESERVED_2[12];
  __I  uint32_t SPDIFRXCCHANNEL_ADDR_31_0;         /**< SPDIF receive C channel register, bits 31-0, offset: 0x60 */
  __I  uint32_t SPDIFRXCCHANNEL_ADDR_63_32;        /**< SPDIF receive C channel register, bits 63-32, offset: 0x64 */
  __I  uint32_t SPDIFRXCCHANNEL_ADDR_95_64;        /**< SPDIF receive C channel register, bits 95-64, offset: 0x68 */
  __I  uint32_t SPDIFRXCCHANNEL_ADDR_127_96;       /**< SPDIF receive C channel register, bits 127-96, offset: 0x6C */
  __I  uint32_t SPDIFRXCCHANNEL_ADDR_159_128;      /**< SPDIF receive C channel register, bits 159-128, offset: 0x70 */
  __I  uint32_t SPDIFRXCCHANNEL_ADDR_191_160;      /**< SPDIF receive C channel register, bits 191-160, offset: 0x74 */
} SPDIF_Type;

/* ----------------------------------------------------------------------------
   -- SPDIF Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SPDIF_Register_Masks SPDIF Register Masks
 * @{
 */

/*! @name SCR - SPDIF Configuration Register */
/*! @{ */

#define SPDIF_SCR_USRC_SEL_MASK                  (0x3U)
#define SPDIF_SCR_USRC_SEL_SHIFT                 (0U)
/*! USrc_Sel - USrc_Sel
 *  0b00..No embedded U channel
 *  0b01..U channel from SPDIF receive block (CD mode)
 *  0b10..Reserved
 *  0b11..U channel from on chip transmitter
 */
#define SPDIF_SCR_USRC_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)

#define SPDIF_SCR_TXSEL_MASK                     (0x1CU)
#define SPDIF_SCR_TXSEL_SHIFT                    (2U)
/*! TxSel - TxSel
 *  0b000..Off and output 0
 *  0b001..Feed-through SPDIF_IN1
 *  0b010..Feed-through SPDIF_IN2
 *  0b011..Feed-through SPDIF_IN3
 *  0b100..Feed-through SPDIF_IN4
 *  0b101..Tx Normal operation - From SPDIF Tx Block
 *  0b110, 0b111..Reserved
 */
#define SPDIF_SCR_TXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)

#define SPDIF_SCR_VALCTRL_MASK                   (0x20U)
#define SPDIF_SCR_VALCTRL_SHIFT                  (5U)
/*! ValCtrl - ValCtrl
 *  0b0..Outgoing Validity always set
 *  0b1..Outgoing Validity always clear
 */
#define SPDIF_SCR_VALCTRL(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)

#define SPDIF_SCR_INPUTSRCSEL_MASK               (0xC0U)
#define SPDIF_SCR_INPUTSRCSEL_SHIFT              (6U)
/*! InputSrcSel - InputSrcSel
 *  0b00..SPDIF_IN1
 *  0b01..SPDIF_IN2
 *  0b10..SPDIF_IN3
 *  0b11..SPDIF_IN4
 */
#define SPDIF_SCR_INPUTSRCSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_INPUTSRCSEL_SHIFT)) & SPDIF_SCR_INPUTSRCSEL_MASK)

#define SPDIF_SCR_DMA_TX_EN_MASK                 (0x100U)
#define SPDIF_SCR_DMA_TX_EN_SHIFT                (8U)
/*! DMA_TX_En - DMA_TX_En */
#define SPDIF_SCR_DMA_TX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)

#define SPDIF_SCR_DMA_RX_EN_MASK                 (0x200U)
#define SPDIF_SCR_DMA_RX_EN_SHIFT                (9U)
/*! DMA_Rx_En - DMA_Rx_En */
#define SPDIF_SCR_DMA_RX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)

#define SPDIF_SCR_TXFIFO_CTRL_MASK               (0xC00U)
#define SPDIF_SCR_TXFIFO_CTRL_SHIFT              (10U)
/*! TxFIFO_Ctrl - TxFIFO_Ctrl
 *  0b00..Send out digital zero on SPDIF Tx
 *  0b01..Tx Normal operation
 *  0b10..Reset to 1 sample remaining
 *  0b11..Reserved
 */
#define SPDIF_SCR_TXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)

#define SPDIF_SCR_SOFT_RESET_MASK                (0x1000U)
#define SPDIF_SCR_SOFT_RESET_SHIFT               (12U)
/*! soft_reset - soft_reset */
#define SPDIF_SCR_SOFT_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)

#define SPDIF_SCR_LOW_POWER_MASK                 (0x2000U)
#define SPDIF_SCR_LOW_POWER_SHIFT                (13U)
/*! LOW_POWER - LOW_POWER */
#define SPDIF_SCR_LOW_POWER(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)

#define SPDIF_SCR_RAW_CAPTURE_MODE_MASK          (0x4000U)
#define SPDIF_SCR_RAW_CAPTURE_MODE_SHIFT         (14U)
/*! RAW_CAPTURE_MODE - RAW_CAPTURE_MODE */
#define SPDIF_SCR_RAW_CAPTURE_MODE(x)            (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RAW_CAPTURE_MODE_SHIFT)) & SPDIF_SCR_RAW_CAPTURE_MODE_MASK)

#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK           (0x18000U)
#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT          (15U)
/*! TxFIFOEmpty_Sel - TxFIFOEmpty_Sel
 *  0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
 *  0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
 *  0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
 *  0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
 */
#define SPDIF_SCR_TXFIFOEMPTY_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)

#define SPDIF_SCR_TXAUTOSYNC_MASK                (0x20000U)
#define SPDIF_SCR_TXAUTOSYNC_SHIFT               (17U)
/*! TxAutoSync - TxAutoSync
 *  0b0..Tx FIFO auto sync off
 *  0b1..Tx FIFO auto sync on
 */
#define SPDIF_SCR_TXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)

#define SPDIF_SCR_RXAUTOSYNC_MASK                (0x40000U)
#define SPDIF_SCR_RXAUTOSYNC_SHIFT               (18U)
/*! RxAutoSync - RxAutoSync
 *  0b0..Rx FIFO auto sync off
 *  0b1..RxFIFO auto sync on
 */
#define SPDIF_SCR_RXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)

#define SPDIF_SCR_RXFIFOFULL_SEL_MASK            (0x180000U)
#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT           (19U)
/*! RxFIFOFull_Sel - RxFIFOFull_Sel
 *  0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
 *  0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
 *  0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
 *  0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
 */
#define SPDIF_SCR_RXFIFOFULL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)

#define SPDIF_SCR_RXFIFO_RST_MASK                (0x200000U)
#define SPDIF_SCR_RXFIFO_RST_SHIFT               (21U)
/*! RxFIFO_Rst - RxFIFO_Rst
 *  0b0..Normal operation
 *  0b1..Reset register to 1 sample remaining
 */
#define SPDIF_SCR_RXFIFO_RST(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)

#define SPDIF_SCR_RXFIFO_OFF_ON_MASK             (0x400000U)
#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT            (22U)
/*! RxFIFO_Off_On - RxFIFO_Off_On
 *  0b0..SPDIF Rx FIFO is on
 *  0b1..SPDIF Rx FIFO is off. Does not accept data from interface
 */
#define SPDIF_SCR_RXFIFO_OFF_ON(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)

#define SPDIF_SCR_RXFIFO_CTRL_MASK               (0x800000U)
#define SPDIF_SCR_RXFIFO_CTRL_SHIFT              (23U)
/*! RxFIFO_Ctrl - RxFIFO_Ctrl
 *  0b0..Normal operation
 *  0b1..Always read zero from Rx data register
 */
#define SPDIF_SCR_RXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)

#define SPDIF_SCR_RXCCHANNEL_192B_EN_MASK        (0x2000000U)
#define SPDIF_SCR_RXCCHANNEL_192B_EN_SHIFT       (25U)
/*! RXCChannel_192b_en - RXCChannel_192b_en
 *  0b0..SPDIF receives only 48 bits of 192 C bits from input audio stream
 *  0b1..SPDIF receives 192 bits of C in audio stream
 */
#define SPDIF_SCR_RXCCHANNEL_192B_EN(x)          (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXCCHANNEL_192B_EN_SHIFT)) & SPDIF_SCR_RXCCHANNEL_192B_EN_MASK)
/*! @} */

/*! @name SRCD - CDText Control Register */
/*! @{ */

#define SPDIF_SRCD_USYNCMODE_MASK                (0x2U)
#define SPDIF_SRCD_USYNCMODE_SHIFT               (1U)
/*! USyncMode - USyncMode
 *  0b0..Non-CD data
 *  0b1..CD user channel subcode
 */
#define SPDIF_SRCD_USYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
/*! @} */

/*! @name SRPC - PhaseConfig Register */
/*! @{ */

#define SPDIF_SRPC_GAINSEL_MASK                  (0x38U)
#define SPDIF_SRPC_GAINSEL_SHIFT                 (3U)
/*! GainSel - GainSel
 *  0b000..24*(2**10)
 *  0b001..16*(2**10)
 *  0b010..12*(2**10)
 *  0b011..8*(2**10)
 *  0b100..6*(2**10)
 *  0b101..4*(2**10)
 *  0b110..3*(2**10)
 */
#define SPDIF_SRPC_GAINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)

#define SPDIF_SRPC_LOCK_MASK                     (0x40U)
#define SPDIF_SRPC_LOCK_SHIFT                    (6U)
/*! LOCK - LOCK */
#define SPDIF_SRPC_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)

#define SPDIF_SRPC_CLKSRC_SEL_MASK               (0x780U)
#define SPDIF_SRPC_CLKSRC_SEL_SHIFT              (7U)
/*! ClkSrc_Sel - ClkSrc_Sel
 *  0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)
 *  0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)
 *  0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK
 *  0b0101..REF_CLK_32K (XTALOSC)
 *  0b0110..tx_clk (SPDIF0_CLK_ROOT)
 *  0b1000..SPDIF_EXT_CLK
 */
#define SPDIF_SRPC_CLKSRC_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
/*! @} */

/*! @name SIE - InterruptEn Register */
/*! @{ */

#define SPDIF_SIE_RXFIFOFUL_MASK                 (0x1U)
#define SPDIF_SIE_RXFIFOFUL_SHIFT                (0U)
/*! RxFIFOFul - RxFIFOFul */
#define SPDIF_SIE_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)

#define SPDIF_SIE_TXEM_MASK                      (0x2U)
#define SPDIF_SIE_TXEM_SHIFT                     (1U)
/*! TxEm - TxEm */
#define SPDIF_SIE_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)

#define SPDIF_SIE_LOCKLOSS_MASK                  (0x4U)
#define SPDIF_SIE_LOCKLOSS_SHIFT                 (2U)
/*! LockLoss - LockLoss */
#define SPDIF_SIE_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)

#define SPDIF_SIE_RXFIFORESYN_MASK               (0x8U)
#define SPDIF_SIE_RXFIFORESYN_SHIFT              (3U)
/*! RxFIFOResyn - RxFIFOResyn */
#define SPDIF_SIE_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)

#define SPDIF_SIE_RXFIFOUNOV_MASK                (0x10U)
#define SPDIF_SIE_RXFIFOUNOV_SHIFT               (4U)
/*! RxFIFOUnOv - RxFIFOUnOv */
#define SPDIF_SIE_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)

#define SPDIF_SIE_UQERR_MASK                     (0x20U)
#define SPDIF_SIE_UQERR_SHIFT                    (5U)
/*! UQErr - UQErr */
#define SPDIF_SIE_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)

#define SPDIF_SIE_UQSYNC_MASK                    (0x40U)
#define SPDIF_SIE_UQSYNC_SHIFT                   (6U)
/*! UQSync - UQSync */
#define SPDIF_SIE_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)

#define SPDIF_SIE_QRXOV_MASK                     (0x80U)
#define SPDIF_SIE_QRXOV_SHIFT                    (7U)
/*! QRxOv - QRxOv */
#define SPDIF_SIE_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)

#define SPDIF_SIE_QRXFUL_MASK                    (0x100U)
#define SPDIF_SIE_QRXFUL_SHIFT                   (8U)
/*! QRxFul - QRxFul */
#define SPDIF_SIE_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)

#define SPDIF_SIE_URXOV_MASK                     (0x200U)
#define SPDIF_SIE_URXOV_SHIFT                    (9U)
/*! URxOv - URxOv */
#define SPDIF_SIE_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)

#define SPDIF_SIE_URXFUL_MASK                    (0x400U)
#define SPDIF_SIE_URXFUL_SHIFT                   (10U)
/*! URxFul - URxFul */
#define SPDIF_SIE_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)

#define SPDIF_SIE_BITERR_MASK                    (0x4000U)
#define SPDIF_SIE_BITERR_SHIFT                   (14U)
/*! BitErr - BitErr */
#define SPDIF_SIE_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)

#define SPDIF_SIE_SYMERR_MASK                    (0x8000U)
#define SPDIF_SIE_SYMERR_SHIFT                   (15U)
/*! SymErr - SymErr */
#define SPDIF_SIE_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)

#define SPDIF_SIE_VALNOGOOD_MASK                 (0x10000U)
#define SPDIF_SIE_VALNOGOOD_SHIFT                (16U)
/*! ValNoGood - ValNoGood */
#define SPDIF_SIE_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)

#define SPDIF_SIE_CNEW_MASK                      (0x20000U)
#define SPDIF_SIE_CNEW_SHIFT                     (17U)
/*! CNew - CNew */
#define SPDIF_SIE_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)

#define SPDIF_SIE_TXRESYN_MASK                   (0x40000U)
#define SPDIF_SIE_TXRESYN_SHIFT                  (18U)
/*! TxResyn - TxResyn */
#define SPDIF_SIE_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)

#define SPDIF_SIE_TXUNOV_MASK                    (0x80000U)
#define SPDIF_SIE_TXUNOV_SHIFT                   (19U)
/*! TxUnOv - TxUnOv */
#define SPDIF_SIE_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)

#define SPDIF_SIE_LOCK_MASK                      (0x100000U)
#define SPDIF_SIE_LOCK_SHIFT                     (20U)
/*! Lock - Lock */
#define SPDIF_SIE_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
/*! @} */

/*! @name SIS - InterruptStat Register */
/*! @{ */

#define SPDIF_SIS_RXFIFOFUL_MASK                 (0x1U)
#define SPDIF_SIS_RXFIFOFUL_SHIFT                (0U)
/*! RxFIFOFul - RxFIFOFul */
#define SPDIF_SIS_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)

#define SPDIF_SIS_TXEM_MASK                      (0x2U)
#define SPDIF_SIS_TXEM_SHIFT                     (1U)
/*! TxEm - TxEm */
#define SPDIF_SIS_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)

#define SPDIF_SIS_LOCKLOSS_MASK                  (0x4U)
#define SPDIF_SIS_LOCKLOSS_SHIFT                 (2U)
/*! LockLoss - LockLoss */
#define SPDIF_SIS_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)

#define SPDIF_SIS_RXFIFORESYN_MASK               (0x8U)
#define SPDIF_SIS_RXFIFORESYN_SHIFT              (3U)
/*! RxFIFOResyn - RxFIFOResyn */
#define SPDIF_SIS_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)

#define SPDIF_SIS_RXFIFOUNOV_MASK                (0x10U)
#define SPDIF_SIS_RXFIFOUNOV_SHIFT               (4U)
/*! RxFIFOUnOv - RxFIFOUnOv */
#define SPDIF_SIS_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)

#define SPDIF_SIS_UQERR_MASK                     (0x20U)
#define SPDIF_SIS_UQERR_SHIFT                    (5U)
/*! UQErr - UQErr */
#define SPDIF_SIS_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)

#define SPDIF_SIS_UQSYNC_MASK                    (0x40U)
#define SPDIF_SIS_UQSYNC_SHIFT                   (6U)
/*! UQSync - UQSync */
#define SPDIF_SIS_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)

#define SPDIF_SIS_QRXOV_MASK                     (0x80U)
#define SPDIF_SIS_QRXOV_SHIFT                    (7U)
/*! QRxOv - QRxOv */
#define SPDIF_SIS_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)

#define SPDIF_SIS_QRXFUL_MASK                    (0x100U)
#define SPDIF_SIS_QRXFUL_SHIFT                   (8U)
/*! QRxFul - QRxFul */
#define SPDIF_SIS_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)

#define SPDIF_SIS_URXOV_MASK                     (0x200U)
#define SPDIF_SIS_URXOV_SHIFT                    (9U)
/*! URxOv - URxOv */
#define SPDIF_SIS_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)

#define SPDIF_SIS_URXFUL_MASK                    (0x400U)
#define SPDIF_SIS_URXFUL_SHIFT                   (10U)
/*! URxFul - URxFul */
#define SPDIF_SIS_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)

#define SPDIF_SIS_BITERR_MASK                    (0x4000U)
#define SPDIF_SIS_BITERR_SHIFT                   (14U)
/*! BitErr - BitErr */
#define SPDIF_SIS_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)

#define SPDIF_SIS_SYMERR_MASK                    (0x8000U)
#define SPDIF_SIS_SYMERR_SHIFT                   (15U)
/*! SymErr - SymErr */
#define SPDIF_SIS_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)

#define SPDIF_SIS_VALNOGOOD_MASK                 (0x10000U)
#define SPDIF_SIS_VALNOGOOD_SHIFT                (16U)
/*! ValNoGood - ValNoGood */
#define SPDIF_SIS_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)

#define SPDIF_SIS_CNEW_MASK                      (0x20000U)
#define SPDIF_SIS_CNEW_SHIFT                     (17U)
/*! CNew - CNew */
#define SPDIF_SIS_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)

#define SPDIF_SIS_TXRESYN_MASK                   (0x40000U)
#define SPDIF_SIS_TXRESYN_SHIFT                  (18U)
/*! TxResyn - TxResyn */
#define SPDIF_SIS_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)

#define SPDIF_SIS_TXUNOV_MASK                    (0x80000U)
#define SPDIF_SIS_TXUNOV_SHIFT                   (19U)
/*! TxUnOv - TxUnOv */
#define SPDIF_SIS_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)

#define SPDIF_SIS_LOCK_MASK                      (0x100000U)
#define SPDIF_SIS_LOCK_SHIFT                     (20U)
/*! Lock - Lock */
#define SPDIF_SIS_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
/*! @} */

/*! @name SRL - SPDIFRxLeft Register */
/*! @{ */

#define SPDIF_SRL_RXDATALEFT_MASK                (0xFFFFFFU)
#define SPDIF_SRL_RXDATALEFT_SHIFT               (0U)
/*! RxDataLeft - RxDataLeft */
#define SPDIF_SRL_RXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
/*! @} */

/*! @name SRR - SPDIFRxRight Register */
/*! @{ */

#define SPDIF_SRR_RXDATARIGHT_MASK               (0xFFFFFFU)
#define SPDIF_SRR_RXDATARIGHT_SHIFT              (0U)
/*! RxDataRight - RxDataRight */
#define SPDIF_SRR_RXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
/*! @} */

/*! @name SRCSH - SPDIFRxCChannel_h Register */
/*! @{ */

#define SPDIF_SRCSH_RXCCHANNEL_H_MASK            (0xFFFFFFU)
#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT           (0U)
/*! RxCChannel_h - RxCChannel_h */
#define SPDIF_SRCSH_RXCCHANNEL_H(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
/*! @} */

/*! @name SRCSL - SPDIFRxCChannel_l Register */
/*! @{ */

#define SPDIF_SRCSL_RXCCHANNEL_L_MASK            (0xFFFFFFU)
#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT           (0U)
/*! RxCChannel_l - RxCChannel_l */
#define SPDIF_SRCSL_RXCCHANNEL_L(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
/*! @} */

/*! @name SRU - UchannelRx Register */
/*! @{ */

#define SPDIF_SRU_RXUCHANNEL_MASK                (0xFFFFFFU)
#define SPDIF_SRU_RXUCHANNEL_SHIFT               (0U)
/*! RxUChannel - RxUChannel */
#define SPDIF_SRU_RXUCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
/*! @} */

/*! @name SRQ - QchannelRx Register */
/*! @{ */

#define SPDIF_SRQ_RXQCHANNEL_MASK                (0xFFFFFFU)
#define SPDIF_SRQ_RXQCHANNEL_SHIFT               (0U)
/*! RxQChannel - RxQChannel */
#define SPDIF_SRQ_RXQCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
/*! @} */

/*! @name STL - SPDIFTxLeft Register */
/*! @{ */

#define SPDIF_STL_TXDATALEFT_MASK                (0xFFFFFFU)
#define SPDIF_STL_TXDATALEFT_SHIFT               (0U)
/*! TxDataLeft - TxDataLeft */
#define SPDIF_STL_TXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
/*! @} */

/*! @name STR - SPDIFTxRight Register */
/*! @{ */

#define SPDIF_STR_TXDATARIGHT_MASK               (0xFFFFFFU)
#define SPDIF_STR_TXDATARIGHT_SHIFT              (0U)
/*! TxDataRight - TxDataRight */
#define SPDIF_STR_TXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
/*! @} */

/*! @name STCSCH - SPDIFTxCChannelCons_h Register */
/*! @{ */

#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK       (0xFFFFFFU)
#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT      (0U)
/*! TxCChannelCons_h - TxCChannelCons_h */
#define SPDIF_STCSCH_TXCCHANNELCONS_H(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
/*! @} */

/*! @name STCSCL - SPDIFTxCChannelCons_l Register */
/*! @{ */

#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK       (0xFFFFFFU)
#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT      (0U)
/*! TxCChannelCons_l - TxCChannelCons_l */
#define SPDIF_STCSCL_TXCCHANNELCONS_L(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
/*! @} */

/*! @name SRFM - FreqMeas Register */
/*! @{ */

#define SPDIF_SRFM_FREQMEAS_MASK                 (0xFFFFFFU)
#define SPDIF_SRFM_FREQMEAS_SHIFT                (0U)
/*! FreqMeas - FreqMeas */
#define SPDIF_SRFM_FREQMEAS(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
/*! @} */

/*! @name STC - SPDIFTxClk Register */
/*! @{ */

#define SPDIF_STC_TXCLK_DF_MASK                  (0x7FU)
#define SPDIF_STC_TXCLK_DF_SHIFT                 (0U)
/*! TxClk_DF - TxClk_DF
 *  0b0000000..divider factor is 1
 *  0b0000001..divider factor is 2
 *  0b1111111..divider factor is 128
 */
#define SPDIF_STC_TXCLK_DF(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)

#define SPDIF_STC_TX_ALL_CLK_EN_MASK             (0x80U)
#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT            (7U)
/*! tx_all_clk_en - tx_all_clk_en
 *  0b0..disable transfer clock.
 *  0b1..enable transfer clock.
 */
#define SPDIF_STC_TX_ALL_CLK_EN(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)

#define SPDIF_STC_TXCLK_SOURCE_MASK              (0x700U)
#define SPDIF_STC_TXCLK_SOURCE_SHIFT             (8U)
/*! TxClk_Source - TxClk_Source
 *  0b000..REF_CLK_32K input (XTALOSC 32 kHz clock)
 *  0b001..tx_clk input (from SPDIF0_CLK_ROOT)
 *  0b011..SPDIF_EXT_CLK, from pads
 *  0b101..ipg_clk input (frequency divided)
 */
#define SPDIF_STC_TXCLK_SOURCE(x)                (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)

#define SPDIF_STC_SYSCLK_DF_MASK                 (0xFF800U)
#define SPDIF_STC_SYSCLK_DF_SHIFT                (11U)
/*! SYSCLK_DF - SYSCLK_DF
 *  0b000000000..no clock signal
 *  0b000000001..divider factor is 2
 *  0b111111111..divider factor is 512
 */
#define SPDIF_STC_SYSCLK_DF(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
/*! @} */

/*! @name SPDIFRXCCHANNEL_ADDR_31_0 - SPDIF receive C channel register, bits 31-0 */
/*! @{ */

#define SPDIF_SPDIFRXCCHANNEL_ADDR_31_0_RXCCHANNEL_ADDR_31_0_MASK (0xFFFFFFFFU)
#define SPDIF_SPDIFRXCCHANNEL_ADDR_31_0_RXCCHANNEL_ADDR_31_0_SHIFT (0U)
/*! RxCChannel_Addr_31_0 - RxCChannel_Addr_31_0 */
#define SPDIF_SPDIFRXCCHANNEL_ADDR_31_0_RXCCHANNEL_ADDR_31_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFRXCCHANNEL_ADDR_31_0_RXCCHANNEL_ADDR_31_0_SHIFT)) & SPDIF_SPDIFRXCCHANNEL_ADDR_31_0_RXCCHANNEL_ADDR_31_0_MASK)
/*! @} */

/*! @name SPDIFRXCCHANNEL_ADDR_63_32 - SPDIF receive C channel register, bits 63-32 */
/*! @{ */

#define SPDIF_SPDIFRXCCHANNEL_ADDR_63_32_RXCCHANNEL_ADDR_63_32_MASK (0xFFFFFFFFU)
#define SPDIF_SPDIFRXCCHANNEL_ADDR_63_32_RXCCHANNEL_ADDR_63_32_SHIFT (0U)
/*! RxCChannel_Addr_63_32 - RxCChannel_Addr_63_32 */
#define SPDIF_SPDIFRXCCHANNEL_ADDR_63_32_RXCCHANNEL_ADDR_63_32(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFRXCCHANNEL_ADDR_63_32_RXCCHANNEL_ADDR_63_32_SHIFT)) & SPDIF_SPDIFRXCCHANNEL_ADDR_63_32_RXCCHANNEL_ADDR_63_32_MASK)
/*! @} */

/*! @name SPDIFRXCCHANNEL_ADDR_95_64 - SPDIF receive C channel register, bits 95-64 */
/*! @{ */

#define SPDIF_SPDIFRXCCHANNEL_ADDR_95_64_RXCCHANNEL_ADDR_95_64_MASK (0xFFFFFFFFU)
#define SPDIF_SPDIFRXCCHANNEL_ADDR_95_64_RXCCHANNEL_ADDR_95_64_SHIFT (0U)
/*! RxCChannel_Addr_95_64 - RxCChannel_Addr_95_64 */
#define SPDIF_SPDIFRXCCHANNEL_ADDR_95_64_RXCCHANNEL_ADDR_95_64(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFRXCCHANNEL_ADDR_95_64_RXCCHANNEL_ADDR_95_64_SHIFT)) & SPDIF_SPDIFRXCCHANNEL_ADDR_95_64_RXCCHANNEL_ADDR_95_64_MASK)
/*! @} */

/*! @name SPDIFRXCCHANNEL_ADDR_127_96 - SPDIF receive C channel register, bits 127-96 */
/*! @{ */

#define SPDIF_SPDIFRXCCHANNEL_ADDR_127_96_RXCCHANNEL_ADDR_127_96_MASK (0xFFFFFFFFU)
#define SPDIF_SPDIFRXCCHANNEL_ADDR_127_96_RXCCHANNEL_ADDR_127_96_SHIFT (0U)
/*! RxCChannel_Addr_127_96 - RxCChannel_Addr_127_96 */
#define SPDIF_SPDIFRXCCHANNEL_ADDR_127_96_RXCCHANNEL_ADDR_127_96(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFRXCCHANNEL_ADDR_127_96_RXCCHANNEL_ADDR_127_96_SHIFT)) & SPDIF_SPDIFRXCCHANNEL_ADDR_127_96_RXCCHANNEL_ADDR_127_96_MASK)
/*! @} */

/*! @name SPDIFRXCCHANNEL_ADDR_159_128 - SPDIF receive C channel register, bits 159-128 */
/*! @{ */

#define SPDIF_SPDIFRXCCHANNEL_ADDR_159_128_RXCCHANNEL_ADDR_159_128_MASK (0xFFFFFFFFU)
#define SPDIF_SPDIFRXCCHANNEL_ADDR_159_128_RXCCHANNEL_ADDR_159_128_SHIFT (0U)
/*! RxCChannel_Addr_159_128 - RxCChannel_Addr_159_128 */
#define SPDIF_SPDIFRXCCHANNEL_ADDR_159_128_RXCCHANNEL_ADDR_159_128(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFRXCCHANNEL_ADDR_159_128_RXCCHANNEL_ADDR_159_128_SHIFT)) & SPDIF_SPDIFRXCCHANNEL_ADDR_159_128_RXCCHANNEL_ADDR_159_128_MASK)
/*! @} */

/*! @name SPDIFRXCCHANNEL_ADDR_191_160 - SPDIF receive C channel register, bits 191-160 */
/*! @{ */

#define SPDIF_SPDIFRXCCHANNEL_ADDR_191_160_RXCCHANNEL_ADDR_191_160_MASK (0xFFFFFFFFU)
#define SPDIF_SPDIFRXCCHANNEL_ADDR_191_160_RXCCHANNEL_ADDR_191_160_SHIFT (0U)
/*! RxCChannel_Addr_191_160 - RxCChannel_Addr_191_160 */
#define SPDIF_SPDIFRXCCHANNEL_ADDR_191_160_RXCCHANNEL_ADDR_191_160(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFRXCCHANNEL_ADDR_191_160_RXCCHANNEL_ADDR_191_160_SHIFT)) & SPDIF_SPDIFRXCCHANNEL_ADDR_191_160_RXCCHANNEL_ADDR_191_160_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SPDIF_Register_Masks */


/* SPDIF - Peripheral instance base addresses */
/** Peripheral SPDIF base address */
#define SPDIF_BASE                               (0x2DAB0000u)
/** Peripheral SPDIF base pointer */
#define SPDIF                                    ((SPDIF_Type *)SPDIF_BASE)
/** Array initializer of SPDIF peripheral base addresses */
#define SPDIF_BASE_ADDRS                         { SPDIF_BASE }
/** Array initializer of SPDIF peripheral base pointers */
#define SPDIF_BASE_PTRS                          { SPDIF }
/** Interrupt vectors for the SPDIF peripheral type */
#define SPDIF_IRQS                               { SPDIF_IRQn }

/*!
 * @}
 */ /* end of group SPDIF_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SYSPM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSPM_Peripheral_Access_Layer SYSPM Peripheral Access Layer
 * @{
 */

/** SYSPM - Register Layout Typedef */
typedef struct {
  __I  uint32_t CFGSS[6];                          /**< Configuration 0..Configuration 5, array offset: 0x0, array step: 0x4 */
       uint8_t RESERVED_0[488];
  struct {                                         /* offset: 0x200, array step: 0x100 */
    __IO uint32_t PMCR;                              /**< Performance Monitor Control Register, array offset: 0x200, array step: 0x100 */
         uint8_t RESERVED_0[12];
    __I  uint8_t PMICTR_HI;                          /**< Performance Monitor Instruction Counter, array offset: 0x210, array step: 0x100 */
         uint8_t RESERVED_1[3];
    __I  uint32_t PMICTR_LO;                         /**< Performance Monitor Instruction Counter, array offset: 0x214, array step: 0x100 */
    struct {                                         /* offset: 0x218, array step: index*0x100, index2*0x8 */
      __I  uint8_t HI;                                 /**< Performance Monitor Event Counter, array offset: 0x218, array step: index*0x100, index2*0x8 */
           uint8_t RESERVED_0[3];
      __I  uint32_t LO;                                /**< Performance Monitor Event Counter, array offset: 0x21C, array step: index*0x100, index2*0x8 */
    } PMECTR[3];
         uint8_t RESERVED_2[208];
  } PMCR[4];
} SYSPM_Type;

/* ----------------------------------------------------------------------------
   -- SYSPM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSPM_Register_Masks SYSPM Register Masks
 * @{
 */

/*! @name CFGSS - Configuration 0..Configuration 5 */
/*! @{ */

#define SYSPM_CFGSS_ID_MASK                      (0xFFU)
#define SYSPM_CFGSS_ID_SHIFT                     (0U)
/*! ID - Identifier */
#define SYSPM_CFGSS_ID(x)                        (((uint32_t)(((uint32_t)(x)) << SYSPM_CFGSS_ID_SHIFT)) & SYSPM_CFGSS_ID_MASK)

#define SYSPM_CFGSS_HRL_MASK                     (0xFF00U)
#define SYSPM_CFGSS_HRL_SHIFT                    (8U)
/*! HRL - Hardware revision level */
#define SYSPM_CFGSS_HRL(x)                       (((uint32_t)(((uint32_t)(x)) << SYSPM_CFGSS_HRL_SHIFT)) & SYSPM_CFGSS_HRL_MASK)

#define SYSPM_CFGSS_NCTRS_MASK                   (0xFF0000U)
#define SYSPM_CFGSS_NCTRS_SHIFT                  (16U)
/*! NCTRS - Number of Counters */
#define SYSPM_CFGSS_NCTRS(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_CFGSS_NCTRS_SHIFT)) & SYSPM_CFGSS_NCTRS_MASK)

#define SYSPM_CFGSS_MSC_MASK                     (0xFF000000U)
#define SYSPM_CFGSS_MSC_SHIFT                    (24U)
/*! MSC - Miscellaneous */
#define SYSPM_CFGSS_MSC(x)                       (((uint32_t)(((uint32_t)(x)) << SYSPM_CFGSS_MSC_SHIFT)) & SYSPM_CFGSS_MSC_MASK)
/*! @} */

/* The count of SYSPM_CFGSS */
#define SYSPM_CFGSS_COUNT                        (6U)

/*! @name PMCR - Performance Monitor Control Register */
/*! @{ */

#define SYSPM_PMCR_MENB_MASK                     (0x1U)
#define SYSPM_PMCR_MENB_SHIFT                    (0U)
/*! MENB - Module is Enabled
 *  0b0..Disable the performance monitor.
 *  0b1..Enable the performance monitor.
 */
#define SYSPM_PMCR_MENB(x)                       (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_MENB_SHIFT)) & SYSPM_PMCR_MENB_MASK)

#define SYSPM_PMCR_SSC_MASK                      (0xEU)
#define SYSPM_PMCR_SSC_SHIFT                     (1U)
/*! SSC - Start/Stop Control
 *  0b000..Idle
 *  0b001..local stop
 *  0b010..local start
 *  0b011..local start
 *  0b100..
 *  0b101..
 *  0b110..
 *  0b111..
 */
#define SYSPM_PMCR_SSC(x)                        (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SSC_SHIFT)) & SYSPM_PMCR_SSC_MASK)

#define SYSPM_PMCR_CMODE_MASK                    (0x30U)
#define SYSPM_PMCR_CMODE_SHIFT                   (4U)
/*! CMODE - Count Mode
 *  0b00..count in both user and previleged modes
 *  0b01..Reserved
 *  0b10..count only in user mode
 *  0b11..count only in privileged mode
 */
#define SYSPM_PMCR_CMODE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_CMODE_SHIFT)) & SYSPM_PMCR_CMODE_MASK)

#define SYSPM_PMCR_RICTR_MASK                    (0x80U)
#define SYSPM_PMCR_RICTR_SHIFT                   (7U)
/*! RICTR - Resets the Instruction Counter
 *  0b0..do not reset the instruction counter
 *  0b1..clear the instruction counter
 */
#define SYSPM_PMCR_RICTR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RICTR_SHIFT)) & SYSPM_PMCR_RICTR_MASK)

#define SYSPM_PMCR_RECTR1_MASK                   (0x100U)
#define SYSPM_PMCR_RECTR1_SHIFT                  (8U)
/*! RECTR1 - Reset Event Counter 1 */
#define SYSPM_PMCR_RECTR1(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR1_SHIFT)) & SYSPM_PMCR_RECTR1_MASK)

#define SYSPM_PMCR_RECTR2_MASK                   (0x200U)
#define SYSPM_PMCR_RECTR2_SHIFT                  (9U)
/*! RECTR2 - Reset Event Counter 2 */
#define SYSPM_PMCR_RECTR2(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR2_SHIFT)) & SYSPM_PMCR_RECTR2_MASK)

#define SYSPM_PMCR_RECTR3_MASK                   (0x400U)
#define SYSPM_PMCR_RECTR3_SHIFT                  (10U)
/*! RECTR3 - Reset Event Counter 3
 *  0b0..Counter runs normally
 *  0b1..Counter value resets at the end of the cycle
 */
#define SYSPM_PMCR_RECTR3(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR3_SHIFT)) & SYSPM_PMCR_RECTR3_MASK)

#define SYSPM_PMCR_SELEVT1_MASK                  (0x3F800U)
#define SYSPM_PMCR_SELEVT1_SHIFT                 (11U)
/*! SELEVT1 - Select Event 1 */
#define SYSPM_PMCR_SELEVT1(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT1_SHIFT)) & SYSPM_PMCR_SELEVT1_MASK)

#define SYSPM_PMCR_SELEVT2_MASK                  (0x1FC0000U)
#define SYSPM_PMCR_SELEVT2_SHIFT                 (18U)
/*! SELEVT2 - Select Event 2 */
#define SYSPM_PMCR_SELEVT2(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT2_SHIFT)) & SYSPM_PMCR_SELEVT2_MASK)

#define SYSPM_PMCR_SELEVT3_MASK                  (0xFE000000U)
#define SYSPM_PMCR_SELEVT3_SHIFT                 (25U)
/*! SELEVT3 - Select Event 3 */
#define SYSPM_PMCR_SELEVT3(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT3_SHIFT)) & SYSPM_PMCR_SELEVT3_MASK)
/*! @} */

/* The count of SYSPM_PMCR */
#define SYSPM_PMCR_COUNT                         (4U)

/*! @name PMICTR_HI - Performance Monitor Instruction Counter */
/*! @{ */

#define SYSPM_PMICTR_HI_ICTR_MASK                (0xFFU)
#define SYSPM_PMICTR_HI_ICTR_SHIFT               (0U)
/*! ICTR - Instruction counter */
#define SYSPM_PMICTR_HI_ICTR(x)                  (((uint8_t)(((uint8_t)(x)) << SYSPM_PMICTR_HI_ICTR_SHIFT)) & SYSPM_PMICTR_HI_ICTR_MASK)
/*! @} */

/* The count of SYSPM_PMICTR_HI */
#define SYSPM_PMICTR_HI_COUNT                    (4U)

/*! @name PMICTR_LO - Performance Monitor Instruction Counter */
/*! @{ */

#define SYSPM_PMICTR_LO_ICTR_MASK                (0xFFFFFFFFU)
#define SYSPM_PMICTR_LO_ICTR_SHIFT               (0U)
/*! ICTR - Instruction counter */
#define SYSPM_PMICTR_LO_ICTR(x)                  (((uint32_t)(((uint32_t)(x)) << SYSPM_PMICTR_LO_ICTR_SHIFT)) & SYSPM_PMICTR_LO_ICTR_MASK)
/*! @} */

/* The count of SYSPM_PMICTR_LO */
#define SYSPM_PMICTR_LO_COUNT                    (4U)

/*! @name HI - Performance Monitor Event Counter */
/*! @{ */

#define SYSPM_HI_ECTR_MASK                       (0xFFU)
#define SYSPM_HI_ECTR_SHIFT                      (0U)
/*! ECTR - Event Counter */
#define SYSPM_HI_ECTR(x)                         (((uint8_t)(((uint8_t)(x)) << SYSPM_HI_ECTR_SHIFT)) & SYSPM_HI_ECTR_MASK)
/*! @} */

/* The count of SYSPM_HI */
#define SYSPM_HI_COUNT                           (4U)

/* The count of SYSPM_HI */
#define SYSPM_HI_COUNT2                          (3U)

/*! @name LO - Performance Monitor Event Counter */
/*! @{ */

#define SYSPM_LO_ECTR_MASK                       (0xFFFFFFFFU)
#define SYSPM_LO_ECTR_SHIFT                      (0U)
/*! ECTR - Event Counter */
#define SYSPM_LO_ECTR(x)                         (((uint32_t)(((uint32_t)(x)) << SYSPM_LO_ECTR_SHIFT)) & SYSPM_LO_ECTR_MASK)
/*! @} */

/* The count of SYSPM_LO */
#define SYSPM_LO_COUNT                           (4U)

/* The count of SYSPM_LO */
#define SYSPM_LO_COUNT2                          (3U)


/*!
 * @}
 */ /* end of group SYSPM_Register_Masks */


/* SYSPM - Peripheral instance base addresses */
/** Peripheral SYSPM0 base address */
#define SYSPM0_BASE                              (0x28026000u)
/** Peripheral SYSPM0 base pointer */
#define SYSPM0                                   ((SYSPM_Type *)SYSPM0_BASE)
/** Peripheral SYSPM1 base address */
#define SYSPM1_BASE                              (0x29270000u)
/** Peripheral SYSPM1 base pointer */
#define SYSPM1                                   ((SYSPM_Type *)SYSPM1_BASE)
/** Array initializer of SYSPM peripheral base addresses */
#define SYSPM_BASE_ADDRS                         { SYSPM0_BASE, SYSPM1_BASE }
/** Array initializer of SYSPM peripheral base pointers */
#define SYSPM_BASE_PTRS                          { SYSPM0, SYSPM1 }

/*!
 * @}
 */ /* end of group SYSPM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TPM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
 * @{
 */

/** TPM - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
  __IO uint32_t GLOBAL;                            /**< TPM Global, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t SC;                                /**< Status and Control, offset: 0x10 */
  __IO uint32_t CNT;                               /**< Counter, offset: 0x14 */
  __IO uint32_t MOD;                               /**< Modulo, offset: 0x18 */
  __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x1C */
  struct {                                         /* offset: 0x20, array step: 0x8 */
    __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8, irregular array, not all indices are valid */
    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x24, array step: 0x8, irregular array, not all indices are valid */
  } CONTROLS[6];
       uint8_t RESERVED_1[20];
  __IO uint32_t COMBINE;                           /**< Combine Channel Register, offset: 0x64 */
       uint8_t RESERVED_2[4];
  __IO uint32_t TRIG;                              /**< Channel Trigger, offset: 0x6C */
  __IO uint32_t POL;                               /**< Channel Polarity, offset: 0x70 */
       uint8_t RESERVED_3[4];
  __IO uint32_t FILTER;                            /**< Filter Control, offset: 0x78 */
       uint8_t RESERVED_4[4];
  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control and Status, offset: 0x80 */
  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
} TPM_Type;

/* ----------------------------------------------------------------------------
   -- TPM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TPM_Register_Masks TPM Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define TPM_VERID_FEATURE_MASK                   (0xFFFFU)
#define TPM_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Identification Number
 *  0b0000000000000001..Standard feature set.
 *  0b0000000000000011..Standard feature set with Filter and Combine registers implemented.
 *  0b0000000000000101..Standard feature set with Quadrature registers implemented.
 *  0b0000000000000111..Standard feature set with Filter, Combine and Quadrature registers implemented.
 */
#define TPM_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK)

#define TPM_VERID_MINOR_MASK                     (0xFF0000U)
#define TPM_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number */
#define TPM_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK)

#define TPM_VERID_MAJOR_MASK                     (0xFF000000U)
#define TPM_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number */
#define TPM_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define TPM_PARAM_CHAN_MASK                      (0xFFU)
#define TPM_PARAM_CHAN_SHIFT                     (0U)
/*! CHAN - Channel Count */
#define TPM_PARAM_CHAN(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK)

#define TPM_PARAM_TRIG_MASK                      (0xFF00U)
#define TPM_PARAM_TRIG_SHIFT                     (8U)
/*! TRIG - Trigger Count */
#define TPM_PARAM_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK)

#define TPM_PARAM_WIDTH_MASK                     (0xFF0000U)
#define TPM_PARAM_WIDTH_SHIFT                    (16U)
/*! WIDTH - Counter Width */
#define TPM_PARAM_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK)
/*! @} */

/*! @name GLOBAL - TPM Global */
/*! @{ */

#define TPM_GLOBAL_NOUPDATE_MASK                 (0x1U)
#define TPM_GLOBAL_NOUPDATE_SHIFT                (0U)
/*! NOUPDATE - No Update
 *  0b0..Internal double buffered registers update as normal.
 *  0b1..Internal double buffered registers do not update.
 */
#define TPM_GLOBAL_NOUPDATE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_NOUPDATE_SHIFT)) & TPM_GLOBAL_NOUPDATE_MASK)

#define TPM_GLOBAL_RST_MASK                      (0x2U)
#define TPM_GLOBAL_RST_SHIFT                     (1U)
/*! RST - Software Reset
 *  0b0..Module is not reset.
 *  0b1..Module is reset.
 */
#define TPM_GLOBAL_RST(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK)
/*! @} */

/*! @name SC - Status and Control */
/*! @{ */

#define TPM_SC_PS_MASK                           (0x7U)
#define TPM_SC_PS_SHIFT                          (0U)
/*! PS - Prescale Factor Selection
 *  0b000..Divide by 1
 *  0b001..Divide by 2
 *  0b010..Divide by 4
 *  0b011..Divide by 8
 *  0b100..Divide by 16
 *  0b101..Divide by 32
 *  0b110..Divide by 64
 *  0b111..Divide by 128
 */
#define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)

#define TPM_SC_CMOD_MASK                         (0x18U)
#define TPM_SC_CMOD_SHIFT                        (3U)
/*! CMOD - Clock Mode Selection
 *  0b00..TPM counter is disabled
 *  0b01..TPM counter increments on every TPM counter clock
 *  0b10..TPM counter increments on rising edge of EXTCLK synchronized to the TPM counter clock
 *  0b11..TPM counter increments on rising edge of the selected external input trigger.
 */
#define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)

#define TPM_SC_CPWMS_MASK                        (0x20U)
#define TPM_SC_CPWMS_SHIFT                       (5U)
/*! CPWMS - Center-Aligned PWM Select
 *  0b0..TPM counter operates in up counting mode.
 *  0b1..TPM counter operates in up-down counting mode.
 */
#define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)

#define TPM_SC_TOIE_MASK                         (0x40U)
#define TPM_SC_TOIE_SHIFT                        (6U)
/*! TOIE - Timer Overflow Interrupt Enable
 *  0b0..Disable TOF interrupts. Use software polling or DMA request.
 *  0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
 */
#define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)

#define TPM_SC_TOF_MASK                          (0x80U)
#define TPM_SC_TOF_SHIFT                         (7U)
/*! TOF - Timer Overflow Flag
 *  0b0..TPM counter has not overflowed.
 *  0b1..TPM counter has overflowed.
 */
#define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)

#define TPM_SC_DMA_MASK                          (0x100U)
#define TPM_SC_DMA_SHIFT                         (8U)
/*! DMA - DMA Enable
 *  0b0..Disables DMA transfers.
 *  0b1..Enables DMA transfers.
 */
#define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
/*! @} */

/*! @name CNT - Counter */
/*! @{ */

#define TPM_CNT_COUNT_MASK                       (0xFFFFFFFFU)  /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
#define TPM_CNT_COUNT_SHIFT                      (0U)
/*! COUNT - Counter value */
#define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)  /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
/*! @} */

/*! @name MOD - Modulo */
/*! @{ */

#define TPM_MOD_MOD_MASK                         (0xFFFFFFFFU)  /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
#define TPM_MOD_MOD_SHIFT                        (0U)
/*! MOD - Modulo value */
#define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)  /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
/*! @} */

/*! @name STATUS - Capture and Compare Status */
/*! @{ */

#define TPM_STATUS_CH0F_MASK                     (0x1U)
#define TPM_STATUS_CH0F_SHIFT                    (0U)
/*! CH0F - Channel 0 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)

#define TPM_STATUS_CH1F_MASK                     (0x2U)
#define TPM_STATUS_CH1F_SHIFT                    (1U)
/*! CH1F - Channel 1 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)

#define TPM_STATUS_CH2F_MASK                     (0x4U)
#define TPM_STATUS_CH2F_SHIFT                    (2U)
/*! CH2F - Channel 2 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)

#define TPM_STATUS_CH3F_MASK                     (0x8U)
#define TPM_STATUS_CH3F_SHIFT                    (3U)
/*! CH3F - Channel 3 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)

#define TPM_STATUS_CH4F_MASK                     (0x10U)
#define TPM_STATUS_CH4F_SHIFT                    (4U)
/*! CH4F - Channel 4 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)

#define TPM_STATUS_CH5F_MASK                     (0x20U)
#define TPM_STATUS_CH5F_SHIFT                    (5U)
/*! CH5F - Channel 5 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)

#define TPM_STATUS_TOF_MASK                      (0x100U)
#define TPM_STATUS_TOF_SHIFT                     (8U)
/*! TOF - Timer Overflow Flag
 *  0b0..TPM counter has not overflowed.
 *  0b1..TPM counter has overflowed.
 */
#define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
/*! @} */

/*! @name CnSC - Channel (n) Status and Control */
/*! @{ */

#define TPM_CnSC_DMA_MASK                        (0x1U)
#define TPM_CnSC_DMA_SHIFT                       (0U)
/*! DMA - DMA Enable
 *  0b0..Disable DMA transfers.
 *  0b1..Enable DMA transfers.
 */
#define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)

#define TPM_CnSC_ELSA_MASK                       (0x4U)
#define TPM_CnSC_ELSA_SHIFT                      (2U)
/*! ELSA - Edge or Level Select */
#define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)

#define TPM_CnSC_ELSB_MASK                       (0x8U)
#define TPM_CnSC_ELSB_SHIFT                      (3U)
/*! ELSB - Edge or Level Select */
#define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)

#define TPM_CnSC_MSA_MASK                        (0x10U)
#define TPM_CnSC_MSA_SHIFT                       (4U)
/*! MSA - Channel Mode Select */
#define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)

#define TPM_CnSC_MSB_MASK                        (0x20U)
#define TPM_CnSC_MSB_SHIFT                       (5U)
/*! MSB - Channel Mode Select */
#define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)

#define TPM_CnSC_CHIE_MASK                       (0x40U)
#define TPM_CnSC_CHIE_SHIFT                      (6U)
/*! CHIE - Channel Interrupt Enable
 *  0b0..Disable channel interrupts.
 *  0b1..Enable channel interrupts.
 */
#define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)

#define TPM_CnSC_CHF_MASK                        (0x80U)
#define TPM_CnSC_CHF_SHIFT                       (7U)
/*! CHF - Channel Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
/*! @} */

/* The count of TPM_CnSC */
#define TPM_CnSC_COUNT                           (6U)

/*! @name CnV - Channel (n) Value */
/*! @{ */

#define TPM_CnV_VAL_MASK                         (0xFFFFFFFFU)  /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
#define TPM_CnV_VAL_SHIFT                        (0U)
/*! VAL - Channel Value */
#define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)  /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
/*! @} */

/* The count of TPM_CnV */
#define TPM_CnV_COUNT                            (6U)

/*! @name COMBINE - Combine Channel Register */
/*! @{ */

#define TPM_COMBINE_COMBINE0_MASK                (0x1U)
#define TPM_COMBINE_COMBINE0_SHIFT               (0U)
/*! COMBINE0 - Combine Channels 0 and 1
 *  0b0..Channels 0 and 1 are independent.
 *  0b1..Channels 0 and 1 are combined.
 */
#define TPM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)

#define TPM_COMBINE_COMSWAP0_MASK                (0x2U)
#define TPM_COMBINE_COMSWAP0_SHIFT               (1U)
/*! COMSWAP0 - Combine Channel 0 and 1 Swap
 *  0b0..Even channel is used for input capture and 1st compare.
 *  0b1..Odd channel is used for input capture and 1st compare.
 */
#define TPM_COMBINE_COMSWAP0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)

#define TPM_COMBINE_COMBINE1_MASK                (0x100U)
#define TPM_COMBINE_COMBINE1_SHIFT               (8U)
/*! COMBINE1 - Combine Channels 2 and 3
 *  0b0..Channels 2 and 3 are independent.
 *  0b1..Channels 2 and 3 are combined.
 */
#define TPM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK)

#define TPM_COMBINE_COMSWAP1_MASK                (0x200U)
#define TPM_COMBINE_COMSWAP1_SHIFT               (9U)
/*! COMSWAP1 - Combine Channels 2 and 3 Swap
 *  0b0..Even channel is used for input capture and 1st compare.
 *  0b1..Odd channel is used for input capture and 1st compare.
 */
#define TPM_COMBINE_COMSWAP1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK)

#define TPM_COMBINE_COMBINE2_MASK                (0x10000U)
#define TPM_COMBINE_COMBINE2_SHIFT               (16U)
/*! COMBINE2 - Combine Channels 4 and 5
 *  0b0..Channels 4 and 5 are independent.
 *  0b1..Channels 4 and 5 are combined.
 */
#define TPM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK)

#define TPM_COMBINE_COMSWAP2_MASK                (0x20000U)
#define TPM_COMBINE_COMSWAP2_SHIFT               (17U)
/*! COMSWAP2 - Combine Channels 4 and 5 Swap
 *  0b0..Even channel is used for input capture and 1st compare.
 *  0b1..Odd channel is used for input capture and 1st compare.
 */
#define TPM_COMBINE_COMSWAP2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK)
/*! @} */

/*! @name TRIG - Channel Trigger */
/*! @{ */

#define TPM_TRIG_TRIG0_MASK                      (0x1U)
#define TPM_TRIG_TRIG0_SHIFT                     (0U)
/*! TRIG0 - Channel 0 Trigger
 *  0b0..No effect.
 *  0b1..Configures trigger input 0 to be used by channel 0.
 */
#define TPM_TRIG_TRIG0(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK)

#define TPM_TRIG_TRIG1_MASK                      (0x2U)
#define TPM_TRIG_TRIG1_SHIFT                     (1U)
/*! TRIG1 - Channel 1 Trigger
 *  0b0..No effect.
 *  0b1..Configures trigger input 1 to be used by channel 1.
 */
#define TPM_TRIG_TRIG1(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK)

#define TPM_TRIG_TRIG2_MASK                      (0x4U)
#define TPM_TRIG_TRIG2_SHIFT                     (2U)
/*! TRIG2 - Channel 2 Trigger
 *  0b0..No effect.
 *  0b1..Configures trigger input 0 to be used by channel 2.
 */
#define TPM_TRIG_TRIG2(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK)

#define TPM_TRIG_TRIG3_MASK                      (0x8U)
#define TPM_TRIG_TRIG3_SHIFT                     (3U)
/*! TRIG3 - Channel 3 Trigger
 *  0b0..No effect.
 *  0b1..Configures trigger input 1 to be used by channel 3.
 */
#define TPM_TRIG_TRIG3(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK)

#define TPM_TRIG_TRIG4_MASK                      (0x10U)
#define TPM_TRIG_TRIG4_SHIFT                     (4U)
/*! TRIG4 - Channel 4 Trigger
 *  0b0..No effect.
 *  0b1..Configures trigger input 0 to be used by channel 4.
 */
#define TPM_TRIG_TRIG4(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG4_SHIFT)) & TPM_TRIG_TRIG4_MASK)

#define TPM_TRIG_TRIG5_MASK                      (0x20U)
#define TPM_TRIG_TRIG5_SHIFT                     (5U)
/*! TRIG5 - Channel 5 Trigger
 *  0b0..No effect.
 *  0b1..Configures trigger input 1 to be used by channel 5.
 */
#define TPM_TRIG_TRIG5(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG5_SHIFT)) & TPM_TRIG_TRIG5_MASK)
/*! @} */

/*! @name POL - Channel Polarity */
/*! @{ */

#define TPM_POL_POL0_MASK                        (0x1U)
#define TPM_POL_POL0_SHIFT                       (0U)
/*! POL0 - Channel 0 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)

#define TPM_POL_POL1_MASK                        (0x2U)
#define TPM_POL_POL1_SHIFT                       (1U)
/*! POL1 - Channel 1 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)

#define TPM_POL_POL2_MASK                        (0x4U)
#define TPM_POL_POL2_SHIFT                       (2U)
/*! POL2 - Channel 2 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)

#define TPM_POL_POL3_MASK                        (0x8U)
#define TPM_POL_POL3_SHIFT                       (3U)
/*! POL3 - Channel 3 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)

#define TPM_POL_POL4_MASK                        (0x10U)
#define TPM_POL_POL4_SHIFT                       (4U)
/*! POL4 - Channel 4 Polarity
 *  0b0..The channel polarity is active high
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK)

#define TPM_POL_POL5_MASK                        (0x20U)
#define TPM_POL_POL5_SHIFT                       (5U)
/*! POL5 - Channel 5 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK)
/*! @} */

/*! @name FILTER - Filter Control */
/*! @{ */

#define TPM_FILTER_CH0FVAL_MASK                  (0xFU)
#define TPM_FILTER_CH0FVAL_SHIFT                 (0U)
/*! CH0FVAL - Channel 0 Filter Value */
#define TPM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)

#define TPM_FILTER_CH1FVAL_MASK                  (0xF0U)
#define TPM_FILTER_CH1FVAL_SHIFT                 (4U)
/*! CH1FVAL - Channel 1 Filter Value */
#define TPM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)

#define TPM_FILTER_CH2FVAL_MASK                  (0xF00U)
#define TPM_FILTER_CH2FVAL_SHIFT                 (8U)
/*! CH2FVAL - Channel 2 Filter Value */
#define TPM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK)

#define TPM_FILTER_CH3FVAL_MASK                  (0xF000U)
#define TPM_FILTER_CH3FVAL_SHIFT                 (12U)
/*! CH3FVAL - Channel 3 Filter Value */
#define TPM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK)

#define TPM_FILTER_CH4FVAL_MASK                  (0xF0000U)
#define TPM_FILTER_CH4FVAL_SHIFT                 (16U)
/*! CH4FVAL - Channel 4 Filter Value */
#define TPM_FILTER_CH4FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK)

#define TPM_FILTER_CH5FVAL_MASK                  (0xF00000U)
#define TPM_FILTER_CH5FVAL_SHIFT                 (20U)
/*! CH5FVAL - Channel 5 Filter Value */
#define TPM_FILTER_CH5FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK)
/*! @} */

/*! @name QDCTRL - Quadrature Decoder Control and Status */
/*! @{ */

#define TPM_QDCTRL_QUADEN_MASK                   (0x1U)
#define TPM_QDCTRL_QUADEN_SHIFT                  (0U)
/*! QUADEN - QUADEN
 *  0b0..Quadrature decoder mode is disabled.
 *  0b1..Quadrature decoder mode is enabled.
 */
#define TPM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)

#define TPM_QDCTRL_TOFDIR_MASK                   (0x2U)
#define TPM_QDCTRL_TOFDIR_SHIFT                  (1U)
/*! TOFDIR - TOFDIR
 *  0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes
 *       from its minimum value (zero) to its maximum value (MOD register).
 *  0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from
 *       its maximum value (MOD register) to its minimum value (zero).
 */
#define TPM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)

#define TPM_QDCTRL_QUADIR_MASK                   (0x4U)
#define TPM_QDCTRL_QUADIR_SHIFT                  (2U)
/*! QUADIR - Counter Direction in Quadrature Decode Mode
 *  0b0..Counter direction is decreasing (counter decrement).
 *  0b1..Counter direction is increasing (counter increment).
 */
#define TPM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)

#define TPM_QDCTRL_QUADMODE_MASK                 (0x8U)
#define TPM_QDCTRL_QUADMODE_SHIFT                (3U)
/*! QUADMODE - Quadrature Decoder Mode
 *  0b0..Phase encoding mode.
 *  0b1..Count and direction encoding mode.
 */
#define TPM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
/*! @} */

/*! @name CONF - Configuration */
/*! @{ */

#define TPM_CONF_DOZEEN_MASK                     (0x20U)
#define TPM_CONF_DOZEEN_SHIFT                    (5U)
/*! DOZEEN - Doze Enable
 *  0b0..Internal TPM counter continues.
 *  0b1..Internal TPM counter is paused and does not increment. Trigger inputs and input capture events are
 *       ignored, and PWM outputs are forced to their default state.
 */
#define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)

#define TPM_CONF_DBGMODE_MASK                    (0xC0U)
#define TPM_CONF_DBGMODE_SHIFT                   (6U)
/*! DBGMODE - Debug Mode
 *  0b00..TPM counter is paused and does not increment. Trigger inputs and input capture events are ignored, and
 *        PWM outputs are forced to their default state.
 *  0b11..TPM counter continues.
 */
#define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)

#define TPM_CONF_GTBSYNC_MASK                    (0x100U)
#define TPM_CONF_GTBSYNC_SHIFT                   (8U)
/*! GTBSYNC - Global Time Base Synchronization
 *  0b0..Global timebase synchronization disabled.
 *  0b1..Global timebase synchronization enabled.
 */
#define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)

#define TPM_CONF_GTBEEN_MASK                     (0x200U)
#define TPM_CONF_GTBEEN_SHIFT                    (9U)
/*! GTBEEN - Global time base enable
 *  0b0..All channels use the internally generated TPM counter as their timebase
 *  0b1..All channels use an externally generated global timebase as their timebase
 */
#define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)

#define TPM_CONF_CSOT_MASK                       (0x10000U)
#define TPM_CONF_CSOT_SHIFT                      (16U)
/*! CSOT - Counter Start on Trigger
 *  0b0..TPM counter starts to increment immediately, once it is enabled.
 *  0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected,
 *       after it has been enabled or after it has stopped due to overflow.
 */
#define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)

#define TPM_CONF_CSOO_MASK                       (0x20000U)
#define TPM_CONF_CSOO_SHIFT                      (17U)
/*! CSOO - Counter Stop On Overflow
 *  0b0..TPM counter continues incrementing or decrementing after overflow
 *  0b1..TPM counter stops incrementing or decrementing after overflow.
 */
#define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)

#define TPM_CONF_CROT_MASK                       (0x40000U)
#define TPM_CONF_CROT_SHIFT                      (18U)
/*! CROT - Counter Reload On Trigger
 *  0b0..Counter is not reloaded due to a rising edge on the selected input trigger
 *  0b1..Counter is reloaded when a rising edge is detected on the selected input trigger
 */
#define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)

#define TPM_CONF_CPOT_MASK                       (0x80000U)
#define TPM_CONF_CPOT_SHIFT                      (19U)
/*! CPOT - Counter Pause On Trigger
 *  0b0..TPM counter continues
 *  0b1..TPM counter pauses
 */
#define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)

#define TPM_CONF_TRGPOL_MASK                     (0x400000U)
#define TPM_CONF_TRGPOL_SHIFT                    (22U)
/*! TRGPOL - Trigger Polarity
 *  0b0..Trigger is active high.
 *  0b1..Trigger is active low.
 */
#define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)

#define TPM_CONF_TRGSRC_MASK                     (0x800000U)
#define TPM_CONF_TRGSRC_SHIFT                    (23U)
/*! TRGSRC - Trigger Source
 *  0b0..Trigger source selected by TRGSEL is external.
 *  0b1..Trigger source selected by TRGSEL is internal (channel pin input capture).
 */
#define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)

#define TPM_CONF_TRGSEL_MASK                     (0x7000000U)  /* Merged from fields with different position or width, of widths (2, 3), largest definition used */
#define TPM_CONF_TRGSEL_SHIFT                    (24U)
/*! TRGSEL - Trigger Select
 *  0b001..Channel 0 pin input capture
 *  0b010..Channel 1 pin input capture
 *  0b011..Channel 0 or Channel 1 pin input capture
 *  0b100..Channel 2 pin input capture
 *  0b101..Channel 0 or Channel 2 pin input capture
 *  0b110..Channel 1 or Channel 2 pin input capture
 *  0b111..Channel 0 or Channel 1 or Channel 2 pin input capture
 */
#define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)  /* Merged from fields with different position or width, of widths (2, 3), largest definition used */
/*! @} */


/*!
 * @}
 */ /* end of group TPM_Register_Masks */


/* TPM - Peripheral instance base addresses */
/** Peripheral TPM0 base address */
#define TPM0_BASE                                (0x28095000u)
/** Peripheral TPM0 base pointer */
#define TPM0                                     ((TPM_Type *)TPM0_BASE)
/** Peripheral TPM1 base address */
#define TPM1_BASE                                (0x28096000u)
/** Peripheral TPM1 base pointer */
#define TPM1                                     ((TPM_Type *)TPM1_BASE)
/** Peripheral TPM2 base address */
#define TPM2_BASE                                (0x28105000u)
/** Peripheral TPM2 base pointer */
#define TPM2                                     ((TPM_Type *)TPM2_BASE)
/** Peripheral TPM3 base address */
#define TPM3_BASE                                (0x28106000u)
/** Peripheral TPM3 base pointer */
#define TPM3                                     ((TPM_Type *)TPM3_BASE)
/** Peripheral TPM4 base address */
#define TPM4_BASE                                (0x29330000u)
/** Peripheral TPM4 base pointer */
#define TPM4                                     ((TPM_Type *)TPM4_BASE)
/** Peripheral TPM5 base address */
#define TPM5_BASE                                (0x29340000u)
/** Peripheral TPM5 base pointer */
#define TPM5                                     ((TPM_Type *)TPM5_BASE)
/** Peripheral TPM6 base address */
#define TPM6_BASE                                (0x29820000u)
/** Peripheral TPM6 base pointer */
#define TPM6                                     ((TPM_Type *)TPM6_BASE)
/** Peripheral TPM7 base address */
#define TPM7_BASE                                (0x29830000u)
/** Peripheral TPM7 base pointer */
#define TPM7                                     ((TPM_Type *)TPM7_BASE)
/** Peripheral TPM8 base address */
#define TPM8_BASE                                (0x2DA80000u)
/** Peripheral TPM8 base pointer */
#define TPM8                                     ((TPM_Type *)TPM8_BASE)
/** Array initializer of TPM peripheral base addresses */
#define TPM_BASE_ADDRS                           { TPM0_BASE, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE, TPM7_BASE, TPM8_BASE }
/** Array initializer of TPM peripheral base pointers */
#define TPM_BASE_PTRS                            { TPM0, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6, TPM7, TPM8 }
/** Interrupt vectors for the TPM peripheral type */
#define TPM_IRQS                                 { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, TPM8_IRQn }

/*!
 * @}
 */ /* end of group TPM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TRDC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer
 * @{
 */

/** TRDC - Register Layout Typedef */
typedef struct {
  __IO uint32_t TRDC_CR;                           /**< TRDC Register, offset: 0x0 */
       uint8_t RESERVED_0[236];
  __I  uint32_t TRDC_HWCFG0;                       /**< Hardware Configuration Register 0, offset: 0xF0 */
  __I  uint32_t TRDC_HWCFG1;                       /**< TRDC Hardware Configuration Register 1, offset: 0xF4 */
       uint8_t RESERVED_1[8];
  __I  uint8_t DACFG[8];                           /**< Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 */
       uint8_t RESERVED_2[56];
  __I  uint32_t CFG[4][2];                         /**< Memory Block Configuration Register, array offset: 0x140, array step: index*0x8, index2*0x4 */
  __I  uint8_t MRCFG[8];                           /**< Memory Region Configuration Register, array offset: 0x160, array step: 0x1 */
       uint8_t RESERVED_3[88];
  __IO uint32_t TRDC_IDAU_CR;                      /**< TRDC IDAU Control Register, offset: 0x1C0 */
       uint8_t RESERVED_4[28];
  __IO uint32_t TRDC_FLW_CTL;                      /**< TRDC FLW Control, offset: 0x1E0 */
  __I  uint32_t TRDC_FLW_PBASE;                    /**< TRDC FLW Physical Base, offset: 0x1E4 */
  __IO uint32_t TRDC_FLW_ABASE;                    /**< TRDC FLW Array Base, offset: 0x1E8 */
  __IO uint32_t TRDC_FLW_BCNT;                     /**< TRDC FLW Block Count, offset: 0x1EC */
       uint8_t RESERVED_5[12];
  __IO uint32_t TRDC_FDID;                         /**< TRDC Fault Domain ID, offset: 0x1FC */
  __I  uint32_t TRDC_DERRLOC[8];                   /**< TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_6[480];
  struct {                                         /* offset: 0x400, array step: 0x10 */
    __I  uint32_t W0;                                /**< MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10 */
    __I  uint32_t W1;                                /**< MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10 */
         uint8_t RESERVED_0[4];
    __O  uint32_t W3;                                /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10 */
  } MBC_DERR[4];
       uint8_t RESERVED_7[64];
  struct {                                         /* offset: 0x480, array step: 0x10 */
    __I  uint32_t W0;                                /**< MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10 */
    __I  uint32_t W1;                                /**< MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10 */
         uint8_t RESERVED_0[4];
    __O  uint32_t W3;                                /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10 */
  } MRC_DERR[2];
       uint8_t RESERVED_8[864];
  __IO uint32_t MDA_W0_0_DFMT0;                    /**< DAC Master Domain Assignment Register, offset: 0x800 */
       uint8_t RESERVED_9[28];
  struct {                                         /* offset: 0x820, array step: 0x20 */
    __IO uint32_t MDA_W0_x_DFMT1;                    /**< DAC Master Domain Assignment Register, array offset: 0x820, array step: 0x20 */
         uint8_t RESERVED_0[28];
  } MDA_W0_DFMT1[7];
       uint8_t RESERVED_10[1792];
  struct {                                         /* offset: 0x1000, array step: 0x1000 */
    __I  uint32_t MBC_MEM_GLBCFG[4];                 /**< MBC Global Configuration Register, array offset: 0x1000, array step: index*0x1000, index2*0x4 */
    __IO uint32_t MBC_NSE_BLK_INDEX;                 /**< MBC NonSecure Enable Block Index, array offset: 0x1010, array step: 0x1000 */
    __O  uint32_t MBC_NSE_BLK_SET;                   /**< MBC NonSecure Enable Block Set, array offset: 0x1014, array step: 0x1000 */
    __O  uint32_t MBC_NSE_BLK_CLR;                   /**< MBC NonSecure Enable Block Clear, array offset: 0x1018, array step: 0x1000 */
    __O  uint32_t MBC_NSE_BLK_CLR_ALL;               /**< MBC NonSecure Enable Block Clear All, array offset: 0x101C, array step: 0x1000 */
    __IO uint32_t MBC_MEMN_GLBAC[8];                 /**< MBC Global Access Control, array offset: 0x1020, array step: index*0x1000, index2*0x4 */
    __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[9];        /**< MBC Memory Block Configuration Word, array offset: 0x1040, array step: index*0x1000, index2*0x4, valid indices: [0][0], [1][0], [2][0-8], [3][0-2] */
         uint8_t RESERVED_0[220];
    __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[3];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1140, array step: index*0x1000, index2*0x4, valid indices: [0-3][0], [2][1], [2][2] */
         uint8_t RESERVED_1[52];
    __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[6];        /**< MBC Memory Block Configuration Word, array offset: 0x1180, array step: index*0x1000, index2*0x4, valid indices: [0][0-1], [1][0], [2][0-5] */
         uint8_t RESERVED_2[8];
    __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[2];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11A0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1] */
    __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x11A8, array step: index*0x1000, index2*0x4, valid indices: [0][0-3], [1][0], [2][0] */
         uint8_t RESERVED_3[16];
    __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11C8, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_4[4];
    __IO uint32_t MBC_DOM0_MEM3_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x11D0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_5[28];
    __IO uint32_t MBC_DOM0_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11F0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_6[76];
    __IO uint32_t MBC_DOM1_MEM0_BLK_CFG_W[9];        /**< MBC Memory Block Configuration Word, array offset: 0x1240, array step: index*0x1000, index2*0x4, valid indices: [0][0], [1][0], [2][0-8], [3][0-2] */
         uint8_t RESERVED_7[220];
    __IO uint32_t MBC_DOM1_MEM0_BLK_NSE_W[3];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1340, array step: index*0x1000, index2*0x4, valid indices: [0-3][0], [2][1], [2][2] */
         uint8_t RESERVED_8[52];
    __IO uint32_t MBC_DOM1_MEM1_BLK_CFG_W[6];        /**< MBC Memory Block Configuration Word, array offset: 0x1380, array step: index*0x1000, index2*0x4, valid indices: [0][0-1], [1][0], [2][0-5] */
         uint8_t RESERVED_9[8];
    __IO uint32_t MBC_DOM1_MEM1_BLK_NSE_W[2];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x13A0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1] */
    __IO uint32_t MBC_DOM1_MEM2_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x13A8, array step: index*0x1000, index2*0x4, valid indices: [0][0-3], [1][0], [2][0] */
         uint8_t RESERVED_10[16];
    __IO uint32_t MBC_DOM1_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x13C8, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_11[4];
    __IO uint32_t MBC_DOM1_MEM3_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x13D0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_12[28];
    __IO uint32_t MBC_DOM1_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x13F0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_13[76];
    __IO uint32_t MBC_DOM2_MEM0_BLK_CFG_W[9];        /**< MBC Memory Block Configuration Word, array offset: 0x1440, array step: index*0x1000, index2*0x4, valid indices: [0][0], [1][0], [2][0-8], [3][0-2] */
         uint8_t RESERVED_14[220];
    __IO uint32_t MBC_DOM2_MEM0_BLK_NSE_W[3];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1540, array step: index*0x1000, index2*0x4, valid indices: [0-3][0], [2][1], [2][2] */
         uint8_t RESERVED_15[52];
    __IO uint32_t MBC_DOM2_MEM1_BLK_CFG_W[6];        /**< MBC Memory Block Configuration Word, array offset: 0x1580, array step: index*0x1000, index2*0x4, valid indices: [0][0-1], [1][0], [2][0-5] */
         uint8_t RESERVED_16[8];
    __IO uint32_t MBC_DOM2_MEM1_BLK_NSE_W[2];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x15A0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1] */
    __IO uint32_t MBC_DOM2_MEM2_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x15A8, array step: index*0x1000, index2*0x4, valid indices: [0][0-3], [1][0], [2][0] */
         uint8_t RESERVED_17[16];
    __IO uint32_t MBC_DOM2_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x15C8, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_18[4];
    __IO uint32_t MBC_DOM2_MEM3_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x15D0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_19[28];
    __IO uint32_t MBC_DOM2_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x15F0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_20[76];
    __IO uint32_t MBC_DOM3_MEM0_BLK_CFG_W[9];        /**< MBC Memory Block Configuration Word, array offset: 0x1640, array step: index*0x1000, index2*0x4, valid indices: [0][0], [1][0], [2][0-8], [3][0-2] */
         uint8_t RESERVED_21[220];
    __IO uint32_t MBC_DOM3_MEM0_BLK_NSE_W[3];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1740, array step: index*0x1000, index2*0x4, valid indices: [0-3][0], [2][1], [2][2] */
         uint8_t RESERVED_22[52];
    __IO uint32_t MBC_DOM3_MEM1_BLK_CFG_W[6];        /**< MBC Memory Block Configuration Word, array offset: 0x1780, array step: index*0x1000, index2*0x4, valid indices: [0][0-1], [1][0], [2][0-5] */
         uint8_t RESERVED_23[8];
    __IO uint32_t MBC_DOM3_MEM1_BLK_NSE_W[2];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x17A0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1] */
    __IO uint32_t MBC_DOM3_MEM2_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x17A8, array step: index*0x1000, index2*0x4, valid indices: [0][0-3], [1][0], [2][0] */
         uint8_t RESERVED_24[16];
    __IO uint32_t MBC_DOM3_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x17C8, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_25[4];
    __IO uint32_t MBC_DOM3_MEM3_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x17D0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_26[28];
    __IO uint32_t MBC_DOM3_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x17F0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_27[76];
    __IO uint32_t MBC_DOM4_MEM0_BLK_CFG_W[9];        /**< MBC Memory Block Configuration Word, array offset: 0x1840, array step: index*0x1000, index2*0x4, valid indices: [0][0], [1][0], [2][0-8], [3][0-2] */
         uint8_t RESERVED_28[220];
    __IO uint32_t MBC_DOM4_MEM0_BLK_NSE_W[3];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1940, array step: index*0x1000, index2*0x4, valid indices: [0-3][0], [2][1], [2][2] */
         uint8_t RESERVED_29[52];
    __IO uint32_t MBC_DOM4_MEM1_BLK_CFG_W[6];        /**< MBC Memory Block Configuration Word, array offset: 0x1980, array step: index*0x1000, index2*0x4, valid indices: [0][0-1], [1][0], [2][0-5] */
         uint8_t RESERVED_30[8];
    __IO uint32_t MBC_DOM4_MEM1_BLK_NSE_W[2];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x19A0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1] */
    __IO uint32_t MBC_DOM4_MEM2_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x19A8, array step: index*0x1000, index2*0x4, valid indices: [0][0-3], [1][0], [2][0] */
         uint8_t RESERVED_31[16];
    __IO uint32_t MBC_DOM4_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x19C8, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_32[4];
    __IO uint32_t MBC_DOM4_MEM3_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x19D0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_33[28];
    __IO uint32_t MBC_DOM4_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x19F0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_34[76];
    __IO uint32_t MBC_DOM5_MEM0_BLK_CFG_W[9];        /**< MBC Memory Block Configuration Word, array offset: 0x1A40, array step: index*0x1000, index2*0x4, valid indices: [0][0], [1][0], [2][0-8], [3][0-2] */
         uint8_t RESERVED_35[220];
    __IO uint32_t MBC_DOM5_MEM0_BLK_NSE_W[3];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1B40, array step: index*0x1000, index2*0x4, valid indices: [0-3][0], [2][1], [2][2] */
         uint8_t RESERVED_36[52];
    __IO uint32_t MBC_DOM5_MEM1_BLK_CFG_W[6];        /**< MBC Memory Block Configuration Word, array offset: 0x1B80, array step: index*0x1000, index2*0x4, valid indices: [0][0-1], [1][0], [2][0-5] */
         uint8_t RESERVED_37[8];
    __IO uint32_t MBC_DOM5_MEM1_BLK_NSE_W[2];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1BA0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1] */
    __IO uint32_t MBC_DOM5_MEM2_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x1BA8, array step: index*0x1000, index2*0x4, valid indices: [0][0-3], [1][0], [2][0] */
         uint8_t RESERVED_38[16];
    __IO uint32_t MBC_DOM5_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1BC8, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_39[4];
    __IO uint32_t MBC_DOM5_MEM3_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x1BD0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_40[28];
    __IO uint32_t MBC_DOM5_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1BF0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_41[76];
    __IO uint32_t MBC_DOM6_MEM0_BLK_CFG_W[9];        /**< MBC Memory Block Configuration Word, array offset: 0x1C40, array step: index*0x1000, index2*0x4, valid indices: [0][0], [1][0], [2][0-8], [3][0-2] */
         uint8_t RESERVED_42[220];
    __IO uint32_t MBC_DOM6_MEM0_BLK_NSE_W[3];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1D40, array step: index*0x1000, index2*0x4, valid indices: [0-3][0], [2][1], [2][2] */
         uint8_t RESERVED_43[52];
    __IO uint32_t MBC_DOM6_MEM1_BLK_CFG_W[6];        /**< MBC Memory Block Configuration Word, array offset: 0x1D80, array step: index*0x1000, index2*0x4, valid indices: [0][0-1], [1][0], [2][0-5] */
         uint8_t RESERVED_44[8];
    __IO uint32_t MBC_DOM6_MEM1_BLK_NSE_W[2];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1DA0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1] */
    __IO uint32_t MBC_DOM6_MEM2_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x1DA8, array step: index*0x1000, index2*0x4, valid indices: [0][0-3], [1][0], [2][0] */
         uint8_t RESERVED_45[16];
    __IO uint32_t MBC_DOM6_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1DC8, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_46[4];
    __IO uint32_t MBC_DOM6_MEM3_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x1DD0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_47[28];
    __IO uint32_t MBC_DOM6_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1DF0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_48[76];
    __IO uint32_t MBC_DOM7_MEM0_BLK_CFG_W[9];        /**< MBC Memory Block Configuration Word, array offset: 0x1E40, array step: index*0x1000, index2*0x4, valid indices: [0][0], [1][0], [2][0-8], [3][0-2] */
         uint8_t RESERVED_49[220];
    __IO uint32_t MBC_DOM7_MEM0_BLK_NSE_W[3];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1F40, array step: index*0x1000, index2*0x4, valid indices: [0-3][0], [2][1], [2][2] */
         uint8_t RESERVED_50[52];
    __IO uint32_t MBC_DOM7_MEM1_BLK_CFG_W[6];        /**< MBC Memory Block Configuration Word, array offset: 0x1F80, array step: index*0x1000, index2*0x4, valid indices: [0][0-1], [1][0], [2][0-5] */
         uint8_t RESERVED_51[8];
    __IO uint32_t MBC_DOM7_MEM1_BLK_NSE_W[2];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1FA0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1] */
    __IO uint32_t MBC_DOM7_MEM2_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x1FA8, array step: index*0x1000, index2*0x4, valid indices: [0][0-3], [1][0], [2][0] */
         uint8_t RESERVED_52[16];
    __IO uint32_t MBC_DOM7_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1FC8, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_53[4];
    __IO uint32_t MBC_DOM7_MEM3_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x1FD0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_54[28];
    __IO uint32_t MBC_DOM7_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1FF0, array step: index*0x1000, index2*0x4, valid indices: [0-2][0] */
         uint8_t RESERVED_55[12];
  } MBC_INDEX[4];
  struct {                                         /* offset: 0x5000, array step: 0x800 */
    __I  uint32_t MRC_GLBCFG;                        /**< MRC Global Configuration Register, array offset: 0x5000, array step: 0x800 */
         uint8_t RESERVED_0[12];
    __IO uint32_t MRC_NSE_RGN_INDIRECT;              /**< MRC NonSecure Enable Region Indirect, array offset: 0x5010, array step: 0x800 */
    __O  uint32_t MRC_NSE_RGN_SET;                   /**< MRC NonSecure Enable Region Set, array offset: 0x5014, array step: 0x800 */
    __O  uint32_t MRC_NSE_RGN_CLR;                   /**< MRC NonSecure Enable Region Clear, array offset: 0x5018, array step: 0x800 */
    __O  uint32_t MRC_NSE_RGN_CLR_ALL;               /**< MRC NonSecure Enable Region Clear All, array offset: 0x501C, array step: 0x800 */
    __IO uint32_t MRC_GLBAC[8];                      /**< MRC Global Access Control, array offset: 0x5020, array step: index*0x800, index2*0x4 */
    __IO uint32_t MRC_DOM0_RGD_W[8][2];              /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x5040, array step: index*0x800, index2*0x8, index3*0x4 */
         uint8_t RESERVED_1[64];
    __IO uint32_t MRC_DOM0_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x50C0, array step: 0x800 */
         uint8_t RESERVED_2[124];
    __IO uint32_t MRC_DOM1_RGD_W[8][2];              /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x5140, array step: index*0x800, index2*0x8, index3*0x4 */
         uint8_t RESERVED_3[64];
    __IO uint32_t MRC_DOM1_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x51C0, array step: 0x800 */
         uint8_t RESERVED_4[124];
    __IO uint32_t MRC_DOM2_RGD_W[8][2];              /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x5240, array step: index*0x800, index2*0x8, index3*0x4 */
         uint8_t RESERVED_5[64];
    __IO uint32_t MRC_DOM2_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x52C0, array step: 0x800 */
         uint8_t RESERVED_6[124];
    __IO uint32_t MRC_DOM3_RGD_W[8][2];              /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x5340, array step: index*0x800, index2*0x8, index3*0x4 */
         uint8_t RESERVED_7[64];
    __IO uint32_t MRC_DOM3_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x53C0, array step: 0x800 */
         uint8_t RESERVED_8[124];
    __IO uint32_t MRC_DOM4_RGD_W[8][2];              /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x5440, array step: index*0x800, index2*0x8, index3*0x4 */
         uint8_t RESERVED_9[64];
    __IO uint32_t MRC_DOM4_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x54C0, array step: 0x800 */
         uint8_t RESERVED_10[124];
    __IO uint32_t MRC_DOM5_RGD_W[8][2];              /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x5540, array step: index*0x800, index2*0x8, index3*0x4 */
         uint8_t RESERVED_11[64];
    __IO uint32_t MRC_DOM5_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x55C0, array step: 0x800 */
         uint8_t RESERVED_12[124];
    __IO uint32_t MRC_DOM6_RGD_W[8][2];              /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x5640, array step: index*0x800, index2*0x8, index3*0x4 */
         uint8_t RESERVED_13[64];
    __IO uint32_t MRC_DOM6_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x56C0, array step: 0x800 */
         uint8_t RESERVED_14[124];
    __IO uint32_t MRC_DOM7_RGD_W[8][2];              /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x5740, array step: index*0x800, index2*0x8, index3*0x4 */
         uint8_t RESERVED_15[64];
    __IO uint32_t MRC_DOM7_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x57C0, array step: 0x800 */
         uint8_t RESERVED_16[60];
  } MRC_INDEX[2];
} TRDC_Type;

/* ----------------------------------------------------------------------------
   -- TRDC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TRDC_Register_Masks TRDC Register Masks
 * @{
 */

/*! @name TRDC_CR - TRDC Register */
/*! @{ */

#define TRDC_TRDC_CR_GVLDM_MASK                  (0x1U)
#define TRDC_TRDC_CR_GVLDM_SHIFT                 (0U)
/*! GVLDM - Global Valid for Domain Assignment Controllers
 *  0b0..TRDC DACs are disabled.
 *  0b1..TRDC DACs are enabled.
 */
#define TRDC_TRDC_CR_GVLDM(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_GVLDM_SHIFT)) & TRDC_TRDC_CR_GVLDM_MASK)

#define TRDC_TRDC_CR_HRL_MASK                    (0x1EU)
#define TRDC_TRDC_CR_HRL_SHIFT                   (1U)
/*! HRL - Hardware Revision Level */
#define TRDC_TRDC_CR_HRL(x)                      (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_HRL_SHIFT)) & TRDC_TRDC_CR_HRL_MASK)

#define TRDC_TRDC_CR_GVLDB_MASK                  (0x4000U)
#define TRDC_TRDC_CR_GVLDB_SHIFT                 (14U)
/*! GVLDB - Global Valid for Memory Block Checkers
 *  0b0..TRDC MBCs are disabled.
 *  0b1..TRDC MBCs are enabled.
 */
#define TRDC_TRDC_CR_GVLDB(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_GVLDB_SHIFT)) & TRDC_TRDC_CR_GVLDB_MASK)

#define TRDC_TRDC_CR_GVLDR_MASK                  (0x8000U)
#define TRDC_TRDC_CR_GVLDR_SHIFT                 (15U)
/*! GVLDR - Global Valid for Memory Region Checkers
 *  0b0..TRDC MRCs are disabled.
 *  0b1..TRDC MRCs are enabled.
 */
#define TRDC_TRDC_CR_GVLDR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_GVLDR_SHIFT)) & TRDC_TRDC_CR_GVLDR_MASK)

#define TRDC_TRDC_CR_LK1_MASK                    (0x40000000U)
#define TRDC_TRDC_CR_LK1_SHIFT                   (30U)
/*! LK1 - Lock Status
 *  0b0..The CR can be written by any secure privileged write.
 *  0b1..The CR is locked (read-only) until the next reset.
 */
#define TRDC_TRDC_CR_LK1(x)                      (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_LK1_SHIFT)) & TRDC_TRDC_CR_LK1_MASK)
/*! @} */

/*! @name TRDC_HWCFG0 - Hardware Configuration Register 0 */
/*! @{ */

#define TRDC_TRDC_HWCFG0_NDID_MASK               (0xFU)
#define TRDC_TRDC_HWCFG0_NDID_SHIFT              (0U)
/*! NDID - Number of domains */
#define TRDC_TRDC_HWCFG0_NDID(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NDID_SHIFT)) & TRDC_TRDC_HWCFG0_NDID_MASK)

#define TRDC_TRDC_HWCFG0_NMSTR_MASK              (0xFF00U)
#define TRDC_TRDC_HWCFG0_NMSTR_SHIFT             (8U)
/*! NMSTR - Number of bus masters */
#define TRDC_TRDC_HWCFG0_NMSTR(x)                (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NMSTR_SHIFT)) & TRDC_TRDC_HWCFG0_NMSTR_MASK)

#define TRDC_TRDC_HWCFG0_NMBC_MASK               (0x70000U)
#define TRDC_TRDC_HWCFG0_NMBC_SHIFT              (16U)
/*! NMBC - Number of MBCs */
#define TRDC_TRDC_HWCFG0_NMBC(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NMBC_SHIFT)) & TRDC_TRDC_HWCFG0_NMBC_MASK)

#define TRDC_TRDC_HWCFG0_NMRC_MASK               (0xF000000U)
#define TRDC_TRDC_HWCFG0_NMRC_SHIFT              (24U)
/*! NMRC - Number of MRCs */
#define TRDC_TRDC_HWCFG0_NMRC(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NMRC_SHIFT)) & TRDC_TRDC_HWCFG0_NMRC_MASK)

#define TRDC_TRDC_HWCFG0_MID_MASK                (0xF0000000U)
#define TRDC_TRDC_HWCFG0_MID_SHIFT               (28U)
/*! MID - Module ID */
#define TRDC_TRDC_HWCFG0_MID(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_MID_SHIFT)) & TRDC_TRDC_HWCFG0_MID_MASK)
/*! @} */

/*! @name TRDC_HWCFG1 - TRDC Hardware Configuration Register 1 */
/*! @{ */

#define TRDC_TRDC_HWCFG1_DID_MASK                (0x7U)
#define TRDC_TRDC_HWCFG1_DID_SHIFT               (0U)
/*! DID - Domain identifier number */
#define TRDC_TRDC_HWCFG1_DID(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG1_DID_SHIFT)) & TRDC_TRDC_HWCFG1_DID_MASK)
/*! @} */

/*! @name DACFG - Domain Assignment Configuration Register */
/*! @{ */

#define TRDC_DACFG_NMDAR_MASK                    (0xFU)
#define TRDC_DACFG_NMDAR_SHIFT                   (0U)
/*! NMDAR - Number of master domain assignment registers for bus master m */
#define TRDC_DACFG_NMDAR(x)                      (((uint8_t)(((uint8_t)(x)) << TRDC_DACFG_NMDAR_SHIFT)) & TRDC_DACFG_NMDAR_MASK)

#define TRDC_DACFG_NCM_MASK                      (0x80U)
#define TRDC_DACFG_NCM_SHIFT                     (7U)
/*! NCM - Non-CPU Master
 *  0b0..Bus master is a processor.
 *  0b1..Bus master is a non-processor.
 */
#define TRDC_DACFG_NCM(x)                        (((uint8_t)(((uint8_t)(x)) << TRDC_DACFG_NCM_SHIFT)) & TRDC_DACFG_NCM_MASK)
/*! @} */

/* The count of TRDC_DACFG */
#define TRDC_DACFG_COUNT                         (8U)

/*! @name CFG - Memory Block Configuration Register */
/*! @{ */

#define TRDC_CFG_SLV0_NMBLK_MASK                 (0x3FFU)
#define TRDC_CFG_SLV0_NMBLK_SHIFT                (0U)
/*! SLV0_NMBLK - Number of blocks in slave 0. */
#define TRDC_CFG_SLV0_NMBLK(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV0_NMBLK_SHIFT)) & TRDC_CFG_SLV0_NMBLK_MASK)

#define TRDC_CFG_SLV2_NMBLK_MASK                 (0x3FFU)
#define TRDC_CFG_SLV2_NMBLK_SHIFT                (0U)
/*! SLV2_NMBLK - Number of blocks in slave 2. */
#define TRDC_CFG_SLV2_NMBLK(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV2_NMBLK_SHIFT)) & TRDC_CFG_SLV2_NMBLK_MASK)

#define TRDC_CFG_SLV0_BLKSZL2_MASK               (0x7C00U)
#define TRDC_CFG_SLV0_BLKSZL2_SHIFT              (10U)
/*! SLV0_BLKSZL2 - Block size log2 in slave 0. */
#define TRDC_CFG_SLV0_BLKSZL2(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV0_BLKSZL2_SHIFT)) & TRDC_CFG_SLV0_BLKSZL2_MASK)

#define TRDC_CFG_SLV2_BLKSZL2_MASK               (0x7C00U)
#define TRDC_CFG_SLV2_BLKSZL2_SHIFT              (10U)
/*! SLV2_BLKSZL2 - Block size log2 in slave 2. */
#define TRDC_CFG_SLV2_BLKSZL2(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV2_BLKSZL2_SHIFT)) & TRDC_CFG_SLV2_BLKSZL2_MASK)

#define TRDC_CFG_SLV1_NMBLK_MASK                 (0x3FF0000U)
#define TRDC_CFG_SLV1_NMBLK_SHIFT                (16U)
/*! SLV1_NMBLK - Number of blocks in slave 1. */
#define TRDC_CFG_SLV1_NMBLK(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV1_NMBLK_SHIFT)) & TRDC_CFG_SLV1_NMBLK_MASK)

#define TRDC_CFG_SLV3_NMBLK_MASK                 (0x3FF0000U)
#define TRDC_CFG_SLV3_NMBLK_SHIFT                (16U)
/*! SLV3_NMBLK - Number of blocks in slave 3. */
#define TRDC_CFG_SLV3_NMBLK(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV3_NMBLK_SHIFT)) & TRDC_CFG_SLV3_NMBLK_MASK)

#define TRDC_CFG_SLV1_BLKSZL2_MASK               (0x7C000000U)
#define TRDC_CFG_SLV1_BLKSZL2_SHIFT              (26U)
/*! SLV1_BLKSZL2 - Block size log2 in slave 1. */
#define TRDC_CFG_SLV1_BLKSZL2(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV1_BLKSZL2_SHIFT)) & TRDC_CFG_SLV1_BLKSZL2_MASK)

#define TRDC_CFG_SLV3_BLKSZL2_MASK               (0x7C000000U)
#define TRDC_CFG_SLV3_BLKSZL2_SHIFT              (26U)
/*! SLV3_BLKSZL2 - Block size log2 in slave 3. */
#define TRDC_CFG_SLV3_BLKSZL2(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV3_BLKSZL2_SHIFT)) & TRDC_CFG_SLV3_BLKSZL2_MASK)
/*! @} */

/* The count of TRDC_CFG */
#define TRDC_CFG_COUNT                           (4U)

/* The count of TRDC_CFG */
#define TRDC_CFG_COUNT2                          (2U)

/*! @name MRCFG - Memory Region Configuration Register */
/*! @{ */

#define TRDC_MRCFG_NMRGD_MASK                    (0x1FU)
#define TRDC_MRCFG_NMRGD_SHIFT                   (0U)
/*! NMRGD - Number of memory region descriptors for memory region checker n */
#define TRDC_MRCFG_NMRGD(x)                      (((uint8_t)(((uint8_t)(x)) << TRDC_MRCFG_NMRGD_SHIFT)) & TRDC_MRCFG_NMRGD_MASK)
/*! @} */

/* The count of TRDC_MRCFG */
#define TRDC_MRCFG_COUNT                         (8U)

/*! @name TRDC_IDAU_CR - TRDC IDAU Control Register */
/*! @{ */

#define TRDC_TRDC_IDAU_CR_VLD_MASK               (0x1U)
#define TRDC_TRDC_IDAU_CR_VLD_SHIFT              (0U)
/*! VLD - Valid */
#define TRDC_TRDC_IDAU_CR_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_VLD_SHIFT)) & TRDC_TRDC_IDAU_CR_VLD_MASK)

#define TRDC_TRDC_IDAU_CR_CFGSECEXT_MASK         (0x8U)
#define TRDC_TRDC_IDAU_CR_CFGSECEXT_SHIFT        (3U)
/*! CFGSECEXT - Configure Security Extension
 *  0b0..ARMv8M Security Extension is disabled
 *  0b1..ARMv8-M Security Extension is enabled
 */
#define TRDC_TRDC_IDAU_CR_CFGSECEXT(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_CFGSECEXT_SHIFT)) & TRDC_TRDC_IDAU_CR_CFGSECEXT_MASK)

#define TRDC_TRDC_IDAU_CR_MPUSDIS_MASK           (0x10U)
#define TRDC_TRDC_IDAU_CR_MPUSDIS_SHIFT          (4U)
/*! MPUSDIS - Secure Memory Protection Unit Disabled
 *  0b0..Secure MPU is enabled
 *  0b1..Secure MPU is disabled
 */
#define TRDC_TRDC_IDAU_CR_MPUSDIS(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_MPUSDIS_SHIFT)) & TRDC_TRDC_IDAU_CR_MPUSDIS_MASK)

#define TRDC_TRDC_IDAU_CR_MPUNSDIS_MASK          (0x20U)
#define TRDC_TRDC_IDAU_CR_MPUNSDIS_SHIFT         (5U)
/*! MPUNSDIS - NonSecure Memory Protection Unit Disabled
 *  0b0..Nonsecure MPU is enabled
 *  0b1..Nonsecure MPU is disabled
 */
#define TRDC_TRDC_IDAU_CR_MPUNSDIS(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_MPUNSDIS_SHIFT)) & TRDC_TRDC_IDAU_CR_MPUNSDIS_MASK)

#define TRDC_TRDC_IDAU_CR_SAUDIS_MASK            (0x40U)
#define TRDC_TRDC_IDAU_CR_SAUDIS_SHIFT           (6U)
/*! SAUDIS - Security Attribution Unit Disable
 *  0b0..SAU is enabled
 *  0b1..SAU is disabled
 */
#define TRDC_TRDC_IDAU_CR_SAUDIS(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_SAUDIS_SHIFT)) & TRDC_TRDC_IDAU_CR_SAUDIS_MASK)

#define TRDC_TRDC_IDAU_CR_LKSVTAIRCR_MASK        (0x100U)
#define TRDC_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT       (8U)
/*! LKSVTAIRCR - Lock Secure VTOR, Application interrupt and Reset Control Registers
 *  0b0..Unlock these registers
 *  0b1..Disable writes to the VTOR_S, AIRCR[PRIS], and AIRCR[BFHFNMINS] registers
 */
#define TRDC_TRDC_IDAU_CR_LKSVTAIRCR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT)) & TRDC_TRDC_IDAU_CR_LKSVTAIRCR_MASK)

#define TRDC_TRDC_IDAU_CR_LKNSVTOR_MASK          (0x200U)
#define TRDC_TRDC_IDAU_CR_LKNSVTOR_SHIFT         (9U)
/*! LKNSVTOR - Lock Nonsecure Vector Table Offset Register
 *  0b0..Unlock this register
 *  0b1..Disable writes to the VTOR_NS register
 */
#define TRDC_TRDC_IDAU_CR_LKNSVTOR(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKNSVTOR_SHIFT)) & TRDC_TRDC_IDAU_CR_LKNSVTOR_MASK)

#define TRDC_TRDC_IDAU_CR_LKSMPU_MASK            (0x400U)
#define TRDC_TRDC_IDAU_CR_LKSMPU_SHIFT           (10U)
/*! LKSMPU - Lock Secure MPU
 *  0b0..Unlock these registers
 *  0b1..Disable writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or
 *       from a debug agent connected to the processor in Secure state
 */
#define TRDC_TRDC_IDAU_CR_LKSMPU(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKSMPU_SHIFT)) & TRDC_TRDC_IDAU_CR_LKSMPU_MASK)

#define TRDC_TRDC_IDAU_CR_LKNSMPU_MASK           (0x800U)
#define TRDC_TRDC_IDAU_CR_LKNSMPU_SHIFT          (11U)
/*! LKNSMPU - Lock Nonsecure MPU
 *  0b0..Unlock these registers
 *  0b1..Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and
 *       MPU_RLAR_A_NSn from software or from a debug agent connected to the processor
 */
#define TRDC_TRDC_IDAU_CR_LKNSMPU(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKNSMPU_SHIFT)) & TRDC_TRDC_IDAU_CR_LKNSMPU_MASK)

#define TRDC_TRDC_IDAU_CR_LKSAU_MASK             (0x1000U)
#define TRDC_TRDC_IDAU_CR_LKSAU_SHIFT            (12U)
/*! LKSAU - Lock SAU
 *  0b0..Unlock these registers
 *  0b1..Disable writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor
 */
#define TRDC_TRDC_IDAU_CR_LKSAU(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKSAU_SHIFT)) & TRDC_TRDC_IDAU_CR_LKSAU_MASK)

#define TRDC_TRDC_IDAU_CR_PCURRNS_MASK           (0x80000000U)
#define TRDC_TRDC_IDAU_CR_PCURRNS_SHIFT          (31U)
/*! PCURRNS - Processor current security
 *  0b0..Processor is in Secure state
 *  0b1..Processor is in Nonsecure state
 */
#define TRDC_TRDC_IDAU_CR_PCURRNS(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_PCURRNS_SHIFT)) & TRDC_TRDC_IDAU_CR_PCURRNS_MASK)
/*! @} */

/*! @name TRDC_FLW_CTL - TRDC FLW Control */
/*! @{ */

#define TRDC_TRDC_FLW_CTL_LK_MASK                (0x40000000U)
#define TRDC_TRDC_FLW_CTL_LK_SHIFT               (30U)
/*! LK - Lock bit
 *  0b0..FLW register may be modified.
 *  0b1..FLW registers are locked until the next reset.
 */
#define TRDC_TRDC_FLW_CTL_LK(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_CTL_LK_SHIFT)) & TRDC_TRDC_FLW_CTL_LK_MASK)

#define TRDC_TRDC_FLW_CTL_V_MASK                 (0x80000000U)
#define TRDC_TRDC_FLW_CTL_V_SHIFT                (31U)
/*! V - Valid bit
 *  0b0..FLW function is disabled.
 *  0b1..FLW function is enabled.
 */
#define TRDC_TRDC_FLW_CTL_V(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_CTL_V_SHIFT)) & TRDC_TRDC_FLW_CTL_V_MASK)
/*! @} */

/*! @name TRDC_FLW_PBASE - TRDC FLW Physical Base */
/*! @{ */

#define TRDC_TRDC_FLW_PBASE_PBASE_MASK           (0xFFFFFFFFU)
#define TRDC_TRDC_FLW_PBASE_PBASE_SHIFT          (0U)
/*! PBASE - Physical base address */
#define TRDC_TRDC_FLW_PBASE_PBASE(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_PBASE_PBASE_SHIFT)) & TRDC_TRDC_FLW_PBASE_PBASE_MASK)
/*! @} */

/*! @name TRDC_FLW_ABASE - TRDC FLW Array Base */
/*! @{ */

#define TRDC_TRDC_FLW_ABASE_ABASE_L_MASK         (0x3F8000U)
#define TRDC_TRDC_FLW_ABASE_ABASE_L_SHIFT        (15U)
/*! ABASE_L - Array base address low */
#define TRDC_TRDC_FLW_ABASE_ABASE_L(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_ABASE_ABASE_L_SHIFT)) & TRDC_TRDC_FLW_ABASE_ABASE_L_MASK)

#define TRDC_TRDC_FLW_ABASE_ABASE_H_MASK         (0xFFC00000U)
#define TRDC_TRDC_FLW_ABASE_ABASE_H_SHIFT        (22U)
/*! ABASE_H - Array base address high */
#define TRDC_TRDC_FLW_ABASE_ABASE_H(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_ABASE_ABASE_H_SHIFT)) & TRDC_TRDC_FLW_ABASE_ABASE_H_MASK)
/*! @} */

/*! @name TRDC_FLW_BCNT - TRDC FLW Block Count */
/*! @{ */

#define TRDC_TRDC_FLW_BCNT_BCNT_MASK             (0x7FFFU)
#define TRDC_TRDC_FLW_BCNT_BCNT_SHIFT            (0U)
/*! BCNT - Block Count */
#define TRDC_TRDC_FLW_BCNT_BCNT(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_BCNT_BCNT_SHIFT)) & TRDC_TRDC_FLW_BCNT_BCNT_MASK)
/*! @} */

/*! @name TRDC_FDID - TRDC Fault Domain ID */
/*! @{ */

#define TRDC_TRDC_FDID_FDID_MASK                 (0xFU)
#define TRDC_TRDC_FDID_FDID_SHIFT                (0U)
/*! FDID - Domain ID of Faulted Access */
#define TRDC_TRDC_FDID_FDID(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FDID_FDID_SHIFT)) & TRDC_TRDC_FDID_FDID_MASK)
/*! @} */

/*! @name TRDC_DERRLOC - TRDC Domain Error Location Register */
/*! @{ */

#define TRDC_TRDC_DERRLOC_mbc0_err_slv_MASK      (0xFU)
#define TRDC_TRDC_DERRLOC_mbc0_err_slv_SHIFT     (0U)
/*! mbc0_err_slv - MBC0 ERROR SLAVE */
#define TRDC_TRDC_DERRLOC_mbc0_err_slv(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_DERRLOC_mbc0_err_slv_SHIFT)) & TRDC_TRDC_DERRLOC_mbc0_err_slv_MASK)

#define TRDC_TRDC_DERRLOC_mbc1_err_slv_MASK      (0xF0U)
#define TRDC_TRDC_DERRLOC_mbc1_err_slv_SHIFT     (4U)
/*! mbc1_err_slv - MBC1 ERROR SLAVE */
#define TRDC_TRDC_DERRLOC_mbc1_err_slv(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_DERRLOC_mbc1_err_slv_SHIFT)) & TRDC_TRDC_DERRLOC_mbc1_err_slv_MASK)

#define TRDC_TRDC_DERRLOC_mbc2_err_slv_MASK      (0xF00U)
#define TRDC_TRDC_DERRLOC_mbc2_err_slv_SHIFT     (8U)
/*! mbc2_err_slv - MBC2 ERROR SLAVE */
#define TRDC_TRDC_DERRLOC_mbc2_err_slv(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_DERRLOC_mbc2_err_slv_SHIFT)) & TRDC_TRDC_DERRLOC_mbc2_err_slv_MASK)

#define TRDC_TRDC_DERRLOC_mbc3_err_slv_MASK      (0xF000U)
#define TRDC_TRDC_DERRLOC_mbc3_err_slv_SHIFT     (12U)
/*! mbc3_err_slv - MBC3 ERROR SLAVE */
#define TRDC_TRDC_DERRLOC_mbc3_err_slv(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_DERRLOC_mbc3_err_slv_SHIFT)) & TRDC_TRDC_DERRLOC_mbc3_err_slv_MASK)

#define TRDC_TRDC_DERRLOC_MRCINST_MASK           (0xFF0000U)
#define TRDC_TRDC_DERRLOC_MRCINST_SHIFT          (16U)
/*! MRCINST - MRC instance */
#define TRDC_TRDC_DERRLOC_MRCINST(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_DERRLOC_MRCINST_SHIFT)) & TRDC_TRDC_DERRLOC_MRCINST_MASK)
/*! @} */

/* The count of TRDC_TRDC_DERRLOC */
#define TRDC_TRDC_DERRLOC_COUNT                  (8U)

/*! @name W0 - MBC Domain Error Word0 Register */
/*! @{ */

#define TRDC_W0_EADDR_MASK                       (0xFFFFFFFFU)
#define TRDC_W0_EADDR_SHIFT                      (0U)
/*! EADDR - Error address */
#define TRDC_W0_EADDR(x)                         (((uint32_t)(((uint32_t)(x)) << TRDC_W0_EADDR_SHIFT)) & TRDC_W0_EADDR_MASK)
/*! @} */

/* The count of TRDC_W0 */
#define TRDC_W0_COUNT                            (4U)

/*! @name W1 - MBC Domain Error Word1 Register */
/*! @{ */

#define TRDC_W1_EDID_MASK                        (0xFU)
#define TRDC_W1_EDID_SHIFT                       (0U)
/*! EDID - Error domain identifier */
#define TRDC_W1_EDID(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EDID_SHIFT)) & TRDC_W1_EDID_MASK)

#define TRDC_W1_EATR_MASK                        (0x700U)
#define TRDC_W1_EATR_SHIFT                       (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define TRDC_W1_EATR(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EATR_SHIFT)) & TRDC_W1_EATR_MASK)

#define TRDC_W1_ERW_MASK                         (0x800U)
#define TRDC_W1_ERW_SHIFT                        (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define TRDC_W1_ERW(x)                           (((uint32_t)(((uint32_t)(x)) << TRDC_W1_ERW_SHIFT)) & TRDC_W1_ERW_MASK)

#define TRDC_W1_EPORT_MASK                       (0x7000000U)
#define TRDC_W1_EPORT_SHIFT                      (24U)
/*! EPORT - Error port
 *  0b000..mbcxslv0
 *  0b001..mbcxslv1
 *  0b010..mbcxslv2
 *  0b011..mbcxslv3
 */
#define TRDC_W1_EPORT(x)                         (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EPORT_SHIFT)) & TRDC_W1_EPORT_MASK)

#define TRDC_W1_EST_MASK                         (0xC0000000U)
#define TRDC_W1_EST_SHIFT                        (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define TRDC_W1_EST(x)                           (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EST_SHIFT)) & TRDC_W1_EST_MASK)
/*! @} */

/* The count of TRDC_W1 */
#define TRDC_W1_COUNT                            (4U)

/*! @name W3 - MBC Domain Error Word3 Register */
/*! @{ */

#define TRDC_W3_RECR_MASK                        (0xC0000000U)
#define TRDC_W3_RECR_SHIFT                       (30U)
/*! RECR - Rearm Error Capture Registers */
#define TRDC_W3_RECR(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W3_RECR_SHIFT)) & TRDC_W3_RECR_MASK)
/*! @} */

/* The count of TRDC_W3 */
#define TRDC_W3_COUNT                            (4U)

/*! @name W0 - MRC Domain Error Word0 Register */
/*! @{ */

#define TRDC_W0_EADDR_MASK                       (0xFFFFFFFFU)
#define TRDC_W0_EADDR_SHIFT                      (0U)
/*! EADDR - Error address */
#define TRDC_W0_EADDR(x)                         (((uint32_t)(((uint32_t)(x)) << TRDC_W0_EADDR_SHIFT)) & TRDC_W0_EADDR_MASK)
/*! @} */

/* The count of TRDC_W0 */
#define TRDC_MRC_DERR_W0_COUNT                   (2U)

/*! @name W1 - MRC Domain Error Word1 Register */
/*! @{ */

#define TRDC_W1_EDID_MASK                        (0xFU)
#define TRDC_W1_EDID_SHIFT                       (0U)
/*! EDID - Error domain identifier */
#define TRDC_W1_EDID(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EDID_SHIFT)) & TRDC_W1_EDID_MASK)

#define TRDC_W1_EATR_MASK                        (0x700U)
#define TRDC_W1_EATR_SHIFT                       (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define TRDC_W1_EATR(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EATR_SHIFT)) & TRDC_W1_EATR_MASK)

#define TRDC_W1_ERW_MASK                         (0x800U)
#define TRDC_W1_ERW_SHIFT                        (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define TRDC_W1_ERW(x)                           (((uint32_t)(((uint32_t)(x)) << TRDC_W1_ERW_SHIFT)) & TRDC_W1_ERW_MASK)

#define TRDC_W1_EPORT_MASK                       (0x7000000U)
#define TRDC_W1_EPORT_SHIFT                      (24U)
/*! EPORT - Error port */
#define TRDC_W1_EPORT(x)                         (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EPORT_SHIFT)) & TRDC_W1_EPORT_MASK)

#define TRDC_W1_EST_MASK                         (0xC0000000U)
#define TRDC_W1_EST_SHIFT                        (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define TRDC_W1_EST(x)                           (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EST_SHIFT)) & TRDC_W1_EST_MASK)
/*! @} */

/* The count of TRDC_W1 */
#define TRDC_MRC_DERR_W1_COUNT                   (2U)

/*! @name W3 - MRC Domain Error Word3 Register */
/*! @{ */

#define TRDC_W3_RECR_MASK                        (0xC0000000U)
#define TRDC_W3_RECR_SHIFT                       (30U)
/*! RECR - Rearm Error Capture Registers */
#define TRDC_W3_RECR(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W3_RECR_SHIFT)) & TRDC_W3_RECR_MASK)
/*! @} */

/* The count of TRDC_W3 */
#define TRDC_MRC_DERR_W3_COUNT                   (2U)

/*! @name MDA_W0_0_DFMT0 - DAC Master Domain Assignment Register */
/*! @{ */

#define TRDC_MDA_W0_0_DFMT0_DID_MASK             (0xFU)
#define TRDC_MDA_W0_0_DFMT0_DID_SHIFT            (0U)
/*! DID - Domain identifier */
#define TRDC_MDA_W0_0_DFMT0_DID(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_DID_SHIFT)) & TRDC_MDA_W0_0_DFMT0_DID_MASK)

#define TRDC_MDA_W0_0_DFMT0_DIDS_MASK            (0x30U)
#define TRDC_MDA_W0_0_DFMT0_DIDS_SHIFT           (4U)
/*! DIDS - DID Select
 *  0b00..Use MDAm[3:0] as the domain identifier.
 *  0b01..Use the input DID as the domain identifier.
 *  0b10..Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier.
 *  0b11..Reserved for future use.
 */
#define TRDC_MDA_W0_0_DFMT0_DIDS(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_DIDS_SHIFT)) & TRDC_MDA_W0_0_DFMT0_DIDS_MASK)

#define TRDC_MDA_W0_0_DFMT0_SA_MASK              (0xC000U)
#define TRDC_MDA_W0_0_DFMT0_SA_SHIFT             (14U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define TRDC_MDA_W0_0_DFMT0_SA(x)                (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_SA_SHIFT)) & TRDC_MDA_W0_0_DFMT0_SA_MASK)

#define TRDC_MDA_W0_0_DFMT0_DFMT_MASK            (0x20000000U)
#define TRDC_MDA_W0_0_DFMT0_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define TRDC_MDA_W0_0_DFMT0_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_DFMT_SHIFT)) & TRDC_MDA_W0_0_DFMT0_DFMT_MASK)

#define TRDC_MDA_W0_0_DFMT0_LK1_MASK             (0x40000000U)
#define TRDC_MDA_W0_0_DFMT0_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define TRDC_MDA_W0_0_DFMT0_LK1(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_LK1_SHIFT)) & TRDC_MDA_W0_0_DFMT0_LK1_MASK)

#define TRDC_MDA_W0_0_DFMT0_VLD_MASK             (0x80000000U)
#define TRDC_MDA_W0_0_DFMT0_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define TRDC_MDA_W0_0_DFMT0_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_VLD_SHIFT)) & TRDC_MDA_W0_0_DFMT0_VLD_MASK)
/*! @} */

/*! @name MDA_W0_x_DFMT1 - DAC Master Domain Assignment Register */
/*! @{ */

#define TRDC_MDA_W0_x_DFMT1_DID_MASK             (0xFU)
#define TRDC_MDA_W0_x_DFMT1_DID_SHIFT            (0U)
/*! DID - Domain identifier */
#define TRDC_MDA_W0_x_DFMT1_DID(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_DID_SHIFT)) & TRDC_MDA_W0_x_DFMT1_DID_MASK)

#define TRDC_MDA_W0_x_DFMT1_PA_MASK              (0x30U)
#define TRDC_MDA_W0_x_DFMT1_PA_SHIFT             (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define TRDC_MDA_W0_x_DFMT1_PA(x)                (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_PA_SHIFT)) & TRDC_MDA_W0_x_DFMT1_PA_MASK)

#define TRDC_MDA_W0_x_DFMT1_SA_MASK              (0xC0U)
#define TRDC_MDA_W0_x_DFMT1_SA_SHIFT             (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define TRDC_MDA_W0_x_DFMT1_SA(x)                (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_SA_SHIFT)) & TRDC_MDA_W0_x_DFMT1_SA_MASK)

#define TRDC_MDA_W0_x_DFMT1_DIDB_MASK            (0x100U)
#define TRDC_MDA_W0_x_DFMT1_DIDB_SHIFT           (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define TRDC_MDA_W0_x_DFMT1_DIDB(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_DIDB_SHIFT)) & TRDC_MDA_W0_x_DFMT1_DIDB_MASK)

#define TRDC_MDA_W0_x_DFMT1_DFMT_MASK            (0x20000000U)
#define TRDC_MDA_W0_x_DFMT1_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define TRDC_MDA_W0_x_DFMT1_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_DFMT_SHIFT)) & TRDC_MDA_W0_x_DFMT1_DFMT_MASK)

#define TRDC_MDA_W0_x_DFMT1_LK1_MASK             (0x40000000U)
#define TRDC_MDA_W0_x_DFMT1_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define TRDC_MDA_W0_x_DFMT1_LK1(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_LK1_SHIFT)) & TRDC_MDA_W0_x_DFMT1_LK1_MASK)

#define TRDC_MDA_W0_x_DFMT1_VLD_MASK             (0x80000000U)
#define TRDC_MDA_W0_x_DFMT1_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define TRDC_MDA_W0_x_DFMT1_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_VLD_SHIFT)) & TRDC_MDA_W0_x_DFMT1_VLD_MASK)
/*! @} */

/* The count of TRDC_MDA_W0_x_DFMT1 */
#define TRDC_MDA_W0_x_DFMT1_COUNT                (7U)

/*! @name MBC_MEM_GLBCFG - MBC Global Configuration Register */
/*! @{ */

#define TRDC_MBC_MEM_GLBCFG_NBLKS_MASK           (0x3FFU)
#define TRDC_MBC_MEM_GLBCFG_NBLKS_SHIFT          (0U)
/*! NBLKS - Number of blocks in this memory */
#define TRDC_MBC_MEM_GLBCFG_NBLKS(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_MEM_GLBCFG_NBLKS_MASK)

#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK       (0x1F0000U)
#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT      (16U)
/*! SIZE_LOG2 - Log2 size per block */
#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK)
/*! @} */

/* The count of TRDC_MBC_MEM_GLBCFG */
#define TRDC_MBC_MEM_GLBCFG_COUNT                (4U)

/* The count of TRDC_MBC_MEM_GLBCFG */
#define TRDC_MBC_MEM_GLBCFG_COUNT2               (4U)

/*! @name MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */
/*! @{ */

#define TRDC_MBC_NSE_BLK_INDEX_WNDX_MASK         (0x3CU)
#define TRDC_MBC_NSE_BLK_INDEX_WNDX_SHIFT        (2U)
/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */
#define TRDC_MBC_NSE_BLK_INDEX_WNDX(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_WNDX_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_MEM_SEL_MASK      (0xF00U)
#define TRDC_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT     (8U)
/*! MEM_SEL - Memory Select */
#define TRDC_MBC_NSE_BLK_INDEX_MEM_SEL(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_MEM_SEL_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL0_MASK     (0x10000U)
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT    (16U)
/*! DID_SEL0 - DID Select
 *  0b0..No effect.
 *  0b1..Selects NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL0(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL0_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL1_MASK     (0x20000U)
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT    (17U)
/*! DID_SEL1 - DID Select
 *  0b0..No effect.
 *  0b1..Selects NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL1(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL1_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL2_MASK     (0x40000U)
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT    (18U)
/*! DID_SEL2 - DID Select
 *  0b0..No effect.
 *  0b1..Selects NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL2(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL2_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL3_MASK     (0x80000U)
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL3_SHIFT    (19U)
/*! DID_SEL3 - DID Select
 *  0b0..No effect.
 *  0b1..Selects NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL3(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL3_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL3_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL4_MASK     (0x100000U)
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL4_SHIFT    (20U)
/*! DID_SEL4 - DID Select
 *  0b0..No effect.
 *  0b1..Selects NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL4(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL4_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL4_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL5_MASK     (0x200000U)
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL5_SHIFT    (21U)
/*! DID_SEL5 - DID Select
 *  0b0..No effect.
 *  0b1..Selects NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL5(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL5_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL5_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL6_MASK     (0x400000U)
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL6_SHIFT    (22U)
/*! DID_SEL6 - DID Select
 *  0b0..No effect.
 *  0b1..Selects NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL6(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL6_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL6_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL7_MASK     (0x800000U)
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL7_SHIFT    (23U)
/*! DID_SEL7 - DID Select
 *  0b0..No effect.
 *  0b1..Selects NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL7(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL7_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL7_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_AI_MASK           (0x80000000U)
#define TRDC_MBC_NSE_BLK_INDEX_AI_SHIFT          (31U)
/*! AI - Auto Increment
 *  0b0..No effect.
 *  0b1..Add 1 to the WNDX field after the register write.
 */
#define TRDC_MBC_NSE_BLK_INDEX_AI(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_AI_MASK)
/*! @} */

/* The count of TRDC_MBC_NSE_BLK_INDEX */
#define TRDC_MBC_NSE_BLK_INDEX_COUNT             (4U)

/*! @name MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */
/*! @{ */

#define TRDC_MBC_NSE_BLK_SET_W1SET_MASK          (0xFFFFFFFFU)
#define TRDC_MBC_NSE_BLK_SET_W1SET_SHIFT         (0U)
/*! W1SET - Write-1 Set */
#define TRDC_MBC_NSE_BLK_SET_W1SET(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC_NSE_BLK_SET_W1SET_MASK)
/*! @} */

/* The count of TRDC_MBC_NSE_BLK_SET */
#define TRDC_MBC_NSE_BLK_SET_COUNT               (4U)

/*! @name MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */
/*! @{ */

#define TRDC_MBC_NSE_BLK_CLR_W1CLR_MASK          (0xFFFFFFFFU)
#define TRDC_MBC_NSE_BLK_CLR_W1CLR_SHIFT         (0U)
/*! W1CLR - Write-1 Clear */
#define TRDC_MBC_NSE_BLK_CLR_W1CLR(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_W1CLR_MASK)
/*! @} */

/* The count of TRDC_MBC_NSE_BLK_CLR */
#define TRDC_MBC_NSE_BLK_CLR_COUNT               (4U)

/*! @name MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */
/*! @{ */

#define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK     (0xF00U)
#define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT    (8U)
/*! MEMSEL - Memory Select */
#define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK)

#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK   (0x10000U)
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT  (16U)
/*! DID_SEL0 - DID Select
 *  0b0..No effect.
 *  0b1..Clear all NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK)

#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL1_MASK   (0x20000U)
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL1_SHIFT  (17U)
/*! DID_SEL1 - DID Select
 *  0b0..No effect.
 *  0b1..Clear all NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL1_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL1_MASK)

#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL2_MASK   (0x40000U)
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL2_SHIFT  (18U)
/*! DID_SEL2 - DID Select
 *  0b0..No effect.
 *  0b1..Clear all NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL2_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL2_MASK)

#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL3_MASK   (0x80000U)
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL3_SHIFT  (19U)
/*! DID_SEL3 - DID Select
 *  0b0..No effect.
 *  0b1..Clear all NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL3_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL3_MASK)

#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL4_MASK   (0x100000U)
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL4_SHIFT  (20U)
/*! DID_SEL4 - DID Select
 *  0b0..No effect.
 *  0b1..Clear all NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL4_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL4_MASK)

#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL5_MASK   (0x200000U)
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL5_SHIFT  (21U)
/*! DID_SEL5 - DID Select
 *  0b0..No effect.
 *  0b1..Clear all NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL5_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL5_MASK)

#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL6_MASK   (0x400000U)
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL6_SHIFT  (22U)
/*! DID_SEL6 - DID Select
 *  0b0..No effect.
 *  0b1..Clear all NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL6_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL6_MASK)

#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL7_MASK   (0x800000U)
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL7_SHIFT  (23U)
/*! DID_SEL7 - DID Select
 *  0b0..No effect.
 *  0b1..Clear all NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL7_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL7_MASK)
/*! @} */

/* The count of TRDC_MBC_NSE_BLK_CLR_ALL */
#define TRDC_MBC_NSE_BLK_CLR_ALL_COUNT           (4U)

/*! @name MBC_MEMN_GLBAC - MBC Global Access Control */
/*! @{ */

#define TRDC_MBC_MEMN_GLBAC_NUX_MASK             (0x1U)
#define TRDC_MBC_MEMN_GLBAC_NUX_SHIFT            (0U)
/*! NUX - NonsecureUser Execute
 *  0b0..Execute access is not allowed in Nonsecure User mode.
 *  0b1..Execute access is allowed in Nonsecure User mode.
 */
#define TRDC_MBC_MEMN_GLBAC_NUX(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NUX_MASK)

#define TRDC_MBC_MEMN_GLBAC_NUW_MASK             (0x2U)
#define TRDC_MBC_MEMN_GLBAC_NUW_SHIFT            (1U)
/*! NUW - NonsecureUser Write
 *  0b0..Write access is not allowed in Nonsecure User mode.
 *  0b1..Write access is allowed in Nonsecure User mode.
 */
#define TRDC_MBC_MEMN_GLBAC_NUW(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NUW_MASK)

#define TRDC_MBC_MEMN_GLBAC_NUR_MASK             (0x4U)
#define TRDC_MBC_MEMN_GLBAC_NUR_SHIFT            (2U)
/*! NUR - NonsecureUser Read
 *  0b0..Read access is not allowed in Nonsecure User mode.
 *  0b1..Read access is allowed in Nonsecure User mode.
 */
#define TRDC_MBC_MEMN_GLBAC_NUR(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NUR_MASK)

#define TRDC_MBC_MEMN_GLBAC_NPX_MASK             (0x10U)
#define TRDC_MBC_MEMN_GLBAC_NPX_SHIFT            (4U)
/*! NPX - NonsecurePriv Execute
 *  0b0..Execute access is not allowed in Nonsecure Privilege mode.
 *  0b1..Execute access is allowed in Nonsecure Privilege mode.
 */
#define TRDC_MBC_MEMN_GLBAC_NPX(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NPX_MASK)

#define TRDC_MBC_MEMN_GLBAC_NPW_MASK             (0x20U)
#define TRDC_MBC_MEMN_GLBAC_NPW_SHIFT            (5U)
/*! NPW - NonsecurePriv Write
 *  0b0..Write access is not allowed in Nonsecure Privilege mode.
 *  0b1..Write access is allowed in Nonsecure Privilege mode.
 */
#define TRDC_MBC_MEMN_GLBAC_NPW(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NPW_MASK)

#define TRDC_MBC_MEMN_GLBAC_NPR_MASK             (0x40U)
#define TRDC_MBC_MEMN_GLBAC_NPR_SHIFT            (6U)
/*! NPR - NonsecurePriv Read
 *  0b0..Read access is not allowed in Nonsecure Privilege mode.
 *  0b1..Read access is allowed in Nonsecure Privilege mode.
 */
#define TRDC_MBC_MEMN_GLBAC_NPR(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NPR_MASK)

#define TRDC_MBC_MEMN_GLBAC_SUX_MASK             (0x100U)
#define TRDC_MBC_MEMN_GLBAC_SUX_SHIFT            (8U)
/*! SUX - SecureUser Execute
 *  0b0..Execute access is not allowed in Secure User mode.
 *  0b1..Execute access is allowed in Secure User mode.
 */
#define TRDC_MBC_MEMN_GLBAC_SUX(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SUX_MASK)

#define TRDC_MBC_MEMN_GLBAC_SUW_MASK             (0x200U)
#define TRDC_MBC_MEMN_GLBAC_SUW_SHIFT            (9U)
/*! SUW - SecureUser Write
 *  0b0..Write access is not allowed in Secure User mode.
 *  0b1..Write access is allowed in Secure User mode.
 */
#define TRDC_MBC_MEMN_GLBAC_SUW(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SUW_MASK)

#define TRDC_MBC_MEMN_GLBAC_SUR_MASK             (0x400U)
#define TRDC_MBC_MEMN_GLBAC_SUR_SHIFT            (10U)
/*! SUR - SecureUser Read
 *  0b0..Read access is not allowed in Secure User mode.
 *  0b1..Read access is allowed in Secure User mode.
 */
#define TRDC_MBC_MEMN_GLBAC_SUR(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SUR_MASK)

#define TRDC_MBC_MEMN_GLBAC_SPX_MASK             (0x1000U)
#define TRDC_MBC_MEMN_GLBAC_SPX_SHIFT            (12U)
/*! SPX - SecurePriv Execute
 *  0b0..Execute access is not allowed in Secure Privilege mode.
 *  0b1..Execute access is allowed in Secure Privilege mode.
 */
#define TRDC_MBC_MEMN_GLBAC_SPX(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SPX_MASK)

#define TRDC_MBC_MEMN_GLBAC_SPW_MASK             (0x2000U)
#define TRDC_MBC_MEMN_GLBAC_SPW_SHIFT            (13U)
/*! SPW - SecurePriv Write
 *  0b0..Write access is not allowed in Secure Privilege mode.
 *  0b1..Write access is allowed in Secure Privilege mode.
 */
#define TRDC_MBC_MEMN_GLBAC_SPW(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SPW_MASK)

#define TRDC_MBC_MEMN_GLBAC_SPR_MASK             (0x4000U)
#define TRDC_MBC_MEMN_GLBAC_SPR_SHIFT            (14U)
/*! SPR - SecurePriv Read
 *  0b0..Read access is not allowed in Secure Privilege mode.
 *  0b1..Read access is allowed in Secure Privilege mode.
 */
#define TRDC_MBC_MEMN_GLBAC_SPR(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SPR_MASK)

#define TRDC_MBC_MEMN_GLBAC_LK_MASK              (0x80000000U)
#define TRDC_MBC_MEMN_GLBAC_LK_SHIFT             (31U)
/*! LK - LOCK
 *  0b0..This register is not locked and can be altered.
 *  0b1..This register is locked and cannot be altered.
 */
#define TRDC_MBC_MEMN_GLBAC_LK(x)                (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_MEMN_GLBAC_LK_MASK)
/*! @} */

/* The count of TRDC_MBC_MEMN_GLBAC */
#define TRDC_MBC_MEMN_GLBAC_COUNT                (4U)

/* The count of TRDC_MBC_MEMN_GLBAC */
#define TRDC_MBC_MEMN_GLBAC_COUNT2               (8U)

/*! @name MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM0_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2      (9U)

/*! @name MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM0_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2      (3U)

/*! @name MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM0_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2      (6U)

/*! @name MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM0_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2      (2U)

/*! @name MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM0_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2      (4U)

/*! @name MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM0_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM0_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM0_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_COUNT2      (1U)

/*! @name MBC_DOM0_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM0_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM1_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM1_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_COUNT2      (9U)

/*! @name MBC_DOM1_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM1_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_COUNT2      (3U)

/*! @name MBC_DOM1_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM1_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_COUNT2      (6U)

/*! @name MBC_DOM1_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM1_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_COUNT2      (2U)

/*! @name MBC_DOM1_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM1_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_COUNT2      (4U)

/*! @name MBC_DOM1_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM1_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM1_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM1_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_COUNT2      (1U)

/*! @name MBC_DOM1_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM1_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM2_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM2_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_COUNT2      (9U)

/*! @name MBC_DOM2_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM2_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_COUNT2      (3U)

/*! @name MBC_DOM2_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM2_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_COUNT2      (6U)

/*! @name MBC_DOM2_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM2_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_COUNT2      (2U)

/*! @name MBC_DOM2_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM2_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_COUNT2      (4U)

/*! @name MBC_DOM2_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM2_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM2_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM2_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_COUNT2      (1U)

/*! @name MBC_DOM2_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM2_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM3_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM3_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM3_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_COUNT2      (9U)

/*! @name MBC_DOM3_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM3_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM3_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_COUNT2      (3U)

/*! @name MBC_DOM3_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM3_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM3_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_COUNT2      (6U)

/*! @name MBC_DOM3_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM3_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM3_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_COUNT2      (2U)

/*! @name MBC_DOM3_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM3_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM3_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_COUNT2      (4U)

/*! @name MBC_DOM3_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM3_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM3_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM3_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM3_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM3_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_COUNT2      (1U)

/*! @name MBC_DOM3_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM3_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM3_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM4_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM4_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM4_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_COUNT2      (9U)

/*! @name MBC_DOM4_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM4_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM4_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_COUNT2      (3U)

/*! @name MBC_DOM4_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM4_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM4_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_COUNT2      (6U)

/*! @name MBC_DOM4_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM4_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM4_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_COUNT2      (2U)

/*! @name MBC_DOM4_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM4_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM4_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_COUNT2      (4U)

/*! @name MBC_DOM4_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM4_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM4_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM4_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM4_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM4_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_COUNT2      (1U)

/*! @name MBC_DOM4_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM4_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM4_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM5_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM5_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM5_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_COUNT2      (9U)

/*! @name MBC_DOM5_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM5_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM5_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_COUNT2      (3U)

/*! @name MBC_DOM5_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM5_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM5_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_COUNT2      (6U)

/*! @name MBC_DOM5_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM5_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM5_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_COUNT2      (2U)

/*! @name MBC_DOM5_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM5_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM5_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_COUNT2      (4U)

/*! @name MBC_DOM5_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM5_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM5_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM5_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM5_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM5_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_COUNT2      (1U)

/*! @name MBC_DOM5_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM5_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM5_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM6_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM6_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM6_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_COUNT2      (9U)

/*! @name MBC_DOM6_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM6_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM6_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_COUNT2      (3U)

/*! @name MBC_DOM6_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM6_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM6_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_COUNT2      (6U)

/*! @name MBC_DOM6_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM6_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM6_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_COUNT2      (2U)

/*! @name MBC_DOM6_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM6_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM6_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_COUNT2      (4U)

/*! @name MBC_DOM6_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM6_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM6_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM6_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM6_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM6_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_COUNT2      (1U)

/*! @name MBC_DOM6_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM6_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM6_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM7_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM7_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM7_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_COUNT2      (9U)

/*! @name MBC_DOM7_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM7_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM7_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_COUNT2      (3U)

/*! @name MBC_DOM7_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM7_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM7_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_COUNT2      (6U)

/*! @name MBC_DOM7_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM7_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM7_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_COUNT2      (2U)

/*! @name MBC_DOM7_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM7_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM7_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_COUNT2      (4U)

/*! @name MBC_DOM7_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM7_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM7_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM7_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM7_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM7_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_COUNT2      (1U)

/*! @name MBC_DOM7_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM7_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_COUNT       (4U)

/* The count of TRDC_MBC_DOM7_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_COUNT2      (1U)

/*! @name MRC_GLBCFG - MRC Global Configuration Register */
/*! @{ */

#define TRDC_MRC_GLBCFG_NRGNS_MASK               (0x1FU)
#define TRDC_MRC_GLBCFG_NRGNS_SHIFT              (0U)
/*! NRGNS - Number of regions [1-16] */
#define TRDC_MRC_GLBCFG_NRGNS(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBCFG_NRGNS_SHIFT)) & TRDC_MRC_GLBCFG_NRGNS_MASK)
/*! @} */

/* The count of TRDC_MRC_GLBCFG */
#define TRDC_MRC_GLBCFG_COUNT                    (2U)

/*! @name MRC_NSE_RGN_INDIRECT - MRC NonSecure Enable Region Indirect */
/*! @{ */

#define TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK   (0xFF0000U)
#define TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT  (16U)
/*! DID_SEL - DID Select */
#define TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT)) & TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK)
/*! @} */

/* The count of TRDC_MRC_NSE_RGN_INDIRECT */
#define TRDC_MRC_NSE_RGN_INDIRECT_COUNT          (2U)

/*! @name MRC_NSE_RGN_SET - MRC NonSecure Enable Region Set */
/*! @{ */

#define TRDC_MRC_NSE_RGN_SET_W1SET_MASK          (0xFFFFU)
#define TRDC_MRC_NSE_RGN_SET_W1SET_SHIFT         (0U)
/*! W1SET - Write-1 Set */
#define TRDC_MRC_NSE_RGN_SET_W1SET(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_NSE_RGN_SET_W1SET_SHIFT)) & TRDC_MRC_NSE_RGN_SET_W1SET_MASK)
/*! @} */

/* The count of TRDC_MRC_NSE_RGN_SET */
#define TRDC_MRC_NSE_RGN_SET_COUNT               (2U)

/*! @name MRC_NSE_RGN_CLR - MRC NonSecure Enable Region Clear */
/*! @{ */

#define TRDC_MRC_NSE_RGN_CLR_W1CLR_MASK          (0xFFFFU)
#define TRDC_MRC_NSE_RGN_CLR_W1CLR_SHIFT         (0U)
/*! W1CLR - Write-1 Clear */
#define TRDC_MRC_NSE_RGN_CLR_W1CLR(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_NSE_RGN_CLR_W1CLR_SHIFT)) & TRDC_MRC_NSE_RGN_CLR_W1CLR_MASK)
/*! @} */

/* The count of TRDC_MRC_NSE_RGN_CLR */
#define TRDC_MRC_NSE_RGN_CLR_COUNT               (2U)

/*! @name MRC_NSE_RGN_CLR_ALL - MRC NonSecure Enable Region Clear All */
/*! @{ */

#define TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK    (0xFF0000U)
#define TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT   (16U)
/*! DID_SEL - DID Select */
#define TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL(x)      (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT)) & TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK)
/*! @} */

/* The count of TRDC_MRC_NSE_RGN_CLR_ALL */
#define TRDC_MRC_NSE_RGN_CLR_ALL_COUNT           (2U)

/*! @name MRC_GLBAC - MRC Global Access Control */
/*! @{ */

#define TRDC_MRC_GLBAC_NUX_MASK                  (0x1U)
#define TRDC_MRC_GLBAC_NUX_SHIFT                 (0U)
/*! NUX - NonsecureUser Execute
 *  0b0..Execute access is not allowed in Nonsecure User mode.
 *  0b1..Execute access is allowed in Nonsecure User mode.
 */
#define TRDC_MRC_GLBAC_NUX(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NUX_SHIFT)) & TRDC_MRC_GLBAC_NUX_MASK)

#define TRDC_MRC_GLBAC_NUW_MASK                  (0x2U)
#define TRDC_MRC_GLBAC_NUW_SHIFT                 (1U)
/*! NUW - NonsecureUser Write
 *  0b0..Write access is not allowed in Nonsecure User mode.
 *  0b1..Write access is allowed in Nonsecure User mode.
 */
#define TRDC_MRC_GLBAC_NUW(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NUW_SHIFT)) & TRDC_MRC_GLBAC_NUW_MASK)

#define TRDC_MRC_GLBAC_NUR_MASK                  (0x4U)
#define TRDC_MRC_GLBAC_NUR_SHIFT                 (2U)
/*! NUR - NonsecureUser Read
 *  0b0..Read access is not allowed in Nonsecure User mode.
 *  0b1..Read access is allowed in Nonsecure User mode.
 */
#define TRDC_MRC_GLBAC_NUR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NUR_SHIFT)) & TRDC_MRC_GLBAC_NUR_MASK)

#define TRDC_MRC_GLBAC_NPX_MASK                  (0x10U)
#define TRDC_MRC_GLBAC_NPX_SHIFT                 (4U)
/*! NPX - NonsecurePriv Execute
 *  0b0..Execute access is not allowed in Nonsecure Privilege mode.
 *  0b1..Execute access is allowed in Nonsecure Privilege mode.
 */
#define TRDC_MRC_GLBAC_NPX(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NPX_SHIFT)) & TRDC_MRC_GLBAC_NPX_MASK)

#define TRDC_MRC_GLBAC_NPW_MASK                  (0x20U)
#define TRDC_MRC_GLBAC_NPW_SHIFT                 (5U)
/*! NPW - NonsecurePriv Write
 *  0b0..Write access is not allowed in Nonsecure Privilege mode.
 *  0b1..Write access is allowed in Nonsecure Privilege mode.
 */
#define TRDC_MRC_GLBAC_NPW(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NPW_SHIFT)) & TRDC_MRC_GLBAC_NPW_MASK)

#define TRDC_MRC_GLBAC_NPR_MASK                  (0x40U)
#define TRDC_MRC_GLBAC_NPR_SHIFT                 (6U)
/*! NPR - NonsecurePriv Read
 *  0b0..Read access is not allowed in Nonsecure Privilege mode.
 *  0b1..Read access is allowed in Nonsecure Privilege mode.
 */
#define TRDC_MRC_GLBAC_NPR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NPR_SHIFT)) & TRDC_MRC_GLBAC_NPR_MASK)

#define TRDC_MRC_GLBAC_SUX_MASK                  (0x100U)
#define TRDC_MRC_GLBAC_SUX_SHIFT                 (8U)
/*! SUX - SecureUser Execute
 *  0b0..Execute access is not allowed in Secure User mode.
 *  0b1..Execute access is allowed in Secure User mode.
 */
#define TRDC_MRC_GLBAC_SUX(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SUX_SHIFT)) & TRDC_MRC_GLBAC_SUX_MASK)

#define TRDC_MRC_GLBAC_SUW_MASK                  (0x200U)
#define TRDC_MRC_GLBAC_SUW_SHIFT                 (9U)
/*! SUW - SecureUser Write
 *  0b0..Write access is not allowed in Secure User mode.
 *  0b1..Write access is allowed in Secure User mode.
 */
#define TRDC_MRC_GLBAC_SUW(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SUW_SHIFT)) & TRDC_MRC_GLBAC_SUW_MASK)

#define TRDC_MRC_GLBAC_SUR_MASK                  (0x400U)
#define TRDC_MRC_GLBAC_SUR_SHIFT                 (10U)
/*! SUR - SecureUser Read
 *  0b0..Read access is not allowed in Secure User mode.
 *  0b1..Read access is allowed in Secure User mode.
 */
#define TRDC_MRC_GLBAC_SUR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SUR_SHIFT)) & TRDC_MRC_GLBAC_SUR_MASK)

#define TRDC_MRC_GLBAC_SPX_MASK                  (0x1000U)
#define TRDC_MRC_GLBAC_SPX_SHIFT                 (12U)
/*! SPX - SecurePriv Execute
 *  0b0..Execute access is not allowed in Secure Privilege mode.
 *  0b1..Execute access is allowed in Secure Privilege mode.
 */
#define TRDC_MRC_GLBAC_SPX(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SPX_SHIFT)) & TRDC_MRC_GLBAC_SPX_MASK)

#define TRDC_MRC_GLBAC_SPW_MASK                  (0x2000U)
#define TRDC_MRC_GLBAC_SPW_SHIFT                 (13U)
/*! SPW - SecurePriv Write
 *  0b0..Write access is not allowed in Secure Privilege mode.
 *  0b1..Write access is allowed in Secure Privilege mode.
 */
#define TRDC_MRC_GLBAC_SPW(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SPW_SHIFT)) & TRDC_MRC_GLBAC_SPW_MASK)

#define TRDC_MRC_GLBAC_SPR_MASK                  (0x4000U)
#define TRDC_MRC_GLBAC_SPR_SHIFT                 (14U)
/*! SPR - SecurePriv Read
 *  0b0..Read access is not allowed in Secure Privilege mode.
 *  0b1..Read access is allowed in Secure Privilege mode.
 */
#define TRDC_MRC_GLBAC_SPR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SPR_SHIFT)) & TRDC_MRC_GLBAC_SPR_MASK)

#define TRDC_MRC_GLBAC_LK_MASK                   (0x80000000U)
#define TRDC_MRC_GLBAC_LK_SHIFT                  (31U)
/*! LK - LOCK
 *  0b0..This register is not locked and can be altered.
 *  0b1..This register is locked (read-only) and cannot be altered.
 */
#define TRDC_MRC_GLBAC_LK(x)                     (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_LK_SHIFT)) & TRDC_MRC_GLBAC_LK_MASK)
/*! @} */

/* The count of TRDC_MRC_GLBAC */
#define TRDC_MRC_GLBAC_COUNT                     (2U)

/* The count of TRDC_MRC_GLBAC */
#define TRDC_MRC_GLBAC_COUNT2                    (8U)

/*! @name MRC_DOM0_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
/*! @{ */

#define TRDC_MRC_DOM0_RGD_W_MRACSEL_MASK         (0x7U)
#define TRDC_MRC_DOM0_RGD_W_MRACSEL_SHIFT        (0U)
/*! MRACSEL - Memory Region Access Control Select
 *  0b000..Select MRC_GLBAC0 access control policy
 *  0b001..Select MRC_GLBAC1 access control policy
 *  0b010..Select MRC_GLBAC2 access control policy
 *  0b011..Select MRC_GLBAC3 access control policy
 *  0b100..Select MRC_GLBAC4 access control policy
 *  0b101..Select MRC_GLBAC5 access control policy
 *  0b110..Select MRC_GLBAC6 access control policy
 *  0b111..Select MRC_GLBAC7 access control policy
 */
#define TRDC_MRC_DOM0_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM0_RGD_W_MRACSEL_MASK)

#define TRDC_MRC_DOM0_RGD_W_VLD_MASK             (0x1U)
#define TRDC_MRC_DOM0_RGD_W_VLD_SHIFT            (0U)
/*! VLD - Valid */
#define TRDC_MRC_DOM0_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM0_RGD_W_VLD_MASK)

#define TRDC_MRC_DOM0_RGD_W_NSE_MASK             (0x10U)
#define TRDC_MRC_DOM0_RGD_W_NSE_SHIFT            (4U)
/*! NSE - NonSecure Enable
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM0_RGD_W_NSE_MASK)

#define TRDC_MRC_DOM0_RGD_W_END_ADDR_MASK        (0xFFFFF000U)
#define TRDC_MRC_DOM0_RGD_W_END_ADDR_SHIFT       (12U)
/*! END_ADDR - End Address */
#define TRDC_MRC_DOM0_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM0_RGD_W_END_ADDR_MASK)

#define TRDC_MRC_DOM0_RGD_W_STRT_ADDR_MASK       (0xFFFFF000U)
#define TRDC_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT      (12U)
/*! STRT_ADDR - Start Address */
#define TRDC_MRC_DOM0_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM0_RGD_W_STRT_ADDR_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM0_RGD_W */
#define TRDC_MRC_DOM0_RGD_W_COUNT                (2U)

/* The count of TRDC_MRC_DOM0_RGD_W */
#define TRDC_MRC_DOM0_RGD_W_COUNT2               (8U)

/* The count of TRDC_MRC_DOM0_RGD_W */
#define TRDC_MRC_DOM0_RGD_W_COUNT3               (2U)

/*! @name MRC_DOM0_RGD_NSE - MRC Region Descriptor NonSecure Enable */
/*! @{ */

#define TRDC_MRC_DOM0_RGD_NSE_BIT0_MASK          (0x1U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT0_SHIFT         (0U)
/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT0_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT1_MASK          (0x2U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT1_SHIFT         (1U)
/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT1_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT2_MASK          (0x4U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT2_SHIFT         (2U)
/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT2_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT3_MASK          (0x8U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT3_SHIFT         (3U)
/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT3_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT4_MASK          (0x10U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT4_SHIFT         (4U)
/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT4_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT5_MASK          (0x20U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT5_SHIFT         (5U)
/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT5_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT6_MASK          (0x40U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT6_SHIFT         (6U)
/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT6_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT7_MASK          (0x80U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT7_SHIFT         (7U)
/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT7_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM0_RGD_NSE */
#define TRDC_MRC_DOM0_RGD_NSE_COUNT              (2U)

/*! @name MRC_DOM1_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
/*! @{ */

#define TRDC_MRC_DOM1_RGD_W_MRACSEL_MASK         (0x7U)
#define TRDC_MRC_DOM1_RGD_W_MRACSEL_SHIFT        (0U)
/*! MRACSEL - Memory Region Access Control Select
 *  0b000..Select MRC_GLBAC0 access control policy
 *  0b001..Select MRC_GLBAC1 access control policy
 *  0b010..Select MRC_GLBAC2 access control policy
 *  0b011..Select MRC_GLBAC3 access control policy
 *  0b100..Select MRC_GLBAC4 access control policy
 *  0b101..Select MRC_GLBAC5 access control policy
 *  0b110..Select MRC_GLBAC6 access control policy
 *  0b111..Select MRC_GLBAC7 access control policy
 */
#define TRDC_MRC_DOM1_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM1_RGD_W_MRACSEL_MASK)

#define TRDC_MRC_DOM1_RGD_W_VLD_MASK             (0x1U)
#define TRDC_MRC_DOM1_RGD_W_VLD_SHIFT            (0U)
/*! VLD - Valid */
#define TRDC_MRC_DOM1_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM1_RGD_W_VLD_MASK)

#define TRDC_MRC_DOM1_RGD_W_NSE_MASK             (0x10U)
#define TRDC_MRC_DOM1_RGD_W_NSE_SHIFT            (4U)
/*! NSE - NonSecure Enable
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM1_RGD_W_NSE_MASK)

#define TRDC_MRC_DOM1_RGD_W_END_ADDR_MASK        (0xFFFFF000U)
#define TRDC_MRC_DOM1_RGD_W_END_ADDR_SHIFT       (12U)
/*! END_ADDR - End Address */
#define TRDC_MRC_DOM1_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM1_RGD_W_END_ADDR_MASK)

#define TRDC_MRC_DOM1_RGD_W_STRT_ADDR_MASK       (0xFFFFF000U)
#define TRDC_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT      (12U)
/*! STRT_ADDR - Start Address */
#define TRDC_MRC_DOM1_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM1_RGD_W_STRT_ADDR_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM1_RGD_W */
#define TRDC_MRC_DOM1_RGD_W_COUNT                (2U)

/* The count of TRDC_MRC_DOM1_RGD_W */
#define TRDC_MRC_DOM1_RGD_W_COUNT2               (8U)

/* The count of TRDC_MRC_DOM1_RGD_W */
#define TRDC_MRC_DOM1_RGD_W_COUNT3               (2U)

/*! @name MRC_DOM1_RGD_NSE - MRC Region Descriptor NonSecure Enable */
/*! @{ */

#define TRDC_MRC_DOM1_RGD_NSE_BIT0_MASK          (0x1U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT0_SHIFT         (0U)
/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT0_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT1_MASK          (0x2U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT1_SHIFT         (1U)
/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT1_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT2_MASK          (0x4U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT2_SHIFT         (2U)
/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT2_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT3_MASK          (0x8U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT3_SHIFT         (3U)
/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT3_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT4_MASK          (0x10U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT4_SHIFT         (4U)
/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT4_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT5_MASK          (0x20U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT5_SHIFT         (5U)
/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT5_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT6_MASK          (0x40U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT6_SHIFT         (6U)
/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT6_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT7_MASK          (0x80U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT7_SHIFT         (7U)
/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT7_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM1_RGD_NSE */
#define TRDC_MRC_DOM1_RGD_NSE_COUNT              (2U)

/*! @name MRC_DOM2_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
/*! @{ */

#define TRDC_MRC_DOM2_RGD_W_MRACSEL_MASK         (0x7U)
#define TRDC_MRC_DOM2_RGD_W_MRACSEL_SHIFT        (0U)
/*! MRACSEL - Memory Region Access Control Select
 *  0b000..Select MRC_GLBAC0 access control policy
 *  0b001..Select MRC_GLBAC1 access control policy
 *  0b010..Select MRC_GLBAC2 access control policy
 *  0b011..Select MRC_GLBAC3 access control policy
 *  0b100..Select MRC_GLBAC4 access control policy
 *  0b101..Select MRC_GLBAC5 access control policy
 *  0b110..Select MRC_GLBAC6 access control policy
 *  0b111..Select MRC_GLBAC7 access control policy
 */
#define TRDC_MRC_DOM2_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM2_RGD_W_MRACSEL_MASK)

#define TRDC_MRC_DOM2_RGD_W_VLD_MASK             (0x1U)
#define TRDC_MRC_DOM2_RGD_W_VLD_SHIFT            (0U)
/*! VLD - Valid */
#define TRDC_MRC_DOM2_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM2_RGD_W_VLD_MASK)

#define TRDC_MRC_DOM2_RGD_W_NSE_MASK             (0x10U)
#define TRDC_MRC_DOM2_RGD_W_NSE_SHIFT            (4U)
/*! NSE - NonSecure Enable
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM2_RGD_W_NSE_MASK)

#define TRDC_MRC_DOM2_RGD_W_END_ADDR_MASK        (0xFFFFF000U)
#define TRDC_MRC_DOM2_RGD_W_END_ADDR_SHIFT       (12U)
/*! END_ADDR - End Address */
#define TRDC_MRC_DOM2_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM2_RGD_W_END_ADDR_MASK)

#define TRDC_MRC_DOM2_RGD_W_STRT_ADDR_MASK       (0xFFFFF000U)
#define TRDC_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT      (12U)
/*! STRT_ADDR - Start Address */
#define TRDC_MRC_DOM2_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM2_RGD_W_STRT_ADDR_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM2_RGD_W */
#define TRDC_MRC_DOM2_RGD_W_COUNT                (2U)

/* The count of TRDC_MRC_DOM2_RGD_W */
#define TRDC_MRC_DOM2_RGD_W_COUNT2               (8U)

/* The count of TRDC_MRC_DOM2_RGD_W */
#define TRDC_MRC_DOM2_RGD_W_COUNT3               (2U)

/*! @name MRC_DOM2_RGD_NSE - MRC Region Descriptor NonSecure Enable */
/*! @{ */

#define TRDC_MRC_DOM2_RGD_NSE_BIT0_MASK          (0x1U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT0_SHIFT         (0U)
/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT0_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT1_MASK          (0x2U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT1_SHIFT         (1U)
/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT1_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT2_MASK          (0x4U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT2_SHIFT         (2U)
/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT2_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT3_MASK          (0x8U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT3_SHIFT         (3U)
/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT3_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT4_MASK          (0x10U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT4_SHIFT         (4U)
/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT4_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT5_MASK          (0x20U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT5_SHIFT         (5U)
/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT5_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT6_MASK          (0x40U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT6_SHIFT         (6U)
/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT6_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT7_MASK          (0x80U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT7_SHIFT         (7U)
/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT7_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM2_RGD_NSE */
#define TRDC_MRC_DOM2_RGD_NSE_COUNT              (2U)

/*! @name MRC_DOM3_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
/*! @{ */

#define TRDC_MRC_DOM3_RGD_W_MRACSEL_MASK         (0x7U)
#define TRDC_MRC_DOM3_RGD_W_MRACSEL_SHIFT        (0U)
/*! MRACSEL - Memory Region Access Control Select
 *  0b000..Select MRC_GLBAC0 access control policy
 *  0b001..Select MRC_GLBAC1 access control policy
 *  0b010..Select MRC_GLBAC2 access control policy
 *  0b011..Select MRC_GLBAC3 access control policy
 *  0b100..Select MRC_GLBAC4 access control policy
 *  0b101..Select MRC_GLBAC5 access control policy
 *  0b110..Select MRC_GLBAC6 access control policy
 *  0b111..Select MRC_GLBAC7 access control policy
 */
#define TRDC_MRC_DOM3_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM3_RGD_W_MRACSEL_MASK)

#define TRDC_MRC_DOM3_RGD_W_VLD_MASK             (0x1U)
#define TRDC_MRC_DOM3_RGD_W_VLD_SHIFT            (0U)
/*! VLD - Valid */
#define TRDC_MRC_DOM3_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM3_RGD_W_VLD_MASK)

#define TRDC_MRC_DOM3_RGD_W_NSE_MASK             (0x10U)
#define TRDC_MRC_DOM3_RGD_W_NSE_SHIFT            (4U)
/*! NSE - NonSecure Enable
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM3_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM3_RGD_W_NSE_MASK)

#define TRDC_MRC_DOM3_RGD_W_END_ADDR_MASK        (0xFFFFF000U)
#define TRDC_MRC_DOM3_RGD_W_END_ADDR_SHIFT       (12U)
/*! END_ADDR - End Address */
#define TRDC_MRC_DOM3_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM3_RGD_W_END_ADDR_MASK)

#define TRDC_MRC_DOM3_RGD_W_STRT_ADDR_MASK       (0xFFFFF000U)
#define TRDC_MRC_DOM3_RGD_W_STRT_ADDR_SHIFT      (12U)
/*! STRT_ADDR - Start Address */
#define TRDC_MRC_DOM3_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM3_RGD_W_STRT_ADDR_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM3_RGD_W */
#define TRDC_MRC_DOM3_RGD_W_COUNT                (2U)

/* The count of TRDC_MRC_DOM3_RGD_W */
#define TRDC_MRC_DOM3_RGD_W_COUNT2               (8U)

/* The count of TRDC_MRC_DOM3_RGD_W */
#define TRDC_MRC_DOM3_RGD_W_COUNT3               (2U)

/*! @name MRC_DOM3_RGD_NSE - MRC Region Descriptor NonSecure Enable */
/*! @{ */

#define TRDC_MRC_DOM3_RGD_NSE_BIT0_MASK          (0x1U)
#define TRDC_MRC_DOM3_RGD_NSE_BIT0_SHIFT         (0U)
/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM3_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT0_MASK)

#define TRDC_MRC_DOM3_RGD_NSE_BIT1_MASK          (0x2U)
#define TRDC_MRC_DOM3_RGD_NSE_BIT1_SHIFT         (1U)
/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM3_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT1_MASK)

#define TRDC_MRC_DOM3_RGD_NSE_BIT2_MASK          (0x4U)
#define TRDC_MRC_DOM3_RGD_NSE_BIT2_SHIFT         (2U)
/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM3_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT2_MASK)

#define TRDC_MRC_DOM3_RGD_NSE_BIT3_MASK          (0x8U)
#define TRDC_MRC_DOM3_RGD_NSE_BIT3_SHIFT         (3U)
/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM3_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT3_MASK)

#define TRDC_MRC_DOM3_RGD_NSE_BIT4_MASK          (0x10U)
#define TRDC_MRC_DOM3_RGD_NSE_BIT4_SHIFT         (4U)
/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM3_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT4_MASK)

#define TRDC_MRC_DOM3_RGD_NSE_BIT5_MASK          (0x20U)
#define TRDC_MRC_DOM3_RGD_NSE_BIT5_SHIFT         (5U)
/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM3_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT5_MASK)

#define TRDC_MRC_DOM3_RGD_NSE_BIT6_MASK          (0x40U)
#define TRDC_MRC_DOM3_RGD_NSE_BIT6_SHIFT         (6U)
/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM3_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT6_MASK)

#define TRDC_MRC_DOM3_RGD_NSE_BIT7_MASK          (0x80U)
#define TRDC_MRC_DOM3_RGD_NSE_BIT7_SHIFT         (7U)
/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM3_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT7_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM3_RGD_NSE */
#define TRDC_MRC_DOM3_RGD_NSE_COUNT              (2U)

/*! @name MRC_DOM4_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
/*! @{ */

#define TRDC_MRC_DOM4_RGD_W_MRACSEL_MASK         (0x7U)
#define TRDC_MRC_DOM4_RGD_W_MRACSEL_SHIFT        (0U)
/*! MRACSEL - Memory Region Access Control Select
 *  0b000..Select MRC_GLBAC0 access control policy
 *  0b001..Select MRC_GLBAC1 access control policy
 *  0b010..Select MRC_GLBAC2 access control policy
 *  0b011..Select MRC_GLBAC3 access control policy
 *  0b100..Select MRC_GLBAC4 access control policy
 *  0b101..Select MRC_GLBAC5 access control policy
 *  0b110..Select MRC_GLBAC6 access control policy
 *  0b111..Select MRC_GLBAC7 access control policy
 */
#define TRDC_MRC_DOM4_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM4_RGD_W_MRACSEL_MASK)

#define TRDC_MRC_DOM4_RGD_W_VLD_MASK             (0x1U)
#define TRDC_MRC_DOM4_RGD_W_VLD_SHIFT            (0U)
/*! VLD - Valid */
#define TRDC_MRC_DOM4_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM4_RGD_W_VLD_MASK)

#define TRDC_MRC_DOM4_RGD_W_NSE_MASK             (0x10U)
#define TRDC_MRC_DOM4_RGD_W_NSE_SHIFT            (4U)
/*! NSE - NonSecure Enable
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM4_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM4_RGD_W_NSE_MASK)

#define TRDC_MRC_DOM4_RGD_W_END_ADDR_MASK        (0xFFFFF000U)
#define TRDC_MRC_DOM4_RGD_W_END_ADDR_SHIFT       (12U)
/*! END_ADDR - End Address */
#define TRDC_MRC_DOM4_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM4_RGD_W_END_ADDR_MASK)

#define TRDC_MRC_DOM4_RGD_W_STRT_ADDR_MASK       (0xFFFFF000U)
#define TRDC_MRC_DOM4_RGD_W_STRT_ADDR_SHIFT      (12U)
/*! STRT_ADDR - Start Address */
#define TRDC_MRC_DOM4_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM4_RGD_W_STRT_ADDR_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM4_RGD_W */
#define TRDC_MRC_DOM4_RGD_W_COUNT                (2U)

/* The count of TRDC_MRC_DOM4_RGD_W */
#define TRDC_MRC_DOM4_RGD_W_COUNT2               (8U)

/* The count of TRDC_MRC_DOM4_RGD_W */
#define TRDC_MRC_DOM4_RGD_W_COUNT3               (2U)

/*! @name MRC_DOM4_RGD_NSE - MRC Region Descriptor NonSecure Enable */
/*! @{ */

#define TRDC_MRC_DOM4_RGD_NSE_BIT0_MASK          (0x1U)
#define TRDC_MRC_DOM4_RGD_NSE_BIT0_SHIFT         (0U)
/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM4_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT0_MASK)

#define TRDC_MRC_DOM4_RGD_NSE_BIT1_MASK          (0x2U)
#define TRDC_MRC_DOM4_RGD_NSE_BIT1_SHIFT         (1U)
/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM4_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT1_MASK)

#define TRDC_MRC_DOM4_RGD_NSE_BIT2_MASK          (0x4U)
#define TRDC_MRC_DOM4_RGD_NSE_BIT2_SHIFT         (2U)
/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM4_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT2_MASK)

#define TRDC_MRC_DOM4_RGD_NSE_BIT3_MASK          (0x8U)
#define TRDC_MRC_DOM4_RGD_NSE_BIT3_SHIFT         (3U)
/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM4_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT3_MASK)

#define TRDC_MRC_DOM4_RGD_NSE_BIT4_MASK          (0x10U)
#define TRDC_MRC_DOM4_RGD_NSE_BIT4_SHIFT         (4U)
/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM4_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT4_MASK)

#define TRDC_MRC_DOM4_RGD_NSE_BIT5_MASK          (0x20U)
#define TRDC_MRC_DOM4_RGD_NSE_BIT5_SHIFT         (5U)
/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM4_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT5_MASK)

#define TRDC_MRC_DOM4_RGD_NSE_BIT6_MASK          (0x40U)
#define TRDC_MRC_DOM4_RGD_NSE_BIT6_SHIFT         (6U)
/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM4_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT6_MASK)

#define TRDC_MRC_DOM4_RGD_NSE_BIT7_MASK          (0x80U)
#define TRDC_MRC_DOM4_RGD_NSE_BIT7_SHIFT         (7U)
/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM4_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT7_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM4_RGD_NSE */
#define TRDC_MRC_DOM4_RGD_NSE_COUNT              (2U)

/*! @name MRC_DOM5_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
/*! @{ */

#define TRDC_MRC_DOM5_RGD_W_MRACSEL_MASK         (0x7U)
#define TRDC_MRC_DOM5_RGD_W_MRACSEL_SHIFT        (0U)
/*! MRACSEL - Memory Region Access Control Select
 *  0b000..Select MRC_GLBAC0 access control policy
 *  0b001..Select MRC_GLBAC1 access control policy
 *  0b010..Select MRC_GLBAC2 access control policy
 *  0b011..Select MRC_GLBAC3 access control policy
 *  0b100..Select MRC_GLBAC4 access control policy
 *  0b101..Select MRC_GLBAC5 access control policy
 *  0b110..Select MRC_GLBAC6 access control policy
 *  0b111..Select MRC_GLBAC7 access control policy
 */
#define TRDC_MRC_DOM5_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM5_RGD_W_MRACSEL_MASK)

#define TRDC_MRC_DOM5_RGD_W_VLD_MASK             (0x1U)
#define TRDC_MRC_DOM5_RGD_W_VLD_SHIFT            (0U)
/*! VLD - Valid */
#define TRDC_MRC_DOM5_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM5_RGD_W_VLD_MASK)

#define TRDC_MRC_DOM5_RGD_W_NSE_MASK             (0x10U)
#define TRDC_MRC_DOM5_RGD_W_NSE_SHIFT            (4U)
/*! NSE - NonSecure Enable
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM5_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM5_RGD_W_NSE_MASK)

#define TRDC_MRC_DOM5_RGD_W_END_ADDR_MASK        (0xFFFFF000U)
#define TRDC_MRC_DOM5_RGD_W_END_ADDR_SHIFT       (12U)
/*! END_ADDR - End Address */
#define TRDC_MRC_DOM5_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM5_RGD_W_END_ADDR_MASK)

#define TRDC_MRC_DOM5_RGD_W_STRT_ADDR_MASK       (0xFFFFF000U)
#define TRDC_MRC_DOM5_RGD_W_STRT_ADDR_SHIFT      (12U)
/*! STRT_ADDR - Start Address */
#define TRDC_MRC_DOM5_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM5_RGD_W_STRT_ADDR_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM5_RGD_W */
#define TRDC_MRC_DOM5_RGD_W_COUNT                (2U)

/* The count of TRDC_MRC_DOM5_RGD_W */
#define TRDC_MRC_DOM5_RGD_W_COUNT2               (8U)

/* The count of TRDC_MRC_DOM5_RGD_W */
#define TRDC_MRC_DOM5_RGD_W_COUNT3               (2U)

/*! @name MRC_DOM5_RGD_NSE - MRC Region Descriptor NonSecure Enable */
/*! @{ */

#define TRDC_MRC_DOM5_RGD_NSE_BIT0_MASK          (0x1U)
#define TRDC_MRC_DOM5_RGD_NSE_BIT0_SHIFT         (0U)
/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM5_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT0_MASK)

#define TRDC_MRC_DOM5_RGD_NSE_BIT1_MASK          (0x2U)
#define TRDC_MRC_DOM5_RGD_NSE_BIT1_SHIFT         (1U)
/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM5_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT1_MASK)

#define TRDC_MRC_DOM5_RGD_NSE_BIT2_MASK          (0x4U)
#define TRDC_MRC_DOM5_RGD_NSE_BIT2_SHIFT         (2U)
/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM5_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT2_MASK)

#define TRDC_MRC_DOM5_RGD_NSE_BIT3_MASK          (0x8U)
#define TRDC_MRC_DOM5_RGD_NSE_BIT3_SHIFT         (3U)
/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM5_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT3_MASK)

#define TRDC_MRC_DOM5_RGD_NSE_BIT4_MASK          (0x10U)
#define TRDC_MRC_DOM5_RGD_NSE_BIT4_SHIFT         (4U)
/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM5_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT4_MASK)

#define TRDC_MRC_DOM5_RGD_NSE_BIT5_MASK          (0x20U)
#define TRDC_MRC_DOM5_RGD_NSE_BIT5_SHIFT         (5U)
/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM5_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT5_MASK)

#define TRDC_MRC_DOM5_RGD_NSE_BIT6_MASK          (0x40U)
#define TRDC_MRC_DOM5_RGD_NSE_BIT6_SHIFT         (6U)
/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM5_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT6_MASK)

#define TRDC_MRC_DOM5_RGD_NSE_BIT7_MASK          (0x80U)
#define TRDC_MRC_DOM5_RGD_NSE_BIT7_SHIFT         (7U)
/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM5_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT7_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM5_RGD_NSE */
#define TRDC_MRC_DOM5_RGD_NSE_COUNT              (2U)

/*! @name MRC_DOM6_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
/*! @{ */

#define TRDC_MRC_DOM6_RGD_W_MRACSEL_MASK         (0x7U)
#define TRDC_MRC_DOM6_RGD_W_MRACSEL_SHIFT        (0U)
/*! MRACSEL - Memory Region Access Control Select
 *  0b000..Select MRC_GLBAC0 access control policy
 *  0b001..Select MRC_GLBAC1 access control policy
 *  0b010..Select MRC_GLBAC2 access control policy
 *  0b011..Select MRC_GLBAC3 access control policy
 *  0b100..Select MRC_GLBAC4 access control policy
 *  0b101..Select MRC_GLBAC5 access control policy
 *  0b110..Select MRC_GLBAC6 access control policy
 *  0b111..Select MRC_GLBAC7 access control policy
 */
#define TRDC_MRC_DOM6_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM6_RGD_W_MRACSEL_MASK)

#define TRDC_MRC_DOM6_RGD_W_VLD_MASK             (0x1U)
#define TRDC_MRC_DOM6_RGD_W_VLD_SHIFT            (0U)
/*! VLD - Valid */
#define TRDC_MRC_DOM6_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM6_RGD_W_VLD_MASK)

#define TRDC_MRC_DOM6_RGD_W_NSE_MASK             (0x10U)
#define TRDC_MRC_DOM6_RGD_W_NSE_SHIFT            (4U)
/*! NSE - NonSecure Enable
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM6_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM6_RGD_W_NSE_MASK)

#define TRDC_MRC_DOM6_RGD_W_END_ADDR_MASK        (0xFFFFF000U)
#define TRDC_MRC_DOM6_RGD_W_END_ADDR_SHIFT       (12U)
/*! END_ADDR - End Address */
#define TRDC_MRC_DOM6_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM6_RGD_W_END_ADDR_MASK)

#define TRDC_MRC_DOM6_RGD_W_STRT_ADDR_MASK       (0xFFFFF000U)
#define TRDC_MRC_DOM6_RGD_W_STRT_ADDR_SHIFT      (12U)
/*! STRT_ADDR - Start Address */
#define TRDC_MRC_DOM6_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM6_RGD_W_STRT_ADDR_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM6_RGD_W */
#define TRDC_MRC_DOM6_RGD_W_COUNT                (2U)

/* The count of TRDC_MRC_DOM6_RGD_W */
#define TRDC_MRC_DOM6_RGD_W_COUNT2               (8U)

/* The count of TRDC_MRC_DOM6_RGD_W */
#define TRDC_MRC_DOM6_RGD_W_COUNT3               (2U)

/*! @name MRC_DOM6_RGD_NSE - MRC Region Descriptor NonSecure Enable */
/*! @{ */

#define TRDC_MRC_DOM6_RGD_NSE_BIT0_MASK          (0x1U)
#define TRDC_MRC_DOM6_RGD_NSE_BIT0_SHIFT         (0U)
/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM6_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT0_MASK)

#define TRDC_MRC_DOM6_RGD_NSE_BIT1_MASK          (0x2U)
#define TRDC_MRC_DOM6_RGD_NSE_BIT1_SHIFT         (1U)
/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM6_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT1_MASK)

#define TRDC_MRC_DOM6_RGD_NSE_BIT2_MASK          (0x4U)
#define TRDC_MRC_DOM6_RGD_NSE_BIT2_SHIFT         (2U)
/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM6_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT2_MASK)

#define TRDC_MRC_DOM6_RGD_NSE_BIT3_MASK          (0x8U)
#define TRDC_MRC_DOM6_RGD_NSE_BIT3_SHIFT         (3U)
/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM6_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT3_MASK)

#define TRDC_MRC_DOM6_RGD_NSE_BIT4_MASK          (0x10U)
#define TRDC_MRC_DOM6_RGD_NSE_BIT4_SHIFT         (4U)
/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM6_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT4_MASK)

#define TRDC_MRC_DOM6_RGD_NSE_BIT5_MASK          (0x20U)
#define TRDC_MRC_DOM6_RGD_NSE_BIT5_SHIFT         (5U)
/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM6_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT5_MASK)

#define TRDC_MRC_DOM6_RGD_NSE_BIT6_MASK          (0x40U)
#define TRDC_MRC_DOM6_RGD_NSE_BIT6_SHIFT         (6U)
/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM6_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT6_MASK)

#define TRDC_MRC_DOM6_RGD_NSE_BIT7_MASK          (0x80U)
#define TRDC_MRC_DOM6_RGD_NSE_BIT7_SHIFT         (7U)
/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM6_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT7_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM6_RGD_NSE */
#define TRDC_MRC_DOM6_RGD_NSE_COUNT              (2U)

/*! @name MRC_DOM7_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
/*! @{ */

#define TRDC_MRC_DOM7_RGD_W_MRACSEL_MASK         (0x7U)
#define TRDC_MRC_DOM7_RGD_W_MRACSEL_SHIFT        (0U)
/*! MRACSEL - Memory Region Access Control Select
 *  0b000..Select MRC_GLBAC0 access control policy
 *  0b001..Select MRC_GLBAC1 access control policy
 *  0b010..Select MRC_GLBAC2 access control policy
 *  0b011..Select MRC_GLBAC3 access control policy
 *  0b100..Select MRC_GLBAC4 access control policy
 *  0b101..Select MRC_GLBAC5 access control policy
 *  0b110..Select MRC_GLBAC6 access control policy
 *  0b111..Select MRC_GLBAC7 access control policy
 */
#define TRDC_MRC_DOM7_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM7_RGD_W_MRACSEL_MASK)

#define TRDC_MRC_DOM7_RGD_W_VLD_MASK             (0x1U)
#define TRDC_MRC_DOM7_RGD_W_VLD_SHIFT            (0U)
/*! VLD - Valid */
#define TRDC_MRC_DOM7_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM7_RGD_W_VLD_MASK)

#define TRDC_MRC_DOM7_RGD_W_NSE_MASK             (0x10U)
#define TRDC_MRC_DOM7_RGD_W_NSE_SHIFT            (4U)
/*! NSE - NonSecure Enable
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM7_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM7_RGD_W_NSE_MASK)

#define TRDC_MRC_DOM7_RGD_W_END_ADDR_MASK        (0xFFFFF000U)
#define TRDC_MRC_DOM7_RGD_W_END_ADDR_SHIFT       (12U)
/*! END_ADDR - End Address */
#define TRDC_MRC_DOM7_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM7_RGD_W_END_ADDR_MASK)

#define TRDC_MRC_DOM7_RGD_W_STRT_ADDR_MASK       (0xFFFFF000U)
#define TRDC_MRC_DOM7_RGD_W_STRT_ADDR_SHIFT      (12U)
/*! STRT_ADDR - Start Address */
#define TRDC_MRC_DOM7_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM7_RGD_W_STRT_ADDR_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM7_RGD_W */
#define TRDC_MRC_DOM7_RGD_W_COUNT                (2U)

/* The count of TRDC_MRC_DOM7_RGD_W */
#define TRDC_MRC_DOM7_RGD_W_COUNT2               (8U)

/* The count of TRDC_MRC_DOM7_RGD_W */
#define TRDC_MRC_DOM7_RGD_W_COUNT3               (2U)

/*! @name MRC_DOM7_RGD_NSE - MRC Region Descriptor NonSecure Enable */
/*! @{ */

#define TRDC_MRC_DOM7_RGD_NSE_BIT0_MASK          (0x1U)
#define TRDC_MRC_DOM7_RGD_NSE_BIT0_SHIFT         (0U)
/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM7_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT0_MASK)

#define TRDC_MRC_DOM7_RGD_NSE_BIT1_MASK          (0x2U)
#define TRDC_MRC_DOM7_RGD_NSE_BIT1_SHIFT         (1U)
/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM7_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT1_MASK)

#define TRDC_MRC_DOM7_RGD_NSE_BIT2_MASK          (0x4U)
#define TRDC_MRC_DOM7_RGD_NSE_BIT2_SHIFT         (2U)
/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM7_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT2_MASK)

#define TRDC_MRC_DOM7_RGD_NSE_BIT3_MASK          (0x8U)
#define TRDC_MRC_DOM7_RGD_NSE_BIT3_SHIFT         (3U)
/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM7_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT3_MASK)

#define TRDC_MRC_DOM7_RGD_NSE_BIT4_MASK          (0x10U)
#define TRDC_MRC_DOM7_RGD_NSE_BIT4_SHIFT         (4U)
/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM7_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT4_MASK)

#define TRDC_MRC_DOM7_RGD_NSE_BIT5_MASK          (0x20U)
#define TRDC_MRC_DOM7_RGD_NSE_BIT5_SHIFT         (5U)
/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM7_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT5_MASK)

#define TRDC_MRC_DOM7_RGD_NSE_BIT6_MASK          (0x40U)
#define TRDC_MRC_DOM7_RGD_NSE_BIT6_SHIFT         (6U)
/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM7_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT6_MASK)

#define TRDC_MRC_DOM7_RGD_NSE_BIT7_MASK          (0x80U)
#define TRDC_MRC_DOM7_RGD_NSE_BIT7_SHIFT         (7U)
/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM7_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT7_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM7_RGD_NSE */
#define TRDC_MRC_DOM7_RGD_NSE_COUNT              (2U)


/*!
 * @}
 */ /* end of group TRDC_Register_Masks */


/* TRDC - Peripheral instance base addresses */
/** Peripheral TRDC base address */
#define TRDC_BASE                                (0x28031000u)
/** Peripheral TRDC base pointer */
#define TRDC                                     ((TRDC_Type *)TRDC_BASE)
/** Array initializer of TRDC peripheral base addresses */
#define TRDC_BASE_ADDRS                          { TRDC_BASE }
/** Array initializer of TRDC peripheral base pointers */
#define TRDC_BASE_PTRS                           { TRDC }

/*!
 * @}
 */ /* end of group TRDC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TRGMUX Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer
 * @{
 */

/** TRGMUX - Register Layout Typedef */
typedef struct {
  __IO uint32_t TRGCFG[25];                        /**< TRGMUX LPIT0 Register..TRGMUX DAC1 Register, array offset: 0x0, array step: 0x4, irregular array, not all indices are valid */
} TRGMUX_Type;

/* ----------------------------------------------------------------------------
   -- TRGMUX Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks
 * @{
 */

/*! @name TRGCFG - TRGMUX LPIT0 Register..TRGMUX DAC1 Register */
/*! @{ */

#define TRGMUX_TRGCFG_SEL0_MASK                  (0x7FU)
#define TRGMUX_TRGCFG_SEL0_SHIFT                 (0U)
/*! SEL0 - Trigger MUX Input 0 Source Select */
#define TRGMUX_TRGCFG_SEL0(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL0_SHIFT)) & TRGMUX_TRGCFG_SEL0_MASK)

#define TRGMUX_TRGCFG_SEL1_MASK                  (0x7F00U)
#define TRGMUX_TRGCFG_SEL1_SHIFT                 (8U)
/*! SEL1 - Trigger MUX Input 1 Source Select */
#define TRGMUX_TRGCFG_SEL1(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL1_SHIFT)) & TRGMUX_TRGCFG_SEL1_MASK)

#define TRGMUX_TRGCFG_SEL2_MASK                  (0x7F0000U)
#define TRGMUX_TRGCFG_SEL2_SHIFT                 (16U)
/*! SEL2 - Trigger MUX Input 2 Source Select */
#define TRGMUX_TRGCFG_SEL2(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL2_SHIFT)) & TRGMUX_TRGCFG_SEL2_MASK)

#define TRGMUX_TRGCFG_SEL3_MASK                  (0x7F000000U)
#define TRGMUX_TRGCFG_SEL3_SHIFT                 (24U)
/*! SEL3 - Trigger MUX Input 3 Source Select */
#define TRGMUX_TRGCFG_SEL3(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL3_SHIFT)) & TRGMUX_TRGCFG_SEL3_MASK)

#define TRGMUX_TRGCFG_LK_MASK                    (0x80000000U)
#define TRGMUX_TRGCFG_LK_SHIFT                   (31U)
/*! LK - TRGMUX register lock.
 *  0b0..Register can be written.
 *  0b1..Register cannot be written until the next system Reset.
 */
#define TRGMUX_TRGCFG_LK(x)                      (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_LK_SHIFT)) & TRGMUX_TRGCFG_LK_MASK)
/*! @} */

/* The count of TRGMUX_TRGCFG */
#define TRGMUX_TRGCFG_COUNT                      (25U)


/*!
 * @}
 */ /* end of group TRGMUX_Register_Masks */


/* TRGMUX - Peripheral instance base addresses */
/** Peripheral TRGMUX0 base address */
#define TRGMUX0_BASE                             (0x28027000u)
/** Peripheral TRGMUX0 base pointer */
#define TRGMUX0                                  ((TRGMUX_Type *)TRGMUX0_BASE)
/** Peripheral TRGMUX1 base address */
#define TRGMUX1_BASE                             (0x29250000u)
/** Peripheral TRGMUX1 base pointer */
#define TRGMUX1                                  ((TRGMUX_Type *)TRGMUX1_BASE)
/** Array initializer of TRGMUX peripheral base addresses */
#define TRGMUX_BASE_ADDRS                        { TRGMUX0_BASE, TRGMUX1_BASE }
/** Array initializer of TRGMUX peripheral base pointers */
#define TRGMUX_BASE_PTRS                         { TRGMUX0, TRGMUX1 }

/*!
 * @}
 */ /* end of group TRGMUX_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TSTMR Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer
 * @{
 */

/** TSTMR - Register Layout Typedef */
typedef struct {
  __I  uint32_t L;                                 /**< Time Stamp Timer Register Low, offset: 0x0 */
  __I  uint32_t H;                                 /**< Time Stamp Timer Register High, offset: 0x4 */
} TSTMR_Type;

/* ----------------------------------------------------------------------------
   -- TSTMR Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TSTMR_Register_Masks TSTMR Register Masks
 * @{
 */

/*! @name L - Time Stamp Timer Register Low */
/*! @{ */

#define TSTMR_L_VALUE_MASK                       (0xFFFFFFFFU)
#define TSTMR_L_VALUE_SHIFT                      (0U)
/*! VALUE - Time Stamp Timer Low */
#define TSTMR_L_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK)
/*! @} */

/*! @name H - Time Stamp Timer Register High */
/*! @{ */

#define TSTMR_H_VALUE_MASK                       (0xFFFFFFFFU)
#define TSTMR_H_VALUE_SHIFT                      (0U)
/*! VALUE - Time Stamp Timer High */
#define TSTMR_H_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group TSTMR_Register_Masks */


/* TSTMR - Peripheral instance base addresses */
/** Peripheral TSTMR0__TIMESTAMP0 base address */
#define TSTMR0__TIMESTAMP0_BASE                  (0x2802AC00u)
/** Peripheral TSTMR0__TIMESTAMP0 base pointer */
#define TSTMR0__TIMESTAMP0                       ((TSTMR_Type *)TSTMR0__TIMESTAMP0_BASE)
/** Peripheral TSTMR1__TIMESTAMP0 base address */
#define TSTMR1__TIMESTAMP0_BASE                  (0x29290C00u)
/** Peripheral TSTMR1__TIMESTAMP0 base pointer */
#define TSTMR1__TIMESTAMP0                       ((TSTMR_Type *)TSTMR1__TIMESTAMP0_BASE)
/** Array initializer of TSTMR peripheral base addresses */
#define TSTMR_BASE_ADDRS                         { TSTMR0__TIMESTAMP0_BASE, TSTMR1__TIMESTAMP0_BASE }
/** Array initializer of TSTMR peripheral base pointers */
#define TSTMR_BASE_PTRS                          { TSTMR0__TIMESTAMP0, TSTMR1__TIMESTAMP0 }

/*!
 * @}
 */ /* end of group TSTMR_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USB Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
 * @{
 */

/** USB - Register Layout Typedef */
typedef struct {
  __I  uint32_t ID;                                /**< Identification register, offset: 0x0 */
  __I  uint32_t HWGENERAL;                         /**< Hardware General, offset: 0x4 */
  __I  uint32_t HWHOST;                            /**< Host Hardware Parameters, offset: 0x8 */
  __I  uint32_t HWDEVICE;                          /**< Device Hardware Parameters, offset: 0xC */
  __I  uint32_t HWTXBUF;                           /**< TX Buffer Hardware Parameters, offset: 0x10 */
  __I  uint32_t HWRXBUF;                           /**< RX Buffer Hardware Parameters, offset: 0x14 */
       uint8_t RESERVED_0[104];
  __IO uint32_t GPTIMER0LD;                        /**< General Purpose Timer #0 Load, offset: 0x80 */
  __IO uint32_t GPTIMER0CTRL;                      /**< General Purpose Timer #0 Controller, offset: 0x84 */
  __IO uint32_t GPTIMER1LD;                        /**< General Purpose Timer #1 Load, offset: 0x88 */
  __IO uint32_t GPTIMER1CTRL;                      /**< General Purpose Timer #1 Controller, offset: 0x8C */
  __IO uint32_t SBUSCFG;                           /**< System Bus Config, offset: 0x90 */
       uint8_t RESERVED_1[108];
  __I  uint8_t CAPLENGTH;                          /**< Capability Registers Length, offset: 0x100 */
       uint8_t RESERVED_2[1];
  __I  uint16_t HCIVERSION;                        /**< Host Controller Interface Version, offset: 0x102 */
  __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x104 */
  __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x108 */
       uint8_t RESERVED_3[20];
  __I  uint16_t DCIVERSION;                        /**< Device Controller Interface Version, offset: 0x120 */
       uint8_t RESERVED_4[2];
  __I  uint32_t DCCPARAMS;                         /**< Device Controller Capability Parameters, offset: 0x124 */
       uint8_t RESERVED_5[24];
  __IO uint32_t USBCMD;                            /**< USB Command Register, offset: 0x140 */
  __IO uint32_t USBSTS;                            /**< USB Status Register, offset: 0x144 */
  __IO uint32_t USBINTR;                           /**< Interrupt Enable Register, offset: 0x148 */
  __IO uint32_t FRINDEX;                           /**< USB Frame Index, offset: 0x14C */
       uint8_t RESERVED_6[4];
  union {                                          /* offset: 0x154 */
    __IO uint32_t DEVICEADDR;                        /**< Device Address, offset: 0x154 */
    __IO uint32_t PERIODICLISTBASE;                  /**< Frame List Base Address, offset: 0x154 */
  };
  union {                                          /* offset: 0x158 */
    __IO uint32_t ASYNCLISTADDR;                     /**< Next Asynch. Address, offset: 0x158 */
    __IO uint32_t ENDPTLISTADDR;                     /**< Endpoint List Address, offset: 0x158 */
  };
       uint8_t RESERVED_7[4];
  __IO uint32_t BURSTSIZE;                         /**< Programmable Burst Size, offset: 0x160 */
  __IO uint32_t TXFILLTUNING;                      /**< TX FIFO Fill Tuning, offset: 0x164 */
       uint8_t RESERVED_8[16];
  __IO uint32_t ENDPTNAK;                          /**< Endpoint NAK, offset: 0x178 */
  __IO uint32_t ENDPTNAKEN;                        /**< Endpoint NAK Enable, offset: 0x17C */
  __I  uint32_t CONFIGFLAG;                        /**< Configure Flag Register, offset: 0x180 */
  __IO uint32_t PORTSC1;                           /**< Port Status & Control, offset: 0x184 */
       uint8_t RESERVED_9[28];
  __IO uint32_t OTGSC;                             /**< On-The-Go Status & control, offset: 0x1A4 */
  __IO uint32_t USBMODE;                           /**< USB Device Mode, offset: 0x1A8 */
  __IO uint32_t ENDPTSETUPSTAT;                    /**< Endpoint Setup Status, offset: 0x1AC */
  __IO uint32_t ENDPTPRIME;                        /**< Endpoint Prime, offset: 0x1B0 */
  __IO uint32_t ENDPTFLUSH;                        /**< Endpoint Flush, offset: 0x1B4 */
  __I  uint32_t ENDPTSTAT;                         /**< Endpoint Status, offset: 0x1B8 */
  __IO uint32_t ENDPTCOMPLETE;                     /**< Endpoint Complete, offset: 0x1BC */
  __IO uint32_t ENDPTCTRL0;                        /**< Endpoint Control0, offset: 0x1C0 */
  __IO uint32_t ENDPTCTRL[7];                      /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */
} USB_Type;

/* ----------------------------------------------------------------------------
   -- USB Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USB_Register_Masks USB Register Masks
 * @{
 */

/*! @name ID - Identification register */
/*! @{ */

#define USB_ID_ID_MASK                           (0x3FU)
#define USB_ID_ID_SHIFT                          (0U)
/*! ID - ID */
#define USB_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)

#define USB_ID_NID_MASK                          (0x3F00U)
#define USB_ID_NID_SHIFT                         (8U)
/*! NID - NID */
#define USB_ID_NID(x)                            (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)

#define USB_ID_REVISION_MASK                     (0xFF0000U)
#define USB_ID_REVISION_SHIFT                    (16U)
/*! REVISION - REVISION */
#define USB_ID_REVISION(x)                       (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
/*! @} */

/*! @name HWGENERAL - Hardware General */
/*! @{ */

#define USB_HWGENERAL_PHYW_MASK                  (0x30U)
#define USB_HWGENERAL_PHYW_SHIFT                 (4U)
/*! PHYW - PHYW
 *  0b00..8 bit wide data bus (Software non-programmable)
 *  0b01..16 bit wide data bus (Software non-programmable)
 *  0b10..Reset to 8 bit wide data bus (Software programmable)
 *  0b11..Reset to 16 bit wide data bus (Software programmable)
 */
#define USB_HWGENERAL_PHYW(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)

#define USB_HWGENERAL_PHYM_MASK                  (0x1C0U)
#define USB_HWGENERAL_PHYM_SHIFT                 (6U)
/*! PHYM - PHYM
 *  0b000..UTMI/UMTI+
 *  0b001..ULPI DDR
 *  0b010..ULPI
 *  0b011..Serial Only
 *  0b100..Software programmable - reset to UTMI/UTMI+
 *  0b101..Software programmable - reset to ULPI DDR
 *  0b110..Software programmable - reset to ULPI
 *  0b111..Software programmable - reset to Serial
 */
#define USB_HWGENERAL_PHYM(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)

#define USB_HWGENERAL_SM_MASK                    (0x600U)
#define USB_HWGENERAL_SM_SHIFT                   (9U)
/*! SM - SM
 *  0b00..No Serial Engine, always use parallel signalling.
 *  0b01..Serial Engine present, always use serial signalling for FS/LS.
 *  0b10..Software programmable - Reset to use parallel signalling for FS/LS
 *  0b11..Software programmable - Reset to use serial signalling for FS/LS
 */
#define USB_HWGENERAL_SM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
/*! @} */

/*! @name HWHOST - Host Hardware Parameters */
/*! @{ */

#define USB_HWHOST_HC_MASK                       (0x1U)
#define USB_HWHOST_HC_SHIFT                      (0U)
/*! HC - HC
 *  0b1..Supported
 *  0b0..Not supported
 */
#define USB_HWHOST_HC(x)                         (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)

#define USB_HWHOST_NPORT_MASK                    (0xEU)
#define USB_HWHOST_NPORT_SHIFT                   (1U)
/*! NPORT - NPORT */
#define USB_HWHOST_NPORT(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
/*! @} */

/*! @name HWDEVICE - Device Hardware Parameters */
/*! @{ */

#define USB_HWDEVICE_DC_MASK                     (0x1U)
#define USB_HWDEVICE_DC_SHIFT                    (0U)
/*! DC - DC
 *  0b1..Supported
 *  0b0..Not supported
 */
#define USB_HWDEVICE_DC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)

#define USB_HWDEVICE_DEVEP_MASK                  (0x3EU)
#define USB_HWDEVICE_DEVEP_SHIFT                 (1U)
/*! DEVEP - DEVEP */
#define USB_HWDEVICE_DEVEP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
/*! @} */

/*! @name HWTXBUF - TX Buffer Hardware Parameters */
/*! @{ */

#define USB_HWTXBUF_TXBURST_MASK                 (0xFFU)
#define USB_HWTXBUF_TXBURST_SHIFT                (0U)
/*! TXBURST - TXBURST */
#define USB_HWTXBUF_TXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)

#define USB_HWTXBUF_TXCHANADD_MASK               (0xFF0000U)
#define USB_HWTXBUF_TXCHANADD_SHIFT              (16U)
/*! TXCHANADD - TXCHANADD */
#define USB_HWTXBUF_TXCHANADD(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
/*! @} */

/*! @name HWRXBUF - RX Buffer Hardware Parameters */
/*! @{ */

#define USB_HWRXBUF_RXBURST_MASK                 (0xFFU)
#define USB_HWRXBUF_RXBURST_SHIFT                (0U)
/*! RXBURST - RXBURST */
#define USB_HWRXBUF_RXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)

#define USB_HWRXBUF_RXADD_MASK                   (0xFF00U)
#define USB_HWRXBUF_RXADD_SHIFT                  (8U)
/*! RXADD - RXADD */
#define USB_HWRXBUF_RXADD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
/*! @} */

/*! @name GPTIMER0LD - General Purpose Timer #0 Load */
/*! @{ */

#define USB_GPTIMER0LD_GPTLD_MASK                (0xFFFFFFU)
#define USB_GPTIMER0LD_GPTLD_SHIFT               (0U)
/*! GPTLD - GPTLD */
#define USB_GPTIMER0LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
/*! @} */

/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */
/*! @{ */

#define USB_GPTIMER0CTRL_GPTCNT_MASK             (0xFFFFFFU)
#define USB_GPTIMER0CTRL_GPTCNT_SHIFT            (0U)
/*! GPTCNT - GPTCNT */
#define USB_GPTIMER0CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)

#define USB_GPTIMER0CTRL_GPTMODE_MASK            (0x1000000U)
#define USB_GPTIMER0CTRL_GPTMODE_SHIFT           (24U)
/*! GPTMODE - GPTMODE
 *  0b0..One Shot Mode
 *  0b1..Repeat Mode
 */
#define USB_GPTIMER0CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)

#define USB_GPTIMER0CTRL_GPTRST_MASK             (0x40000000U)
#define USB_GPTIMER0CTRL_GPTRST_SHIFT            (30U)
/*! GPTRST - GPTRST
 *  0b0..No action
 *  0b1..Load counter value from GPTLD bits in n_GPTIMER0LD
 */
#define USB_GPTIMER0CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)

#define USB_GPTIMER0CTRL_GPTRUN_MASK             (0x80000000U)
#define USB_GPTIMER0CTRL_GPTRUN_SHIFT            (31U)
/*! GPTRUN - GPTRUN
 *  0b0..Stop counting
 *  0b1..Run
 */
#define USB_GPTIMER0CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
/*! @} */

/*! @name GPTIMER1LD - General Purpose Timer #1 Load */
/*! @{ */

#define USB_GPTIMER1LD_GPTLD_MASK                (0xFFFFFFU)
#define USB_GPTIMER1LD_GPTLD_SHIFT               (0U)
/*! GPTLD - GPTLD */
#define USB_GPTIMER1LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
/*! @} */

/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */
/*! @{ */

#define USB_GPTIMER1CTRL_GPTCNT_MASK             (0xFFFFFFU)
#define USB_GPTIMER1CTRL_GPTCNT_SHIFT            (0U)
/*! GPTCNT - GPTCNT */
#define USB_GPTIMER1CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)

#define USB_GPTIMER1CTRL_GPTMODE_MASK            (0x1000000U)
#define USB_GPTIMER1CTRL_GPTMODE_SHIFT           (24U)
/*! GPTMODE - GPTMODE
 *  0b0..One Shot Mode
 *  0b1..Repeat Mode
 */
#define USB_GPTIMER1CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)

#define USB_GPTIMER1CTRL_GPTRST_MASK             (0x40000000U)
#define USB_GPTIMER1CTRL_GPTRST_SHIFT            (30U)
/*! GPTRST - GPTRST
 *  0b0..No action
 *  0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD
 */
#define USB_GPTIMER1CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)

#define USB_GPTIMER1CTRL_GPTRUN_MASK             (0x80000000U)
#define USB_GPTIMER1CTRL_GPTRUN_SHIFT            (31U)
/*! GPTRUN - GPTRUN
 *  0b0..Stop counting
 *  0b1..Run
 */
#define USB_GPTIMER1CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
/*! @} */

/*! @name SBUSCFG - System Bus Config */
/*! @{ */

#define USB_SBUSCFG_AHBBRST_MASK                 (0x7U)
#define USB_SBUSCFG_AHBBRST_SHIFT                (0U)
/*! AHBBRST - AHBBRST
 *  0b000..Incremental burst of unspecified length only
 *  0b001..INCR4 burst, then single transfer
 *  0b010..INCR8 burst, INCR4 burst, then single transfer
 *  0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer
 *  0b100..Reserved, don't use
 *  0b101..INCR4 burst, then incremental burst of unspecified length
 *  0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length
 *  0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length
 */
#define USB_SBUSCFG_AHBBRST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
/*! @} */

/*! @name CAPLENGTH - Capability Registers Length */
/*! @{ */

#define USB_CAPLENGTH_CAPLENGTH_MASK             (0xFFU)
#define USB_CAPLENGTH_CAPLENGTH_SHIFT            (0U)
/*! CAPLENGTH - CAPLENGTH */
#define USB_CAPLENGTH_CAPLENGTH(x)               (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
/*! @} */

/*! @name HCIVERSION - Host Controller Interface Version */
/*! @{ */

#define USB_HCIVERSION_HCIVERSION_MASK           (0xFFFFU)
#define USB_HCIVERSION_HCIVERSION_SHIFT          (0U)
/*! HCIVERSION - HCIVERSION */
#define USB_HCIVERSION_HCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
/*! @} */

/*! @name HCSPARAMS - Host Controller Structural Parameters */
/*! @{ */

#define USB_HCSPARAMS_N_PORTS_MASK               (0xFU)
#define USB_HCSPARAMS_N_PORTS_SHIFT              (0U)
/*! N_PORTS - N_PORTS */
#define USB_HCSPARAMS_N_PORTS(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)

#define USB_HCSPARAMS_PPC_MASK                   (0x10U)
#define USB_HCSPARAMS_PPC_SHIFT                  (4U)
/*! PPC - PPC */
#define USB_HCSPARAMS_PPC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)

#define USB_HCSPARAMS_N_PCC_MASK                 (0xF00U)
#define USB_HCSPARAMS_N_PCC_SHIFT                (8U)
/*! N_PCC - N_PCC */
#define USB_HCSPARAMS_N_PCC(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)

#define USB_HCSPARAMS_N_CC_MASK                  (0xF000U)
#define USB_HCSPARAMS_N_CC_SHIFT                 (12U)
/*! N_CC - N_CC
 *  0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported.
 *  0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported.
 */
#define USB_HCSPARAMS_N_CC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)

#define USB_HCSPARAMS_PI_MASK                    (0x10000U)
#define USB_HCSPARAMS_PI_SHIFT                   (16U)
/*! PI - PI */
#define USB_HCSPARAMS_PI(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)

#define USB_HCSPARAMS_N_PTT_MASK                 (0xF00000U)
#define USB_HCSPARAMS_N_PTT_SHIFT                (20U)
/*! N_PTT - N_PTT */
#define USB_HCSPARAMS_N_PTT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)

#define USB_HCSPARAMS_N_TT_MASK                  (0xF000000U)
#define USB_HCSPARAMS_N_TT_SHIFT                 (24U)
/*! N_TT - N_TT */
#define USB_HCSPARAMS_N_TT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
/*! @} */

/*! @name HCCPARAMS - Host Controller Capability Parameters */
/*! @{ */

#define USB_HCCPARAMS_ADC_MASK                   (0x1U)
#define USB_HCCPARAMS_ADC_SHIFT                  (0U)
/*! ADC - ADC */
#define USB_HCCPARAMS_ADC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)

#define USB_HCCPARAMS_PFL_MASK                   (0x2U)
#define USB_HCCPARAMS_PFL_SHIFT                  (1U)
/*! PFL - PFL */
#define USB_HCCPARAMS_PFL(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)

#define USB_HCCPARAMS_ASP_MASK                   (0x4U)
#define USB_HCCPARAMS_ASP_SHIFT                  (2U)
/*! ASP - ASP */
#define USB_HCCPARAMS_ASP(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)

#define USB_HCCPARAMS_IST_MASK                   (0xF0U)
#define USB_HCCPARAMS_IST_SHIFT                  (4U)
/*! IST - IST */
#define USB_HCCPARAMS_IST(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)

#define USB_HCCPARAMS_EECP_MASK                  (0xFF00U)
#define USB_HCCPARAMS_EECP_SHIFT                 (8U)
/*! EECP - EECP */
#define USB_HCCPARAMS_EECP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
/*! @} */

/*! @name DCIVERSION - Device Controller Interface Version */
/*! @{ */

#define USB_DCIVERSION_DCIVERSION_MASK           (0xFFFFU)
#define USB_DCIVERSION_DCIVERSION_SHIFT          (0U)
/*! DCIVERSION - DCIVERSION */
#define USB_DCIVERSION_DCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
/*! @} */

/*! @name DCCPARAMS - Device Controller Capability Parameters */
/*! @{ */

#define USB_DCCPARAMS_DEN_MASK                   (0x1FU)
#define USB_DCCPARAMS_DEN_SHIFT                  (0U)
/*! DEN - DEN */
#define USB_DCCPARAMS_DEN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)

#define USB_DCCPARAMS_DC_MASK                    (0x80U)
#define USB_DCCPARAMS_DC_SHIFT                   (7U)
/*! DC - DC */
#define USB_DCCPARAMS_DC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)

#define USB_DCCPARAMS_HC_MASK                    (0x100U)
#define USB_DCCPARAMS_HC_SHIFT                   (8U)
/*! HC - HC */
#define USB_DCCPARAMS_HC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
/*! @} */

/*! @name USBCMD - USB Command Register */
/*! @{ */

#define USB_USBCMD_RS_MASK                       (0x1U)
#define USB_USBCMD_RS_SHIFT                      (0U)
/*! RS - RS */
#define USB_USBCMD_RS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)

#define USB_USBCMD_RST_MASK                      (0x2U)
#define USB_USBCMD_RST_SHIFT                     (1U)
/*! RST - RST */
#define USB_USBCMD_RST(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)

#define USB_USBCMD_FS_1_MASK                     (0xCU)
#define USB_USBCMD_FS_1_SHIFT                    (2U)
/*! FS_1 - FS_1 */
#define USB_USBCMD_FS_1(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)

#define USB_USBCMD_PSE_MASK                      (0x10U)
#define USB_USBCMD_PSE_SHIFT                     (4U)
/*! PSE - PSE
 *  0b0..Do not process the Periodic Schedule
 *  0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule.
 */
#define USB_USBCMD_PSE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)

#define USB_USBCMD_ASE_MASK                      (0x20U)
#define USB_USBCMD_ASE_SHIFT                     (5U)
/*! ASE - ASE
 *  0b0..Do not process the Asynchronous Schedule.
 *  0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
 */
#define USB_USBCMD_ASE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)

#define USB_USBCMD_IAA_MASK                      (0x40U)
#define USB_USBCMD_IAA_SHIFT                     (6U)
/*! IAA - IAA */
#define USB_USBCMD_IAA(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)

#define USB_USBCMD_ASP_MASK                      (0x300U)
#define USB_USBCMD_ASP_SHIFT                     (8U)
/*! ASP - ASP */
#define USB_USBCMD_ASP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)

#define USB_USBCMD_ASPE_MASK                     (0x800U)
#define USB_USBCMD_ASPE_SHIFT                    (11U)
/*! ASPE - ASPE */
#define USB_USBCMD_ASPE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)

#define USB_USBCMD_SUTW_MASK                     (0x2000U)
#define USB_USBCMD_SUTW_SHIFT                    (13U)
/*! SUTW - SUTW */
#define USB_USBCMD_SUTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)

#define USB_USBCMD_ATDTW_MASK                    (0x4000U)
#define USB_USBCMD_ATDTW_SHIFT                   (14U)
/*! ATDTW - ATDTW */
#define USB_USBCMD_ATDTW(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)

#define USB_USBCMD_FS_2_MASK                     (0x8000U)
#define USB_USBCMD_FS_2_SHIFT                    (15U)
/*! FS_2 - FS_2 */
#define USB_USBCMD_FS_2(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)

#define USB_USBCMD_ITC_MASK                      (0xFF0000U)
#define USB_USBCMD_ITC_SHIFT                     (16U)
/*! ITC - ITC
 *  0b00000000..Immediate (no threshold)
 *  0b00000001..1 micro-frame
 *  0b00000010..2 micro-frames
 *  0b00000100..4 micro-frames
 *  0b00001000..8 micro-frames
 *  0b00010000..16 micro-frames
 *  0b00100000..32 micro-frames
 *  0b01000000..64 micro-frames
 */
#define USB_USBCMD_ITC(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
/*! @} */

/*! @name USBSTS - USB Status Register */
/*! @{ */

#define USB_USBSTS_UI_MASK                       (0x1U)
#define USB_USBSTS_UI_SHIFT                      (0U)
/*! UI - UI */
#define USB_USBSTS_UI(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)

#define USB_USBSTS_UEI_MASK                      (0x2U)
#define USB_USBSTS_UEI_SHIFT                     (1U)
/*! UEI - UEI */
#define USB_USBSTS_UEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)

#define USB_USBSTS_PCI_MASK                      (0x4U)
#define USB_USBSTS_PCI_SHIFT                     (2U)
/*! PCI - PCI */
#define USB_USBSTS_PCI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)

#define USB_USBSTS_FRI_MASK                      (0x8U)
#define USB_USBSTS_FRI_SHIFT                     (3U)
/*! FRI - FRI */
#define USB_USBSTS_FRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)

#define USB_USBSTS_SEI_MASK                      (0x10U)
#define USB_USBSTS_SEI_SHIFT                     (4U)
/*! SEI - SEI */
#define USB_USBSTS_SEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)

#define USB_USBSTS_AAI_MASK                      (0x20U)
#define USB_USBSTS_AAI_SHIFT                     (5U)
/*! AAI - AAI */
#define USB_USBSTS_AAI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)

#define USB_USBSTS_URI_MASK                      (0x40U)
#define USB_USBSTS_URI_SHIFT                     (6U)
/*! URI - URI */
#define USB_USBSTS_URI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)

#define USB_USBSTS_SRI_MASK                      (0x80U)
#define USB_USBSTS_SRI_SHIFT                     (7U)
/*! SRI - SRI */
#define USB_USBSTS_SRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)

#define USB_USBSTS_SLI_MASK                      (0x100U)
#define USB_USBSTS_SLI_SHIFT                     (8U)
/*! SLI - SLI */
#define USB_USBSTS_SLI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)

#define USB_USBSTS_ULPII_MASK                    (0x400U)
#define USB_USBSTS_ULPII_SHIFT                   (10U)
/*! ULPII - ULPII */
#define USB_USBSTS_ULPII(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)

#define USB_USBSTS_HCH_MASK                      (0x1000U)
#define USB_USBSTS_HCH_SHIFT                     (12U)
/*! HCH - HCH */
#define USB_USBSTS_HCH(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)

#define USB_USBSTS_RCL_MASK                      (0x2000U)
#define USB_USBSTS_RCL_SHIFT                     (13U)
/*! RCL - RCL */
#define USB_USBSTS_RCL(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)

#define USB_USBSTS_PS_MASK                       (0x4000U)
#define USB_USBSTS_PS_SHIFT                      (14U)
/*! PS - PS */
#define USB_USBSTS_PS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)

#define USB_USBSTS_AS_MASK                       (0x8000U)
#define USB_USBSTS_AS_SHIFT                      (15U)
/*! AS - AS */
#define USB_USBSTS_AS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)

#define USB_USBSTS_NAKI_MASK                     (0x10000U)
#define USB_USBSTS_NAKI_SHIFT                    (16U)
/*! NAKI - NAKI */
#define USB_USBSTS_NAKI(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)

#define USB_USBSTS_TI0_MASK                      (0x1000000U)
#define USB_USBSTS_TI0_SHIFT                     (24U)
/*! TI0 - TI0 */
#define USB_USBSTS_TI0(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)

#define USB_USBSTS_TI1_MASK                      (0x2000000U)
#define USB_USBSTS_TI1_SHIFT                     (25U)
/*! TI1 - TI1 */
#define USB_USBSTS_TI1(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
/*! @} */

/*! @name USBINTR - Interrupt Enable Register */
/*! @{ */

#define USB_USBINTR_UE_MASK                      (0x1U)
#define USB_USBINTR_UE_SHIFT                     (0U)
/*! UE - UE */
#define USB_USBINTR_UE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)

#define USB_USBINTR_UEE_MASK                     (0x2U)
#define USB_USBINTR_UEE_SHIFT                    (1U)
/*! UEE - UEE */
#define USB_USBINTR_UEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)

#define USB_USBINTR_PCE_MASK                     (0x4U)
#define USB_USBINTR_PCE_SHIFT                    (2U)
/*! PCE - PCE */
#define USB_USBINTR_PCE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)

#define USB_USBINTR_FRE_MASK                     (0x8U)
#define USB_USBINTR_FRE_SHIFT                    (3U)
/*! FRE - FRE */
#define USB_USBINTR_FRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)

#define USB_USBINTR_SEE_MASK                     (0x10U)
#define USB_USBINTR_SEE_SHIFT                    (4U)
/*! SEE - SEE */
#define USB_USBINTR_SEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)

#define USB_USBINTR_AAE_MASK                     (0x20U)
#define USB_USBINTR_AAE_SHIFT                    (5U)
/*! AAE - AAE */
#define USB_USBINTR_AAE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)

#define USB_USBINTR_URE_MASK                     (0x40U)
#define USB_USBINTR_URE_SHIFT                    (6U)
/*! URE - URE */
#define USB_USBINTR_URE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)

#define USB_USBINTR_SRE_MASK                     (0x80U)
#define USB_USBINTR_SRE_SHIFT                    (7U)
/*! SRE - SRE */
#define USB_USBINTR_SRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)

#define USB_USBINTR_SLE_MASK                     (0x100U)
#define USB_USBINTR_SLE_SHIFT                    (8U)
/*! SLE - SLE */
#define USB_USBINTR_SLE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)

#define USB_USBINTR_ULPIE_MASK                   (0x400U)
#define USB_USBINTR_ULPIE_SHIFT                  (10U)
/*! ULPIE - ULPIE */
#define USB_USBINTR_ULPIE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)

#define USB_USBINTR_NAKE_MASK                    (0x10000U)
#define USB_USBINTR_NAKE_SHIFT                   (16U)
/*! NAKE - NAKE */
#define USB_USBINTR_NAKE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)

#define USB_USBINTR_UAIE_MASK                    (0x40000U)
#define USB_USBINTR_UAIE_SHIFT                   (18U)
/*! UAIE - UAIE */
#define USB_USBINTR_UAIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)

#define USB_USBINTR_UPIE_MASK                    (0x80000U)
#define USB_USBINTR_UPIE_SHIFT                   (19U)
/*! UPIE - UPIE */
#define USB_USBINTR_UPIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)

#define USB_USBINTR_TIE0_MASK                    (0x1000000U)
#define USB_USBINTR_TIE0_SHIFT                   (24U)
/*! TIE0 - TIE0 */
#define USB_USBINTR_TIE0(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)

#define USB_USBINTR_TIE1_MASK                    (0x2000000U)
#define USB_USBINTR_TIE1_SHIFT                   (25U)
/*! TIE1 - TIE1 */
#define USB_USBINTR_TIE1(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
/*! @} */

/*! @name FRINDEX - USB Frame Index */
/*! @{ */

#define USB_FRINDEX_FRINDEX_MASK                 (0x3FFFU)
#define USB_FRINDEX_FRINDEX_SHIFT                (0U)
/*! FRINDEX - FRINDEX
 *  0b00000000000000..(1024) 12
 *  0b00000000000001..(512) 11
 *  0b00000000000010..(256) 10
 *  0b00000000000011..(128) 9
 *  0b00000000000100..(64) 8
 *  0b00000000000101..(32) 7
 *  0b00000000000110..(16) 6
 *  0b00000000000111..(8) 5
 */
#define USB_FRINDEX_FRINDEX(x)                   (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
/*! @} */

/*! @name DEVICEADDR - Device Address */
/*! @{ */

#define USB_DEVICEADDR_USBADRA_MASK              (0x1000000U)
#define USB_DEVICEADDR_USBADRA_SHIFT             (24U)
/*! USBADRA - USBADRA */
#define USB_DEVICEADDR_USBADRA(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)

#define USB_DEVICEADDR_USBADR_MASK               (0xFE000000U)
#define USB_DEVICEADDR_USBADR_SHIFT              (25U)
/*! USBADR - USBADR */
#define USB_DEVICEADDR_USBADR(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
/*! @} */

/*! @name PERIODICLISTBASE - Frame List Base Address */
/*! @{ */

#define USB_PERIODICLISTBASE_BASEADR_MASK        (0xFFFFF000U)
#define USB_PERIODICLISTBASE_BASEADR_SHIFT       (12U)
/*! BASEADR - BASEADR */
#define USB_PERIODICLISTBASE_BASEADR(x)          (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
/*! @} */

/*! @name ASYNCLISTADDR - Next Asynch. Address */
/*! @{ */

#define USB_ASYNCLISTADDR_ASYBASE_MASK           (0xFFFFFFE0U)
#define USB_ASYNCLISTADDR_ASYBASE_SHIFT          (5U)
/*! ASYBASE - ASYBASE */
#define USB_ASYNCLISTADDR_ASYBASE(x)             (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
/*! @} */

/*! @name ENDPTLISTADDR - Endpoint List Address */
/*! @{ */

#define USB_ENDPTLISTADDR_EPBASE_MASK            (0xFFFFF800U)
#define USB_ENDPTLISTADDR_EPBASE_SHIFT           (11U)
/*! EPBASE - EPBASE */
#define USB_ENDPTLISTADDR_EPBASE(x)              (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
/*! @} */

/*! @name BURSTSIZE - Programmable Burst Size */
/*! @{ */

#define USB_BURSTSIZE_RXPBURST_MASK              (0xFFU)
#define USB_BURSTSIZE_RXPBURST_SHIFT             (0U)
/*! RXPBURST - RXPBURST */
#define USB_BURSTSIZE_RXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)

#define USB_BURSTSIZE_TXPBURST_MASK              (0x1FF00U)
#define USB_BURSTSIZE_TXPBURST_SHIFT             (8U)
/*! TXPBURST - TXPBURST */
#define USB_BURSTSIZE_TXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
/*! @} */

/*! @name TXFILLTUNING - TX FIFO Fill Tuning */
/*! @{ */

#define USB_TXFILLTUNING_TXSCHOH_MASK            (0xFFU)
#define USB_TXFILLTUNING_TXSCHOH_SHIFT           (0U)
/*! TXSCHOH - TXSCHOH */
#define USB_TXFILLTUNING_TXSCHOH(x)              (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)

#define USB_TXFILLTUNING_TXSCHHEALTH_MASK        (0x1F00U)
#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT       (8U)
/*! TXSCHHEALTH - TXSCHHEALTH */
#define USB_TXFILLTUNING_TXSCHHEALTH(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)

#define USB_TXFILLTUNING_TXFIFOTHRES_MASK        (0x3F0000U)
#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT       (16U)
/*! TXFIFOTHRES - TXFIFOTHRES */
#define USB_TXFILLTUNING_TXFIFOTHRES(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
/*! @} */

/*! @name ENDPTNAK - Endpoint NAK */
/*! @{ */

#define USB_ENDPTNAK_EPRN_MASK                   (0xFFU)
#define USB_ENDPTNAK_EPRN_SHIFT                  (0U)
/*! EPRN - EPRN */
#define USB_ENDPTNAK_EPRN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)

#define USB_ENDPTNAK_EPTN_MASK                   (0xFF0000U)
#define USB_ENDPTNAK_EPTN_SHIFT                  (16U)
/*! EPTN - EPTN */
#define USB_ENDPTNAK_EPTN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
/*! @} */

/*! @name ENDPTNAKEN - Endpoint NAK Enable */
/*! @{ */

#define USB_ENDPTNAKEN_EPRNE_MASK                (0xFFU)
#define USB_ENDPTNAKEN_EPRNE_SHIFT               (0U)
/*! EPRNE - EPRNE */
#define USB_ENDPTNAKEN_EPRNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)

#define USB_ENDPTNAKEN_EPTNE_MASK                (0xFF0000U)
#define USB_ENDPTNAKEN_EPTNE_SHIFT               (16U)
/*! EPTNE - EPTNE */
#define USB_ENDPTNAKEN_EPTNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
/*! @} */

/*! @name CONFIGFLAG - Configure Flag Register */
/*! @{ */

#define USB_CONFIGFLAG_CF_MASK                   (0x1U)
#define USB_CONFIGFLAG_CF_SHIFT                  (0U)
/*! CF - CF
 *  0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller.
 *  0b1..Port routing control logic default-routes all ports to this host controller.
 */
#define USB_CONFIGFLAG_CF(x)                     (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
/*! @} */

/*! @name PORTSC1 - Port Status & Control */
/*! @{ */

#define USB_PORTSC1_CCS_MASK                     (0x1U)
#define USB_PORTSC1_CCS_SHIFT                    (0U)
/*! CCS - CCS */
#define USB_PORTSC1_CCS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)

#define USB_PORTSC1_CSC_MASK                     (0x2U)
#define USB_PORTSC1_CSC_SHIFT                    (1U)
/*! CSC - CSC */
#define USB_PORTSC1_CSC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)

#define USB_PORTSC1_PE_MASK                      (0x4U)
#define USB_PORTSC1_PE_SHIFT                     (2U)
/*! PE - PE */
#define USB_PORTSC1_PE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)

#define USB_PORTSC1_PEC_MASK                     (0x8U)
#define USB_PORTSC1_PEC_SHIFT                    (3U)
/*! PEC - PEC */
#define USB_PORTSC1_PEC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)

#define USB_PORTSC1_OCA_MASK                     (0x10U)
#define USB_PORTSC1_OCA_SHIFT                    (4U)
/*! OCA - OCA
 *  0b1..This port currently has an over-current condition
 *  0b0..This port does not have an over-current condition.
 */
#define USB_PORTSC1_OCA(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)

#define USB_PORTSC1_OCC_MASK                     (0x20U)
#define USB_PORTSC1_OCC_SHIFT                    (5U)
/*! OCC - OCC */
#define USB_PORTSC1_OCC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)

#define USB_PORTSC1_FPR_MASK                     (0x40U)
#define USB_PORTSC1_FPR_SHIFT                    (6U)
/*! FPR - FPR */
#define USB_PORTSC1_FPR(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)

#define USB_PORTSC1_SUSP_MASK                    (0x80U)
#define USB_PORTSC1_SUSP_SHIFT                   (7U)
/*! SUSP - SUSP */
#define USB_PORTSC1_SUSP(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)

#define USB_PORTSC1_PR_MASK                      (0x100U)
#define USB_PORTSC1_PR_SHIFT                     (8U)
/*! PR - PR */
#define USB_PORTSC1_PR(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)

#define USB_PORTSC1_HSP_MASK                     (0x200U)
#define USB_PORTSC1_HSP_SHIFT                    (9U)
/*! HSP - HSP */
#define USB_PORTSC1_HSP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)

#define USB_PORTSC1_LS_MASK                      (0xC00U)
#define USB_PORTSC1_LS_SHIFT                     (10U)
/*! LS - LS
 *  0b00..SE0
 *  0b10..J-state
 *  0b01..K-state
 *  0b11..Undefined
 */
#define USB_PORTSC1_LS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)

#define USB_PORTSC1_PP_MASK                      (0x1000U)
#define USB_PORTSC1_PP_SHIFT                     (12U)
/*! PP - PP */
#define USB_PORTSC1_PP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)

#define USB_PORTSC1_PO_MASK                      (0x2000U)
#define USB_PORTSC1_PO_SHIFT                     (13U)
/*! PO - PO */
#define USB_PORTSC1_PO(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)

#define USB_PORTSC1_PIC_MASK                     (0xC000U)
#define USB_PORTSC1_PIC_SHIFT                    (14U)
/*! PIC - PIC
 *  0b00..Port indicators are off
 *  0b01..Amber
 *  0b10..Green
 *  0b11..Undefined
 */
#define USB_PORTSC1_PIC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)

#define USB_PORTSC1_PTC_MASK                     (0xF0000U)
#define USB_PORTSC1_PTC_SHIFT                    (16U)
/*! PTC - PTC
 *  0b0000..TEST_MODE_DISABLE
 *  0b0001..J_STATE
 *  0b0010..K_STATE
 *  0b0011..SE0 (host) / NAK (device)
 *  0b0100..Packet
 *  0b0101..FORCE_ENABLE_HS
 *  0b0110..FORCE_ENABLE_FS
 *  0b0111..FORCE_ENABLE_LS
 *  0b1000-0b1111..Reserved
 */
#define USB_PORTSC1_PTC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)

#define USB_PORTSC1_WKCN_MASK                    (0x100000U)
#define USB_PORTSC1_WKCN_SHIFT                   (20U)
/*! WKCN - WKCN */
#define USB_PORTSC1_WKCN(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)

#define USB_PORTSC1_WKDC_MASK                    (0x200000U)
#define USB_PORTSC1_WKDC_SHIFT                   (21U)
/*! WKDC - WKDC */
#define USB_PORTSC1_WKDC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)

#define USB_PORTSC1_WKOC_MASK                    (0x400000U)
#define USB_PORTSC1_WKOC_SHIFT                   (22U)
/*! WKOC - WKOC */
#define USB_PORTSC1_WKOC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)

#define USB_PORTSC1_PHCD_MASK                    (0x800000U)
#define USB_PORTSC1_PHCD_SHIFT                   (23U)
/*! PHCD - PHCD
 *  0b1..Disable PHY clock
 *  0b0..Enable PHY clock
 */
#define USB_PORTSC1_PHCD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)

#define USB_PORTSC1_PFSC_MASK                    (0x1000000U)
#define USB_PORTSC1_PFSC_SHIFT                   (24U)
/*! PFSC - PFSC
 *  0b1..Forced to full speed
 *  0b0..Normal operation
 */
#define USB_PORTSC1_PFSC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)

#define USB_PORTSC1_PTS_2_MASK                   (0x2000000U)
#define USB_PORTSC1_PTS_2_SHIFT                  (25U)
/*! PTS_2 - PTS_2 */
#define USB_PORTSC1_PTS_2(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)

#define USB_PORTSC1_PSPD_MASK                    (0xC000000U)
#define USB_PORTSC1_PSPD_SHIFT                   (26U)
/*! PSPD - PSPD
 *  0b00..Full Speed
 *  0b01..Low Speed
 *  0b10..High Speed
 *  0b11..Undefined
 */
#define USB_PORTSC1_PSPD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)

#define USB_PORTSC1_PTW_MASK                     (0x10000000U)
#define USB_PORTSC1_PTW_SHIFT                    (28U)
/*! PTW - PTW
 *  0b0..Select the 8-bit UTMI interface [60MHz]
 *  0b1..Select the 16-bit UTMI interface [30MHz]
 */
#define USB_PORTSC1_PTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)

#define USB_PORTSC1_STS_MASK                     (0x20000000U)
#define USB_PORTSC1_STS_SHIFT                    (29U)
/*! STS - STS */
#define USB_PORTSC1_STS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)

#define USB_PORTSC1_PTS_1_MASK                   (0xC0000000U)
#define USB_PORTSC1_PTS_1_SHIFT                  (30U)
/*! PTS_1 - PTS_1 */
#define USB_PORTSC1_PTS_1(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
/*! @} */

/*! @name OTGSC - On-The-Go Status & control */
/*! @{ */

#define USB_OTGSC_VD_MASK                        (0x1U)
#define USB_OTGSC_VD_SHIFT                       (0U)
/*! VD - VD */
#define USB_OTGSC_VD(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)

#define USB_OTGSC_VC_MASK                        (0x2U)
#define USB_OTGSC_VC_SHIFT                       (1U)
/*! VC - VC */
#define USB_OTGSC_VC(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)

#define USB_OTGSC_OT_MASK                        (0x8U)
#define USB_OTGSC_OT_SHIFT                       (3U)
/*! OT - OT */
#define USB_OTGSC_OT(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)

#define USB_OTGSC_DP_MASK                        (0x10U)
#define USB_OTGSC_DP_SHIFT                       (4U)
/*! DP - DP */
#define USB_OTGSC_DP(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)

#define USB_OTGSC_IDPU_MASK                      (0x20U)
#define USB_OTGSC_IDPU_SHIFT                     (5U)
/*! IDPU - IDPU */
#define USB_OTGSC_IDPU(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)

#define USB_OTGSC_ID_MASK                        (0x100U)
#define USB_OTGSC_ID_SHIFT                       (8U)
/*! ID - ID */
#define USB_OTGSC_ID(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)

#define USB_OTGSC_AVV_MASK                       (0x200U)
#define USB_OTGSC_AVV_SHIFT                      (9U)
/*! AVV - AVV */
#define USB_OTGSC_AVV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)

#define USB_OTGSC_ASV_MASK                       (0x400U)
#define USB_OTGSC_ASV_SHIFT                      (10U)
/*! ASV - ASV */
#define USB_OTGSC_ASV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)

#define USB_OTGSC_BSV_MASK                       (0x800U)
#define USB_OTGSC_BSV_SHIFT                      (11U)
/*! BSV - BSV */
#define USB_OTGSC_BSV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)

#define USB_OTGSC_BSE_MASK                       (0x1000U)
#define USB_OTGSC_BSE_SHIFT                      (12U)
/*! BSE - BSE */
#define USB_OTGSC_BSE(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)

#define USB_OTGSC_TOG_1MS_MASK                   (0x2000U)
#define USB_OTGSC_TOG_1MS_SHIFT                  (13U)
/*! TOG_1MS - TOG_1MS */
#define USB_OTGSC_TOG_1MS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)

#define USB_OTGSC_DPS_MASK                       (0x4000U)
#define USB_OTGSC_DPS_SHIFT                      (14U)
/*! DPS - DPS */
#define USB_OTGSC_DPS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)

#define USB_OTGSC_IDIS_MASK                      (0x10000U)
#define USB_OTGSC_IDIS_SHIFT                     (16U)
/*! IDIS - IDIS */
#define USB_OTGSC_IDIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)

#define USB_OTGSC_AVVIS_MASK                     (0x20000U)
#define USB_OTGSC_AVVIS_SHIFT                    (17U)
/*! AVVIS - AVVIS */
#define USB_OTGSC_AVVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)

#define USB_OTGSC_ASVIS_MASK                     (0x40000U)
#define USB_OTGSC_ASVIS_SHIFT                    (18U)
/*! ASVIS - ASVIS */
#define USB_OTGSC_ASVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)

#define USB_OTGSC_BSVIS_MASK                     (0x80000U)
#define USB_OTGSC_BSVIS_SHIFT                    (19U)
/*! BSVIS - BSVIS */
#define USB_OTGSC_BSVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)

#define USB_OTGSC_BSEIS_MASK                     (0x100000U)
#define USB_OTGSC_BSEIS_SHIFT                    (20U)
/*! BSEIS - BSEIS */
#define USB_OTGSC_BSEIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)

#define USB_OTGSC_STATUS_1MS_MASK                (0x200000U)
#define USB_OTGSC_STATUS_1MS_SHIFT               (21U)
/*! STATUS_1MS - STATUS_1MS */
#define USB_OTGSC_STATUS_1MS(x)                  (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)

#define USB_OTGSC_DPIS_MASK                      (0x400000U)
#define USB_OTGSC_DPIS_SHIFT                     (22U)
/*! DPIS - DPIS */
#define USB_OTGSC_DPIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)

#define USB_OTGSC_IDIE_MASK                      (0x1000000U)
#define USB_OTGSC_IDIE_SHIFT                     (24U)
/*! IDIE - IDIE */
#define USB_OTGSC_IDIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)

#define USB_OTGSC_AVVIE_MASK                     (0x2000000U)
#define USB_OTGSC_AVVIE_SHIFT                    (25U)
/*! AVVIE - AVVIE */
#define USB_OTGSC_AVVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)

#define USB_OTGSC_ASVIE_MASK                     (0x4000000U)
#define USB_OTGSC_ASVIE_SHIFT                    (26U)
/*! ASVIE - ASVIE */
#define USB_OTGSC_ASVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)

#define USB_OTGSC_BSVIE_MASK                     (0x8000000U)
#define USB_OTGSC_BSVIE_SHIFT                    (27U)
/*! BSVIE - BSVIE */
#define USB_OTGSC_BSVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)

#define USB_OTGSC_BSEIE_MASK                     (0x10000000U)
#define USB_OTGSC_BSEIE_SHIFT                    (28U)
/*! BSEIE - BSEIE */
#define USB_OTGSC_BSEIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)

#define USB_OTGSC_EN_1MS_MASK                    (0x20000000U)
#define USB_OTGSC_EN_1MS_SHIFT                   (29U)
/*! EN_1MS - EN_1MS */
#define USB_OTGSC_EN_1MS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)

#define USB_OTGSC_DPIE_MASK                      (0x40000000U)
#define USB_OTGSC_DPIE_SHIFT                     (30U)
/*! DPIE - DPIE */
#define USB_OTGSC_DPIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
/*! @} */

/*! @name USBMODE - USB Device Mode */
/*! @{ */

#define USB_USBMODE_CM_MASK                      (0x3U)
#define USB_USBMODE_CM_SHIFT                     (0U)
/*! CM - CM
 *  0b00..Idle [Default for combination host/device]
 *  0b01..Reserved
 *  0b10..Device Controller [Default for device only controller]
 *  0b11..Host Controller [Default for host only controller]
 */
#define USB_USBMODE_CM(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)

#define USB_USBMODE_ES_MASK                      (0x4U)
#define USB_USBMODE_ES_SHIFT                     (2U)
/*! ES - ES
 *  0b0..Little Endian [Default]
 *  0b1..Big Endian
 */
#define USB_USBMODE_ES(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)

#define USB_USBMODE_SLOM_MASK                    (0x8U)
#define USB_USBMODE_SLOM_SHIFT                   (3U)
/*! SLOM - SLOM
 *  0b0..Setup Lockouts On (default);
 *  0b1..Setup Lockouts Off
 */
#define USB_USBMODE_SLOM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)

#define USB_USBMODE_SDIS_MASK                    (0x10U)
#define USB_USBMODE_SDIS_SHIFT                   (4U)
/*! SDIS - SDIS */
#define USB_USBMODE_SDIS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
/*! @} */

/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */
/*! @{ */

#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK   (0xFFFFU)
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT  (0U)
/*! ENDPTSETUPSTAT - ENDPTSETUPSTAT */
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
/*! @} */

/*! @name ENDPTPRIME - Endpoint Prime */
/*! @{ */

#define USB_ENDPTPRIME_PERB_MASK                 (0xFFU)
#define USB_ENDPTPRIME_PERB_SHIFT                (0U)
/*! PERB - PERB */
#define USB_ENDPTPRIME_PERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)

#define USB_ENDPTPRIME_PETB_MASK                 (0xFF0000U)
#define USB_ENDPTPRIME_PETB_SHIFT                (16U)
/*! PETB - PETB */
#define USB_ENDPTPRIME_PETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
/*! @} */

/*! @name ENDPTFLUSH - Endpoint Flush */
/*! @{ */

#define USB_ENDPTFLUSH_FERB_MASK                 (0xFFU)
#define USB_ENDPTFLUSH_FERB_SHIFT                (0U)
/*! FERB - FERB */
#define USB_ENDPTFLUSH_FERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)

#define USB_ENDPTFLUSH_FETB_MASK                 (0xFF0000U)
#define USB_ENDPTFLUSH_FETB_SHIFT                (16U)
/*! FETB - FETB */
#define USB_ENDPTFLUSH_FETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
/*! @} */

/*! @name ENDPTSTAT - Endpoint Status */
/*! @{ */

#define USB_ENDPTSTAT_ERBR_MASK                  (0xFFU)
#define USB_ENDPTSTAT_ERBR_SHIFT                 (0U)
/*! ERBR - ERBR */
#define USB_ENDPTSTAT_ERBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)

#define USB_ENDPTSTAT_ETBR_MASK                  (0xFF0000U)
#define USB_ENDPTSTAT_ETBR_SHIFT                 (16U)
/*! ETBR - ETBR */
#define USB_ENDPTSTAT_ETBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
/*! @} */

/*! @name ENDPTCOMPLETE - Endpoint Complete */
/*! @{ */

#define USB_ENDPTCOMPLETE_ERCE_MASK              (0xFFU)
#define USB_ENDPTCOMPLETE_ERCE_SHIFT             (0U)
/*! ERCE - ERCE */
#define USB_ENDPTCOMPLETE_ERCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)

#define USB_ENDPTCOMPLETE_ETCE_MASK              (0xFF0000U)
#define USB_ENDPTCOMPLETE_ETCE_SHIFT             (16U)
/*! ETCE - ETCE */
#define USB_ENDPTCOMPLETE_ETCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
/*! @} */

/*! @name ENDPTCTRL0 - Endpoint Control0 */
/*! @{ */

#define USB_ENDPTCTRL0_RXS_MASK                  (0x1U)
#define USB_ENDPTCTRL0_RXS_SHIFT                 (0U)
/*! RXS - RXS */
#define USB_ENDPTCTRL0_RXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)

#define USB_ENDPTCTRL0_RXT_MASK                  (0xCU)
#define USB_ENDPTCTRL0_RXT_SHIFT                 (2U)
/*! RXT - RXT */
#define USB_ENDPTCTRL0_RXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)

#define USB_ENDPTCTRL0_RXE_MASK                  (0x80U)
#define USB_ENDPTCTRL0_RXE_SHIFT                 (7U)
/*! RXE - RXE */
#define USB_ENDPTCTRL0_RXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)

#define USB_ENDPTCTRL0_TXS_MASK                  (0x10000U)
#define USB_ENDPTCTRL0_TXS_SHIFT                 (16U)
/*! TXS - TXS */
#define USB_ENDPTCTRL0_TXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)

#define USB_ENDPTCTRL0_TXT_MASK                  (0xC0000U)
#define USB_ENDPTCTRL0_TXT_SHIFT                 (18U)
/*! TXT - TXT */
#define USB_ENDPTCTRL0_TXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)

#define USB_ENDPTCTRL0_TXE_MASK                  (0x800000U)
#define USB_ENDPTCTRL0_TXE_SHIFT                 (23U)
/*! TXE - TXE */
#define USB_ENDPTCTRL0_TXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
/*! @} */

/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */
/*! @{ */

#define USB_ENDPTCTRL_RXS_MASK                   (0x1U)
#define USB_ENDPTCTRL_RXS_SHIFT                  (0U)
/*! RXS - RXS */
#define USB_ENDPTCTRL_RXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)

#define USB_ENDPTCTRL_RXD_MASK                   (0x2U)
#define USB_ENDPTCTRL_RXD_SHIFT                  (1U)
/*! RXD - RXD */
#define USB_ENDPTCTRL_RXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)

#define USB_ENDPTCTRL_RXT_MASK                   (0xCU)
#define USB_ENDPTCTRL_RXT_SHIFT                  (2U)
/*! RXT - RXT */
#define USB_ENDPTCTRL_RXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)

#define USB_ENDPTCTRL_RXI_MASK                   (0x20U)
#define USB_ENDPTCTRL_RXI_SHIFT                  (5U)
/*! RXI - RXI */
#define USB_ENDPTCTRL_RXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)

#define USB_ENDPTCTRL_RXR_MASK                   (0x40U)
#define USB_ENDPTCTRL_RXR_SHIFT                  (6U)
/*! RXR - RXR */
#define USB_ENDPTCTRL_RXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)

#define USB_ENDPTCTRL_RXE_MASK                   (0x80U)
#define USB_ENDPTCTRL_RXE_SHIFT                  (7U)
/*! RXE - RXE */
#define USB_ENDPTCTRL_RXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)

#define USB_ENDPTCTRL_TXS_MASK                   (0x10000U)
#define USB_ENDPTCTRL_TXS_SHIFT                  (16U)
/*! TXS - TXS */
#define USB_ENDPTCTRL_TXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)

#define USB_ENDPTCTRL_TXD_MASK                   (0x20000U)
#define USB_ENDPTCTRL_TXD_SHIFT                  (17U)
/*! TXD - TXD */
#define USB_ENDPTCTRL_TXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)

#define USB_ENDPTCTRL_TXT_MASK                   (0xC0000U)
#define USB_ENDPTCTRL_TXT_SHIFT                  (18U)
/*! TXT - TXT */
#define USB_ENDPTCTRL_TXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)

#define USB_ENDPTCTRL_TXI_MASK                   (0x200000U)
#define USB_ENDPTCTRL_TXI_SHIFT                  (21U)
/*! TXI - TXI */
#define USB_ENDPTCTRL_TXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)

#define USB_ENDPTCTRL_TXR_MASK                   (0x400000U)
#define USB_ENDPTCTRL_TXR_SHIFT                  (22U)
/*! TXR - TXR */
#define USB_ENDPTCTRL_TXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)

#define USB_ENDPTCTRL_TXE_MASK                   (0x800000U)
#define USB_ENDPTCTRL_TXE_SHIFT                  (23U)
/*! TXE - TXE */
#define USB_ENDPTCTRL_TXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
/*! @} */

/* The count of USB_ENDPTCTRL */
#define USB_ENDPTCTRL_COUNT                      (7U)


/*!
 * @}
 */ /* end of group USB_Register_Masks */


/* USB - Peripheral instance base addresses */
/** Peripheral USB0 base address */
#define USB0_BASE                                (0x29900000u)
/** Peripheral USB0 base pointer */
#define USB0                                     ((USB_Type *)USB0_BASE)
/** Peripheral USB1 base address */
#define USB1_BASE                                (0x29920000u)
/** Peripheral USB1 base pointer */
#define USB1                                     ((USB_Type *)USB1_BASE)
/** Peripheral USB_XBAR base address */
#define USB_XBAR_BASE                            (0x29940000u)
/** Peripheral USB_XBAR base pointer */
#define USB_XBAR                                 ((USB_Type *)USB_XBAR_BASE)
/** Array initializer of USB peripheral base addresses */
#define USB_BASE_ADDRS                           { USB0_BASE, USB1_BASE, USB_XBAR_BASE }
/** Array initializer of USB peripheral base pointers */
#define USB_BASE_PTRS                            { USB0, USB1, USB_XBAR }

/*!
 * @}
 */ /* end of group USB_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USBHSDCD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
 * @{
 */

/** USBHSDCD - Register Layout Typedef */
typedef struct {
  __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
  __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
  __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
  __IO uint32_t SIGNAL_OVERRIDE;                   /**< Signal Override Register, offset: 0xC */
  __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
  __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
  union {                                          /* offset: 0x18 */
    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
  };
} USBHSDCD_Type;

/* ----------------------------------------------------------------------------
   -- USBHSDCD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
 * @{
 */

/*! @name CONTROL - Control register */
/*! @{ */

#define USBHSDCD_CONTROL_IACK_MASK               (0x1U)
#define USBHSDCD_CONTROL_IACK_SHIFT              (0U)
/*! IACK - Interrupt Acknowledge
 *  0b0..Do not clear the interrupt.
 *  0b1..Clear the IF bit (interrupt flag).
 */
#define USBHSDCD_CONTROL_IACK(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)

#define USBHSDCD_CONTROL_IF_MASK                 (0x100U)
#define USBHSDCD_CONTROL_IF_SHIFT                (8U)
/*! IF - Interrupt Flag
 *  0b0..No interrupt is pending.
 *  0b1..An interrupt is pending.
 */
#define USBHSDCD_CONTROL_IF(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)

#define USBHSDCD_CONTROL_IE_MASK                 (0x10000U)
#define USBHSDCD_CONTROL_IE_SHIFT                (16U)
/*! IE - Interrupt Enable
 *  0b0..Disable interrupts to the system.
 *  0b1..Enable interrupts to the system.
 */
#define USBHSDCD_CONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)

#define USBHSDCD_CONTROL_BC12_MASK               (0x20000U)
#define USBHSDCD_CONTROL_BC12_SHIFT              (17U)
/*! BC12 - BC12
 *  0b0..Compatible with BC1.1 (default)
 *  0b1..Compatible with BC1.2
 */
#define USBHSDCD_CONTROL_BC12(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)

#define USBHSDCD_CONTROL_START_MASK              (0x1000000U)
#define USBHSDCD_CONTROL_START_SHIFT             (24U)
/*! START - Start Change Detection Sequence
 *  0b0..Do not start the sequence. Writes of this value have no effect.
 *  0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
 */
#define USBHSDCD_CONTROL_START(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)

#define USBHSDCD_CONTROL_SR_MASK                 (0x2000000U)
#define USBHSDCD_CONTROL_SR_SHIFT                (25U)
/*! SR - Software Reset
 *  0b0..Do not perform a software reset.
 *  0b1..Perform a software reset.
 */
#define USBHSDCD_CONTROL_SR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
/*! @} */

/*! @name CLOCK - Clock register */
/*! @{ */

#define USBHSDCD_CLOCK_CLOCK_UNIT_MASK           (0x1U)
#define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT          (0U)
/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
 *  0b0..kHz Speed (between 1 kHz and 1023 kHz)
 *  0b1..MHz Speed (between 1 MHz and 1023 MHz)
 */
#define USBHSDCD_CLOCK_CLOCK_UNIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)

#define USBHSDCD_CLOCK_CLOCK_SPEED_MASK          (0xFFCU)
#define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT         (2U)
/*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary */
#define USBHSDCD_CLOCK_CLOCK_SPEED(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
/*! @} */

/*! @name STATUS - Status register */
/*! @{ */

#define USBHSDCD_STATUS_SEQ_RES_MASK             (0x30000U)
#define USBHSDCD_STATUS_SEQ_RES_SHIFT            (16U)
/*! SEQ_RES - Charger Detection Sequence Results
 *  0b00..No results to report.
 *  0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
 *  0b10..Attached to a charging port. The exact meaning depends on bit 18 (value 0: Attached to either a CDP or a
 *        DCP. The charger type detection has not completed. value 1: Attached to a CDP. The charger type
 *        detection has completed.)
 *  0b11..Attached to a DCP.
 */
#define USBHSDCD_STATUS_SEQ_RES(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)

#define USBHSDCD_STATUS_SEQ_STAT_MASK            (0xC0000U)
#define USBHSDCD_STATUS_SEQ_STAT_SHIFT           (18U)
/*! SEQ_STAT - Charger Detection Sequence Status
 *  0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
 *  0b01..Data pin contact detection is complete.
 *  0b10..Charging port detection is complete.
 *  0b11..Charger type detection is complete.
 */
#define USBHSDCD_STATUS_SEQ_STAT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)

#define USBHSDCD_STATUS_ERR_MASK                 (0x100000U)
#define USBHSDCD_STATUS_ERR_SHIFT                (20U)
/*! ERR - Error Flag
 *  0b0..No sequence errors.
 *  0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
 */
#define USBHSDCD_STATUS_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)

#define USBHSDCD_STATUS_TO_MASK                  (0x200000U)
#define USBHSDCD_STATUS_TO_SHIFT                 (21U)
/*! TO - Timeout Flag
 *  0b0..The detection sequence has not been running for over 1s.
 *  0b1..It has been over 1 s since the data pin contact was detected and debounced.
 */
#define USBHSDCD_STATUS_TO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)

#define USBHSDCD_STATUS_ACTIVE_MASK              (0x400000U)
#define USBHSDCD_STATUS_ACTIVE_SHIFT             (22U)
/*! ACTIVE - Active Status Indicator
 *  0b0..The sequence is not running.
 *  0b1..The sequence is running.
 */
#define USBHSDCD_STATUS_ACTIVE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
/*! @} */

/*! @name SIGNAL_OVERRIDE - Signal Override Register */
/*! @{ */

#define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK         (0x3U)
#define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT        (0U)
/*! PS - Phase Selection
 *  0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent
 *        unexpected conditions on USB_DP and USB_DM pins. (Default)
 *  0b01..Reserved, not for customer use.
 *  0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
 *  0b11..Reserved, not for customer use.
 */
#define USBHSDCD_SIGNAL_OVERRIDE_PS(x)           (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
/*! @} */

/*! @name TIMER0 - TIMER0 register */
/*! @{ */

#define USBHSDCD_TIMER0_TUNITCON_MASK            (0xFFFU)
#define USBHSDCD_TIMER0_TUNITCON_SHIFT           (0U)
/*! TUNITCON - Unit Connection Timer Elapse (in ms) */
#define USBHSDCD_TIMER0_TUNITCON(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)

#define USBHSDCD_TIMER0_TSEQ_INIT_MASK           (0x3FF0000U)
#define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT          (16U)
/*! TSEQ_INIT - Sequence Initiation Time
 *  0b0000000000-0b1111111111..0ms - 1023ms
 */
#define USBHSDCD_TIMER0_TSEQ_INIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
/*! @} */

/*! @name TIMER1 - TIMER1 register */
/*! @{ */

#define USBHSDCD_TIMER1_TVDPSRC_ON_MASK          (0x3FFU)
#define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT         (0U)
/*! TVDPSRC_ON - Time Period Comparator Enabled
 *  0b0000000001-0b1111111111..1ms - 1023ms
 */
#define USBHSDCD_TIMER1_TVDPSRC_ON(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)

#define USBHSDCD_TIMER1_TDCD_DBNC_MASK           (0x3FF0000U)
#define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT          (16U)
/*! TDCD_DBNC - Time Period to Debounce D+ Signal
 *  0b0000000001-0b1111111111..1ms - 1023ms
 */
#define USBHSDCD_TIMER1_TDCD_DBNC(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
/*! @} */

/*! @name TIMER2_BC11 - TIMER2_BC11 register */
/*! @{ */

#define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK       (0xFU)
#define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT      (0U)
/*! CHECK_DM - Time Before Check of D- Line
 *  0b0001-0b1111..1ms - 15ms
 */
#define USBHSDCD_TIMER2_BC11_CHECK_DM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)

#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK    (0x3FF0000U)
#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT   (16U)
/*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup
 *  0b0000000001-0b1111111111..1ms - 1023ms
 */
#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x)      (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
/*! @} */

/*! @name TIMER2_BC12 - TIMER2_BC12 register */
/*! @{ */

#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK     (0x3FFU)
#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT    (0U)
/*! TVDMSRC_ON - TVDMSRC_ON
 *  0b0000000000-0b0000101000..0ms - 40ms
 */
#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x)       (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)

#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
/*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD
 *  0b0000000001-0b1111111111..1ms - 1023ms
 */
#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)  (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USBHSDCD_Register_Masks */


/* USBHSDCD - Peripheral instance base addresses */
/** Peripheral USBDCD0 base address */
#define USBDCD0_BASE                             (0x29910800u)
/** Peripheral USBDCD0 base pointer */
#define USBDCD0                                  ((USBHSDCD_Type *)USBDCD0_BASE)
/** Peripheral USBDCD1 base address */
#define USBDCD1_BASE                             (0x29930800u)
/** Peripheral USBDCD1 base pointer */
#define USBDCD1                                  ((USBHSDCD_Type *)USBDCD1_BASE)
/** Array initializer of USBHSDCD peripheral base addresses */
#define USBHSDCD_BASE_ADDRS                      { USBDCD0_BASE, USBDCD1_BASE }
/** Array initializer of USBHSDCD peripheral base pointers */
#define USBHSDCD_BASE_PTRS                       { USBDCD0, USBDCD1 }

/*!
 * @}
 */ /* end of group USBHSDCD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USBNC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
 * @{
 */

/** USBNC - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL1;                             /**< USB OTG Control 1 Register, offset: 0x0 */
  __IO uint32_t CTRL2;                             /**< USB OTG Control 2 Register, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t HSIC_CTRL;                         /**< USB Host HSIC Control Register, offset: 0x10 */
} USBNC_Type;

/* ----------------------------------------------------------------------------
   -- USBNC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBNC_Register_Masks USBNC Register Masks
 * @{
 */

/*! @name CTRL1 - USB OTG Control 1 Register */
/*! @{ */

#define USBNC_CTRL1_OVER_CUR_DIS_MASK            (0x80U)
#define USBNC_CTRL1_OVER_CUR_DIS_SHIFT           (7U)
/*! OVER_CUR_DIS - OVER_CUR_DIS
 *  0b1..Disables overcurrent detection
 *  0b0..Enables overcurrent detection
 */
#define USBNC_CTRL1_OVER_CUR_DIS(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK)

#define USBNC_CTRL1_OVER_CUR_POL_MASK            (0x100U)
#define USBNC_CTRL1_OVER_CUR_POL_SHIFT           (8U)
/*! OVER_CUR_POL - OVER_CUR_POL
 *  0b1..Low active (low on this signal represents an overcurrent condition)
 *  0b0..High active (high on this signal represents an overcurrent condition)
 */
#define USBNC_CTRL1_OVER_CUR_POL(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK)

#define USBNC_CTRL1_PWR_POL_MASK                 (0x200U)
#define USBNC_CTRL1_PWR_POL_SHIFT                (9U)
/*! PWR_POL - PWR_POL
 *  0b1..PMIC Power Pin is High active.
 *  0b0..PMIC Power Pin is Low active.
 */
#define USBNC_CTRL1_PWR_POL(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK)

#define USBNC_CTRL1_WIE_MASK                     (0x400U)
#define USBNC_CTRL1_WIE_SHIFT                    (10U)
/*! WIE - WIE
 *  0b1..Interrupt Enabled
 *  0b0..Interrupt Disabled
 */
#define USBNC_CTRL1_WIE(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK)

#define USBNC_CTRL1_WKUP_SW_EN_MASK              (0x4000U)
#define USBNC_CTRL1_WKUP_SW_EN_SHIFT             (14U)
/*! WKUP_SW_EN - WKUP_SW_EN
 *  0b1..Enable
 *  0b0..Disable
 */
#define USBNC_CTRL1_WKUP_SW_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK)

#define USBNC_CTRL1_WKUP_SW_MASK                 (0x8000U)
#define USBNC_CTRL1_WKUP_SW_SHIFT                (15U)
/*! WKUP_SW - WKUP_SW
 *  0b1..Force wake-up
 *  0b0..Inactive
 */
#define USBNC_CTRL1_WKUP_SW(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK)

#define USBNC_CTRL1_WKUP_ID_EN_MASK              (0x10000U)
#define USBNC_CTRL1_WKUP_ID_EN_SHIFT             (16U)
/*! WKUP_ID_EN - WKUP_ID_EN
 *  0b1..Enable
 *  0b0..Disable
 */
#define USBNC_CTRL1_WKUP_ID_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK)

#define USBNC_CTRL1_WKUP_VBUS_EN_MASK            (0x20000U)
#define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT           (17U)
/*! WKUP_VBUS_EN - WKUP_VBUS_EN
 *  0b1..Enable
 *  0b0..Disable
 */
#define USBNC_CTRL1_WKUP_VBUS_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK)

#define USBNC_CTRL1_WKUP_DPDM_EN_MASK            (0x20000000U)
#define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT           (29U)
/*! WKUP_DPDM_EN - Wake-up on DPDM change enable
 *  0b1..(Default) DPDM changes wake-up to be enabled, it is for device only.
 *  0b0..DPDM changes wake-up to be disabled only when VBUS is 0.
 */
#define USBNC_CTRL1_WKUP_DPDM_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK)

#define USBNC_CTRL1_WIR_MASK                     (0x80000000U)
#define USBNC_CTRL1_WIR_SHIFT                    (31U)
/*! WIR - WIR
 *  0b1..Wake-up Interrupt Request received
 *  0b0..No wake-up interrupt request received
 */
#define USBNC_CTRL1_WIR(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK)
/*! @} */

/*! @name CTRL2 - USB OTG Control 2 Register */
/*! @{ */

#define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK         (0x3U)
#define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT        (0U)
/*! VBUS_SOURCE_SEL - VBUS_SOURCE_SEL
 *  0b00..vbus_valid
 *  0b01..sess_valid
 *  0b10..sess_valid
 *  0b11..sess_valid
 */
#define USBNC_CTRL2_VBUS_SOURCE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK)

#define USBNC_CTRL2_AUTURESUME_EN_MASK           (0x4U)
#define USBNC_CTRL2_AUTURESUME_EN_SHIFT          (2U)
/*! AUTURESUME_EN - Auto Resume Enable
 *  0b0..Default
 */
#define USBNC_CTRL2_AUTURESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK)

#define USBNC_CTRL2_LOWSPEED_EN_MASK             (0x8U)
#define USBNC_CTRL2_LOWSPEED_EN_SHIFT            (3U)
/*! LOWSPEED_EN - LOWSPEED_EN
 *  0b0..Default
 */
#define USBNC_CTRL2_LOWSPEED_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK)

#define USBNC_CTRL2_UTMI_CLK_VLD_MASK            (0x80000000U)
#define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT           (31U)
/*! UTMI_CLK_VLD - UTMI_CLK_VLD
 *  0b0..Default
 */
#define USBNC_CTRL2_UTMI_CLK_VLD(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK)
/*! @} */

/*! @name HSIC_CTRL - USB Host HSIC Control Register */
/*! @{ */

#define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK         (0x800U)
#define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT        (11U)
/*! HSIC_CLK_ON - HSIC_CLK_ON
 *  0b1..Active
 *  0b0..Inactive
 */
#define USBNC_HSIC_CTRL_HSIC_CLK_ON(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK)

#define USBNC_HSIC_CTRL_HSIC_EN_MASK             (0x1000U)
#define USBNC_HSIC_CTRL_HSIC_EN_SHIFT            (12U)
/*! HSIC_EN - HSIC_EN
 *  0b1..Enabled
 *  0b0..Disabled
 */
#define USBNC_HSIC_CTRL_HSIC_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK)

#define USBNC_HSIC_CTRL_CLK_VLD_MASK             (0x80000000U)
#define USBNC_HSIC_CTRL_CLK_VLD_SHIFT            (31U)
/*! CLK_VLD - CLK_VLD
 *  0b1..Valid
 *  0b0..Invalid
 */
#define USBNC_HSIC_CTRL_CLK_VLD(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USBNC_Register_Masks */


/* USBNC - Peripheral instance base addresses */
/** Peripheral USBNC0 base address */
#define USBNC0_BASE                              (0x29900200u)
/** Peripheral USBNC0 base pointer */
#define USBNC0                                   ((USBNC_Type *)USBNC0_BASE)
/** Peripheral USBNC1 base address */
#define USBNC1_BASE                              (0x29920200u)
/** Peripheral USBNC1 base pointer */
#define USBNC1                                   ((USBNC_Type *)USBNC1_BASE)
/** Peripheral USBNC_XBAR base address */
#define USBNC_XBAR_BASE                          (0x29940200u)
/** Peripheral USBNC_XBAR base pointer */
#define USBNC_XBAR                               ((USBNC_Type *)USBNC_XBAR_BASE)
/** Array initializer of USBNC peripheral base addresses */
#define USBNC_BASE_ADDRS                         { USBNC0_BASE, USBNC1_BASE, USBNC_XBAR_BASE }
/** Array initializer of USBNC peripheral base pointers */
#define USBNC_BASE_PTRS                          { USBNC0, USBNC1, USBNC_XBAR }

/*!
 * @}
 */ /* end of group USBNC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USBPHY Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
 * @{
 */

/** USBPHY - Register Layout Typedef */
typedef struct {
  __IO uint32_t PWD;                               /**< USB PHY Power-Down Register, offset: 0x0 */
  __IO uint32_t PWD_SET;                           /**< USB PHY Power-Down Register, offset: 0x4 */
  __IO uint32_t PWD_CLR;                           /**< USB PHY Power-Down Register, offset: 0x8 */
  __IO uint32_t PWD_TOG;                           /**< USB PHY Power-Down Register, offset: 0xC */
  __IO uint32_t TX;                                /**< USB PHY Transmitter Control Register, offset: 0x10 */
  __IO uint32_t TX_SET;                            /**< USB PHY Transmitter Control Register, offset: 0x14 */
  __IO uint32_t TX_CLR;                            /**< USB PHY Transmitter Control Register, offset: 0x18 */
  __IO uint32_t TX_TOG;                            /**< USB PHY Transmitter Control Register, offset: 0x1C */
  __IO uint32_t RX;                                /**< USB PHY Receiver Control Register, offset: 0x20 */
  __IO uint32_t RX_SET;                            /**< USB PHY Receiver Control Register, offset: 0x24 */
  __IO uint32_t RX_CLR;                            /**< USB PHY Receiver Control Register, offset: 0x28 */
  __IO uint32_t RX_TOG;                            /**< USB PHY Receiver Control Register, offset: 0x2C */
  __IO uint32_t CTRL;                              /**< USB PHY General Control Register, offset: 0x30 */
  __IO uint32_t CTRL_SET;                          /**< USB PHY General Control Register, offset: 0x34 */
  __IO uint32_t CTRL_CLR;                          /**< USB PHY General Control Register, offset: 0x38 */
  __IO uint32_t CTRL_TOG;                          /**< USB PHY General Control Register, offset: 0x3C */
  __I  uint32_t STATUS;                            /**< USB PHY Status Register, offset: 0x40 */
       uint8_t RESERVED_0[12];
  __IO uint32_t DEBUGr;                            /**< USB PHY Debug Register, offset: 0x50, 'r' suffix has been added to avoid clash with DEBUG symbolic constant */
  __IO uint32_t DEBUG_SET;                         /**< USB PHY Debug Register, offset: 0x54 */
  __IO uint32_t DEBUG_CLR;                         /**< USB PHY Debug Register, offset: 0x58 */
  __IO uint32_t DEBUG_TOG;                         /**< USB PHY Debug Register, offset: 0x5C */
  __I  uint32_t DEBUG0_STATUS;                     /**< UTMI Debug Status Register 0, offset: 0x60 */
       uint8_t RESERVED_1[12];
  __IO uint32_t DEBUG1;                            /**< UTMI Debug Status Register 1, offset: 0x70 */
  __IO uint32_t DEBUG1_SET;                        /**< UTMI Debug Status Register 1, offset: 0x74 */
  __IO uint32_t DEBUG1_CLR;                        /**< UTMI Debug Status Register 1, offset: 0x78 */
  __IO uint32_t DEBUG1_TOG;                        /**< UTMI Debug Status Register 1, offset: 0x7C */
  __I  uint32_t VERSION;                           /**< UTMI RTL Version, offset: 0x80 */
       uint8_t RESERVED_2[28];
  __IO uint32_t PLL_SIC;                           /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
  __IO uint32_t PLL_SIC_SET;                       /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
  __IO uint32_t PLL_SIC_CLR;                       /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
  __IO uint32_t PLL_SIC_TOG;                       /**< USB PHY PLL Control/Status Register, offset: 0xAC */
       uint8_t RESERVED_3[16];
  __IO uint32_t USB1_VBUS_DETECT;                  /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
  __IO uint32_t USB1_VBUS_DETECT_SET;              /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
  __IO uint32_t USB1_VBUS_DETECT_CLR;              /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
  __IO uint32_t USB1_VBUS_DETECT_TOG;              /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
  __I  uint32_t USB1_VBUS_DET_STAT;                /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */
       uint8_t RESERVED_4[12];
  __IO uint32_t USB1_CHRG_DETECT;                  /**< USB PHY Charger Detect Control Register, offset: 0xE0 */
  __IO uint32_t USB1_CHRG_DETECT_SET;              /**< USB PHY Charger Detect Control Register, offset: 0xE4 */
  __IO uint32_t USB1_CHRG_DETECT_CLR;              /**< USB PHY Charger Detect Control Register, offset: 0xE8 */
  __IO uint32_t USB1_CHRG_DETECT_TOG;              /**< USB PHY Charger Detect Control Register, offset: 0xEC */
  __I  uint32_t USB1_CHRG_DET_STAT;                /**< USB PHY Charger Detect Status Register, offset: 0xF0 */
       uint8_t RESERVED_5[12];
  __IO uint32_t ANACTRL;                           /**< USB PHY Analog Control Register, offset: 0x100 */
  __IO uint32_t ANACTRL_SET;                       /**< USB PHY Analog Control Register, offset: 0x104 */
  __IO uint32_t ANACTRL_CLR;                       /**< USB PHY Analog Control Register, offset: 0x108 */
  __IO uint32_t ANACTRL_TOG;                       /**< USB PHY Analog Control Register, offset: 0x10C */
  __IO uint32_t USB1_LOOPBACK;                     /**< USB PHY Loopback Control/Status Register, offset: 0x110 */
  __IO uint32_t USB1_LOOPBACK_SET;                 /**< USB PHY Loopback Control/Status Register, offset: 0x114 */
  __IO uint32_t USB1_LOOPBACK_CLR;                 /**< USB PHY Loopback Control/Status Register, offset: 0x118 */
  __IO uint32_t USB1_LOOPBACK_TOG;                 /**< USB PHY Loopback Control/Status Register, offset: 0x11C */
  __IO uint32_t USB1_LOOPBACK_HSFSCNT;             /**< USB PHY Loopback Packet Number Select Register, offset: 0x120 */
  __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x124 */
  __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x128 */
  __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x12C */
  __IO uint32_t TRIM_OVERRIDE_EN;                  /**< USB PHY Trim Override Enable Register, offset: 0x130 */
  __IO uint32_t TRIM_OVERRIDE_EN_SET;              /**< USB PHY Trim Override Enable Register, offset: 0x134 */
  __IO uint32_t TRIM_OVERRIDE_EN_CLR;              /**< USB PHY Trim Override Enable Register, offset: 0x138 */
  __IO uint32_t TRIM_OVERRIDE_EN_TOG;              /**< USB PHY Trim Override Enable Register, offset: 0x13C */
} USBPHY_Type;

/* ----------------------------------------------------------------------------
   -- USBPHY Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
 * @{
 */

/*! @name PWD - USB PHY Power-Down Register */
/*! @{ */

#define USBPHY_PWD_TXPWDFS_MASK                  (0x400U)
#define USBPHY_PWD_TXPWDFS_SHIFT                 (10U)
/*! TXPWDFS - TXPWDFS
 *  0b0..Normal operation.
 *  0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
 */
#define USBPHY_PWD_TXPWDFS(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)

#define USBPHY_PWD_TXPWDIBIAS_MASK               (0x800U)
#define USBPHY_PWD_TXPWDIBIAS_SHIFT              (11U)
/*! TXPWDIBIAS - TXPWDIBIAS
 *  0b0..Normal operation
 *  0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB
 *       is in suspend mode. This effectively powers down the entire USB transmit path
 */
#define USBPHY_PWD_TXPWDIBIAS(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)

#define USBPHY_PWD_TXPWDV2I_MASK                 (0x1000U)
#define USBPHY_PWD_TXPWDV2I_SHIFT                (12U)
/*! TXPWDV2I - TXPWDV2I
 *  0b0..Normal operation.
 *  0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
 */
#define USBPHY_PWD_TXPWDV2I(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)

#define USBPHY_PWD_RXPWDENV_MASK                 (0x20000U)
#define USBPHY_PWD_RXPWDENV_SHIFT                (17U)
/*! RXPWDENV - RXPWDENV
 *  0b0..Normal operation.
 *  0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
 */
#define USBPHY_PWD_RXPWDENV(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)

#define USBPHY_PWD_RXPWD1PT1_MASK                (0x40000U)
#define USBPHY_PWD_RXPWD1PT1_SHIFT               (18U)
/*! RXPWD1PT1 - RXPWD1PT1
 *  0b0..Normal operation
 *  0b1..Power-down the USB full-speed differential receiver.
 */
#define USBPHY_PWD_RXPWD1PT1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)

#define USBPHY_PWD_RXPWDDIFF_MASK                (0x80000U)
#define USBPHY_PWD_RXPWDDIFF_SHIFT               (19U)
/*! RXPWDDIFF - RXPWDDIFF
 *  0b0..Normal operation.
 *  0b1..Power-down the USB high-speed differential receiver
 */
#define USBPHY_PWD_RXPWDDIFF(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)

#define USBPHY_PWD_RXPWDRX_MASK                  (0x100000U)
#define USBPHY_PWD_RXPWDRX_SHIFT                 (20U)
/*! RXPWDRX - RXPWDRX
 *  0b0..Normal operation
 *  0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
 */
#define USBPHY_PWD_RXPWDRX(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
/*! @} */

/*! @name PWD_SET - USB PHY Power-Down Register */
/*! @{ */

#define USBPHY_PWD_SET_TXPWDFS_MASK              (0x400U)
#define USBPHY_PWD_SET_TXPWDFS_SHIFT             (10U)
/*! TXPWDFS - TXPWDFS */
#define USBPHY_PWD_SET_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)

#define USBPHY_PWD_SET_TXPWDIBIAS_MASK           (0x800U)
#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT          (11U)
/*! TXPWDIBIAS - TXPWDIBIAS */
#define USBPHY_PWD_SET_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)

#define USBPHY_PWD_SET_TXPWDV2I_MASK             (0x1000U)
#define USBPHY_PWD_SET_TXPWDV2I_SHIFT            (12U)
/*! TXPWDV2I - TXPWDV2I */
#define USBPHY_PWD_SET_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)

#define USBPHY_PWD_SET_RXPWDENV_MASK             (0x20000U)
#define USBPHY_PWD_SET_RXPWDENV_SHIFT            (17U)
/*! RXPWDENV - RXPWDENV */
#define USBPHY_PWD_SET_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)

#define USBPHY_PWD_SET_RXPWD1PT1_MASK            (0x40000U)
#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT           (18U)
/*! RXPWD1PT1 - RXPWD1PT1 */
#define USBPHY_PWD_SET_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)

#define USBPHY_PWD_SET_RXPWDDIFF_MASK            (0x80000U)
#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT           (19U)
/*! RXPWDDIFF - RXPWDDIFF */
#define USBPHY_PWD_SET_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)

#define USBPHY_PWD_SET_RXPWDRX_MASK              (0x100000U)
#define USBPHY_PWD_SET_RXPWDRX_SHIFT             (20U)
/*! RXPWDRX - RXPWDRX */
#define USBPHY_PWD_SET_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
/*! @} */

/*! @name PWD_CLR - USB PHY Power-Down Register */
/*! @{ */

#define USBPHY_PWD_CLR_TXPWDFS_MASK              (0x400U)
#define USBPHY_PWD_CLR_TXPWDFS_SHIFT             (10U)
/*! TXPWDFS - TXPWDFS */
#define USBPHY_PWD_CLR_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)

#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK           (0x800U)
#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT          (11U)
/*! TXPWDIBIAS - TXPWDIBIAS */
#define USBPHY_PWD_CLR_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)

#define USBPHY_PWD_CLR_TXPWDV2I_MASK             (0x1000U)
#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT            (12U)
/*! TXPWDV2I - TXPWDV2I */
#define USBPHY_PWD_CLR_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)

#define USBPHY_PWD_CLR_RXPWDENV_MASK             (0x20000U)
#define USBPHY_PWD_CLR_RXPWDENV_SHIFT            (17U)
/*! RXPWDENV - RXPWDENV */
#define USBPHY_PWD_CLR_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)

#define USBPHY_PWD_CLR_RXPWD1PT1_MASK            (0x40000U)
#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT           (18U)
/*! RXPWD1PT1 - RXPWD1PT1 */
#define USBPHY_PWD_CLR_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)

#define USBPHY_PWD_CLR_RXPWDDIFF_MASK            (0x80000U)
#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT           (19U)
/*! RXPWDDIFF - RXPWDDIFF */
#define USBPHY_PWD_CLR_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)

#define USBPHY_PWD_CLR_RXPWDRX_MASK              (0x100000U)
#define USBPHY_PWD_CLR_RXPWDRX_SHIFT             (20U)
/*! RXPWDRX - RXPWDRX */
#define USBPHY_PWD_CLR_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
/*! @} */

/*! @name PWD_TOG - USB PHY Power-Down Register */
/*! @{ */

#define USBPHY_PWD_TOG_TXPWDFS_MASK              (0x400U)
#define USBPHY_PWD_TOG_TXPWDFS_SHIFT             (10U)
/*! TXPWDFS - TXPWDFS */
#define USBPHY_PWD_TOG_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)

#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK           (0x800U)
#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT          (11U)
/*! TXPWDIBIAS - TXPWDIBIAS */
#define USBPHY_PWD_TOG_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)

#define USBPHY_PWD_TOG_TXPWDV2I_MASK             (0x1000U)
#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT            (12U)
/*! TXPWDV2I - TXPWDV2I */
#define USBPHY_PWD_TOG_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)

#define USBPHY_PWD_TOG_RXPWDENV_MASK             (0x20000U)
#define USBPHY_PWD_TOG_RXPWDENV_SHIFT            (17U)
/*! RXPWDENV - RXPWDENV */
#define USBPHY_PWD_TOG_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)

#define USBPHY_PWD_TOG_RXPWD1PT1_MASK            (0x40000U)
#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT           (18U)
/*! RXPWD1PT1 - RXPWD1PT1 */
#define USBPHY_PWD_TOG_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)

#define USBPHY_PWD_TOG_RXPWDDIFF_MASK            (0x80000U)
#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT           (19U)
/*! RXPWDDIFF - RXPWDDIFF */
#define USBPHY_PWD_TOG_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)

#define USBPHY_PWD_TOG_RXPWDRX_MASK              (0x100000U)
#define USBPHY_PWD_TOG_RXPWDRX_SHIFT             (20U)
/*! RXPWDRX - RXPWDRX */
#define USBPHY_PWD_TOG_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
/*! @} */

/*! @name TX - USB PHY Transmitter Control Register */
/*! @{ */

#define USBPHY_TX_D_CAL_MASK                     (0xFU)
#define USBPHY_TX_D_CAL_SHIFT                    (0U)
/*! D_CAL - D_CAL
 *  0b0000..+20.30%
 *  0b0001..+17.60%
 *  0b0010..+14.80%
 *  0b0011..+12.60%
 *  0b0100..+8.79%
 *  0b0101..+6.04%
 *  0b0110..+2.75%
 *  0b0111..0%
 *  0b1000..-2.75%
 *  0b1001..-5.49%
 *  0b1010..-7.69%
 *  0b1011..-10.40%
 *  0b1100..-12.60%
 *  0b1101..-14.30%
 *  0b1110..-18.10%
 *  0b1111..-22.00%
 */
#define USBPHY_TX_D_CAL(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)

#define USBPHY_TX_TXCAL45DN_MASK                 (0xF00U)
#define USBPHY_TX_TXCAL45DN_SHIFT                (8U)
/*! TXCAL45DN - TXCAL45DN
 *  0b0000..+19.95%
 *  0b0001..+17.35%
 *  0b0010..+14.85%
 *  0b0011..+12.46%
 *  0b0100..+9.07%
 *  0b0101..+5.87%
 *  0b0110..+2.85%
 *  0b0111..0%
 *  0b1000..-2.70%
 *  0b1001..-5.25%
 *  0b1010..-7.67%
 *  0b1011..-9.98%
 *  0b1100..-12.17%
 *  0b1101..-14.25%
 *  0b1110..-18.14%
 *  0b1111..-21.68%
 */
#define USBPHY_TX_TXCAL45DN(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)

#define USBPHY_TX_TXCAL45DP_MASK                 (0xF0000U)
#define USBPHY_TX_TXCAL45DP_SHIFT                (16U)
/*! TXCAL45DP - TXCAL45DP
 *  0b0000..+19.95%
 *  0b0001..+17.35%
 *  0b0010..+14.85%
 *  0b0011..+12.46%
 *  0b0100..+9.07%
 *  0b0101..+5.87%
 *  0b0110..+2.85%
 *  0b0111..0%
 *  0b1000..-2.70%
 *  0b1001..-5.25%
 *  0b1010..-7.67%
 *  0b1011..-9.98%
 *  0b1100..-12.17%
 *  0b1101..-14.25%
 *  0b1110..-18.14%
 *  0b1111..-21.68%
 */
#define USBPHY_TX_TXCAL45DP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
/*! @} */

/*! @name TX_SET - USB PHY Transmitter Control Register */
/*! @{ */

#define USBPHY_TX_SET_D_CAL_MASK                 (0xFU)
#define USBPHY_TX_SET_D_CAL_SHIFT                (0U)
/*! D_CAL - D_CAL */
#define USBPHY_TX_SET_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)

#define USBPHY_TX_SET_TXCAL45DN_MASK             (0xF00U)
#define USBPHY_TX_SET_TXCAL45DN_SHIFT            (8U)
/*! TXCAL45DN - TXCAL45DN */
#define USBPHY_TX_SET_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)

#define USBPHY_TX_SET_TXCAL45DP_MASK             (0xF0000U)
#define USBPHY_TX_SET_TXCAL45DP_SHIFT            (16U)
/*! TXCAL45DP - TXCAL45DP */
#define USBPHY_TX_SET_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
/*! @} */

/*! @name TX_CLR - USB PHY Transmitter Control Register */
/*! @{ */

#define USBPHY_TX_CLR_D_CAL_MASK                 (0xFU)
#define USBPHY_TX_CLR_D_CAL_SHIFT                (0U)
/*! D_CAL - D_CAL */
#define USBPHY_TX_CLR_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)

#define USBPHY_TX_CLR_TXCAL45DN_MASK             (0xF00U)
#define USBPHY_TX_CLR_TXCAL45DN_SHIFT            (8U)
/*! TXCAL45DN - TXCAL45DN */
#define USBPHY_TX_CLR_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)

#define USBPHY_TX_CLR_TXCAL45DP_MASK             (0xF0000U)
#define USBPHY_TX_CLR_TXCAL45DP_SHIFT            (16U)
/*! TXCAL45DP - TXCAL45DP */
#define USBPHY_TX_CLR_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
/*! @} */

/*! @name TX_TOG - USB PHY Transmitter Control Register */
/*! @{ */

#define USBPHY_TX_TOG_D_CAL_MASK                 (0xFU)
#define USBPHY_TX_TOG_D_CAL_SHIFT                (0U)
/*! D_CAL - D_CAL */
#define USBPHY_TX_TOG_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)

#define USBPHY_TX_TOG_TXCAL45DN_MASK             (0xF00U)
#define USBPHY_TX_TOG_TXCAL45DN_SHIFT            (8U)
/*! TXCAL45DN - TXCAL45DN */
#define USBPHY_TX_TOG_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)

#define USBPHY_TX_TOG_TXCAL45DP_MASK             (0xF0000U)
#define USBPHY_TX_TOG_TXCAL45DP_SHIFT            (16U)
/*! TXCAL45DP - TXCAL45DP */
#define USBPHY_TX_TOG_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
/*! @} */

/*! @name RX - USB PHY Receiver Control Register */
/*! @{ */

#define USBPHY_RX_ENVADJ_MASK                    (0x7U)
#define USBPHY_RX_ENVADJ_SHIFT                   (0U)
/*! ENVADJ - ENVADJ
 *  0b000..Trip-Level Voltage is 0.1000 V
 *  0b001..Trip-Level Voltage is 0.1125 V
 *  0b010..Trip-Level Voltage is 0.1250 V
 *  0b011..Trip-Level Voltage is 0.0875 V
 *  0b1xx..Reserved
 */
#define USBPHY_RX_ENVADJ(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)

#define USBPHY_RX_DISCONADJ_MASK                 (0x70U)
#define USBPHY_RX_DISCONADJ_SHIFT                (4U)
/*! DISCONADJ - DISCONADJ
 *  0b000..Trip-Level Voltage is 0.56875 V
 *  0b001..Trip-Level Voltage is 0.55000 V
 *  0b010..Trip-Level Voltage is 0.58125 V
 *  0b011..Trip-Level Voltage is 0.60000 V
 *  0b1xx..Reserved
 */
#define USBPHY_RX_DISCONADJ(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)

#define USBPHY_RX_RXDBYPASS_MASK                 (0x400000U)
#define USBPHY_RX_RXDBYPASS_SHIFT                (22U)
/*! RXDBYPASS - RXDBYPASS
 *  0b0..Normal operation.
 *  0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
 */
#define USBPHY_RX_RXDBYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
/*! @} */

/*! @name RX_SET - USB PHY Receiver Control Register */
/*! @{ */

#define USBPHY_RX_SET_ENVADJ_MASK                (0x7U)
#define USBPHY_RX_SET_ENVADJ_SHIFT               (0U)
/*! ENVADJ - ENVADJ */
#define USBPHY_RX_SET_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)

#define USBPHY_RX_SET_DISCONADJ_MASK             (0x70U)
#define USBPHY_RX_SET_DISCONADJ_SHIFT            (4U)
/*! DISCONADJ - DISCONADJ */
#define USBPHY_RX_SET_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)

#define USBPHY_RX_SET_RXDBYPASS_MASK             (0x400000U)
#define USBPHY_RX_SET_RXDBYPASS_SHIFT            (22U)
/*! RXDBYPASS - RXDBYPASS */
#define USBPHY_RX_SET_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
/*! @} */

/*! @name RX_CLR - USB PHY Receiver Control Register */
/*! @{ */

#define USBPHY_RX_CLR_ENVADJ_MASK                (0x7U)
#define USBPHY_RX_CLR_ENVADJ_SHIFT               (0U)
/*! ENVADJ - ENVADJ */
#define USBPHY_RX_CLR_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)

#define USBPHY_RX_CLR_DISCONADJ_MASK             (0x70U)
#define USBPHY_RX_CLR_DISCONADJ_SHIFT            (4U)
/*! DISCONADJ - DISCONADJ */
#define USBPHY_RX_CLR_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)

#define USBPHY_RX_CLR_RXDBYPASS_MASK             (0x400000U)
#define USBPHY_RX_CLR_RXDBYPASS_SHIFT            (22U)
/*! RXDBYPASS - RXDBYPASS */
#define USBPHY_RX_CLR_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
/*! @} */

/*! @name RX_TOG - USB PHY Receiver Control Register */
/*! @{ */

#define USBPHY_RX_TOG_ENVADJ_MASK                (0x7U)
#define USBPHY_RX_TOG_ENVADJ_SHIFT               (0U)
/*! ENVADJ - ENVADJ */
#define USBPHY_RX_TOG_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)

#define USBPHY_RX_TOG_DISCONADJ_MASK             (0x70U)
#define USBPHY_RX_TOG_DISCONADJ_SHIFT            (4U)
/*! DISCONADJ - DISCONADJ */
#define USBPHY_RX_TOG_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)

#define USBPHY_RX_TOG_RXDBYPASS_MASK             (0x400000U)
#define USBPHY_RX_TOG_RXDBYPASS_SHIFT            (22U)
/*! RXDBYPASS - RXDBYPASS */
#define USBPHY_RX_TOG_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
/*! @} */

/*! @name CTRL - USB PHY General Control Register */
/*! @{ */

#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK        (0x1U)
#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT       (0U)
/*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ */
#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)

#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK      (0x2U)
#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT     (1U)
/*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT */
#define USBPHY_CTRL_ENHOSTDISCONDETECT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)

#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK         (0x4U)
#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT        (2U)
/*! ENIRQHOSTDISCON - ENIRQHOSTDISCON */
#define USBPHY_CTRL_ENIRQHOSTDISCON(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)

#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK    (0x8U)
#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
/*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ */
#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)

#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK       (0x10U)
#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT      (4U)
/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
 *  0b0..Disables 200kohm pullup resistors on DP and DN pins
 *  0b1..Enables 200kohm pullup resistors on DP and DN pins
 */
#define USBPHY_CTRL_ENDEVPLUGINDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)

#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK      (0x20U)
#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT     (5U)
/*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY */
#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)

#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK          (0x40U)
#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT         (6U)
/*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ */
#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)

#define USBPHY_CTRL_ENOTGIDDETECT_MASK           (0x80U)
#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT          (7U)
/*! ENOTGIDDETECT - ENOTGIDDETECT */
#define USBPHY_CTRL_ENOTGIDDETECT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)

#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK         (0x100U)
#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT        (8U)
/*! RESUMEIRQSTICKY - RESUMEIRQSTICKY */
#define USBPHY_CTRL_RESUMEIRQSTICKY(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)

#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK       (0x200U)
#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT      (9U)
/*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT */
#define USBPHY_CTRL_ENIRQRESUMEDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)

#define USBPHY_CTRL_RESUME_IRQ_MASK              (0x400U)
#define USBPHY_CTRL_RESUME_IRQ_SHIFT             (10U)
/*! RESUME_IRQ - RESUME_IRQ */
#define USBPHY_CTRL_RESUME_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)

#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK          (0x800U)
#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT         (11U)
/*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN */
#define USBPHY_CTRL_ENIRQDEVPLUGIN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)

#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK           (0x1000U)
#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT          (12U)
/*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ */
#define USBPHY_CTRL_DEVPLUGIN_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)

#define USBPHY_CTRL_ENUTMILEVEL2_MASK            (0x4000U)
#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT           (14U)
/*! ENUTMILEVEL2 - ENUTMILEVEL2 */
#define USBPHY_CTRL_ENUTMILEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)

#define USBPHY_CTRL_ENUTMILEVEL3_MASK            (0x8000U)
#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT           (15U)
/*! ENUTMILEVEL3 - ENUTMILEVEL3 */
#define USBPHY_CTRL_ENUTMILEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)

#define USBPHY_CTRL_ENIRQWAKEUP_MASK             (0x10000U)
#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT            (16U)
/*! ENIRQWAKEUP - ENIRQWAKEUP */
#define USBPHY_CTRL_ENIRQWAKEUP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)

#define USBPHY_CTRL_WAKEUP_IRQ_MASK              (0x20000U)
#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT             (17U)
/*! WAKEUP_IRQ - WAKEUP_IRQ */
#define USBPHY_CTRL_WAKEUP_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)

#define USBPHY_CTRL_AUTORESUME_EN_MASK           (0x40000U)
#define USBPHY_CTRL_AUTORESUME_EN_SHIFT          (18U)
/*! AUTORESUME_EN - AUTORESUME_EN */
#define USBPHY_CTRL_AUTORESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)

#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK       (0x80000U)
#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT      (19U)
/*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE */
#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)

#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK       (0x100000U)
#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT      (20U)
/*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD */
#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)

#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK          (0x200000U)
#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT         (21U)
/*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP */
#define USBPHY_CTRL_ENDPDMCHG_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)

#define USBPHY_CTRL_ENIDCHG_WKUP_MASK            (0x400000U)
#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT           (22U)
/*! ENIDCHG_WKUP - ENIDCHG_WKUP */
#define USBPHY_CTRL_ENIDCHG_WKUP(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)

#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK          (0x800000U)
#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT         (23U)
/*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP */
#define USBPHY_CTRL_ENVBUSCHG_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)

#define USBPHY_CTRL_FSDLL_RST_EN_MASK            (0x1000000U)
#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT           (24U)
/*! FSDLL_RST_EN - FSDLL_RST_EN */
#define USBPHY_CTRL_FSDLL_RST_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)

#define USBPHY_CTRL_OTG_ID_VALUE_MASK            (0x8000000U)
#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT           (27U)
/*! OTG_ID_VALUE - OTG_ID_VALUE */
#define USBPHY_CTRL_OTG_ID_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)

#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK       (0x10000000U)
#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT      (28U)
/*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0 */
#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)

#define USBPHY_CTRL_UTMI_SUSPENDM_MASK           (0x20000000U)
#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT          (29U)
/*! UTMI_SUSPENDM - UTMI_SUSPENDM */
#define USBPHY_CTRL_UTMI_SUSPENDM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)

#define USBPHY_CTRL_CLKGATE_MASK                 (0x40000000U)
#define USBPHY_CTRL_CLKGATE_SHIFT                (30U)
/*! CLKGATE - CLKGATE */
#define USBPHY_CTRL_CLKGATE(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)

#define USBPHY_CTRL_SFTRST_MASK                  (0x80000000U)
#define USBPHY_CTRL_SFTRST_SHIFT                 (31U)
/*! SFTRST - SFTRST */
#define USBPHY_CTRL_SFTRST(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
/*! @} */

/*! @name CTRL_SET - USB PHY General Control Register */
/*! @{ */

#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
/*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ */
#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)

#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK  (0x2U)
#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
/*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT */
#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)

#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK     (0x4U)
#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT    (2U)
/*! ENIRQHOSTDISCON - ENIRQHOSTDISCON */
#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)

#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
/*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ */
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)

#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK   (0x10U)
#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT  (4U)
/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection */
#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)

#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK  (0x20U)
#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
/*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY */
#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)

#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK      (0x40U)
#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT     (6U)
/*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ */
#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)

#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK       (0x80U)
#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT      (7U)
/*! ENOTGIDDETECT - ENOTGIDDETECT */
#define USBPHY_CTRL_SET_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)

#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK     (0x100U)
#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT    (8U)
/*! RESUMEIRQSTICKY - RESUMEIRQSTICKY */
#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)

#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK   (0x200U)
#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT  (9U)
/*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT */
#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)

#define USBPHY_CTRL_SET_RESUME_IRQ_MASK          (0x400U)
#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT         (10U)
/*! RESUME_IRQ - RESUME_IRQ */
#define USBPHY_CTRL_SET_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)

#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK      (0x800U)
#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT     (11U)
/*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN */
#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)

#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK       (0x1000U)
#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT      (12U)
/*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ */
#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)

#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK        (0x4000U)
#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT       (14U)
/*! ENUTMILEVEL2 - ENUTMILEVEL2 */
#define USBPHY_CTRL_SET_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)

#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK        (0x8000U)
#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT       (15U)
/*! ENUTMILEVEL3 - ENUTMILEVEL3 */
#define USBPHY_CTRL_SET_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)

#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK         (0x10000U)
#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT        (16U)
/*! ENIRQWAKEUP - ENIRQWAKEUP */
#define USBPHY_CTRL_SET_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)

#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK          (0x20000U)
#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT         (17U)
/*! WAKEUP_IRQ - WAKEUP_IRQ */
#define USBPHY_CTRL_SET_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)

#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK       (0x40000U)
#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT      (18U)
/*! AUTORESUME_EN - AUTORESUME_EN */
#define USBPHY_CTRL_SET_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)

#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT  (19U)
/*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE */
#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)

#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
/*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD */
#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)

#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK      (0x200000U)
#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT     (21U)
/*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP */
#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)

#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK        (0x400000U)
#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT       (22U)
/*! ENIDCHG_WKUP - ENIDCHG_WKUP */
#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)

#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK      (0x800000U)
#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT     (23U)
/*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP */
#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)

#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK        (0x1000000U)
#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT       (24U)
/*! FSDLL_RST_EN - FSDLL_RST_EN */
#define USBPHY_CTRL_SET_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)

#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK        (0x8000000U)
#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT       (27U)
/*! OTG_ID_VALUE - OTG_ID_VALUE */
#define USBPHY_CTRL_SET_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)

#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT  (28U)
/*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0 */
#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)

#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK       (0x20000000U)
#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT      (29U)
/*! UTMI_SUSPENDM - UTMI_SUSPENDM */
#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)

#define USBPHY_CTRL_SET_CLKGATE_MASK             (0x40000000U)
#define USBPHY_CTRL_SET_CLKGATE_SHIFT            (30U)
/*! CLKGATE - CLKGATE */
#define USBPHY_CTRL_SET_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)

#define USBPHY_CTRL_SET_SFTRST_MASK              (0x80000000U)
#define USBPHY_CTRL_SET_SFTRST_SHIFT             (31U)
/*! SFTRST - SFTRST */
#define USBPHY_CTRL_SET_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
/*! @} */

/*! @name CTRL_CLR - USB PHY General Control Register */
/*! @{ */

#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
/*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ */
#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)

#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK  (0x2U)
#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
/*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT */
#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)

#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK     (0x4U)
#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT    (2U)
/*! ENIRQHOSTDISCON - ENIRQHOSTDISCON */
#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)

#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
/*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ */
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)

#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK   (0x10U)
#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT  (4U)
/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection */
#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)

#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK  (0x20U)
#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
/*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY */
#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)

#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK      (0x40U)
#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT     (6U)
/*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ */
#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)

#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK       (0x80U)
#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT      (7U)
/*! ENOTGIDDETECT - ENOTGIDDETECT */
#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)

#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK     (0x100U)
#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT    (8U)
/*! RESUMEIRQSTICKY - RESUMEIRQSTICKY */
#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)

#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK   (0x200U)
#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT  (9U)
/*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT */
#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)

#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK          (0x400U)
#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT         (10U)
/*! RESUME_IRQ - RESUME_IRQ */
#define USBPHY_CTRL_CLR_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)

#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK      (0x800U)
#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT     (11U)
/*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN */
#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)

#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK       (0x1000U)
#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT      (12U)
/*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ */
#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)

#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK        (0x4000U)
#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT       (14U)
/*! ENUTMILEVEL2 - ENUTMILEVEL2 */
#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)

#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK        (0x8000U)
#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT       (15U)
/*! ENUTMILEVEL3 - ENUTMILEVEL3 */
#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)

#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK         (0x10000U)
#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT        (16U)
/*! ENIRQWAKEUP - ENIRQWAKEUP */
#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)

#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK          (0x20000U)
#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT         (17U)
/*! WAKEUP_IRQ - WAKEUP_IRQ */
#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)

#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK       (0x40000U)
#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT      (18U)
/*! AUTORESUME_EN - AUTORESUME_EN */
#define USBPHY_CTRL_CLR_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)

#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT  (19U)
/*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE */
#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)

#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
/*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD */
#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)

#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK      (0x200000U)
#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT     (21U)
/*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP */
#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)

#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK        (0x400000U)
#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT       (22U)
/*! ENIDCHG_WKUP - ENIDCHG_WKUP */
#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)

#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK      (0x800000U)
#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT     (23U)
/*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP */
#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)

#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK        (0x1000000U)
#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT       (24U)
/*! FSDLL_RST_EN - FSDLL_RST_EN */
#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)

#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK        (0x8000000U)
#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT       (27U)
/*! OTG_ID_VALUE - OTG_ID_VALUE */
#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)

#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT  (28U)
/*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0 */
#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)

#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK       (0x20000000U)
#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT      (29U)
/*! UTMI_SUSPENDM - UTMI_SUSPENDM */
#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)

#define USBPHY_CTRL_CLR_CLKGATE_MASK             (0x40000000U)
#define USBPHY_CTRL_CLR_CLKGATE_SHIFT            (30U)
/*! CLKGATE - CLKGATE */
#define USBPHY_CTRL_CLR_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)

#define USBPHY_CTRL_CLR_SFTRST_MASK              (0x80000000U)
#define USBPHY_CTRL_CLR_SFTRST_SHIFT             (31U)
/*! SFTRST - SFTRST */
#define USBPHY_CTRL_CLR_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
/*! @} */

/*! @name CTRL_TOG - USB PHY General Control Register */
/*! @{ */

#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
/*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ */
#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)

#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK  (0x2U)
#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
/*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT */
#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)

#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK     (0x4U)
#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT    (2U)
/*! ENIRQHOSTDISCON - ENIRQHOSTDISCON */
#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)

#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
/*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ */
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)

#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK   (0x10U)
#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT  (4U)
/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection */
#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)

#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK  (0x20U)
#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
/*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY */
#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)

#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK      (0x40U)
#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT     (6U)
/*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ */
#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)

#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK       (0x80U)
#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT      (7U)
/*! ENOTGIDDETECT - ENOTGIDDETECT */
#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)

#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK     (0x100U)
#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT    (8U)
/*! RESUMEIRQSTICKY - RESUMEIRQSTICKY */
#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)

#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK   (0x200U)
#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT  (9U)
/*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT */
#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)

#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK          (0x400U)
#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT         (10U)
/*! RESUME_IRQ - RESUME_IRQ */
#define USBPHY_CTRL_TOG_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)

#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK      (0x800U)
#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT     (11U)
/*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN */
#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)

#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK       (0x1000U)
#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT      (12U)
/*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ */
#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)

#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK        (0x4000U)
#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT       (14U)
/*! ENUTMILEVEL2 - ENUTMILEVEL2 */
#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)

#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK        (0x8000U)
#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT       (15U)
/*! ENUTMILEVEL3 - ENUTMILEVEL3 */
#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)

#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK         (0x10000U)
#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT        (16U)
/*! ENIRQWAKEUP - ENIRQWAKEUP */
#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)

#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK          (0x20000U)
#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT         (17U)
/*! WAKEUP_IRQ - WAKEUP_IRQ */
#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)

#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK       (0x40000U)
#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT      (18U)
/*! AUTORESUME_EN - AUTORESUME_EN */
#define USBPHY_CTRL_TOG_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)

#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT  (19U)
/*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE */
#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)

#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
/*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD */
#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)

#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK      (0x200000U)
#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT     (21U)
/*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP */
#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)

#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK        (0x400000U)
#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT       (22U)
/*! ENIDCHG_WKUP - ENIDCHG_WKUP */
#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)

#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK      (0x800000U)
#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT     (23U)
/*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP */
#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)

#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK        (0x1000000U)
#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT       (24U)
/*! FSDLL_RST_EN - FSDLL_RST_EN */
#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)

#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK        (0x8000000U)
#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT       (27U)
/*! OTG_ID_VALUE - OTG_ID_VALUE */
#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)

#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT  (28U)
/*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0 */
#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)

#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK       (0x20000000U)
#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT      (29U)
/*! UTMI_SUSPENDM - UTMI_SUSPENDM */
#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)

#define USBPHY_CTRL_TOG_CLKGATE_MASK             (0x40000000U)
#define USBPHY_CTRL_TOG_CLKGATE_SHIFT            (30U)
/*! CLKGATE - CLKGATE */
#define USBPHY_CTRL_TOG_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)

#define USBPHY_CTRL_TOG_SFTRST_MASK              (0x80000000U)
#define USBPHY_CTRL_TOG_SFTRST_SHIFT             (31U)
/*! SFTRST - SFTRST */
#define USBPHY_CTRL_TOG_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
/*! @} */

/*! @name STATUS - USB PHY Status Register */
/*! @{ */

#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
/*! HOSTDISCONDETECT_STATUS - HOSTDISCONDETECT_STATUS
 *  0b0..USB cable disconnect has not been detected at the local host
 *  0b1..USB cable disconnect has been detected at the local host
 */
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)

#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK      (0x40U)
#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT     (6U)
/*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection
 *  0b0..No attachment to a USB host is detected
 *  0b1..Cable attachment to a USB host is detected
 */
#define USBPHY_STATUS_DEVPLUGIN_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)

#define USBPHY_STATUS_OTGID_STATUS_MASK          (0x100U)
#define USBPHY_STATUS_OTGID_STATUS_SHIFT         (8U)
/*! OTGID_STATUS - OTGID_STATUS */
#define USBPHY_STATUS_OTGID_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)

#define USBPHY_STATUS_RESUME_STATUS_MASK         (0x400U)
#define USBPHY_STATUS_RESUME_STATUS_SHIFT        (10U)
/*! RESUME_STATUS - RESUME_STATUS */
#define USBPHY_STATUS_RESUME_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
/*! @} */

/*! @name DEBUG - USB PHY Debug Register */
/*! @{ */

#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK           (0x1U)
#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT          (0U)
/*! OTGIDPIOLOCK - OTGIDPIOLOCK */
#define USBPHY_DEBUG_OTGIDPIOLOCK(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)

#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK   (0x2U)
#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT  (1U)
/*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD */
#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)

#define USBPHY_DEBUG_HSTPULLDOWN_MASK            (0xCU)
#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT           (2U)
/*! HSTPULLDOWN - HSTPULLDOWN */
#define USBPHY_DEBUG_HSTPULLDOWN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)

#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK          (0x30U)
#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT         (4U)
/*! ENHSTPULLDOWN - ENHSTPULLDOWN */
#define USBPHY_DEBUG_ENHSTPULLDOWN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)

#define USBPHY_DEBUG_TX2RXCOUNT_MASK             (0xF00U)
#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT            (8U)
/*! TX2RXCOUNT - TX2RXCOUNT */
#define USBPHY_DEBUG_TX2RXCOUNT(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)

#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK           (0x1000U)
#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT          (12U)
/*! ENTX2RXCOUNT - ENTX2RXCOUNT */
#define USBPHY_DEBUG_ENTX2RXCOUNT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)

#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK      (0x1F0000U)
#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT     (16U)
/*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT */
#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)

#define USBPHY_DEBUG_ENSQUELCHRESET_MASK         (0x1000000U)
#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT        (24U)
/*! ENSQUELCHRESET - ENSQUELCHRESET */
#define USBPHY_DEBUG_ENSQUELCHRESET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)

#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK     (0x1E000000U)
#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT    (25U)
/*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH */
#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)

#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK      (0x20000000U)
#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT     (29U)
/*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG */
#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)

#define USBPHY_DEBUG_CLKGATE_MASK                (0x40000000U)
#define USBPHY_DEBUG_CLKGATE_SHIFT               (30U)
/*! CLKGATE - CLKGATE */
#define USBPHY_DEBUG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
/*! @} */

/*! @name DEBUG_SET - USB PHY Debug Register */
/*! @{ */

#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK       (0x1U)
#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT      (0U)
/*! OTGIDPIOLOCK - OTGIDPIOLOCK */
#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)

#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
/*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD */
#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)

#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK        (0xCU)
#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT       (2U)
/*! HSTPULLDOWN - HSTPULLDOWN */
#define USBPHY_DEBUG_SET_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)

#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK      (0x30U)
#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT     (4U)
/*! ENHSTPULLDOWN - ENHSTPULLDOWN */
#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)

#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK         (0xF00U)
#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT        (8U)
/*! TX2RXCOUNT - TX2RXCOUNT */
#define USBPHY_DEBUG_SET_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)

#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK       (0x1000U)
#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT      (12U)
/*! ENTX2RXCOUNT - ENTX2RXCOUNT */
#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)

#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
/*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT */
#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)

#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK     (0x1000000U)
#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT    (24U)
/*! ENSQUELCHRESET - ENSQUELCHRESET */
#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)

#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
/*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH */
#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)

#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK  (0x20000000U)
#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
/*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG */
#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)

#define USBPHY_DEBUG_SET_CLKGATE_MASK            (0x40000000U)
#define USBPHY_DEBUG_SET_CLKGATE_SHIFT           (30U)
/*! CLKGATE - CLKGATE */
#define USBPHY_DEBUG_SET_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
/*! @} */

/*! @name DEBUG_CLR - USB PHY Debug Register */
/*! @{ */

#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK       (0x1U)
#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT      (0U)
/*! OTGIDPIOLOCK - OTGIDPIOLOCK */
#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)

#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
/*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD */
#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)

#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK        (0xCU)
#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT       (2U)
/*! HSTPULLDOWN - HSTPULLDOWN */
#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)

#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK      (0x30U)
#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT     (4U)
/*! ENHSTPULLDOWN - ENHSTPULLDOWN */
#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)

#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK         (0xF00U)
#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT        (8U)
/*! TX2RXCOUNT - TX2RXCOUNT */
#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)

#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK       (0x1000U)
#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT      (12U)
/*! ENTX2RXCOUNT - ENTX2RXCOUNT */
#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)

#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
/*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT */
#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)

#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK     (0x1000000U)
#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT    (24U)
/*! ENSQUELCHRESET - ENSQUELCHRESET */
#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)

#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
/*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH */
#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)

#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK  (0x20000000U)
#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
/*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG */
#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)

#define USBPHY_DEBUG_CLR_CLKGATE_MASK            (0x40000000U)
#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT           (30U)
/*! CLKGATE - CLKGATE */
#define USBPHY_DEBUG_CLR_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
/*! @} */

/*! @name DEBUG_TOG - USB PHY Debug Register */
/*! @{ */

#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK       (0x1U)
#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT      (0U)
/*! OTGIDPIOLOCK - OTGIDPIOLOCK */
#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)

#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
/*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD */
#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)

#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK        (0xCU)
#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT       (2U)
/*! HSTPULLDOWN - HSTPULLDOWN */
#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)

#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK      (0x30U)
#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT     (4U)
/*! ENHSTPULLDOWN - ENHSTPULLDOWN */
#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)

#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK         (0xF00U)
#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT        (8U)
/*! TX2RXCOUNT - TX2RXCOUNT */
#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)

#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK       (0x1000U)
#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT      (12U)
/*! ENTX2RXCOUNT - ENTX2RXCOUNT */
#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)

#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
/*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT */
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)

#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK     (0x1000000U)
#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT    (24U)
/*! ENSQUELCHRESET - ENSQUELCHRESET */
#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)

#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
/*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH */
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)

#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK  (0x20000000U)
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
/*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG */
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)

#define USBPHY_DEBUG_TOG_CLKGATE_MASK            (0x40000000U)
#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT           (30U)
/*! CLKGATE - CLKGATE */
#define USBPHY_DEBUG_TOG_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
/*! @} */

/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
/*! @{ */

#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
/*! LOOP_BACK_FAIL_COUNT - LOOP_BACK_FAIL_COUNT */
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)

#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
/*! UTMI_RXERROR_FAIL_COUNT - UTMI_RXERROR_FAIL_COUNT */
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)

#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK  (0xFC000000U)
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
/*! SQUELCH_COUNT - SQUELCH_COUNT */
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
/*! @} */

/*! @name DEBUG1 - UTMI Debug Status Register 1 */
/*! @{ */

#define USBPHY_DEBUG1_ENTAILADJVD_MASK           (0x6000U)
#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT          (13U)
/*! ENTAILADJVD - ENTAILADJVD
 *  0b00..Delay is nominal
 *  0b01..Delay is +20%
 *  0b10..Delay is -20%
 *  0b11..Delay is -40%
 */
#define USBPHY_DEBUG1_ENTAILADJVD(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)

#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
/*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. */
#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK)

#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
/*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register. */
#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK)

#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK   (0x20000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT  (17U)
/*! USB2_REFBIAS_LOWPWR - to be added */
#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK)

#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK   (0x1C0000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT  (18U)
/*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */
#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK      (0x600000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT     (21U)
/*! USB2_REFBIAS_TST - Bias current control for usb2_phy */
#define USBPHY_DEBUG1_USB2_REFBIAS_TST(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK)
/*! @} */

/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
/*! @{ */

#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK       (0x6000U)
#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT      (13U)
/*! ENTAILADJVD - ENTAILADJVD */
#define USBPHY_DEBUG1_SET_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)

#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
/*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. */
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK)

#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
/*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register. */
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK)

#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT (17U)
/*! USB2_REFBIAS_LOWPWR - to be added */
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK)

#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U)
/*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK  (0x600000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U)
/*! USB2_REFBIAS_TST - Bias current control for usb2_phy */
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK)
/*! @} */

/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
/*! @{ */

#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK       (0x6000U)
#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT      (13U)
/*! ENTAILADJVD - ENTAILADJVD */
#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)

#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
/*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. */
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK)

#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
/*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register. */
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK)

#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT (17U)
/*! USB2_REFBIAS_LOWPWR - to be added */
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK)

#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U)
/*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK  (0x600000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U)
/*! USB2_REFBIAS_TST - Bias current control for usb2_phy */
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK)
/*! @} */

/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
/*! @{ */

#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK       (0x6000U)
#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT      (13U)
/*! ENTAILADJVD - ENTAILADJVD */
#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)

#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
/*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. */
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK)

#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
/*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register. */
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK)

#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT (17U)
/*! USB2_REFBIAS_LOWPWR - to be added */
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK)

#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U)
/*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK  (0x600000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U)
/*! USB2_REFBIAS_TST - Bias current control for usb2_phy */
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK)
/*! @} */

/*! @name VERSION - UTMI RTL Version */
/*! @{ */

#define USBPHY_VERSION_STEP_MASK                 (0xFFFFU)
#define USBPHY_VERSION_STEP_SHIFT                (0U)
/*! STEP - STEP */
#define USBPHY_VERSION_STEP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)

#define USBPHY_VERSION_MINOR_MASK                (0xFF0000U)
#define USBPHY_VERSION_MINOR_SHIFT               (16U)
/*! MINOR - MINOR */
#define USBPHY_VERSION_MINOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)

#define USBPHY_VERSION_MAJOR_MASK                (0xFF000000U)
#define USBPHY_VERSION_MAJOR_SHIFT               (24U)
/*! MAJOR - MAJOR */
#define USBPHY_VERSION_MAJOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
/*! @} */

/*! @name PLL_SIC - USB PHY PLL Control/Status Register */
/*! @{ */

#define USBPHY_PLL_SIC_PLL_POSTDIV_MASK          (0x1CU)
#define USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT         (2U)
/*! PLL_POSTDIV - PLL_POSTDIV */
#define USBPHY_PLL_SIC_PLL_POSTDIV(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_POSTDIV_MASK)

#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK      (0x40U)
#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT     (6U)
/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS */
#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)

#define USBPHY_PLL_SIC_PLL_POWER_MASK            (0x1000U)
#define USBPHY_PLL_SIC_PLL_POWER_SHIFT           (12U)
/*! PLL_POWER - PLL_POWER */
#define USBPHY_PLL_SIC_PLL_POWER(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)

#define USBPHY_PLL_SIC_PLL_ENABLE_MASK           (0x2000U)
#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT          (13U)
/*! PLL_ENABLE - PLL_ENABLE */
#define USBPHY_PLL_SIC_PLL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)

#define USBPHY_PLL_SIC_PLL_BYPASS_MASK           (0x10000U)
#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT          (16U)
/*! PLL_BYPASS - PLL_BYPASS */
#define USBPHY_PLL_SIC_PLL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)

#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK      (0x80000U)
#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT     (19U)
/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
 *  0b0..Selects PLL_POWER to control the reference bias
 *  0b1..Selects REFBIAS_PWD to control the reference bias.
 */
#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)

#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK          (0x100000U)
#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT         (20U)
/*! REFBIAS_PWD - Power down the reference bias */
#define USBPHY_PLL_SIC_REFBIAS_PWD(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)

#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK       (0x200000U)
#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT      (21U)
/*! PLL_REG_ENABLE - PLL_REG_ENABLE */
#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)

#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK          (0x1C00000U)
#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT         (22U)
/*! PLL_DIV_SEL - PLL_DIV_SEL
 *  0b000..Divide by 13
 *  0b001..Divide by 15
 *  0b010..Divide by 16
 *  0b011..Divide by 20
 *  0b100..Divide by 22
 *  0b101..Divide by 25
 *  0b110..Divide by 30
 *  0b111..Divide by 240
 */
#define USBPHY_PLL_SIC_PLL_DIV_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)

#define USBPHY_PLL_SIC_PLL_LOCK_MASK             (0x80000000U)
#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT            (31U)
/*! PLL_LOCK - PLL_LOCK
 *  0b0..PLL is not currently locked
 *  0b1..PLL is currently locked
 */
#define USBPHY_PLL_SIC_PLL_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
/*! @} */

/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
/*! @{ */

#define USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK      (0x1CU)
#define USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT     (2U)
/*! PLL_POSTDIV - PLL_POSTDIV */
#define USBPHY_PLL_SIC_SET_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK)

#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK  (0x40U)
#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS */
#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)

#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK        (0x1000U)
#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT       (12U)
/*! PLL_POWER - PLL_POWER */
#define USBPHY_PLL_SIC_SET_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)

#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK       (0x2000U)
#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT      (13U)
/*! PLL_ENABLE - PLL_ENABLE */
#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)

#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK       (0x10000U)
#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT      (16U)
/*! PLL_BYPASS - PLL_BYPASS */
#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)

#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK  (0x80000U)
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL */
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)

#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK      (0x100000U)
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT     (20U)
/*! REFBIAS_PWD - Power down the reference bias */
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)

#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK   (0x200000U)
#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT  (21U)
/*! PLL_REG_ENABLE - PLL_REG_ENABLE */
#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)

#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK      (0x1C00000U)
#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT     (22U)
/*! PLL_DIV_SEL - PLL_DIV_SEL */
#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)

#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK         (0x80000000U)
#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT        (31U)
/*! PLL_LOCK - PLL_LOCK */
#define USBPHY_PLL_SIC_SET_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
/*! @} */

/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
/*! @{ */

#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK      (0x1CU)
#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT     (2U)
/*! PLL_POSTDIV - PLL_POSTDIV */
#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK  (0x40U)
#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS */
#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK        (0x1000U)
#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT       (12U)
/*! PLL_POWER - PLL_POWER */
#define USBPHY_PLL_SIC_CLR_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK       (0x2000U)
#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT      (13U)
/*! PLL_ENABLE - PLL_ENABLE */
#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK       (0x10000U)
#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT      (16U)
/*! PLL_BYPASS - PLL_BYPASS */
#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)

#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK  (0x80000U)
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL */
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)

#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK      (0x100000U)
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT     (20U)
/*! REFBIAS_PWD - Power down the reference bias */
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK   (0x200000U)
#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT  (21U)
/*! PLL_REG_ENABLE - PLL_REG_ENABLE */
#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK      (0x1C00000U)
#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT     (22U)
/*! PLL_DIV_SEL - PLL_DIV_SEL */
#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)

#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK         (0x80000000U)
#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT        (31U)
/*! PLL_LOCK - PLL_LOCK */
#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
/*! @} */

/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
/*! @{ */

#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK      (0x1CU)
#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT     (2U)
/*! PLL_POSTDIV - PLL_POSTDIV */
#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK  (0x40U)
#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS */
#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK        (0x1000U)
#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT       (12U)
/*! PLL_POWER - PLL_POWER */
#define USBPHY_PLL_SIC_TOG_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK       (0x2000U)
#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT      (13U)
/*! PLL_ENABLE - PLL_ENABLE */
#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK       (0x10000U)
#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT      (16U)
/*! PLL_BYPASS - PLL_BYPASS */
#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)

#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK  (0x80000U)
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL */
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)

#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK      (0x100000U)
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT     (20U)
/*! REFBIAS_PWD - Power down the reference bias */
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK   (0x200000U)
#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT  (21U)
/*! PLL_REG_ENABLE - PLL_REG_ENABLE */
#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK      (0x1C00000U)
#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT     (22U)
/*! PLL_DIV_SEL - PLL_DIV_SEL */
#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)

#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK         (0x80000000U)
#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT        (31U)
/*! PLL_LOCK - PLL_LOCK */
#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
/*! @} */

/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
/*! @{ */

#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH - VBUSVALID_THRESH
 *  0b000..4.0 V
 *  0b001..4.1 V
 *  0b010..4.2 V
 *  0b011..4.3 V
 *  0b100..4.4 V (Default)
 *  0b101..4.5 V
 *  0b110..4.6 V
 *  0b111..4.7 V
 */
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)

#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
 *  0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
 *  0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
 */
#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)

#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
/*! SESSEND_OVERRIDE - Override value for SESSEND */
#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
/*! BVALID_OVERRIDE - Override value for B-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
/*! AVALID_OVERRIDE - Override value for A-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
 *  0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
 *  0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
 */
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
 *  0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
 *  0b01..Use the Session Valid comparator results for signal reported to the USB controller
 *  0b10..Use the Session Valid comparator results for signal reported to the USB controller
 *  0b11..Reserved, do not use
 */
#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U)
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U)
/*! ID_OVERRIDE_EN - TBA */
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK)

#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U)
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U)
/*! ID_OVERRIDE - TBA */
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
 *  0b0..Use the VBUS_VALID comparator for VBUS_VALID results
 *  0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
 */
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)

#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK  (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
 *  0b000..Powers down the VBUS_VALID comparator
 *  0b001..Enables the SESS_VALID comparator (default)
 *  0b010..Enables the 3Vdetect (default)
 */
#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)

#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
 *  0b0..VBUS discharge resistor is disabled (Default)
 *  0b1..VBUS discharge resistor is enabled
 */
#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)

#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
 *  0b0..Disable resistive charger detection resistors on DP and DP
 *  0b1..Enable resistive charger detection resistors on DP and DP
 */
#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
/*! @} */

/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */
/*! @{ */

#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH - VBUSVALID_THRESH */
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable */
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
/*! SESSEND_OVERRIDE - Override value for SESSEND */
#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
/*! BVALID_OVERRIDE - Override value for B-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
/*! AVALID_OVERRIDE - Override value for A-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller */
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller */
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U)
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U)
/*! ID_OVERRIDE_EN - TBA */
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U)
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U)
/*! ID_OVERRIDE - TBA */
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID */
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS - Enables the VBUS_VALID comparator */
#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS - Controls VBUS discharge resistor */
#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)

#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection */
#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
/*! @} */

/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */
/*! @{ */

#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH - VBUSVALID_THRESH */
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable */
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
/*! SESSEND_OVERRIDE - Override value for SESSEND */
#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
/*! BVALID_OVERRIDE - Override value for B-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
/*! AVALID_OVERRIDE - Override value for A-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller */
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller */
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U)
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U)
/*! ID_OVERRIDE_EN - TBA */
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U)
/*! ID_OVERRIDE - TBA */
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID */
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS - Enables the VBUS_VALID comparator */
#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS - Controls VBUS discharge resistor */
#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)

#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection */
#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
/*! @} */

/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */
/*! @{ */

#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH - VBUSVALID_THRESH */
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable */
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
/*! SESSEND_OVERRIDE - Override value for SESSEND */
#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
/*! BVALID_OVERRIDE - Override value for B-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
/*! AVALID_OVERRIDE - Override value for A-Device Session Valid */
#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller */
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller */
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U)
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U)
/*! ID_OVERRIDE_EN - TBA */
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U)
/*! ID_OVERRIDE - TBA */
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID */
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS - Enables the VBUS_VALID comparator */
#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS - Controls VBUS discharge resistor */
#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)

#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection */
#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
/*! @} */

/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */
/*! @{ */

#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK   (0x1U)
#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT  (0U)
/*! SESSEND - Session End indicator
 *  0b0..The VBUS voltage is above the Session Valid threshold
 *  0b1..The VBUS voltage is below the Session Valid threshold
 */
#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)

#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK    (0x2U)
#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT   (1U)
/*! BVALID - B-Device Session Valid status
 *  0b0..The VBUS voltage is below the Session Valid threshold
 *  0b1..The VBUS voltage is above the Session Valid threshold
 */
#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)

#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK    (0x4U)
#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT   (2U)
/*! AVALID - A-Device Session Valid status
 *  0b0..The VBUS voltage is below the Session Valid threshold
 *  0b1..The VBUS voltage is above the Session Valid threshold
 */
#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)

#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
/*! VBUS_VALID - VBUS voltage status
 *  0b0..VBUS is below the comparator threshold
 *  0b1..VBUS is above the comparator threshold
 */
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)

#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
/*! VBUS_VALID_3V - VBUS_VALID_3V detector status
 *  0b0..VBUS voltage is below VBUS_VALID_3V threshold
 *  0b1..VBUS voltage is above VBUS_VALID_3V threshold
 */
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
/*! @} */

/*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */
/*! @{ */

#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK   (0x4U)
#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT  (2U)
/*! PULLUP_DP - PULLUP_DP */
#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK)

#define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK    (0x800000U)
#define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT   (23U)
/*! BGR_BIAS - BGR_BIAS
 *  0b0..Use local bias powered from USB1_VBUS for 10uA reference (Default)
 *  0b1..Use bandgap bias powered from VREGIN0/VREGIN1 for 10uA reference
 */
#define USBPHY_USB1_CHRG_DETECT_BGR_BIAS(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK)

#define USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK      (0x80000000U)
#define USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT     (31U)
/*! DCDSEL - Selects control source for Battery Charging Detection
 *  0b0..Bit fields in USB1_CHRG_DETECT control BC 1.2 functionality
 *  0b1..Bit fields and state machines in USBHSDCD module control BC 1.2 functionality
 */
#define USBPHY_USB1_CHRG_DETECT_DCDSEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK)
/*! @} */

/*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */
/*! @{ */

#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U)
#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U)
/*! PULLUP_DP - PULLUP_DP */
#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK)

#define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK (0x800000U)
#define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT (23U)
/*! BGR_BIAS - BGR_BIAS */
#define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK)

#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK  (0x80000000U)
#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT (31U)
/*! DCDSEL - Selects control source for Battery Charging Detection */
#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK)
/*! @} */

/*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */
/*! @{ */

#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U)
#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U)
/*! PULLUP_DP - PULLUP_DP */
#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK)

#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK (0x800000U)
#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT (23U)
/*! BGR_BIAS - BGR_BIAS */
#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK)

#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK  (0x80000000U)
#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT (31U)
/*! DCDSEL - Selects control source for Battery Charging Detection */
#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK)
/*! @} */

/*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */
/*! @{ */

#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U)
#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U)
/*! PULLUP_DP - PULLUP_DP */
#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK)

#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK (0x800000U)
#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT (23U)
/*! BGR_BIAS - BGR_BIAS */
#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK)

#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK  (0x80000000U)
#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT (31U)
/*! DCDSEL - Selects control source for Battery Charging Detection */
#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK)
/*! @} */

/*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */
/*! @{ */

#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
/*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output
 *  0b0..No USB cable attachment has been detected
 *  0b1..A USB cable attachment between the device and host has been detected
 */
#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)

#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
/*! CHRG_DETECTED - Battery Charging Primary Detection phase output
 *  0b0..Standard Downstream Port (SDP) has been detected
 *  0b1..Charging Port has been detected
 */
#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)

#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK  (0x4U)
#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT (2U)
/*! DN_STATE - DN_STATE
 *  0b0..DN pin voltage is < 0.8V
 *  0b1..DN pin voltage is > 2.0V
 */
#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK)

#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK  (0x8U)
#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
/*! DP_STATE - DP_STATE
 *  0b0..DP pin voltage is < 0.8V
 *  0b1..DP pin voltage is > 2.0V
 */
#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)

#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
/*! SECDET_DCP - Battery Charging Secondary Detection phase output
 *  0b0..Charging Downstream Port (CDP) has been detected
 *  0b1..Downstream Charging Port (DCP) has been detected
 */
#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
/*! @} */

/*! @name ANACTRL - USB PHY Analog Control Register */
/*! @{ */

#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK         (0x400U)
#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT        (10U)
/*! DEV_PULLDOWN - DEV_PULLDOWN
 *  0b0..The 15kohm nominal pulldowns on the DP and DN pinsare disabled in device mode.
 *  0b1..The 15kohm nominal pulldowns on the DP and DN pinsare enabled in device mode.
 */
#define USBPHY_ANACTRL_DEV_PULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
/*! @} */

/*! @name ANACTRL_SET - USB PHY Analog Control Register */
/*! @{ */

#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK     (0x400U)
#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT    (10U)
/*! DEV_PULLDOWN - DEV_PULLDOWN */
#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
/*! @} */

/*! @name ANACTRL_CLR - USB PHY Analog Control Register */
/*! @{ */

#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK     (0x400U)
#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT    (10U)
/*! DEV_PULLDOWN - DEV_PULLDOWN */
#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
/*! @} */

/*! @name ANACTRL_TOG - USB PHY Analog Control Register */
/*! @{ */

#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK     (0x400U)
#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT    (10U)
/*! DEV_PULLDOWN - DEV_PULLDOWN */
#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
/*! @} */

/*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
/*! UTMI_TESTSTART - UTMI_TESTSTART */
#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)

#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK  (0x2U)
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
/*! UTMI_DIG_TST0 - UTMI_DIG_TST0 */
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK  (0x4U)
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
/*! UTMI_DIG_TST1 - UTMI_DIG_TST1 */
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
/*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE */
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
/*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE */
#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK     (0x20U)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT    (5U)
/*! TSTI_TX_EN - TSTI_TX_EN */
#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)

#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK    (0x40U)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT   (6U)
/*! TSTI_TX_HIZ - TSTI_TX_HIZ */
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)

#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK  (0x80U)
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
/*! UTMO_DIG_TST0 - UTMO_DIG_TST0 */
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK  (0x100U)
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
/*! UTMO_DIG_TST1 - UTMO_DIG_TST1 */
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN */
#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)

#define USBPHY_USB1_LOOPBACK_TSTPKT_MASK         (0xFF0000U)
#define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT        (16U)
/*! TSTPKT - TSTPKT */
#define USBPHY_USB1_LOOPBACK_TSTPKT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
/*! UTMI_TESTSTART - UTMI_TESTSTART */
#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)

#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
/*! UTMI_DIG_TST0 - UTMI_DIG_TST0 */
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
/*! UTMI_DIG_TST1 - UTMI_DIG_TST1 */
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
/*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE */
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
/*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE */
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
/*! TSTI_TX_EN - TSTI_TX_EN */
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)

#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
/*! TSTI_TX_HIZ - TSTI_TX_HIZ */
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)

#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
/*! UTMO_DIG_TST0 - UTMO_DIG_TST0 */
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
/*! UTMO_DIG_TST1 - UTMO_DIG_TST1 */
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN */
#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)

#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK     (0xFF0000U)
#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT    (16U)
/*! TSTPKT - TSTPKT */
#define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
/*! UTMI_TESTSTART - UTMI_TESTSTART */
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
/*! UTMI_DIG_TST0 - UTMI_DIG_TST0 */
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
/*! UTMI_DIG_TST1 - UTMI_DIG_TST1 */
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
/*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE */
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
/*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE */
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
/*! TSTI_TX_EN - TSTI_TX_EN */
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
/*! TSTI_TX_HIZ - TSTI_TX_HIZ */
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
/*! UTMO_DIG_TST0 - UTMO_DIG_TST0 */
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
/*! UTMO_DIG_TST1 - UTMO_DIG_TST1 */
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN */
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)

#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK     (0xFF0000U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT    (16U)
/*! TSTPKT - TSTPKT */
#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
/*! UTMI_TESTSTART - UTMI_TESTSTART */
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
/*! UTMI_DIG_TST0 - UTMI_DIG_TST0 */
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
/*! UTMI_DIG_TST1 - UTMI_DIG_TST1 */
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
/*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE */
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
/*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE */
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
/*! TSTI_TX_EN - TSTI_TX_EN */
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
/*! TSTI_TX_HIZ - TSTI_TX_HIZ */
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
/*! UTMO_DIG_TST0 - UTMO_DIG_TST0 */
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
/*! UTMO_DIG_TST1 - UTMO_DIG_TST1 */
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN */
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)

#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK     (0xFF0000U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT    (16U)
/*! TSTPKT - TSTPKT */
#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
/*! TSTI_HS_NUMBER - TSTI_HS_NUMBER */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)

#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
/*! TSTI_FS_NUMBER - TSTI_FS_NUMBER */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
/*! TSTI_HS_NUMBER - TSTI_HS_NUMBER */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)

#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
/*! TSTI_FS_NUMBER - TSTI_FS_NUMBER */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
/*! TSTI_HS_NUMBER - TSTI_HS_NUMBER */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)

#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
/*! TSTI_FS_NUMBER - TSTI_FS_NUMBER */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
/*! @} */

/*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */
/*! @{ */

#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
/*! TSTI_HS_NUMBER - TSTI_HS_NUMBER */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)

#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
/*! TSTI_FS_NUMBER - TSTI_FS_NUMBER */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
/*! @} */

/*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */
/*! @{ */

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
/*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
/*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
/*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
/*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
/*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
/*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
/*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
/*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
/*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
/*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
/*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
/*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK)
/*! @} */

/*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */
/*! @{ */

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
/*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
/*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
/*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
/*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
/*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
/*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
/*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
/*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
/*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
/*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
/*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
/*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK)
/*! @} */

/*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */
/*! @{ */

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
/*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
/*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
/*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
/*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
/*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
/*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
/*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
/*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
/*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
/*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
/*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
/*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK)
/*! @} */

/*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */
/*! @{ */

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
/*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
/*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
/*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
/*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
/*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
/*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
/*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
/*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
/*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
/*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
/*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)

#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
/*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USBPHY_Register_Masks */


/* USBPHY - Peripheral instance base addresses */
/** Peripheral USB0_PHY base address */
#define USB0_PHY_BASE                            (0x29910000u)
/** Peripheral USB0_PHY base pointer */
#define USB0_PHY                                 ((USBPHY_Type *)USB0_PHY_BASE)
/** Peripheral USB1_PHY base address */
#define USB1_PHY_BASE                            (0x29930000u)
/** Peripheral USB1_PHY base pointer */
#define USB1_PHY                                 ((USBPHY_Type *)USB1_PHY_BASE)
/** Array initializer of USBPHY peripheral base addresses */
#define USBPHY_BASE_ADDRS                        { USB0_PHY_BASE, USB1_PHY_BASE }
/** Array initializer of USBPHY peripheral base pointers */
#define USBPHY_BASE_PTRS                         { USB0_PHY, USB1_PHY }
/* Backward compatibility */
#define USBPHY_CTRL_ENDEVPLUGINDET_MASK     USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT    USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
#define USBPHY_CTRL_ENDEVPLUGINDET(x)       USBPHY_CTRL_ENDEVPLUGINDETECT(x)
#define USBPHY_TX_TXCAL45DM_MASK            USBPHY_TX_TXCAL45DN_MASK
#define USBPHY_TX_TXCAL45DM_SHIFT           USBPHY_TX_TXCAL45DN_SHIFT
#define USBPHY_TX_TXCAL45DM(x)              USBPHY_TX_TXCAL45DN(x)


/*!
 * @}
 */ /* end of group USBPHY_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USDHC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
 * @{
 */

/** USDHC - Register Layout Typedef */
typedef struct {
  __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
  __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
  __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
  __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
  __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
  __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
  __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
  __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
  __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
  __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
  __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
  __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
  __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
  __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
  __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
  __IO uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
  __IO uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
  __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
  __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
       uint8_t RESERVED_0[4];
  __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
  __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status, offset: 0x54 */
  __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
       uint8_t RESERVED_1[4];
  __IO uint32_t DLL_CTRL;                          /**< DLL (Delay Line) Control, offset: 0x60 */
  __I  uint32_t DLL_STATUS;                        /**< DLL Status, offset: 0x64 */
  __IO uint32_t CLK_TUNE_CTRL_STATUS;              /**< CLK Tuning Control and Status, offset: 0x68 */
       uint8_t RESERVED_2[4];
  __IO uint32_t STROBE_DLL_CTRL;                   /**< Strobe DLL control, offset: 0x70 */
  __I  uint32_t STROBE_DLL_STATUS;                 /**< Strobe DLL status, offset: 0x74 */
       uint8_t RESERVED_3[72];
  __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
  __IO uint32_t MMC_BOOT;                          /**< eMMC Boot, offset: 0xC4 */
  __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
  __IO uint32_t TUNING_CTRL;                       /**< Tuning Control, offset: 0xCC */
       uint8_t RESERVED_4[48];
  __I  uint32_t CQVER;                             /**< Command Queuing Version, offset: 0x100 */
  __IO uint32_t CQCAP;                             /**< Command Queuing Capabilities, offset: 0x104 */
  __IO uint32_t CQCFG;                             /**< Command Queuing Configuration, offset: 0x108 */
  __IO uint32_t CQCTL;                             /**< Command Queuing Control, offset: 0x10C */
  __IO uint32_t CQIS;                              /**< Command Queuing Interrupt Status, offset: 0x110 */
  __IO uint32_t CQISTE;                            /**< Command Queuing Interrupt Status Enable, offset: 0x114 */
  __IO uint32_t CQISGE;                            /**< Command Queuing Interrupt Signal Enable, offset: 0x118 */
  __IO uint32_t CQIC;                              /**< Command Queuing Interrupt Coalescing, offset: 0x11C */
  __IO uint32_t CQTDLBA;                           /**< Command Queuing Task Descriptor List Base Address, offset: 0x120 */
  __IO uint32_t CQTDLBAU;                          /**< Command Queuing Task Descriptor List Base Address Upper 32 Bits, offset: 0x124 */
  __IO uint32_t CQTDBR;                            /**< Command Queuing Task Doorbell, offset: 0x128 */
  __IO uint32_t CQTCN;                             /**< Command Queuing Task Completion Notification, offset: 0x12C */
  __I  uint32_t CQDQS;                             /**< Command Queuing Device Queue Status, offset: 0x130 */
  __I  uint32_t CQDPT;                             /**< Command Queuing Device Pending Tasks, offset: 0x134 */
  __IO uint32_t CQTCLR;                            /**< Command Queuing Task Clear, offset: 0x138 */
       uint8_t RESERVED_5[4];
  __IO uint32_t CQSSC1;                            /**< Command Queuing Send Status Configuration 1, offset: 0x140 */
  __IO uint32_t CQSSC2;                            /**< Command Queuing Send Status Configuration 2, offset: 0x144 */
  __I  uint32_t CQCRDCT;                           /**< Command Queuing Command Response for Direct-Command Task, offset: 0x148 */
       uint8_t RESERVED_6[4];
  __IO uint32_t CQRMEM;                            /**< Command Queuing Response Mode Error Mask, offset: 0x150 */
  __I  uint32_t CQTERRI;                           /**< Command Queuing Task Error Information, offset: 0x154 */
  __I  uint32_t CQCRI;                             /**< Command Queuing Command Response Index, offset: 0x158 */
  __I  uint32_t CQCRA;                             /**< Command Queuing Command Response Argument, offset: 0x15C */
} USDHC_Type;

/* ----------------------------------------------------------------------------
   -- USDHC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USDHC_Register_Masks USDHC Register Masks
 * @{
 */

/*! @name DS_ADDR - DMA System Address */
/*! @{ */

#define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFFU)
#define USDHC_DS_ADDR_DS_ADDR_SHIFT              (0U)
/*! DS_ADDR - System address */
#define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
/*! @} */

/*! @name BLK_ATT - Block Attributes */
/*! @{ */

#define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
#define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
/*! BLKSIZE - Transfer block size
 *  0b1000000000000..4096 bytes
 *  0b0100000000000..2048 bytes
 *  0b0001000000000..512 bytes
 *  0b0000111111111..511 bytes
 *  0b0000000000100..4 bytes
 *  0b0000000000011..3 bytes
 *  0b0000000000010..2 bytes
 *  0b0000000000001..1 byte
 *  0b0000000000000..No data transfer
 */
#define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)

#define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
#define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
/*! BLKCNT - Blocks count for current transfer
 *  0b1111111111111111..65535 blocks
 *  0b0000000000000010..2 blocks
 *  0b0000000000000001..1 block
 *  0b0000000000000000..Stop count
 */
#define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
/*! @} */

/*! @name CMD_ARG - Command Argument */
/*! @{ */

#define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
#define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
/*! CMDARG - Command argument */
#define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
/*! @} */

/*! @name CMD_XFR_TYP - Command Transfer Type */
/*! @{ */

#define USDHC_CMD_XFR_TYP_DMAEN_MASK             (0x1U)
#define USDHC_CMD_XFR_TYP_DMAEN_SHIFT            (0U)
/*! DMAEN - DMAEN
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_DMAEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DMAEN_SHIFT)) & USDHC_CMD_XFR_TYP_DMAEN_MASK)

#define USDHC_CMD_XFR_TYP_BCEN_MASK              (0x2U)
#define USDHC_CMD_XFR_TYP_BCEN_SHIFT             (1U)
/*! BCEN - BCEN
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_BCEN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_BCEN_SHIFT)) & USDHC_CMD_XFR_TYP_BCEN_MASK)

#define USDHC_CMD_XFR_TYP_AC12EN_MASK            (0x4U)
#define USDHC_CMD_XFR_TYP_AC12EN_SHIFT           (2U)
/*! AC12EN - AC12EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_AC12EN(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC12EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC12EN_MASK)

#define USDHC_CMD_XFR_TYP_DDR_EN_MASK            (0x8U)
#define USDHC_CMD_XFR_TYP_DDR_EN_SHIFT           (3U)
/*! DDR_EN - DDR_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_DDR_EN(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DDR_EN_SHIFT)) & USDHC_CMD_XFR_TYP_DDR_EN_MASK)

#define USDHC_CMD_XFR_TYP_DTDSEL_MASK            (0x10U)
#define USDHC_CMD_XFR_TYP_DTDSEL_SHIFT           (4U)
/*! DTDSEL - DTDSEL
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_DTDSEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DTDSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DTDSEL_MASK)

#define USDHC_CMD_XFR_TYP_MSBSEL_MASK            (0x20U)
#define USDHC_CMD_XFR_TYP_MSBSEL_SHIFT           (5U)
/*! MSBSEL - MSBSEL
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_MSBSEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_MSBSEL_SHIFT)) & USDHC_CMD_XFR_TYP_MSBSEL_MASK)

#define USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK        (0x40U)
#define USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT       (6U)
/*! NIBBLE_POS - NIBBLE_POS
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_NIBBLE_POS(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT)) & USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK)

#define USDHC_CMD_XFR_TYP_AC23EN_MASK            (0x80U)
#define USDHC_CMD_XFR_TYP_AC23EN_SHIFT           (7U)
/*! AC23EN - AC23EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_CMD_XFR_TYP_AC23EN(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC23EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC23EN_MASK)

#define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
/*! RSPTYP - Response type select
 *  0b00..No response
 *  0b01..Response length 136
 *  0b10..Response length 48
 *  0b11..Response length 48, check busy after response
 */
#define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)

#define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
/*! CCCEN - Command CRC check enable
 *  0b1..Enables command CRC check
 *  0b0..Disables command CRC check
 */
#define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)

#define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
#define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
/*! CICEN - Command index check enable
 *  0b1..Enables command index check
 *  0b0..Disable command index check
 */
#define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)

#define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
/*! DPSEL - Data present select
 *  0b1..Data present
 *  0b0..No data present
 */
#define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)

#define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
/*! CMDTYP - Command type
 *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
 *  0b10..Resume CMD52 for writing function select in CCCR
 *  0b01..Suspend CMD52 for writing bus suspend in CCCR
 *  0b00..Normal other commands
 */
#define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)

#define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
/*! CMDINX - Command index */
#define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
/*! @} */

/*! @name CMD_RSP0 - Command Response0 */
/*! @{ */

#define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
/*! CMDRSP0 - Command response 0 */
#define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
/*! @} */

/*! @name CMD_RSP1 - Command Response1 */
/*! @{ */

#define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
/*! CMDRSP1 - Command response 1 */
#define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/*! @} */

/*! @name CMD_RSP2 - Command Response2 */
/*! @{ */

#define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
/*! CMDRSP2 - Command response 2 */
#define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/*! @} */

/*! @name CMD_RSP3 - Command Response3 */
/*! @{ */

#define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
/*! CMDRSP3 - Command response 3 */
#define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
/*! @} */

/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
/*! @{ */

#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
/*! DATCONT - Data content */
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
/*! @} */

/*! @name PRES_STATE - Present State */
/*! @{ */

#define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
#define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
/*! CIHB - Command inhibit (CMD)
 *  0b1..Cannot issue command
 *  0b0..Can issue command using only CMD line
 */
#define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)

#define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
#define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
/*! CDIHB - Command Inhibit Data (DATA)
 *  0b1..Cannot issue command that uses the DATA line
 *  0b0..Can issue command that uses the DATA line
 */
#define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)

#define USDHC_PRES_STATE_DLA_MASK                (0x4U)
#define USDHC_PRES_STATE_DLA_SHIFT               (2U)
/*! DLA - Data line active
 *  0b1..DATA line active
 *  0b0..DATA line inactive
 */
#define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)

#define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
#define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
/*! SDSTB - SD clock stable
 *  0b1..Clock is stable.
 *  0b0..Clock is changing frequency and not stable.
 */
#define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)

#define USDHC_PRES_STATE_WTA_MASK                (0x100U)
#define USDHC_PRES_STATE_WTA_SHIFT               (8U)
/*! WTA - Write transfer active
 *  0b1..Transferring data
 *  0b0..No valid data
 */
#define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)

#define USDHC_PRES_STATE_RTA_MASK                (0x200U)
#define USDHC_PRES_STATE_RTA_SHIFT               (9U)
/*! RTA - Read transfer active
 *  0b1..Transferring data
 *  0b0..No valid data
 */
#define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)

#define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
#define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
/*! BWEN - Buffer write enable
 *  0b1..Write enable
 *  0b0..Write disable
 */
#define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)

#define USDHC_PRES_STATE_BREN_MASK               (0x800U)
#define USDHC_PRES_STATE_BREN_SHIFT              (11U)
/*! BREN - Buffer read enable
 *  0b1..Read enable
 *  0b0..Read disable
 */
#define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)

#define USDHC_PRES_STATE_RTR_MASK                (0x1000U)
#define USDHC_PRES_STATE_RTR_SHIFT               (12U)
/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode,and eMMC HS200 mode)
 *  0b1..Sampling clock needs re-tuning
 *  0b0..Fixed or well tuned sampling clock
 */
#define USDHC_PRES_STATE_RTR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)

#define USDHC_PRES_STATE_TSCD_MASK               (0x8000U)
#define USDHC_PRES_STATE_TSCD_SHIFT              (15U)
/*! TSCD - Tap select change done
 *  0b1..Delay cell select change is finished.
 *  0b0..Delay cell select change is not finished.
 */
#define USDHC_PRES_STATE_TSCD(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)

#define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
#define USDHC_PRES_STATE_CINST_SHIFT             (16U)
/*! CINST - Card inserted
 *  0b1..Card inserted
 *  0b0..Power on reset or no card
 */
#define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)

#define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
#define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
/*! CDPL - Card detect pin level
 *  0b1..Card present (CD_B = 0)
 *  0b0..No card present (CD_B = 1)
 */
#define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)

#define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
#define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
/*! WPSPL - Write protect switch pin level
 *  0b1..Write enabled (WP = 0)
 *  0b0..Write protected (WP = 1)
 */
#define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)

#define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
#define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
/*! CLSL - CMD line signal level */
#define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)

#define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
#define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
/*! DLSL - DATA[7:0] line signal level
 *  0b00000111..Data 7 line signal level
 *  0b00000110..Data 6 line signal level
 *  0b00000101..Data 5 line signal level
 *  0b00000100..Data 4 line signal level
 *  0b00000011..Data 3 line signal level
 *  0b00000010..Data 2 line signal level
 *  0b00000001..Data 1 line signal level
 *  0b00000000..Data 0 line signal level
 */
#define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
/*! @} */

/*! @name PROT_CTRL - Protocol Control */
/*! @{ */

#define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
#define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
/*! DTW - Data transfer width
 *  0b10..8-bit mode
 *  0b01..4-bit mode
 *  0b00..1-bit mode
 *  0b11..Reserved
 */
#define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)

#define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
#define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
/*! D3CD - DATA3 as card detection pin
 *  0b1..DATA3 as card detection pin
 *  0b0..DATA3 does not monitor card insertion
 */
#define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)

#define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
#define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
/*! EMODE - Endian mode
 *  0b00..Big endian mode
 *  0b01..Half word big endian mode
 *  0b10..Little endian mode
 *  0b11..Reserved
 */
#define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)

#define USDHC_PROT_CTRL_CDTL_MASK                (0x40U)
#define USDHC_PROT_CTRL_CDTL_SHIFT               (6U)
/*! CDTL - Card detect test level
 *  0b1..Card detect test level is 1, card inserted
 *  0b0..Card detect test level is 0, no card inserted
 */
#define USDHC_PROT_CTRL_CDTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)

#define USDHC_PROT_CTRL_CDSS_MASK                (0x80U)
#define USDHC_PROT_CTRL_CDSS_SHIFT               (7U)
/*! CDSS - Card detect signal selection
 *  0b1..Card detection test level is selected (for test purpose).
 *  0b0..Card detection level is selected (for normal purpose).
 */
#define USDHC_PROT_CTRL_CDSS(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)

#define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
#define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
/*! DMASEL - DMA select
 *  0b00..No DMA or simple DMA is selected.
 *  0b01..ADMA1 is selected.
 *  0b10..ADMA2 is selected.
 *  0b11..Reserved
 */
#define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)

#define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
#define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
/*! SABGREQ - Stop at block gap request
 *  0b1..Stop
 *  0b0..Transfer
 */
#define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)

#define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
#define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
/*! CREQ - Continue request
 *  0b1..Restart
 *  0b0..No effect
 */
#define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)

#define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
#define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
/*! RWCTL - Read wait control
 *  0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
 *  0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
 */
#define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)

#define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
#define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
/*! IABG - Interrupt at block gap
 *  0b1..Enables interrupt at block gap
 *  0b0..Disables interrupt at block gap
 */
#define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)

#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
/*! RD_DONE_NO_8CLK - Read performed number 8 clock */
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)

#define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
#define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
/*! WECINT - Wakeup event enable on card interrupt
 *  0b1..Enables wakeup event enable on card interrupt
 *  0b0..Disables wakeup event enable on card interrupt
 */
#define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)

#define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
#define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
/*! WECINS - Wakeup event enable on SD card insertion
 *  0b1..Enable wakeup event enable on SD card insertion
 *  0b0..Disable wakeup event enable on SD card insertion
 */
#define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)

#define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
#define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
/*! WECRM - Wakeup event enable on SD card removal
 *  0b1..Enables wakeup event enable on SD card removal
 *  0b0..Disables wakeup event enable on SD card removal
 */
#define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)

#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
/*! NON_EXACT_BLK_RD - Non-exact block read
 *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
 *  0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
 */
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
/*! @} */

/*! @name SYS_CTRL - System Control */
/*! @{ */

#define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
#define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
/*! DVS - Divisor
 *  0b0000..Divide-by-1
 *  0b0001..Divide-by-2
 *  0b1110..Divide-by-15
 *  0b1111..Divide-by-16
 */
#define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)

#define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
#define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
/*! SDCLKFS - SDCLK frequency select */
#define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)

#define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
#define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
/*! DTOCV - Data timeout counter value
 *  0b1111..SDCLK x 2 31 recommend to use for HS400 mode
 *  0b1110..SDCLK x 2 30 recommend to use for HS200/SDR104 mode
 *  0b1101..SDCLK x 2 29 recommend to use for other speed mode except HS400/HS200/SDR104 mode
 *  0b0011..SDCLK x 2 19
 *  0b0010..SDCLK x 2 18
 *  0b0001..SDCLK x 2 33
 *  0b0000..SDCLK x 2 32
 */
#define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)

#define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
/*! IPP_RST_N - Hardware reset */
#define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)

#define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
#define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
/*! RSTA - Software reset for all
 *  0b1..Reset
 *  0b0..No reset
 */
#define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)

#define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
#define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
/*! RSTC - Software reset for CMD line
 *  0b1..Reset
 *  0b0..No reset
 */
#define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)

#define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
#define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
/*! RSTD - Software reset for data line
 *  0b1..Reset
 *  0b0..No reset
 */
#define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)

#define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
#define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
/*! INITA - Initialization active */
#define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)

#define USDHC_SYS_CTRL_RSTT_MASK                 (0x10000000U)
#define USDHC_SYS_CTRL_RSTT_SHIFT                (28U)
/*! RSTT - Reset tuning */
#define USDHC_SYS_CTRL_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
/*! @} */

/*! @name INT_STATUS - Interrupt Status */
/*! @{ */

#define USDHC_INT_STATUS_CC_MASK                 (0x1U)
#define USDHC_INT_STATUS_CC_SHIFT                (0U)
/*! CC - Command complete
 *  0b1..Command complete
 *  0b0..Command not complete
 */
#define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)

#define USDHC_INT_STATUS_TC_MASK                 (0x2U)
#define USDHC_INT_STATUS_TC_SHIFT                (1U)
/*! TC - Transfer complete
 *  0b1..Transfer complete
 *  0b0..Transfer does not complete
 */
#define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)

#define USDHC_INT_STATUS_BGE_MASK                (0x4U)
#define USDHC_INT_STATUS_BGE_SHIFT               (2U)
/*! BGE - Block gap event
 *  0b1..Transaction stopped at block gap
 *  0b0..No block gap event
 */
#define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)

#define USDHC_INT_STATUS_DINT_MASK               (0x8U)
#define USDHC_INT_STATUS_DINT_SHIFT              (3U)
/*! DINT - DMA interrupt
 *  0b1..DMA interrupt is generated.
 *  0b0..No DMA interrupt
 */
#define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)

#define USDHC_INT_STATUS_BWR_MASK                (0x10U)
#define USDHC_INT_STATUS_BWR_SHIFT               (4U)
/*! BWR - Buffer write ready
 *  0b1..Ready to write buffer
 *  0b0..Not ready to write buffer
 */
#define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)

#define USDHC_INT_STATUS_BRR_MASK                (0x20U)
#define USDHC_INT_STATUS_BRR_SHIFT               (5U)
/*! BRR - Buffer read ready
 *  0b1..Ready to read buffer
 *  0b0..Not ready to read buffer
 */
#define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)

#define USDHC_INT_STATUS_CINS_MASK               (0x40U)
#define USDHC_INT_STATUS_CINS_SHIFT              (6U)
/*! CINS - Card insertion
 *  0b1..Card inserted
 *  0b0..Card state unstable or removed
 */
#define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)

#define USDHC_INT_STATUS_CRM_MASK                (0x80U)
#define USDHC_INT_STATUS_CRM_SHIFT               (7U)
/*! CRM - Card removal
 *  0b1..Card removed
 *  0b0..Card state unstable or inserted
 */
#define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)

#define USDHC_INT_STATUS_CINT_MASK               (0x100U)
#define USDHC_INT_STATUS_CINT_SHIFT              (8U)
/*! CINT - Card interrupt
 *  0b1..Generate card interrupt
 *  0b0..No card interrupt
 */
#define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)

#define USDHC_INT_STATUS_RTE_MASK                (0x1000U)
#define USDHC_INT_STATUS_RTE_SHIFT               (12U)
/*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and eMMC HS200 mode)
 *  0b1..Re-tuning should be performed.
 *  0b0..Re-tuning is not required.
 */
#define USDHC_INT_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)

#define USDHC_INT_STATUS_TP_MASK                 (0x2000U)
#define USDHC_INT_STATUS_TP_SHIFT                (13U)
/*! TP - Tuning pass:(only for SD3.0 SDR104 mode and eMMC HS200 mode) */
#define USDHC_INT_STATUS_TP(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)

#define USDHC_INT_STATUS_CQI_MASK                (0x4000U)
#define USDHC_INT_STATUS_CQI_SHIFT               (14U)
/*! CQI - Command queuing interrupt */
#define USDHC_INT_STATUS_CQI(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CQI_SHIFT)) & USDHC_INT_STATUS_CQI_MASK)

#define USDHC_INT_STATUS_ERR_INT_STATUS_MASK     (0x8000U)
#define USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT    (15U)
/*! ERR_INT_STATUS - Error Interrupt Status */
#define USDHC_INT_STATUS_ERR_INT_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT)) & USDHC_INT_STATUS_ERR_INT_STATUS_MASK)

#define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
#define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
/*! CTOE - Command timeout error
 *  0b1..Time out
 *  0b0..No error
 */
#define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)

#define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
#define USDHC_INT_STATUS_CCE_SHIFT               (17U)
/*! CCE - Command CRC error
 *  0b1..CRC error generated
 *  0b0..No error
 */
#define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)

#define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
#define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
/*! CEBE - Command end bit error
 *  0b1..End bit error generated
 *  0b0..No error
 */
#define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)

#define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
#define USDHC_INT_STATUS_CIE_SHIFT               (19U)
/*! CIE - Command index error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)

#define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
#define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
/*! DTOE - Data timeout error
 *  0b1..Time out
 *  0b0..No error
 */
#define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)

#define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
#define USDHC_INT_STATUS_DCE_SHIFT               (21U)
/*! DCE - Data CRC error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)

#define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
#define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
/*! DEBE - Data end bit error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)

#define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
#define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
/*! AC12E - Auto CMD12 error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)

#define USDHC_INT_STATUS_TNE_MASK                (0x4000000U)
#define USDHC_INT_STATUS_TNE_SHIFT               (26U)
/*! TNE - Tuning error: (only for SD3.0 SDR104 mode and eMMC HS200 mode) */
#define USDHC_INT_STATUS_TNE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)

#define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
#define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
/*! DMAE - DMA error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
/*! @} */

/*! @name INT_STATUS_EN - Interrupt Status Enable */
/*! @{ */

#define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
#define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
/*! CCSEN - Command complete status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)

#define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
#define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
/*! TCSEN - Transfer complete status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)

#define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
#define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
/*! BGESEN - Block gap event status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)

#define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
/*! DINTSEN - DMA interrupt status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)

#define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
/*! BWRSEN - Buffer write ready status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)

#define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
/*! BRRSEN - Buffer read ready status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)

#define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
/*! CINSSEN - Card insertion status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)

#define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
/*! CRMSEN - Card removal status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)

#define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
/*! CINTSEN - Card interrupt status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)

#define USDHC_INT_STATUS_EN_RTESEN_MASK          (0x1000U)
#define USDHC_INT_STATUS_EN_RTESEN_SHIFT         (12U)
/*! RTESEN - Re-tuning event status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_RTESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)

#define USDHC_INT_STATUS_EN_TPSEN_MASK           (0x2000U)
#define USDHC_INT_STATUS_EN_TPSEN_SHIFT          (13U)
/*! TPSEN - Tuning pass status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_TPSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)

#define USDHC_INT_STATUS_EN_CQISEN_MASK          (0x4000U)
#define USDHC_INT_STATUS_EN_CQISEN_SHIFT         (14U)
/*! CQISEN - Command queuing status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CQISEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & USDHC_INT_STATUS_EN_CQISEN_MASK)

#define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
/*! CTOESEN - Command timeout error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)

#define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
#define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
/*! CCESEN - Command CRC error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)

#define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
/*! CEBESEN - Command end bit error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)

#define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
#define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
/*! CIESEN - Command index error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)

#define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
/*! DTOESEN - Data timeout error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)

#define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
#define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
/*! DCESEN - Data CRC error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)

#define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
/*! DEBESEN - Data end bit error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)

#define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
/*! AC12ESEN - Auto CMD12 error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)

#define USDHC_INT_STATUS_EN_TNESEN_MASK          (0x4000000U)
#define USDHC_INT_STATUS_EN_TNESEN_SHIFT         (26U)
/*! TNESEN - Tuning error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_TNESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)

#define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
/*! DMAESEN - DMA error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
/*! @} */

/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
/*! @{ */

#define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
/*! CCIEN - Command complete interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)

#define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
/*! TCIEN - Transfer complete interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)

#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
/*! BGEIEN - Block gap event interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
/*! DINTIEN - DMA interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)

#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
/*! BWRIEN - Buffer write ready interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)

#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
/*! BRRIEN - Buffer read ready interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
/*! CINSIEN - Card insertion interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
/*! CRMIEN - Card removal interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
/*! CINTIEN - Card interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)

#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK          (0x1000U)
#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         (12U)
/*! RTEIEN - Re-tuning event interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_RTEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_TPIEN_MASK           (0x2000U)
#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT          (13U)
/*! TPIEN - Tuning pass interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_TPIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CQIIEN_MASK          (0x4000U)
#define USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT         (14U)
/*! CQIIEN - Command queuing signal enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CQIIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CQIIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
/*! CTOEIEN - Command timeout error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
/*! CCEIEN - Command CRC error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
/*! CEBEIEN - Command end bit error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
/*! CIEIEN - Command index error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
/*! DTOEIEN - Data timeout error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
/*! DCEIEN - Data CRC error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
/*! DEBEIEN - Data end bit error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
/*! AC12EIEN - Auto CMD12 error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)

#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK          (0x4000000U)
#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         (26U)
/*! TNEIEN - Tuning error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_TNEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)

#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
/*! DMAEIEN - DMA error interrupt enable
 *  0b1..Enable
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
/*! @} */

/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
/*! @{ */

#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
/*! AC12NE - Auto CMD12 not executed
 *  0b1..Not executed
 *  0b0..Executed
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
/*! AC12TOE - Auto CMD12 / 23 timeout error
 *  0b1..Time out
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x4U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (2U)
/*! AC12CE - Auto CMD12 / 23 CRC error
 *  0b1..CRC error met in Auto CMD12/23 response
 *  0b0..No CRC error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x8U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (3U)
/*! AC12EBE - Auto CMD12 / 23 end bit error
 *  0b1..End bit error generated
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
/*! AC12IE - Auto CMD12 / 23 index error
 *  0b1..Error, the CMD index in response is not CMD12/23
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
/*! CNIBAC12E - Command not issued by Auto CMD12 error
 *  0b1..Not issued
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
/*! EXECUTE_TUNING - Execute tuning
 *  0b1..Start tuning procedure
 *  0b0..Tuning procedure is aborted
 */
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)

#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
/*! SMP_CLK_SEL - Sample clock select
 *  0b1..Tuned clock is used to sample data
 *  0b0..Fixed clock is used to sample data
 */
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
/*! @} */

/*! @name HOST_CTRL_CAP - Host Controller Capabilities */
/*! @{ */

#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   (0x1U)
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT  (0U)
/*! SDR50_SUPPORT - SDR50 support */
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)

#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK  (0x2U)
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
/*! SDR104_SUPPORT - SDR104 support */
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)

#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  (2U)
/*! DDR50_SUPPORT - DDR50 support */
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)

#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
/*! USE_TUNING_SDR50 - Use Tuning for SDR50
 *  0b1..SDR50 supports tuning
 *  0b0..SDR50 does not support tuning
 */
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)

#define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
#define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
/*! MBL - Max block length
 *  0b000..512 bytes
 *  0b001..1024 bytes
 *  0b010..2048 bytes
 *  0b011..4096 bytes
 */
#define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)

#define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
/*! ADMAS - ADMA support
 *  0b1..Advanced DMA supported
 *  0b0..Advanced DMA not supported
 */
#define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)

#define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
#define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
/*! HSS - High speed support
 *  0b1..High speed supported
 *  0b0..High speed not supported
 */
#define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)

#define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
/*! DMAS - DMA support
 *  0b1..DMA supported
 *  0b0..DMA not supported
 */
#define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)

#define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
#define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
/*! SRS - Suspend / resume support
 *  0b1..Supported
 *  0b0..Not supported
 */
#define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)

#define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
#define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
/*! VS33 - Voltage support 3.3 V
 *  0b1..3.3 V supported
 *  0b0..3.3 V not supported
 */
#define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)

#define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
#define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
/*! VS30 - Voltage support 3.0 V
 *  0b1..3.0 V supported
 *  0b0..3.0 V not supported
 */
#define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)

#define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
#define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
/*! VS18 - Voltage support 1.8 V
 *  0b1..1.8 V supported
 *  0b0..1.8 V not supported
 */
#define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
/*! @} */

/*! @name WTMK_LVL - Watermark Level */
/*! @{ */

#define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
#define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
/*! RD_WML - Read watermark level */
#define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)

#define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
#define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
/*! WR_WML - Write watermark level */
#define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
/*! @} */

/*! @name MIX_CTRL - Mixer Control */
/*! @{ */

#define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
#define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
/*! DMAEN - DMA enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)

#define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
#define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
/*! BCEN - Block count enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)

#define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
#define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
/*! AC12EN - Auto CMD12 enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)

#define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
#define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
/*! DDR_EN - Dual data rate mode selection */
#define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)

#define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
#define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
/*! DTDSEL - Data transfer direction select
 *  0b1..Read (Card to host)
 *  0b0..Write (Host to card)
 */
#define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)

#define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
#define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
/*! MSBSEL - Multi / Single block select
 *  0b1..Multiple blocks
 *  0b0..Single block
 */
#define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)

#define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
/*! NIBBLE_POS - Nibble position indication */
#define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)

#define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
#define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
/*! AC23EN - Auto CMD23 enable */
#define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)

#define USDHC_MIX_CTRL_EXE_TUNE_MASK             (0x400000U)
#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT            (22U)
/*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and eMMC HS200 mode)
 *  0b1..Execute tuning
 *  0b0..Not tuned or tuning completed
 */
#define USDHC_MIX_CTRL_EXE_TUNE(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)

#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK          (0x800000U)
#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         (23U)
/*! SMP_CLK_SEL - Clock selection
 *  0b1..Tuned clock is used to sample data / cmd
 *  0b0..Fixed clock is used to sample data / cmd
 */
#define USDHC_MIX_CTRL_SMP_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)

#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         (0x1000000U)
#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        (24U)
/*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and eMMC HS200 mode)
 *  0b1..Enable auto tuning
 *  0b0..Disable auto tuning
 */
#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)

#define USDHC_MIX_CTRL_FBCLK_SEL_MASK            (0x2000000U)
#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT           (25U)
/*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and eMMC HS200 mode)
 *  0b1..Feedback clock comes from the ipp_card_clk_out
 *  0b0..Feedback clock comes from the loopback CLK
 */
#define USDHC_MIX_CTRL_FBCLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)

#define USDHC_MIX_CTRL_HS400_MODE_MASK           (0x4000000U)
#define USDHC_MIX_CTRL_HS400_MODE_SHIFT          (26U)
/*! HS400_MODE - Enable HS400 mode */
#define USDHC_MIX_CTRL_HS400_MODE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)

#define USDHC_MIX_CTRL_EN_HS400_MODE_MASK        (0x8000000U)
#define USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT       (27U)
/*! EN_HS400_MODE - Enable enhance HS400 mode */
#define USDHC_MIX_CTRL_EN_HS400_MODE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_EN_HS400_MODE_MASK)
/*! @} */

/*! @name FORCE_EVENT - Force Event */
/*! @{ */

#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
/*! FEVTAC12NE - Force event auto command 12 not executed */
#define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)

#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
/*! FEVTAC12TOE - Force event auto command 12 time out error */
#define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)

#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
/*! FEVTAC12CE - Force event auto command 12 CRC error */
#define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)

#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
/*! FEVTAC12EBE - Force event Auto Command 12 end bit error */
#define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)

#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
/*! FEVTAC12IE - Force event Auto Command 12 index error */
#define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)

#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
/*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error */
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)

#define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
/*! FEVTCTOE - Force event command time out error */
#define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)

#define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
/*! FEVTCCE - Force event command CRC error */
#define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)

#define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
/*! FEVTCEBE - Force event command end bit error */
#define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)

#define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
/*! FEVTCIE - Force event command index error */
#define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)

#define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
/*! FEVTDTOE - Force event data time out error */
#define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)

#define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
/*! FEVTDCE - Force event data CRC error */
#define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)

#define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
/*! FEVTDEBE - Force event data end bit error */
#define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)

#define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
/*! FEVTAC12E - Force event Auto Command 12 error */
#define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)

#define USDHC_FORCE_EVENT_FEVTTNE_MASK           (0x4000000U)
#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT          (26U)
/*! FEVTTNE - Force tuning error */
#define USDHC_FORCE_EVENT_FEVTTNE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)

#define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
/*! FEVTDMAE - Force event DMA error */
#define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)

#define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
/*! FEVTCINT - Force event card interrupt */
#define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
/*! @} */

/*! @name ADMA_ERR_STATUS - ADMA Error Status */
/*! @{ */

#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
/*! ADMAES - ADMA error state (when ADMA error is occurred) */
#define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)

#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
/*! ADMALME - ADMA length mismatch error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)

#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
/*! ADMADCE - ADMA descriptor error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
/*! @} */

/*! @name ADMA_SYS_ADDR - ADMA System Address */
/*! @{ */

#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
/*! ADS_ADDR - ADMA system address */
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
/*! @} */

/*! @name DLL_CTRL - DLL (Delay Line) Control */
/*! @{ */

#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK      (0x1U)
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT     (0U)
/*! DLL_CTRL_ENABLE - DLL and delay chain */
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK       (0x2U)
#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT      (1U)
/*! DLL_CTRL_RESET - DLL reset */
#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
/*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
/*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0 */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
/*! DLL_CTRL_GATE_UPDATE - DLL gate update */
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
/*! DLL_CTRL_SLV_OVERRIDE - DLL slave override */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
/*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
/*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1 */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
/*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)

#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
/*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval */
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */

/*! @name DLL_STATUS - DLL Status */
/*! @{ */

#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   (0x1U)
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT  (0U)
/*! DLL_STS_SLV_LOCK - Slave delay-line lock status */
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)

#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   (0x2U)
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT  (1U)
/*! DLL_STS_REF_LOCK - Reference DLL lock status */
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)

#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK    (0x1FCU)
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   (2U)
/*! DLL_STS_SLV_SEL - Slave delay line select status */
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)

#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK    (0xFE00U)
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   (9U)
/*! DLL_STS_REF_SEL - Reference delay line select taps */
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
/*! @} */

/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
/*! @{ */

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
/*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST */
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
/*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT */
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
/*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE */
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK  (0x8000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
/*! NXT_ERR - NXT error */
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
/*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST */
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
/*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT */
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
/*! TAP_SEL_PRE - TAP_SEL_PRE */
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)

#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK  (0x80000000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
/*! PRE_ERR - PRE error */
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
/*! @} */

/*! @name STROBE_DLL_CTRL - Strobe DLL control */
/*! @{ */

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
/*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
/*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
/*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
/*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
/*! STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
/*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
/*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
/*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
/*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */

/*! @name STROBE_DLL_STATUS - Strobe DLL status */
/*! @{ */

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
/*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
/*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
/*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
/*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
/*! @} */

/*! @name VEND_SPEC - Vendor Specific Register */
/*! @{ */

#define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
#define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
/*! VSELECT - Voltage selection
 *  0b1..Change the voltage to low voltage range, around 1.8 V
 *  0b0..Change the voltage to high voltage range, around 3.0 V
 */
#define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)

#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     (0x4U)
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    (2U)
/*! CONFLICT_CHK_EN - Conflict check enable
 *  0b0..Conflict check disable
 *  0b1..Conflict check enable
 */
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)

#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
/*! AC12_WR_CHKBUSY_EN - Check busy enable
 *  0b0..Do not check busy after auto CMD12 for write data packet
 *  0b1..Check busy after auto CMD12 for write data packet
 */
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)

#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
/*! FRC_SDCLK_ON - Force CLK
 *  0b0..CLK active or inactive is fully controlled by the hardware.
 *  0b1..Force CLK active
 */
#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)

#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
/*! CRC_CHK_DIS - CRC Check Disable
 *  0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
 *  0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
 */
#define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)

#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
/*! CMD_BYTE_EN - Register byte access for CMD_XFR_TYP
 *  0b0..Disable. MIX_CTRL[7:0] is read/write and CMD_XFR_TYP[7:0] is read-only.
 *  0b1..Enable. MIX_CTRL[7:0] is read-only and CMD_XFR_TYP[7:0] is read/write.
 */
#define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
/*! @} */

/*! @name MMC_BOOT - eMMC Boot */
/*! @{ */

#define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
/*! DTOCV_ACK - DTOCV_ACK
 *  0b0000..SDCLK x 2^32
 *  0b0001..SDCLK x 2^33
 *  0b0010..SDCLK x 2^18
 *  0b0011..SDCLK x 2^19
 *  0b0100..SDCLK x 2^20
 *  0b0101..SDCLK x 2^21
 *  0b0110..SDCLK x 2^22
 *  0b0111..SDCLK x 2^23
 *  0b1110..SDCLK x 2^30
 *  0b1111..SDCLK x 2^31
 */
#define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)

#define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
/*! BOOT_ACK - BOOT ACK
 *  0b0..No ack
 *  0b1..Ack
 */
#define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)

#define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
/*! BOOT_MODE - Boot mode
 *  0b0..Normal boot
 *  0b1..Alternative boot
 */
#define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)

#define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
#define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
/*! BOOT_EN - Boot enable
 *  0b0..Fast boot disable
 *  0b1..Fast boot enable
 */
#define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)

#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
/*! AUTO_SABG_EN - Auto stop at block gap */
#define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)

#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
/*! DISABLE_TIME_OUT - Time out
 *  0b0..Enable time out
 *  0b1..Disable time out
 */
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)

#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
/*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode */
#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
/*! @} */

/*! @name VEND_SPEC2 - Vendor Specific 2 Register */
/*! @{ */

#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
/*! CARD_INT_D3_TEST - Card interrupt detection test
 *  0b0..Check the card interrupt only when DATA3 is high.
 *  0b1..Check the card interrupt by ignoring the status of DATA3.
 */
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)

#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK     (0x10U)
#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT    (4U)
/*! TUNING_8bit_EN - Tuning 8bit enable */
#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)

#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK     (0x20U)
#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT    (5U)
/*! TUNING_1bit_EN - Tuning 1bit enable */
#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)

#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      (0x40U)
#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     (6U)
/*! TUNING_CMD_EN - Tuning command enable
 *  0b0..Auto tuning circuit does not check the CMD line.
 *  0b1..Auto tuning circuit checks the CMD line.
 */
#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)

#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
/*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable */
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)

#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
/*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable */
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)

#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
 *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
 *  0b0..Disable
 */
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)

#define USDHC_VEND_SPEC2_EN_32K_CLK_MASK         (0x8000U)
#define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT        (15U)
/*! EN_32K_CLK - Enable 32khz clock for card detection */
#define USDHC_VEND_SPEC2_EN_32K_CLK(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK)

#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK      (0xFFFF0000U)
#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT     (16U)
/*! FBCLK_TAP_SEL - Enable extra delay on internal feedback clock */
#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT)) & USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK)
/*! @} */

/*! @name TUNING_CTRL - Tuning Control */
/*! @{ */

#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK  (0x7FU)
#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
/*! TUNING_START_TAP - Tuning start */
#define USDHC_TUNING_CTRL_TUNING_START_TAP(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)

#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U)
#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U)
/*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning */
#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)

#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK    (0xFF00U)
#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   (8U)
/*! TUNING_COUNTER - Tuning counter */
#define USDHC_TUNING_CTRL_TUNING_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)

#define USDHC_TUNING_CTRL_TUNING_STEP_MASK       (0x70000U)
#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT      (16U)
/*! TUNING_STEP - TUNING_STEP */
#define USDHC_TUNING_CTRL_TUNING_STEP(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)

#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK     (0x700000U)
#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT    (20U)
/*! TUNING_WINDOW - Data window */
#define USDHC_TUNING_CTRL_TUNING_WINDOW(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)

#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK     (0x1000000U)
#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT    (24U)
/*! STD_TUNING_EN - Standard tuning circuit and procedure enable */
#define USDHC_TUNING_CTRL_STD_TUNING_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
/*! @} */

/*! @name CQVER - Command Queuing Version */
/*! @{ */

#define USDHC_CQVER_VERSION_SUFFIX_MASK          (0xFU)
#define USDHC_CQVER_VERSION_SUFFIX_SHIFT         (0U)
/*! VERSION_SUFFIX - eMMC version suffix */
#define USDHC_CQVER_VERSION_SUFFIX(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_VERSION_SUFFIX_SHIFT)) & USDHC_CQVER_VERSION_SUFFIX_MASK)

#define USDHC_CQVER_MINOR_VN_MASK                (0xF0U)
#define USDHC_CQVER_MINOR_VN_SHIFT               (4U)
/*! MINOR_VN - eMMC minor version number */
#define USDHC_CQVER_MINOR_VN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MINOR_VN_SHIFT)) & USDHC_CQVER_MINOR_VN_MASK)

#define USDHC_CQVER_MAJOR_VN_MASK                (0xF00U)
#define USDHC_CQVER_MAJOR_VN_SHIFT               (8U)
/*! MAJOR_VN - eMMC major version number */
#define USDHC_CQVER_MAJOR_VN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MAJOR_VN_SHIFT)) & USDHC_CQVER_MAJOR_VN_MASK)
/*! @} */

/*! @name CQCAP - Command Queuing Capabilities */
/*! @{ */

#define USDHC_CQCAP_ITCFVAL_MASK                 (0x3FFU)
#define USDHC_CQCAP_ITCFVAL_SHIFT                (0U)
/*! ITCFVAL - Internal timer clock frequency value */
#define USDHC_CQCAP_ITCFVAL(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFVAL_SHIFT)) & USDHC_CQCAP_ITCFVAL_MASK)

#define USDHC_CQCAP_ITCFMUL_MASK                 (0xF000U)
#define USDHC_CQCAP_ITCFMUL_SHIFT                (12U)
/*! ITCFMUL - Internal timer clock frequency multiplier
 *  0b0001..0.001 MHz
 *  0b0010..0.01 MHz
 *  0b0011..0.1 MHz
 *  0b0100..1 MHz
 *  0b0101..10 MHz
 *  0b0110-0b1001..Reserved
 */
#define USDHC_CQCAP_ITCFMUL(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFMUL_SHIFT)) & USDHC_CQCAP_ITCFMUL_MASK)
/*! @} */

/*! @name CQCFG - Command Queuing Configuration */
/*! @{ */

#define USDHC_CQCFG_CQUE_MASK                    (0x1U)
#define USDHC_CQCFG_CQUE_SHIFT                   (0U)
/*! CQUE - Command queuing enable */
#define USDHC_CQCFG_CQUE(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_CQUE_SHIFT)) & USDHC_CQCFG_CQUE_MASK)

#define USDHC_CQCFG_TDS_MASK                     (0x100U)
#define USDHC_CQCFG_TDS_SHIFT                    (8U)
/*! TDS - Task descriptor size
 *  0b0..Task descriptor size is 64 bits
 *  0b1..Task descriptor size is 128 bits
 */
#define USDHC_CQCFG_TDS(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_TDS_SHIFT)) & USDHC_CQCFG_TDS_MASK)

#define USDHC_CQCFG_DCMDE_MASK                   (0x1000U)
#define USDHC_CQCFG_DCMDE_SHIFT                  (12U)
/*! DCMDE - Direct command (DCMD) enable
 *  0b0..Task descriptor in slot #31 is a Data Transfer Task Descriptor
 *  0b1..Task descriptor in slot #31 is a DCMD Task Descriptor
 */
#define USDHC_CQCFG_DCMDE(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_DCMDE_SHIFT)) & USDHC_CQCFG_DCMDE_MASK)
/*! @} */

/*! @name CQCTL - Command Queuing Control */
/*! @{ */

#define USDHC_CQCTL_HALT_MASK                    (0x1U)
#define USDHC_CQCTL_HALT_SHIFT                   (0U)
/*! HALT - Halt */
#define USDHC_CQCTL_HALT(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_HALT_SHIFT)) & USDHC_CQCTL_HALT_MASK)

#define USDHC_CQCTL_CLEAR_MASK                   (0x100U)
#define USDHC_CQCTL_CLEAR_SHIFT                  (8U)
/*! CLEAR - Clear all tasks */
#define USDHC_CQCTL_CLEAR(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_CLEAR_SHIFT)) & USDHC_CQCTL_CLEAR_MASK)
/*! @} */

/*! @name CQIS - Command Queuing Interrupt Status */
/*! @{ */

#define USDHC_CQIS_HAC_MASK                      (0x1U)
#define USDHC_CQIS_HAC_SHIFT                     (0U)
/*! HAC - Halt complete interrupt */
#define USDHC_CQIS_HAC(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_HAC_SHIFT)) & USDHC_CQIS_HAC_MASK)

#define USDHC_CQIS_TCC_MASK                      (0x2U)
#define USDHC_CQIS_TCC_SHIFT                     (1U)
/*! TCC - Task complete interrupt */
#define USDHC_CQIS_TCC(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCC_SHIFT)) & USDHC_CQIS_TCC_MASK)

#define USDHC_CQIS_RED_MASK                      (0x4U)
#define USDHC_CQIS_RED_SHIFT                     (2U)
/*! RED - Response error detected interrupt */
#define USDHC_CQIS_RED(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_RED_SHIFT)) & USDHC_CQIS_RED_MASK)

#define USDHC_CQIS_TCL_MASK                      (0x8U)
#define USDHC_CQIS_TCL_SHIFT                     (3U)
/*! TCL - Task cleared */
#define USDHC_CQIS_TCL(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCL_SHIFT)) & USDHC_CQIS_TCL_MASK)
/*! @} */

/*! @name CQISTE - Command Queuing Interrupt Status Enable */
/*! @{ */

#define USDHC_CQISTE_HAC_STE_MASK                (0x1U)
#define USDHC_CQISTE_HAC_STE_SHIFT               (0U)
/*! HAC_STE - Halt complete status enable
 *  0b0..CQIS[HAC] is disabled
 *  0b1..CQIS[HAC] is set when its interrupt condition is active
 */
#define USDHC_CQISTE_HAC_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_HAC_STE_SHIFT)) & USDHC_CQISTE_HAC_STE_MASK)

#define USDHC_CQISTE_TCC_STE_MASK                (0x2U)
#define USDHC_CQISTE_TCC_STE_SHIFT               (1U)
/*! TCC_STE - Task complete status enable
 *  0b0..CQIS[TCC] is disabled
 *  0b1..CQIS[TCC] is set when its interrupt condition is active
 */
#define USDHC_CQISTE_TCC_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCC_STE_SHIFT)) & USDHC_CQISTE_TCC_STE_MASK)

#define USDHC_CQISTE_RED_STE_MASK                (0x4U)
#define USDHC_CQISTE_RED_STE_SHIFT               (2U)
/*! RED_STE - Response error detected status enable
 *  0b0..CQIS[RED]is disabled
 *  0b1..CQIS[RED] is set when its interrupt condition is active
 */
#define USDHC_CQISTE_RED_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_RED_STE_SHIFT)) & USDHC_CQISTE_RED_STE_MASK)

#define USDHC_CQISTE_TCL_STE_MASK                (0x8U)
#define USDHC_CQISTE_TCL_STE_SHIFT               (3U)
/*! TCL_STE - Task cleared status enable
 *  0b0..CQIS[TCL] is disabled
 *  0b1..CQIS[TCL] is set when its interrupt condition is active
 */
#define USDHC_CQISTE_TCL_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCL_STE_SHIFT)) & USDHC_CQISTE_TCL_STE_MASK)
/*! @} */

/*! @name CQISGE - Command Queuing Interrupt Signal Enable */
/*! @{ */

#define USDHC_CQISGE_HAC_SGE_MASK                (0x1U)
#define USDHC_CQISGE_HAC_SGE_SHIFT               (0U)
/*! HAC_SGE - Halt complete signal enable */
#define USDHC_CQISGE_HAC_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_HAC_SGE_SHIFT)) & USDHC_CQISGE_HAC_SGE_MASK)

#define USDHC_CQISGE_TCC_SGE_MASK                (0x2U)
#define USDHC_CQISGE_TCC_SGE_SHIFT               (1U)
/*! TCC_SGE - Task complete signal enable */
#define USDHC_CQISGE_TCC_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCC_SGE_SHIFT)) & USDHC_CQISGE_TCC_SGE_MASK)

#define USDHC_CQISGE_RED_SGE_MASK                (0x4U)
#define USDHC_CQISGE_RED_SGE_SHIFT               (2U)
/*! RED_SGE - Response error detected signal enable */
#define USDHC_CQISGE_RED_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_RED_SGE_SHIFT)) & USDHC_CQISGE_RED_SGE_MASK)

#define USDHC_CQISGE_TCL_SGE_MASK                (0x8U)
#define USDHC_CQISGE_TCL_SGE_SHIFT               (3U)
/*! TCL_SGE - Task cleared signal enable */
#define USDHC_CQISGE_TCL_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCL_SGE_SHIFT)) & USDHC_CQISGE_TCL_SGE_MASK)
/*! @} */

/*! @name CQIC - Command Queuing Interrupt Coalescing */
/*! @{ */

#define USDHC_CQIC_ICTOVAL_MASK                  (0x7FU)
#define USDHC_CQIC_ICTOVAL_SHIFT                 (0U)
/*! ICTOVAL - Interrupt coalescing timeout value */
#define USDHC_CQIC_ICTOVAL(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVAL_SHIFT)) & USDHC_CQIC_ICTOVAL_MASK)

#define USDHC_CQIC_ICTOVALWEN_MASK               (0x80U)
#define USDHC_CQIC_ICTOVALWEN_SHIFT              (7U)
/*! ICTOVALWEN - Interrupt coalescing timeout value write enable */
#define USDHC_CQIC_ICTOVALWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVALWEN_SHIFT)) & USDHC_CQIC_ICTOVALWEN_MASK)

#define USDHC_CQIC_ICCTH_MASK                    (0x1F00U)
#define USDHC_CQIC_ICCTH_SHIFT                   (8U)
/*! ICCTH - Interrupt coalescing counter threshold */
#define USDHC_CQIC_ICCTH(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTH_SHIFT)) & USDHC_CQIC_ICCTH_MASK)

#define USDHC_CQIC_ICCTHWEN_MASK                 (0x8000U)
#define USDHC_CQIC_ICCTHWEN_SHIFT                (15U)
/*! ICCTHWEN - Interrupt coalescing counter threshold write enable */
#define USDHC_CQIC_ICCTHWEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTHWEN_SHIFT)) & USDHC_CQIC_ICCTHWEN_MASK)

#define USDHC_CQIC_ICCTR_MASK                    (0x10000U)
#define USDHC_CQIC_ICCTR_SHIFT                   (16U)
/*! ICCTR - Counter and timer reset */
#define USDHC_CQIC_ICCTR(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTR_SHIFT)) & USDHC_CQIC_ICCTR_MASK)

#define USDHC_CQIC_ICSB_MASK                     (0x100000U)
#define USDHC_CQIC_ICSB_SHIFT                    (20U)
/*! ICSB - Interrupt coalescing status
 *  0b0..No task completions have occurred since last counter reset (IC counter =0)
 *  0b1..At least one task completion has been counted (IC counter >0)
 */
#define USDHC_CQIC_ICSB(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICSB_SHIFT)) & USDHC_CQIC_ICSB_MASK)

#define USDHC_CQIC_ICENDIS_MASK                  (0x80000000U)
#define USDHC_CQIC_ICENDIS_SHIFT                 (31U)
/*! ICENDIS - Interrupt coalescing enable/disable */
#define USDHC_CQIC_ICENDIS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICENDIS_SHIFT)) & USDHC_CQIC_ICENDIS_MASK)
/*! @} */

/*! @name CQTDLBA - Command Queuing Task Descriptor List Base Address */
/*! @{ */

#define USDHC_CQTDLBA_TDLBA_MASK                 (0xFFFFFFFFU)
#define USDHC_CQTDLBA_TDLBA_SHIFT                (0U)
/*! TDLBA - Task descriptor list base address */
#define USDHC_CQTDLBA_TDLBA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBA_TDLBA_SHIFT)) & USDHC_CQTDLBA_TDLBA_MASK)
/*! @} */

/*! @name CQTDLBAU - Command Queuing Task Descriptor List Base Address Upper 32 Bits */
/*! @{ */

#define USDHC_CQTDLBAU_TDLBAU_MASK               (0xFFFFFFFFU)
#define USDHC_CQTDLBAU_TDLBAU_SHIFT              (0U)
/*! TDLBAU - Task descriptor list base address */
#define USDHC_CQTDLBAU_TDLBAU(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBAU_TDLBAU_SHIFT)) & USDHC_CQTDLBAU_TDLBAU_MASK)
/*! @} */

/*! @name CQTDBR - Command Queuing Task Doorbell */
/*! @{ */

#define USDHC_CQTDBR_TDBR_MASK                   (0xFFFFFFFFU)
#define USDHC_CQTDBR_TDBR_SHIFT                  (0U)
/*! TDBR - Task doorbell */
#define USDHC_CQTDBR_TDBR(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDBR_TDBR_SHIFT)) & USDHC_CQTDBR_TDBR_MASK)
/*! @} */

/*! @name CQTCN - Command Queuing Task Completion Notification */
/*! @{ */

#define USDHC_CQTCN_TCN_MASK                     (0xFFFFFFFFU)
#define USDHC_CQTCN_TCN_SHIFT                    (0U)
/*! TCN - Task complete notification */
#define USDHC_CQTCN_TCN(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCN_TCN_SHIFT)) & USDHC_CQTCN_TCN_MASK)
/*! @} */

/*! @name CQDQS - Command Queuing Device Queue Status */
/*! @{ */

#define USDHC_CQDQS_DQS_MASK                     (0xFFFFFFFFU)
#define USDHC_CQDQS_DQS_SHIFT                    (0U)
/*! DQS - Device queue status */
#define USDHC_CQDQS_DQS(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQDQS_DQS_SHIFT)) & USDHC_CQDQS_DQS_MASK)
/*! @} */

/*! @name CQDPT - Command Queuing Device Pending Tasks */
/*! @{ */

#define USDHC_CQDPT_DPT_MASK                     (0xFFFFFFFFU)
#define USDHC_CQDPT_DPT_SHIFT                    (0U)
/*! DPT - Device pending tasks */
#define USDHC_CQDPT_DPT(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQDPT_DPT_SHIFT)) & USDHC_CQDPT_DPT_MASK)
/*! @} */

/*! @name CQTCLR - Command Queuing Task Clear */
/*! @{ */

#define USDHC_CQTCLR_TCLR_MASK                   (0xFFFFFFFFU)
#define USDHC_CQTCLR_TCLR_SHIFT                  (0U)
/*! TCLR - Task clear */
#define USDHC_CQTCLR_TCLR(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCLR_TCLR_SHIFT)) & USDHC_CQTCLR_TCLR_MASK)
/*! @} */

/*! @name CQSSC1 - Command Queuing Send Status Configuration 1 */
/*! @{ */

#define USDHC_CQSSC1_CIT_MASK                    (0xFFFFU)
#define USDHC_CQSSC1_CIT_SHIFT                   (0U)
/*! CIT - Send status command idle timer */
#define USDHC_CQSSC1_CIT(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CIT_SHIFT)) & USDHC_CQSSC1_CIT_MASK)

#define USDHC_CQSSC1_CBC_MASK                    (0xF0000U)
#define USDHC_CQSSC1_CBC_SHIFT                   (16U)
/*! CBC - Send status command block counter */
#define USDHC_CQSSC1_CBC(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CBC_SHIFT)) & USDHC_CQSSC1_CBC_MASK)
/*! @} */

/*! @name CQSSC2 - Command Queuing Send Status Configuration 2 */
/*! @{ */

#define USDHC_CQSSC2_SSC2_MASK                   (0xFFFFU)
#define USDHC_CQSSC2_SSC2_SHIFT                  (0U)
/*! SSC2 - Send queue status RCA */
#define USDHC_CQSSC2_SSC2(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC2_SSC2_SHIFT)) & USDHC_CQSSC2_SSC2_MASK)
/*! @} */

/*! @name CQCRDCT - Command Queuing Command Response for Direct-Command Task */
/*! @{ */

#define USDHC_CQCRDCT_CRDCT_MASK                 (0xFFFFFFFFU)
#define USDHC_CQCRDCT_CRDCT_SHIFT                (0U)
/*! CRDCT - Direct command last response */
#define USDHC_CQCRDCT_CRDCT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRDCT_CRDCT_SHIFT)) & USDHC_CQCRDCT_CRDCT_MASK)
/*! @} */

/*! @name CQRMEM - Command Queuing Response Mode Error Mask */
/*! @{ */

#define USDHC_CQRMEM_RMEM_MASK                   (0xFFFFFFFFU)
#define USDHC_CQRMEM_RMEM_SHIFT                  (0U)
/*! RMEM - Response mode error mask
 *  0b00000000000000000000000000000000..When a R1/R1b response is received, bit i in the device status is ignored
 *  0b00000000000000000000000000000001..When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated
 */
#define USDHC_CQRMEM_RMEM(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQRMEM_RMEM_SHIFT)) & USDHC_CQRMEM_RMEM_MASK)
/*! @} */

/*! @name CQTERRI - Command Queuing Task Error Information */
/*! @{ */

#define USDHC_CQTERRI_RMECI_MASK                 (0x3FU)
#define USDHC_CQTERRI_RMECI_SHIFT                (0U)
/*! RMECI - Response mode error command index */
#define USDHC_CQTERRI_RMECI(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMECI_SHIFT)) & USDHC_CQTERRI_RMECI_MASK)

#define USDHC_CQTERRI_RMETID_MASK                (0x1F00U)
#define USDHC_CQTERRI_RMETID_SHIFT               (8U)
/*! RMETID - Response mode error task ID */
#define USDHC_CQTERRI_RMETID(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMETID_SHIFT)) & USDHC_CQTERRI_RMETID_MASK)

#define USDHC_CQTERRI_RMEFV_MASK                 (0x8000U)
#define USDHC_CQTERRI_RMEFV_SHIFT                (15U)
/*! RMEFV - Response mode error fields valid */
#define USDHC_CQTERRI_RMEFV(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMEFV_SHIFT)) & USDHC_CQTERRI_RMEFV_MASK)

#define USDHC_CQTERRI_DTECI_MASK                 (0x3F0000U)
#define USDHC_CQTERRI_DTECI_SHIFT                (16U)
/*! DTECI - Data transfer error command index */
#define USDHC_CQTERRI_DTECI(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTECI_SHIFT)) & USDHC_CQTERRI_DTECI_MASK)

#define USDHC_CQTERRI_DTETID_MASK                (0x1F000000U)
#define USDHC_CQTERRI_DTETID_SHIFT               (24U)
/*! DTETID - Data transfer error task ID */
#define USDHC_CQTERRI_DTETID(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTETID_SHIFT)) & USDHC_CQTERRI_DTETID_MASK)

#define USDHC_CQTERRI_DTEFV_MASK                 (0x80000000U)
#define USDHC_CQTERRI_DTEFV_SHIFT                (31U)
/*! DTEFV - Data transfer error fields valid */
#define USDHC_CQTERRI_DTEFV(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTEFV_SHIFT)) & USDHC_CQTERRI_DTEFV_MASK)
/*! @} */

/*! @name CQCRI - Command Queuing Command Response Index */
/*! @{ */

#define USDHC_CQCRI_LCMDRI_MASK                  (0x3FU)
#define USDHC_CQCRI_LCMDRI_SHIFT                 (0U)
/*! LCMDRI - Last command response index */
#define USDHC_CQCRI_LCMDRI(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRI_LCMDRI_SHIFT)) & USDHC_CQCRI_LCMDRI_MASK)
/*! @} */

/*! @name CQCRA - Command Queuing Command Response Argument */
/*! @{ */

#define USDHC_CQCRA_LCMDRA_MASK                  (0xFFFFFFFFU)
#define USDHC_CQCRA_LCMDRA_SHIFT                 (0U)
/*! LCMDRA - Last command response argument */
#define USDHC_CQCRA_LCMDRA(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRA_LCMDRA_SHIFT)) & USDHC_CQCRA_LCMDRA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USDHC_Register_Masks */


/* USDHC - Peripheral instance base addresses */
/** Peripheral USDHC0 base address */
#define USDHC0_BASE                              (0x298D0000u)
/** Peripheral USDHC0 base pointer */
#define USDHC0                                   ((USDHC_Type *)USDHC0_BASE)
/** Peripheral USDHC1 base address */
#define USDHC1_BASE                              (0x298E0000u)
/** Peripheral USDHC1 base pointer */
#define USDHC1                                   ((USDHC_Type *)USDHC1_BASE)
/** Peripheral USDHC2 base address */
#define USDHC2_BASE                              (0x298F0000u)
/** Peripheral USDHC2 base pointer */
#define USDHC2                                   ((USDHC_Type *)USDHC2_BASE)
/** Array initializer of USDHC peripheral base addresses */
#define USDHC_BASE_ADDRS                         { USDHC0_BASE, USDHC1_BASE, USDHC2_BASE }
/** Array initializer of USDHC peripheral base pointers */
#define USDHC_BASE_PTRS                          { USDHC0, USDHC1, USDHC2 }

/*!
 * @}
 */ /* end of group USDHC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- WDOG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
 * @{
 */

/** WDOG - Register Layout Typedef */
typedef struct {
  __IO uint32_t CS;                                /**< Watchdog Control and Status Register, offset: 0x0 */
  __IO uint32_t CNT;                               /**< Watchdog Counter Register, offset: 0x4 */
  __IO uint32_t TOVAL;                             /**< Watchdog Timeout Value Register, offset: 0x8 */
  __IO uint32_t WIN;                               /**< Watchdog Window Register, offset: 0xC */
} WDOG_Type;

/* ----------------------------------------------------------------------------
   -- WDOG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WDOG_Register_Masks WDOG Register Masks
 * @{
 */

/*! @name CS - Watchdog Control and Status Register */
/*! @{ */

#define WDOG_CS_STOP_MASK                        (0x1U)
#define WDOG_CS_STOP_SHIFT                       (0U)
/*! STOP - Stop Enable
 *  0b0..Watchdog disabled in chip stop mode.
 *  0b1..Watchdog enabled in chip stop mode.
 */
#define WDOG_CS_STOP(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK)

#define WDOG_CS_WAIT_MASK                        (0x2U)
#define WDOG_CS_WAIT_SHIFT                       (1U)
/*! WAIT - Wait Enable
 *  0b0..Watchdog disabled in chip wait mode.
 *  0b1..Watchdog enabled in chip wait mode.
 */
#define WDOG_CS_WAIT(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK)

#define WDOG_CS_DBG_MASK                         (0x4U)
#define WDOG_CS_DBG_SHIFT                        (2U)
/*! DBG - Debug Enable
 *  0b0..Watchdog disabled in chip debug mode.
 *  0b1..Watchdog enabled in chip debug mode.
 */
#define WDOG_CS_DBG(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK)

#define WDOG_CS_TST_MASK                         (0x18U)
#define WDOG_CS_TST_SHIFT                        (3U)
/*! TST - Watchdog Test
 *  0b00..Watchdog test mode disabled.
 *  0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should
 *        use this setting to indicate that the watchdog is functioning normally in user mode.
 *  0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
 *  0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
 */
#define WDOG_CS_TST(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK)

#define WDOG_CS_UPDATE_MASK                      (0x20U)
#define WDOG_CS_UPDATE_SHIFT                     (5U)
/*! UPDATE - Allow updates
 *  0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
 *  0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
 */
#define WDOG_CS_UPDATE(x)                        (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK)

#define WDOG_CS_INT_MASK                         (0x40U)
#define WDOG_CS_INT_SHIFT                        (6U)
/*! INT - Watchdog Interrupt
 *  0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
 *  0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 1023 bus clocks from the interrupt vector fetch.
 */
#define WDOG_CS_INT(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK)

#define WDOG_CS_EN_MASK                          (0x80U)
#define WDOG_CS_EN_SHIFT                         (7U)
/*! EN - Watchdog Enable
 *  0b0..Watchdog disabled.
 *  0b1..Watchdog enabled.
 */
#define WDOG_CS_EN(x)                            (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK)

#define WDOG_CS_CLK_MASK                         (0x300U)
#define WDOG_CS_CLK_SHIFT                        (8U)
/*! CLK - Watchdog Clock */
#define WDOG_CS_CLK(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK)

#define WDOG_CS_RCS_MASK                         (0x400U)
#define WDOG_CS_RCS_SHIFT                        (10U)
/*! RCS - Reconfiguration Success
 *  0b0..Reconfiguring WDOG.
 *  0b1..Reconfiguration is successful.
 */
#define WDOG_CS_RCS(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK)

#define WDOG_CS_ULK_MASK                         (0x800U)
#define WDOG_CS_ULK_SHIFT                        (11U)
/*! ULK - Unlock status
 *  0b0..WDOG is locked.
 *  0b1..WDOG is unlocked.
 */
#define WDOG_CS_ULK(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK)

#define WDOG_CS_PRES_MASK                        (0x1000U)
#define WDOG_CS_PRES_SHIFT                       (12U)
/*! PRES - Watchdog prescaler
 *  0b0..256 prescaler disabled.
 *  0b1..256 prescaler enabled.
 */
#define WDOG_CS_PRES(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK)

#define WDOG_CS_CMD32EN_MASK                     (0x2000U)
#define WDOG_CS_CMD32EN_SHIFT                    (13U)
/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
 *  0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
 *  0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
 */
#define WDOG_CS_CMD32EN(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK)

#define WDOG_CS_FLG_MASK                         (0x4000U)
#define WDOG_CS_FLG_SHIFT                        (14U)
/*! FLG - Watchdog Interrupt Flag
 *  0b0..No interrupt occurred.
 *  0b1..An interrupt occurred.
 */
#define WDOG_CS_FLG(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK)

#define WDOG_CS_WIN_MASK                         (0x8000U)
#define WDOG_CS_WIN_SHIFT                        (15U)
/*! WIN - Watchdog Window
 *  0b0..Window mode disabled.
 *  0b1..Window mode enabled.
 */
#define WDOG_CS_WIN(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK)
/*! @} */

/*! @name CNT - Watchdog Counter Register */
/*! @{ */

#define WDOG_CNT_CNTLOW_MASK                     (0xFFU)
#define WDOG_CNT_CNTLOW_SHIFT                    (0U)
/*! CNTLOW - Low byte of the Watchdog Counter */
#define WDOG_CNT_CNTLOW(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK)

#define WDOG_CNT_CNTHIGH_MASK                    (0xFF00U)
#define WDOG_CNT_CNTHIGH_SHIFT                   (8U)
/*! CNTHIGH - High byte of the Watchdog Counter */
#define WDOG_CNT_CNTHIGH(x)                      (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK)
/*! @} */

/*! @name TOVAL - Watchdog Timeout Value Register */
/*! @{ */

#define WDOG_TOVAL_TOVALLOW_MASK                 (0xFFU)
#define WDOG_TOVAL_TOVALLOW_SHIFT                (0U)
/*! TOVALLOW - Low byte of the timeout value */
#define WDOG_TOVAL_TOVALLOW(x)                   (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK)

#define WDOG_TOVAL_TOVALHIGH_MASK                (0xFF00U)
#define WDOG_TOVAL_TOVALHIGH_SHIFT               (8U)
/*! TOVALHIGH - High byte of the timeout value */
#define WDOG_TOVAL_TOVALHIGH(x)                  (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK)
/*! @} */

/*! @name WIN - Watchdog Window Register */
/*! @{ */

#define WDOG_WIN_WINLOW_MASK                     (0xFFU)
#define WDOG_WIN_WINLOW_SHIFT                    (0U)
/*! WINLOW - Low byte of Watchdog Window */
#define WDOG_WIN_WINLOW(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK)

#define WDOG_WIN_WINHIGH_MASK                    (0xFF00U)
#define WDOG_WIN_WINHIGH_SHIFT                   (8U)
/*! WINHIGH - High byte of Watchdog Window */
#define WDOG_WIN_WINHIGH(x)                      (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group WDOG_Register_Masks */


/* WDOG - Peripheral instance base addresses */
/** Peripheral WDOG0 base address */
#define WDOG0_BASE                               (0x2802C000u)
/** Peripheral WDOG0 base pointer */
#define WDOG0                                    ((WDOG_Type *)WDOG0_BASE)
/** Peripheral WDOG1 base address */
#define WDOG1_BASE                               (0x2802D000u)
/** Peripheral WDOG1 base pointer */
#define WDOG1                                    ((WDOG_Type *)WDOG1_BASE)
/** Peripheral WDOG2 base address */
#define WDOG2_BASE                               (0x28101000u)
/** Peripheral WDOG2 base pointer */
#define WDOG2                                    ((WDOG_Type *)WDOG2_BASE)
/** Peripheral WDOG3 base address */
#define WDOG3_BASE                               (0x292A0000u)
/** Peripheral WDOG3 base pointer */
#define WDOG3                                    ((WDOG_Type *)WDOG3_BASE)
/** Peripheral WDOG4 base address */
#define WDOG4_BASE                               (0x292B0000u)
/** Peripheral WDOG4 base pointer */
#define WDOG4                                    ((WDOG_Type *)WDOG4_BASE)
/** Peripheral WDOG5 base address */
#define WDOG5_BASE                               (0x2DB20000u)
/** Peripheral WDOG5 base pointer */
#define WDOG5                                    ((WDOG_Type *)WDOG5_BASE)
/** Array initializer of WDOG peripheral base addresses */
#define WDOG_BASE_ADDRS                          { WDOG0_BASE, WDOG1_BASE, WDOG2_BASE, WDOG3_BASE, WDOG4_BASE, WDOG5_BASE }
/** Array initializer of WDOG peripheral base pointers */
#define WDOG_BASE_PTRS                           { WDOG0, WDOG1, WDOG2, WDOG3, WDOG4, WDOG5 }
/** Interrupt vectors for the WDOG peripheral type */
#define WDOG_IRQS                                { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, WDOG5_IRQn }
/* Extra definition */
#define WDOG_UPDATE_KEY                          (0xD928C520U)
#define WDOG_REFRESH_KEY                         (0xB480A602U)


/*!
 * @}
 */ /* end of group WDOG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- WUU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WUU_Peripheral_Access_Layer WUU Peripheral Access Layer
 * @{
 */

/** WUU - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
  __IO uint32_t PE1;                               /**< Pin Enable 1, offset: 0x8 */
  __IO uint32_t PE2;                               /**< Pin Enable 2, offset: 0xC */
       uint8_t RESERVED_0[8];
  __IO uint32_t ME;                                /**< Module Interrupt Enable, offset: 0x18 */
  __IO uint32_t DE;                                /**< Module DMA/Trigger Enable, offset: 0x1C */
  __IO uint32_t PF;                                /**< Pin Flag, offset: 0x20 */
       uint8_t RESERVED_1[4];
  __I  uint32_t MF;                                /**< Module Interrupt Flag, offset: 0x28 */
       uint8_t RESERVED_2[4];
  __IO uint32_t FILT;                              /**< Pin Filter, offset: 0x30 */
       uint8_t RESERVED_3[4];
  __IO uint32_t PDC1;                              /**< Pin DMA/Trigger Configuration 1, offset: 0x38 */
  __IO uint32_t PDC2;                              /**< Pin DMA/Trigger Configuration 2, offset: 0x3C */
       uint8_t RESERVED_4[8];
  __IO uint32_t FDC;                               /**< Pin Filter DMA/Trigger Configuration, offset: 0x48 */
       uint8_t RESERVED_5[4];
  __IO uint32_t PMC;                               /**< Pin Mode Configuration, offset: 0x50 */
       uint8_t RESERVED_6[4];
  __IO uint32_t FMC;                               /**< Pin Filter Mode Configuration, offset: 0x58 */
} WUU_Type;

/* ----------------------------------------------------------------------------
   -- WUU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WUU_Register_Masks WUU Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define WUU_VERID_FEATURE_MASK                   (0xFFFFU)
#define WUU_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000000..Standard features implemented
 *  0b0000000000000001..Support for DMA/Trigger generation from wakeup pins and filters enabled. Support for
 *                      external pin/filter detection during all power modes enabled.
 */
#define WUU_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK)

#define WUU_VERID_MINOR_MASK                     (0xFF0000U)
#define WUU_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number */
#define WUU_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MINOR_SHIFT)) & WUU_VERID_MINOR_MASK)

#define WUU_VERID_MAJOR_MASK                     (0xFF000000U)
#define WUU_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number */
#define WUU_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MAJOR_SHIFT)) & WUU_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define WUU_PARAM_FILTERS_MASK                   (0xFFU)
#define WUU_PARAM_FILTERS_SHIFT                  (0U)
/*! FILTERS - Filter Number */
#define WUU_PARAM_FILTERS(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_FILTERS_SHIFT)) & WUU_PARAM_FILTERS_MASK)

#define WUU_PARAM_DMAS_MASK                      (0xFF00U)
#define WUU_PARAM_DMAS_SHIFT                     (8U)
/*! DMAS - DMA Number */
#define WUU_PARAM_DMAS(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_DMAS_SHIFT)) & WUU_PARAM_DMAS_MASK)

#define WUU_PARAM_MODULES_MASK                   (0xFF0000U)
#define WUU_PARAM_MODULES_SHIFT                  (16U)
/*! MODULES - Module Number */
#define WUU_PARAM_MODULES(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_MODULES_SHIFT)) & WUU_PARAM_MODULES_MASK)

#define WUU_PARAM_PINS_MASK                      (0xFF000000U)
#define WUU_PARAM_PINS_SHIFT                     (24U)
/*! PINS - Pin Number */
#define WUU_PARAM_PINS(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_PINS_SHIFT)) & WUU_PARAM_PINS_MASK)
/*! @} */

/*! @name PE1 - Pin Enable 1 */
/*! @{ */

#define WUU_PE1_WUPE0_MASK                       (0x3U)
#define WUU_PE1_WUPE0_SHIFT                      (0U)
/*! WUPE0 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE0(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE0_SHIFT)) & WUU_PE1_WUPE0_MASK)

#define WUU_PE1_WUPE1_MASK                       (0xCU)
#define WUU_PE1_WUPE1_SHIFT                      (2U)
/*! WUPE1 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE1(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE1_SHIFT)) & WUU_PE1_WUPE1_MASK)

#define WUU_PE1_WUPE2_MASK                       (0x30U)
#define WUU_PE1_WUPE2_SHIFT                      (4U)
/*! WUPE2 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE2(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE2_SHIFT)) & WUU_PE1_WUPE2_MASK)

#define WUU_PE1_WUPE3_MASK                       (0xC0U)
#define WUU_PE1_WUPE3_SHIFT                      (6U)
/*! WUPE3 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE3(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE3_SHIFT)) & WUU_PE1_WUPE3_MASK)

#define WUU_PE1_WUPE4_MASK                       (0x300U)
#define WUU_PE1_WUPE4_SHIFT                      (8U)
/*! WUPE4 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE4(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE4_SHIFT)) & WUU_PE1_WUPE4_MASK)

#define WUU_PE1_WUPE5_MASK                       (0xC00U)
#define WUU_PE1_WUPE5_SHIFT                      (10U)
/*! WUPE5 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE5(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE5_SHIFT)) & WUU_PE1_WUPE5_MASK)

#define WUU_PE1_WUPE6_MASK                       (0x3000U)
#define WUU_PE1_WUPE6_SHIFT                      (12U)
/*! WUPE6 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE6(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE6_SHIFT)) & WUU_PE1_WUPE6_MASK)

#define WUU_PE1_WUPE7_MASK                       (0xC000U)
#define WUU_PE1_WUPE7_SHIFT                      (14U)
/*! WUPE7 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE7(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE7_SHIFT)) & WUU_PE1_WUPE7_MASK)

#define WUU_PE1_WUPE8_MASK                       (0x30000U)
#define WUU_PE1_WUPE8_SHIFT                      (16U)
/*! WUPE8 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE8(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE8_SHIFT)) & WUU_PE1_WUPE8_MASK)

#define WUU_PE1_WUPE9_MASK                       (0xC0000U)
#define WUU_PE1_WUPE9_SHIFT                      (18U)
/*! WUPE9 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE9(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE9_SHIFT)) & WUU_PE1_WUPE9_MASK)

#define WUU_PE1_WUPE10_MASK                      (0x300000U)
#define WUU_PE1_WUPE10_SHIFT                     (20U)
/*! WUPE10 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE10(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE10_SHIFT)) & WUU_PE1_WUPE10_MASK)

#define WUU_PE1_WUPE11_MASK                      (0xC00000U)
#define WUU_PE1_WUPE11_SHIFT                     (22U)
/*! WUPE11 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE11(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE11_SHIFT)) & WUU_PE1_WUPE11_MASK)

#define WUU_PE1_WUPE12_MASK                      (0x3000000U)
#define WUU_PE1_WUPE12_SHIFT                     (24U)
/*! WUPE12 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE12(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE12_SHIFT)) & WUU_PE1_WUPE12_MASK)

#define WUU_PE1_WUPE13_MASK                      (0xC000000U)
#define WUU_PE1_WUPE13_SHIFT                     (26U)
/*! WUPE13 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE13(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE13_SHIFT)) & WUU_PE1_WUPE13_MASK)

#define WUU_PE1_WUPE14_MASK                      (0x30000000U)
#define WUU_PE1_WUPE14_SHIFT                     (28U)
/*! WUPE14 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE14(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE14_SHIFT)) & WUU_PE1_WUPE14_MASK)

#define WUU_PE1_WUPE15_MASK                      (0xC0000000U)
#define WUU_PE1_WUPE15_SHIFT                     (30U)
/*! WUPE15 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE15(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE15_SHIFT)) & WUU_PE1_WUPE15_MASK)
/*! @} */

/*! @name PE2 - Pin Enable 2 */
/*! @{ */

#define WUU_PE2_Reserved16_MASK                  (0x3U)
#define WUU_PE2_Reserved16_SHIFT                 (0U)
/*! Reserved16 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved16(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved16_SHIFT)) & WUU_PE2_Reserved16_MASK)

#define WUU_PE2_WUPE16_MASK                      (0x3U)
#define WUU_PE2_WUPE16_SHIFT                     (0U)
/*! WUPE16 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE16(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE16_SHIFT)) & WUU_PE2_WUPE16_MASK)

#define WUU_PE2_Reserved17_MASK                  (0xCU)
#define WUU_PE2_Reserved17_SHIFT                 (2U)
/*! Reserved17 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved17(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved17_SHIFT)) & WUU_PE2_Reserved17_MASK)

#define WUU_PE2_WUPE17_MASK                      (0xCU)
#define WUU_PE2_WUPE17_SHIFT                     (2U)
/*! WUPE17 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE17(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE17_SHIFT)) & WUU_PE2_WUPE17_MASK)

#define WUU_PE2_Reserved18_MASK                  (0x30U)
#define WUU_PE2_Reserved18_SHIFT                 (4U)
/*! Reserved18 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved18(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved18_SHIFT)) & WUU_PE2_Reserved18_MASK)

#define WUU_PE2_WUPE18_MASK                      (0x30U)
#define WUU_PE2_WUPE18_SHIFT                     (4U)
/*! WUPE18 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE18(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE18_SHIFT)) & WUU_PE2_WUPE18_MASK)

#define WUU_PE2_Reserved19_MASK                  (0xC0U)
#define WUU_PE2_Reserved19_SHIFT                 (6U)
/*! Reserved19 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved19(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved19_SHIFT)) & WUU_PE2_Reserved19_MASK)

#define WUU_PE2_WUPE19_MASK                      (0xC0U)
#define WUU_PE2_WUPE19_SHIFT                     (6U)
/*! WUPE19 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE19(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE19_SHIFT)) & WUU_PE2_WUPE19_MASK)

#define WUU_PE2_Reserved20_MASK                  (0x300U)
#define WUU_PE2_Reserved20_SHIFT                 (8U)
/*! Reserved20 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved20(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved20_SHIFT)) & WUU_PE2_Reserved20_MASK)

#define WUU_PE2_WUPE20_MASK                      (0x300U)
#define WUU_PE2_WUPE20_SHIFT                     (8U)
/*! WUPE20 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE20(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE20_SHIFT)) & WUU_PE2_WUPE20_MASK)

#define WUU_PE2_Reserved21_MASK                  (0xC00U)
#define WUU_PE2_Reserved21_SHIFT                 (10U)
/*! Reserved21 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved21(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved21_SHIFT)) & WUU_PE2_Reserved21_MASK)

#define WUU_PE2_WUPE21_MASK                      (0xC00U)
#define WUU_PE2_WUPE21_SHIFT                     (10U)
/*! WUPE21 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE21(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE21_SHIFT)) & WUU_PE2_WUPE21_MASK)

#define WUU_PE2_Reserved22_MASK                  (0x3000U)
#define WUU_PE2_Reserved22_SHIFT                 (12U)
/*! Reserved22 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved22(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved22_SHIFT)) & WUU_PE2_Reserved22_MASK)

#define WUU_PE2_WUPE22_MASK                      (0x3000U)
#define WUU_PE2_WUPE22_SHIFT                     (12U)
/*! WUPE22 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE22(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE22_SHIFT)) & WUU_PE2_WUPE22_MASK)

#define WUU_PE2_Reserved23_MASK                  (0xC000U)
#define WUU_PE2_Reserved23_SHIFT                 (14U)
/*! Reserved23 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved23(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved23_SHIFT)) & WUU_PE2_Reserved23_MASK)

#define WUU_PE2_WUPE23_MASK                      (0xC000U)
#define WUU_PE2_WUPE23_SHIFT                     (14U)
/*! WUPE23 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE23(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE23_SHIFT)) & WUU_PE2_WUPE23_MASK)

#define WUU_PE2_Reserved24_MASK                  (0x30000U)
#define WUU_PE2_Reserved24_SHIFT                 (16U)
/*! Reserved24 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved24(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved24_SHIFT)) & WUU_PE2_Reserved24_MASK)

#define WUU_PE2_WUPE24_MASK                      (0x30000U)
#define WUU_PE2_WUPE24_SHIFT                     (16U)
/*! WUPE24 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE24(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE24_SHIFT)) & WUU_PE2_WUPE24_MASK)

#define WUU_PE2_Reserved25_MASK                  (0xC0000U)
#define WUU_PE2_Reserved25_SHIFT                 (18U)
/*! Reserved25 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved25(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved25_SHIFT)) & WUU_PE2_Reserved25_MASK)

#define WUU_PE2_WUPE25_MASK                      (0xC0000U)
#define WUU_PE2_WUPE25_SHIFT                     (18U)
/*! WUPE25 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE25(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE25_SHIFT)) & WUU_PE2_WUPE25_MASK)

#define WUU_PE2_Reserved26_MASK                  (0x300000U)
#define WUU_PE2_Reserved26_SHIFT                 (20U)
/*! Reserved26 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved26(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved26_SHIFT)) & WUU_PE2_Reserved26_MASK)

#define WUU_PE2_WUPE26_MASK                      (0x300000U)
#define WUU_PE2_WUPE26_SHIFT                     (20U)
/*! WUPE26 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE26(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE26_SHIFT)) & WUU_PE2_WUPE26_MASK)

#define WUU_PE2_Reserved27_MASK                  (0xC00000U)
#define WUU_PE2_Reserved27_SHIFT                 (22U)
/*! Reserved27 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved27(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved27_SHIFT)) & WUU_PE2_Reserved27_MASK)

#define WUU_PE2_WUPE27_MASK                      (0xC00000U)
#define WUU_PE2_WUPE27_SHIFT                     (22U)
/*! WUPE27 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE27(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE27_SHIFT)) & WUU_PE2_WUPE27_MASK)

#define WUU_PE2_Reserved28_MASK                  (0x3000000U)
#define WUU_PE2_Reserved28_SHIFT                 (24U)
/*! Reserved28 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved28(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved28_SHIFT)) & WUU_PE2_Reserved28_MASK)

#define WUU_PE2_Reserved29_MASK                  (0xC000000U)
#define WUU_PE2_Reserved29_SHIFT                 (26U)
/*! Reserved29 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved29(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved29_SHIFT)) & WUU_PE2_Reserved29_MASK)

#define WUU_PE2_Reserved30_MASK                  (0x30000000U)
#define WUU_PE2_Reserved30_SHIFT                 (28U)
/*! Reserved30 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved30(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved30_SHIFT)) & WUU_PE2_Reserved30_MASK)

#define WUU_PE2_Reserved31_MASK                  (0xC0000000U)
#define WUU_PE2_Reserved31_SHIFT                 (30U)
/*! Reserved31 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE2_Reserved31(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved31_SHIFT)) & WUU_PE2_Reserved31_MASK)
/*! @} */

/*! @name ME - Module Interrupt Enable */
/*! @{ */

#define WUU_ME_WUME0_MASK                        (0x1U)
#define WUU_ME_WUME0_SHIFT                       (0U)
/*! WUME0 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME0(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK)

#define WUU_ME_WUME1_MASK                        (0x2U)
#define WUU_ME_WUME1_SHIFT                       (1U)
/*! WUME1 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME1(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME1_SHIFT)) & WUU_ME_WUME1_MASK)

#define WUU_ME_WUME2_MASK                        (0x4U)
#define WUU_ME_WUME2_SHIFT                       (2U)
/*! WUME2 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME2(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK)

#define WUU_ME_WUME3_MASK                        (0x8U)
#define WUU_ME_WUME3_SHIFT                       (3U)
/*! WUME3 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME3(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME3_SHIFT)) & WUU_ME_WUME3_MASK)

#define WUU_ME_WUME4_MASK                        (0x10U)
#define WUU_ME_WUME4_SHIFT                       (4U)
/*! WUME4 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME4(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME4_SHIFT)) & WUU_ME_WUME4_MASK)

#define WUU_ME_WUME5_MASK                        (0x20U)
#define WUU_ME_WUME5_SHIFT                       (5U)
/*! WUME5 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME5(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME5_SHIFT)) & WUU_ME_WUME5_MASK)

#define WUU_ME_WUME6_MASK                        (0x40U)
#define WUU_ME_WUME6_SHIFT                       (6U)
/*! WUME6 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME6(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK)

#define WUU_ME_WUME7_MASK                        (0x80U)
#define WUU_ME_WUME7_SHIFT                       (7U)
/*! WUME7 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME7(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME7_SHIFT)) & WUU_ME_WUME7_MASK)

#define WUU_ME_Reserved8_MASK                    (0x100U)
#define WUU_ME_Reserved8_SHIFT                   (8U)
/*! Reserved8 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved8(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved8_SHIFT)) & WUU_ME_Reserved8_MASK)

#define WUU_ME_Reserved9_MASK                    (0x200U)
#define WUU_ME_Reserved9_SHIFT                   (9U)
/*! Reserved9 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved9(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved9_SHIFT)) & WUU_ME_Reserved9_MASK)

#define WUU_ME_Reserved10_MASK                   (0x400U)
#define WUU_ME_Reserved10_SHIFT                  (10U)
/*! Reserved10 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved10(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved10_SHIFT)) & WUU_ME_Reserved10_MASK)

#define WUU_ME_Reserved11_MASK                   (0x800U)
#define WUU_ME_Reserved11_SHIFT                  (11U)
/*! Reserved11 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved11(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved11_SHIFT)) & WUU_ME_Reserved11_MASK)

#define WUU_ME_Reserved12_MASK                   (0x1000U)
#define WUU_ME_Reserved12_SHIFT                  (12U)
/*! Reserved12 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved12(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved12_SHIFT)) & WUU_ME_Reserved12_MASK)

#define WUU_ME_Reserved13_MASK                   (0x2000U)
#define WUU_ME_Reserved13_SHIFT                  (13U)
/*! Reserved13 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved13(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved13_SHIFT)) & WUU_ME_Reserved13_MASK)

#define WUU_ME_Reserved14_MASK                   (0x4000U)
#define WUU_ME_Reserved14_SHIFT                  (14U)
/*! Reserved14 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved14(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved14_SHIFT)) & WUU_ME_Reserved14_MASK)

#define WUU_ME_Reserved15_MASK                   (0x8000U)
#define WUU_ME_Reserved15_SHIFT                  (15U)
/*! Reserved15 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved15(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved15_SHIFT)) & WUU_ME_Reserved15_MASK)

#define WUU_ME_Reserved16_MASK                   (0x10000U)
#define WUU_ME_Reserved16_SHIFT                  (16U)
/*! Reserved16 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved16(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved16_SHIFT)) & WUU_ME_Reserved16_MASK)

#define WUU_ME_Reserved17_MASK                   (0x20000U)
#define WUU_ME_Reserved17_SHIFT                  (17U)
/*! Reserved17 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved17(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved17_SHIFT)) & WUU_ME_Reserved17_MASK)

#define WUU_ME_Reserved18_MASK                   (0x40000U)
#define WUU_ME_Reserved18_SHIFT                  (18U)
/*! Reserved18 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved18(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved18_SHIFT)) & WUU_ME_Reserved18_MASK)

#define WUU_ME_Reserved19_MASK                   (0x80000U)
#define WUU_ME_Reserved19_SHIFT                  (19U)
/*! Reserved19 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved19(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved19_SHIFT)) & WUU_ME_Reserved19_MASK)

#define WUU_ME_Reserved20_MASK                   (0x100000U)
#define WUU_ME_Reserved20_SHIFT                  (20U)
/*! Reserved20 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved20(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved20_SHIFT)) & WUU_ME_Reserved20_MASK)

#define WUU_ME_Reserved21_MASK                   (0x200000U)
#define WUU_ME_Reserved21_SHIFT                  (21U)
/*! Reserved21 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved21(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved21_SHIFT)) & WUU_ME_Reserved21_MASK)

#define WUU_ME_Reserved22_MASK                   (0x400000U)
#define WUU_ME_Reserved22_SHIFT                  (22U)
/*! Reserved22 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved22(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved22_SHIFT)) & WUU_ME_Reserved22_MASK)

#define WUU_ME_Reserved23_MASK                   (0x800000U)
#define WUU_ME_Reserved23_SHIFT                  (23U)
/*! Reserved23 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved23(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved23_SHIFT)) & WUU_ME_Reserved23_MASK)

#define WUU_ME_Reserved24_MASK                   (0x1000000U)
#define WUU_ME_Reserved24_SHIFT                  (24U)
/*! Reserved24 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved24(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved24_SHIFT)) & WUU_ME_Reserved24_MASK)

#define WUU_ME_Reserved25_MASK                   (0x2000000U)
#define WUU_ME_Reserved25_SHIFT                  (25U)
/*! Reserved25 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved25(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved25_SHIFT)) & WUU_ME_Reserved25_MASK)

#define WUU_ME_Reserved26_MASK                   (0x4000000U)
#define WUU_ME_Reserved26_SHIFT                  (26U)
/*! Reserved26 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved26(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved26_SHIFT)) & WUU_ME_Reserved26_MASK)

#define WUU_ME_Reserved27_MASK                   (0x8000000U)
#define WUU_ME_Reserved27_SHIFT                  (27U)
/*! Reserved27 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved27(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved27_SHIFT)) & WUU_ME_Reserved27_MASK)

#define WUU_ME_Reserved28_MASK                   (0x10000000U)
#define WUU_ME_Reserved28_SHIFT                  (28U)
/*! Reserved28 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved28(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved28_SHIFT)) & WUU_ME_Reserved28_MASK)

#define WUU_ME_Reserved29_MASK                   (0x20000000U)
#define WUU_ME_Reserved29_SHIFT                  (29U)
/*! Reserved29 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved29(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved29_SHIFT)) & WUU_ME_Reserved29_MASK)

#define WUU_ME_Reserved30_MASK                   (0x40000000U)
#define WUU_ME_Reserved30_SHIFT                  (30U)
/*! Reserved30 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved30(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved30_SHIFT)) & WUU_ME_Reserved30_MASK)

#define WUU_ME_Reserved31_MASK                   (0x80000000U)
#define WUU_ME_Reserved31_SHIFT                  (31U)
/*! Reserved31 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_ME_Reserved31(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_ME_Reserved31_SHIFT)) & WUU_ME_Reserved31_MASK)
/*! @} */

/*! @name DE - Module DMA/Trigger Enable */
/*! @{ */

#define WUU_DE_Reserved0_MASK                    (0x1U)
#define WUU_DE_Reserved0_SHIFT                   (0U)
/*! Reserved0 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved0(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved0_SHIFT)) & WUU_DE_Reserved0_MASK)

#define WUU_DE_WUDE0_MASK                        (0x1U)
#define WUU_DE_WUDE0_SHIFT                       (0U)
/*! WUDE0 - DMA/Trigger wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_DE_WUDE0(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE0_SHIFT)) & WUU_DE_WUDE0_MASK)

#define WUU_DE_Reserved1_MASK                    (0x2U)
#define WUU_DE_Reserved1_SHIFT                   (1U)
/*! Reserved1 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved1(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved1_SHIFT)) & WUU_DE_Reserved1_MASK)

#define WUU_DE_WUDE1_MASK                        (0x2U)
#define WUU_DE_WUDE1_SHIFT                       (1U)
/*! WUDE1 - DMA/Trigger wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_DE_WUDE1(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE1_SHIFT)) & WUU_DE_WUDE1_MASK)

#define WUU_DE_Reserved2_MASK                    (0x4U)
#define WUU_DE_Reserved2_SHIFT                   (2U)
/*! Reserved2 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved2(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved2_SHIFT)) & WUU_DE_Reserved2_MASK)

#define WUU_DE_Reserved3_MASK                    (0x8U)
#define WUU_DE_Reserved3_SHIFT                   (3U)
/*! Reserved3 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved3(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved3_SHIFT)) & WUU_DE_Reserved3_MASK)

#define WUU_DE_Reserved4_MASK                    (0x10U)
#define WUU_DE_Reserved4_SHIFT                   (4U)
/*! Reserved4 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved4(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved4_SHIFT)) & WUU_DE_Reserved4_MASK)

#define WUU_DE_Reserved5_MASK                    (0x20U)
#define WUU_DE_Reserved5_SHIFT                   (5U)
/*! Reserved5 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved5(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved5_SHIFT)) & WUU_DE_Reserved5_MASK)

#define WUU_DE_Reserved6_MASK                    (0x40U)
#define WUU_DE_Reserved6_SHIFT                   (6U)
/*! Reserved6 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved6(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved6_SHIFT)) & WUU_DE_Reserved6_MASK)

#define WUU_DE_Reserved7_MASK                    (0x80U)
#define WUU_DE_Reserved7_SHIFT                   (7U)
/*! Reserved7 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved7(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved7_SHIFT)) & WUU_DE_Reserved7_MASK)

#define WUU_DE_Reserved8_MASK                    (0x100U)
#define WUU_DE_Reserved8_SHIFT                   (8U)
/*! Reserved8 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved8(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved8_SHIFT)) & WUU_DE_Reserved8_MASK)

#define WUU_DE_Reserved9_MASK                    (0x200U)
#define WUU_DE_Reserved9_SHIFT                   (9U)
/*! Reserved9 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved9(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved9_SHIFT)) & WUU_DE_Reserved9_MASK)

#define WUU_DE_Reserved10_MASK                   (0x400U)
#define WUU_DE_Reserved10_SHIFT                  (10U)
/*! Reserved10 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved10(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved10_SHIFT)) & WUU_DE_Reserved10_MASK)

#define WUU_DE_Reserved11_MASK                   (0x800U)
#define WUU_DE_Reserved11_SHIFT                  (11U)
/*! Reserved11 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved11(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved11_SHIFT)) & WUU_DE_Reserved11_MASK)

#define WUU_DE_Reserved12_MASK                   (0x1000U)
#define WUU_DE_Reserved12_SHIFT                  (12U)
/*! Reserved12 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved12(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved12_SHIFT)) & WUU_DE_Reserved12_MASK)

#define WUU_DE_Reserved13_MASK                   (0x2000U)
#define WUU_DE_Reserved13_SHIFT                  (13U)
/*! Reserved13 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved13(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved13_SHIFT)) & WUU_DE_Reserved13_MASK)

#define WUU_DE_Reserved14_MASK                   (0x4000U)
#define WUU_DE_Reserved14_SHIFT                  (14U)
/*! Reserved14 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved14(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved14_SHIFT)) & WUU_DE_Reserved14_MASK)

#define WUU_DE_Reserved15_MASK                   (0x8000U)
#define WUU_DE_Reserved15_SHIFT                  (15U)
/*! Reserved15 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved15(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved15_SHIFT)) & WUU_DE_Reserved15_MASK)

#define WUU_DE_Reserved16_MASK                   (0x10000U)
#define WUU_DE_Reserved16_SHIFT                  (16U)
/*! Reserved16 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved16(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved16_SHIFT)) & WUU_DE_Reserved16_MASK)

#define WUU_DE_Reserved17_MASK                   (0x20000U)
#define WUU_DE_Reserved17_SHIFT                  (17U)
/*! Reserved17 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved17(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved17_SHIFT)) & WUU_DE_Reserved17_MASK)

#define WUU_DE_Reserved18_MASK                   (0x40000U)
#define WUU_DE_Reserved18_SHIFT                  (18U)
/*! Reserved18 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved18(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved18_SHIFT)) & WUU_DE_Reserved18_MASK)

#define WUU_DE_Reserved19_MASK                   (0x80000U)
#define WUU_DE_Reserved19_SHIFT                  (19U)
/*! Reserved19 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved19(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved19_SHIFT)) & WUU_DE_Reserved19_MASK)

#define WUU_DE_Reserved20_MASK                   (0x100000U)
#define WUU_DE_Reserved20_SHIFT                  (20U)
/*! Reserved20 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved20(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved20_SHIFT)) & WUU_DE_Reserved20_MASK)

#define WUU_DE_Reserved21_MASK                   (0x200000U)
#define WUU_DE_Reserved21_SHIFT                  (21U)
/*! Reserved21 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved21(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved21_SHIFT)) & WUU_DE_Reserved21_MASK)

#define WUU_DE_Reserved22_MASK                   (0x400000U)
#define WUU_DE_Reserved22_SHIFT                  (22U)
/*! Reserved22 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved22(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved22_SHIFT)) & WUU_DE_Reserved22_MASK)

#define WUU_DE_Reserved23_MASK                   (0x800000U)
#define WUU_DE_Reserved23_SHIFT                  (23U)
/*! Reserved23 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved23(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved23_SHIFT)) & WUU_DE_Reserved23_MASK)

#define WUU_DE_Reserved24_MASK                   (0x1000000U)
#define WUU_DE_Reserved24_SHIFT                  (24U)
/*! Reserved24 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved24(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved24_SHIFT)) & WUU_DE_Reserved24_MASK)

#define WUU_DE_Reserved25_MASK                   (0x2000000U)
#define WUU_DE_Reserved25_SHIFT                  (25U)
/*! Reserved25 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved25(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved25_SHIFT)) & WUU_DE_Reserved25_MASK)

#define WUU_DE_Reserved26_MASK                   (0x4000000U)
#define WUU_DE_Reserved26_SHIFT                  (26U)
/*! Reserved26 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved26(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved26_SHIFT)) & WUU_DE_Reserved26_MASK)

#define WUU_DE_Reserved27_MASK                   (0x8000000U)
#define WUU_DE_Reserved27_SHIFT                  (27U)
/*! Reserved27 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved27(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved27_SHIFT)) & WUU_DE_Reserved27_MASK)

#define WUU_DE_Reserved28_MASK                   (0x10000000U)
#define WUU_DE_Reserved28_SHIFT                  (28U)
/*! Reserved28 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved28(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved28_SHIFT)) & WUU_DE_Reserved28_MASK)

#define WUU_DE_Reserved29_MASK                   (0x20000000U)
#define WUU_DE_Reserved29_SHIFT                  (29U)
/*! Reserved29 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved29(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved29_SHIFT)) & WUU_DE_Reserved29_MASK)

#define WUU_DE_Reserved30_MASK                   (0x40000000U)
#define WUU_DE_Reserved30_SHIFT                  (30U)
/*! Reserved30 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved30(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved30_SHIFT)) & WUU_DE_Reserved30_MASK)

#define WUU_DE_Reserved31_MASK                   (0x80000000U)
#define WUU_DE_Reserved31_SHIFT                  (31U)
/*! Reserved31 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_DE_Reserved31(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_DE_Reserved31_SHIFT)) & WUU_DE_Reserved31_MASK)
/*! @} */

/*! @name PF - Pin Flag */
/*! @{ */

#define WUU_PF_WUF0_MASK                         (0x1U)
#define WUU_PF_WUF0_SHIFT                        (0U)
/*! WUF0 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF0(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF0_SHIFT)) & WUU_PF_WUF0_MASK)

#define WUU_PF_WUF1_MASK                         (0x2U)
#define WUU_PF_WUF1_SHIFT                        (1U)
/*! WUF1 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF1(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF1_SHIFT)) & WUU_PF_WUF1_MASK)

#define WUU_PF_WUF2_MASK                         (0x4U)
#define WUU_PF_WUF2_SHIFT                        (2U)
/*! WUF2 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF2(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF2_SHIFT)) & WUU_PF_WUF2_MASK)

#define WUU_PF_WUF3_MASK                         (0x8U)
#define WUU_PF_WUF3_SHIFT                        (3U)
/*! WUF3 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF3(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF3_SHIFT)) & WUU_PF_WUF3_MASK)

#define WUU_PF_WUF4_MASK                         (0x10U)
#define WUU_PF_WUF4_SHIFT                        (4U)
/*! WUF4 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF4(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF4_SHIFT)) & WUU_PF_WUF4_MASK)

#define WUU_PF_WUF5_MASK                         (0x20U)
#define WUU_PF_WUF5_SHIFT                        (5U)
/*! WUF5 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF5(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF5_SHIFT)) & WUU_PF_WUF5_MASK)

#define WUU_PF_WUF6_MASK                         (0x40U)
#define WUU_PF_WUF6_SHIFT                        (6U)
/*! WUF6 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF6(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF6_SHIFT)) & WUU_PF_WUF6_MASK)

#define WUU_PF_WUF7_MASK                         (0x80U)
#define WUU_PF_WUF7_SHIFT                        (7U)
/*! WUF7 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF7(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF7_SHIFT)) & WUU_PF_WUF7_MASK)

#define WUU_PF_WUF8_MASK                         (0x100U)
#define WUU_PF_WUF8_SHIFT                        (8U)
/*! WUF8 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF8(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF8_SHIFT)) & WUU_PF_WUF8_MASK)

#define WUU_PF_WUF9_MASK                         (0x200U)
#define WUU_PF_WUF9_SHIFT                        (9U)
/*! WUF9 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF9(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF9_SHIFT)) & WUU_PF_WUF9_MASK)

#define WUU_PF_WUF10_MASK                        (0x400U)
#define WUU_PF_WUF10_SHIFT                       (10U)
/*! WUF10 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF10(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF10_SHIFT)) & WUU_PF_WUF10_MASK)

#define WUU_PF_WUF11_MASK                        (0x800U)
#define WUU_PF_WUF11_SHIFT                       (11U)
/*! WUF11 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF11(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF11_SHIFT)) & WUU_PF_WUF11_MASK)

#define WUU_PF_WUF12_MASK                        (0x1000U)
#define WUU_PF_WUF12_SHIFT                       (12U)
/*! WUF12 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF12(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF12_SHIFT)) & WUU_PF_WUF12_MASK)

#define WUU_PF_WUF13_MASK                        (0x2000U)
#define WUU_PF_WUF13_SHIFT                       (13U)
/*! WUF13 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF13(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF13_SHIFT)) & WUU_PF_WUF13_MASK)

#define WUU_PF_WUF14_MASK                        (0x4000U)
#define WUU_PF_WUF14_SHIFT                       (14U)
/*! WUF14 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF14(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF14_SHIFT)) & WUU_PF_WUF14_MASK)

#define WUU_PF_WUF15_MASK                        (0x8000U)
#define WUU_PF_WUF15_SHIFT                       (15U)
/*! WUF15 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF15(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF15_SHIFT)) & WUU_PF_WUF15_MASK)

#define WUU_PF_Reserved16_MASK                   (0x10000U)
#define WUU_PF_Reserved16_SHIFT                  (16U)
/*! Reserved16 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved16(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved16_SHIFT)) & WUU_PF_Reserved16_MASK)

#define WUU_PF_WUF16_MASK                        (0x10000U)
#define WUU_PF_WUF16_SHIFT                       (16U)
/*! WUF16 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF16(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF16_SHIFT)) & WUU_PF_WUF16_MASK)

#define WUU_PF_Reserved17_MASK                   (0x20000U)
#define WUU_PF_Reserved17_SHIFT                  (17U)
/*! Reserved17 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved17(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved17_SHIFT)) & WUU_PF_Reserved17_MASK)

#define WUU_PF_WUF17_MASK                        (0x20000U)
#define WUU_PF_WUF17_SHIFT                       (17U)
/*! WUF17 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF17(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF17_SHIFT)) & WUU_PF_WUF17_MASK)

#define WUU_PF_Reserved18_MASK                   (0x40000U)
#define WUU_PF_Reserved18_SHIFT                  (18U)
/*! Reserved18 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved18(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved18_SHIFT)) & WUU_PF_Reserved18_MASK)

#define WUU_PF_WUF18_MASK                        (0x40000U)
#define WUU_PF_WUF18_SHIFT                       (18U)
/*! WUF18 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF18(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF18_SHIFT)) & WUU_PF_WUF18_MASK)

#define WUU_PF_Reserved19_MASK                   (0x80000U)
#define WUU_PF_Reserved19_SHIFT                  (19U)
/*! Reserved19 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved19(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved19_SHIFT)) & WUU_PF_Reserved19_MASK)

#define WUU_PF_WUF19_MASK                        (0x80000U)
#define WUU_PF_WUF19_SHIFT                       (19U)
/*! WUF19 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF19(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF19_SHIFT)) & WUU_PF_WUF19_MASK)

#define WUU_PF_Reserved20_MASK                   (0x100000U)
#define WUU_PF_Reserved20_SHIFT                  (20U)
/*! Reserved20 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved20(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved20_SHIFT)) & WUU_PF_Reserved20_MASK)

#define WUU_PF_WUF20_MASK                        (0x100000U)
#define WUU_PF_WUF20_SHIFT                       (20U)
/*! WUF20 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF20(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF20_SHIFT)) & WUU_PF_WUF20_MASK)

#define WUU_PF_Reserved21_MASK                   (0x200000U)
#define WUU_PF_Reserved21_SHIFT                  (21U)
/*! Reserved21 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved21(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved21_SHIFT)) & WUU_PF_Reserved21_MASK)

#define WUU_PF_WUF21_MASK                        (0x200000U)
#define WUU_PF_WUF21_SHIFT                       (21U)
/*! WUF21 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF21(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF21_SHIFT)) & WUU_PF_WUF21_MASK)

#define WUU_PF_Reserved22_MASK                   (0x400000U)
#define WUU_PF_Reserved22_SHIFT                  (22U)
/*! Reserved22 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved22(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved22_SHIFT)) & WUU_PF_Reserved22_MASK)

#define WUU_PF_WUF22_MASK                        (0x400000U)
#define WUU_PF_WUF22_SHIFT                       (22U)
/*! WUF22 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF22(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF22_SHIFT)) & WUU_PF_WUF22_MASK)

#define WUU_PF_Reserved23_MASK                   (0x800000U)
#define WUU_PF_Reserved23_SHIFT                  (23U)
/*! Reserved23 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved23(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved23_SHIFT)) & WUU_PF_Reserved23_MASK)

#define WUU_PF_WUF23_MASK                        (0x800000U)
#define WUU_PF_WUF23_SHIFT                       (23U)
/*! WUF23 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF23(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF23_SHIFT)) & WUU_PF_WUF23_MASK)

#define WUU_PF_Reserved24_MASK                   (0x1000000U)
#define WUU_PF_Reserved24_SHIFT                  (24U)
/*! Reserved24 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved24(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved24_SHIFT)) & WUU_PF_Reserved24_MASK)

#define WUU_PF_WUF24_MASK                        (0x1000000U)
#define WUU_PF_WUF24_SHIFT                       (24U)
/*! WUF24 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF24(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF24_SHIFT)) & WUU_PF_WUF24_MASK)

#define WUU_PF_Reserved25_MASK                   (0x2000000U)
#define WUU_PF_Reserved25_SHIFT                  (25U)
/*! Reserved25 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved25(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved25_SHIFT)) & WUU_PF_Reserved25_MASK)

#define WUU_PF_WUF25_MASK                        (0x2000000U)
#define WUU_PF_WUF25_SHIFT                       (25U)
/*! WUF25 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF25(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF25_SHIFT)) & WUU_PF_WUF25_MASK)

#define WUU_PF_Reserved26_MASK                   (0x4000000U)
#define WUU_PF_Reserved26_SHIFT                  (26U)
/*! Reserved26 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved26(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved26_SHIFT)) & WUU_PF_Reserved26_MASK)

#define WUU_PF_WUF26_MASK                        (0x4000000U)
#define WUU_PF_WUF26_SHIFT                       (26U)
/*! WUF26 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF26(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF26_SHIFT)) & WUU_PF_WUF26_MASK)

#define WUU_PF_Reserved27_MASK                   (0x8000000U)
#define WUU_PF_Reserved27_SHIFT                  (27U)
/*! Reserved27 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved27(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved27_SHIFT)) & WUU_PF_Reserved27_MASK)

#define WUU_PF_WUF27_MASK                        (0x8000000U)
#define WUU_PF_WUF27_SHIFT                       (27U)
/*! WUF27 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF27(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF27_SHIFT)) & WUU_PF_WUF27_MASK)

#define WUU_PF_Reserved28_MASK                   (0x10000000U)
#define WUU_PF_Reserved28_SHIFT                  (28U)
/*! Reserved28 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved28(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved28_SHIFT)) & WUU_PF_Reserved28_MASK)

#define WUU_PF_Reserved29_MASK                   (0x20000000U)
#define WUU_PF_Reserved29_SHIFT                  (29U)
/*! Reserved29 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved29(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved29_SHIFT)) & WUU_PF_Reserved29_MASK)

#define WUU_PF_Reserved30_MASK                   (0x40000000U)
#define WUU_PF_Reserved30_SHIFT                  (30U)
/*! Reserved30 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved30(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved30_SHIFT)) & WUU_PF_Reserved30_MASK)

#define WUU_PF_Reserved31_MASK                   (0x80000000U)
#define WUU_PF_Reserved31_SHIFT                  (31U)
/*! Reserved31 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PF_Reserved31(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved31_SHIFT)) & WUU_PF_Reserved31_MASK)
/*! @} */

/*! @name MF - Module Interrupt Flag */
/*! @{ */

#define WUU_MF_MWUF0_MASK                        (0x1U)
#define WUU_MF_MWUF0_SHIFT                       (0U)
/*! MWUF0 - Wakeup flag for module n
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_MF_MWUF0(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_MF_MWUF0_SHIFT)) & WUU_MF_MWUF0_MASK)

#define WUU_MF_MWUF1_MASK                        (0x2U)
#define WUU_MF_MWUF1_SHIFT                       (1U)
/*! MWUF1 - Wakeup flag for module n
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_MF_MWUF1(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_MF_MWUF1_SHIFT)) & WUU_MF_MWUF1_MASK)

#define WUU_MF_MWUF2_MASK                        (0x4U)
#define WUU_MF_MWUF2_SHIFT                       (2U)
/*! MWUF2 - Wakeup flag for module n
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_MF_MWUF2(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_MF_MWUF2_SHIFT)) & WUU_MF_MWUF2_MASK)

#define WUU_MF_MWUF3_MASK                        (0x8U)
#define WUU_MF_MWUF3_SHIFT                       (3U)
/*! MWUF3 - Wakeup flag for module n
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_MF_MWUF3(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_MF_MWUF3_SHIFT)) & WUU_MF_MWUF3_MASK)

#define WUU_MF_MWUF4_MASK                        (0x10U)
#define WUU_MF_MWUF4_SHIFT                       (4U)
/*! MWUF4 - Wakeup flag for module n
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_MF_MWUF4(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_MF_MWUF4_SHIFT)) & WUU_MF_MWUF4_MASK)

#define WUU_MF_MWUF5_MASK                        (0x20U)
#define WUU_MF_MWUF5_SHIFT                       (5U)
/*! MWUF5 - Wakeup flag for module n
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_MF_MWUF5(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_MF_MWUF5_SHIFT)) & WUU_MF_MWUF5_MASK)

#define WUU_MF_MWUF6_MASK                        (0x40U)
#define WUU_MF_MWUF6_SHIFT                       (6U)
/*! MWUF6 - Wakeup flag for module n
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_MF_MWUF6(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_MF_MWUF6_SHIFT)) & WUU_MF_MWUF6_MASK)

#define WUU_MF_MWUF7_MASK                        (0x80U)
#define WUU_MF_MWUF7_SHIFT                       (7U)
/*! MWUF7 - Wakeup flag for module n
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_MF_MWUF7(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_MF_MWUF7_SHIFT)) & WUU_MF_MWUF7_MASK)
/*! @} */

/*! @name FILT - Pin Filter */
/*! @{ */

#define WUU_FILT_FILTSEL1_MASK                   (0x1FU)
#define WUU_FILT_FILTSEL1_SHIFT                  (0U)
/*! FILTSEL1 - Filter 1 Pin Select
 *  0b00000..Select WUU_P0
 *  0b11111..Select WUU_P31
 */
#define WUU_FILT_FILTSEL1(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL1_SHIFT)) & WUU_FILT_FILTSEL1_MASK)

#define WUU_FILT_FILTE1_MASK                     (0x60U)
#define WUU_FILT_FILTE1_SHIFT                    (5U)
/*! FILTE1 - Filter 1 Enable
 *  0b00..Disable filter
 *  0b01..Enable filter. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a
 *        trigger request: Detect on high level
 *  0b10..Enable filter. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a
 *        trigger request: Detect on low level
 *  0b11..Enable filter. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_FILT_FILTE1(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE1_SHIFT)) & WUU_FILT_FILTE1_MASK)

#define WUU_FILT_FILTF1_MASK                     (0x80U)
#define WUU_FILT_FILTF1_SHIFT                    (7U)
/*! FILTF1 - Filter 1 Flag
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_FILT_FILTF1(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF1_SHIFT)) & WUU_FILT_FILTF1_MASK)

#define WUU_FILT_FILTSEL2_MASK                   (0x1F00U)
#define WUU_FILT_FILTSEL2_SHIFT                  (8U)
/*! FILTSEL2 - Filter 2 Pin Select
 *  0b00000..Select WUU_P0
 *  0b11111..Select WUU_P31
 */
#define WUU_FILT_FILTSEL2(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL2_SHIFT)) & WUU_FILT_FILTSEL2_MASK)

#define WUU_FILT_FILTE2_MASK                     (0x6000U)
#define WUU_FILT_FILTE2_SHIFT                    (13U)
/*! FILTE2 - Filter 2 Enable
 *  0b00..Disable filter
 *  0b01..Enable filter. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a
 *        trigger request: Detect on high level
 *  0b10..Enable filter. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a
 *        trigger request: Detect on low level
 *  0b11..Enable filter. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_FILT_FILTE2(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE2_SHIFT)) & WUU_FILT_FILTE2_MASK)

#define WUU_FILT_FILTF2_MASK                     (0x8000U)
#define WUU_FILT_FILTF2_SHIFT                    (15U)
/*! FILTF2 - Filter 2 Flag
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_FILT_FILTF2(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF2_SHIFT)) & WUU_FILT_FILTF2_MASK)

#define WUU_FILT_FILTSEL3_MASK                   (0x1F0000U)
#define WUU_FILT_FILTSEL3_SHIFT                  (16U)
/*! FILTSEL3 - Filter 3 Pin Select
 *  0b00000..Select WUU_P0
 *  0b11111..Select WUU_P31
 */
#define WUU_FILT_FILTSEL3(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL3_SHIFT)) & WUU_FILT_FILTSEL3_MASK)

#define WUU_FILT_FILTE3_MASK                     (0x600000U)
#define WUU_FILT_FILTE3_SHIFT                    (21U)
/*! FILTE3 - Filter 3 Enable
 *  0b00..Disable filter
 *  0b01..Enable filter. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a
 *        trigger request: Detect on high level
 *  0b10..Enable filter. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a
 *        trigger request: Detect on low level
 *  0b11..Enable filter. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_FILT_FILTE3(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE3_SHIFT)) & WUU_FILT_FILTE3_MASK)

#define WUU_FILT_FILTF3_MASK                     (0x800000U)
#define WUU_FILT_FILTF3_SHIFT                    (23U)
/*! FILTF3 - Filter 3 Flag
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_FILT_FILTF3(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF3_SHIFT)) & WUU_FILT_FILTF3_MASK)

#define WUU_FILT_FILTSEL4_MASK                   (0x1F000000U)
#define WUU_FILT_FILTSEL4_SHIFT                  (24U)
/*! FILTSEL4 - Filter 4 Pin Select
 *  0b00000..Select WUU_P0
 *  0b11111..Select WUU_P31
 */
#define WUU_FILT_FILTSEL4(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL4_SHIFT)) & WUU_FILT_FILTSEL4_MASK)

#define WUU_FILT_FILTE4_MASK                     (0x60000000U)
#define WUU_FILT_FILTE4_SHIFT                    (29U)
/*! FILTE4 - Filter 4 Enable
 *  0b00..Disable filter
 *  0b01..Enable filter. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a
 *        trigger request: Detect on high level
 *  0b10..Enable filter. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a
 *        trigger request: Detect on low level
 *  0b11..Enable filter. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_FILT_FILTE4(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE4_SHIFT)) & WUU_FILT_FILTE4_MASK)

#define WUU_FILT_FILTF4_MASK                     (0x80000000U)
#define WUU_FILT_FILTF4_SHIFT                    (31U)
/*! FILTF4 - Filter 4 Flag
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_FILT_FILTF4(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF4_SHIFT)) & WUU_FILT_FILTF4_MASK)
/*! @} */

/*! @name PDC1 - Pin DMA/Trigger Configuration 1 */
/*! @{ */

#define WUU_PDC1_WUPDC0_MASK                     (0x3U)
#define WUU_PDC1_WUPDC0_SHIFT                    (0U)
/*! WUPDC0 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC0(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC0_SHIFT)) & WUU_PDC1_WUPDC0_MASK)

#define WUU_PDC1_WUPDC1_MASK                     (0xCU)
#define WUU_PDC1_WUPDC1_SHIFT                    (2U)
/*! WUPDC1 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC1(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC1_SHIFT)) & WUU_PDC1_WUPDC1_MASK)

#define WUU_PDC1_WUPDC2_MASK                     (0x30U)
#define WUU_PDC1_WUPDC2_SHIFT                    (4U)
/*! WUPDC2 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC2(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC2_SHIFT)) & WUU_PDC1_WUPDC2_MASK)

#define WUU_PDC1_WUPDC3_MASK                     (0xC0U)
#define WUU_PDC1_WUPDC3_SHIFT                    (6U)
/*! WUPDC3 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC3(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC3_SHIFT)) & WUU_PDC1_WUPDC3_MASK)

#define WUU_PDC1_WUPDC4_MASK                     (0x300U)
#define WUU_PDC1_WUPDC4_SHIFT                    (8U)
/*! WUPDC4 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC4(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC4_SHIFT)) & WUU_PDC1_WUPDC4_MASK)

#define WUU_PDC1_WUPDC5_MASK                     (0xC00U)
#define WUU_PDC1_WUPDC5_SHIFT                    (10U)
/*! WUPDC5 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC5(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC5_SHIFT)) & WUU_PDC1_WUPDC5_MASK)

#define WUU_PDC1_WUPDC6_MASK                     (0x3000U)
#define WUU_PDC1_WUPDC6_SHIFT                    (12U)
/*! WUPDC6 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC6(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC6_SHIFT)) & WUU_PDC1_WUPDC6_MASK)

#define WUU_PDC1_WUPDC7_MASK                     (0xC000U)
#define WUU_PDC1_WUPDC7_SHIFT                    (14U)
/*! WUPDC7 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC7(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC7_SHIFT)) & WUU_PDC1_WUPDC7_MASK)

#define WUU_PDC1_WUPDC8_MASK                     (0x30000U)
#define WUU_PDC1_WUPDC8_SHIFT                    (16U)
/*! WUPDC8 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC8(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC8_SHIFT)) & WUU_PDC1_WUPDC8_MASK)

#define WUU_PDC1_WUPDC9_MASK                     (0xC0000U)
#define WUU_PDC1_WUPDC9_SHIFT                    (18U)
/*! WUPDC9 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC9(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC9_SHIFT)) & WUU_PDC1_WUPDC9_MASK)

#define WUU_PDC1_WUPDC10_MASK                    (0x300000U)
#define WUU_PDC1_WUPDC10_SHIFT                   (20U)
/*! WUPDC10 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC10(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC10_SHIFT)) & WUU_PDC1_WUPDC10_MASK)

#define WUU_PDC1_WUPDC11_MASK                    (0xC00000U)
#define WUU_PDC1_WUPDC11_SHIFT                   (22U)
/*! WUPDC11 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC11(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC11_SHIFT)) & WUU_PDC1_WUPDC11_MASK)

#define WUU_PDC1_WUPDC12_MASK                    (0x3000000U)
#define WUU_PDC1_WUPDC12_SHIFT                   (24U)
/*! WUPDC12 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC12(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC12_SHIFT)) & WUU_PDC1_WUPDC12_MASK)

#define WUU_PDC1_WUPDC13_MASK                    (0xC000000U)
#define WUU_PDC1_WUPDC13_SHIFT                   (26U)
/*! WUPDC13 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC13(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC13_SHIFT)) & WUU_PDC1_WUPDC13_MASK)

#define WUU_PDC1_WUPDC14_MASK                    (0x30000000U)
#define WUU_PDC1_WUPDC14_SHIFT                   (28U)
/*! WUPDC14 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC14(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC14_SHIFT)) & WUU_PDC1_WUPDC14_MASK)

#define WUU_PDC1_WUPDC15_MASK                    (0xC0000000U)
#define WUU_PDC1_WUPDC15_SHIFT                   (30U)
/*! WUPDC15 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC15(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC15_SHIFT)) & WUU_PDC1_WUPDC15_MASK)
/*! @} */

/*! @name PDC2 - Pin DMA/Trigger Configuration 2 */
/*! @{ */

#define WUU_PDC2_Reserved16_MASK                 (0x3U)
#define WUU_PDC2_Reserved16_SHIFT                (0U)
/*! Reserved16 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved16(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved16_SHIFT)) & WUU_PDC2_Reserved16_MASK)

#define WUU_PDC2_WUPDC16_MASK                    (0x3U)
#define WUU_PDC2_WUPDC16_SHIFT                   (0U)
/*! WUPDC16 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC16(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC16_SHIFT)) & WUU_PDC2_WUPDC16_MASK)

#define WUU_PDC2_Reserved17_MASK                 (0xCU)
#define WUU_PDC2_Reserved17_SHIFT                (2U)
/*! Reserved17 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved17(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved17_SHIFT)) & WUU_PDC2_Reserved17_MASK)

#define WUU_PDC2_WUPDC17_MASK                    (0xCU)
#define WUU_PDC2_WUPDC17_SHIFT                   (2U)
/*! WUPDC17 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC17(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC17_SHIFT)) & WUU_PDC2_WUPDC17_MASK)

#define WUU_PDC2_Reserved18_MASK                 (0x30U)
#define WUU_PDC2_Reserved18_SHIFT                (4U)
/*! Reserved18 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved18(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved18_SHIFT)) & WUU_PDC2_Reserved18_MASK)

#define WUU_PDC2_WUPDC18_MASK                    (0x30U)
#define WUU_PDC2_WUPDC18_SHIFT                   (4U)
/*! WUPDC18 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC18(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC18_SHIFT)) & WUU_PDC2_WUPDC18_MASK)

#define WUU_PDC2_Reserved19_MASK                 (0xC0U)
#define WUU_PDC2_Reserved19_SHIFT                (6U)
/*! Reserved19 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved19(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved19_SHIFT)) & WUU_PDC2_Reserved19_MASK)

#define WUU_PDC2_WUPDC19_MASK                    (0xC0U)
#define WUU_PDC2_WUPDC19_SHIFT                   (6U)
/*! WUPDC19 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC19(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC19_SHIFT)) & WUU_PDC2_WUPDC19_MASK)

#define WUU_PDC2_Reserved20_MASK                 (0x300U)
#define WUU_PDC2_Reserved20_SHIFT                (8U)
/*! Reserved20 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved20(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved20_SHIFT)) & WUU_PDC2_Reserved20_MASK)

#define WUU_PDC2_WUPDC20_MASK                    (0x300U)
#define WUU_PDC2_WUPDC20_SHIFT                   (8U)
/*! WUPDC20 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC20(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC20_SHIFT)) & WUU_PDC2_WUPDC20_MASK)

#define WUU_PDC2_Reserved21_MASK                 (0xC00U)
#define WUU_PDC2_Reserved21_SHIFT                (10U)
/*! Reserved21 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved21(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved21_SHIFT)) & WUU_PDC2_Reserved21_MASK)

#define WUU_PDC2_WUPDC21_MASK                    (0xC00U)
#define WUU_PDC2_WUPDC21_SHIFT                   (10U)
/*! WUPDC21 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC21(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC21_SHIFT)) & WUU_PDC2_WUPDC21_MASK)

#define WUU_PDC2_Reserved22_MASK                 (0x3000U)
#define WUU_PDC2_Reserved22_SHIFT                (12U)
/*! Reserved22 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved22(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved22_SHIFT)) & WUU_PDC2_Reserved22_MASK)

#define WUU_PDC2_WUPDC22_MASK                    (0x3000U)
#define WUU_PDC2_WUPDC22_SHIFT                   (12U)
/*! WUPDC22 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC22(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC22_SHIFT)) & WUU_PDC2_WUPDC22_MASK)

#define WUU_PDC2_Reserved23_MASK                 (0xC000U)
#define WUU_PDC2_Reserved23_SHIFT                (14U)
/*! Reserved23 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved23(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved23_SHIFT)) & WUU_PDC2_Reserved23_MASK)

#define WUU_PDC2_WUPDC23_MASK                    (0xC000U)
#define WUU_PDC2_WUPDC23_SHIFT                   (14U)
/*! WUPDC23 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC23(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC23_SHIFT)) & WUU_PDC2_WUPDC23_MASK)

#define WUU_PDC2_Reserved24_MASK                 (0x30000U)
#define WUU_PDC2_Reserved24_SHIFT                (16U)
/*! Reserved24 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved24(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved24_SHIFT)) & WUU_PDC2_Reserved24_MASK)

#define WUU_PDC2_WUPDC24_MASK                    (0x30000U)
#define WUU_PDC2_WUPDC24_SHIFT                   (16U)
/*! WUPDC24 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC24(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC24_SHIFT)) & WUU_PDC2_WUPDC24_MASK)

#define WUU_PDC2_Reserved25_MASK                 (0xC0000U)
#define WUU_PDC2_Reserved25_SHIFT                (18U)
/*! Reserved25 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved25(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved25_SHIFT)) & WUU_PDC2_Reserved25_MASK)

#define WUU_PDC2_WUPDC25_MASK                    (0xC0000U)
#define WUU_PDC2_WUPDC25_SHIFT                   (18U)
/*! WUPDC25 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC25(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC25_SHIFT)) & WUU_PDC2_WUPDC25_MASK)

#define WUU_PDC2_Reserved26_MASK                 (0x300000U)
#define WUU_PDC2_Reserved26_SHIFT                (20U)
/*! Reserved26 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved26(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved26_SHIFT)) & WUU_PDC2_Reserved26_MASK)

#define WUU_PDC2_WUPDC26_MASK                    (0x300000U)
#define WUU_PDC2_WUPDC26_SHIFT                   (20U)
/*! WUPDC26 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC26(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC26_SHIFT)) & WUU_PDC2_WUPDC26_MASK)

#define WUU_PDC2_Reserved27_MASK                 (0xC00000U)
#define WUU_PDC2_Reserved27_SHIFT                (22U)
/*! Reserved27 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved27(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved27_SHIFT)) & WUU_PDC2_Reserved27_MASK)

#define WUU_PDC2_WUPDC27_MASK                    (0xC00000U)
#define WUU_PDC2_WUPDC27_SHIFT                   (22U)
/*! WUPDC27 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC27(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC27_SHIFT)) & WUU_PDC2_WUPDC27_MASK)

#define WUU_PDC2_Reserved28_MASK                 (0x3000000U)
#define WUU_PDC2_Reserved28_SHIFT                (24U)
/*! Reserved28 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved28(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved28_SHIFT)) & WUU_PDC2_Reserved28_MASK)

#define WUU_PDC2_Reserved29_MASK                 (0xC000000U)
#define WUU_PDC2_Reserved29_SHIFT                (26U)
/*! Reserved29 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved29(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved29_SHIFT)) & WUU_PDC2_Reserved29_MASK)

#define WUU_PDC2_Reserved30_MASK                 (0x30000000U)
#define WUU_PDC2_Reserved30_SHIFT                (28U)
/*! Reserved30 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved30(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved30_SHIFT)) & WUU_PDC2_Reserved30_MASK)

#define WUU_PDC2_Reserved31_MASK                 (0xC0000000U)
#define WUU_PDC2_Reserved31_SHIFT                (30U)
/*! Reserved31 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PDC2_Reserved31(x)                   (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
/*! @} */

/*! @name FDC - Pin Filter DMA/Trigger Configuration */
/*! @{ */

#define WUU_FDC_FILTC1_MASK                      (0x3U)
#define WUU_FDC_FILTC1_SHIFT                     (0U)
/*! FILTC1 - Filter configuration for FILTn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_FDC_FILTC1(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC1_SHIFT)) & WUU_FDC_FILTC1_MASK)

#define WUU_FDC_FILTC2_MASK                      (0xCU)
#define WUU_FDC_FILTC2_SHIFT                     (2U)
/*! FILTC2 - Filter configuration for FILTn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_FDC_FILTC2(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC2_SHIFT)) & WUU_FDC_FILTC2_MASK)

#define WUU_FDC_FILTC3_MASK                      (0x30U)
#define WUU_FDC_FILTC3_SHIFT                     (4U)
/*! FILTC3 - Filter configuration for FILTn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_FDC_FILTC3(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC3_SHIFT)) & WUU_FDC_FILTC3_MASK)

#define WUU_FDC_FILTC4_MASK                      (0xC0U)
#define WUU_FDC_FILTC4_SHIFT                     (6U)
/*! FILTC4 - Filter configuration for FILTn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_FDC_FILTC4(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC4_SHIFT)) & WUU_FDC_FILTC4_MASK)
/*! @} */

/*! @name PMC - Pin Mode Configuration */
/*! @{ */

#define WUU_PMC_WUPMC0_MASK                      (0x1U)
#define WUU_PMC_WUPMC0_SHIFT                     (0U)
/*! WUPMC0 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC0(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC0_SHIFT)) & WUU_PMC_WUPMC0_MASK)

#define WUU_PMC_WUPMC1_MASK                      (0x2U)
#define WUU_PMC_WUPMC1_SHIFT                     (1U)
/*! WUPMC1 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC1(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC1_SHIFT)) & WUU_PMC_WUPMC1_MASK)

#define WUU_PMC_WUPMC2_MASK                      (0x4U)
#define WUU_PMC_WUPMC2_SHIFT                     (2U)
/*! WUPMC2 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC2(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC2_SHIFT)) & WUU_PMC_WUPMC2_MASK)

#define WUU_PMC_WUPMC3_MASK                      (0x8U)
#define WUU_PMC_WUPMC3_SHIFT                     (3U)
/*! WUPMC3 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC3(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC3_SHIFT)) & WUU_PMC_WUPMC3_MASK)

#define WUU_PMC_WUPMC4_MASK                      (0x10U)
#define WUU_PMC_WUPMC4_SHIFT                     (4U)
/*! WUPMC4 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC4(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC4_SHIFT)) & WUU_PMC_WUPMC4_MASK)

#define WUU_PMC_WUPMC5_MASK                      (0x20U)
#define WUU_PMC_WUPMC5_SHIFT                     (5U)
/*! WUPMC5 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC5(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC5_SHIFT)) & WUU_PMC_WUPMC5_MASK)

#define WUU_PMC_WUPMC6_MASK                      (0x40U)
#define WUU_PMC_WUPMC6_SHIFT                     (6U)
/*! WUPMC6 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC6(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC6_SHIFT)) & WUU_PMC_WUPMC6_MASK)

#define WUU_PMC_WUPMC7_MASK                      (0x80U)
#define WUU_PMC_WUPMC7_SHIFT                     (7U)
/*! WUPMC7 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC7(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC7_SHIFT)) & WUU_PMC_WUPMC7_MASK)

#define WUU_PMC_WUPMC8_MASK                      (0x100U)
#define WUU_PMC_WUPMC8_SHIFT                     (8U)
/*! WUPMC8 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC8(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC8_SHIFT)) & WUU_PMC_WUPMC8_MASK)

#define WUU_PMC_WUPMC9_MASK                      (0x200U)
#define WUU_PMC_WUPMC9_SHIFT                     (9U)
/*! WUPMC9 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC9(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC9_SHIFT)) & WUU_PMC_WUPMC9_MASK)

#define WUU_PMC_WUPMC10_MASK                     (0x400U)
#define WUU_PMC_WUPMC10_SHIFT                    (10U)
/*! WUPMC10 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC10(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC10_SHIFT)) & WUU_PMC_WUPMC10_MASK)

#define WUU_PMC_WUPMC11_MASK                     (0x800U)
#define WUU_PMC_WUPMC11_SHIFT                    (11U)
/*! WUPMC11 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC11(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC11_SHIFT)) & WUU_PMC_WUPMC11_MASK)

#define WUU_PMC_WUPMC12_MASK                     (0x1000U)
#define WUU_PMC_WUPMC12_SHIFT                    (12U)
/*! WUPMC12 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC12(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC12_SHIFT)) & WUU_PMC_WUPMC12_MASK)

#define WUU_PMC_WUPMC13_MASK                     (0x2000U)
#define WUU_PMC_WUPMC13_SHIFT                    (13U)
/*! WUPMC13 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC13(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC13_SHIFT)) & WUU_PMC_WUPMC13_MASK)

#define WUU_PMC_WUPMC14_MASK                     (0x4000U)
#define WUU_PMC_WUPMC14_SHIFT                    (14U)
/*! WUPMC14 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC14(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC14_SHIFT)) & WUU_PMC_WUPMC14_MASK)

#define WUU_PMC_WUPMC15_MASK                     (0x8000U)
#define WUU_PMC_WUPMC15_SHIFT                    (15U)
/*! WUPMC15 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC15(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC15_SHIFT)) & WUU_PMC_WUPMC15_MASK)

#define WUU_PMC_Reserved16_MASK                  (0x10000U)
#define WUU_PMC_Reserved16_SHIFT                 (16U)
/*! Reserved16 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved16(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved16_SHIFT)) & WUU_PMC_Reserved16_MASK)

#define WUU_PMC_WUPMC16_MASK                     (0x10000U)
#define WUU_PMC_WUPMC16_SHIFT                    (16U)
/*! WUPMC16 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC16(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC16_SHIFT)) & WUU_PMC_WUPMC16_MASK)

#define WUU_PMC_Reserved17_MASK                  (0x20000U)
#define WUU_PMC_Reserved17_SHIFT                 (17U)
/*! Reserved17 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved17(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved17_SHIFT)) & WUU_PMC_Reserved17_MASK)

#define WUU_PMC_WUPMC17_MASK                     (0x20000U)
#define WUU_PMC_WUPMC17_SHIFT                    (17U)
/*! WUPMC17 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC17(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC17_SHIFT)) & WUU_PMC_WUPMC17_MASK)

#define WUU_PMC_Reserved18_MASK                  (0x40000U)
#define WUU_PMC_Reserved18_SHIFT                 (18U)
/*! Reserved18 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved18(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved18_SHIFT)) & WUU_PMC_Reserved18_MASK)

#define WUU_PMC_WUPMC18_MASK                     (0x40000U)
#define WUU_PMC_WUPMC18_SHIFT                    (18U)
/*! WUPMC18 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC18(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC18_SHIFT)) & WUU_PMC_WUPMC18_MASK)

#define WUU_PMC_Reserved19_MASK                  (0x80000U)
#define WUU_PMC_Reserved19_SHIFT                 (19U)
/*! Reserved19 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved19(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved19_SHIFT)) & WUU_PMC_Reserved19_MASK)

#define WUU_PMC_WUPMC19_MASK                     (0x80000U)
#define WUU_PMC_WUPMC19_SHIFT                    (19U)
/*! WUPMC19 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC19(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC19_SHIFT)) & WUU_PMC_WUPMC19_MASK)

#define WUU_PMC_Reserved20_MASK                  (0x100000U)
#define WUU_PMC_Reserved20_SHIFT                 (20U)
/*! Reserved20 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved20(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved20_SHIFT)) & WUU_PMC_Reserved20_MASK)

#define WUU_PMC_WUPMC20_MASK                     (0x100000U)
#define WUU_PMC_WUPMC20_SHIFT                    (20U)
/*! WUPMC20 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC20(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC20_SHIFT)) & WUU_PMC_WUPMC20_MASK)

#define WUU_PMC_Reserved21_MASK                  (0x200000U)
#define WUU_PMC_Reserved21_SHIFT                 (21U)
/*! Reserved21 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved21(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved21_SHIFT)) & WUU_PMC_Reserved21_MASK)

#define WUU_PMC_WUPMC21_MASK                     (0x200000U)
#define WUU_PMC_WUPMC21_SHIFT                    (21U)
/*! WUPMC21 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC21(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC21_SHIFT)) & WUU_PMC_WUPMC21_MASK)

#define WUU_PMC_Reserved22_MASK                  (0x400000U)
#define WUU_PMC_Reserved22_SHIFT                 (22U)
/*! Reserved22 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved22(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved22_SHIFT)) & WUU_PMC_Reserved22_MASK)

#define WUU_PMC_WUPMC22_MASK                     (0x400000U)
#define WUU_PMC_WUPMC22_SHIFT                    (22U)
/*! WUPMC22 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC22(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC22_SHIFT)) & WUU_PMC_WUPMC22_MASK)

#define WUU_PMC_Reserved23_MASK                  (0x800000U)
#define WUU_PMC_Reserved23_SHIFT                 (23U)
/*! Reserved23 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved23(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved23_SHIFT)) & WUU_PMC_Reserved23_MASK)

#define WUU_PMC_WUPMC23_MASK                     (0x800000U)
#define WUU_PMC_WUPMC23_SHIFT                    (23U)
/*! WUPMC23 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC23(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC23_SHIFT)) & WUU_PMC_WUPMC23_MASK)

#define WUU_PMC_Reserved24_MASK                  (0x1000000U)
#define WUU_PMC_Reserved24_SHIFT                 (24U)
/*! Reserved24 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved24(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved24_SHIFT)) & WUU_PMC_Reserved24_MASK)

#define WUU_PMC_WUPMC24_MASK                     (0x1000000U)
#define WUU_PMC_WUPMC24_SHIFT                    (24U)
/*! WUPMC24 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC24(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC24_SHIFT)) & WUU_PMC_WUPMC24_MASK)

#define WUU_PMC_Reserved25_MASK                  (0x2000000U)
#define WUU_PMC_Reserved25_SHIFT                 (25U)
/*! Reserved25 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved25(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved25_SHIFT)) & WUU_PMC_Reserved25_MASK)

#define WUU_PMC_WUPMC25_MASK                     (0x2000000U)
#define WUU_PMC_WUPMC25_SHIFT                    (25U)
/*! WUPMC25 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC25(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC25_SHIFT)) & WUU_PMC_WUPMC25_MASK)

#define WUU_PMC_Reserved26_MASK                  (0x4000000U)
#define WUU_PMC_Reserved26_SHIFT                 (26U)
/*! Reserved26 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved26(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved26_SHIFT)) & WUU_PMC_Reserved26_MASK)

#define WUU_PMC_WUPMC26_MASK                     (0x4000000U)
#define WUU_PMC_WUPMC26_SHIFT                    (26U)
/*! WUPMC26 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC26(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC26_SHIFT)) & WUU_PMC_WUPMC26_MASK)

#define WUU_PMC_Reserved27_MASK                  (0x8000000U)
#define WUU_PMC_Reserved27_SHIFT                 (27U)
/*! Reserved27 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved27(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved27_SHIFT)) & WUU_PMC_Reserved27_MASK)

#define WUU_PMC_WUPMC27_MASK                     (0x8000000U)
#define WUU_PMC_WUPMC27_SHIFT                    (27U)
/*! WUPMC27 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during Power Down/Deep Power Down mode. Software can modify the corresponding fields within
 *       the Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC27(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC27_SHIFT)) & WUU_PMC_WUPMC27_MASK)

#define WUU_PMC_Reserved28_MASK                  (0x10000000U)
#define WUU_PMC_Reserved28_SHIFT                 (28U)
/*! Reserved28 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved28(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved28_SHIFT)) & WUU_PMC_Reserved28_MASK)

#define WUU_PMC_Reserved29_MASK                  (0x20000000U)
#define WUU_PMC_Reserved29_SHIFT                 (29U)
/*! Reserved29 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved29(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved29_SHIFT)) & WUU_PMC_Reserved29_MASK)

#define WUU_PMC_Reserved30_MASK                  (0x40000000U)
#define WUU_PMC_Reserved30_SHIFT                 (30U)
/*! Reserved30 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved30(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved30_SHIFT)) & WUU_PMC_Reserved30_MASK)

#define WUU_PMC_Reserved31_MASK                  (0x80000000U)
#define WUU_PMC_Reserved31_SHIFT                 (31U)
/*! Reserved31 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define WUU_PMC_Reserved31(x)                    (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved31_SHIFT)) & WUU_PMC_Reserved31_MASK)
/*! @} */

/*! @name FMC - Pin Filter Mode Configuration */
/*! @{ */

#define WUU_FMC_FILTM1_MASK                      (0x1U)
#define WUU_FMC_FILTM1_SHIFT                     (0U)
/*! FILTM1 - Filter Mode for FILTn
 *  0b0..Active only during Power Down/Deep Power Down mode
 *  0b1..Active during all power modes
 */
#define WUU_FMC_FILTM1(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM1_SHIFT)) & WUU_FMC_FILTM1_MASK)

#define WUU_FMC_FILTM2_MASK                      (0x2U)
#define WUU_FMC_FILTM2_SHIFT                     (1U)
/*! FILTM2 - Filter Mode for FILTn
 *  0b0..Active only during Power Down/Deep Power Down mode
 *  0b1..Active during all power modes
 */
#define WUU_FMC_FILTM2(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM2_SHIFT)) & WUU_FMC_FILTM2_MASK)

#define WUU_FMC_FILTM3_MASK                      (0x4U)
#define WUU_FMC_FILTM3_SHIFT                     (2U)
/*! FILTM3 - Filter Mode for FILTn
 *  0b0..Active only during Power Down/Deep Power Down mode
 *  0b1..Active during all power modes
 */
#define WUU_FMC_FILTM3(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM3_SHIFT)) & WUU_FMC_FILTM3_MASK)

#define WUU_FMC_FILTM4_MASK                      (0x8U)
#define WUU_FMC_FILTM4_SHIFT                     (3U)
/*! FILTM4 - Filter Mode for FILTn
 *  0b0..Active only during Power Down/Deep Power Down mode
 *  0b1..Active during all power modes
 */
#define WUU_FMC_FILTM4(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM4_SHIFT)) & WUU_FMC_FILTM4_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group WUU_Register_Masks */


/* WUU - Peripheral instance base addresses */
/** Peripheral WUU0 base address */
#define WUU0_BASE                                (0x28028000u)
/** Peripheral WUU0 base pointer */
#define WUU0                                     ((WUU_Type *)WUU0_BASE)
/** Peripheral WUU1 base address */
#define WUU1_BASE                                (0x29260000u)
/** Peripheral WUU1 base pointer */
#define WUU1                                     ((WUU_Type *)WUU1_BASE)
/** Array initializer of WUU peripheral base addresses */
#define WUU_BASE_ADDRS                           { WUU0_BASE, WUU1_BASE }
/** Array initializer of WUU peripheral base pointers */
#define WUU_BASE_PTRS                            { WUU0, WUU1 }

/*!
 * @}
 */ /* end of group WUU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- XRDC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XRDC_Peripheral_Access_Layer XRDC Peripheral Access Layer
 * @{
 */

/** XRDC - Register Layout Typedef */
typedef struct {
  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
       uint8_t RESERVED_0[236];
  __I  uint32_t HWCFG0;                            /**< Hardware Configuration Register 0, offset: 0xF0 */
  __I  uint32_t HWCFG1;                            /**< Hardware Configuration Register 1, offset: 0xF4 */
  __I  uint32_t HWCFG2;                            /**< Hardware Configuration Register 2, offset: 0xF8 */
  __I  uint32_t HWCFG3;                            /**< Hardware Configuration Register 3, offset: 0xFC */
  __I  uint8_t MDACFG[17];                         /**< Master Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 */
       uint8_t RESERVED_1[47];
  __I  uint8_t MRCFG[13];                          /**< Memory Region Configuration Register, array offset: 0x140, array step: 0x1 */
       uint8_t RESERVED_2[175];
  __IO uint32_t FDID;                              /**< Fault Domain ID, offset: 0x1FC */
  __I  uint32_t DERRLOC[8];                        /**< Domain Error Location Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_3[480];
  __I  uint32_t DERR_W0_0;                         /**< Domain Error Word0 Register, offset: 0x400 */
  __I  uint32_t DERR_W1_0;                         /**< Domain Error Word1 Register, offset: 0x404 */
       uint8_t RESERVED_4[4];
  __O  uint32_t DERR_W3_0;                         /**< Domain Error Word3 Register, offset: 0x40C */
  __I  uint32_t DERR_W0_1;                         /**< Domain Error Word0 Register, offset: 0x410 */
  __I  uint32_t DERR_W1_1;                         /**< Domain Error Word1 Register, offset: 0x414 */
       uint8_t RESERVED_5[4];
  __O  uint32_t DERR_W3_1;                         /**< Domain Error Word3 Register, offset: 0x41C */
  __I  uint32_t DERR_W0_2;                         /**< Domain Error Word0 Register, offset: 0x420 */
  __I  uint32_t DERR_W1_2;                         /**< Domain Error Word1 Register, offset: 0x424 */
       uint8_t RESERVED_6[4];
  __O  uint32_t DERR_W3_2;                         /**< Domain Error Word3 Register, offset: 0x42C */
  __I  uint32_t DERR_W0_3;                         /**< Domain Error Word0 Register, offset: 0x430 */
  __I  uint32_t DERR_W1_3;                         /**< Domain Error Word1 Register, offset: 0x434 */
       uint8_t RESERVED_7[4];
  __O  uint32_t DERR_W3_3;                         /**< Domain Error Word3 Register, offset: 0x43C */
  __I  uint32_t DERR_W0_4;                         /**< Domain Error Word0 Register, offset: 0x440 */
  __I  uint32_t DERR_W1_4;                         /**< Domain Error Word1 Register, offset: 0x444 */
       uint8_t RESERVED_8[4];
  __O  uint32_t DERR_W3_4;                         /**< Domain Error Word3 Register, offset: 0x44C */
  __I  uint32_t DERR_W0_5;                         /**< Domain Error Word0 Register, offset: 0x450 */
  __I  uint32_t DERR_W1_5;                         /**< Domain Error Word1 Register, offset: 0x454 */
       uint8_t RESERVED_9[4];
  __O  uint32_t DERR_W3_5;                         /**< Domain Error Word3 Register, offset: 0x45C */
  __I  uint32_t DERR_W0_6;                         /**< Domain Error Word0 Register, offset: 0x460 */
  __I  uint32_t DERR_W1_6;                         /**< Domain Error Word1 Register, offset: 0x464 */
       uint8_t RESERVED_10[4];
  __O  uint32_t DERR_W3_6;                         /**< Domain Error Word3 Register, offset: 0x46C */
  __I  uint32_t DERR_W0_7;                         /**< Domain Error Word0 Register, offset: 0x470 */
  __I  uint32_t DERR_W1_7;                         /**< Domain Error Word1 Register, offset: 0x474 */
       uint8_t RESERVED_11[4];
  __O  uint32_t DERR_W3_7;                         /**< Domain Error Word3 Register, offset: 0x47C */
  __I  uint32_t DERR_W0_8;                         /**< Domain Error Word0 Register, offset: 0x480 */
  __I  uint32_t DERR_W1_8;                         /**< Domain Error Word1 Register, offset: 0x484 */
       uint8_t RESERVED_12[4];
  __O  uint32_t DERR_W3_8;                         /**< Domain Error Word3 Register, offset: 0x48C */
  __I  uint32_t DERR_W0_9;                         /**< Domain Error Word0 Register, offset: 0x490 */
  __I  uint32_t DERR_W1_9;                         /**< Domain Error Word1 Register, offset: 0x494 */
       uint8_t RESERVED_13[4];
  __O  uint32_t DERR_W3_9;                         /**< Domain Error Word3 Register, offset: 0x49C */
  __I  uint32_t DERR_W0_10;                        /**< Domain Error Word0 Register, offset: 0x4A0 */
  __I  uint32_t DERR_W1_10;                        /**< Domain Error Word1 Register, offset: 0x4A4 */
       uint8_t RESERVED_14[4];
  __O  uint32_t DERR_W3_10;                        /**< Domain Error Word3 Register, offset: 0x4AC */
  __I  uint32_t DERR_W0_11;                        /**< Domain Error Word0 Register, offset: 0x4B0 */
  __I  uint32_t DERR_W1_11;                        /**< Domain Error Word1 Register, offset: 0x4B4 */
       uint8_t RESERVED_15[4];
  __O  uint32_t DERR_W3_11;                        /**< Domain Error Word3 Register, offset: 0x4BC */
  __I  uint32_t DERR_W0_12;                        /**< Domain Error Word0 Register, offset: 0x4C0 */
  __I  uint32_t DERR_W1_12;                        /**< Domain Error Word1 Register, offset: 0x4C4 */
       uint8_t RESERVED_16[4];
  __O  uint32_t DERR_W3_12;                        /**< Domain Error Word3 Register, offset: 0x4CC */
       uint8_t RESERVED_17[48];
  __I  uint32_t DERR_W0_16;                        /**< Domain Error Word0 Register, offset: 0x500 */
  __I  uint32_t DERR_W1_16;                        /**< Domain Error Word1 Register, offset: 0x504 */
       uint8_t RESERVED_18[4];
  __O  uint32_t DERR_W3_16;                        /**< Domain Error Word3 Register, offset: 0x50C */
  __I  uint32_t DERR_W0_17;                        /**< Domain Error Word0 Register, offset: 0x510 */
  __I  uint32_t DERR_W1_17;                        /**< Domain Error Word1 Register, offset: 0x514 */
       uint8_t RESERVED_19[4];
  __O  uint32_t DERR_W3_17;                        /**< Domain Error Word3 Register, offset: 0x51C */
  __I  uint32_t DERR_W0_18;                        /**< Domain Error Word0 Register, offset: 0x520 */
  __I  uint32_t DERR_W1_18;                        /**< Domain Error Word1 Register, offset: 0x524 */
       uint8_t RESERVED_20[4];
  __O  uint32_t DERR_W3_18;                        /**< Domain Error Word3 Register, offset: 0x52C */
       uint8_t RESERVED_21[16];
  __I  uint32_t DERR_W0_20;                        /**< Domain Error Word0 Register, offset: 0x540 */
  __I  uint32_t DERR_W1_20;                        /**< Domain Error Word1 Register, offset: 0x544 */
       uint8_t RESERVED_22[4];
  __O  uint32_t DERR_W3_20;                        /**< Domain Error Word3 Register, offset: 0x54C */
  __I  uint32_t DERR_W0_21;                        /**< Domain Error Word0 Register, offset: 0x550 */
  __I  uint32_t DERR_W1_21;                        /**< Domain Error Word1 Register, offset: 0x554 */
       uint8_t RESERVED_23[4];
  __O  uint32_t DERR_W3_21;                        /**< Domain Error Word3 Register, offset: 0x55C */
  __I  uint32_t DERR_W0_22;                        /**< Domain Error Word0 Register, offset: 0x560 */
  __I  uint32_t DERR_W1_22;                        /**< Domain Error Word1 Register, offset: 0x564 */
       uint8_t RESERVED_24[4];
  __O  uint32_t DERR_W3_22;                        /**< Domain Error Word3 Register, offset: 0x56C */
       uint8_t RESERVED_25[400];
  __IO uint32_t PID0;                              /**< Process Identifier, offset: 0x700 */
       uint8_t RESERVED_26[252];
  __IO uint32_t MDA_W0_0_DFMT0;                    /**< Master Domain Assignment, offset: 0x800 */
  __IO uint32_t MDA_W1_0_DFMT0;                    /**< Master Domain Assignment, offset: 0x804 */
       uint8_t RESERVED_27[24];
  __IO uint32_t MDA_W0_1_DFMT1;                    /**< Master Domain Assignment, offset: 0x820 */
       uint8_t RESERVED_28[28];
  __IO uint32_t MDA_W0_2_DFMT1;                    /**< Master Domain Assignment, offset: 0x840 */
       uint8_t RESERVED_29[28];
  __IO uint32_t MDA_W0_3_DFMT1;                    /**< Master Domain Assignment, offset: 0x860 */
       uint8_t RESERVED_30[28];
  __IO uint32_t MDA_W0_4_DFMT1;                    /**< Master Domain Assignment, offset: 0x880 */
       uint8_t RESERVED_31[28];
  __IO uint32_t MDA_W0_5_DFMT1;                    /**< Master Domain Assignment, offset: 0x8A0 */
       uint8_t RESERVED_32[28];
  __IO uint32_t MDA_W0_6_DFMT1;                    /**< Master Domain Assignment, offset: 0x8C0 */
       uint8_t RESERVED_33[28];
  __IO uint32_t MDA_W0_7_DFMT1;                    /**< Master Domain Assignment, offset: 0x8E0 */
       uint8_t RESERVED_34[28];
  __IO uint32_t MDA_W0_8_DFMT1;                    /**< Master Domain Assignment, offset: 0x900 */
       uint8_t RESERVED_35[28];
  __IO uint32_t MDA_W0_9_DFMT1;                    /**< Master Domain Assignment, offset: 0x920 */
       uint8_t RESERVED_36[28];
  __IO uint32_t MDA_W0_10_DFMT1;                   /**< Master Domain Assignment, offset: 0x940 */
       uint8_t RESERVED_37[28];
  __IO uint32_t MDA_W0_11_DFMT1;                   /**< Master Domain Assignment, offset: 0x960 */
       uint8_t RESERVED_38[28];
  __IO uint32_t MDA_W0_12_DFMT1;                   /**< Master Domain Assignment, offset: 0x980 */
       uint8_t RESERVED_39[28];
  __IO uint32_t MDA_W0_13_DFMT1;                   /**< Master Domain Assignment, offset: 0x9A0 */
       uint8_t RESERVED_40[28];
  __IO uint32_t MDA_W0_14_DFMT1;                   /**< Master Domain Assignment, offset: 0x9C0 */
       uint8_t RESERVED_41[28];
  __IO uint32_t MDA_W0_15_DFMT1;                   /**< Master Domain Assignment, offset: 0x9E0 */
       uint8_t RESERVED_42[28];
  __IO uint32_t MDA_W0_16_DFMT1;                   /**< Master Domain Assignment, offset: 0xA00 */
       uint8_t RESERVED_43[1532];
  __IO uint32_t PDAC_W0_0_0;                       /**< Peripheral Domain Access Control, offset: 0x1000 */
  __IO uint32_t PDAC_W1_0_0;                       /**< Peripheral Domain Access Control, offset: 0x1004 */
  __IO uint32_t PDAC_W0_0_1;                       /**< Peripheral Domain Access Control, offset: 0x1008 */
  __IO uint32_t PDAC_W1_0_1;                       /**< Peripheral Domain Access Control, offset: 0x100C */
  __IO uint32_t PDAC_W0_0_2;                       /**< Peripheral Domain Access Control, offset: 0x1010 */
  __IO uint32_t PDAC_W1_0_2;                       /**< Peripheral Domain Access Control, offset: 0x1014 */
  __IO uint32_t PDAC_W0_0_3;                       /**< Peripheral Domain Access Control, offset: 0x1018 */
  __IO uint32_t PDAC_W1_0_3;                       /**< Peripheral Domain Access Control, offset: 0x101C */
  __IO uint32_t PDAC_W0_0_4;                       /**< Peripheral Domain Access Control, offset: 0x1020 */
  __IO uint32_t PDAC_W1_0_4;                       /**< Peripheral Domain Access Control, offset: 0x1024 */
  __IO uint32_t PDAC_W0_0_5;                       /**< Peripheral Domain Access Control, offset: 0x1028 */
  __IO uint32_t PDAC_W1_0_5;                       /**< Peripheral Domain Access Control, offset: 0x102C */
  __IO uint32_t PDAC_W0_0_6;                       /**< Peripheral Domain Access Control, offset: 0x1030 */
  __IO uint32_t PDAC_W1_0_6;                       /**< Peripheral Domain Access Control, offset: 0x1034 */
  __IO uint32_t PDAC_W0_0_7;                       /**< Peripheral Domain Access Control, offset: 0x1038 */
  __IO uint32_t PDAC_W1_0_7;                       /**< Peripheral Domain Access Control, offset: 0x103C */
  __IO uint32_t PDAC_W0_0_8;                       /**< Peripheral Domain Access Control, offset: 0x1040 */
  __IO uint32_t PDAC_W1_0_8;                       /**< Peripheral Domain Access Control, offset: 0x1044 */
  __IO uint32_t PDAC_W0_0_9;                       /**< Peripheral Domain Access Control, offset: 0x1048 */
  __IO uint32_t PDAC_W1_0_9;                       /**< Peripheral Domain Access Control, offset: 0x104C */
  __IO uint32_t PDAC_W0_0_10;                      /**< Peripheral Domain Access Control, offset: 0x1050 */
  __IO uint32_t PDAC_W1_0_10;                      /**< Peripheral Domain Access Control, offset: 0x1054 */
  __IO uint32_t PDAC_W0_0_11;                      /**< Peripheral Domain Access Control, offset: 0x1058 */
  __IO uint32_t PDAC_W1_0_11;                      /**< Peripheral Domain Access Control, offset: 0x105C */
  __IO uint32_t PDAC_W0_0_12;                      /**< Peripheral Domain Access Control, offset: 0x1060 */
  __IO uint32_t PDAC_W1_0_12;                      /**< Peripheral Domain Access Control, offset: 0x1064 */
  __IO uint32_t PDAC_W0_0_13;                      /**< Peripheral Domain Access Control, offset: 0x1068 */
  __IO uint32_t PDAC_W1_0_13;                      /**< Peripheral Domain Access Control, offset: 0x106C */
  __IO uint32_t PDAC_W0_0_14;                      /**< Peripheral Domain Access Control, offset: 0x1070 */
  __IO uint32_t PDAC_W1_0_14;                      /**< Peripheral Domain Access Control, offset: 0x1074 */
  __IO uint32_t PDAC_W0_0_15;                      /**< Peripheral Domain Access Control, offset: 0x1078 */
  __IO uint32_t PDAC_W1_0_15;                      /**< Peripheral Domain Access Control, offset: 0x107C */
  __IO uint32_t PDAC_W0_0_16;                      /**< Peripheral Domain Access Control, offset: 0x1080 */
  __IO uint32_t PDAC_W1_0_16;                      /**< Peripheral Domain Access Control, offset: 0x1084 */
  __IO uint32_t PDAC_W0_0_17;                      /**< Peripheral Domain Access Control, offset: 0x1088 */
  __IO uint32_t PDAC_W1_0_17;                      /**< Peripheral Domain Access Control, offset: 0x108C */
  __IO uint32_t PDAC_W0_0_18;                      /**< Peripheral Domain Access Control, offset: 0x1090 */
  __IO uint32_t PDAC_W1_0_18;                      /**< Peripheral Domain Access Control, offset: 0x1094 */
  __IO uint32_t PDAC_W0_0_19;                      /**< Peripheral Domain Access Control, offset: 0x1098 */
  __IO uint32_t PDAC_W1_0_19;                      /**< Peripheral Domain Access Control, offset: 0x109C */
  __IO uint32_t PDAC_W0_0_20;                      /**< Peripheral Domain Access Control, offset: 0x10A0 */
  __IO uint32_t PDAC_W1_0_20;                      /**< Peripheral Domain Access Control, offset: 0x10A4 */
  __IO uint32_t PDAC_W0_0_21;                      /**< Peripheral Domain Access Control, offset: 0x10A8 */
  __IO uint32_t PDAC_W1_0_21;                      /**< Peripheral Domain Access Control, offset: 0x10AC */
  __IO uint32_t PDAC_W0_0_22;                      /**< Peripheral Domain Access Control, offset: 0x10B0 */
  __IO uint32_t PDAC_W1_0_22;                      /**< Peripheral Domain Access Control, offset: 0x10B4 */
  __IO uint32_t PDAC_W0_0_23;                      /**< Peripheral Domain Access Control, offset: 0x10B8 */
  __IO uint32_t PDAC_W1_0_23;                      /**< Peripheral Domain Access Control, offset: 0x10BC */
  __IO uint32_t PDAC_W0_0_24;                      /**< Peripheral Domain Access Control, offset: 0x10C0 */
  __IO uint32_t PDAC_W1_0_24;                      /**< Peripheral Domain Access Control, offset: 0x10C4 */
  __IO uint32_t PDAC_W0_0_25;                      /**< Peripheral Domain Access Control, offset: 0x10C8 */
  __IO uint32_t PDAC_W1_0_25;                      /**< Peripheral Domain Access Control, offset: 0x10CC */
  __IO uint32_t PDAC_W0_0_26;                      /**< Peripheral Domain Access Control, offset: 0x10D0 */
  __IO uint32_t PDAC_W1_0_26;                      /**< Peripheral Domain Access Control, offset: 0x10D4 */
  __IO uint32_t PDAC_W0_0_27;                      /**< Peripheral Domain Access Control, offset: 0x10D8 */
  __IO uint32_t PDAC_W1_0_27;                      /**< Peripheral Domain Access Control, offset: 0x10DC */
  __IO uint32_t PDAC_W0_0_28;                      /**< Peripheral Domain Access Control, offset: 0x10E0 */
  __IO uint32_t PDAC_W1_0_28;                      /**< Peripheral Domain Access Control, offset: 0x10E4 */
  __IO uint32_t PDAC_W0_0_29;                      /**< Peripheral Domain Access Control, offset: 0x10E8 */
  __IO uint32_t PDAC_W1_0_29;                      /**< Peripheral Domain Access Control, offset: 0x10EC */
  __IO uint32_t PDAC_W0_0_30;                      /**< Peripheral Domain Access Control, offset: 0x10F0 */
  __IO uint32_t PDAC_W1_0_30;                      /**< Peripheral Domain Access Control, offset: 0x10F4 */
  __IO uint32_t PDAC_W0_0_31;                      /**< Peripheral Domain Access Control, offset: 0x10F8 */
  __IO uint32_t PDAC_W1_0_31;                      /**< Peripheral Domain Access Control, offset: 0x10FC */
  __IO uint32_t PDAC_W0_0_32;                      /**< Peripheral Domain Access Control, offset: 0x1100 */
  __IO uint32_t PDAC_W1_0_32;                      /**< Peripheral Domain Access Control, offset: 0x1104 */
  __IO uint32_t PDAC_W0_0_33;                      /**< Peripheral Domain Access Control, offset: 0x1108 */
  __IO uint32_t PDAC_W1_0_33;                      /**< Peripheral Domain Access Control, offset: 0x110C */
  __IO uint32_t PDAC_W0_0_34;                      /**< Peripheral Domain Access Control, offset: 0x1110 */
  __IO uint32_t PDAC_W1_0_34;                      /**< Peripheral Domain Access Control, offset: 0x1114 */
  __IO uint32_t PDAC_W0_0_35;                      /**< Peripheral Domain Access Control, offset: 0x1118 */
  __IO uint32_t PDAC_W1_0_35;                      /**< Peripheral Domain Access Control, offset: 0x111C */
  __IO uint32_t PDAC_W0_0_36;                      /**< Peripheral Domain Access Control, offset: 0x1120 */
  __IO uint32_t PDAC_W1_0_36;                      /**< Peripheral Domain Access Control, offset: 0x1124 */
  __IO uint32_t PDAC_W0_0_37;                      /**< Peripheral Domain Access Control, offset: 0x1128 */
  __IO uint32_t PDAC_W1_0_37;                      /**< Peripheral Domain Access Control, offset: 0x112C */
  __IO uint32_t PDAC_W0_0_38;                      /**< Peripheral Domain Access Control, offset: 0x1130 */
  __IO uint32_t PDAC_W1_0_38;                      /**< Peripheral Domain Access Control, offset: 0x1134 */
  __IO uint32_t PDAC_W0_0_39;                      /**< Peripheral Domain Access Control, offset: 0x1138 */
  __IO uint32_t PDAC_W1_0_39;                      /**< Peripheral Domain Access Control, offset: 0x113C */
  __IO uint32_t PDAC_W0_0_40;                      /**< Peripheral Domain Access Control, offset: 0x1140 */
  __IO uint32_t PDAC_W1_0_40;                      /**< Peripheral Domain Access Control, offset: 0x1144 */
  __IO uint32_t PDAC_W0_0_41;                      /**< Peripheral Domain Access Control, offset: 0x1148 */
  __IO uint32_t PDAC_W1_0_41;                      /**< Peripheral Domain Access Control, offset: 0x114C */
  __IO uint32_t PDAC_W0_0_42;                      /**< Peripheral Domain Access Control, offset: 0x1150 */
  __IO uint32_t PDAC_W1_0_42;                      /**< Peripheral Domain Access Control, offset: 0x1154 */
  __IO uint32_t PDAC_W0_0_43;                      /**< Peripheral Domain Access Control, offset: 0x1158 */
  __IO uint32_t PDAC_W1_0_43;                      /**< Peripheral Domain Access Control, offset: 0x115C */
  __IO uint32_t PDAC_W0_0_44;                      /**< Peripheral Domain Access Control, offset: 0x1160 */
  __IO uint32_t PDAC_W1_0_44;                      /**< Peripheral Domain Access Control, offset: 0x1164 */
  __IO uint32_t PDAC_W0_0_45;                      /**< Peripheral Domain Access Control, offset: 0x1168 */
  __IO uint32_t PDAC_W1_0_45;                      /**< Peripheral Domain Access Control, offset: 0x116C */
  __IO uint32_t PDAC_W0_0_46;                      /**< Peripheral Domain Access Control, offset: 0x1170 */
  __IO uint32_t PDAC_W1_0_46;                      /**< Peripheral Domain Access Control, offset: 0x1174 */
  __IO uint32_t PDAC_W0_0_47;                      /**< Peripheral Domain Access Control, offset: 0x1178 */
  __IO uint32_t PDAC_W1_0_47;                      /**< Peripheral Domain Access Control, offset: 0x117C */
  __IO uint32_t PDAC_W0_0_48;                      /**< Peripheral Domain Access Control, offset: 0x1180 */
  __IO uint32_t PDAC_W1_0_48;                      /**< Peripheral Domain Access Control, offset: 0x1184 */
  __IO uint32_t PDAC_W0_0_49;                      /**< Peripheral Domain Access Control, offset: 0x1188 */
  __IO uint32_t PDAC_W1_0_49;                      /**< Peripheral Domain Access Control, offset: 0x118C */
  __IO uint32_t PDAC_W0_0_50;                      /**< Peripheral Domain Access Control, offset: 0x1190 */
  __IO uint32_t PDAC_W1_0_50;                      /**< Peripheral Domain Access Control, offset: 0x1194 */
  __IO uint32_t PDAC_W0_0_51;                      /**< Peripheral Domain Access Control, offset: 0x1198 */
  __IO uint32_t PDAC_W1_0_51;                      /**< Peripheral Domain Access Control, offset: 0x119C */
  __IO uint32_t PDAC_W0_0_52;                      /**< Peripheral Domain Access Control, offset: 0x11A0 */
  __IO uint32_t PDAC_W1_0_52;                      /**< Peripheral Domain Access Control, offset: 0x11A4 */
  __IO uint32_t PDAC_W0_0_53;                      /**< Peripheral Domain Access Control, offset: 0x11A8 */
  __IO uint32_t PDAC_W1_0_53;                      /**< Peripheral Domain Access Control, offset: 0x11AC */
  __IO uint32_t PDAC_W0_0_54;                      /**< Peripheral Domain Access Control, offset: 0x11B0 */
  __IO uint32_t PDAC_W1_0_54;                      /**< Peripheral Domain Access Control, offset: 0x11B4 */
  __IO uint32_t PDAC_W0_0_55;                      /**< Peripheral Domain Access Control, offset: 0x11B8 */
  __IO uint32_t PDAC_W1_0_55;                      /**< Peripheral Domain Access Control, offset: 0x11BC */
  __IO uint32_t PDAC_W0_0_56;                      /**< Peripheral Domain Access Control, offset: 0x11C0 */
  __IO uint32_t PDAC_W1_0_56;                      /**< Peripheral Domain Access Control, offset: 0x11C4 */
  __IO uint32_t PDAC_W0_0_57;                      /**< Peripheral Domain Access Control, offset: 0x11C8 */
  __IO uint32_t PDAC_W1_0_57;                      /**< Peripheral Domain Access Control, offset: 0x11CC */
  __IO uint32_t PDAC_W0_0_58;                      /**< Peripheral Domain Access Control, offset: 0x11D0 */
  __IO uint32_t PDAC_W1_0_58;                      /**< Peripheral Domain Access Control, offset: 0x11D4 */
  __IO uint32_t PDAC_W0_0_59;                      /**< Peripheral Domain Access Control, offset: 0x11D8 */
  __IO uint32_t PDAC_W1_0_59;                      /**< Peripheral Domain Access Control, offset: 0x11DC */
  __IO uint32_t PDAC_W0_0_60;                      /**< Peripheral Domain Access Control, offset: 0x11E0 */
  __IO uint32_t PDAC_W1_0_60;                      /**< Peripheral Domain Access Control, offset: 0x11E4 */
       uint8_t RESERVED_44[536];
  __IO uint32_t PDAC_W0_1_0;                       /**< Peripheral Domain Access Control, offset: 0x1400 */
  __IO uint32_t PDAC_W1_1_0;                       /**< Peripheral Domain Access Control, offset: 0x1404 */
  __IO uint32_t PDAC_W0_1_1;                       /**< Peripheral Domain Access Control, offset: 0x1408 */
  __IO uint32_t PDAC_W1_1_1;                       /**< Peripheral Domain Access Control, offset: 0x140C */
  __IO uint32_t PDAC_W0_1_2;                       /**< Peripheral Domain Access Control, offset: 0x1410 */
  __IO uint32_t PDAC_W1_1_2;                       /**< Peripheral Domain Access Control, offset: 0x1414 */
  __IO uint32_t PDAC_W0_1_3;                       /**< Peripheral Domain Access Control, offset: 0x1418 */
  __IO uint32_t PDAC_W1_1_3;                       /**< Peripheral Domain Access Control, offset: 0x141C */
  __IO uint32_t PDAC_W0_1_4;                       /**< Peripheral Domain Access Control, offset: 0x1420 */
  __IO uint32_t PDAC_W1_1_4;                       /**< Peripheral Domain Access Control, offset: 0x1424 */
  __IO uint32_t PDAC_W0_1_5;                       /**< Peripheral Domain Access Control, offset: 0x1428 */
  __IO uint32_t PDAC_W1_1_5;                       /**< Peripheral Domain Access Control, offset: 0x142C */
  __IO uint32_t PDAC_W0_1_6;                       /**< Peripheral Domain Access Control, offset: 0x1430 */
  __IO uint32_t PDAC_W1_1_6;                       /**< Peripheral Domain Access Control, offset: 0x1434 */
  __IO uint32_t PDAC_W0_1_7;                       /**< Peripheral Domain Access Control, offset: 0x1438 */
  __IO uint32_t PDAC_W1_1_7;                       /**< Peripheral Domain Access Control, offset: 0x143C */
  __IO uint32_t PDAC_W0_1_8;                       /**< Peripheral Domain Access Control, offset: 0x1440 */
  __IO uint32_t PDAC_W1_1_8;                       /**< Peripheral Domain Access Control, offset: 0x1444 */
  __IO uint32_t PDAC_W0_1_9;                       /**< Peripheral Domain Access Control, offset: 0x1448 */
  __IO uint32_t PDAC_W1_1_9;                       /**< Peripheral Domain Access Control, offset: 0x144C */
  __IO uint32_t PDAC_W0_1_10;                      /**< Peripheral Domain Access Control, offset: 0x1450 */
  __IO uint32_t PDAC_W1_1_10;                      /**< Peripheral Domain Access Control, offset: 0x1454 */
  __IO uint32_t PDAC_W0_1_11;                      /**< Peripheral Domain Access Control, offset: 0x1458 */
  __IO uint32_t PDAC_W1_1_11;                      /**< Peripheral Domain Access Control, offset: 0x145C */
  __IO uint32_t PDAC_W0_1_12;                      /**< Peripheral Domain Access Control, offset: 0x1460 */
  __IO uint32_t PDAC_W1_1_12;                      /**< Peripheral Domain Access Control, offset: 0x1464 */
  __IO uint32_t PDAC_W0_1_13;                      /**< Peripheral Domain Access Control, offset: 0x1468 */
  __IO uint32_t PDAC_W1_1_13;                      /**< Peripheral Domain Access Control, offset: 0x146C */
  __IO uint32_t PDAC_W0_1_14;                      /**< Peripheral Domain Access Control, offset: 0x1470 */
  __IO uint32_t PDAC_W1_1_14;                      /**< Peripheral Domain Access Control, offset: 0x1474 */
  __IO uint32_t PDAC_W0_1_15;                      /**< Peripheral Domain Access Control, offset: 0x1478 */
  __IO uint32_t PDAC_W1_1_15;                      /**< Peripheral Domain Access Control, offset: 0x147C */
  __IO uint32_t PDAC_W0_1_16;                      /**< Peripheral Domain Access Control, offset: 0x1480 */
  __IO uint32_t PDAC_W1_1_16;                      /**< Peripheral Domain Access Control, offset: 0x1484 */
  __IO uint32_t PDAC_W0_1_17;                      /**< Peripheral Domain Access Control, offset: 0x1488 */
  __IO uint32_t PDAC_W1_1_17;                      /**< Peripheral Domain Access Control, offset: 0x148C */
  __IO uint32_t PDAC_W0_1_18;                      /**< Peripheral Domain Access Control, offset: 0x1490 */
  __IO uint32_t PDAC_W1_1_18;                      /**< Peripheral Domain Access Control, offset: 0x1494 */
  __IO uint32_t PDAC_W0_1_19;                      /**< Peripheral Domain Access Control, offset: 0x1498 */
  __IO uint32_t PDAC_W1_1_19;                      /**< Peripheral Domain Access Control, offset: 0x149C */
  __IO uint32_t PDAC_W0_1_20;                      /**< Peripheral Domain Access Control, offset: 0x14A0 */
  __IO uint32_t PDAC_W1_1_20;                      /**< Peripheral Domain Access Control, offset: 0x14A4 */
  __IO uint32_t PDAC_W0_1_21;                      /**< Peripheral Domain Access Control, offset: 0x14A8 */
  __IO uint32_t PDAC_W1_1_21;                      /**< Peripheral Domain Access Control, offset: 0x14AC */
  __IO uint32_t PDAC_W0_1_22;                      /**< Peripheral Domain Access Control, offset: 0x14B0 */
  __IO uint32_t PDAC_W1_1_22;                      /**< Peripheral Domain Access Control, offset: 0x14B4 */
       uint8_t RESERVED_45[840];
  __IO uint32_t PDAC_W0_2_0;                       /**< Peripheral Domain Access Control, offset: 0x1800 */
  __IO uint32_t PDAC_W1_2_0;                       /**< Peripheral Domain Access Control, offset: 0x1804 */
  __IO uint32_t PDAC_W0_2_1;                       /**< Peripheral Domain Access Control, offset: 0x1808 */
  __IO uint32_t PDAC_W1_2_1;                       /**< Peripheral Domain Access Control, offset: 0x180C */
  __IO uint32_t PDAC_W0_2_2;                       /**< Peripheral Domain Access Control, offset: 0x1810 */
  __IO uint32_t PDAC_W1_2_2;                       /**< Peripheral Domain Access Control, offset: 0x1814 */
  __IO uint32_t PDAC_W0_2_3;                       /**< Peripheral Domain Access Control, offset: 0x1818 */
  __IO uint32_t PDAC_W1_2_3;                       /**< Peripheral Domain Access Control, offset: 0x181C */
  __IO uint32_t PDAC_W0_2_4;                       /**< Peripheral Domain Access Control, offset: 0x1820 */
  __IO uint32_t PDAC_W1_2_4;                       /**< Peripheral Domain Access Control, offset: 0x1824 */
  __IO uint32_t PDAC_W0_2_5;                       /**< Peripheral Domain Access Control, offset: 0x1828 */
  __IO uint32_t PDAC_W1_2_5;                       /**< Peripheral Domain Access Control, offset: 0x182C */
  __IO uint32_t PDAC_W0_2_6;                       /**< Peripheral Domain Access Control, offset: 0x1830 */
  __IO uint32_t PDAC_W1_2_6;                       /**< Peripheral Domain Access Control, offset: 0x1834 */
  __IO uint32_t PDAC_W0_2_7;                       /**< Peripheral Domain Access Control, offset: 0x1838 */
  __IO uint32_t PDAC_W1_2_7;                       /**< Peripheral Domain Access Control, offset: 0x183C */
  __IO uint32_t PDAC_W0_2_8;                       /**< Peripheral Domain Access Control, offset: 0x1840 */
  __IO uint32_t PDAC_W1_2_8;                       /**< Peripheral Domain Access Control, offset: 0x1844 */
  __IO uint32_t PDAC_W0_2_9;                       /**< Peripheral Domain Access Control, offset: 0x1848 */
  __IO uint32_t PDAC_W1_2_9;                       /**< Peripheral Domain Access Control, offset: 0x184C */
  __IO uint32_t PDAC_W0_2_10;                      /**< Peripheral Domain Access Control, offset: 0x1850 */
  __IO uint32_t PDAC_W1_2_10;                      /**< Peripheral Domain Access Control, offset: 0x1854 */
  __IO uint32_t PDAC_W0_2_11;                      /**< Peripheral Domain Access Control, offset: 0x1858 */
  __IO uint32_t PDAC_W1_2_11;                      /**< Peripheral Domain Access Control, offset: 0x185C */
  __IO uint32_t PDAC_W0_2_12;                      /**< Peripheral Domain Access Control, offset: 0x1860 */
  __IO uint32_t PDAC_W1_2_12;                      /**< Peripheral Domain Access Control, offset: 0x1864 */
  __IO uint32_t PDAC_W0_2_13;                      /**< Peripheral Domain Access Control, offset: 0x1868 */
  __IO uint32_t PDAC_W1_2_13;                      /**< Peripheral Domain Access Control, offset: 0x186C */
  __IO uint32_t PDAC_W0_2_14;                      /**< Peripheral Domain Access Control, offset: 0x1870 */
  __IO uint32_t PDAC_W1_2_14;                      /**< Peripheral Domain Access Control, offset: 0x1874 */
  __IO uint32_t PDAC_W0_2_15;                      /**< Peripheral Domain Access Control, offset: 0x1878 */
  __IO uint32_t PDAC_W1_2_15;                      /**< Peripheral Domain Access Control, offset: 0x187C */
  __IO uint32_t PDAC_W0_2_16;                      /**< Peripheral Domain Access Control, offset: 0x1880 */
  __IO uint32_t PDAC_W1_2_16;                      /**< Peripheral Domain Access Control, offset: 0x1884 */
  __IO uint32_t PDAC_W0_2_17;                      /**< Peripheral Domain Access Control, offset: 0x1888 */
  __IO uint32_t PDAC_W1_2_17;                      /**< Peripheral Domain Access Control, offset: 0x188C */
  __IO uint32_t PDAC_W0_2_18;                      /**< Peripheral Domain Access Control, offset: 0x1890 */
  __IO uint32_t PDAC_W1_2_18;                      /**< Peripheral Domain Access Control, offset: 0x1894 */
  __IO uint32_t PDAC_W0_2_19;                      /**< Peripheral Domain Access Control, offset: 0x1898 */
  __IO uint32_t PDAC_W1_2_19;                      /**< Peripheral Domain Access Control, offset: 0x189C */
  __IO uint32_t PDAC_W0_2_20;                      /**< Peripheral Domain Access Control, offset: 0x18A0 */
  __IO uint32_t PDAC_W1_2_20;                      /**< Peripheral Domain Access Control, offset: 0x18A4 */
  __IO uint32_t PDAC_W0_2_21;                      /**< Peripheral Domain Access Control, offset: 0x18A8 */
  __IO uint32_t PDAC_W1_2_21;                      /**< Peripheral Domain Access Control, offset: 0x18AC */
  __IO uint32_t PDAC_W0_2_22;                      /**< Peripheral Domain Access Control, offset: 0x18B0 */
  __IO uint32_t PDAC_W1_2_22;                      /**< Peripheral Domain Access Control, offset: 0x18B4 */
  __IO uint32_t PDAC_W0_2_23;                      /**< Peripheral Domain Access Control, offset: 0x18B8 */
  __IO uint32_t PDAC_W1_2_23;                      /**< Peripheral Domain Access Control, offset: 0x18BC */
  __IO uint32_t PDAC_W0_2_24;                      /**< Peripheral Domain Access Control, offset: 0x18C0 */
  __IO uint32_t PDAC_W1_2_24;                      /**< Peripheral Domain Access Control, offset: 0x18C4 */
  __IO uint32_t PDAC_W0_2_25;                      /**< Peripheral Domain Access Control, offset: 0x18C8 */
  __IO uint32_t PDAC_W1_2_25;                      /**< Peripheral Domain Access Control, offset: 0x18CC */
  __IO uint32_t PDAC_W0_2_26;                      /**< Peripheral Domain Access Control, offset: 0x18D0 */
  __IO uint32_t PDAC_W1_2_26;                      /**< Peripheral Domain Access Control, offset: 0x18D4 */
  __IO uint32_t PDAC_W0_2_27;                      /**< Peripheral Domain Access Control, offset: 0x18D8 */
  __IO uint32_t PDAC_W1_2_27;                      /**< Peripheral Domain Access Control, offset: 0x18DC */
  __IO uint32_t PDAC_W0_2_28;                      /**< Peripheral Domain Access Control, offset: 0x18E0 */
  __IO uint32_t PDAC_W1_2_28;                      /**< Peripheral Domain Access Control, offset: 0x18E4 */
  __IO uint32_t PDAC_W0_2_29;                      /**< Peripheral Domain Access Control, offset: 0x18E8 */
  __IO uint32_t PDAC_W1_2_29;                      /**< Peripheral Domain Access Control, offset: 0x18EC */
  __IO uint32_t PDAC_W0_2_30;                      /**< Peripheral Domain Access Control, offset: 0x18F0 */
  __IO uint32_t PDAC_W1_2_30;                      /**< Peripheral Domain Access Control, offset: 0x18F4 */
  __IO uint32_t PDAC_W0_2_31;                      /**< Peripheral Domain Access Control, offset: 0x18F8 */
  __IO uint32_t PDAC_W1_2_31;                      /**< Peripheral Domain Access Control, offset: 0x18FC */
  __IO uint32_t PDAC_W0_2_32;                      /**< Peripheral Domain Access Control, offset: 0x1900 */
  __IO uint32_t PDAC_W1_2_32;                      /**< Peripheral Domain Access Control, offset: 0x1904 */
  __IO uint32_t PDAC_W0_2_33;                      /**< Peripheral Domain Access Control, offset: 0x1908 */
  __IO uint32_t PDAC_W1_2_33;                      /**< Peripheral Domain Access Control, offset: 0x190C */
  __IO uint32_t PDAC_W0_2_34;                      /**< Peripheral Domain Access Control, offset: 0x1910 */
  __IO uint32_t PDAC_W1_2_34;                      /**< Peripheral Domain Access Control, offset: 0x1914 */
  __IO uint32_t PDAC_W0_2_35;                      /**< Peripheral Domain Access Control, offset: 0x1918 */
  __IO uint32_t PDAC_W1_2_35;                      /**< Peripheral Domain Access Control, offset: 0x191C */
  __IO uint32_t PDAC_W0_2_36;                      /**< Peripheral Domain Access Control, offset: 0x1920 */
  __IO uint32_t PDAC_W1_2_36;                      /**< Peripheral Domain Access Control, offset: 0x1924 */
  __IO uint32_t PDAC_W0_2_37;                      /**< Peripheral Domain Access Control, offset: 0x1928 */
  __IO uint32_t PDAC_W1_2_37;                      /**< Peripheral Domain Access Control, offset: 0x192C */
  __IO uint32_t PDAC_W0_2_38;                      /**< Peripheral Domain Access Control, offset: 0x1930 */
  __IO uint32_t PDAC_W1_2_38;                      /**< Peripheral Domain Access Control, offset: 0x1934 */
  __IO uint32_t PDAC_W0_2_39;                      /**< Peripheral Domain Access Control, offset: 0x1938 */
  __IO uint32_t PDAC_W1_2_39;                      /**< Peripheral Domain Access Control, offset: 0x193C */
  __IO uint32_t PDAC_W0_2_40;                      /**< Peripheral Domain Access Control, offset: 0x1940 */
  __IO uint32_t PDAC_W1_2_40;                      /**< Peripheral Domain Access Control, offset: 0x1944 */
  __IO uint32_t PDAC_W0_2_41;                      /**< Peripheral Domain Access Control, offset: 0x1948 */
  __IO uint32_t PDAC_W1_2_41;                      /**< Peripheral Domain Access Control, offset: 0x194C */
  __IO uint32_t PDAC_W0_2_42;                      /**< Peripheral Domain Access Control, offset: 0x1950 */
  __IO uint32_t PDAC_W1_2_42;                      /**< Peripheral Domain Access Control, offset: 0x1954 */
  __IO uint32_t PDAC_W0_2_43;                      /**< Peripheral Domain Access Control, offset: 0x1958 */
  __IO uint32_t PDAC_W1_2_43;                      /**< Peripheral Domain Access Control, offset: 0x195C */
  __IO uint32_t PDAC_W0_2_44;                      /**< Peripheral Domain Access Control, offset: 0x1960 */
  __IO uint32_t PDAC_W1_2_44;                      /**< Peripheral Domain Access Control, offset: 0x1964 */
  __IO uint32_t PDAC_W0_2_45;                      /**< Peripheral Domain Access Control, offset: 0x1968 */
  __IO uint32_t PDAC_W1_2_45;                      /**< Peripheral Domain Access Control, offset: 0x196C */
  __IO uint32_t PDAC_W0_2_46;                      /**< Peripheral Domain Access Control, offset: 0x1970 */
  __IO uint32_t PDAC_W1_2_46;                      /**< Peripheral Domain Access Control, offset: 0x1974 */
  __IO uint32_t PDAC_W0_2_47;                      /**< Peripheral Domain Access Control, offset: 0x1978 */
  __IO uint32_t PDAC_W1_2_47;                      /**< Peripheral Domain Access Control, offset: 0x197C */
  __IO uint32_t PDAC_W0_2_48;                      /**< Peripheral Domain Access Control, offset: 0x1980 */
  __IO uint32_t PDAC_W1_2_48;                      /**< Peripheral Domain Access Control, offset: 0x1984 */
       uint8_t RESERVED_46[8];
  __IO uint32_t PDAC_W0_2_50;                      /**< Peripheral Domain Access Control, offset: 0x1990 */
  __IO uint32_t PDAC_W1_2_50;                      /**< Peripheral Domain Access Control, offset: 0x1994 */
  __IO uint32_t PDAC_W0_2_51;                      /**< Peripheral Domain Access Control, offset: 0x1998 */
  __IO uint32_t PDAC_W1_2_51;                      /**< Peripheral Domain Access Control, offset: 0x199C */
  __IO uint32_t PDAC_W0_2_52;                      /**< Peripheral Domain Access Control, offset: 0x19A0 */
  __IO uint32_t PDAC_W1_2_52;                      /**< Peripheral Domain Access Control, offset: 0x19A4 */
       uint8_t RESERVED_47[1624];
  __IO uint32_t MRGD_W0_0_0;                       /**< Memory Region Descriptor, offset: 0x2000 */
  __IO uint32_t MRGD_W1_0_0;                       /**< Memory Region Descriptor, offset: 0x2004 */
  __IO uint32_t MRGD_W2_0_0;                       /**< Memory Region Descriptor, offset: 0x2008 */
  __IO uint32_t MRGD_W3_0_0;                       /**< Memory Region Descriptor, offset: 0x200C */
  __IO uint32_t MRGD_W4_0_0;                       /**< Memory Region Descriptor, offset: 0x2010 */
       uint8_t RESERVED_48[12];
  __IO uint32_t MRGD_W0_0_1;                       /**< Memory Region Descriptor, offset: 0x2020 */
  __IO uint32_t MRGD_W1_0_1;                       /**< Memory Region Descriptor, offset: 0x2024 */
  __IO uint32_t MRGD_W2_0_1;                       /**< Memory Region Descriptor, offset: 0x2028 */
  __IO uint32_t MRGD_W3_0_1;                       /**< Memory Region Descriptor, offset: 0x202C */
  __IO uint32_t MRGD_W4_0_1;                       /**< Memory Region Descriptor, offset: 0x2030 */
       uint8_t RESERVED_49[12];
  __IO uint32_t MRGD_W0_0_2;                       /**< Memory Region Descriptor, offset: 0x2040 */
  __IO uint32_t MRGD_W1_0_2;                       /**< Memory Region Descriptor, offset: 0x2044 */
  __IO uint32_t MRGD_W2_0_2;                       /**< Memory Region Descriptor, offset: 0x2048 */
  __IO uint32_t MRGD_W3_0_2;                       /**< Memory Region Descriptor, offset: 0x204C */
  __IO uint32_t MRGD_W4_0_2;                       /**< Memory Region Descriptor, offset: 0x2050 */
       uint8_t RESERVED_50[12];
  __IO uint32_t MRGD_W0_0_3;                       /**< Memory Region Descriptor, offset: 0x2060 */
  __IO uint32_t MRGD_W1_0_3;                       /**< Memory Region Descriptor, offset: 0x2064 */
  __IO uint32_t MRGD_W2_0_3;                       /**< Memory Region Descriptor, offset: 0x2068 */
  __IO uint32_t MRGD_W3_0_3;                       /**< Memory Region Descriptor, offset: 0x206C */
  __IO uint32_t MRGD_W4_0_3;                       /**< Memory Region Descriptor, offset: 0x2070 */
       uint8_t RESERVED_51[396];
  __IO uint32_t MRGD_W0_1_0;                       /**< Memory Region Descriptor, offset: 0x2200 */
  __IO uint32_t MRGD_W1_1_0;                       /**< Memory Region Descriptor, offset: 0x2204 */
  __IO uint32_t MRGD_W2_1_0;                       /**< Memory Region Descriptor, offset: 0x2208 */
  __IO uint32_t MRGD_W3_1_0;                       /**< Memory Region Descriptor, offset: 0x220C */
  __IO uint32_t MRGD_W4_1_0;                       /**< Memory Region Descriptor, offset: 0x2210 */
       uint8_t RESERVED_52[12];
  __IO uint32_t MRGD_W0_1_1;                       /**< Memory Region Descriptor, offset: 0x2220 */
  __IO uint32_t MRGD_W1_1_1;                       /**< Memory Region Descriptor, offset: 0x2224 */
  __IO uint32_t MRGD_W2_1_1;                       /**< Memory Region Descriptor, offset: 0x2228 */
  __IO uint32_t MRGD_W3_1_1;                       /**< Memory Region Descriptor, offset: 0x222C */
  __IO uint32_t MRGD_W4_1_1;                       /**< Memory Region Descriptor, offset: 0x2230 */
       uint8_t RESERVED_53[12];
  __IO uint32_t MRGD_W0_1_2;                       /**< Memory Region Descriptor, offset: 0x2240 */
  __IO uint32_t MRGD_W1_1_2;                       /**< Memory Region Descriptor, offset: 0x2244 */
  __IO uint32_t MRGD_W2_1_2;                       /**< Memory Region Descriptor, offset: 0x2248 */
  __IO uint32_t MRGD_W3_1_2;                       /**< Memory Region Descriptor, offset: 0x224C */
  __IO uint32_t MRGD_W4_1_2;                       /**< Memory Region Descriptor, offset: 0x2250 */
       uint8_t RESERVED_54[12];
  __IO uint32_t MRGD_W0_1_3;                       /**< Memory Region Descriptor, offset: 0x2260 */
  __IO uint32_t MRGD_W1_1_3;                       /**< Memory Region Descriptor, offset: 0x2264 */
  __IO uint32_t MRGD_W2_1_3;                       /**< Memory Region Descriptor, offset: 0x2268 */
  __IO uint32_t MRGD_W3_1_3;                       /**< Memory Region Descriptor, offset: 0x226C */
  __IO uint32_t MRGD_W4_1_3;                       /**< Memory Region Descriptor, offset: 0x2270 */
       uint8_t RESERVED_55[12];
  __IO uint32_t MRGD_W0_1_4;                       /**< Memory Region Descriptor, offset: 0x2280 */
  __IO uint32_t MRGD_W1_1_4;                       /**< Memory Region Descriptor, offset: 0x2284 */
  __IO uint32_t MRGD_W2_1_4;                       /**< Memory Region Descriptor, offset: 0x2288 */
  __IO uint32_t MRGD_W3_1_4;                       /**< Memory Region Descriptor, offset: 0x228C */
  __IO uint32_t MRGD_W4_1_4;                       /**< Memory Region Descriptor, offset: 0x2290 */
       uint8_t RESERVED_56[12];
  __IO uint32_t MRGD_W0_1_5;                       /**< Memory Region Descriptor, offset: 0x22A0 */
  __IO uint32_t MRGD_W1_1_5;                       /**< Memory Region Descriptor, offset: 0x22A4 */
  __IO uint32_t MRGD_W2_1_5;                       /**< Memory Region Descriptor, offset: 0x22A8 */
  __IO uint32_t MRGD_W3_1_5;                       /**< Memory Region Descriptor, offset: 0x22AC */
  __IO uint32_t MRGD_W4_1_5;                       /**< Memory Region Descriptor, offset: 0x22B0 */
       uint8_t RESERVED_57[12];
  __IO uint32_t MRGD_W0_1_6;                       /**< Memory Region Descriptor, offset: 0x22C0 */
  __IO uint32_t MRGD_W1_1_6;                       /**< Memory Region Descriptor, offset: 0x22C4 */
  __IO uint32_t MRGD_W2_1_6;                       /**< Memory Region Descriptor, offset: 0x22C8 */
  __IO uint32_t MRGD_W3_1_6;                       /**< Memory Region Descriptor, offset: 0x22CC */
  __IO uint32_t MRGD_W4_1_6;                       /**< Memory Region Descriptor, offset: 0x22D0 */
       uint8_t RESERVED_58[12];
  __IO uint32_t MRGD_W0_1_7;                       /**< Memory Region Descriptor, offset: 0x22E0 */
  __IO uint32_t MRGD_W1_1_7;                       /**< Memory Region Descriptor, offset: 0x22E4 */
  __IO uint32_t MRGD_W2_1_7;                       /**< Memory Region Descriptor, offset: 0x22E8 */
  __IO uint32_t MRGD_W3_1_7;                       /**< Memory Region Descriptor, offset: 0x22EC */
  __IO uint32_t MRGD_W4_1_7;                       /**< Memory Region Descriptor, offset: 0x22F0 */
       uint8_t RESERVED_59[268];
  __IO uint32_t MRGD_W0_2_0;                       /**< Memory Region Descriptor, offset: 0x2400 */
  __IO uint32_t MRGD_W1_2_0;                       /**< Memory Region Descriptor, offset: 0x2404 */
  __IO uint32_t MRGD_W2_2_0;                       /**< Memory Region Descriptor, offset: 0x2408 */
  __IO uint32_t MRGD_W3_2_0;                       /**< Memory Region Descriptor, offset: 0x240C */
  __IO uint32_t MRGD_W4_2_0;                       /**< Memory Region Descriptor, offset: 0x2410 */
       uint8_t RESERVED_60[12];
  __IO uint32_t MRGD_W0_2_1;                       /**< Memory Region Descriptor, offset: 0x2420 */
  __IO uint32_t MRGD_W1_2_1;                       /**< Memory Region Descriptor, offset: 0x2424 */
  __IO uint32_t MRGD_W2_2_1;                       /**< Memory Region Descriptor, offset: 0x2428 */
  __IO uint32_t MRGD_W3_2_1;                       /**< Memory Region Descriptor, offset: 0x242C */
  __IO uint32_t MRGD_W4_2_1;                       /**< Memory Region Descriptor, offset: 0x2430 */
       uint8_t RESERVED_61[12];
  __IO uint32_t MRGD_W0_2_2;                       /**< Memory Region Descriptor, offset: 0x2440 */
  __IO uint32_t MRGD_W1_2_2;                       /**< Memory Region Descriptor, offset: 0x2444 */
  __IO uint32_t MRGD_W2_2_2;                       /**< Memory Region Descriptor, offset: 0x2448 */
  __IO uint32_t MRGD_W3_2_2;                       /**< Memory Region Descriptor, offset: 0x244C */
  __IO uint32_t MRGD_W4_2_2;                       /**< Memory Region Descriptor, offset: 0x2450 */
       uint8_t RESERVED_62[12];
  __IO uint32_t MRGD_W0_2_3;                       /**< Memory Region Descriptor, offset: 0x2460 */
  __IO uint32_t MRGD_W1_2_3;                       /**< Memory Region Descriptor, offset: 0x2464 */
  __IO uint32_t MRGD_W2_2_3;                       /**< Memory Region Descriptor, offset: 0x2468 */
  __IO uint32_t MRGD_W3_2_3;                       /**< Memory Region Descriptor, offset: 0x246C */
  __IO uint32_t MRGD_W4_2_3;                       /**< Memory Region Descriptor, offset: 0x2470 */
       uint8_t RESERVED_63[396];
  __IO uint32_t MRGD_W0_3_0;                       /**< Memory Region Descriptor, offset: 0x2600 */
  __IO uint32_t MRGD_W1_3_0;                       /**< Memory Region Descriptor, offset: 0x2604 */
  __IO uint32_t MRGD_W2_3_0;                       /**< Memory Region Descriptor, offset: 0x2608 */
  __IO uint32_t MRGD_W3_3_0;                       /**< Memory Region Descriptor, offset: 0x260C */
  __IO uint32_t MRGD_W4_3_0;                       /**< Memory Region Descriptor, offset: 0x2610 */
       uint8_t RESERVED_64[12];
  __IO uint32_t MRGD_W0_3_1;                       /**< Memory Region Descriptor, offset: 0x2620 */
  __IO uint32_t MRGD_W1_3_1;                       /**< Memory Region Descriptor, offset: 0x2624 */
  __IO uint32_t MRGD_W2_3_1;                       /**< Memory Region Descriptor, offset: 0x2628 */
  __IO uint32_t MRGD_W3_3_1;                       /**< Memory Region Descriptor, offset: 0x262C */
  __IO uint32_t MRGD_W4_3_1;                       /**< Memory Region Descriptor, offset: 0x2630 */
       uint8_t RESERVED_65[12];
  __IO uint32_t MRGD_W0_3_2;                       /**< Memory Region Descriptor, offset: 0x2640 */
  __IO uint32_t MRGD_W1_3_2;                       /**< Memory Region Descriptor, offset: 0x2644 */
  __IO uint32_t MRGD_W2_3_2;                       /**< Memory Region Descriptor, offset: 0x2648 */
  __IO uint32_t MRGD_W3_3_2;                       /**< Memory Region Descriptor, offset: 0x264C */
  __IO uint32_t MRGD_W4_3_2;                       /**< Memory Region Descriptor, offset: 0x2650 */
       uint8_t RESERVED_66[12];
  __IO uint32_t MRGD_W0_3_3;                       /**< Memory Region Descriptor, offset: 0x2660 */
  __IO uint32_t MRGD_W1_3_3;                       /**< Memory Region Descriptor, offset: 0x2664 */
  __IO uint32_t MRGD_W2_3_3;                       /**< Memory Region Descriptor, offset: 0x2668 */
  __IO uint32_t MRGD_W3_3_3;                       /**< Memory Region Descriptor, offset: 0x266C */
  __IO uint32_t MRGD_W4_3_3;                       /**< Memory Region Descriptor, offset: 0x2670 */
       uint8_t RESERVED_67[396];
  __IO uint32_t MRGD_W0_4_0;                       /**< Memory Region Descriptor, offset: 0x2800 */
  __IO uint32_t MRGD_W1_4_0;                       /**< Memory Region Descriptor, offset: 0x2804 */
  __IO uint32_t MRGD_W2_4_0;                       /**< Memory Region Descriptor, offset: 0x2808 */
  __IO uint32_t MRGD_W3_4_0;                       /**< Memory Region Descriptor, offset: 0x280C */
  __IO uint32_t MRGD_W4_4_0;                       /**< Memory Region Descriptor, offset: 0x2810 */
       uint8_t RESERVED_68[12];
  __IO uint32_t MRGD_W0_4_1;                       /**< Memory Region Descriptor, offset: 0x2820 */
  __IO uint32_t MRGD_W1_4_1;                       /**< Memory Region Descriptor, offset: 0x2824 */
  __IO uint32_t MRGD_W2_4_1;                       /**< Memory Region Descriptor, offset: 0x2828 */
  __IO uint32_t MRGD_W3_4_1;                       /**< Memory Region Descriptor, offset: 0x282C */
  __IO uint32_t MRGD_W4_4_1;                       /**< Memory Region Descriptor, offset: 0x2830 */
       uint8_t RESERVED_69[12];
  __IO uint32_t MRGD_W0_4_2;                       /**< Memory Region Descriptor, offset: 0x2840 */
  __IO uint32_t MRGD_W1_4_2;                       /**< Memory Region Descriptor, offset: 0x2844 */
  __IO uint32_t MRGD_W2_4_2;                       /**< Memory Region Descriptor, offset: 0x2848 */
  __IO uint32_t MRGD_W3_4_2;                       /**< Memory Region Descriptor, offset: 0x284C */
  __IO uint32_t MRGD_W4_4_2;                       /**< Memory Region Descriptor, offset: 0x2850 */
       uint8_t RESERVED_70[12];
  __IO uint32_t MRGD_W0_4_3;                       /**< Memory Region Descriptor, offset: 0x2860 */
  __IO uint32_t MRGD_W1_4_3;                       /**< Memory Region Descriptor, offset: 0x2864 */
  __IO uint32_t MRGD_W2_4_3;                       /**< Memory Region Descriptor, offset: 0x2868 */
  __IO uint32_t MRGD_W3_4_3;                       /**< Memory Region Descriptor, offset: 0x286C */
  __IO uint32_t MRGD_W4_4_3;                       /**< Memory Region Descriptor, offset: 0x2870 */
       uint8_t RESERVED_71[12];
  __IO uint32_t MRGD_W0_4_4;                       /**< Memory Region Descriptor, offset: 0x2880 */
  __IO uint32_t MRGD_W1_4_4;                       /**< Memory Region Descriptor, offset: 0x2884 */
  __IO uint32_t MRGD_W2_4_4;                       /**< Memory Region Descriptor, offset: 0x2888 */
  __IO uint32_t MRGD_W3_4_4;                       /**< Memory Region Descriptor, offset: 0x288C */
  __IO uint32_t MRGD_W4_4_4;                       /**< Memory Region Descriptor, offset: 0x2890 */
       uint8_t RESERVED_72[12];
  __IO uint32_t MRGD_W0_4_5;                       /**< Memory Region Descriptor, offset: 0x28A0 */
  __IO uint32_t MRGD_W1_4_5;                       /**< Memory Region Descriptor, offset: 0x28A4 */
  __IO uint32_t MRGD_W2_4_5;                       /**< Memory Region Descriptor, offset: 0x28A8 */
  __IO uint32_t MRGD_W3_4_5;                       /**< Memory Region Descriptor, offset: 0x28AC */
  __IO uint32_t MRGD_W4_4_5;                       /**< Memory Region Descriptor, offset: 0x28B0 */
       uint8_t RESERVED_73[12];
  __IO uint32_t MRGD_W0_4_6;                       /**< Memory Region Descriptor, offset: 0x28C0 */
  __IO uint32_t MRGD_W1_4_6;                       /**< Memory Region Descriptor, offset: 0x28C4 */
  __IO uint32_t MRGD_W2_4_6;                       /**< Memory Region Descriptor, offset: 0x28C8 */
  __IO uint32_t MRGD_W3_4_6;                       /**< Memory Region Descriptor, offset: 0x28CC */
  __IO uint32_t MRGD_W4_4_6;                       /**< Memory Region Descriptor, offset: 0x28D0 */
       uint8_t RESERVED_74[12];
  __IO uint32_t MRGD_W0_4_7;                       /**< Memory Region Descriptor, offset: 0x28E0 */
  __IO uint32_t MRGD_W1_4_7;                       /**< Memory Region Descriptor, offset: 0x28E4 */
  __IO uint32_t MRGD_W2_4_7;                       /**< Memory Region Descriptor, offset: 0x28E8 */
  __IO uint32_t MRGD_W3_4_7;                       /**< Memory Region Descriptor, offset: 0x28EC */
  __IO uint32_t MRGD_W4_4_7;                       /**< Memory Region Descriptor, offset: 0x28F0 */
       uint8_t RESERVED_75[268];
  __IO uint32_t MRGD_W0_5_0;                       /**< Memory Region Descriptor, offset: 0x2A00 */
  __IO uint32_t MRGD_W1_5_0;                       /**< Memory Region Descriptor, offset: 0x2A04 */
  __IO uint32_t MRGD_W2_5_0;                       /**< Memory Region Descriptor, offset: 0x2A08 */
  __IO uint32_t MRGD_W3_5_0;                       /**< Memory Region Descriptor, offset: 0x2A0C */
  __IO uint32_t MRGD_W4_5_0;                       /**< Memory Region Descriptor, offset: 0x2A10 */
       uint8_t RESERVED_76[12];
  __IO uint32_t MRGD_W0_5_1;                       /**< Memory Region Descriptor, offset: 0x2A20 */
  __IO uint32_t MRGD_W1_5_1;                       /**< Memory Region Descriptor, offset: 0x2A24 */
  __IO uint32_t MRGD_W2_5_1;                       /**< Memory Region Descriptor, offset: 0x2A28 */
  __IO uint32_t MRGD_W3_5_1;                       /**< Memory Region Descriptor, offset: 0x2A2C */
  __IO uint32_t MRGD_W4_5_1;                       /**< Memory Region Descriptor, offset: 0x2A30 */
       uint8_t RESERVED_77[12];
  __IO uint32_t MRGD_W0_5_2;                       /**< Memory Region Descriptor, offset: 0x2A40 */
  __IO uint32_t MRGD_W1_5_2;                       /**< Memory Region Descriptor, offset: 0x2A44 */
  __IO uint32_t MRGD_W2_5_2;                       /**< Memory Region Descriptor, offset: 0x2A48 */
  __IO uint32_t MRGD_W3_5_2;                       /**< Memory Region Descriptor, offset: 0x2A4C */
  __IO uint32_t MRGD_W4_5_2;                       /**< Memory Region Descriptor, offset: 0x2A50 */
       uint8_t RESERVED_78[12];
  __IO uint32_t MRGD_W0_5_3;                       /**< Memory Region Descriptor, offset: 0x2A60 */
  __IO uint32_t MRGD_W1_5_3;                       /**< Memory Region Descriptor, offset: 0x2A64 */
  __IO uint32_t MRGD_W2_5_3;                       /**< Memory Region Descriptor, offset: 0x2A68 */
  __IO uint32_t MRGD_W3_5_3;                       /**< Memory Region Descriptor, offset: 0x2A6C */
  __IO uint32_t MRGD_W4_5_3;                       /**< Memory Region Descriptor, offset: 0x2A70 */
       uint8_t RESERVED_79[12];
  __IO uint32_t MRGD_W0_5_4;                       /**< Memory Region Descriptor, offset: 0x2A80 */
  __IO uint32_t MRGD_W1_5_4;                       /**< Memory Region Descriptor, offset: 0x2A84 */
  __IO uint32_t MRGD_W2_5_4;                       /**< Memory Region Descriptor, offset: 0x2A88 */
  __IO uint32_t MRGD_W3_5_4;                       /**< Memory Region Descriptor, offset: 0x2A8C */
  __IO uint32_t MRGD_W4_5_4;                       /**< Memory Region Descriptor, offset: 0x2A90 */
       uint8_t RESERVED_80[12];
  __IO uint32_t MRGD_W0_5_5;                       /**< Memory Region Descriptor, offset: 0x2AA0 */
  __IO uint32_t MRGD_W1_5_5;                       /**< Memory Region Descriptor, offset: 0x2AA4 */
  __IO uint32_t MRGD_W2_5_5;                       /**< Memory Region Descriptor, offset: 0x2AA8 */
  __IO uint32_t MRGD_W3_5_5;                       /**< Memory Region Descriptor, offset: 0x2AAC */
  __IO uint32_t MRGD_W4_5_5;                       /**< Memory Region Descriptor, offset: 0x2AB0 */
       uint8_t RESERVED_81[12];
  __IO uint32_t MRGD_W0_5_6;                       /**< Memory Region Descriptor, offset: 0x2AC0 */
  __IO uint32_t MRGD_W1_5_6;                       /**< Memory Region Descriptor, offset: 0x2AC4 */
  __IO uint32_t MRGD_W2_5_6;                       /**< Memory Region Descriptor, offset: 0x2AC8 */
  __IO uint32_t MRGD_W3_5_6;                       /**< Memory Region Descriptor, offset: 0x2ACC */
  __IO uint32_t MRGD_W4_5_6;                       /**< Memory Region Descriptor, offset: 0x2AD0 */
       uint8_t RESERVED_82[12];
  __IO uint32_t MRGD_W0_5_7;                       /**< Memory Region Descriptor, offset: 0x2AE0 */
  __IO uint32_t MRGD_W1_5_7;                       /**< Memory Region Descriptor, offset: 0x2AE4 */
  __IO uint32_t MRGD_W2_5_7;                       /**< Memory Region Descriptor, offset: 0x2AE8 */
  __IO uint32_t MRGD_W3_5_7;                       /**< Memory Region Descriptor, offset: 0x2AEC */
  __IO uint32_t MRGD_W4_5_7;                       /**< Memory Region Descriptor, offset: 0x2AF0 */
       uint8_t RESERVED_83[268];
  __IO uint32_t MRGD_W0_6_0;                       /**< Memory Region Descriptor, offset: 0x2C00 */
  __IO uint32_t MRGD_W1_6_0;                       /**< Memory Region Descriptor, offset: 0x2C04 */
  __IO uint32_t MRGD_W2_6_0;                       /**< Memory Region Descriptor, offset: 0x2C08 */
  __IO uint32_t MRGD_W3_6_0;                       /**< Memory Region Descriptor, offset: 0x2C0C */
  __IO uint32_t MRGD_W4_6_0;                       /**< Memory Region Descriptor, offset: 0x2C10 */
       uint8_t RESERVED_84[12];
  __IO uint32_t MRGD_W0_6_1;                       /**< Memory Region Descriptor, offset: 0x2C20 */
  __IO uint32_t MRGD_W1_6_1;                       /**< Memory Region Descriptor, offset: 0x2C24 */
  __IO uint32_t MRGD_W2_6_1;                       /**< Memory Region Descriptor, offset: 0x2C28 */
  __IO uint32_t MRGD_W3_6_1;                       /**< Memory Region Descriptor, offset: 0x2C2C */
  __IO uint32_t MRGD_W4_6_1;                       /**< Memory Region Descriptor, offset: 0x2C30 */
       uint8_t RESERVED_85[12];
  __IO uint32_t MRGD_W0_6_2;                       /**< Memory Region Descriptor, offset: 0x2C40 */
  __IO uint32_t MRGD_W1_6_2;                       /**< Memory Region Descriptor, offset: 0x2C44 */
  __IO uint32_t MRGD_W2_6_2;                       /**< Memory Region Descriptor, offset: 0x2C48 */
  __IO uint32_t MRGD_W3_6_2;                       /**< Memory Region Descriptor, offset: 0x2C4C */
  __IO uint32_t MRGD_W4_6_2;                       /**< Memory Region Descriptor, offset: 0x2C50 */
       uint8_t RESERVED_86[12];
  __IO uint32_t MRGD_W0_6_3;                       /**< Memory Region Descriptor, offset: 0x2C60 */
  __IO uint32_t MRGD_W1_6_3;                       /**< Memory Region Descriptor, offset: 0x2C64 */
  __IO uint32_t MRGD_W2_6_3;                       /**< Memory Region Descriptor, offset: 0x2C68 */
  __IO uint32_t MRGD_W3_6_3;                       /**< Memory Region Descriptor, offset: 0x2C6C */
  __IO uint32_t MRGD_W4_6_3;                       /**< Memory Region Descriptor, offset: 0x2C70 */
       uint8_t RESERVED_87[12];
  __IO uint32_t MRGD_W0_6_4;                       /**< Memory Region Descriptor, offset: 0x2C80 */
  __IO uint32_t MRGD_W1_6_4;                       /**< Memory Region Descriptor, offset: 0x2C84 */
  __IO uint32_t MRGD_W2_6_4;                       /**< Memory Region Descriptor, offset: 0x2C88 */
  __IO uint32_t MRGD_W3_6_4;                       /**< Memory Region Descriptor, offset: 0x2C8C */
  __IO uint32_t MRGD_W4_6_4;                       /**< Memory Region Descriptor, offset: 0x2C90 */
       uint8_t RESERVED_88[12];
  __IO uint32_t MRGD_W0_6_5;                       /**< Memory Region Descriptor, offset: 0x2CA0 */
  __IO uint32_t MRGD_W1_6_5;                       /**< Memory Region Descriptor, offset: 0x2CA4 */
  __IO uint32_t MRGD_W2_6_5;                       /**< Memory Region Descriptor, offset: 0x2CA8 */
  __IO uint32_t MRGD_W3_6_5;                       /**< Memory Region Descriptor, offset: 0x2CAC */
  __IO uint32_t MRGD_W4_6_5;                       /**< Memory Region Descriptor, offset: 0x2CB0 */
       uint8_t RESERVED_89[12];
  __IO uint32_t MRGD_W0_6_6;                       /**< Memory Region Descriptor, offset: 0x2CC0 */
  __IO uint32_t MRGD_W1_6_6;                       /**< Memory Region Descriptor, offset: 0x2CC4 */
  __IO uint32_t MRGD_W2_6_6;                       /**< Memory Region Descriptor, offset: 0x2CC8 */
  __IO uint32_t MRGD_W3_6_6;                       /**< Memory Region Descriptor, offset: 0x2CCC */
  __IO uint32_t MRGD_W4_6_6;                       /**< Memory Region Descriptor, offset: 0x2CD0 */
       uint8_t RESERVED_90[12];
  __IO uint32_t MRGD_W0_6_7;                       /**< Memory Region Descriptor, offset: 0x2CE0 */
  __IO uint32_t MRGD_W1_6_7;                       /**< Memory Region Descriptor, offset: 0x2CE4 */
  __IO uint32_t MRGD_W2_6_7;                       /**< Memory Region Descriptor, offset: 0x2CE8 */
  __IO uint32_t MRGD_W3_6_7;                       /**< Memory Region Descriptor, offset: 0x2CEC */
  __IO uint32_t MRGD_W4_6_7;                       /**< Memory Region Descriptor, offset: 0x2CF0 */
       uint8_t RESERVED_91[268];
  __IO uint32_t MRGD_W0_7_0;                       /**< Memory Region Descriptor, offset: 0x2E00 */
  __IO uint32_t MRGD_W1_7_0;                       /**< Memory Region Descriptor, offset: 0x2E04 */
  __IO uint32_t MRGD_W2_7_0;                       /**< Memory Region Descriptor, offset: 0x2E08 */
  __IO uint32_t MRGD_W3_7_0;                       /**< Memory Region Descriptor, offset: 0x2E0C */
  __IO uint32_t MRGD_W4_7_0;                       /**< Memory Region Descriptor, offset: 0x2E10 */
       uint8_t RESERVED_92[12];
  __IO uint32_t MRGD_W0_7_1;                       /**< Memory Region Descriptor, offset: 0x2E20 */
  __IO uint32_t MRGD_W1_7_1;                       /**< Memory Region Descriptor, offset: 0x2E24 */
  __IO uint32_t MRGD_W2_7_1;                       /**< Memory Region Descriptor, offset: 0x2E28 */
  __IO uint32_t MRGD_W3_7_1;                       /**< Memory Region Descriptor, offset: 0x2E2C */
  __IO uint32_t MRGD_W4_7_1;                       /**< Memory Region Descriptor, offset: 0x2E30 */
       uint8_t RESERVED_93[12];
  __IO uint32_t MRGD_W0_7_2;                       /**< Memory Region Descriptor, offset: 0x2E40 */
  __IO uint32_t MRGD_W1_7_2;                       /**< Memory Region Descriptor, offset: 0x2E44 */
  __IO uint32_t MRGD_W2_7_2;                       /**< Memory Region Descriptor, offset: 0x2E48 */
  __IO uint32_t MRGD_W3_7_2;                       /**< Memory Region Descriptor, offset: 0x2E4C */
  __IO uint32_t MRGD_W4_7_2;                       /**< Memory Region Descriptor, offset: 0x2E50 */
       uint8_t RESERVED_94[12];
  __IO uint32_t MRGD_W0_7_3;                       /**< Memory Region Descriptor, offset: 0x2E60 */
  __IO uint32_t MRGD_W1_7_3;                       /**< Memory Region Descriptor, offset: 0x2E64 */
  __IO uint32_t MRGD_W2_7_3;                       /**< Memory Region Descriptor, offset: 0x2E68 */
  __IO uint32_t MRGD_W3_7_3;                       /**< Memory Region Descriptor, offset: 0x2E6C */
  __IO uint32_t MRGD_W4_7_3;                       /**< Memory Region Descriptor, offset: 0x2E70 */
       uint8_t RESERVED_95[12];
  __IO uint32_t MRGD_W0_7_4;                       /**< Memory Region Descriptor, offset: 0x2E80 */
  __IO uint32_t MRGD_W1_7_4;                       /**< Memory Region Descriptor, offset: 0x2E84 */
  __IO uint32_t MRGD_W2_7_4;                       /**< Memory Region Descriptor, offset: 0x2E88 */
  __IO uint32_t MRGD_W3_7_4;                       /**< Memory Region Descriptor, offset: 0x2E8C */
  __IO uint32_t MRGD_W4_7_4;                       /**< Memory Region Descriptor, offset: 0x2E90 */
       uint8_t RESERVED_96[12];
  __IO uint32_t MRGD_W0_7_5;                       /**< Memory Region Descriptor, offset: 0x2EA0 */
  __IO uint32_t MRGD_W1_7_5;                       /**< Memory Region Descriptor, offset: 0x2EA4 */
  __IO uint32_t MRGD_W2_7_5;                       /**< Memory Region Descriptor, offset: 0x2EA8 */
  __IO uint32_t MRGD_W3_7_5;                       /**< Memory Region Descriptor, offset: 0x2EAC */
  __IO uint32_t MRGD_W4_7_5;                       /**< Memory Region Descriptor, offset: 0x2EB0 */
       uint8_t RESERVED_97[12];
  __IO uint32_t MRGD_W0_7_6;                       /**< Memory Region Descriptor, offset: 0x2EC0 */
  __IO uint32_t MRGD_W1_7_6;                       /**< Memory Region Descriptor, offset: 0x2EC4 */
  __IO uint32_t MRGD_W2_7_6;                       /**< Memory Region Descriptor, offset: 0x2EC8 */
  __IO uint32_t MRGD_W3_7_6;                       /**< Memory Region Descriptor, offset: 0x2ECC */
  __IO uint32_t MRGD_W4_7_6;                       /**< Memory Region Descriptor, offset: 0x2ED0 */
       uint8_t RESERVED_98[12];
  __IO uint32_t MRGD_W0_7_7;                       /**< Memory Region Descriptor, offset: 0x2EE0 */
  __IO uint32_t MRGD_W1_7_7;                       /**< Memory Region Descriptor, offset: 0x2EE4 */
  __IO uint32_t MRGD_W2_7_7;                       /**< Memory Region Descriptor, offset: 0x2EE8 */
  __IO uint32_t MRGD_W3_7_7;                       /**< Memory Region Descriptor, offset: 0x2EEC */
  __IO uint32_t MRGD_W4_7_7;                       /**< Memory Region Descriptor, offset: 0x2EF0 */
       uint8_t RESERVED_99[268];
  __IO uint32_t MRGD_W0_8_0;                       /**< Memory Region Descriptor, offset: 0x3000 */
  __IO uint32_t MRGD_W1_8_0;                       /**< Memory Region Descriptor, offset: 0x3004 */
  __IO uint32_t MRGD_W2_8_0;                       /**< Memory Region Descriptor, offset: 0x3008 */
  __IO uint32_t MRGD_W3_8_0;                       /**< Memory Region Descriptor, offset: 0x300C */
  __IO uint32_t MRGD_W4_8_0;                       /**< Memory Region Descriptor, offset: 0x3010 */
       uint8_t RESERVED_100[12];
  __IO uint32_t MRGD_W0_8_1;                       /**< Memory Region Descriptor, offset: 0x3020 */
  __IO uint32_t MRGD_W1_8_1;                       /**< Memory Region Descriptor, offset: 0x3024 */
  __IO uint32_t MRGD_W2_8_1;                       /**< Memory Region Descriptor, offset: 0x3028 */
  __IO uint32_t MRGD_W3_8_1;                       /**< Memory Region Descriptor, offset: 0x302C */
  __IO uint32_t MRGD_W4_8_1;                       /**< Memory Region Descriptor, offset: 0x3030 */
       uint8_t RESERVED_101[12];
  __IO uint32_t MRGD_W0_8_2;                       /**< Memory Region Descriptor, offset: 0x3040 */
  __IO uint32_t MRGD_W1_8_2;                       /**< Memory Region Descriptor, offset: 0x3044 */
  __IO uint32_t MRGD_W2_8_2;                       /**< Memory Region Descriptor, offset: 0x3048 */
  __IO uint32_t MRGD_W3_8_2;                       /**< Memory Region Descriptor, offset: 0x304C */
  __IO uint32_t MRGD_W4_8_2;                       /**< Memory Region Descriptor, offset: 0x3050 */
       uint8_t RESERVED_102[12];
  __IO uint32_t MRGD_W0_8_3;                       /**< Memory Region Descriptor, offset: 0x3060 */
  __IO uint32_t MRGD_W1_8_3;                       /**< Memory Region Descriptor, offset: 0x3064 */
  __IO uint32_t MRGD_W2_8_3;                       /**< Memory Region Descriptor, offset: 0x3068 */
  __IO uint32_t MRGD_W3_8_3;                       /**< Memory Region Descriptor, offset: 0x306C */
  __IO uint32_t MRGD_W4_8_3;                       /**< Memory Region Descriptor, offset: 0x3070 */
       uint8_t RESERVED_103[396];
  __IO uint32_t MRGD_W0_9_0;                       /**< Memory Region Descriptor, offset: 0x3200 */
  __IO uint32_t MRGD_W1_9_0;                       /**< Memory Region Descriptor, offset: 0x3204 */
  __IO uint32_t MRGD_W2_9_0;                       /**< Memory Region Descriptor, offset: 0x3208 */
  __IO uint32_t MRGD_W3_9_0;                       /**< Memory Region Descriptor, offset: 0x320C */
  __IO uint32_t MRGD_W4_9_0;                       /**< Memory Region Descriptor, offset: 0x3210 */
       uint8_t RESERVED_104[12];
  __IO uint32_t MRGD_W0_9_1;                       /**< Memory Region Descriptor, offset: 0x3220 */
  __IO uint32_t MRGD_W1_9_1;                       /**< Memory Region Descriptor, offset: 0x3224 */
  __IO uint32_t MRGD_W2_9_1;                       /**< Memory Region Descriptor, offset: 0x3228 */
  __IO uint32_t MRGD_W3_9_1;                       /**< Memory Region Descriptor, offset: 0x322C */
  __IO uint32_t MRGD_W4_9_1;                       /**< Memory Region Descriptor, offset: 0x3230 */
       uint8_t RESERVED_105[12];
  __IO uint32_t MRGD_W0_9_2;                       /**< Memory Region Descriptor, offset: 0x3240 */
  __IO uint32_t MRGD_W1_9_2;                       /**< Memory Region Descriptor, offset: 0x3244 */
  __IO uint32_t MRGD_W2_9_2;                       /**< Memory Region Descriptor, offset: 0x3248 */
  __IO uint32_t MRGD_W3_9_2;                       /**< Memory Region Descriptor, offset: 0x324C */
  __IO uint32_t MRGD_W4_9_2;                       /**< Memory Region Descriptor, offset: 0x3250 */
       uint8_t RESERVED_106[12];
  __IO uint32_t MRGD_W0_9_3;                       /**< Memory Region Descriptor, offset: 0x3260 */
  __IO uint32_t MRGD_W1_9_3;                       /**< Memory Region Descriptor, offset: 0x3264 */
  __IO uint32_t MRGD_W2_9_3;                       /**< Memory Region Descriptor, offset: 0x3268 */
  __IO uint32_t MRGD_W3_9_3;                       /**< Memory Region Descriptor, offset: 0x326C */
  __IO uint32_t MRGD_W4_9_3;                       /**< Memory Region Descriptor, offset: 0x3270 */
       uint8_t RESERVED_107[12];
  __IO uint32_t MRGD_W0_9_4;                       /**< Memory Region Descriptor, offset: 0x3280 */
  __IO uint32_t MRGD_W1_9_4;                       /**< Memory Region Descriptor, offset: 0x3284 */
  __IO uint32_t MRGD_W2_9_4;                       /**< Memory Region Descriptor, offset: 0x3288 */
  __IO uint32_t MRGD_W3_9_4;                       /**< Memory Region Descriptor, offset: 0x328C */
  __IO uint32_t MRGD_W4_9_4;                       /**< Memory Region Descriptor, offset: 0x3290 */
       uint8_t RESERVED_108[12];
  __IO uint32_t MRGD_W0_9_5;                       /**< Memory Region Descriptor, offset: 0x32A0 */
  __IO uint32_t MRGD_W1_9_5;                       /**< Memory Region Descriptor, offset: 0x32A4 */
  __IO uint32_t MRGD_W2_9_5;                       /**< Memory Region Descriptor, offset: 0x32A8 */
  __IO uint32_t MRGD_W3_9_5;                       /**< Memory Region Descriptor, offset: 0x32AC */
  __IO uint32_t MRGD_W4_9_5;                       /**< Memory Region Descriptor, offset: 0x32B0 */
       uint8_t RESERVED_109[12];
  __IO uint32_t MRGD_W0_9_6;                       /**< Memory Region Descriptor, offset: 0x32C0 */
  __IO uint32_t MRGD_W1_9_6;                       /**< Memory Region Descriptor, offset: 0x32C4 */
  __IO uint32_t MRGD_W2_9_6;                       /**< Memory Region Descriptor, offset: 0x32C8 */
  __IO uint32_t MRGD_W3_9_6;                       /**< Memory Region Descriptor, offset: 0x32CC */
  __IO uint32_t MRGD_W4_9_6;                       /**< Memory Region Descriptor, offset: 0x32D0 */
       uint8_t RESERVED_110[12];
  __IO uint32_t MRGD_W0_9_7;                       /**< Memory Region Descriptor, offset: 0x32E0 */
  __IO uint32_t MRGD_W1_9_7;                       /**< Memory Region Descriptor, offset: 0x32E4 */
  __IO uint32_t MRGD_W2_9_7;                       /**< Memory Region Descriptor, offset: 0x32E8 */
  __IO uint32_t MRGD_W3_9_7;                       /**< Memory Region Descriptor, offset: 0x32EC */
  __IO uint32_t MRGD_W4_9_7;                       /**< Memory Region Descriptor, offset: 0x32F0 */
       uint8_t RESERVED_111[268];
  __IO uint32_t MRGD_W0_10_0;                      /**< Memory Region Descriptor, offset: 0x3400 */
  __IO uint32_t MRGD_W1_10_0;                      /**< Memory Region Descriptor, offset: 0x3404 */
  __IO uint32_t MRGD_W2_10_0;                      /**< Memory Region Descriptor, offset: 0x3408 */
  __IO uint32_t MRGD_W3_10_0;                      /**< Memory Region Descriptor, offset: 0x340C */
  __IO uint32_t MRGD_W4_10_0;                      /**< Memory Region Descriptor, offset: 0x3410 */
       uint8_t RESERVED_112[12];
  __IO uint32_t MRGD_W0_10_1;                      /**< Memory Region Descriptor, offset: 0x3420 */
  __IO uint32_t MRGD_W1_10_1;                      /**< Memory Region Descriptor, offset: 0x3424 */
  __IO uint32_t MRGD_W2_10_1;                      /**< Memory Region Descriptor, offset: 0x3428 */
  __IO uint32_t MRGD_W3_10_1;                      /**< Memory Region Descriptor, offset: 0x342C */
  __IO uint32_t MRGD_W4_10_1;                      /**< Memory Region Descriptor, offset: 0x3430 */
       uint8_t RESERVED_113[12];
  __IO uint32_t MRGD_W0_10_2;                      /**< Memory Region Descriptor, offset: 0x3440 */
  __IO uint32_t MRGD_W1_10_2;                      /**< Memory Region Descriptor, offset: 0x3444 */
  __IO uint32_t MRGD_W2_10_2;                      /**< Memory Region Descriptor, offset: 0x3448 */
  __IO uint32_t MRGD_W3_10_2;                      /**< Memory Region Descriptor, offset: 0x344C */
  __IO uint32_t MRGD_W4_10_2;                      /**< Memory Region Descriptor, offset: 0x3450 */
       uint8_t RESERVED_114[12];
  __IO uint32_t MRGD_W0_10_3;                      /**< Memory Region Descriptor, offset: 0x3460 */
  __IO uint32_t MRGD_W1_10_3;                      /**< Memory Region Descriptor, offset: 0x3464 */
  __IO uint32_t MRGD_W2_10_3;                      /**< Memory Region Descriptor, offset: 0x3468 */
  __IO uint32_t MRGD_W3_10_3;                      /**< Memory Region Descriptor, offset: 0x346C */
  __IO uint32_t MRGD_W4_10_3;                      /**< Memory Region Descriptor, offset: 0x3470 */
       uint8_t RESERVED_115[12];
  __IO uint32_t MRGD_W0_10_4;                      /**< Memory Region Descriptor, offset: 0x3480 */
  __IO uint32_t MRGD_W1_10_4;                      /**< Memory Region Descriptor, offset: 0x3484 */
  __IO uint32_t MRGD_W2_10_4;                      /**< Memory Region Descriptor, offset: 0x3488 */
  __IO uint32_t MRGD_W3_10_4;                      /**< Memory Region Descriptor, offset: 0x348C */
  __IO uint32_t MRGD_W4_10_4;                      /**< Memory Region Descriptor, offset: 0x3490 */
       uint8_t RESERVED_116[12];
  __IO uint32_t MRGD_W0_10_5;                      /**< Memory Region Descriptor, offset: 0x34A0 */
  __IO uint32_t MRGD_W1_10_5;                      /**< Memory Region Descriptor, offset: 0x34A4 */
  __IO uint32_t MRGD_W2_10_5;                      /**< Memory Region Descriptor, offset: 0x34A8 */
  __IO uint32_t MRGD_W3_10_5;                      /**< Memory Region Descriptor, offset: 0x34AC */
  __IO uint32_t MRGD_W4_10_5;                      /**< Memory Region Descriptor, offset: 0x34B0 */
       uint8_t RESERVED_117[12];
  __IO uint32_t MRGD_W0_10_6;                      /**< Memory Region Descriptor, offset: 0x34C0 */
  __IO uint32_t MRGD_W1_10_6;                      /**< Memory Region Descriptor, offset: 0x34C4 */
  __IO uint32_t MRGD_W2_10_6;                      /**< Memory Region Descriptor, offset: 0x34C8 */
  __IO uint32_t MRGD_W3_10_6;                      /**< Memory Region Descriptor, offset: 0x34CC */
  __IO uint32_t MRGD_W4_10_6;                      /**< Memory Region Descriptor, offset: 0x34D0 */
       uint8_t RESERVED_118[12];
  __IO uint32_t MRGD_W0_10_7;                      /**< Memory Region Descriptor, offset: 0x34E0 */
  __IO uint32_t MRGD_W1_10_7;                      /**< Memory Region Descriptor, offset: 0x34E4 */
  __IO uint32_t MRGD_W2_10_7;                      /**< Memory Region Descriptor, offset: 0x34E8 */
  __IO uint32_t MRGD_W3_10_7;                      /**< Memory Region Descriptor, offset: 0x34EC */
  __IO uint32_t MRGD_W4_10_7;                      /**< Memory Region Descriptor, offset: 0x34F0 */
       uint8_t RESERVED_119[268];
  __IO uint32_t MRGD_W0_11_0;                      /**< Memory Region Descriptor, offset: 0x3600 */
  __IO uint32_t MRGD_W1_11_0;                      /**< Memory Region Descriptor, offset: 0x3604 */
  __IO uint32_t MRGD_W2_11_0;                      /**< Memory Region Descriptor, offset: 0x3608 */
  __IO uint32_t MRGD_W3_11_0;                      /**< Memory Region Descriptor, offset: 0x360C */
  __IO uint32_t MRGD_W4_11_0;                      /**< Memory Region Descriptor, offset: 0x3610 */
       uint8_t RESERVED_120[12];
  __IO uint32_t MRGD_W0_11_1;                      /**< Memory Region Descriptor, offset: 0x3620 */
  __IO uint32_t MRGD_W1_11_1;                      /**< Memory Region Descriptor, offset: 0x3624 */
  __IO uint32_t MRGD_W2_11_1;                      /**< Memory Region Descriptor, offset: 0x3628 */
  __IO uint32_t MRGD_W3_11_1;                      /**< Memory Region Descriptor, offset: 0x362C */
  __IO uint32_t MRGD_W4_11_1;                      /**< Memory Region Descriptor, offset: 0x3630 */
       uint8_t RESERVED_121[12];
  __IO uint32_t MRGD_W0_11_2;                      /**< Memory Region Descriptor, offset: 0x3640 */
  __IO uint32_t MRGD_W1_11_2;                      /**< Memory Region Descriptor, offset: 0x3644 */
  __IO uint32_t MRGD_W2_11_2;                      /**< Memory Region Descriptor, offset: 0x3648 */
  __IO uint32_t MRGD_W3_11_2;                      /**< Memory Region Descriptor, offset: 0x364C */
  __IO uint32_t MRGD_W4_11_2;                      /**< Memory Region Descriptor, offset: 0x3650 */
       uint8_t RESERVED_122[12];
  __IO uint32_t MRGD_W0_11_3;                      /**< Memory Region Descriptor, offset: 0x3660 */
  __IO uint32_t MRGD_W1_11_3;                      /**< Memory Region Descriptor, offset: 0x3664 */
  __IO uint32_t MRGD_W2_11_3;                      /**< Memory Region Descriptor, offset: 0x3668 */
  __IO uint32_t MRGD_W3_11_3;                      /**< Memory Region Descriptor, offset: 0x366C */
  __IO uint32_t MRGD_W4_11_3;                      /**< Memory Region Descriptor, offset: 0x3670 */
       uint8_t RESERVED_123[396];
  __IO uint32_t MRGD_W0_12_0;                      /**< Memory Region Descriptor, offset: 0x3800 */
  __IO uint32_t MRGD_W1_12_0;                      /**< Memory Region Descriptor, offset: 0x3804 */
  __IO uint32_t MRGD_W2_12_0;                      /**< Memory Region Descriptor, offset: 0x3808 */
  __IO uint32_t MRGD_W3_12_0;                      /**< Memory Region Descriptor, offset: 0x380C */
  __IO uint32_t MRGD_W4_12_0;                      /**< Memory Region Descriptor, offset: 0x3810 */
       uint8_t RESERVED_124[12];
  __IO uint32_t MRGD_W0_12_1;                      /**< Memory Region Descriptor, offset: 0x3820 */
  __IO uint32_t MRGD_W1_12_1;                      /**< Memory Region Descriptor, offset: 0x3824 */
  __IO uint32_t MRGD_W2_12_1;                      /**< Memory Region Descriptor, offset: 0x3828 */
  __IO uint32_t MRGD_W3_12_1;                      /**< Memory Region Descriptor, offset: 0x382C */
  __IO uint32_t MRGD_W4_12_1;                      /**< Memory Region Descriptor, offset: 0x3830 */
       uint8_t RESERVED_125[1996];
  __IO uint32_t MSAC_W0_0_0;                       /**< Memory Slot Access Control, offset: 0x4000 */
  __IO uint32_t MSAC_W1_0_0;                       /**< Memory Slot Access Control, offset: 0x4004 */
  __IO uint32_t MSAC_W0_0_1;                       /**< Memory Slot Access Control, offset: 0x4008 */
  __IO uint32_t MSAC_W1_0_1;                       /**< Memory Slot Access Control, offset: 0x400C */
       uint8_t RESERVED_126[1008];
  __IO uint32_t MSAC_W0_1_0;                       /**< Memory Slot Access Control, offset: 0x4400 */
  __IO uint32_t MSAC_W1_1_0;                       /**< Memory Slot Access Control, offset: 0x4404 */
       uint8_t RESERVED_127[1016];
  __IO uint32_t MSAC_W0_2_0;                       /**< Memory Slot Access Control, offset: 0x4800 */
  __IO uint32_t MSAC_W1_2_0;                       /**< Memory Slot Access Control, offset: 0x4804 */
  __IO uint32_t MSAC_W0_2_1;                       /**< Memory Slot Access Control, offset: 0x4808 */
  __IO uint32_t MSAC_W1_2_1;                       /**< Memory Slot Access Control, offset: 0x480C */
  __IO uint32_t MSAC_W0_2_2;                       /**< Memory Slot Access Control, offset: 0x4810 */
  __IO uint32_t MSAC_W1_2_2;                       /**< Memory Slot Access Control, offset: 0x4814 */
  __IO uint32_t MSAC_W0_2_3;                       /**< Memory Slot Access Control, offset: 0x4818 */
  __IO uint32_t MSAC_W1_2_3;                       /**< Memory Slot Access Control, offset: 0x481C */
  __IO uint32_t MSAC_W0_2_4;                       /**< Memory Slot Access Control, offset: 0x4820 */
  __IO uint32_t MSAC_W1_2_4;                       /**< Memory Slot Access Control, offset: 0x4824 */
  __IO uint32_t MSAC_W0_2_5;                       /**< Memory Slot Access Control, offset: 0x4828 */
  __IO uint32_t MSAC_W1_2_5;                       /**< Memory Slot Access Control, offset: 0x482C */
  __IO uint32_t MSAC_W0_2_6;                       /**< Memory Slot Access Control, offset: 0x4830 */
  __IO uint32_t MSAC_W1_2_6;                       /**< Memory Slot Access Control, offset: 0x4834 */
} XRDC_Type;

/* ----------------------------------------------------------------------------
   -- XRDC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XRDC_Register_Masks XRDC Register Masks
 * @{
 */

/*! @name CR - Control Register */
/*! @{ */

#define XRDC_CR_GVLDM_MASK                       (0x1U)
#define XRDC_CR_GVLDM_SHIFT                      (0U)
/*! GVLDM - Global Valid for MDACs(XRDC global enable/disable).
 *  0b0..XRDC MDACs are disabled.
 *  0b1..XRDC MDACs are enabled.
 */
#define XRDC_CR_GVLDM(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDM_SHIFT)) & XRDC_CR_GVLDM_MASK)

#define XRDC_CR_HRL_MASK                         (0x1EU)
#define XRDC_CR_HRL_SHIFT                        (1U)
/*! HRL - Hardware Revision Level */
#define XRDC_CR_HRL(x)                           (((uint32_t)(((uint32_t)(x)) << XRDC_CR_HRL_SHIFT)) & XRDC_CR_HRL_MASK)

#define XRDC_CR_GVLDP_MASK                       (0x4000U)
#define XRDC_CR_GVLDP_SHIFT                      (14U)
/*! GVLDP - Global Valid for PACs/MSCs
 *  0b0..XRDC PACs/MSCs are disabled.
 *  0b1..XRDC PACs/MSCs are enabled.
 */
#define XRDC_CR_GVLDP(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDP_SHIFT)) & XRDC_CR_GVLDP_MASK)

#define XRDC_CR_GVLDC_MASK                       (0x8000U)
#define XRDC_CR_GVLDC_SHIFT                      (15U)
/*! GVLDC - Global Valid for MRCs
 *  0b0..XRDC MRCs are disabled.
 *  0b1..XRDC MRCs are enabled.
 */
#define XRDC_CR_GVLDC(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDC_SHIFT)) & XRDC_CR_GVLDC_MASK)

#define XRDC_CR_DBDS_MASK                        (0xF0000U)
#define XRDC_CR_DBDS_SHIFT                       (16U)
/*! DBDS - Deny by Default (DBD) Status
 *  0b0000..Not in Deny by Default window
 *  0b1111..All accesses allowed
 *  0b1000..Deny by default and (S400 + CA35 SecPriv allowed)
 *  0b1001..Deny by default and (S400 + CM33 allowed)
 *  0b1010..Deny by default and (S400 + CM33 SecPriv allowed)
 *  0b1011..Deny by default and (S400 + CM33 SecPriv + CA35 SecPriv allowed)
 *  0b1100..Deny by default and (S400 allowed)
 *  0b1110..All accesses denied
 */
#define XRDC_CR_DBDS(x)                          (((uint32_t)(((uint32_t)(x)) << XRDC_CR_DBDS_SHIFT)) & XRDC_CR_DBDS_MASK)

#define XRDC_CR_LK1_MASK                         (0x40000000U)
#define XRDC_CR_LK1_SHIFT                        (30U)
/*! LK1 - Lock Status
 *  0b0..The CR can be written by any secure privileged write.
 *  0b1..The CR is locked (read-only) until the next reset.
 */
#define XRDC_CR_LK1(x)                           (((uint32_t)(((uint32_t)(x)) << XRDC_CR_LK1_SHIFT)) & XRDC_CR_LK1_MASK)
/*! @} */

/*! @name HWCFG0 - Hardware Configuration Register 0 */
/*! @{ */

#define XRDC_HWCFG0_NDID_MASK                    (0xFFU)
#define XRDC_HWCFG0_NDID_SHIFT                   (0U)
/*! NDID - Number of domains */
#define XRDC_HWCFG0_NDID(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NDID_SHIFT)) & XRDC_HWCFG0_NDID_MASK)

#define XRDC_HWCFG0_NMSTR_MASK                   (0xFF00U)
#define XRDC_HWCFG0_NMSTR_SHIFT                  (8U)
/*! NMSTR - Number of bus masters */
#define XRDC_HWCFG0_NMSTR(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMSTR_SHIFT)) & XRDC_HWCFG0_NMSTR_MASK)

#define XRDC_HWCFG0_NMRC_MASK                    (0xFF0000U)
#define XRDC_HWCFG0_NMRC_SHIFT                   (16U)
/*! NMRC - Number of MRCs */
#define XRDC_HWCFG0_NMRC(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMRC_SHIFT)) & XRDC_HWCFG0_NMRC_MASK)

#define XRDC_HWCFG0_NPAC_MASK                    (0x3000000U)
#define XRDC_HWCFG0_NPAC_SHIFT                   (24U)
/*! NPAC - Number of PACs */
#define XRDC_HWCFG0_NPAC(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NPAC_SHIFT)) & XRDC_HWCFG0_NPAC_MASK)

#define XRDC_HWCFG0_NMSC_MASK                    (0xC000000U)
#define XRDC_HWCFG0_NMSC_SHIFT                   (26U)
/*! NMSC - Number of MSCs */
#define XRDC_HWCFG0_NMSC(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMSC_SHIFT)) & XRDC_HWCFG0_NMSC_MASK)

#define XRDC_HWCFG0_MID_MASK                     (0xF0000000U)
#define XRDC_HWCFG0_MID_SHIFT                    (28U)
/*! MID - Module ID */
#define XRDC_HWCFG0_MID(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_MID_SHIFT)) & XRDC_HWCFG0_MID_MASK)
/*! @} */

/*! @name HWCFG1 - Hardware Configuration Register 1 */
/*! @{ */

#define XRDC_HWCFG1_DID_MASK                     (0xFU)
#define XRDC_HWCFG1_DID_SHIFT                    (0U)
/*! DID - Domain identifier number */
#define XRDC_HWCFG1_DID(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG1_DID_SHIFT)) & XRDC_HWCFG1_DID_MASK)
/*! @} */

/*! @name HWCFG2 - Hardware Configuration Register 2 */
/*! @{ */

#define XRDC_HWCFG2_PIDP0_MASK                   (0x1U)
#define XRDC_HWCFG2_PIDP0_SHIFT                  (0U)
/*! PIDP0 - Process identifier
 *  0b0..Bus master 0 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 0 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP0(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP0_SHIFT)) & XRDC_HWCFG2_PIDP0_MASK)

#define XRDC_HWCFG2_PIDP1_MASK                   (0x2U)
#define XRDC_HWCFG2_PIDP1_SHIFT                  (1U)
/*! PIDP1 - Process identifier
 *  0b0..Bus master 1 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 1 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP1(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP1_SHIFT)) & XRDC_HWCFG2_PIDP1_MASK)

#define XRDC_HWCFG2_PIDP2_MASK                   (0x4U)
#define XRDC_HWCFG2_PIDP2_SHIFT                  (2U)
/*! PIDP2 - Process identifier
 *  0b0..Bus master 2 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 2 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP2(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP2_SHIFT)) & XRDC_HWCFG2_PIDP2_MASK)

#define XRDC_HWCFG2_PIDP3_MASK                   (0x8U)
#define XRDC_HWCFG2_PIDP3_SHIFT                  (3U)
/*! PIDP3 - Process identifier
 *  0b0..Bus master 3 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 3 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP3(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP3_SHIFT)) & XRDC_HWCFG2_PIDP3_MASK)

#define XRDC_HWCFG2_PIDP4_MASK                   (0x10U)
#define XRDC_HWCFG2_PIDP4_SHIFT                  (4U)
/*! PIDP4 - Process identifier
 *  0b0..Bus master 4 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 4 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP4(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP4_SHIFT)) & XRDC_HWCFG2_PIDP4_MASK)

#define XRDC_HWCFG2_PIDP5_MASK                   (0x20U)
#define XRDC_HWCFG2_PIDP5_SHIFT                  (5U)
/*! PIDP5 - Process identifier
 *  0b0..Bus master 5 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 5 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP5(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP5_SHIFT)) & XRDC_HWCFG2_PIDP5_MASK)

#define XRDC_HWCFG2_PIDP6_MASK                   (0x40U)
#define XRDC_HWCFG2_PIDP6_SHIFT                  (6U)
/*! PIDP6 - Process identifier
 *  0b0..Bus master 6 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 6 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP6(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP6_SHIFT)) & XRDC_HWCFG2_PIDP6_MASK)

#define XRDC_HWCFG2_PIDP7_MASK                   (0x80U)
#define XRDC_HWCFG2_PIDP7_SHIFT                  (7U)
/*! PIDP7 - Process identifier
 *  0b0..Bus master 7 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 7 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP7(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP7_SHIFT)) & XRDC_HWCFG2_PIDP7_MASK)

#define XRDC_HWCFG2_PIDP8_MASK                   (0x100U)
#define XRDC_HWCFG2_PIDP8_SHIFT                  (8U)
/*! PIDP8 - Process identifier
 *  0b0..Bus master 8 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 8 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP8(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP8_SHIFT)) & XRDC_HWCFG2_PIDP8_MASK)

#define XRDC_HWCFG2_PIDP9_MASK                   (0x200U)
#define XRDC_HWCFG2_PIDP9_SHIFT                  (9U)
/*! PIDP9 - Process identifier
 *  0b0..Bus master 9 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 9 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP9(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP9_SHIFT)) & XRDC_HWCFG2_PIDP9_MASK)

#define XRDC_HWCFG2_PIDP10_MASK                  (0x400U)
#define XRDC_HWCFG2_PIDP10_SHIFT                 (10U)
/*! PIDP10 - Process identifier
 *  0b0..Bus master 10 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 10 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP10(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP10_SHIFT)) & XRDC_HWCFG2_PIDP10_MASK)

#define XRDC_HWCFG2_PIDP11_MASK                  (0x800U)
#define XRDC_HWCFG2_PIDP11_SHIFT                 (11U)
/*! PIDP11 - Process identifier
 *  0b0..Bus master 11 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 11 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP11(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP11_SHIFT)) & XRDC_HWCFG2_PIDP11_MASK)

#define XRDC_HWCFG2_PIDP12_MASK                  (0x1000U)
#define XRDC_HWCFG2_PIDP12_SHIFT                 (12U)
/*! PIDP12 - Process identifier
 *  0b0..Bus master 12 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 12 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP12(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP12_SHIFT)) & XRDC_HWCFG2_PIDP12_MASK)

#define XRDC_HWCFG2_PIDP13_MASK                  (0x2000U)
#define XRDC_HWCFG2_PIDP13_SHIFT                 (13U)
/*! PIDP13 - Process identifier
 *  0b0..Bus master 13 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 13 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP13(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP13_SHIFT)) & XRDC_HWCFG2_PIDP13_MASK)

#define XRDC_HWCFG2_PIDP14_MASK                  (0x4000U)
#define XRDC_HWCFG2_PIDP14_SHIFT                 (14U)
/*! PIDP14 - Process identifier
 *  0b0..Bus master 14 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 14 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP14(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP14_SHIFT)) & XRDC_HWCFG2_PIDP14_MASK)

#define XRDC_HWCFG2_PIDP15_MASK                  (0x8000U)
#define XRDC_HWCFG2_PIDP15_SHIFT                 (15U)
/*! PIDP15 - Process identifier
 *  0b0..Bus master 15 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 15 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP15(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP15_SHIFT)) & XRDC_HWCFG2_PIDP15_MASK)

#define XRDC_HWCFG2_PIDP16_MASK                  (0x10000U)
#define XRDC_HWCFG2_PIDP16_SHIFT                 (16U)
/*! PIDP16 - Process identifier
 *  0b0..Bus master 16 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 16 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP16(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP16_SHIFT)) & XRDC_HWCFG2_PIDP16_MASK)

#define XRDC_HWCFG2_PIDP17_MASK                  (0x20000U)
#define XRDC_HWCFG2_PIDP17_SHIFT                 (17U)
/*! PIDP17 - Process identifier
 *  0b0..Bus master 17 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 17 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP17(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP17_SHIFT)) & XRDC_HWCFG2_PIDP17_MASK)

#define XRDC_HWCFG2_PIDP18_MASK                  (0x40000U)
#define XRDC_HWCFG2_PIDP18_SHIFT                 (18U)
/*! PIDP18 - Process identifier
 *  0b0..Bus master 18 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 18 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP18(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP18_SHIFT)) & XRDC_HWCFG2_PIDP18_MASK)

#define XRDC_HWCFG2_PIDP19_MASK                  (0x80000U)
#define XRDC_HWCFG2_PIDP19_SHIFT                 (19U)
/*! PIDP19 - Process identifier
 *  0b0..Bus master 19 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 19 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP19(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP19_SHIFT)) & XRDC_HWCFG2_PIDP19_MASK)

#define XRDC_HWCFG2_PIDP20_MASK                  (0x100000U)
#define XRDC_HWCFG2_PIDP20_SHIFT                 (20U)
/*! PIDP20 - Process identifier
 *  0b0..Bus master 20 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 20 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP20(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP20_SHIFT)) & XRDC_HWCFG2_PIDP20_MASK)

#define XRDC_HWCFG2_PIDP21_MASK                  (0x200000U)
#define XRDC_HWCFG2_PIDP21_SHIFT                 (21U)
/*! PIDP21 - Process identifier
 *  0b0..Bus master 21 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 21 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP21(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP21_SHIFT)) & XRDC_HWCFG2_PIDP21_MASK)

#define XRDC_HWCFG2_PIDP22_MASK                  (0x400000U)
#define XRDC_HWCFG2_PIDP22_SHIFT                 (22U)
/*! PIDP22 - Process identifier
 *  0b0..Bus master 22 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 22 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP22(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP22_SHIFT)) & XRDC_HWCFG2_PIDP22_MASK)

#define XRDC_HWCFG2_PIDP23_MASK                  (0x800000U)
#define XRDC_HWCFG2_PIDP23_SHIFT                 (23U)
/*! PIDP23 - Process identifier
 *  0b0..Bus master 23 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 23 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP23(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP23_SHIFT)) & XRDC_HWCFG2_PIDP23_MASK)

#define XRDC_HWCFG2_PIDP24_MASK                  (0x1000000U)
#define XRDC_HWCFG2_PIDP24_SHIFT                 (24U)
/*! PIDP24 - Process identifier
 *  0b0..Bus master 24 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 24 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP24(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP24_SHIFT)) & XRDC_HWCFG2_PIDP24_MASK)

#define XRDC_HWCFG2_PIDP25_MASK                  (0x2000000U)
#define XRDC_HWCFG2_PIDP25_SHIFT                 (25U)
/*! PIDP25 - Process identifier
 *  0b0..Bus master 25 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 25 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP25(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP25_SHIFT)) & XRDC_HWCFG2_PIDP25_MASK)

#define XRDC_HWCFG2_PIDP26_MASK                  (0x4000000U)
#define XRDC_HWCFG2_PIDP26_SHIFT                 (26U)
/*! PIDP26 - Process identifier
 *  0b0..Bus master 26 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 26 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP26(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP26_SHIFT)) & XRDC_HWCFG2_PIDP26_MASK)

#define XRDC_HWCFG2_PIDP27_MASK                  (0x8000000U)
#define XRDC_HWCFG2_PIDP27_SHIFT                 (27U)
/*! PIDP27 - Process identifier
 *  0b0..Bus master 27 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 27 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP27(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP27_SHIFT)) & XRDC_HWCFG2_PIDP27_MASK)

#define XRDC_HWCFG2_PIDP28_MASK                  (0x10000000U)
#define XRDC_HWCFG2_PIDP28_SHIFT                 (28U)
/*! PIDP28 - Process identifier
 *  0b0..Bus master 28 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 28 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP28(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP28_SHIFT)) & XRDC_HWCFG2_PIDP28_MASK)

#define XRDC_HWCFG2_PIDP29_MASK                  (0x20000000U)
#define XRDC_HWCFG2_PIDP29_SHIFT                 (29U)
/*! PIDP29 - Process identifier
 *  0b0..Bus master 29 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 29 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP29(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP29_SHIFT)) & XRDC_HWCFG2_PIDP29_MASK)

#define XRDC_HWCFG2_PIDP30_MASK                  (0x40000000U)
#define XRDC_HWCFG2_PIDP30_SHIFT                 (30U)
/*! PIDP30 - Process identifier
 *  0b0..Bus master 30 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 30 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP30(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP30_SHIFT)) & XRDC_HWCFG2_PIDP30_MASK)

#define XRDC_HWCFG2_PIDP31_MASK                  (0x80000000U)
#define XRDC_HWCFG2_PIDP31_SHIFT                 (31U)
/*! PIDP31 - Process identifier
 *  0b0..Bus master 31 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
 *  0b1..Bus master 31 sources a process identifier register to the XRDC_MDAC logic.
 */
#define XRDC_HWCFG2_PIDP31(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP31_SHIFT)) & XRDC_HWCFG2_PIDP31_MASK)
/*! @} */

/*! @name HWCFG3 - Hardware Configuration Register 3 */
/*! @{ */

#define XRDC_HWCFG3_PIDPn_MASK                   (0xFFFFFFFFU)
#define XRDC_HWCFG3_PIDPn_SHIFT                  (0U)
/*! PIDPn - Process identifier */
#define XRDC_HWCFG3_PIDPn(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDPn_SHIFT)) & XRDC_HWCFG3_PIDPn_MASK)
/*! @} */

/*! @name MDACFG - Master Domain Assignment Configuration Register */
/*! @{ */

#define XRDC_MDACFG_NMDAR_MASK                   (0xFU)
#define XRDC_MDACFG_NMDAR_SHIFT                  (0U)
/*! NMDAR - Number of master domain assignment registers for bus master m */
#define XRDC_MDACFG_NMDAR(x)                     (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NMDAR_SHIFT)) & XRDC_MDACFG_NMDAR_MASK)

#define XRDC_MDACFG_NCM_MASK                     (0x80U)
#define XRDC_MDACFG_NCM_SHIFT                    (7U)
/*! NCM - Non-CPU Master
 *  0b0..Bus master is a processor.
 *  0b1..Bus master is a non-processor.
 */
#define XRDC_MDACFG_NCM(x)                       (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NCM_SHIFT)) & XRDC_MDACFG_NCM_MASK)
/*! @} */

/* The count of XRDC_MDACFG */
#define XRDC_MDACFG_COUNT                        (17U)

/*! @name MRCFG - Memory Region Configuration Register */
/*! @{ */

#define XRDC_MRCFG_NMRGD_MASK                    (0x1FU)
#define XRDC_MRCFG_NMRGD_SHIFT                   (0U)
/*! NMRGD - Number of memory region descriptors for memory region controller n */
#define XRDC_MRCFG_NMRGD(x)                      (((uint8_t)(((uint8_t)(x)) << XRDC_MRCFG_NMRGD_SHIFT)) & XRDC_MRCFG_NMRGD_MASK)
/*! @} */

/* The count of XRDC_MRCFG */
#define XRDC_MRCFG_COUNT                         (13U)

/*! @name FDID - Fault Domain ID */
/*! @{ */

#define XRDC_FDID_FDID_MASK                      (0xFU)
#define XRDC_FDID_FDID_SHIFT                     (0U)
/*! FDID - Domain ID of Faulted Access */
#define XRDC_FDID_FDID(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_FDID_FDID_SHIFT)) & XRDC_FDID_FDID_MASK)
/*! @} */

/*! @name DERRLOC - Domain Error Location Register */
/*! @{ */

#define XRDC_DERRLOC_MRCINST_MASK                (0xFFFFU)
#define XRDC_DERRLOC_MRCINST_SHIFT               (0U)
/*! MRCINST - MRC instance */
#define XRDC_DERRLOC_MRCINST(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_MRCINST_SHIFT)) & XRDC_DERRLOC_MRCINST_MASK)

#define XRDC_DERRLOC_PACINST_MASK                (0xF0000U)
#define XRDC_DERRLOC_PACINST_SHIFT               (16U)
/*! PACINST - PAC instance */
#define XRDC_DERRLOC_PACINST(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_PACINST_SHIFT)) & XRDC_DERRLOC_PACINST_MASK)

#define XRDC_DERRLOC_MSCINST_MASK                (0xF00000U)
#define XRDC_DERRLOC_MSCINST_SHIFT               (20U)
/*! MSCINST - MSC instance */
#define XRDC_DERRLOC_MSCINST(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_MSCINST_SHIFT)) & XRDC_DERRLOC_MSCINST_MASK)
/*! @} */

/* The count of XRDC_DERRLOC */
#define XRDC_DERRLOC_COUNT                       (8U)

/*! @name DERR_W0_0 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_0_EADDR_MASK                (0xFFFFFFFFU)
#define XRDC_DERR_W0_0_EADDR_SHIFT               (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_0_EADDR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_0_EADDR_SHIFT)) & XRDC_DERR_W0_0_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_0 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_0_EDID_MASK                 (0xFU)
#define XRDC_DERR_W1_0_EDID_SHIFT                (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_0_EDID(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_0_EDID_SHIFT)) & XRDC_DERR_W1_0_EDID_MASK)

#define XRDC_DERR_W1_0_EATR_MASK                 (0x700U)
#define XRDC_DERR_W1_0_EATR_SHIFT                (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_0_EATR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_0_EATR_SHIFT)) & XRDC_DERR_W1_0_EATR_MASK)

#define XRDC_DERR_W1_0_ERW_MASK                  (0x800U)
#define XRDC_DERR_W1_0_ERW_SHIFT                 (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_0_ERW(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_0_ERW_SHIFT)) & XRDC_DERR_W1_0_ERW_MASK)

#define XRDC_DERR_W1_0_EPORT_MASK                (0x7000000U)
#define XRDC_DERR_W1_0_EPORT_SHIFT               (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_0_EPORT(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_0_EPORT_SHIFT)) & XRDC_DERR_W1_0_EPORT_MASK)

#define XRDC_DERR_W1_0_EST_MASK                  (0xC0000000U)
#define XRDC_DERR_W1_0_EST_SHIFT                 (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_0_EST(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_0_EST_SHIFT)) & XRDC_DERR_W1_0_EST_MASK)
/*! @} */

/*! @name DERR_W3_0 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_0_RECR_MASK                 (0xC0000000U)
#define XRDC_DERR_W3_0_RECR_SHIFT                (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_0_RECR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_0_RECR_SHIFT)) & XRDC_DERR_W3_0_RECR_MASK)
/*! @} */

/*! @name DERR_W0_1 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_1_EADDR_MASK                (0xFFFFFFFFU)
#define XRDC_DERR_W0_1_EADDR_SHIFT               (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_1_EADDR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_1_EADDR_SHIFT)) & XRDC_DERR_W0_1_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_1 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_1_EDID_MASK                 (0xFU)
#define XRDC_DERR_W1_1_EDID_SHIFT                (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_1_EDID(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_1_EDID_SHIFT)) & XRDC_DERR_W1_1_EDID_MASK)

#define XRDC_DERR_W1_1_EATR_MASK                 (0x700U)
#define XRDC_DERR_W1_1_EATR_SHIFT                (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_1_EATR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_1_EATR_SHIFT)) & XRDC_DERR_W1_1_EATR_MASK)

#define XRDC_DERR_W1_1_ERW_MASK                  (0x800U)
#define XRDC_DERR_W1_1_ERW_SHIFT                 (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_1_ERW(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_1_ERW_SHIFT)) & XRDC_DERR_W1_1_ERW_MASK)

#define XRDC_DERR_W1_1_EPORT_MASK                (0x7000000U)
#define XRDC_DERR_W1_1_EPORT_SHIFT               (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_1_EPORT(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_1_EPORT_SHIFT)) & XRDC_DERR_W1_1_EPORT_MASK)

#define XRDC_DERR_W1_1_EST_MASK                  (0xC0000000U)
#define XRDC_DERR_W1_1_EST_SHIFT                 (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_1_EST(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_1_EST_SHIFT)) & XRDC_DERR_W1_1_EST_MASK)
/*! @} */

/*! @name DERR_W3_1 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_1_RECR_MASK                 (0xC0000000U)
#define XRDC_DERR_W3_1_RECR_SHIFT                (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_1_RECR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_1_RECR_SHIFT)) & XRDC_DERR_W3_1_RECR_MASK)
/*! @} */

/*! @name DERR_W0_2 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_2_EADDR_MASK                (0xFFFFFFFFU)
#define XRDC_DERR_W0_2_EADDR_SHIFT               (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_2_EADDR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_2_EADDR_SHIFT)) & XRDC_DERR_W0_2_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_2 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_2_EDID_MASK                 (0xFU)
#define XRDC_DERR_W1_2_EDID_SHIFT                (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_2_EDID(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_2_EDID_SHIFT)) & XRDC_DERR_W1_2_EDID_MASK)

#define XRDC_DERR_W1_2_EATR_MASK                 (0x700U)
#define XRDC_DERR_W1_2_EATR_SHIFT                (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_2_EATR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_2_EATR_SHIFT)) & XRDC_DERR_W1_2_EATR_MASK)

#define XRDC_DERR_W1_2_ERW_MASK                  (0x800U)
#define XRDC_DERR_W1_2_ERW_SHIFT                 (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_2_ERW(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_2_ERW_SHIFT)) & XRDC_DERR_W1_2_ERW_MASK)

#define XRDC_DERR_W1_2_EPORT_MASK                (0x7000000U)
#define XRDC_DERR_W1_2_EPORT_SHIFT               (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_2_EPORT(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_2_EPORT_SHIFT)) & XRDC_DERR_W1_2_EPORT_MASK)

#define XRDC_DERR_W1_2_EST_MASK                  (0xC0000000U)
#define XRDC_DERR_W1_2_EST_SHIFT                 (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_2_EST(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_2_EST_SHIFT)) & XRDC_DERR_W1_2_EST_MASK)
/*! @} */

/*! @name DERR_W3_2 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_2_RECR_MASK                 (0xC0000000U)
#define XRDC_DERR_W3_2_RECR_SHIFT                (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_2_RECR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_2_RECR_SHIFT)) & XRDC_DERR_W3_2_RECR_MASK)
/*! @} */

/*! @name DERR_W0_3 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_3_EADDR_MASK                (0xFFFFFFFFU)
#define XRDC_DERR_W0_3_EADDR_SHIFT               (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_3_EADDR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_3_EADDR_SHIFT)) & XRDC_DERR_W0_3_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_3 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_3_EDID_MASK                 (0xFU)
#define XRDC_DERR_W1_3_EDID_SHIFT                (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_3_EDID(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_3_EDID_SHIFT)) & XRDC_DERR_W1_3_EDID_MASK)

#define XRDC_DERR_W1_3_EATR_MASK                 (0x700U)
#define XRDC_DERR_W1_3_EATR_SHIFT                (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_3_EATR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_3_EATR_SHIFT)) & XRDC_DERR_W1_3_EATR_MASK)

#define XRDC_DERR_W1_3_ERW_MASK                  (0x800U)
#define XRDC_DERR_W1_3_ERW_SHIFT                 (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_3_ERW(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_3_ERW_SHIFT)) & XRDC_DERR_W1_3_ERW_MASK)

#define XRDC_DERR_W1_3_EPORT_MASK                (0x7000000U)
#define XRDC_DERR_W1_3_EPORT_SHIFT               (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_3_EPORT(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_3_EPORT_SHIFT)) & XRDC_DERR_W1_3_EPORT_MASK)

#define XRDC_DERR_W1_3_EST_MASK                  (0xC0000000U)
#define XRDC_DERR_W1_3_EST_SHIFT                 (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_3_EST(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_3_EST_SHIFT)) & XRDC_DERR_W1_3_EST_MASK)
/*! @} */

/*! @name DERR_W3_3 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_3_RECR_MASK                 (0xC0000000U)
#define XRDC_DERR_W3_3_RECR_SHIFT                (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_3_RECR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_3_RECR_SHIFT)) & XRDC_DERR_W3_3_RECR_MASK)
/*! @} */

/*! @name DERR_W0_4 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_4_EADDR_MASK                (0xFFFFFFFFU)
#define XRDC_DERR_W0_4_EADDR_SHIFT               (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_4_EADDR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_4_EADDR_SHIFT)) & XRDC_DERR_W0_4_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_4 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_4_EDID_MASK                 (0xFU)
#define XRDC_DERR_W1_4_EDID_SHIFT                (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_4_EDID(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_4_EDID_SHIFT)) & XRDC_DERR_W1_4_EDID_MASK)

#define XRDC_DERR_W1_4_EATR_MASK                 (0x700U)
#define XRDC_DERR_W1_4_EATR_SHIFT                (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_4_EATR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_4_EATR_SHIFT)) & XRDC_DERR_W1_4_EATR_MASK)

#define XRDC_DERR_W1_4_ERW_MASK                  (0x800U)
#define XRDC_DERR_W1_4_ERW_SHIFT                 (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_4_ERW(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_4_ERW_SHIFT)) & XRDC_DERR_W1_4_ERW_MASK)

#define XRDC_DERR_W1_4_EPORT_MASK                (0x7000000U)
#define XRDC_DERR_W1_4_EPORT_SHIFT               (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_4_EPORT(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_4_EPORT_SHIFT)) & XRDC_DERR_W1_4_EPORT_MASK)

#define XRDC_DERR_W1_4_EST_MASK                  (0xC0000000U)
#define XRDC_DERR_W1_4_EST_SHIFT                 (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_4_EST(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_4_EST_SHIFT)) & XRDC_DERR_W1_4_EST_MASK)
/*! @} */

/*! @name DERR_W3_4 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_4_RECR_MASK                 (0xC0000000U)
#define XRDC_DERR_W3_4_RECR_SHIFT                (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_4_RECR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_4_RECR_SHIFT)) & XRDC_DERR_W3_4_RECR_MASK)
/*! @} */

/*! @name DERR_W0_5 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_5_EADDR_MASK                (0xFFFFFFFFU)
#define XRDC_DERR_W0_5_EADDR_SHIFT               (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_5_EADDR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_5_EADDR_SHIFT)) & XRDC_DERR_W0_5_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_5 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_5_EDID_MASK                 (0xFU)
#define XRDC_DERR_W1_5_EDID_SHIFT                (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_5_EDID(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_5_EDID_SHIFT)) & XRDC_DERR_W1_5_EDID_MASK)

#define XRDC_DERR_W1_5_EATR_MASK                 (0x700U)
#define XRDC_DERR_W1_5_EATR_SHIFT                (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_5_EATR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_5_EATR_SHIFT)) & XRDC_DERR_W1_5_EATR_MASK)

#define XRDC_DERR_W1_5_ERW_MASK                  (0x800U)
#define XRDC_DERR_W1_5_ERW_SHIFT                 (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_5_ERW(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_5_ERW_SHIFT)) & XRDC_DERR_W1_5_ERW_MASK)

#define XRDC_DERR_W1_5_EPORT_MASK                (0x7000000U)
#define XRDC_DERR_W1_5_EPORT_SHIFT               (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_5_EPORT(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_5_EPORT_SHIFT)) & XRDC_DERR_W1_5_EPORT_MASK)

#define XRDC_DERR_W1_5_EST_MASK                  (0xC0000000U)
#define XRDC_DERR_W1_5_EST_SHIFT                 (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_5_EST(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_5_EST_SHIFT)) & XRDC_DERR_W1_5_EST_MASK)
/*! @} */

/*! @name DERR_W3_5 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_5_RECR_MASK                 (0xC0000000U)
#define XRDC_DERR_W3_5_RECR_SHIFT                (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_5_RECR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_5_RECR_SHIFT)) & XRDC_DERR_W3_5_RECR_MASK)
/*! @} */

/*! @name DERR_W0_6 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_6_EADDR_MASK                (0xFFFFFFFFU)
#define XRDC_DERR_W0_6_EADDR_SHIFT               (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_6_EADDR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_6_EADDR_SHIFT)) & XRDC_DERR_W0_6_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_6 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_6_EDID_MASK                 (0xFU)
#define XRDC_DERR_W1_6_EDID_SHIFT                (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_6_EDID(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_6_EDID_SHIFT)) & XRDC_DERR_W1_6_EDID_MASK)

#define XRDC_DERR_W1_6_EATR_MASK                 (0x700U)
#define XRDC_DERR_W1_6_EATR_SHIFT                (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_6_EATR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_6_EATR_SHIFT)) & XRDC_DERR_W1_6_EATR_MASK)

#define XRDC_DERR_W1_6_ERW_MASK                  (0x800U)
#define XRDC_DERR_W1_6_ERW_SHIFT                 (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_6_ERW(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_6_ERW_SHIFT)) & XRDC_DERR_W1_6_ERW_MASK)

#define XRDC_DERR_W1_6_EPORT_MASK                (0x7000000U)
#define XRDC_DERR_W1_6_EPORT_SHIFT               (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_6_EPORT(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_6_EPORT_SHIFT)) & XRDC_DERR_W1_6_EPORT_MASK)

#define XRDC_DERR_W1_6_EST_MASK                  (0xC0000000U)
#define XRDC_DERR_W1_6_EST_SHIFT                 (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_6_EST(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_6_EST_SHIFT)) & XRDC_DERR_W1_6_EST_MASK)
/*! @} */

/*! @name DERR_W3_6 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_6_RECR_MASK                 (0xC0000000U)
#define XRDC_DERR_W3_6_RECR_SHIFT                (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_6_RECR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_6_RECR_SHIFT)) & XRDC_DERR_W3_6_RECR_MASK)
/*! @} */

/*! @name DERR_W0_7 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_7_EADDR_MASK                (0xFFFFFFFFU)
#define XRDC_DERR_W0_7_EADDR_SHIFT               (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_7_EADDR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_7_EADDR_SHIFT)) & XRDC_DERR_W0_7_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_7 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_7_EDID_MASK                 (0xFU)
#define XRDC_DERR_W1_7_EDID_SHIFT                (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_7_EDID(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_7_EDID_SHIFT)) & XRDC_DERR_W1_7_EDID_MASK)

#define XRDC_DERR_W1_7_EATR_MASK                 (0x700U)
#define XRDC_DERR_W1_7_EATR_SHIFT                (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_7_EATR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_7_EATR_SHIFT)) & XRDC_DERR_W1_7_EATR_MASK)

#define XRDC_DERR_W1_7_ERW_MASK                  (0x800U)
#define XRDC_DERR_W1_7_ERW_SHIFT                 (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_7_ERW(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_7_ERW_SHIFT)) & XRDC_DERR_W1_7_ERW_MASK)

#define XRDC_DERR_W1_7_EPORT_MASK                (0x7000000U)
#define XRDC_DERR_W1_7_EPORT_SHIFT               (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_7_EPORT(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_7_EPORT_SHIFT)) & XRDC_DERR_W1_7_EPORT_MASK)

#define XRDC_DERR_W1_7_EST_MASK                  (0xC0000000U)
#define XRDC_DERR_W1_7_EST_SHIFT                 (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_7_EST(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_7_EST_SHIFT)) & XRDC_DERR_W1_7_EST_MASK)
/*! @} */

/*! @name DERR_W3_7 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_7_RECR_MASK                 (0xC0000000U)
#define XRDC_DERR_W3_7_RECR_SHIFT                (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_7_RECR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_7_RECR_SHIFT)) & XRDC_DERR_W3_7_RECR_MASK)
/*! @} */

/*! @name DERR_W0_8 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_8_EADDR_MASK                (0xFFFFFFFFU)
#define XRDC_DERR_W0_8_EADDR_SHIFT               (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_8_EADDR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_8_EADDR_SHIFT)) & XRDC_DERR_W0_8_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_8 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_8_EDID_MASK                 (0xFU)
#define XRDC_DERR_W1_8_EDID_SHIFT                (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_8_EDID(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_8_EDID_SHIFT)) & XRDC_DERR_W1_8_EDID_MASK)

#define XRDC_DERR_W1_8_EATR_MASK                 (0x700U)
#define XRDC_DERR_W1_8_EATR_SHIFT                (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_8_EATR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_8_EATR_SHIFT)) & XRDC_DERR_W1_8_EATR_MASK)

#define XRDC_DERR_W1_8_ERW_MASK                  (0x800U)
#define XRDC_DERR_W1_8_ERW_SHIFT                 (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_8_ERW(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_8_ERW_SHIFT)) & XRDC_DERR_W1_8_ERW_MASK)

#define XRDC_DERR_W1_8_EPORT_MASK                (0x7000000U)
#define XRDC_DERR_W1_8_EPORT_SHIFT               (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_8_EPORT(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_8_EPORT_SHIFT)) & XRDC_DERR_W1_8_EPORT_MASK)

#define XRDC_DERR_W1_8_EST_MASK                  (0xC0000000U)
#define XRDC_DERR_W1_8_EST_SHIFT                 (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_8_EST(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_8_EST_SHIFT)) & XRDC_DERR_W1_8_EST_MASK)
/*! @} */

/*! @name DERR_W3_8 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_8_RECR_MASK                 (0xC0000000U)
#define XRDC_DERR_W3_8_RECR_SHIFT                (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_8_RECR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_8_RECR_SHIFT)) & XRDC_DERR_W3_8_RECR_MASK)
/*! @} */

/*! @name DERR_W0_9 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_9_EADDR_MASK                (0xFFFFFFFFU)
#define XRDC_DERR_W0_9_EADDR_SHIFT               (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_9_EADDR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_9_EADDR_SHIFT)) & XRDC_DERR_W0_9_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_9 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_9_EDID_MASK                 (0xFU)
#define XRDC_DERR_W1_9_EDID_SHIFT                (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_9_EDID(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_9_EDID_SHIFT)) & XRDC_DERR_W1_9_EDID_MASK)

#define XRDC_DERR_W1_9_EATR_MASK                 (0x700U)
#define XRDC_DERR_W1_9_EATR_SHIFT                (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_9_EATR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_9_EATR_SHIFT)) & XRDC_DERR_W1_9_EATR_MASK)

#define XRDC_DERR_W1_9_ERW_MASK                  (0x800U)
#define XRDC_DERR_W1_9_ERW_SHIFT                 (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_9_ERW(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_9_ERW_SHIFT)) & XRDC_DERR_W1_9_ERW_MASK)

#define XRDC_DERR_W1_9_EPORT_MASK                (0x7000000U)
#define XRDC_DERR_W1_9_EPORT_SHIFT               (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_9_EPORT(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_9_EPORT_SHIFT)) & XRDC_DERR_W1_9_EPORT_MASK)

#define XRDC_DERR_W1_9_EST_MASK                  (0xC0000000U)
#define XRDC_DERR_W1_9_EST_SHIFT                 (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_9_EST(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_9_EST_SHIFT)) & XRDC_DERR_W1_9_EST_MASK)
/*! @} */

/*! @name DERR_W3_9 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_9_RECR_MASK                 (0xC0000000U)
#define XRDC_DERR_W3_9_RECR_SHIFT                (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_9_RECR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_9_RECR_SHIFT)) & XRDC_DERR_W3_9_RECR_MASK)
/*! @} */

/*! @name DERR_W0_10 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_10_EADDR_MASK               (0xFFFFFFFFU)
#define XRDC_DERR_W0_10_EADDR_SHIFT              (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_10_EADDR(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_10_EADDR_SHIFT)) & XRDC_DERR_W0_10_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_10 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_10_EDID_MASK                (0xFU)
#define XRDC_DERR_W1_10_EDID_SHIFT               (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_10_EDID(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_10_EDID_SHIFT)) & XRDC_DERR_W1_10_EDID_MASK)

#define XRDC_DERR_W1_10_EATR_MASK                (0x700U)
#define XRDC_DERR_W1_10_EATR_SHIFT               (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_10_EATR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_10_EATR_SHIFT)) & XRDC_DERR_W1_10_EATR_MASK)

#define XRDC_DERR_W1_10_ERW_MASK                 (0x800U)
#define XRDC_DERR_W1_10_ERW_SHIFT                (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_10_ERW(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_10_ERW_SHIFT)) & XRDC_DERR_W1_10_ERW_MASK)

#define XRDC_DERR_W1_10_EPORT_MASK               (0x7000000U)
#define XRDC_DERR_W1_10_EPORT_SHIFT              (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_10_EPORT(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_10_EPORT_SHIFT)) & XRDC_DERR_W1_10_EPORT_MASK)

#define XRDC_DERR_W1_10_EST_MASK                 (0xC0000000U)
#define XRDC_DERR_W1_10_EST_SHIFT                (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_10_EST(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_10_EST_SHIFT)) & XRDC_DERR_W1_10_EST_MASK)
/*! @} */

/*! @name DERR_W3_10 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_10_RECR_MASK                (0xC0000000U)
#define XRDC_DERR_W3_10_RECR_SHIFT               (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_10_RECR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_10_RECR_SHIFT)) & XRDC_DERR_W3_10_RECR_MASK)
/*! @} */

/*! @name DERR_W0_11 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_11_EADDR_MASK               (0xFFFFFFFFU)
#define XRDC_DERR_W0_11_EADDR_SHIFT              (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_11_EADDR(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_11_EADDR_SHIFT)) & XRDC_DERR_W0_11_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_11 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_11_EDID_MASK                (0xFU)
#define XRDC_DERR_W1_11_EDID_SHIFT               (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_11_EDID(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_11_EDID_SHIFT)) & XRDC_DERR_W1_11_EDID_MASK)

#define XRDC_DERR_W1_11_EATR_MASK                (0x700U)
#define XRDC_DERR_W1_11_EATR_SHIFT               (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_11_EATR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_11_EATR_SHIFT)) & XRDC_DERR_W1_11_EATR_MASK)

#define XRDC_DERR_W1_11_ERW_MASK                 (0x800U)
#define XRDC_DERR_W1_11_ERW_SHIFT                (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_11_ERW(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_11_ERW_SHIFT)) & XRDC_DERR_W1_11_ERW_MASK)

#define XRDC_DERR_W1_11_EPORT_MASK               (0x7000000U)
#define XRDC_DERR_W1_11_EPORT_SHIFT              (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_11_EPORT(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_11_EPORT_SHIFT)) & XRDC_DERR_W1_11_EPORT_MASK)

#define XRDC_DERR_W1_11_EST_MASK                 (0xC0000000U)
#define XRDC_DERR_W1_11_EST_SHIFT                (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_11_EST(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_11_EST_SHIFT)) & XRDC_DERR_W1_11_EST_MASK)
/*! @} */

/*! @name DERR_W3_11 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_11_RECR_MASK                (0xC0000000U)
#define XRDC_DERR_W3_11_RECR_SHIFT               (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_11_RECR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_11_RECR_SHIFT)) & XRDC_DERR_W3_11_RECR_MASK)
/*! @} */

/*! @name DERR_W0_12 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_12_EADDR_MASK               (0xFFFFFFFFU)
#define XRDC_DERR_W0_12_EADDR_SHIFT              (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_12_EADDR(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_12_EADDR_SHIFT)) & XRDC_DERR_W0_12_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_12 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_12_EDID_MASK                (0xFU)
#define XRDC_DERR_W1_12_EDID_SHIFT               (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_12_EDID(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_12_EDID_SHIFT)) & XRDC_DERR_W1_12_EDID_MASK)

#define XRDC_DERR_W1_12_EATR_MASK                (0x700U)
#define XRDC_DERR_W1_12_EATR_SHIFT               (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_12_EATR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_12_EATR_SHIFT)) & XRDC_DERR_W1_12_EATR_MASK)

#define XRDC_DERR_W1_12_ERW_MASK                 (0x800U)
#define XRDC_DERR_W1_12_ERW_SHIFT                (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_12_ERW(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_12_ERW_SHIFT)) & XRDC_DERR_W1_12_ERW_MASK)

#define XRDC_DERR_W1_12_EPORT_MASK               (0x7000000U)
#define XRDC_DERR_W1_12_EPORT_SHIFT              (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_12_EPORT(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_12_EPORT_SHIFT)) & XRDC_DERR_W1_12_EPORT_MASK)

#define XRDC_DERR_W1_12_EST_MASK                 (0xC0000000U)
#define XRDC_DERR_W1_12_EST_SHIFT                (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_12_EST(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_12_EST_SHIFT)) & XRDC_DERR_W1_12_EST_MASK)
/*! @} */

/*! @name DERR_W3_12 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_12_RECR_MASK                (0xC0000000U)
#define XRDC_DERR_W3_12_RECR_SHIFT               (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_12_RECR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_12_RECR_SHIFT)) & XRDC_DERR_W3_12_RECR_MASK)
/*! @} */

/*! @name DERR_W0_16 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_16_EADDR_MASK               (0xFFFFFFFFU)
#define XRDC_DERR_W0_16_EADDR_SHIFT              (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_16_EADDR(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_16_EADDR_SHIFT)) & XRDC_DERR_W0_16_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_16 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_16_EDID_MASK                (0xFU)
#define XRDC_DERR_W1_16_EDID_SHIFT               (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_16_EDID(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_16_EDID_SHIFT)) & XRDC_DERR_W1_16_EDID_MASK)

#define XRDC_DERR_W1_16_EATR_MASK                (0x700U)
#define XRDC_DERR_W1_16_EATR_SHIFT               (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_16_EATR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_16_EATR_SHIFT)) & XRDC_DERR_W1_16_EATR_MASK)

#define XRDC_DERR_W1_16_ERW_MASK                 (0x800U)
#define XRDC_DERR_W1_16_ERW_SHIFT                (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_16_ERW(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_16_ERW_SHIFT)) & XRDC_DERR_W1_16_ERW_MASK)

#define XRDC_DERR_W1_16_EPORT_MASK               (0x7000000U)
#define XRDC_DERR_W1_16_EPORT_SHIFT              (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_16_EPORT(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_16_EPORT_SHIFT)) & XRDC_DERR_W1_16_EPORT_MASK)

#define XRDC_DERR_W1_16_EST_MASK                 (0xC0000000U)
#define XRDC_DERR_W1_16_EST_SHIFT                (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_16_EST(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_16_EST_SHIFT)) & XRDC_DERR_W1_16_EST_MASK)
/*! @} */

/*! @name DERR_W3_16 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_16_RECR_MASK                (0xC0000000U)
#define XRDC_DERR_W3_16_RECR_SHIFT               (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_16_RECR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_16_RECR_SHIFT)) & XRDC_DERR_W3_16_RECR_MASK)
/*! @} */

/*! @name DERR_W0_17 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_17_EADDR_MASK               (0xFFFFFFFFU)
#define XRDC_DERR_W0_17_EADDR_SHIFT              (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_17_EADDR(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_17_EADDR_SHIFT)) & XRDC_DERR_W0_17_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_17 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_17_EDID_MASK                (0xFU)
#define XRDC_DERR_W1_17_EDID_SHIFT               (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_17_EDID(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_17_EDID_SHIFT)) & XRDC_DERR_W1_17_EDID_MASK)

#define XRDC_DERR_W1_17_EATR_MASK                (0x700U)
#define XRDC_DERR_W1_17_EATR_SHIFT               (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_17_EATR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_17_EATR_SHIFT)) & XRDC_DERR_W1_17_EATR_MASK)

#define XRDC_DERR_W1_17_ERW_MASK                 (0x800U)
#define XRDC_DERR_W1_17_ERW_SHIFT                (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_17_ERW(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_17_ERW_SHIFT)) & XRDC_DERR_W1_17_ERW_MASK)

#define XRDC_DERR_W1_17_EPORT_MASK               (0x7000000U)
#define XRDC_DERR_W1_17_EPORT_SHIFT              (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_17_EPORT(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_17_EPORT_SHIFT)) & XRDC_DERR_W1_17_EPORT_MASK)

#define XRDC_DERR_W1_17_EST_MASK                 (0xC0000000U)
#define XRDC_DERR_W1_17_EST_SHIFT                (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_17_EST(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_17_EST_SHIFT)) & XRDC_DERR_W1_17_EST_MASK)
/*! @} */

/*! @name DERR_W3_17 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_17_RECR_MASK                (0xC0000000U)
#define XRDC_DERR_W3_17_RECR_SHIFT               (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_17_RECR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_17_RECR_SHIFT)) & XRDC_DERR_W3_17_RECR_MASK)
/*! @} */

/*! @name DERR_W0_18 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_18_EADDR_MASK               (0xFFFFFFFFU)
#define XRDC_DERR_W0_18_EADDR_SHIFT              (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_18_EADDR(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_18_EADDR_SHIFT)) & XRDC_DERR_W0_18_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_18 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_18_EDID_MASK                (0xFU)
#define XRDC_DERR_W1_18_EDID_SHIFT               (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_18_EDID(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_18_EDID_SHIFT)) & XRDC_DERR_W1_18_EDID_MASK)

#define XRDC_DERR_W1_18_EATR_MASK                (0x700U)
#define XRDC_DERR_W1_18_EATR_SHIFT               (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_18_EATR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_18_EATR_SHIFT)) & XRDC_DERR_W1_18_EATR_MASK)

#define XRDC_DERR_W1_18_ERW_MASK                 (0x800U)
#define XRDC_DERR_W1_18_ERW_SHIFT                (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_18_ERW(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_18_ERW_SHIFT)) & XRDC_DERR_W1_18_ERW_MASK)

#define XRDC_DERR_W1_18_EPORT_MASK               (0x7000000U)
#define XRDC_DERR_W1_18_EPORT_SHIFT              (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_18_EPORT(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_18_EPORT_SHIFT)) & XRDC_DERR_W1_18_EPORT_MASK)

#define XRDC_DERR_W1_18_EST_MASK                 (0xC0000000U)
#define XRDC_DERR_W1_18_EST_SHIFT                (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_18_EST(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_18_EST_SHIFT)) & XRDC_DERR_W1_18_EST_MASK)
/*! @} */

/*! @name DERR_W3_18 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_18_RECR_MASK                (0xC0000000U)
#define XRDC_DERR_W3_18_RECR_SHIFT               (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_18_RECR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_18_RECR_SHIFT)) & XRDC_DERR_W3_18_RECR_MASK)
/*! @} */

/*! @name DERR_W0_20 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_20_EADDR_MASK               (0xFFFFFFFFU)
#define XRDC_DERR_W0_20_EADDR_SHIFT              (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_20_EADDR(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_20_EADDR_SHIFT)) & XRDC_DERR_W0_20_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_20 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_20_EDID_MASK                (0xFU)
#define XRDC_DERR_W1_20_EDID_SHIFT               (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_20_EDID(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_20_EDID_SHIFT)) & XRDC_DERR_W1_20_EDID_MASK)

#define XRDC_DERR_W1_20_EATR_MASK                (0x700U)
#define XRDC_DERR_W1_20_EATR_SHIFT               (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_20_EATR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_20_EATR_SHIFT)) & XRDC_DERR_W1_20_EATR_MASK)

#define XRDC_DERR_W1_20_ERW_MASK                 (0x800U)
#define XRDC_DERR_W1_20_ERW_SHIFT                (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_20_ERW(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_20_ERW_SHIFT)) & XRDC_DERR_W1_20_ERW_MASK)

#define XRDC_DERR_W1_20_EPORT_MASK               (0x7000000U)
#define XRDC_DERR_W1_20_EPORT_SHIFT              (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_20_EPORT(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_20_EPORT_SHIFT)) & XRDC_DERR_W1_20_EPORT_MASK)

#define XRDC_DERR_W1_20_EST_MASK                 (0xC0000000U)
#define XRDC_DERR_W1_20_EST_SHIFT                (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_20_EST(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_20_EST_SHIFT)) & XRDC_DERR_W1_20_EST_MASK)
/*! @} */

/*! @name DERR_W3_20 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_20_RECR_MASK                (0xC0000000U)
#define XRDC_DERR_W3_20_RECR_SHIFT               (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_20_RECR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_20_RECR_SHIFT)) & XRDC_DERR_W3_20_RECR_MASK)
/*! @} */

/*! @name DERR_W0_21 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_21_EADDR_MASK               (0xFFFFFFFFU)
#define XRDC_DERR_W0_21_EADDR_SHIFT              (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_21_EADDR(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_21_EADDR_SHIFT)) & XRDC_DERR_W0_21_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_21 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_21_EDID_MASK                (0xFU)
#define XRDC_DERR_W1_21_EDID_SHIFT               (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_21_EDID(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_21_EDID_SHIFT)) & XRDC_DERR_W1_21_EDID_MASK)

#define XRDC_DERR_W1_21_EATR_MASK                (0x700U)
#define XRDC_DERR_W1_21_EATR_SHIFT               (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_21_EATR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_21_EATR_SHIFT)) & XRDC_DERR_W1_21_EATR_MASK)

#define XRDC_DERR_W1_21_ERW_MASK                 (0x800U)
#define XRDC_DERR_W1_21_ERW_SHIFT                (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_21_ERW(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_21_ERW_SHIFT)) & XRDC_DERR_W1_21_ERW_MASK)

#define XRDC_DERR_W1_21_EPORT_MASK               (0x7000000U)
#define XRDC_DERR_W1_21_EPORT_SHIFT              (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_21_EPORT(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_21_EPORT_SHIFT)) & XRDC_DERR_W1_21_EPORT_MASK)

#define XRDC_DERR_W1_21_EST_MASK                 (0xC0000000U)
#define XRDC_DERR_W1_21_EST_SHIFT                (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_21_EST(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_21_EST_SHIFT)) & XRDC_DERR_W1_21_EST_MASK)
/*! @} */

/*! @name DERR_W3_21 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_21_RECR_MASK                (0xC0000000U)
#define XRDC_DERR_W3_21_RECR_SHIFT               (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_21_RECR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_21_RECR_SHIFT)) & XRDC_DERR_W3_21_RECR_MASK)
/*! @} */

/*! @name DERR_W0_22 - Domain Error Word0 Register */
/*! @{ */

#define XRDC_DERR_W0_22_EADDR_MASK               (0xFFFFFFFFU)
#define XRDC_DERR_W0_22_EADDR_SHIFT              (0U)
/*! EADDR - Error address */
#define XRDC_DERR_W0_22_EADDR(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_22_EADDR_SHIFT)) & XRDC_DERR_W0_22_EADDR_MASK)
/*! @} */

/*! @name DERR_W1_22 - Domain Error Word1 Register */
/*! @{ */

#define XRDC_DERR_W1_22_EDID_MASK                (0xFU)
#define XRDC_DERR_W1_22_EDID_SHIFT               (0U)
/*! EDID - Error domain identifier */
#define XRDC_DERR_W1_22_EDID(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_22_EDID_SHIFT)) & XRDC_DERR_W1_22_EDID_MASK)

#define XRDC_DERR_W1_22_EATR_MASK                (0x700U)
#define XRDC_DERR_W1_22_EATR_SHIFT               (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define XRDC_DERR_W1_22_EATR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_22_EATR_SHIFT)) & XRDC_DERR_W1_22_EATR_MASK)

#define XRDC_DERR_W1_22_ERW_MASK                 (0x800U)
#define XRDC_DERR_W1_22_ERW_SHIFT                (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define XRDC_DERR_W1_22_ERW(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_22_ERW_SHIFT)) & XRDC_DERR_W1_22_ERW_MASK)

#define XRDC_DERR_W1_22_EPORT_MASK               (0x7000000U)
#define XRDC_DERR_W1_22_EPORT_SHIFT              (24U)
/*! EPORT - Error port */
#define XRDC_DERR_W1_22_EPORT(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_22_EPORT_SHIFT)) & XRDC_DERR_W1_22_EPORT_MASK)

#define XRDC_DERR_W1_22_EST_MASK                 (0xC0000000U)
#define XRDC_DERR_W1_22_EST_SHIFT                (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define XRDC_DERR_W1_22_EST(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_22_EST_SHIFT)) & XRDC_DERR_W1_22_EST_MASK)
/*! @} */

/*! @name DERR_W3_22 - Domain Error Word3 Register */
/*! @{ */

#define XRDC_DERR_W3_22_RECR_MASK                (0xC0000000U)
#define XRDC_DERR_W3_22_RECR_SHIFT               (30U)
/*! RECR - Rearm Error Capture Registers */
#define XRDC_DERR_W3_22_RECR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_22_RECR_SHIFT)) & XRDC_DERR_W3_22_RECR_MASK)
/*! @} */

/*! @name PID0 - Process Identifier */
/*! @{ */

#define XRDC_PID0_PID_MASK                       (0x3FU)
#define XRDC_PID0_PID_SHIFT                      (0U)
/*! PID - Process identifier */
#define XRDC_PID0_PID(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_PID0_PID_SHIFT)) & XRDC_PID0_PID_MASK)

#define XRDC_PID0_SP4SM_MASK                     (0x8000000U)
#define XRDC_PID0_SP4SM_SHIFT                    (27U)
/*! SP4SM - Special 4-state model */
#define XRDC_PID0_SP4SM(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_PID0_SP4SM_SHIFT)) & XRDC_PID0_SP4SM_MASK)

#define XRDC_PID0_TSM_MASK                       (0x10000000U)
#define XRDC_PID0_TSM_SHIFT                      (28U)
/*! TSM - Three-state model */
#define XRDC_PID0_TSM(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_PID0_TSM_SHIFT)) & XRDC_PID0_TSM_MASK)

#define XRDC_PID0_LK2_MASK                       (0x60000000U)
#define XRDC_PID0_LK2_SHIFT                      (29U)
/*! LK2 - Lock
 *  0b00..Register can be written by any secure privileged write.
 *  0b01..Register can be written by any secure privileged write.
 *  0b10..Register can only be written by a secure privileged write from bus master m.
 *  0b11..Register is locked (read-only) until the next reset.
 */
#define XRDC_PID0_LK2(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_PID0_LK2_SHIFT)) & XRDC_PID0_LK2_MASK)
/*! @} */

/*! @name MDA_W0_0_DFMT0 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_0_DFMT0_DID_MASK             (0xFU)
#define XRDC_MDA_W0_0_DFMT0_DID_SHIFT            (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_0_DFMT0_DID(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_DID_SHIFT)) & XRDC_MDA_W0_0_DFMT0_DID_MASK)

#define XRDC_MDA_W0_0_DFMT0_DIDS_MASK            (0x30U)
#define XRDC_MDA_W0_0_DFMT0_DIDS_SHIFT           (4U)
/*! DIDS - DID Select
 *  0b00..Use MDAm[3:0] as the domain identifier.
 *  0b01..Use the input DID as the domain identifier.
 *  0b10..Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier.
 *  0b11..Reserved for future use.
 */
#define XRDC_MDA_W0_0_DFMT0_DIDS(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_DIDS_SHIFT)) & XRDC_MDA_W0_0_DFMT0_DIDS_MASK)

#define XRDC_MDA_W0_0_DFMT0_PE_MASK              (0xC0U)
#define XRDC_MDA_W0_0_DFMT0_PE_SHIFT             (6U)
/*! PE - Process identifier enable
 *  0b00..No process identifier is included in the domain hit evaluation.
 *  0b01..No process identifier is included in the domain hit evaluation.
 *  0b10..The process identifier is included in the domain hit evaluation as defined by the expression:
 *        partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
 *  0b11..The process identifier is included in the domain hit evaluation as defined by the expression:
 *        partial_domain_hit = (PE == 3) && ~((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
 */
#define XRDC_MDA_W0_0_DFMT0_PE(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_PE_SHIFT)) & XRDC_MDA_W0_0_DFMT0_PE_MASK)

#define XRDC_MDA_W0_0_DFMT0_PIDM_MASK            (0x3F00U)
#define XRDC_MDA_W0_0_DFMT0_PIDM_SHIFT           (8U)
/*! PIDM - Process Identifier Mask */
#define XRDC_MDA_W0_0_DFMT0_PIDM(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_PIDM_SHIFT)) & XRDC_MDA_W0_0_DFMT0_PIDM_MASK)

#define XRDC_MDA_W0_0_DFMT0_PID_MASK             (0x3F0000U)
#define XRDC_MDA_W0_0_DFMT0_PID_SHIFT            (16U)
/*! PID - Process Identifier */
#define XRDC_MDA_W0_0_DFMT0_PID(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_PID_SHIFT)) & XRDC_MDA_W0_0_DFMT0_PID_MASK)

#define XRDC_MDA_W0_0_DFMT0_DFMT_MASK            (0x20000000U)
#define XRDC_MDA_W0_0_DFMT0_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_0_DFMT0_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_DFMT_SHIFT)) & XRDC_MDA_W0_0_DFMT0_DFMT_MASK)

#define XRDC_MDA_W0_0_DFMT0_LK1_MASK             (0x40000000U)
#define XRDC_MDA_W0_0_DFMT0_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_0_DFMT0_LK1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_LK1_SHIFT)) & XRDC_MDA_W0_0_DFMT0_LK1_MASK)

#define XRDC_MDA_W0_0_DFMT0_VLD_MASK             (0x80000000U)
#define XRDC_MDA_W0_0_DFMT0_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_0_DFMT0_VLD(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_VLD_SHIFT)) & XRDC_MDA_W0_0_DFMT0_VLD_MASK)
/*! @} */

/*! @name MDA_W1_0_DFMT0 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W1_0_DFMT0_DID_MASK             (0xFU)
#define XRDC_MDA_W1_0_DFMT0_DID_SHIFT            (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W1_0_DFMT0_DID(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT0_DID_SHIFT)) & XRDC_MDA_W1_0_DFMT0_DID_MASK)

#define XRDC_MDA_W1_0_DFMT0_DIDS_MASK            (0x30U)
#define XRDC_MDA_W1_0_DFMT0_DIDS_SHIFT           (4U)
/*! DIDS - DID Select
 *  0b00..Use MDAm[3:0] as the domain identifier.
 *  0b01..Use the input DID as the domain identifier.
 *  0b10..Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier.
 *  0b11..Reserved for future use.
 */
#define XRDC_MDA_W1_0_DFMT0_DIDS(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT0_DIDS_SHIFT)) & XRDC_MDA_W1_0_DFMT0_DIDS_MASK)

#define XRDC_MDA_W1_0_DFMT0_PE_MASK              (0xC0U)
#define XRDC_MDA_W1_0_DFMT0_PE_SHIFT             (6U)
/*! PE - Process identifier enable
 *  0b00..No process identifier is included in the domain hit evaluation.
 *  0b01..No process identifier is included in the domain hit evaluation.
 *  0b10..The process identifier is included in the domain hit evaluation as defined by the expression:
 *        partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
 *  0b11..The process identifier is included in the domain hit evaluation as defined by the expression:
 *        partial_domain_hit = (PE == 3) && ~((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
 */
#define XRDC_MDA_W1_0_DFMT0_PE(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT0_PE_SHIFT)) & XRDC_MDA_W1_0_DFMT0_PE_MASK)

#define XRDC_MDA_W1_0_DFMT0_PIDM_MASK            (0x3F00U)
#define XRDC_MDA_W1_0_DFMT0_PIDM_SHIFT           (8U)
/*! PIDM - Process Identifier Mask */
#define XRDC_MDA_W1_0_DFMT0_PIDM(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT0_PIDM_SHIFT)) & XRDC_MDA_W1_0_DFMT0_PIDM_MASK)

#define XRDC_MDA_W1_0_DFMT0_PID_MASK             (0x3F0000U)
#define XRDC_MDA_W1_0_DFMT0_PID_SHIFT            (16U)
/*! PID - Process Identifier */
#define XRDC_MDA_W1_0_DFMT0_PID(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT0_PID_SHIFT)) & XRDC_MDA_W1_0_DFMT0_PID_MASK)

#define XRDC_MDA_W1_0_DFMT0_DFMT_MASK            (0x20000000U)
#define XRDC_MDA_W1_0_DFMT0_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W1_0_DFMT0_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT0_DFMT_SHIFT)) & XRDC_MDA_W1_0_DFMT0_DFMT_MASK)

#define XRDC_MDA_W1_0_DFMT0_LK1_MASK             (0x40000000U)
#define XRDC_MDA_W1_0_DFMT0_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W1_0_DFMT0_LK1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT0_LK1_SHIFT)) & XRDC_MDA_W1_0_DFMT0_LK1_MASK)

#define XRDC_MDA_W1_0_DFMT0_VLD_MASK             (0x80000000U)
#define XRDC_MDA_W1_0_DFMT0_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W1_0_DFMT0_VLD(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT0_VLD_SHIFT)) & XRDC_MDA_W1_0_DFMT0_VLD_MASK)
/*! @} */

/*! @name MDA_W0_1_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_1_DFMT1_DID_MASK             (0xFU)
#define XRDC_MDA_W0_1_DFMT1_DID_SHIFT            (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_1_DFMT1_DID(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_1_DFMT1_DID_MASK)

#define XRDC_MDA_W0_1_DFMT1_PA_MASK              (0x30U)
#define XRDC_MDA_W0_1_DFMT1_PA_SHIFT             (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_1_DFMT1_PA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_1_DFMT1_PA_MASK)

#define XRDC_MDA_W0_1_DFMT1_SA_MASK              (0xC0U)
#define XRDC_MDA_W0_1_DFMT1_SA_SHIFT             (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_1_DFMT1_SA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_1_DFMT1_SA_MASK)

#define XRDC_MDA_W0_1_DFMT1_DIDB_MASK            (0x100U)
#define XRDC_MDA_W0_1_DFMT1_DIDB_SHIFT           (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_1_DFMT1_DIDB(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_1_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_1_DFMT1_DFMT_MASK            (0x20000000U)
#define XRDC_MDA_W0_1_DFMT1_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_1_DFMT1_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_1_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_1_DFMT1_LK1_MASK             (0x40000000U)
#define XRDC_MDA_W0_1_DFMT1_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_1_DFMT1_LK1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_1_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_1_DFMT1_VLD_MASK             (0x80000000U)
#define XRDC_MDA_W0_1_DFMT1_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_1_DFMT1_VLD(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_1_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_2_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_2_DFMT1_DID_MASK             (0xFU)
#define XRDC_MDA_W0_2_DFMT1_DID_SHIFT            (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_2_DFMT1_DID(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_2_DFMT1_DID_MASK)

#define XRDC_MDA_W0_2_DFMT1_PA_MASK              (0x30U)
#define XRDC_MDA_W0_2_DFMT1_PA_SHIFT             (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_2_DFMT1_PA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_2_DFMT1_PA_MASK)

#define XRDC_MDA_W0_2_DFMT1_SA_MASK              (0xC0U)
#define XRDC_MDA_W0_2_DFMT1_SA_SHIFT             (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_2_DFMT1_SA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_2_DFMT1_SA_MASK)

#define XRDC_MDA_W0_2_DFMT1_DIDB_MASK            (0x100U)
#define XRDC_MDA_W0_2_DFMT1_DIDB_SHIFT           (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_2_DFMT1_DIDB(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_2_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_2_DFMT1_DFMT_MASK            (0x20000000U)
#define XRDC_MDA_W0_2_DFMT1_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_2_DFMT1_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_2_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_2_DFMT1_LK1_MASK             (0x40000000U)
#define XRDC_MDA_W0_2_DFMT1_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_2_DFMT1_LK1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_2_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_2_DFMT1_VLD_MASK             (0x80000000U)
#define XRDC_MDA_W0_2_DFMT1_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_2_DFMT1_VLD(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_2_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_3_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_3_DFMT1_DID_MASK             (0xFU)
#define XRDC_MDA_W0_3_DFMT1_DID_SHIFT            (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_3_DFMT1_DID(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_3_DFMT1_DID_MASK)

#define XRDC_MDA_W0_3_DFMT1_PA_MASK              (0x30U)
#define XRDC_MDA_W0_3_DFMT1_PA_SHIFT             (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_3_DFMT1_PA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_3_DFMT1_PA_MASK)

#define XRDC_MDA_W0_3_DFMT1_SA_MASK              (0xC0U)
#define XRDC_MDA_W0_3_DFMT1_SA_SHIFT             (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_3_DFMT1_SA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_3_DFMT1_SA_MASK)

#define XRDC_MDA_W0_3_DFMT1_DIDB_MASK            (0x100U)
#define XRDC_MDA_W0_3_DFMT1_DIDB_SHIFT           (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_3_DFMT1_DIDB(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_3_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_3_DFMT1_DFMT_MASK            (0x20000000U)
#define XRDC_MDA_W0_3_DFMT1_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_3_DFMT1_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_3_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_3_DFMT1_LK1_MASK             (0x40000000U)
#define XRDC_MDA_W0_3_DFMT1_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_3_DFMT1_LK1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_3_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_3_DFMT1_VLD_MASK             (0x80000000U)
#define XRDC_MDA_W0_3_DFMT1_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_3_DFMT1_VLD(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_3_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_4_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_4_DFMT1_DID_MASK             (0xFU)
#define XRDC_MDA_W0_4_DFMT1_DID_SHIFT            (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_4_DFMT1_DID(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_4_DFMT1_DID_MASK)

#define XRDC_MDA_W0_4_DFMT1_PA_MASK              (0x30U)
#define XRDC_MDA_W0_4_DFMT1_PA_SHIFT             (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_4_DFMT1_PA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_4_DFMT1_PA_MASK)

#define XRDC_MDA_W0_4_DFMT1_SA_MASK              (0xC0U)
#define XRDC_MDA_W0_4_DFMT1_SA_SHIFT             (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_4_DFMT1_SA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_4_DFMT1_SA_MASK)

#define XRDC_MDA_W0_4_DFMT1_DIDB_MASK            (0x100U)
#define XRDC_MDA_W0_4_DFMT1_DIDB_SHIFT           (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_4_DFMT1_DIDB(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_4_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_4_DFMT1_DFMT_MASK            (0x20000000U)
#define XRDC_MDA_W0_4_DFMT1_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_4_DFMT1_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_4_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_4_DFMT1_LK1_MASK             (0x40000000U)
#define XRDC_MDA_W0_4_DFMT1_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_4_DFMT1_LK1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_4_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_4_DFMT1_VLD_MASK             (0x80000000U)
#define XRDC_MDA_W0_4_DFMT1_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_4_DFMT1_VLD(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_4_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_5_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_5_DFMT1_DID_MASK             (0xFU)
#define XRDC_MDA_W0_5_DFMT1_DID_SHIFT            (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_5_DFMT1_DID(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_5_DFMT1_DID_MASK)

#define XRDC_MDA_W0_5_DFMT1_PA_MASK              (0x30U)
#define XRDC_MDA_W0_5_DFMT1_PA_SHIFT             (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_5_DFMT1_PA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_5_DFMT1_PA_MASK)

#define XRDC_MDA_W0_5_DFMT1_SA_MASK              (0xC0U)
#define XRDC_MDA_W0_5_DFMT1_SA_SHIFT             (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_5_DFMT1_SA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_5_DFMT1_SA_MASK)

#define XRDC_MDA_W0_5_DFMT1_DIDB_MASK            (0x100U)
#define XRDC_MDA_W0_5_DFMT1_DIDB_SHIFT           (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_5_DFMT1_DIDB(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_5_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_5_DFMT1_DFMT_MASK            (0x20000000U)
#define XRDC_MDA_W0_5_DFMT1_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_5_DFMT1_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_5_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_5_DFMT1_LK1_MASK             (0x40000000U)
#define XRDC_MDA_W0_5_DFMT1_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_5_DFMT1_LK1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_5_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_5_DFMT1_VLD_MASK             (0x80000000U)
#define XRDC_MDA_W0_5_DFMT1_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_5_DFMT1_VLD(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_5_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_6_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_6_DFMT1_DID_MASK             (0xFU)
#define XRDC_MDA_W0_6_DFMT1_DID_SHIFT            (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_6_DFMT1_DID(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_6_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_6_DFMT1_DID_MASK)

#define XRDC_MDA_W0_6_DFMT1_PA_MASK              (0x30U)
#define XRDC_MDA_W0_6_DFMT1_PA_SHIFT             (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_6_DFMT1_PA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_6_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_6_DFMT1_PA_MASK)

#define XRDC_MDA_W0_6_DFMT1_SA_MASK              (0xC0U)
#define XRDC_MDA_W0_6_DFMT1_SA_SHIFT             (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_6_DFMT1_SA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_6_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_6_DFMT1_SA_MASK)

#define XRDC_MDA_W0_6_DFMT1_DIDB_MASK            (0x100U)
#define XRDC_MDA_W0_6_DFMT1_DIDB_SHIFT           (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_6_DFMT1_DIDB(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_6_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_6_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_6_DFMT1_DFMT_MASK            (0x20000000U)
#define XRDC_MDA_W0_6_DFMT1_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_6_DFMT1_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_6_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_6_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_6_DFMT1_LK1_MASK             (0x40000000U)
#define XRDC_MDA_W0_6_DFMT1_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_6_DFMT1_LK1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_6_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_6_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_6_DFMT1_VLD_MASK             (0x80000000U)
#define XRDC_MDA_W0_6_DFMT1_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_6_DFMT1_VLD(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_6_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_6_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_7_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_7_DFMT1_DID_MASK             (0xFU)
#define XRDC_MDA_W0_7_DFMT1_DID_SHIFT            (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_7_DFMT1_DID(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_7_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_7_DFMT1_DID_MASK)

#define XRDC_MDA_W0_7_DFMT1_PA_MASK              (0x30U)
#define XRDC_MDA_W0_7_DFMT1_PA_SHIFT             (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_7_DFMT1_PA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_7_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_7_DFMT1_PA_MASK)

#define XRDC_MDA_W0_7_DFMT1_SA_MASK              (0xC0U)
#define XRDC_MDA_W0_7_DFMT1_SA_SHIFT             (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_7_DFMT1_SA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_7_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_7_DFMT1_SA_MASK)

#define XRDC_MDA_W0_7_DFMT1_DIDB_MASK            (0x100U)
#define XRDC_MDA_W0_7_DFMT1_DIDB_SHIFT           (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_7_DFMT1_DIDB(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_7_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_7_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_7_DFMT1_DFMT_MASK            (0x20000000U)
#define XRDC_MDA_W0_7_DFMT1_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_7_DFMT1_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_7_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_7_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_7_DFMT1_LK1_MASK             (0x40000000U)
#define XRDC_MDA_W0_7_DFMT1_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_7_DFMT1_LK1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_7_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_7_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_7_DFMT1_VLD_MASK             (0x80000000U)
#define XRDC_MDA_W0_7_DFMT1_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_7_DFMT1_VLD(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_7_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_7_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_8_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_8_DFMT1_DID_MASK             (0xFU)
#define XRDC_MDA_W0_8_DFMT1_DID_SHIFT            (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_8_DFMT1_DID(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_8_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_8_DFMT1_DID_MASK)

#define XRDC_MDA_W0_8_DFMT1_PA_MASK              (0x30U)
#define XRDC_MDA_W0_8_DFMT1_PA_SHIFT             (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_8_DFMT1_PA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_8_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_8_DFMT1_PA_MASK)

#define XRDC_MDA_W0_8_DFMT1_SA_MASK              (0xC0U)
#define XRDC_MDA_W0_8_DFMT1_SA_SHIFT             (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_8_DFMT1_SA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_8_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_8_DFMT1_SA_MASK)

#define XRDC_MDA_W0_8_DFMT1_DIDB_MASK            (0x100U)
#define XRDC_MDA_W0_8_DFMT1_DIDB_SHIFT           (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_8_DFMT1_DIDB(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_8_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_8_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_8_DFMT1_DFMT_MASK            (0x20000000U)
#define XRDC_MDA_W0_8_DFMT1_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_8_DFMT1_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_8_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_8_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_8_DFMT1_LK1_MASK             (0x40000000U)
#define XRDC_MDA_W0_8_DFMT1_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_8_DFMT1_LK1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_8_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_8_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_8_DFMT1_VLD_MASK             (0x80000000U)
#define XRDC_MDA_W0_8_DFMT1_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_8_DFMT1_VLD(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_8_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_8_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_9_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_9_DFMT1_DID_MASK             (0xFU)
#define XRDC_MDA_W0_9_DFMT1_DID_SHIFT            (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_9_DFMT1_DID(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_9_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_9_DFMT1_DID_MASK)

#define XRDC_MDA_W0_9_DFMT1_PA_MASK              (0x30U)
#define XRDC_MDA_W0_9_DFMT1_PA_SHIFT             (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_9_DFMT1_PA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_9_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_9_DFMT1_PA_MASK)

#define XRDC_MDA_W0_9_DFMT1_SA_MASK              (0xC0U)
#define XRDC_MDA_W0_9_DFMT1_SA_SHIFT             (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_9_DFMT1_SA(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_9_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_9_DFMT1_SA_MASK)

#define XRDC_MDA_W0_9_DFMT1_DIDB_MASK            (0x100U)
#define XRDC_MDA_W0_9_DFMT1_DIDB_SHIFT           (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_9_DFMT1_DIDB(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_9_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_9_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_9_DFMT1_DFMT_MASK            (0x20000000U)
#define XRDC_MDA_W0_9_DFMT1_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_9_DFMT1_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_9_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_9_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_9_DFMT1_LK1_MASK             (0x40000000U)
#define XRDC_MDA_W0_9_DFMT1_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_9_DFMT1_LK1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_9_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_9_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_9_DFMT1_VLD_MASK             (0x80000000U)
#define XRDC_MDA_W0_9_DFMT1_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_9_DFMT1_VLD(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_9_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_9_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_10_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_10_DFMT1_DID_MASK            (0xFU)
#define XRDC_MDA_W0_10_DFMT1_DID_SHIFT           (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_10_DFMT1_DID(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_10_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_10_DFMT1_DID_MASK)

#define XRDC_MDA_W0_10_DFMT1_PA_MASK             (0x30U)
#define XRDC_MDA_W0_10_DFMT1_PA_SHIFT            (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_10_DFMT1_PA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_10_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_10_DFMT1_PA_MASK)

#define XRDC_MDA_W0_10_DFMT1_SA_MASK             (0xC0U)
#define XRDC_MDA_W0_10_DFMT1_SA_SHIFT            (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_10_DFMT1_SA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_10_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_10_DFMT1_SA_MASK)

#define XRDC_MDA_W0_10_DFMT1_DIDB_MASK           (0x100U)
#define XRDC_MDA_W0_10_DFMT1_DIDB_SHIFT          (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_10_DFMT1_DIDB(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_10_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_10_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_10_DFMT1_DFMT_MASK           (0x20000000U)
#define XRDC_MDA_W0_10_DFMT1_DFMT_SHIFT          (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_10_DFMT1_DFMT(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_10_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_10_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_10_DFMT1_LK1_MASK            (0x40000000U)
#define XRDC_MDA_W0_10_DFMT1_LK1_SHIFT           (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_10_DFMT1_LK1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_10_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_10_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_10_DFMT1_VLD_MASK            (0x80000000U)
#define XRDC_MDA_W0_10_DFMT1_VLD_SHIFT           (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_10_DFMT1_VLD(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_10_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_10_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_11_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_11_DFMT1_DID_MASK            (0xFU)
#define XRDC_MDA_W0_11_DFMT1_DID_SHIFT           (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_11_DFMT1_DID(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_11_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_11_DFMT1_DID_MASK)

#define XRDC_MDA_W0_11_DFMT1_PA_MASK             (0x30U)
#define XRDC_MDA_W0_11_DFMT1_PA_SHIFT            (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_11_DFMT1_PA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_11_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_11_DFMT1_PA_MASK)

#define XRDC_MDA_W0_11_DFMT1_SA_MASK             (0xC0U)
#define XRDC_MDA_W0_11_DFMT1_SA_SHIFT            (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_11_DFMT1_SA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_11_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_11_DFMT1_SA_MASK)

#define XRDC_MDA_W0_11_DFMT1_DIDB_MASK           (0x100U)
#define XRDC_MDA_W0_11_DFMT1_DIDB_SHIFT          (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_11_DFMT1_DIDB(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_11_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_11_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_11_DFMT1_DFMT_MASK           (0x20000000U)
#define XRDC_MDA_W0_11_DFMT1_DFMT_SHIFT          (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_11_DFMT1_DFMT(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_11_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_11_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_11_DFMT1_LK1_MASK            (0x40000000U)
#define XRDC_MDA_W0_11_DFMT1_LK1_SHIFT           (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_11_DFMT1_LK1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_11_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_11_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_11_DFMT1_VLD_MASK            (0x80000000U)
#define XRDC_MDA_W0_11_DFMT1_VLD_SHIFT           (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_11_DFMT1_VLD(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_11_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_11_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_12_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_12_DFMT1_DID_MASK            (0xFU)
#define XRDC_MDA_W0_12_DFMT1_DID_SHIFT           (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_12_DFMT1_DID(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_12_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_12_DFMT1_DID_MASK)

#define XRDC_MDA_W0_12_DFMT1_PA_MASK             (0x30U)
#define XRDC_MDA_W0_12_DFMT1_PA_SHIFT            (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_12_DFMT1_PA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_12_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_12_DFMT1_PA_MASK)

#define XRDC_MDA_W0_12_DFMT1_SA_MASK             (0xC0U)
#define XRDC_MDA_W0_12_DFMT1_SA_SHIFT            (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_12_DFMT1_SA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_12_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_12_DFMT1_SA_MASK)

#define XRDC_MDA_W0_12_DFMT1_DIDB_MASK           (0x100U)
#define XRDC_MDA_W0_12_DFMT1_DIDB_SHIFT          (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_12_DFMT1_DIDB(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_12_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_12_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_12_DFMT1_DFMT_MASK           (0x20000000U)
#define XRDC_MDA_W0_12_DFMT1_DFMT_SHIFT          (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_12_DFMT1_DFMT(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_12_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_12_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_12_DFMT1_LK1_MASK            (0x40000000U)
#define XRDC_MDA_W0_12_DFMT1_LK1_SHIFT           (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_12_DFMT1_LK1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_12_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_12_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_12_DFMT1_VLD_MASK            (0x80000000U)
#define XRDC_MDA_W0_12_DFMT1_VLD_SHIFT           (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_12_DFMT1_VLD(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_12_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_12_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_13_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_13_DFMT1_DID_MASK            (0xFU)
#define XRDC_MDA_W0_13_DFMT1_DID_SHIFT           (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_13_DFMT1_DID(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_13_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_13_DFMT1_DID_MASK)

#define XRDC_MDA_W0_13_DFMT1_PA_MASK             (0x30U)
#define XRDC_MDA_W0_13_DFMT1_PA_SHIFT            (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_13_DFMT1_PA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_13_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_13_DFMT1_PA_MASK)

#define XRDC_MDA_W0_13_DFMT1_SA_MASK             (0xC0U)
#define XRDC_MDA_W0_13_DFMT1_SA_SHIFT            (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_13_DFMT1_SA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_13_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_13_DFMT1_SA_MASK)

#define XRDC_MDA_W0_13_DFMT1_DIDB_MASK           (0x100U)
#define XRDC_MDA_W0_13_DFMT1_DIDB_SHIFT          (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_13_DFMT1_DIDB(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_13_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_13_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_13_DFMT1_DFMT_MASK           (0x20000000U)
#define XRDC_MDA_W0_13_DFMT1_DFMT_SHIFT          (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_13_DFMT1_DFMT(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_13_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_13_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_13_DFMT1_LK1_MASK            (0x40000000U)
#define XRDC_MDA_W0_13_DFMT1_LK1_SHIFT           (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_13_DFMT1_LK1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_13_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_13_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_13_DFMT1_VLD_MASK            (0x80000000U)
#define XRDC_MDA_W0_13_DFMT1_VLD_SHIFT           (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_13_DFMT1_VLD(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_13_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_13_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_14_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_14_DFMT1_DID_MASK            (0xFU)
#define XRDC_MDA_W0_14_DFMT1_DID_SHIFT           (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_14_DFMT1_DID(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_14_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_14_DFMT1_DID_MASK)

#define XRDC_MDA_W0_14_DFMT1_PA_MASK             (0x30U)
#define XRDC_MDA_W0_14_DFMT1_PA_SHIFT            (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_14_DFMT1_PA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_14_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_14_DFMT1_PA_MASK)

#define XRDC_MDA_W0_14_DFMT1_SA_MASK             (0xC0U)
#define XRDC_MDA_W0_14_DFMT1_SA_SHIFT            (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_14_DFMT1_SA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_14_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_14_DFMT1_SA_MASK)

#define XRDC_MDA_W0_14_DFMT1_DIDB_MASK           (0x100U)
#define XRDC_MDA_W0_14_DFMT1_DIDB_SHIFT          (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_14_DFMT1_DIDB(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_14_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_14_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_14_DFMT1_DFMT_MASK           (0x20000000U)
#define XRDC_MDA_W0_14_DFMT1_DFMT_SHIFT          (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_14_DFMT1_DFMT(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_14_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_14_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_14_DFMT1_LK1_MASK            (0x40000000U)
#define XRDC_MDA_W0_14_DFMT1_LK1_SHIFT           (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_14_DFMT1_LK1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_14_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_14_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_14_DFMT1_VLD_MASK            (0x80000000U)
#define XRDC_MDA_W0_14_DFMT1_VLD_SHIFT           (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_14_DFMT1_VLD(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_14_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_14_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_15_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_15_DFMT1_DID_MASK            (0xFU)
#define XRDC_MDA_W0_15_DFMT1_DID_SHIFT           (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_15_DFMT1_DID(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_15_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_15_DFMT1_DID_MASK)

#define XRDC_MDA_W0_15_DFMT1_PA_MASK             (0x30U)
#define XRDC_MDA_W0_15_DFMT1_PA_SHIFT            (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_15_DFMT1_PA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_15_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_15_DFMT1_PA_MASK)

#define XRDC_MDA_W0_15_DFMT1_SA_MASK             (0xC0U)
#define XRDC_MDA_W0_15_DFMT1_SA_SHIFT            (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_15_DFMT1_SA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_15_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_15_DFMT1_SA_MASK)

#define XRDC_MDA_W0_15_DFMT1_DIDB_MASK           (0x100U)
#define XRDC_MDA_W0_15_DFMT1_DIDB_SHIFT          (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_15_DFMT1_DIDB(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_15_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_15_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_15_DFMT1_DFMT_MASK           (0x20000000U)
#define XRDC_MDA_W0_15_DFMT1_DFMT_SHIFT          (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_15_DFMT1_DFMT(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_15_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_15_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_15_DFMT1_LK1_MASK            (0x40000000U)
#define XRDC_MDA_W0_15_DFMT1_LK1_SHIFT           (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_15_DFMT1_LK1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_15_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_15_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_15_DFMT1_VLD_MASK            (0x80000000U)
#define XRDC_MDA_W0_15_DFMT1_VLD_SHIFT           (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_15_DFMT1_VLD(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_15_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_15_DFMT1_VLD_MASK)
/*! @} */

/*! @name MDA_W0_16_DFMT1 - Master Domain Assignment */
/*! @{ */

#define XRDC_MDA_W0_16_DFMT1_DID_MASK            (0xFU)
#define XRDC_MDA_W0_16_DFMT1_DID_SHIFT           (0U)
/*! DID - Domain identifier */
#define XRDC_MDA_W0_16_DFMT1_DID(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_16_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_16_DFMT1_DID_MASK)

#define XRDC_MDA_W0_16_DFMT1_PA_MASK             (0x30U)
#define XRDC_MDA_W0_16_DFMT1_PA_SHIFT            (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define XRDC_MDA_W0_16_DFMT1_PA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_16_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_16_DFMT1_PA_MASK)

#define XRDC_MDA_W0_16_DFMT1_SA_MASK             (0xC0U)
#define XRDC_MDA_W0_16_DFMT1_SA_SHIFT            (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define XRDC_MDA_W0_16_DFMT1_SA(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_16_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_16_DFMT1_SA_MASK)

#define XRDC_MDA_W0_16_DFMT1_DIDB_MASK           (0x100U)
#define XRDC_MDA_W0_16_DFMT1_DIDB_SHIFT          (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define XRDC_MDA_W0_16_DFMT1_DIDB(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_16_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_16_DFMT1_DIDB_MASK)

#define XRDC_MDA_W0_16_DFMT1_DFMT_MASK           (0x20000000U)
#define XRDC_MDA_W0_16_DFMT1_DFMT_SHIFT          (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define XRDC_MDA_W0_16_DFMT1_DFMT(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_16_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_16_DFMT1_DFMT_MASK)

#define XRDC_MDA_W0_16_DFMT1_LK1_MASK            (0x40000000U)
#define XRDC_MDA_W0_16_DFMT1_LK1_SHIFT           (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define XRDC_MDA_W0_16_DFMT1_LK1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_16_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_16_DFMT1_LK1_MASK)

#define XRDC_MDA_W0_16_DFMT1_VLD_MASK            (0x80000000U)
#define XRDC_MDA_W0_16_DFMT1_VLD_SHIFT           (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define XRDC_MDA_W0_16_DFMT1_VLD(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_16_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_16_DFMT1_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_0 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_0_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_0_0_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_0_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_0_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_0_D0ACP_MASK)

#define XRDC_PDAC_W0_0_0_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_0_0_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_0_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_0_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_0_D1ACP_MASK)

#define XRDC_PDAC_W0_0_0_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_0_0_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_0_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_0_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_0_D2ACP_MASK)

#define XRDC_PDAC_W0_0_0_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_0_0_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_0_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_0_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_0_D3ACP_MASK)

#define XRDC_PDAC_W0_0_0_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_0_0_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_0_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_0_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_0_D4ACP_MASK)

#define XRDC_PDAC_W0_0_0_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_0_0_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_0_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_0_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_0_D5ACP_MASK)

#define XRDC_PDAC_W0_0_0_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_0_0_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_0_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_0_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_0_D6ACP_MASK)

#define XRDC_PDAC_W0_0_0_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_0_0_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_0_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_0_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_0_D7ACP_MASK)

#define XRDC_PDAC_W0_0_0_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_0_0_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_0_EALO_SHIFT)) & XRDC_PDAC_W0_0_0_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_0 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_0_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_0_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_0_EAL_SHIFT)) & XRDC_PDAC_W1_0_0_EAL_MASK)

#define XRDC_PDAC_W1_0_0_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_0_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_0_LK2_SHIFT)) & XRDC_PDAC_W1_0_0_LK2_MASK)

#define XRDC_PDAC_W1_0_0_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_0_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_0_VLD_SHIFT)) & XRDC_PDAC_W1_0_0_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_1 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_1_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_0_1_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_1_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_1_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_1_D0ACP_MASK)

#define XRDC_PDAC_W0_0_1_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_0_1_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_1_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_1_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_1_D1ACP_MASK)

#define XRDC_PDAC_W0_0_1_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_0_1_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_1_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_1_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_1_D2ACP_MASK)

#define XRDC_PDAC_W0_0_1_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_0_1_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_1_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_1_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_1_D3ACP_MASK)

#define XRDC_PDAC_W0_0_1_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_0_1_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_1_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_1_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_1_D4ACP_MASK)

#define XRDC_PDAC_W0_0_1_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_0_1_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_1_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_1_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_1_D5ACP_MASK)

#define XRDC_PDAC_W0_0_1_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_0_1_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_1_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_1_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_1_D6ACP_MASK)

#define XRDC_PDAC_W0_0_1_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_0_1_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_1_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_1_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_1_D7ACP_MASK)

#define XRDC_PDAC_W0_0_1_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_0_1_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_1_EALO_SHIFT)) & XRDC_PDAC_W0_0_1_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_1 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_1_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_0_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_1_EAL_SHIFT)) & XRDC_PDAC_W1_0_1_EAL_MASK)

#define XRDC_PDAC_W1_0_1_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_0_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_1_LK2_SHIFT)) & XRDC_PDAC_W1_0_1_LK2_MASK)

#define XRDC_PDAC_W1_0_1_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_0_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_1_VLD_SHIFT)) & XRDC_PDAC_W1_0_1_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_2 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_2_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_0_2_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_2_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_2_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_2_D0ACP_MASK)

#define XRDC_PDAC_W0_0_2_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_0_2_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_2_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_2_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_2_D1ACP_MASK)

#define XRDC_PDAC_W0_0_2_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_0_2_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_2_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_2_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_2_D2ACP_MASK)

#define XRDC_PDAC_W0_0_2_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_0_2_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_2_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_2_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_2_D3ACP_MASK)

#define XRDC_PDAC_W0_0_2_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_0_2_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_2_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_2_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_2_D4ACP_MASK)

#define XRDC_PDAC_W0_0_2_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_0_2_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_2_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_2_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_2_D5ACP_MASK)

#define XRDC_PDAC_W0_0_2_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_0_2_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_2_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_2_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_2_D6ACP_MASK)

#define XRDC_PDAC_W0_0_2_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_0_2_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_2_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_2_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_2_D7ACP_MASK)

#define XRDC_PDAC_W0_0_2_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_0_2_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_2_EALO_SHIFT)) & XRDC_PDAC_W0_0_2_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_2 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_2_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_0_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_2_EAL_SHIFT)) & XRDC_PDAC_W1_0_2_EAL_MASK)

#define XRDC_PDAC_W1_0_2_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_0_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_2_LK2_SHIFT)) & XRDC_PDAC_W1_0_2_LK2_MASK)

#define XRDC_PDAC_W1_0_2_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_0_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_2_VLD_SHIFT)) & XRDC_PDAC_W1_0_2_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_3 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_3_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_0_3_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_3_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_3_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_3_D0ACP_MASK)

#define XRDC_PDAC_W0_0_3_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_0_3_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_3_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_3_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_3_D1ACP_MASK)

#define XRDC_PDAC_W0_0_3_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_0_3_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_3_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_3_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_3_D2ACP_MASK)

#define XRDC_PDAC_W0_0_3_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_0_3_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_3_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_3_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_3_D3ACP_MASK)

#define XRDC_PDAC_W0_0_3_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_0_3_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_3_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_3_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_3_D4ACP_MASK)

#define XRDC_PDAC_W0_0_3_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_0_3_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_3_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_3_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_3_D5ACP_MASK)

#define XRDC_PDAC_W0_0_3_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_0_3_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_3_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_3_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_3_D6ACP_MASK)

#define XRDC_PDAC_W0_0_3_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_0_3_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_3_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_3_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_3_D7ACP_MASK)

#define XRDC_PDAC_W0_0_3_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_0_3_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_3_EALO_SHIFT)) & XRDC_PDAC_W0_0_3_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_3 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_3_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_0_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_3_EAL_SHIFT)) & XRDC_PDAC_W1_0_3_EAL_MASK)

#define XRDC_PDAC_W1_0_3_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_0_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_3_LK2_SHIFT)) & XRDC_PDAC_W1_0_3_LK2_MASK)

#define XRDC_PDAC_W1_0_3_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_0_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_3_VLD_SHIFT)) & XRDC_PDAC_W1_0_3_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_4 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_4_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_0_4_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_4_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_4_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_4_D0ACP_MASK)

#define XRDC_PDAC_W0_0_4_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_0_4_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_4_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_4_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_4_D1ACP_MASK)

#define XRDC_PDAC_W0_0_4_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_0_4_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_4_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_4_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_4_D2ACP_MASK)

#define XRDC_PDAC_W0_0_4_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_0_4_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_4_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_4_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_4_D3ACP_MASK)

#define XRDC_PDAC_W0_0_4_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_0_4_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_4_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_4_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_4_D4ACP_MASK)

#define XRDC_PDAC_W0_0_4_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_0_4_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_4_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_4_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_4_D5ACP_MASK)

#define XRDC_PDAC_W0_0_4_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_0_4_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_4_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_4_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_4_D6ACP_MASK)

#define XRDC_PDAC_W0_0_4_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_0_4_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_4_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_4_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_4_D7ACP_MASK)

#define XRDC_PDAC_W0_0_4_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_0_4_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_4_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_4_EALO_SHIFT)) & XRDC_PDAC_W0_0_4_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_4 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_4_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_0_4_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_4_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_4_EAL_SHIFT)) & XRDC_PDAC_W1_0_4_EAL_MASK)

#define XRDC_PDAC_W1_0_4_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_0_4_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_4_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_4_LK2_SHIFT)) & XRDC_PDAC_W1_0_4_LK2_MASK)

#define XRDC_PDAC_W1_0_4_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_0_4_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_4_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_4_VLD_SHIFT)) & XRDC_PDAC_W1_0_4_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_5 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_5_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_0_5_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_5_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_5_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_5_D0ACP_MASK)

#define XRDC_PDAC_W0_0_5_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_0_5_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_5_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_5_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_5_D1ACP_MASK)

#define XRDC_PDAC_W0_0_5_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_0_5_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_5_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_5_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_5_D2ACP_MASK)

#define XRDC_PDAC_W0_0_5_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_0_5_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_5_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_5_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_5_D3ACP_MASK)

#define XRDC_PDAC_W0_0_5_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_0_5_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_5_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_5_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_5_D4ACP_MASK)

#define XRDC_PDAC_W0_0_5_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_0_5_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_5_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_5_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_5_D5ACP_MASK)

#define XRDC_PDAC_W0_0_5_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_0_5_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_5_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_5_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_5_D6ACP_MASK)

#define XRDC_PDAC_W0_0_5_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_0_5_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_5_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_5_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_5_D7ACP_MASK)

#define XRDC_PDAC_W0_0_5_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_0_5_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_5_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_5_EALO_SHIFT)) & XRDC_PDAC_W0_0_5_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_5 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_5_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_0_5_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_5_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_5_EAL_SHIFT)) & XRDC_PDAC_W1_0_5_EAL_MASK)

#define XRDC_PDAC_W1_0_5_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_0_5_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_5_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_5_LK2_SHIFT)) & XRDC_PDAC_W1_0_5_LK2_MASK)

#define XRDC_PDAC_W1_0_5_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_0_5_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_5_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_5_VLD_SHIFT)) & XRDC_PDAC_W1_0_5_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_6 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_6_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_0_6_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_6_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_6_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_6_D0ACP_MASK)

#define XRDC_PDAC_W0_0_6_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_0_6_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_6_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_6_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_6_D1ACP_MASK)

#define XRDC_PDAC_W0_0_6_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_0_6_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_6_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_6_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_6_D2ACP_MASK)

#define XRDC_PDAC_W0_0_6_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_0_6_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_6_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_6_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_6_D3ACP_MASK)

#define XRDC_PDAC_W0_0_6_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_0_6_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_6_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_6_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_6_D4ACP_MASK)

#define XRDC_PDAC_W0_0_6_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_0_6_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_6_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_6_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_6_D5ACP_MASK)

#define XRDC_PDAC_W0_0_6_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_0_6_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_6_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_6_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_6_D6ACP_MASK)

#define XRDC_PDAC_W0_0_6_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_0_6_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_6_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_6_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_6_D7ACP_MASK)

#define XRDC_PDAC_W0_0_6_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_0_6_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_6_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_6_EALO_SHIFT)) & XRDC_PDAC_W0_0_6_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_6 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_6_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_0_6_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_6_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_6_EAL_SHIFT)) & XRDC_PDAC_W1_0_6_EAL_MASK)

#define XRDC_PDAC_W1_0_6_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_0_6_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_6_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_6_LK2_SHIFT)) & XRDC_PDAC_W1_0_6_LK2_MASK)

#define XRDC_PDAC_W1_0_6_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_0_6_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_6_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_6_VLD_SHIFT)) & XRDC_PDAC_W1_0_6_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_7 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_7_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_0_7_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_7_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_7_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_7_D0ACP_MASK)

#define XRDC_PDAC_W0_0_7_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_0_7_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_7_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_7_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_7_D1ACP_MASK)

#define XRDC_PDAC_W0_0_7_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_0_7_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_7_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_7_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_7_D2ACP_MASK)

#define XRDC_PDAC_W0_0_7_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_0_7_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_7_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_7_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_7_D3ACP_MASK)

#define XRDC_PDAC_W0_0_7_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_0_7_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_7_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_7_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_7_D4ACP_MASK)

#define XRDC_PDAC_W0_0_7_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_0_7_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_7_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_7_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_7_D5ACP_MASK)

#define XRDC_PDAC_W0_0_7_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_0_7_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_7_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_7_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_7_D6ACP_MASK)

#define XRDC_PDAC_W0_0_7_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_0_7_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_7_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_7_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_7_D7ACP_MASK)

#define XRDC_PDAC_W0_0_7_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_0_7_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_7_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_7_EALO_SHIFT)) & XRDC_PDAC_W0_0_7_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_7 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_7_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_0_7_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_7_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_7_EAL_SHIFT)) & XRDC_PDAC_W1_0_7_EAL_MASK)

#define XRDC_PDAC_W1_0_7_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_0_7_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_7_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_7_LK2_SHIFT)) & XRDC_PDAC_W1_0_7_LK2_MASK)

#define XRDC_PDAC_W1_0_7_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_0_7_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_7_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_7_VLD_SHIFT)) & XRDC_PDAC_W1_0_7_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_8 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_8_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_0_8_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_8_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_8_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_8_D0ACP_MASK)

#define XRDC_PDAC_W0_0_8_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_0_8_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_8_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_8_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_8_D1ACP_MASK)

#define XRDC_PDAC_W0_0_8_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_0_8_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_8_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_8_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_8_D2ACP_MASK)

#define XRDC_PDAC_W0_0_8_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_0_8_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_8_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_8_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_8_D3ACP_MASK)

#define XRDC_PDAC_W0_0_8_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_0_8_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_8_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_8_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_8_D4ACP_MASK)

#define XRDC_PDAC_W0_0_8_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_0_8_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_8_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_8_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_8_D5ACP_MASK)

#define XRDC_PDAC_W0_0_8_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_0_8_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_8_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_8_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_8_D6ACP_MASK)

#define XRDC_PDAC_W0_0_8_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_0_8_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_8_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_8_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_8_D7ACP_MASK)

#define XRDC_PDAC_W0_0_8_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_0_8_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_8_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_8_EALO_SHIFT)) & XRDC_PDAC_W0_0_8_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_8 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_8_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_0_8_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_8_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_8_EAL_SHIFT)) & XRDC_PDAC_W1_0_8_EAL_MASK)

#define XRDC_PDAC_W1_0_8_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_0_8_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_8_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_8_LK2_SHIFT)) & XRDC_PDAC_W1_0_8_LK2_MASK)

#define XRDC_PDAC_W1_0_8_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_0_8_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_8_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_8_VLD_SHIFT)) & XRDC_PDAC_W1_0_8_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_9 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_9_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_0_9_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_9_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_9_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_9_D0ACP_MASK)

#define XRDC_PDAC_W0_0_9_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_0_9_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_9_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_9_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_9_D1ACP_MASK)

#define XRDC_PDAC_W0_0_9_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_0_9_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_9_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_9_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_9_D2ACP_MASK)

#define XRDC_PDAC_W0_0_9_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_0_9_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_9_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_9_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_9_D3ACP_MASK)

#define XRDC_PDAC_W0_0_9_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_0_9_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_9_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_9_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_9_D4ACP_MASK)

#define XRDC_PDAC_W0_0_9_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_0_9_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_9_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_9_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_9_D5ACP_MASK)

#define XRDC_PDAC_W0_0_9_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_0_9_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_9_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_9_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_9_D6ACP_MASK)

#define XRDC_PDAC_W0_0_9_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_0_9_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_9_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_9_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_9_D7ACP_MASK)

#define XRDC_PDAC_W0_0_9_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_0_9_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_9_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_9_EALO_SHIFT)) & XRDC_PDAC_W0_0_9_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_9 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_9_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_0_9_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_9_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_9_EAL_SHIFT)) & XRDC_PDAC_W1_0_9_EAL_MASK)

#define XRDC_PDAC_W1_0_9_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_0_9_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_9_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_9_LK2_SHIFT)) & XRDC_PDAC_W1_0_9_LK2_MASK)

#define XRDC_PDAC_W1_0_9_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_0_9_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_9_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_9_VLD_SHIFT)) & XRDC_PDAC_W1_0_9_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_10 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_10_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_10_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_10_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_10_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_10_D0ACP_MASK)

#define XRDC_PDAC_W0_0_10_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_10_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_10_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_10_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_10_D1ACP_MASK)

#define XRDC_PDAC_W0_0_10_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_10_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_10_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_10_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_10_D2ACP_MASK)

#define XRDC_PDAC_W0_0_10_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_10_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_10_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_10_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_10_D3ACP_MASK)

#define XRDC_PDAC_W0_0_10_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_10_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_10_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_10_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_10_D4ACP_MASK)

#define XRDC_PDAC_W0_0_10_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_10_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_10_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_10_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_10_D5ACP_MASK)

#define XRDC_PDAC_W0_0_10_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_10_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_10_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_10_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_10_D6ACP_MASK)

#define XRDC_PDAC_W0_0_10_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_10_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_10_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_10_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_10_D7ACP_MASK)

#define XRDC_PDAC_W0_0_10_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_10_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_10_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_10_EALO_SHIFT)) & XRDC_PDAC_W0_0_10_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_10 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_10_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_10_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_10_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_10_EAL_SHIFT)) & XRDC_PDAC_W1_0_10_EAL_MASK)

#define XRDC_PDAC_W1_0_10_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_10_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_10_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_10_LK2_SHIFT)) & XRDC_PDAC_W1_0_10_LK2_MASK)

#define XRDC_PDAC_W1_0_10_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_10_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_10_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_10_VLD_SHIFT)) & XRDC_PDAC_W1_0_10_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_11 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_11_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_11_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_11_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_11_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_11_D0ACP_MASK)

#define XRDC_PDAC_W0_0_11_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_11_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_11_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_11_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_11_D1ACP_MASK)

#define XRDC_PDAC_W0_0_11_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_11_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_11_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_11_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_11_D2ACP_MASK)

#define XRDC_PDAC_W0_0_11_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_11_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_11_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_11_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_11_D3ACP_MASK)

#define XRDC_PDAC_W0_0_11_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_11_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_11_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_11_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_11_D4ACP_MASK)

#define XRDC_PDAC_W0_0_11_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_11_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_11_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_11_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_11_D5ACP_MASK)

#define XRDC_PDAC_W0_0_11_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_11_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_11_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_11_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_11_D6ACP_MASK)

#define XRDC_PDAC_W0_0_11_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_11_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_11_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_11_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_11_D7ACP_MASK)

#define XRDC_PDAC_W0_0_11_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_11_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_11_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_11_EALO_SHIFT)) & XRDC_PDAC_W0_0_11_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_11 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_11_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_11_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_11_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_11_EAL_SHIFT)) & XRDC_PDAC_W1_0_11_EAL_MASK)

#define XRDC_PDAC_W1_0_11_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_11_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_11_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_11_LK2_SHIFT)) & XRDC_PDAC_W1_0_11_LK2_MASK)

#define XRDC_PDAC_W1_0_11_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_11_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_11_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_11_VLD_SHIFT)) & XRDC_PDAC_W1_0_11_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_12 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_12_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_12_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_12_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_12_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_12_D0ACP_MASK)

#define XRDC_PDAC_W0_0_12_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_12_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_12_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_12_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_12_D1ACP_MASK)

#define XRDC_PDAC_W0_0_12_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_12_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_12_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_12_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_12_D2ACP_MASK)

#define XRDC_PDAC_W0_0_12_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_12_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_12_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_12_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_12_D3ACP_MASK)

#define XRDC_PDAC_W0_0_12_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_12_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_12_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_12_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_12_D4ACP_MASK)

#define XRDC_PDAC_W0_0_12_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_12_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_12_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_12_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_12_D5ACP_MASK)

#define XRDC_PDAC_W0_0_12_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_12_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_12_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_12_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_12_D6ACP_MASK)

#define XRDC_PDAC_W0_0_12_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_12_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_12_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_12_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_12_D7ACP_MASK)

#define XRDC_PDAC_W0_0_12_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_12_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_12_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_12_EALO_SHIFT)) & XRDC_PDAC_W0_0_12_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_12 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_12_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_12_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_12_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_12_EAL_SHIFT)) & XRDC_PDAC_W1_0_12_EAL_MASK)

#define XRDC_PDAC_W1_0_12_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_12_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_12_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_12_LK2_SHIFT)) & XRDC_PDAC_W1_0_12_LK2_MASK)

#define XRDC_PDAC_W1_0_12_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_12_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_12_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_12_VLD_SHIFT)) & XRDC_PDAC_W1_0_12_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_13 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_13_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_13_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_13_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_13_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_13_D0ACP_MASK)

#define XRDC_PDAC_W0_0_13_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_13_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_13_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_13_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_13_D1ACP_MASK)

#define XRDC_PDAC_W0_0_13_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_13_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_13_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_13_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_13_D2ACP_MASK)

#define XRDC_PDAC_W0_0_13_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_13_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_13_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_13_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_13_D3ACP_MASK)

#define XRDC_PDAC_W0_0_13_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_13_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_13_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_13_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_13_D4ACP_MASK)

#define XRDC_PDAC_W0_0_13_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_13_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_13_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_13_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_13_D5ACP_MASK)

#define XRDC_PDAC_W0_0_13_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_13_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_13_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_13_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_13_D6ACP_MASK)

#define XRDC_PDAC_W0_0_13_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_13_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_13_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_13_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_13_D7ACP_MASK)

#define XRDC_PDAC_W0_0_13_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_13_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_13_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_13_EALO_SHIFT)) & XRDC_PDAC_W0_0_13_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_13 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_13_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_13_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_13_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_13_EAL_SHIFT)) & XRDC_PDAC_W1_0_13_EAL_MASK)

#define XRDC_PDAC_W1_0_13_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_13_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_13_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_13_LK2_SHIFT)) & XRDC_PDAC_W1_0_13_LK2_MASK)

#define XRDC_PDAC_W1_0_13_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_13_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_13_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_13_VLD_SHIFT)) & XRDC_PDAC_W1_0_13_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_14 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_14_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_14_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_14_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_14_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_14_D0ACP_MASK)

#define XRDC_PDAC_W0_0_14_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_14_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_14_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_14_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_14_D1ACP_MASK)

#define XRDC_PDAC_W0_0_14_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_14_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_14_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_14_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_14_D2ACP_MASK)

#define XRDC_PDAC_W0_0_14_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_14_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_14_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_14_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_14_D3ACP_MASK)

#define XRDC_PDAC_W0_0_14_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_14_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_14_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_14_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_14_D4ACP_MASK)

#define XRDC_PDAC_W0_0_14_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_14_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_14_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_14_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_14_D5ACP_MASK)

#define XRDC_PDAC_W0_0_14_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_14_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_14_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_14_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_14_D6ACP_MASK)

#define XRDC_PDAC_W0_0_14_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_14_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_14_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_14_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_14_D7ACP_MASK)

#define XRDC_PDAC_W0_0_14_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_14_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_14_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_14_EALO_SHIFT)) & XRDC_PDAC_W0_0_14_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_14 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_14_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_14_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_14_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_14_EAL_SHIFT)) & XRDC_PDAC_W1_0_14_EAL_MASK)

#define XRDC_PDAC_W1_0_14_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_14_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_14_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_14_LK2_SHIFT)) & XRDC_PDAC_W1_0_14_LK2_MASK)

#define XRDC_PDAC_W1_0_14_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_14_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_14_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_14_VLD_SHIFT)) & XRDC_PDAC_W1_0_14_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_15 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_15_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_15_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_15_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_15_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_15_D0ACP_MASK)

#define XRDC_PDAC_W0_0_15_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_15_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_15_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_15_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_15_D1ACP_MASK)

#define XRDC_PDAC_W0_0_15_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_15_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_15_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_15_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_15_D2ACP_MASK)

#define XRDC_PDAC_W0_0_15_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_15_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_15_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_15_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_15_D3ACP_MASK)

#define XRDC_PDAC_W0_0_15_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_15_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_15_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_15_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_15_D4ACP_MASK)

#define XRDC_PDAC_W0_0_15_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_15_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_15_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_15_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_15_D5ACP_MASK)

#define XRDC_PDAC_W0_0_15_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_15_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_15_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_15_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_15_D6ACP_MASK)

#define XRDC_PDAC_W0_0_15_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_15_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_15_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_15_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_15_D7ACP_MASK)

#define XRDC_PDAC_W0_0_15_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_15_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_15_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_15_EALO_SHIFT)) & XRDC_PDAC_W0_0_15_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_15 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_15_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_15_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_15_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_15_EAL_SHIFT)) & XRDC_PDAC_W1_0_15_EAL_MASK)

#define XRDC_PDAC_W1_0_15_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_15_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_15_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_15_LK2_SHIFT)) & XRDC_PDAC_W1_0_15_LK2_MASK)

#define XRDC_PDAC_W1_0_15_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_15_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_15_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_15_VLD_SHIFT)) & XRDC_PDAC_W1_0_15_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_16 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_16_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_16_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_16_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_16_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_16_D0ACP_MASK)

#define XRDC_PDAC_W0_0_16_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_16_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_16_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_16_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_16_D1ACP_MASK)

#define XRDC_PDAC_W0_0_16_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_16_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_16_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_16_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_16_D2ACP_MASK)

#define XRDC_PDAC_W0_0_16_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_16_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_16_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_16_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_16_D3ACP_MASK)

#define XRDC_PDAC_W0_0_16_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_16_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_16_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_16_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_16_D4ACP_MASK)

#define XRDC_PDAC_W0_0_16_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_16_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_16_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_16_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_16_D5ACP_MASK)

#define XRDC_PDAC_W0_0_16_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_16_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_16_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_16_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_16_D6ACP_MASK)

#define XRDC_PDAC_W0_0_16_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_16_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_16_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_16_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_16_D7ACP_MASK)

#define XRDC_PDAC_W0_0_16_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_16_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_16_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_16_EALO_SHIFT)) & XRDC_PDAC_W0_0_16_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_16 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_16_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_16_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_16_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_16_EAL_SHIFT)) & XRDC_PDAC_W1_0_16_EAL_MASK)

#define XRDC_PDAC_W1_0_16_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_16_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_16_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_16_LK2_SHIFT)) & XRDC_PDAC_W1_0_16_LK2_MASK)

#define XRDC_PDAC_W1_0_16_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_16_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_16_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_16_VLD_SHIFT)) & XRDC_PDAC_W1_0_16_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_17 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_17_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_17_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_17_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_17_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_17_D0ACP_MASK)

#define XRDC_PDAC_W0_0_17_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_17_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_17_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_17_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_17_D1ACP_MASK)

#define XRDC_PDAC_W0_0_17_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_17_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_17_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_17_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_17_D2ACP_MASK)

#define XRDC_PDAC_W0_0_17_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_17_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_17_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_17_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_17_D3ACP_MASK)

#define XRDC_PDAC_W0_0_17_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_17_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_17_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_17_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_17_D4ACP_MASK)

#define XRDC_PDAC_W0_0_17_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_17_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_17_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_17_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_17_D5ACP_MASK)

#define XRDC_PDAC_W0_0_17_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_17_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_17_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_17_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_17_D6ACP_MASK)

#define XRDC_PDAC_W0_0_17_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_17_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_17_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_17_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_17_D7ACP_MASK)

#define XRDC_PDAC_W0_0_17_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_17_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_17_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_17_EALO_SHIFT)) & XRDC_PDAC_W0_0_17_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_17 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_17_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_17_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_17_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_17_EAL_SHIFT)) & XRDC_PDAC_W1_0_17_EAL_MASK)

#define XRDC_PDAC_W1_0_17_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_17_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_17_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_17_LK2_SHIFT)) & XRDC_PDAC_W1_0_17_LK2_MASK)

#define XRDC_PDAC_W1_0_17_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_17_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_17_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_17_VLD_SHIFT)) & XRDC_PDAC_W1_0_17_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_18 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_18_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_18_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_18_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_18_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_18_D0ACP_MASK)

#define XRDC_PDAC_W0_0_18_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_18_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_18_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_18_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_18_D1ACP_MASK)

#define XRDC_PDAC_W0_0_18_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_18_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_18_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_18_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_18_D2ACP_MASK)

#define XRDC_PDAC_W0_0_18_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_18_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_18_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_18_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_18_D3ACP_MASK)

#define XRDC_PDAC_W0_0_18_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_18_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_18_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_18_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_18_D4ACP_MASK)

#define XRDC_PDAC_W0_0_18_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_18_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_18_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_18_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_18_D5ACP_MASK)

#define XRDC_PDAC_W0_0_18_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_18_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_18_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_18_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_18_D6ACP_MASK)

#define XRDC_PDAC_W0_0_18_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_18_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_18_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_18_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_18_D7ACP_MASK)

#define XRDC_PDAC_W0_0_18_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_18_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_18_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_18_EALO_SHIFT)) & XRDC_PDAC_W0_0_18_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_18 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_18_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_18_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_18_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_18_EAL_SHIFT)) & XRDC_PDAC_W1_0_18_EAL_MASK)

#define XRDC_PDAC_W1_0_18_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_18_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_18_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_18_LK2_SHIFT)) & XRDC_PDAC_W1_0_18_LK2_MASK)

#define XRDC_PDAC_W1_0_18_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_18_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_18_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_18_VLD_SHIFT)) & XRDC_PDAC_W1_0_18_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_19 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_19_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_19_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_19_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_19_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_19_D0ACP_MASK)

#define XRDC_PDAC_W0_0_19_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_19_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_19_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_19_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_19_D1ACP_MASK)

#define XRDC_PDAC_W0_0_19_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_19_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_19_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_19_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_19_D2ACP_MASK)

#define XRDC_PDAC_W0_0_19_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_19_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_19_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_19_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_19_D3ACP_MASK)

#define XRDC_PDAC_W0_0_19_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_19_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_19_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_19_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_19_D4ACP_MASK)

#define XRDC_PDAC_W0_0_19_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_19_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_19_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_19_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_19_D5ACP_MASK)

#define XRDC_PDAC_W0_0_19_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_19_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_19_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_19_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_19_D6ACP_MASK)

#define XRDC_PDAC_W0_0_19_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_19_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_19_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_19_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_19_D7ACP_MASK)

#define XRDC_PDAC_W0_0_19_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_19_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_19_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_19_EALO_SHIFT)) & XRDC_PDAC_W0_0_19_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_19 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_19_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_19_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_19_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_19_EAL_SHIFT)) & XRDC_PDAC_W1_0_19_EAL_MASK)

#define XRDC_PDAC_W1_0_19_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_19_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_19_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_19_LK2_SHIFT)) & XRDC_PDAC_W1_0_19_LK2_MASK)

#define XRDC_PDAC_W1_0_19_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_19_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_19_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_19_VLD_SHIFT)) & XRDC_PDAC_W1_0_19_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_20 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_20_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_20_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_20_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_20_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_20_D0ACP_MASK)

#define XRDC_PDAC_W0_0_20_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_20_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_20_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_20_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_20_D1ACP_MASK)

#define XRDC_PDAC_W0_0_20_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_20_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_20_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_20_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_20_D2ACP_MASK)

#define XRDC_PDAC_W0_0_20_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_20_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_20_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_20_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_20_D3ACP_MASK)

#define XRDC_PDAC_W0_0_20_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_20_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_20_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_20_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_20_D4ACP_MASK)

#define XRDC_PDAC_W0_0_20_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_20_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_20_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_20_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_20_D5ACP_MASK)

#define XRDC_PDAC_W0_0_20_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_20_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_20_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_20_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_20_D6ACP_MASK)

#define XRDC_PDAC_W0_0_20_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_20_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_20_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_20_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_20_D7ACP_MASK)

#define XRDC_PDAC_W0_0_20_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_20_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_20_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_20_EALO_SHIFT)) & XRDC_PDAC_W0_0_20_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_20 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_20_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_20_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_20_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_20_EAL_SHIFT)) & XRDC_PDAC_W1_0_20_EAL_MASK)

#define XRDC_PDAC_W1_0_20_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_20_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_20_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_20_LK2_SHIFT)) & XRDC_PDAC_W1_0_20_LK2_MASK)

#define XRDC_PDAC_W1_0_20_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_20_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_20_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_20_VLD_SHIFT)) & XRDC_PDAC_W1_0_20_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_21 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_21_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_21_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_21_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_21_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_21_D0ACP_MASK)

#define XRDC_PDAC_W0_0_21_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_21_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_21_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_21_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_21_D1ACP_MASK)

#define XRDC_PDAC_W0_0_21_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_21_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_21_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_21_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_21_D2ACP_MASK)

#define XRDC_PDAC_W0_0_21_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_21_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_21_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_21_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_21_D3ACP_MASK)

#define XRDC_PDAC_W0_0_21_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_21_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_21_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_21_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_21_D4ACP_MASK)

#define XRDC_PDAC_W0_0_21_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_21_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_21_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_21_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_21_D5ACP_MASK)

#define XRDC_PDAC_W0_0_21_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_21_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_21_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_21_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_21_D6ACP_MASK)

#define XRDC_PDAC_W0_0_21_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_21_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_21_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_21_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_21_D7ACP_MASK)

#define XRDC_PDAC_W0_0_21_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_21_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_21_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_21_EALO_SHIFT)) & XRDC_PDAC_W0_0_21_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_21 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_21_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_21_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_21_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_21_EAL_SHIFT)) & XRDC_PDAC_W1_0_21_EAL_MASK)

#define XRDC_PDAC_W1_0_21_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_21_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_21_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_21_LK2_SHIFT)) & XRDC_PDAC_W1_0_21_LK2_MASK)

#define XRDC_PDAC_W1_0_21_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_21_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_21_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_21_VLD_SHIFT)) & XRDC_PDAC_W1_0_21_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_22 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_22_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_22_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_22_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_22_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_22_D0ACP_MASK)

#define XRDC_PDAC_W0_0_22_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_22_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_22_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_22_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_22_D1ACP_MASK)

#define XRDC_PDAC_W0_0_22_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_22_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_22_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_22_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_22_D2ACP_MASK)

#define XRDC_PDAC_W0_0_22_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_22_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_22_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_22_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_22_D3ACP_MASK)

#define XRDC_PDAC_W0_0_22_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_22_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_22_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_22_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_22_D4ACP_MASK)

#define XRDC_PDAC_W0_0_22_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_22_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_22_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_22_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_22_D5ACP_MASK)

#define XRDC_PDAC_W0_0_22_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_22_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_22_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_22_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_22_D6ACP_MASK)

#define XRDC_PDAC_W0_0_22_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_22_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_22_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_22_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_22_D7ACP_MASK)

#define XRDC_PDAC_W0_0_22_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_22_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_22_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_22_EALO_SHIFT)) & XRDC_PDAC_W0_0_22_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_22 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_22_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_22_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_22_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_22_EAL_SHIFT)) & XRDC_PDAC_W1_0_22_EAL_MASK)

#define XRDC_PDAC_W1_0_22_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_22_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_22_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_22_LK2_SHIFT)) & XRDC_PDAC_W1_0_22_LK2_MASK)

#define XRDC_PDAC_W1_0_22_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_22_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_22_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_22_VLD_SHIFT)) & XRDC_PDAC_W1_0_22_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_23 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_23_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_23_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_23_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_23_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_23_D0ACP_MASK)

#define XRDC_PDAC_W0_0_23_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_23_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_23_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_23_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_23_D1ACP_MASK)

#define XRDC_PDAC_W0_0_23_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_23_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_23_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_23_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_23_D2ACP_MASK)

#define XRDC_PDAC_W0_0_23_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_23_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_23_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_23_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_23_D3ACP_MASK)

#define XRDC_PDAC_W0_0_23_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_23_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_23_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_23_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_23_D4ACP_MASK)

#define XRDC_PDAC_W0_0_23_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_23_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_23_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_23_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_23_D5ACP_MASK)

#define XRDC_PDAC_W0_0_23_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_23_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_23_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_23_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_23_D6ACP_MASK)

#define XRDC_PDAC_W0_0_23_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_23_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_23_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_23_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_23_D7ACP_MASK)

#define XRDC_PDAC_W0_0_23_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_23_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_23_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_23_EALO_SHIFT)) & XRDC_PDAC_W0_0_23_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_23 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_23_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_23_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_23_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_23_EAL_SHIFT)) & XRDC_PDAC_W1_0_23_EAL_MASK)

#define XRDC_PDAC_W1_0_23_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_23_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_23_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_23_LK2_SHIFT)) & XRDC_PDAC_W1_0_23_LK2_MASK)

#define XRDC_PDAC_W1_0_23_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_23_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_23_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_23_VLD_SHIFT)) & XRDC_PDAC_W1_0_23_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_24 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_24_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_24_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_24_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_24_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_24_D0ACP_MASK)

#define XRDC_PDAC_W0_0_24_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_24_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_24_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_24_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_24_D1ACP_MASK)

#define XRDC_PDAC_W0_0_24_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_24_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_24_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_24_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_24_D2ACP_MASK)

#define XRDC_PDAC_W0_0_24_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_24_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_24_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_24_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_24_D3ACP_MASK)

#define XRDC_PDAC_W0_0_24_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_24_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_24_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_24_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_24_D4ACP_MASK)

#define XRDC_PDAC_W0_0_24_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_24_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_24_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_24_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_24_D5ACP_MASK)

#define XRDC_PDAC_W0_0_24_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_24_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_24_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_24_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_24_D6ACP_MASK)

#define XRDC_PDAC_W0_0_24_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_24_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_24_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_24_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_24_D7ACP_MASK)

#define XRDC_PDAC_W0_0_24_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_24_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_24_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_24_EALO_SHIFT)) & XRDC_PDAC_W0_0_24_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_24 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_24_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_24_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_24_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_24_EAL_SHIFT)) & XRDC_PDAC_W1_0_24_EAL_MASK)

#define XRDC_PDAC_W1_0_24_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_24_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_24_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_24_LK2_SHIFT)) & XRDC_PDAC_W1_0_24_LK2_MASK)

#define XRDC_PDAC_W1_0_24_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_24_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_24_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_24_VLD_SHIFT)) & XRDC_PDAC_W1_0_24_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_25 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_25_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_25_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_25_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_25_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_25_D0ACP_MASK)

#define XRDC_PDAC_W0_0_25_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_25_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_25_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_25_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_25_D1ACP_MASK)

#define XRDC_PDAC_W0_0_25_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_25_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_25_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_25_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_25_D2ACP_MASK)

#define XRDC_PDAC_W0_0_25_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_25_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_25_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_25_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_25_D3ACP_MASK)

#define XRDC_PDAC_W0_0_25_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_25_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_25_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_25_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_25_D4ACP_MASK)

#define XRDC_PDAC_W0_0_25_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_25_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_25_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_25_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_25_D5ACP_MASK)

#define XRDC_PDAC_W0_0_25_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_25_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_25_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_25_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_25_D6ACP_MASK)

#define XRDC_PDAC_W0_0_25_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_25_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_25_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_25_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_25_D7ACP_MASK)

#define XRDC_PDAC_W0_0_25_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_25_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_25_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_25_EALO_SHIFT)) & XRDC_PDAC_W0_0_25_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_25 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_25_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_25_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_25_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_25_EAL_SHIFT)) & XRDC_PDAC_W1_0_25_EAL_MASK)

#define XRDC_PDAC_W1_0_25_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_25_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_25_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_25_LK2_SHIFT)) & XRDC_PDAC_W1_0_25_LK2_MASK)

#define XRDC_PDAC_W1_0_25_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_25_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_25_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_25_VLD_SHIFT)) & XRDC_PDAC_W1_0_25_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_26 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_26_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_26_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_26_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_26_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_26_D0ACP_MASK)

#define XRDC_PDAC_W0_0_26_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_26_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_26_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_26_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_26_D1ACP_MASK)

#define XRDC_PDAC_W0_0_26_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_26_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_26_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_26_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_26_D2ACP_MASK)

#define XRDC_PDAC_W0_0_26_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_26_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_26_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_26_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_26_D3ACP_MASK)

#define XRDC_PDAC_W0_0_26_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_26_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_26_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_26_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_26_D4ACP_MASK)

#define XRDC_PDAC_W0_0_26_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_26_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_26_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_26_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_26_D5ACP_MASK)

#define XRDC_PDAC_W0_0_26_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_26_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_26_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_26_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_26_D6ACP_MASK)

#define XRDC_PDAC_W0_0_26_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_26_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_26_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_26_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_26_D7ACP_MASK)

#define XRDC_PDAC_W0_0_26_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_26_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_26_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_26_EALO_SHIFT)) & XRDC_PDAC_W0_0_26_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_26 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_26_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_26_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_26_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_26_EAL_SHIFT)) & XRDC_PDAC_W1_0_26_EAL_MASK)

#define XRDC_PDAC_W1_0_26_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_26_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_26_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_26_LK2_SHIFT)) & XRDC_PDAC_W1_0_26_LK2_MASK)

#define XRDC_PDAC_W1_0_26_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_26_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_26_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_26_VLD_SHIFT)) & XRDC_PDAC_W1_0_26_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_27 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_27_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_27_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_27_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_27_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_27_D0ACP_MASK)

#define XRDC_PDAC_W0_0_27_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_27_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_27_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_27_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_27_D1ACP_MASK)

#define XRDC_PDAC_W0_0_27_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_27_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_27_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_27_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_27_D2ACP_MASK)

#define XRDC_PDAC_W0_0_27_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_27_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_27_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_27_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_27_D3ACP_MASK)

#define XRDC_PDAC_W0_0_27_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_27_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_27_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_27_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_27_D4ACP_MASK)

#define XRDC_PDAC_W0_0_27_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_27_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_27_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_27_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_27_D5ACP_MASK)

#define XRDC_PDAC_W0_0_27_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_27_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_27_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_27_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_27_D6ACP_MASK)

#define XRDC_PDAC_W0_0_27_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_27_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_27_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_27_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_27_D7ACP_MASK)

#define XRDC_PDAC_W0_0_27_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_27_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_27_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_27_EALO_SHIFT)) & XRDC_PDAC_W0_0_27_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_27 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_27_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_27_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_27_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_27_EAL_SHIFT)) & XRDC_PDAC_W1_0_27_EAL_MASK)

#define XRDC_PDAC_W1_0_27_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_27_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_27_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_27_LK2_SHIFT)) & XRDC_PDAC_W1_0_27_LK2_MASK)

#define XRDC_PDAC_W1_0_27_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_27_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_27_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_27_VLD_SHIFT)) & XRDC_PDAC_W1_0_27_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_28 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_28_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_28_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_28_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_28_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_28_D0ACP_MASK)

#define XRDC_PDAC_W0_0_28_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_28_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_28_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_28_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_28_D1ACP_MASK)

#define XRDC_PDAC_W0_0_28_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_28_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_28_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_28_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_28_D2ACP_MASK)

#define XRDC_PDAC_W0_0_28_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_28_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_28_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_28_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_28_D3ACP_MASK)

#define XRDC_PDAC_W0_0_28_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_28_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_28_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_28_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_28_D4ACP_MASK)

#define XRDC_PDAC_W0_0_28_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_28_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_28_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_28_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_28_D5ACP_MASK)

#define XRDC_PDAC_W0_0_28_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_28_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_28_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_28_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_28_D6ACP_MASK)

#define XRDC_PDAC_W0_0_28_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_28_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_28_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_28_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_28_D7ACP_MASK)

#define XRDC_PDAC_W0_0_28_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_28_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_28_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_28_EALO_SHIFT)) & XRDC_PDAC_W0_0_28_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_28 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_28_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_28_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_28_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_28_EAL_SHIFT)) & XRDC_PDAC_W1_0_28_EAL_MASK)

#define XRDC_PDAC_W1_0_28_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_28_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_28_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_28_LK2_SHIFT)) & XRDC_PDAC_W1_0_28_LK2_MASK)

#define XRDC_PDAC_W1_0_28_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_28_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_28_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_28_VLD_SHIFT)) & XRDC_PDAC_W1_0_28_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_29 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_29_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_29_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_29_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_29_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_29_D0ACP_MASK)

#define XRDC_PDAC_W0_0_29_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_29_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_29_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_29_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_29_D1ACP_MASK)

#define XRDC_PDAC_W0_0_29_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_29_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_29_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_29_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_29_D2ACP_MASK)

#define XRDC_PDAC_W0_0_29_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_29_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_29_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_29_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_29_D3ACP_MASK)

#define XRDC_PDAC_W0_0_29_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_29_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_29_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_29_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_29_D4ACP_MASK)

#define XRDC_PDAC_W0_0_29_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_29_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_29_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_29_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_29_D5ACP_MASK)

#define XRDC_PDAC_W0_0_29_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_29_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_29_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_29_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_29_D6ACP_MASK)

#define XRDC_PDAC_W0_0_29_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_29_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_29_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_29_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_29_D7ACP_MASK)

#define XRDC_PDAC_W0_0_29_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_29_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_29_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_29_EALO_SHIFT)) & XRDC_PDAC_W0_0_29_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_29 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_29_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_29_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_29_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_29_EAL_SHIFT)) & XRDC_PDAC_W1_0_29_EAL_MASK)

#define XRDC_PDAC_W1_0_29_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_29_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_29_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_29_LK2_SHIFT)) & XRDC_PDAC_W1_0_29_LK2_MASK)

#define XRDC_PDAC_W1_0_29_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_29_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_29_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_29_VLD_SHIFT)) & XRDC_PDAC_W1_0_29_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_30 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_30_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_30_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_30_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_30_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_30_D0ACP_MASK)

#define XRDC_PDAC_W0_0_30_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_30_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_30_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_30_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_30_D1ACP_MASK)

#define XRDC_PDAC_W0_0_30_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_30_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_30_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_30_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_30_D2ACP_MASK)

#define XRDC_PDAC_W0_0_30_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_30_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_30_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_30_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_30_D3ACP_MASK)

#define XRDC_PDAC_W0_0_30_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_30_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_30_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_30_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_30_D4ACP_MASK)

#define XRDC_PDAC_W0_0_30_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_30_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_30_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_30_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_30_D5ACP_MASK)

#define XRDC_PDAC_W0_0_30_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_30_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_30_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_30_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_30_D6ACP_MASK)

#define XRDC_PDAC_W0_0_30_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_30_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_30_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_30_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_30_D7ACP_MASK)

#define XRDC_PDAC_W0_0_30_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_30_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_30_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_30_EALO_SHIFT)) & XRDC_PDAC_W0_0_30_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_30 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_30_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_30_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_30_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_30_EAL_SHIFT)) & XRDC_PDAC_W1_0_30_EAL_MASK)

#define XRDC_PDAC_W1_0_30_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_30_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_30_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_30_LK2_SHIFT)) & XRDC_PDAC_W1_0_30_LK2_MASK)

#define XRDC_PDAC_W1_0_30_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_30_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_30_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_30_VLD_SHIFT)) & XRDC_PDAC_W1_0_30_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_31 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_31_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_31_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_31_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_31_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_31_D0ACP_MASK)

#define XRDC_PDAC_W0_0_31_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_31_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_31_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_31_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_31_D1ACP_MASK)

#define XRDC_PDAC_W0_0_31_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_31_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_31_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_31_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_31_D2ACP_MASK)

#define XRDC_PDAC_W0_0_31_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_31_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_31_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_31_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_31_D3ACP_MASK)

#define XRDC_PDAC_W0_0_31_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_31_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_31_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_31_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_31_D4ACP_MASK)

#define XRDC_PDAC_W0_0_31_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_31_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_31_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_31_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_31_D5ACP_MASK)

#define XRDC_PDAC_W0_0_31_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_31_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_31_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_31_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_31_D6ACP_MASK)

#define XRDC_PDAC_W0_0_31_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_31_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_31_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_31_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_31_D7ACP_MASK)

#define XRDC_PDAC_W0_0_31_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_31_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_31_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_31_EALO_SHIFT)) & XRDC_PDAC_W0_0_31_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_31 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_31_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_31_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_31_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_31_EAL_SHIFT)) & XRDC_PDAC_W1_0_31_EAL_MASK)

#define XRDC_PDAC_W1_0_31_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_31_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_31_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_31_LK2_SHIFT)) & XRDC_PDAC_W1_0_31_LK2_MASK)

#define XRDC_PDAC_W1_0_31_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_31_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_31_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_31_VLD_SHIFT)) & XRDC_PDAC_W1_0_31_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_32 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_32_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_32_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_32_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_32_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_32_D0ACP_MASK)

#define XRDC_PDAC_W0_0_32_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_32_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_32_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_32_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_32_D1ACP_MASK)

#define XRDC_PDAC_W0_0_32_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_32_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_32_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_32_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_32_D2ACP_MASK)

#define XRDC_PDAC_W0_0_32_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_32_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_32_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_32_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_32_D3ACP_MASK)

#define XRDC_PDAC_W0_0_32_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_32_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_32_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_32_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_32_D4ACP_MASK)

#define XRDC_PDAC_W0_0_32_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_32_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_32_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_32_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_32_D5ACP_MASK)

#define XRDC_PDAC_W0_0_32_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_32_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_32_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_32_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_32_D6ACP_MASK)

#define XRDC_PDAC_W0_0_32_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_32_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_32_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_32_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_32_D7ACP_MASK)

#define XRDC_PDAC_W0_0_32_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_32_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_32_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_32_EALO_SHIFT)) & XRDC_PDAC_W0_0_32_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_32 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_32_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_32_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_32_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_32_EAL_SHIFT)) & XRDC_PDAC_W1_0_32_EAL_MASK)

#define XRDC_PDAC_W1_0_32_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_32_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_32_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_32_LK2_SHIFT)) & XRDC_PDAC_W1_0_32_LK2_MASK)

#define XRDC_PDAC_W1_0_32_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_32_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_32_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_32_VLD_SHIFT)) & XRDC_PDAC_W1_0_32_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_33 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_33_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_33_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_33_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_33_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_33_D0ACP_MASK)

#define XRDC_PDAC_W0_0_33_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_33_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_33_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_33_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_33_D1ACP_MASK)

#define XRDC_PDAC_W0_0_33_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_33_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_33_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_33_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_33_D2ACP_MASK)

#define XRDC_PDAC_W0_0_33_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_33_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_33_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_33_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_33_D3ACP_MASK)

#define XRDC_PDAC_W0_0_33_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_33_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_33_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_33_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_33_D4ACP_MASK)

#define XRDC_PDAC_W0_0_33_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_33_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_33_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_33_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_33_D5ACP_MASK)

#define XRDC_PDAC_W0_0_33_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_33_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_33_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_33_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_33_D6ACP_MASK)

#define XRDC_PDAC_W0_0_33_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_33_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_33_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_33_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_33_D7ACP_MASK)

#define XRDC_PDAC_W0_0_33_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_33_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_33_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_33_EALO_SHIFT)) & XRDC_PDAC_W0_0_33_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_33 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_33_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_33_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_33_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_33_EAL_SHIFT)) & XRDC_PDAC_W1_0_33_EAL_MASK)

#define XRDC_PDAC_W1_0_33_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_33_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_33_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_33_LK2_SHIFT)) & XRDC_PDAC_W1_0_33_LK2_MASK)

#define XRDC_PDAC_W1_0_33_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_33_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_33_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_33_VLD_SHIFT)) & XRDC_PDAC_W1_0_33_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_34 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_34_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_34_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_34_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_34_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_34_D0ACP_MASK)

#define XRDC_PDAC_W0_0_34_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_34_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_34_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_34_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_34_D1ACP_MASK)

#define XRDC_PDAC_W0_0_34_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_34_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_34_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_34_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_34_D2ACP_MASK)

#define XRDC_PDAC_W0_0_34_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_34_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_34_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_34_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_34_D3ACP_MASK)

#define XRDC_PDAC_W0_0_34_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_34_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_34_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_34_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_34_D4ACP_MASK)

#define XRDC_PDAC_W0_0_34_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_34_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_34_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_34_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_34_D5ACP_MASK)

#define XRDC_PDAC_W0_0_34_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_34_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_34_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_34_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_34_D6ACP_MASK)

#define XRDC_PDAC_W0_0_34_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_34_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_34_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_34_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_34_D7ACP_MASK)

#define XRDC_PDAC_W0_0_34_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_34_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_34_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_34_EALO_SHIFT)) & XRDC_PDAC_W0_0_34_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_34 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_34_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_34_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_34_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_34_EAL_SHIFT)) & XRDC_PDAC_W1_0_34_EAL_MASK)

#define XRDC_PDAC_W1_0_34_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_34_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_34_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_34_LK2_SHIFT)) & XRDC_PDAC_W1_0_34_LK2_MASK)

#define XRDC_PDAC_W1_0_34_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_34_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_34_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_34_VLD_SHIFT)) & XRDC_PDAC_W1_0_34_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_35 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_35_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_35_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_35_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_35_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_35_D0ACP_MASK)

#define XRDC_PDAC_W0_0_35_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_35_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_35_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_35_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_35_D1ACP_MASK)

#define XRDC_PDAC_W0_0_35_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_35_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_35_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_35_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_35_D2ACP_MASK)

#define XRDC_PDAC_W0_0_35_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_35_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_35_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_35_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_35_D3ACP_MASK)

#define XRDC_PDAC_W0_0_35_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_35_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_35_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_35_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_35_D4ACP_MASK)

#define XRDC_PDAC_W0_0_35_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_35_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_35_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_35_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_35_D5ACP_MASK)

#define XRDC_PDAC_W0_0_35_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_35_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_35_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_35_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_35_D6ACP_MASK)

#define XRDC_PDAC_W0_0_35_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_35_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_35_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_35_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_35_D7ACP_MASK)

#define XRDC_PDAC_W0_0_35_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_35_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_35_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_35_EALO_SHIFT)) & XRDC_PDAC_W0_0_35_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_35 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_35_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_35_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_35_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_35_EAL_SHIFT)) & XRDC_PDAC_W1_0_35_EAL_MASK)

#define XRDC_PDAC_W1_0_35_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_35_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_35_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_35_LK2_SHIFT)) & XRDC_PDAC_W1_0_35_LK2_MASK)

#define XRDC_PDAC_W1_0_35_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_35_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_35_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_35_VLD_SHIFT)) & XRDC_PDAC_W1_0_35_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_36 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_36_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_36_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_36_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_36_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_36_D0ACP_MASK)

#define XRDC_PDAC_W0_0_36_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_36_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_36_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_36_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_36_D1ACP_MASK)

#define XRDC_PDAC_W0_0_36_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_36_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_36_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_36_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_36_D2ACP_MASK)

#define XRDC_PDAC_W0_0_36_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_36_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_36_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_36_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_36_D3ACP_MASK)

#define XRDC_PDAC_W0_0_36_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_36_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_36_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_36_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_36_D4ACP_MASK)

#define XRDC_PDAC_W0_0_36_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_36_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_36_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_36_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_36_D5ACP_MASK)

#define XRDC_PDAC_W0_0_36_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_36_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_36_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_36_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_36_D6ACP_MASK)

#define XRDC_PDAC_W0_0_36_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_36_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_36_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_36_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_36_D7ACP_MASK)

#define XRDC_PDAC_W0_0_36_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_36_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_36_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_36_EALO_SHIFT)) & XRDC_PDAC_W0_0_36_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_36 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_36_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_36_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_36_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_36_EAL_SHIFT)) & XRDC_PDAC_W1_0_36_EAL_MASK)

#define XRDC_PDAC_W1_0_36_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_36_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_36_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_36_LK2_SHIFT)) & XRDC_PDAC_W1_0_36_LK2_MASK)

#define XRDC_PDAC_W1_0_36_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_36_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_36_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_36_VLD_SHIFT)) & XRDC_PDAC_W1_0_36_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_37 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_37_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_37_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_37_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_37_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_37_D0ACP_MASK)

#define XRDC_PDAC_W0_0_37_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_37_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_37_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_37_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_37_D1ACP_MASK)

#define XRDC_PDAC_W0_0_37_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_37_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_37_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_37_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_37_D2ACP_MASK)

#define XRDC_PDAC_W0_0_37_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_37_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_37_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_37_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_37_D3ACP_MASK)

#define XRDC_PDAC_W0_0_37_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_37_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_37_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_37_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_37_D4ACP_MASK)

#define XRDC_PDAC_W0_0_37_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_37_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_37_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_37_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_37_D5ACP_MASK)

#define XRDC_PDAC_W0_0_37_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_37_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_37_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_37_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_37_D6ACP_MASK)

#define XRDC_PDAC_W0_0_37_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_37_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_37_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_37_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_37_D7ACP_MASK)

#define XRDC_PDAC_W0_0_37_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_37_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_37_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_37_EALO_SHIFT)) & XRDC_PDAC_W0_0_37_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_37 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_37_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_37_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_37_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_37_EAL_SHIFT)) & XRDC_PDAC_W1_0_37_EAL_MASK)

#define XRDC_PDAC_W1_0_37_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_37_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_37_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_37_LK2_SHIFT)) & XRDC_PDAC_W1_0_37_LK2_MASK)

#define XRDC_PDAC_W1_0_37_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_37_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_37_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_37_VLD_SHIFT)) & XRDC_PDAC_W1_0_37_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_38 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_38_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_38_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_38_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_38_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_38_D0ACP_MASK)

#define XRDC_PDAC_W0_0_38_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_38_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_38_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_38_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_38_D1ACP_MASK)

#define XRDC_PDAC_W0_0_38_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_38_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_38_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_38_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_38_D2ACP_MASK)

#define XRDC_PDAC_W0_0_38_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_38_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_38_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_38_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_38_D3ACP_MASK)

#define XRDC_PDAC_W0_0_38_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_38_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_38_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_38_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_38_D4ACP_MASK)

#define XRDC_PDAC_W0_0_38_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_38_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_38_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_38_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_38_D5ACP_MASK)

#define XRDC_PDAC_W0_0_38_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_38_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_38_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_38_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_38_D6ACP_MASK)

#define XRDC_PDAC_W0_0_38_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_38_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_38_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_38_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_38_D7ACP_MASK)

#define XRDC_PDAC_W0_0_38_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_38_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_38_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_38_EALO_SHIFT)) & XRDC_PDAC_W0_0_38_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_38 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_38_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_38_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_38_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_38_EAL_SHIFT)) & XRDC_PDAC_W1_0_38_EAL_MASK)

#define XRDC_PDAC_W1_0_38_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_38_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_38_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_38_LK2_SHIFT)) & XRDC_PDAC_W1_0_38_LK2_MASK)

#define XRDC_PDAC_W1_0_38_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_38_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_38_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_38_VLD_SHIFT)) & XRDC_PDAC_W1_0_38_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_39 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_39_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_39_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_39_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_39_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_39_D0ACP_MASK)

#define XRDC_PDAC_W0_0_39_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_39_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_39_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_39_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_39_D1ACP_MASK)

#define XRDC_PDAC_W0_0_39_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_39_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_39_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_39_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_39_D2ACP_MASK)

#define XRDC_PDAC_W0_0_39_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_39_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_39_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_39_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_39_D3ACP_MASK)

#define XRDC_PDAC_W0_0_39_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_39_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_39_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_39_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_39_D4ACP_MASK)

#define XRDC_PDAC_W0_0_39_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_39_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_39_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_39_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_39_D5ACP_MASK)

#define XRDC_PDAC_W0_0_39_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_39_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_39_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_39_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_39_D6ACP_MASK)

#define XRDC_PDAC_W0_0_39_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_39_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_39_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_39_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_39_D7ACP_MASK)

#define XRDC_PDAC_W0_0_39_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_39_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_39_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_39_EALO_SHIFT)) & XRDC_PDAC_W0_0_39_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_39 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_39_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_39_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_39_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_39_EAL_SHIFT)) & XRDC_PDAC_W1_0_39_EAL_MASK)

#define XRDC_PDAC_W1_0_39_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_39_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_39_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_39_LK2_SHIFT)) & XRDC_PDAC_W1_0_39_LK2_MASK)

#define XRDC_PDAC_W1_0_39_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_39_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_39_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_39_VLD_SHIFT)) & XRDC_PDAC_W1_0_39_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_40 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_40_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_40_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_40_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_40_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_40_D0ACP_MASK)

#define XRDC_PDAC_W0_0_40_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_40_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_40_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_40_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_40_D1ACP_MASK)

#define XRDC_PDAC_W0_0_40_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_40_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_40_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_40_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_40_D2ACP_MASK)

#define XRDC_PDAC_W0_0_40_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_40_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_40_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_40_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_40_D3ACP_MASK)

#define XRDC_PDAC_W0_0_40_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_40_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_40_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_40_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_40_D4ACP_MASK)

#define XRDC_PDAC_W0_0_40_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_40_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_40_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_40_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_40_D5ACP_MASK)

#define XRDC_PDAC_W0_0_40_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_40_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_40_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_40_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_40_D6ACP_MASK)

#define XRDC_PDAC_W0_0_40_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_40_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_40_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_40_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_40_D7ACP_MASK)

#define XRDC_PDAC_W0_0_40_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_40_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_40_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_40_EALO_SHIFT)) & XRDC_PDAC_W0_0_40_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_40 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_40_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_40_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_40_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_40_EAL_SHIFT)) & XRDC_PDAC_W1_0_40_EAL_MASK)

#define XRDC_PDAC_W1_0_40_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_40_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_40_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_40_LK2_SHIFT)) & XRDC_PDAC_W1_0_40_LK2_MASK)

#define XRDC_PDAC_W1_0_40_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_40_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_40_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_40_VLD_SHIFT)) & XRDC_PDAC_W1_0_40_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_41 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_41_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_41_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_41_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_41_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_41_D0ACP_MASK)

#define XRDC_PDAC_W0_0_41_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_41_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_41_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_41_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_41_D1ACP_MASK)

#define XRDC_PDAC_W0_0_41_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_41_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_41_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_41_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_41_D2ACP_MASK)

#define XRDC_PDAC_W0_0_41_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_41_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_41_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_41_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_41_D3ACP_MASK)

#define XRDC_PDAC_W0_0_41_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_41_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_41_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_41_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_41_D4ACP_MASK)

#define XRDC_PDAC_W0_0_41_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_41_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_41_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_41_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_41_D5ACP_MASK)

#define XRDC_PDAC_W0_0_41_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_41_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_41_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_41_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_41_D6ACP_MASK)

#define XRDC_PDAC_W0_0_41_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_41_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_41_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_41_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_41_D7ACP_MASK)

#define XRDC_PDAC_W0_0_41_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_41_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_41_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_41_EALO_SHIFT)) & XRDC_PDAC_W0_0_41_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_41 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_41_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_41_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_41_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_41_EAL_SHIFT)) & XRDC_PDAC_W1_0_41_EAL_MASK)

#define XRDC_PDAC_W1_0_41_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_41_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_41_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_41_LK2_SHIFT)) & XRDC_PDAC_W1_0_41_LK2_MASK)

#define XRDC_PDAC_W1_0_41_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_41_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_41_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_41_VLD_SHIFT)) & XRDC_PDAC_W1_0_41_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_42 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_42_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_42_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_42_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_42_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_42_D0ACP_MASK)

#define XRDC_PDAC_W0_0_42_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_42_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_42_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_42_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_42_D1ACP_MASK)

#define XRDC_PDAC_W0_0_42_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_42_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_42_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_42_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_42_D2ACP_MASK)

#define XRDC_PDAC_W0_0_42_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_42_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_42_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_42_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_42_D3ACP_MASK)

#define XRDC_PDAC_W0_0_42_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_42_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_42_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_42_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_42_D4ACP_MASK)

#define XRDC_PDAC_W0_0_42_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_42_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_42_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_42_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_42_D5ACP_MASK)

#define XRDC_PDAC_W0_0_42_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_42_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_42_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_42_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_42_D6ACP_MASK)

#define XRDC_PDAC_W0_0_42_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_42_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_42_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_42_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_42_D7ACP_MASK)

#define XRDC_PDAC_W0_0_42_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_42_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_42_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_42_EALO_SHIFT)) & XRDC_PDAC_W0_0_42_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_42 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_42_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_42_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_42_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_42_EAL_SHIFT)) & XRDC_PDAC_W1_0_42_EAL_MASK)

#define XRDC_PDAC_W1_0_42_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_42_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_42_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_42_LK2_SHIFT)) & XRDC_PDAC_W1_0_42_LK2_MASK)

#define XRDC_PDAC_W1_0_42_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_42_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_42_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_42_VLD_SHIFT)) & XRDC_PDAC_W1_0_42_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_43 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_43_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_43_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_43_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_43_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_43_D0ACP_MASK)

#define XRDC_PDAC_W0_0_43_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_43_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_43_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_43_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_43_D1ACP_MASK)

#define XRDC_PDAC_W0_0_43_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_43_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_43_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_43_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_43_D2ACP_MASK)

#define XRDC_PDAC_W0_0_43_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_43_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_43_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_43_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_43_D3ACP_MASK)

#define XRDC_PDAC_W0_0_43_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_43_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_43_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_43_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_43_D4ACP_MASK)

#define XRDC_PDAC_W0_0_43_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_43_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_43_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_43_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_43_D5ACP_MASK)

#define XRDC_PDAC_W0_0_43_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_43_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_43_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_43_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_43_D6ACP_MASK)

#define XRDC_PDAC_W0_0_43_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_43_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_43_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_43_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_43_D7ACP_MASK)

#define XRDC_PDAC_W0_0_43_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_43_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_43_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_43_EALO_SHIFT)) & XRDC_PDAC_W0_0_43_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_43 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_43_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_43_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_43_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_43_EAL_SHIFT)) & XRDC_PDAC_W1_0_43_EAL_MASK)

#define XRDC_PDAC_W1_0_43_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_43_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_43_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_43_LK2_SHIFT)) & XRDC_PDAC_W1_0_43_LK2_MASK)

#define XRDC_PDAC_W1_0_43_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_43_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_43_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_43_VLD_SHIFT)) & XRDC_PDAC_W1_0_43_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_44 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_44_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_44_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_44_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_44_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_44_D0ACP_MASK)

#define XRDC_PDAC_W0_0_44_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_44_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_44_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_44_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_44_D1ACP_MASK)

#define XRDC_PDAC_W0_0_44_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_44_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_44_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_44_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_44_D2ACP_MASK)

#define XRDC_PDAC_W0_0_44_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_44_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_44_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_44_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_44_D3ACP_MASK)

#define XRDC_PDAC_W0_0_44_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_44_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_44_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_44_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_44_D4ACP_MASK)

#define XRDC_PDAC_W0_0_44_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_44_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_44_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_44_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_44_D5ACP_MASK)

#define XRDC_PDAC_W0_0_44_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_44_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_44_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_44_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_44_D6ACP_MASK)

#define XRDC_PDAC_W0_0_44_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_44_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_44_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_44_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_44_D7ACP_MASK)

#define XRDC_PDAC_W0_0_44_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_44_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_44_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_44_EALO_SHIFT)) & XRDC_PDAC_W0_0_44_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_44 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_44_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_44_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_44_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_44_EAL_SHIFT)) & XRDC_PDAC_W1_0_44_EAL_MASK)

#define XRDC_PDAC_W1_0_44_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_44_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_44_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_44_LK2_SHIFT)) & XRDC_PDAC_W1_0_44_LK2_MASK)

#define XRDC_PDAC_W1_0_44_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_44_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_44_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_44_VLD_SHIFT)) & XRDC_PDAC_W1_0_44_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_45 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_45_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_45_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_45_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_45_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_45_D0ACP_MASK)

#define XRDC_PDAC_W0_0_45_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_45_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_45_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_45_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_45_D1ACP_MASK)

#define XRDC_PDAC_W0_0_45_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_45_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_45_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_45_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_45_D2ACP_MASK)

#define XRDC_PDAC_W0_0_45_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_45_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_45_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_45_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_45_D3ACP_MASK)

#define XRDC_PDAC_W0_0_45_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_45_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_45_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_45_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_45_D4ACP_MASK)

#define XRDC_PDAC_W0_0_45_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_45_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_45_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_45_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_45_D5ACP_MASK)

#define XRDC_PDAC_W0_0_45_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_45_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_45_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_45_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_45_D6ACP_MASK)

#define XRDC_PDAC_W0_0_45_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_45_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_45_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_45_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_45_D7ACP_MASK)

#define XRDC_PDAC_W0_0_45_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_45_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_45_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_45_EALO_SHIFT)) & XRDC_PDAC_W0_0_45_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_45 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_45_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_45_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_45_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_45_EAL_SHIFT)) & XRDC_PDAC_W1_0_45_EAL_MASK)

#define XRDC_PDAC_W1_0_45_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_45_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_45_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_45_LK2_SHIFT)) & XRDC_PDAC_W1_0_45_LK2_MASK)

#define XRDC_PDAC_W1_0_45_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_45_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_45_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_45_VLD_SHIFT)) & XRDC_PDAC_W1_0_45_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_46 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_46_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_46_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_46_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_46_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_46_D0ACP_MASK)

#define XRDC_PDAC_W0_0_46_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_46_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_46_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_46_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_46_D1ACP_MASK)

#define XRDC_PDAC_W0_0_46_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_46_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_46_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_46_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_46_D2ACP_MASK)

#define XRDC_PDAC_W0_0_46_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_46_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_46_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_46_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_46_D3ACP_MASK)

#define XRDC_PDAC_W0_0_46_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_46_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_46_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_46_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_46_D4ACP_MASK)

#define XRDC_PDAC_W0_0_46_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_46_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_46_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_46_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_46_D5ACP_MASK)

#define XRDC_PDAC_W0_0_46_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_46_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_46_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_46_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_46_D6ACP_MASK)

#define XRDC_PDAC_W0_0_46_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_46_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_46_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_46_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_46_D7ACP_MASK)

#define XRDC_PDAC_W0_0_46_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_46_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_46_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_46_EALO_SHIFT)) & XRDC_PDAC_W0_0_46_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_46 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_46_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_46_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_46_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_46_EAL_SHIFT)) & XRDC_PDAC_W1_0_46_EAL_MASK)

#define XRDC_PDAC_W1_0_46_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_46_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_46_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_46_LK2_SHIFT)) & XRDC_PDAC_W1_0_46_LK2_MASK)

#define XRDC_PDAC_W1_0_46_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_46_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_46_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_46_VLD_SHIFT)) & XRDC_PDAC_W1_0_46_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_47 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_47_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_47_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_47_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_47_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_47_D0ACP_MASK)

#define XRDC_PDAC_W0_0_47_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_47_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_47_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_47_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_47_D1ACP_MASK)

#define XRDC_PDAC_W0_0_47_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_47_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_47_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_47_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_47_D2ACP_MASK)

#define XRDC_PDAC_W0_0_47_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_47_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_47_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_47_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_47_D3ACP_MASK)

#define XRDC_PDAC_W0_0_47_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_47_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_47_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_47_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_47_D4ACP_MASK)

#define XRDC_PDAC_W0_0_47_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_47_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_47_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_47_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_47_D5ACP_MASK)

#define XRDC_PDAC_W0_0_47_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_47_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_47_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_47_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_47_D6ACP_MASK)

#define XRDC_PDAC_W0_0_47_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_47_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_47_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_47_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_47_D7ACP_MASK)

#define XRDC_PDAC_W0_0_47_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_47_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_47_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_47_EALO_SHIFT)) & XRDC_PDAC_W0_0_47_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_47 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_47_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_47_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_47_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_47_EAL_SHIFT)) & XRDC_PDAC_W1_0_47_EAL_MASK)

#define XRDC_PDAC_W1_0_47_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_47_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_47_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_47_LK2_SHIFT)) & XRDC_PDAC_W1_0_47_LK2_MASK)

#define XRDC_PDAC_W1_0_47_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_47_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_47_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_47_VLD_SHIFT)) & XRDC_PDAC_W1_0_47_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_48 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_48_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_48_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_48_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_48_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_48_D0ACP_MASK)

#define XRDC_PDAC_W0_0_48_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_48_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_48_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_48_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_48_D1ACP_MASK)

#define XRDC_PDAC_W0_0_48_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_48_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_48_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_48_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_48_D2ACP_MASK)

#define XRDC_PDAC_W0_0_48_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_48_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_48_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_48_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_48_D3ACP_MASK)

#define XRDC_PDAC_W0_0_48_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_48_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_48_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_48_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_48_D4ACP_MASK)

#define XRDC_PDAC_W0_0_48_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_48_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_48_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_48_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_48_D5ACP_MASK)

#define XRDC_PDAC_W0_0_48_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_48_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_48_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_48_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_48_D6ACP_MASK)

#define XRDC_PDAC_W0_0_48_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_48_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_48_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_48_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_48_D7ACP_MASK)

#define XRDC_PDAC_W0_0_48_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_48_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_48_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_48_EALO_SHIFT)) & XRDC_PDAC_W0_0_48_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_48 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_48_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_48_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_48_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_48_EAL_SHIFT)) & XRDC_PDAC_W1_0_48_EAL_MASK)

#define XRDC_PDAC_W1_0_48_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_48_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_48_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_48_LK2_SHIFT)) & XRDC_PDAC_W1_0_48_LK2_MASK)

#define XRDC_PDAC_W1_0_48_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_48_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_48_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_48_VLD_SHIFT)) & XRDC_PDAC_W1_0_48_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_49 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_49_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_49_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_49_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_49_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_49_D0ACP_MASK)

#define XRDC_PDAC_W0_0_49_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_49_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_49_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_49_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_49_D1ACP_MASK)

#define XRDC_PDAC_W0_0_49_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_49_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_49_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_49_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_49_D2ACP_MASK)

#define XRDC_PDAC_W0_0_49_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_49_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_49_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_49_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_49_D3ACP_MASK)

#define XRDC_PDAC_W0_0_49_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_49_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_49_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_49_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_49_D4ACP_MASK)

#define XRDC_PDAC_W0_0_49_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_49_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_49_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_49_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_49_D5ACP_MASK)

#define XRDC_PDAC_W0_0_49_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_49_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_49_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_49_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_49_D6ACP_MASK)

#define XRDC_PDAC_W0_0_49_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_49_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_49_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_49_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_49_D7ACP_MASK)

#define XRDC_PDAC_W0_0_49_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_49_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_49_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_49_EALO_SHIFT)) & XRDC_PDAC_W0_0_49_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_49 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_49_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_49_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_49_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_49_EAL_SHIFT)) & XRDC_PDAC_W1_0_49_EAL_MASK)

#define XRDC_PDAC_W1_0_49_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_49_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_49_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_49_LK2_SHIFT)) & XRDC_PDAC_W1_0_49_LK2_MASK)

#define XRDC_PDAC_W1_0_49_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_49_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_49_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_49_VLD_SHIFT)) & XRDC_PDAC_W1_0_49_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_50 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_50_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_50_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_50_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_50_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_50_D0ACP_MASK)

#define XRDC_PDAC_W0_0_50_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_50_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_50_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_50_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_50_D1ACP_MASK)

#define XRDC_PDAC_W0_0_50_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_50_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_50_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_50_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_50_D2ACP_MASK)

#define XRDC_PDAC_W0_0_50_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_50_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_50_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_50_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_50_D3ACP_MASK)

#define XRDC_PDAC_W0_0_50_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_50_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_50_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_50_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_50_D4ACP_MASK)

#define XRDC_PDAC_W0_0_50_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_50_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_50_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_50_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_50_D5ACP_MASK)

#define XRDC_PDAC_W0_0_50_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_50_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_50_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_50_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_50_D6ACP_MASK)

#define XRDC_PDAC_W0_0_50_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_50_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_50_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_50_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_50_D7ACP_MASK)

#define XRDC_PDAC_W0_0_50_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_50_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_50_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_50_EALO_SHIFT)) & XRDC_PDAC_W0_0_50_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_50 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_50_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_50_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_50_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_50_EAL_SHIFT)) & XRDC_PDAC_W1_0_50_EAL_MASK)

#define XRDC_PDAC_W1_0_50_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_50_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_50_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_50_LK2_SHIFT)) & XRDC_PDAC_W1_0_50_LK2_MASK)

#define XRDC_PDAC_W1_0_50_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_50_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_50_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_50_VLD_SHIFT)) & XRDC_PDAC_W1_0_50_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_51 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_51_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_51_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_51_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_51_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_51_D0ACP_MASK)

#define XRDC_PDAC_W0_0_51_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_51_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_51_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_51_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_51_D1ACP_MASK)

#define XRDC_PDAC_W0_0_51_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_51_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_51_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_51_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_51_D2ACP_MASK)

#define XRDC_PDAC_W0_0_51_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_51_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_51_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_51_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_51_D3ACP_MASK)

#define XRDC_PDAC_W0_0_51_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_51_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_51_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_51_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_51_D4ACP_MASK)

#define XRDC_PDAC_W0_0_51_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_51_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_51_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_51_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_51_D5ACP_MASK)

#define XRDC_PDAC_W0_0_51_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_51_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_51_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_51_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_51_D6ACP_MASK)

#define XRDC_PDAC_W0_0_51_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_51_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_51_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_51_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_51_D7ACP_MASK)

#define XRDC_PDAC_W0_0_51_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_51_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_51_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_51_EALO_SHIFT)) & XRDC_PDAC_W0_0_51_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_51 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_51_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_51_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_51_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_51_EAL_SHIFT)) & XRDC_PDAC_W1_0_51_EAL_MASK)

#define XRDC_PDAC_W1_0_51_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_51_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_51_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_51_LK2_SHIFT)) & XRDC_PDAC_W1_0_51_LK2_MASK)

#define XRDC_PDAC_W1_0_51_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_51_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_51_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_51_VLD_SHIFT)) & XRDC_PDAC_W1_0_51_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_52 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_52_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_52_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_52_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_52_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_52_D0ACP_MASK)

#define XRDC_PDAC_W0_0_52_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_52_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_52_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_52_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_52_D1ACP_MASK)

#define XRDC_PDAC_W0_0_52_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_52_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_52_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_52_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_52_D2ACP_MASK)

#define XRDC_PDAC_W0_0_52_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_52_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_52_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_52_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_52_D3ACP_MASK)

#define XRDC_PDAC_W0_0_52_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_52_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_52_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_52_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_52_D4ACP_MASK)

#define XRDC_PDAC_W0_0_52_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_52_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_52_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_52_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_52_D5ACP_MASK)

#define XRDC_PDAC_W0_0_52_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_52_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_52_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_52_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_52_D6ACP_MASK)

#define XRDC_PDAC_W0_0_52_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_52_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_52_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_52_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_52_D7ACP_MASK)

#define XRDC_PDAC_W0_0_52_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_52_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_52_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_52_EALO_SHIFT)) & XRDC_PDAC_W0_0_52_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_52 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_52_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_52_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_52_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_52_EAL_SHIFT)) & XRDC_PDAC_W1_0_52_EAL_MASK)

#define XRDC_PDAC_W1_0_52_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_52_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_52_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_52_LK2_SHIFT)) & XRDC_PDAC_W1_0_52_LK2_MASK)

#define XRDC_PDAC_W1_0_52_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_52_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_52_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_52_VLD_SHIFT)) & XRDC_PDAC_W1_0_52_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_53 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_53_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_53_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_53_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_53_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_53_D0ACP_MASK)

#define XRDC_PDAC_W0_0_53_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_53_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_53_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_53_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_53_D1ACP_MASK)

#define XRDC_PDAC_W0_0_53_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_53_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_53_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_53_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_53_D2ACP_MASK)

#define XRDC_PDAC_W0_0_53_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_53_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_53_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_53_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_53_D3ACP_MASK)

#define XRDC_PDAC_W0_0_53_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_53_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_53_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_53_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_53_D4ACP_MASK)

#define XRDC_PDAC_W0_0_53_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_53_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_53_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_53_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_53_D5ACP_MASK)

#define XRDC_PDAC_W0_0_53_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_53_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_53_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_53_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_53_D6ACP_MASK)

#define XRDC_PDAC_W0_0_53_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_53_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_53_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_53_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_53_D7ACP_MASK)

#define XRDC_PDAC_W0_0_53_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_53_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_53_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_53_EALO_SHIFT)) & XRDC_PDAC_W0_0_53_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_53 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_53_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_53_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_53_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_53_EAL_SHIFT)) & XRDC_PDAC_W1_0_53_EAL_MASK)

#define XRDC_PDAC_W1_0_53_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_53_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_53_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_53_LK2_SHIFT)) & XRDC_PDAC_W1_0_53_LK2_MASK)

#define XRDC_PDAC_W1_0_53_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_53_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_53_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_53_VLD_SHIFT)) & XRDC_PDAC_W1_0_53_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_54 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_54_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_54_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_54_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_54_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_54_D0ACP_MASK)

#define XRDC_PDAC_W0_0_54_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_54_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_54_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_54_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_54_D1ACP_MASK)

#define XRDC_PDAC_W0_0_54_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_54_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_54_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_54_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_54_D2ACP_MASK)

#define XRDC_PDAC_W0_0_54_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_54_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_54_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_54_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_54_D3ACP_MASK)

#define XRDC_PDAC_W0_0_54_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_54_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_54_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_54_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_54_D4ACP_MASK)

#define XRDC_PDAC_W0_0_54_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_54_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_54_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_54_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_54_D5ACP_MASK)

#define XRDC_PDAC_W0_0_54_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_54_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_54_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_54_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_54_D6ACP_MASK)

#define XRDC_PDAC_W0_0_54_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_54_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_54_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_54_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_54_D7ACP_MASK)

#define XRDC_PDAC_W0_0_54_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_54_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_54_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_54_EALO_SHIFT)) & XRDC_PDAC_W0_0_54_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_54 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_54_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_54_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_54_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_54_EAL_SHIFT)) & XRDC_PDAC_W1_0_54_EAL_MASK)

#define XRDC_PDAC_W1_0_54_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_54_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_54_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_54_LK2_SHIFT)) & XRDC_PDAC_W1_0_54_LK2_MASK)

#define XRDC_PDAC_W1_0_54_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_54_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_54_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_54_VLD_SHIFT)) & XRDC_PDAC_W1_0_54_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_55 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_55_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_55_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_55_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_55_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_55_D0ACP_MASK)

#define XRDC_PDAC_W0_0_55_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_55_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_55_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_55_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_55_D1ACP_MASK)

#define XRDC_PDAC_W0_0_55_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_55_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_55_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_55_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_55_D2ACP_MASK)

#define XRDC_PDAC_W0_0_55_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_55_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_55_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_55_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_55_D3ACP_MASK)

#define XRDC_PDAC_W0_0_55_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_55_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_55_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_55_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_55_D4ACP_MASK)

#define XRDC_PDAC_W0_0_55_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_55_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_55_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_55_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_55_D5ACP_MASK)

#define XRDC_PDAC_W0_0_55_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_55_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_55_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_55_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_55_D6ACP_MASK)

#define XRDC_PDAC_W0_0_55_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_55_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_55_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_55_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_55_D7ACP_MASK)

#define XRDC_PDAC_W0_0_55_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_55_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_55_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_55_EALO_SHIFT)) & XRDC_PDAC_W0_0_55_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_55 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_55_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_55_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_55_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_55_EAL_SHIFT)) & XRDC_PDAC_W1_0_55_EAL_MASK)

#define XRDC_PDAC_W1_0_55_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_55_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_55_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_55_LK2_SHIFT)) & XRDC_PDAC_W1_0_55_LK2_MASK)

#define XRDC_PDAC_W1_0_55_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_55_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_55_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_55_VLD_SHIFT)) & XRDC_PDAC_W1_0_55_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_56 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_56_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_56_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_56_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_56_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_56_D0ACP_MASK)

#define XRDC_PDAC_W0_0_56_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_56_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_56_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_56_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_56_D1ACP_MASK)

#define XRDC_PDAC_W0_0_56_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_56_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_56_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_56_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_56_D2ACP_MASK)

#define XRDC_PDAC_W0_0_56_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_56_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_56_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_56_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_56_D3ACP_MASK)

#define XRDC_PDAC_W0_0_56_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_56_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_56_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_56_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_56_D4ACP_MASK)

#define XRDC_PDAC_W0_0_56_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_56_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_56_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_56_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_56_D5ACP_MASK)

#define XRDC_PDAC_W0_0_56_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_56_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_56_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_56_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_56_D6ACP_MASK)

#define XRDC_PDAC_W0_0_56_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_56_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_56_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_56_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_56_D7ACP_MASK)

#define XRDC_PDAC_W0_0_56_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_56_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_56_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_56_EALO_SHIFT)) & XRDC_PDAC_W0_0_56_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_56 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_56_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_56_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_56_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_56_EAL_SHIFT)) & XRDC_PDAC_W1_0_56_EAL_MASK)

#define XRDC_PDAC_W1_0_56_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_56_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_56_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_56_LK2_SHIFT)) & XRDC_PDAC_W1_0_56_LK2_MASK)

#define XRDC_PDAC_W1_0_56_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_56_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_56_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_56_VLD_SHIFT)) & XRDC_PDAC_W1_0_56_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_57 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_57_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_57_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_57_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_57_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_57_D0ACP_MASK)

#define XRDC_PDAC_W0_0_57_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_57_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_57_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_57_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_57_D1ACP_MASK)

#define XRDC_PDAC_W0_0_57_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_57_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_57_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_57_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_57_D2ACP_MASK)

#define XRDC_PDAC_W0_0_57_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_57_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_57_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_57_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_57_D3ACP_MASK)

#define XRDC_PDAC_W0_0_57_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_57_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_57_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_57_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_57_D4ACP_MASK)

#define XRDC_PDAC_W0_0_57_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_57_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_57_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_57_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_57_D5ACP_MASK)

#define XRDC_PDAC_W0_0_57_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_57_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_57_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_57_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_57_D6ACP_MASK)

#define XRDC_PDAC_W0_0_57_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_57_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_57_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_57_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_57_D7ACP_MASK)

#define XRDC_PDAC_W0_0_57_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_57_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_57_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_57_EALO_SHIFT)) & XRDC_PDAC_W0_0_57_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_57 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_57_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_57_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_57_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_57_EAL_SHIFT)) & XRDC_PDAC_W1_0_57_EAL_MASK)

#define XRDC_PDAC_W1_0_57_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_57_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_57_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_57_LK2_SHIFT)) & XRDC_PDAC_W1_0_57_LK2_MASK)

#define XRDC_PDAC_W1_0_57_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_57_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_57_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_57_VLD_SHIFT)) & XRDC_PDAC_W1_0_57_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_58 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_58_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_58_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_58_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_58_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_58_D0ACP_MASK)

#define XRDC_PDAC_W0_0_58_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_58_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_58_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_58_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_58_D1ACP_MASK)

#define XRDC_PDAC_W0_0_58_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_58_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_58_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_58_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_58_D2ACP_MASK)

#define XRDC_PDAC_W0_0_58_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_58_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_58_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_58_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_58_D3ACP_MASK)

#define XRDC_PDAC_W0_0_58_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_58_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_58_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_58_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_58_D4ACP_MASK)

#define XRDC_PDAC_W0_0_58_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_58_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_58_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_58_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_58_D5ACP_MASK)

#define XRDC_PDAC_W0_0_58_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_58_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_58_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_58_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_58_D6ACP_MASK)

#define XRDC_PDAC_W0_0_58_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_58_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_58_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_58_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_58_D7ACP_MASK)

#define XRDC_PDAC_W0_0_58_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_58_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_58_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_58_EALO_SHIFT)) & XRDC_PDAC_W0_0_58_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_58 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_58_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_58_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_58_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_58_EAL_SHIFT)) & XRDC_PDAC_W1_0_58_EAL_MASK)

#define XRDC_PDAC_W1_0_58_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_58_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_58_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_58_LK2_SHIFT)) & XRDC_PDAC_W1_0_58_LK2_MASK)

#define XRDC_PDAC_W1_0_58_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_58_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_58_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_58_VLD_SHIFT)) & XRDC_PDAC_W1_0_58_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_59 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_59_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_59_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_59_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_59_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_59_D0ACP_MASK)

#define XRDC_PDAC_W0_0_59_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_59_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_59_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_59_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_59_D1ACP_MASK)

#define XRDC_PDAC_W0_0_59_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_59_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_59_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_59_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_59_D2ACP_MASK)

#define XRDC_PDAC_W0_0_59_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_59_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_59_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_59_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_59_D3ACP_MASK)

#define XRDC_PDAC_W0_0_59_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_59_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_59_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_59_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_59_D4ACP_MASK)

#define XRDC_PDAC_W0_0_59_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_59_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_59_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_59_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_59_D5ACP_MASK)

#define XRDC_PDAC_W0_0_59_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_59_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_59_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_59_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_59_D6ACP_MASK)

#define XRDC_PDAC_W0_0_59_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_59_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_59_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_59_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_59_D7ACP_MASK)

#define XRDC_PDAC_W0_0_59_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_59_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_59_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_59_EALO_SHIFT)) & XRDC_PDAC_W0_0_59_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_59 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_59_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_59_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_59_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_59_EAL_SHIFT)) & XRDC_PDAC_W1_0_59_EAL_MASK)

#define XRDC_PDAC_W1_0_59_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_59_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_59_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_59_LK2_SHIFT)) & XRDC_PDAC_W1_0_59_LK2_MASK)

#define XRDC_PDAC_W1_0_59_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_59_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_59_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_59_VLD_SHIFT)) & XRDC_PDAC_W1_0_59_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_0_60 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_0_60_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_0_60_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_0_60_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_60_D0ACP_SHIFT)) & XRDC_PDAC_W0_0_60_D0ACP_MASK)

#define XRDC_PDAC_W0_0_60_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_0_60_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_0_60_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_60_D1ACP_SHIFT)) & XRDC_PDAC_W0_0_60_D1ACP_MASK)

#define XRDC_PDAC_W0_0_60_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_0_60_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_0_60_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_60_D2ACP_SHIFT)) & XRDC_PDAC_W0_0_60_D2ACP_MASK)

#define XRDC_PDAC_W0_0_60_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_0_60_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_0_60_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_60_D3ACP_SHIFT)) & XRDC_PDAC_W0_0_60_D3ACP_MASK)

#define XRDC_PDAC_W0_0_60_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_0_60_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_0_60_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_60_D4ACP_SHIFT)) & XRDC_PDAC_W0_0_60_D4ACP_MASK)

#define XRDC_PDAC_W0_0_60_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_0_60_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_0_60_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_60_D5ACP_SHIFT)) & XRDC_PDAC_W0_0_60_D5ACP_MASK)

#define XRDC_PDAC_W0_0_60_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_0_60_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_0_60_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_60_D6ACP_SHIFT)) & XRDC_PDAC_W0_0_60_D6ACP_MASK)

#define XRDC_PDAC_W0_0_60_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_0_60_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_0_60_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_60_D7ACP_SHIFT)) & XRDC_PDAC_W0_0_60_D7ACP_MASK)

#define XRDC_PDAC_W0_0_60_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_0_60_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_0_60_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_0_60_EALO_SHIFT)) & XRDC_PDAC_W0_0_60_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_0_60 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_0_60_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_0_60_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_0_60_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_60_EAL_SHIFT)) & XRDC_PDAC_W1_0_60_EAL_MASK)

#define XRDC_PDAC_W1_0_60_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_0_60_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_0_60_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_60_LK2_SHIFT)) & XRDC_PDAC_W1_0_60_LK2_MASK)

#define XRDC_PDAC_W1_0_60_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_0_60_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_0_60_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_0_60_VLD_SHIFT)) & XRDC_PDAC_W1_0_60_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_0 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_0_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_1_0_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_0_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_0_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_0_D0ACP_MASK)

#define XRDC_PDAC_W0_1_0_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_1_0_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_0_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_0_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_0_D1ACP_MASK)

#define XRDC_PDAC_W0_1_0_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_1_0_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_0_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_0_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_0_D2ACP_MASK)

#define XRDC_PDAC_W0_1_0_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_1_0_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_0_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_0_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_0_D3ACP_MASK)

#define XRDC_PDAC_W0_1_0_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_1_0_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_0_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_0_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_0_D4ACP_MASK)

#define XRDC_PDAC_W0_1_0_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_1_0_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_0_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_0_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_0_D5ACP_MASK)

#define XRDC_PDAC_W0_1_0_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_1_0_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_0_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_0_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_0_D6ACP_MASK)

#define XRDC_PDAC_W0_1_0_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_1_0_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_0_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_0_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_0_D7ACP_MASK)

#define XRDC_PDAC_W0_1_0_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_1_0_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_0_EALO_SHIFT)) & XRDC_PDAC_W0_1_0_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_0 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_0_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_1_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_0_EAL_SHIFT)) & XRDC_PDAC_W1_1_0_EAL_MASK)

#define XRDC_PDAC_W1_1_0_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_1_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_0_LK2_SHIFT)) & XRDC_PDAC_W1_1_0_LK2_MASK)

#define XRDC_PDAC_W1_1_0_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_1_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_0_VLD_SHIFT)) & XRDC_PDAC_W1_1_0_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_1 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_1_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_1_1_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_1_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_1_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_1_D0ACP_MASK)

#define XRDC_PDAC_W0_1_1_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_1_1_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_1_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_1_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_1_D1ACP_MASK)

#define XRDC_PDAC_W0_1_1_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_1_1_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_1_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_1_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_1_D2ACP_MASK)

#define XRDC_PDAC_W0_1_1_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_1_1_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_1_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_1_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_1_D3ACP_MASK)

#define XRDC_PDAC_W0_1_1_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_1_1_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_1_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_1_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_1_D4ACP_MASK)

#define XRDC_PDAC_W0_1_1_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_1_1_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_1_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_1_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_1_D5ACP_MASK)

#define XRDC_PDAC_W0_1_1_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_1_1_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_1_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_1_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_1_D6ACP_MASK)

#define XRDC_PDAC_W0_1_1_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_1_1_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_1_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_1_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_1_D7ACP_MASK)

#define XRDC_PDAC_W0_1_1_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_1_1_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_1_EALO_SHIFT)) & XRDC_PDAC_W0_1_1_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_1 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_1_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_1_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_1_EAL_SHIFT)) & XRDC_PDAC_W1_1_1_EAL_MASK)

#define XRDC_PDAC_W1_1_1_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_1_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_1_LK2_SHIFT)) & XRDC_PDAC_W1_1_1_LK2_MASK)

#define XRDC_PDAC_W1_1_1_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_1_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_1_VLD_SHIFT)) & XRDC_PDAC_W1_1_1_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_2 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_2_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_1_2_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_2_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_2_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_2_D0ACP_MASK)

#define XRDC_PDAC_W0_1_2_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_1_2_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_2_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_2_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_2_D1ACP_MASK)

#define XRDC_PDAC_W0_1_2_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_1_2_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_2_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_2_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_2_D2ACP_MASK)

#define XRDC_PDAC_W0_1_2_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_1_2_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_2_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_2_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_2_D3ACP_MASK)

#define XRDC_PDAC_W0_1_2_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_1_2_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_2_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_2_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_2_D4ACP_MASK)

#define XRDC_PDAC_W0_1_2_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_1_2_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_2_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_2_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_2_D5ACP_MASK)

#define XRDC_PDAC_W0_1_2_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_1_2_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_2_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_2_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_2_D6ACP_MASK)

#define XRDC_PDAC_W0_1_2_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_1_2_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_2_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_2_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_2_D7ACP_MASK)

#define XRDC_PDAC_W0_1_2_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_1_2_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_2_EALO_SHIFT)) & XRDC_PDAC_W0_1_2_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_2 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_2_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_1_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_2_EAL_SHIFT)) & XRDC_PDAC_W1_1_2_EAL_MASK)

#define XRDC_PDAC_W1_1_2_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_1_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_2_LK2_SHIFT)) & XRDC_PDAC_W1_1_2_LK2_MASK)

#define XRDC_PDAC_W1_1_2_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_1_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_2_VLD_SHIFT)) & XRDC_PDAC_W1_1_2_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_3 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_3_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_1_3_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_3_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_3_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_3_D0ACP_MASK)

#define XRDC_PDAC_W0_1_3_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_1_3_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_3_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_3_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_3_D1ACP_MASK)

#define XRDC_PDAC_W0_1_3_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_1_3_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_3_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_3_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_3_D2ACP_MASK)

#define XRDC_PDAC_W0_1_3_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_1_3_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_3_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_3_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_3_D3ACP_MASK)

#define XRDC_PDAC_W0_1_3_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_1_3_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_3_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_3_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_3_D4ACP_MASK)

#define XRDC_PDAC_W0_1_3_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_1_3_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_3_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_3_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_3_D5ACP_MASK)

#define XRDC_PDAC_W0_1_3_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_1_3_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_3_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_3_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_3_D6ACP_MASK)

#define XRDC_PDAC_W0_1_3_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_1_3_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_3_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_3_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_3_D7ACP_MASK)

#define XRDC_PDAC_W0_1_3_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_1_3_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_3_EALO_SHIFT)) & XRDC_PDAC_W0_1_3_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_3 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_3_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_1_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_3_EAL_SHIFT)) & XRDC_PDAC_W1_1_3_EAL_MASK)

#define XRDC_PDAC_W1_1_3_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_1_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_3_LK2_SHIFT)) & XRDC_PDAC_W1_1_3_LK2_MASK)

#define XRDC_PDAC_W1_1_3_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_1_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_3_VLD_SHIFT)) & XRDC_PDAC_W1_1_3_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_4 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_4_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_1_4_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_4_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_4_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_4_D0ACP_MASK)

#define XRDC_PDAC_W0_1_4_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_1_4_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_4_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_4_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_4_D1ACP_MASK)

#define XRDC_PDAC_W0_1_4_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_1_4_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_4_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_4_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_4_D2ACP_MASK)

#define XRDC_PDAC_W0_1_4_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_1_4_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_4_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_4_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_4_D3ACP_MASK)

#define XRDC_PDAC_W0_1_4_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_1_4_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_4_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_4_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_4_D4ACP_MASK)

#define XRDC_PDAC_W0_1_4_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_1_4_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_4_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_4_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_4_D5ACP_MASK)

#define XRDC_PDAC_W0_1_4_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_1_4_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_4_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_4_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_4_D6ACP_MASK)

#define XRDC_PDAC_W0_1_4_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_1_4_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_4_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_4_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_4_D7ACP_MASK)

#define XRDC_PDAC_W0_1_4_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_1_4_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_4_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_4_EALO_SHIFT)) & XRDC_PDAC_W0_1_4_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_4 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_4_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_1_4_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_4_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_4_EAL_SHIFT)) & XRDC_PDAC_W1_1_4_EAL_MASK)

#define XRDC_PDAC_W1_1_4_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_1_4_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_4_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_4_LK2_SHIFT)) & XRDC_PDAC_W1_1_4_LK2_MASK)

#define XRDC_PDAC_W1_1_4_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_1_4_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_4_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_4_VLD_SHIFT)) & XRDC_PDAC_W1_1_4_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_5 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_5_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_1_5_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_5_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_5_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_5_D0ACP_MASK)

#define XRDC_PDAC_W0_1_5_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_1_5_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_5_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_5_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_5_D1ACP_MASK)

#define XRDC_PDAC_W0_1_5_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_1_5_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_5_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_5_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_5_D2ACP_MASK)

#define XRDC_PDAC_W0_1_5_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_1_5_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_5_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_5_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_5_D3ACP_MASK)

#define XRDC_PDAC_W0_1_5_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_1_5_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_5_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_5_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_5_D4ACP_MASK)

#define XRDC_PDAC_W0_1_5_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_1_5_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_5_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_5_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_5_D5ACP_MASK)

#define XRDC_PDAC_W0_1_5_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_1_5_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_5_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_5_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_5_D6ACP_MASK)

#define XRDC_PDAC_W0_1_5_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_1_5_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_5_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_5_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_5_D7ACP_MASK)

#define XRDC_PDAC_W0_1_5_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_1_5_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_5_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_5_EALO_SHIFT)) & XRDC_PDAC_W0_1_5_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_5 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_5_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_1_5_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_5_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_5_EAL_SHIFT)) & XRDC_PDAC_W1_1_5_EAL_MASK)

#define XRDC_PDAC_W1_1_5_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_1_5_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_5_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_5_LK2_SHIFT)) & XRDC_PDAC_W1_1_5_LK2_MASK)

#define XRDC_PDAC_W1_1_5_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_1_5_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_5_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_5_VLD_SHIFT)) & XRDC_PDAC_W1_1_5_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_6 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_6_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_1_6_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_6_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_6_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_6_D0ACP_MASK)

#define XRDC_PDAC_W0_1_6_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_1_6_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_6_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_6_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_6_D1ACP_MASK)

#define XRDC_PDAC_W0_1_6_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_1_6_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_6_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_6_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_6_D2ACP_MASK)

#define XRDC_PDAC_W0_1_6_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_1_6_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_6_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_6_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_6_D3ACP_MASK)

#define XRDC_PDAC_W0_1_6_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_1_6_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_6_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_6_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_6_D4ACP_MASK)

#define XRDC_PDAC_W0_1_6_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_1_6_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_6_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_6_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_6_D5ACP_MASK)

#define XRDC_PDAC_W0_1_6_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_1_6_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_6_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_6_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_6_D6ACP_MASK)

#define XRDC_PDAC_W0_1_6_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_1_6_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_6_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_6_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_6_D7ACP_MASK)

#define XRDC_PDAC_W0_1_6_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_1_6_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_6_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_6_EALO_SHIFT)) & XRDC_PDAC_W0_1_6_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_6 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_6_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_1_6_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_6_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_6_EAL_SHIFT)) & XRDC_PDAC_W1_1_6_EAL_MASK)

#define XRDC_PDAC_W1_1_6_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_1_6_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_6_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_6_LK2_SHIFT)) & XRDC_PDAC_W1_1_6_LK2_MASK)

#define XRDC_PDAC_W1_1_6_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_1_6_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_6_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_6_VLD_SHIFT)) & XRDC_PDAC_W1_1_6_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_7 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_7_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_1_7_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_7_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_7_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_7_D0ACP_MASK)

#define XRDC_PDAC_W0_1_7_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_1_7_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_7_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_7_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_7_D1ACP_MASK)

#define XRDC_PDAC_W0_1_7_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_1_7_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_7_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_7_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_7_D2ACP_MASK)

#define XRDC_PDAC_W0_1_7_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_1_7_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_7_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_7_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_7_D3ACP_MASK)

#define XRDC_PDAC_W0_1_7_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_1_7_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_7_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_7_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_7_D4ACP_MASK)

#define XRDC_PDAC_W0_1_7_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_1_7_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_7_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_7_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_7_D5ACP_MASK)

#define XRDC_PDAC_W0_1_7_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_1_7_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_7_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_7_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_7_D6ACP_MASK)

#define XRDC_PDAC_W0_1_7_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_1_7_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_7_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_7_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_7_D7ACP_MASK)

#define XRDC_PDAC_W0_1_7_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_1_7_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_7_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_7_EALO_SHIFT)) & XRDC_PDAC_W0_1_7_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_7 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_7_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_1_7_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_7_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_7_EAL_SHIFT)) & XRDC_PDAC_W1_1_7_EAL_MASK)

#define XRDC_PDAC_W1_1_7_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_1_7_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_7_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_7_LK2_SHIFT)) & XRDC_PDAC_W1_1_7_LK2_MASK)

#define XRDC_PDAC_W1_1_7_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_1_7_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_7_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_7_VLD_SHIFT)) & XRDC_PDAC_W1_1_7_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_8 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_8_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_1_8_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_8_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_8_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_8_D0ACP_MASK)

#define XRDC_PDAC_W0_1_8_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_1_8_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_8_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_8_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_8_D1ACP_MASK)

#define XRDC_PDAC_W0_1_8_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_1_8_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_8_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_8_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_8_D2ACP_MASK)

#define XRDC_PDAC_W0_1_8_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_1_8_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_8_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_8_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_8_D3ACP_MASK)

#define XRDC_PDAC_W0_1_8_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_1_8_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_8_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_8_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_8_D4ACP_MASK)

#define XRDC_PDAC_W0_1_8_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_1_8_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_8_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_8_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_8_D5ACP_MASK)

#define XRDC_PDAC_W0_1_8_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_1_8_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_8_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_8_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_8_D6ACP_MASK)

#define XRDC_PDAC_W0_1_8_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_1_8_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_8_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_8_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_8_D7ACP_MASK)

#define XRDC_PDAC_W0_1_8_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_1_8_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_8_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_8_EALO_SHIFT)) & XRDC_PDAC_W0_1_8_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_8 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_8_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_1_8_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_8_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_8_EAL_SHIFT)) & XRDC_PDAC_W1_1_8_EAL_MASK)

#define XRDC_PDAC_W1_1_8_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_1_8_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_8_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_8_LK2_SHIFT)) & XRDC_PDAC_W1_1_8_LK2_MASK)

#define XRDC_PDAC_W1_1_8_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_1_8_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_8_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_8_VLD_SHIFT)) & XRDC_PDAC_W1_1_8_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_9 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_9_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_1_9_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_9_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_9_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_9_D0ACP_MASK)

#define XRDC_PDAC_W0_1_9_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_1_9_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_9_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_9_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_9_D1ACP_MASK)

#define XRDC_PDAC_W0_1_9_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_1_9_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_9_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_9_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_9_D2ACP_MASK)

#define XRDC_PDAC_W0_1_9_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_1_9_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_9_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_9_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_9_D3ACP_MASK)

#define XRDC_PDAC_W0_1_9_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_1_9_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_9_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_9_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_9_D4ACP_MASK)

#define XRDC_PDAC_W0_1_9_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_1_9_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_9_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_9_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_9_D5ACP_MASK)

#define XRDC_PDAC_W0_1_9_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_1_9_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_9_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_9_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_9_D6ACP_MASK)

#define XRDC_PDAC_W0_1_9_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_1_9_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_9_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_9_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_9_D7ACP_MASK)

#define XRDC_PDAC_W0_1_9_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_1_9_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_9_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_9_EALO_SHIFT)) & XRDC_PDAC_W0_1_9_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_9 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_9_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_1_9_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_9_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_9_EAL_SHIFT)) & XRDC_PDAC_W1_1_9_EAL_MASK)

#define XRDC_PDAC_W1_1_9_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_1_9_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_9_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_9_LK2_SHIFT)) & XRDC_PDAC_W1_1_9_LK2_MASK)

#define XRDC_PDAC_W1_1_9_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_1_9_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_9_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_9_VLD_SHIFT)) & XRDC_PDAC_W1_1_9_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_10 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_10_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_1_10_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_10_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_10_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_10_D0ACP_MASK)

#define XRDC_PDAC_W0_1_10_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_1_10_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_10_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_10_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_10_D1ACP_MASK)

#define XRDC_PDAC_W0_1_10_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_1_10_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_10_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_10_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_10_D2ACP_MASK)

#define XRDC_PDAC_W0_1_10_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_1_10_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_10_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_10_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_10_D3ACP_MASK)

#define XRDC_PDAC_W0_1_10_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_1_10_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_10_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_10_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_10_D4ACP_MASK)

#define XRDC_PDAC_W0_1_10_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_1_10_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_10_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_10_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_10_D5ACP_MASK)

#define XRDC_PDAC_W0_1_10_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_1_10_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_10_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_10_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_10_D6ACP_MASK)

#define XRDC_PDAC_W0_1_10_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_1_10_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_10_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_10_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_10_D7ACP_MASK)

#define XRDC_PDAC_W0_1_10_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_1_10_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_10_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_10_EALO_SHIFT)) & XRDC_PDAC_W0_1_10_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_10 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_10_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_1_10_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_10_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_10_EAL_SHIFT)) & XRDC_PDAC_W1_1_10_EAL_MASK)

#define XRDC_PDAC_W1_1_10_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_1_10_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_10_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_10_LK2_SHIFT)) & XRDC_PDAC_W1_1_10_LK2_MASK)

#define XRDC_PDAC_W1_1_10_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_1_10_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_10_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_10_VLD_SHIFT)) & XRDC_PDAC_W1_1_10_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_11 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_11_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_1_11_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_11_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_11_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_11_D0ACP_MASK)

#define XRDC_PDAC_W0_1_11_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_1_11_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_11_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_11_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_11_D1ACP_MASK)

#define XRDC_PDAC_W0_1_11_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_1_11_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_11_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_11_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_11_D2ACP_MASK)

#define XRDC_PDAC_W0_1_11_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_1_11_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_11_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_11_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_11_D3ACP_MASK)

#define XRDC_PDAC_W0_1_11_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_1_11_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_11_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_11_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_11_D4ACP_MASK)

#define XRDC_PDAC_W0_1_11_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_1_11_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_11_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_11_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_11_D5ACP_MASK)

#define XRDC_PDAC_W0_1_11_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_1_11_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_11_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_11_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_11_D6ACP_MASK)

#define XRDC_PDAC_W0_1_11_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_1_11_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_11_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_11_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_11_D7ACP_MASK)

#define XRDC_PDAC_W0_1_11_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_1_11_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_11_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_11_EALO_SHIFT)) & XRDC_PDAC_W0_1_11_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_11 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_11_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_1_11_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_11_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_11_EAL_SHIFT)) & XRDC_PDAC_W1_1_11_EAL_MASK)

#define XRDC_PDAC_W1_1_11_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_1_11_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_11_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_11_LK2_SHIFT)) & XRDC_PDAC_W1_1_11_LK2_MASK)

#define XRDC_PDAC_W1_1_11_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_1_11_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_11_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_11_VLD_SHIFT)) & XRDC_PDAC_W1_1_11_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_12 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_12_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_1_12_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_12_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_12_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_12_D0ACP_MASK)

#define XRDC_PDAC_W0_1_12_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_1_12_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_12_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_12_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_12_D1ACP_MASK)

#define XRDC_PDAC_W0_1_12_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_1_12_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_12_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_12_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_12_D2ACP_MASK)

#define XRDC_PDAC_W0_1_12_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_1_12_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_12_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_12_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_12_D3ACP_MASK)

#define XRDC_PDAC_W0_1_12_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_1_12_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_12_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_12_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_12_D4ACP_MASK)

#define XRDC_PDAC_W0_1_12_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_1_12_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_12_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_12_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_12_D5ACP_MASK)

#define XRDC_PDAC_W0_1_12_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_1_12_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_12_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_12_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_12_D6ACP_MASK)

#define XRDC_PDAC_W0_1_12_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_1_12_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_12_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_12_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_12_D7ACP_MASK)

#define XRDC_PDAC_W0_1_12_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_1_12_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_12_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_12_EALO_SHIFT)) & XRDC_PDAC_W0_1_12_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_12 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_12_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_1_12_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_12_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_12_EAL_SHIFT)) & XRDC_PDAC_W1_1_12_EAL_MASK)

#define XRDC_PDAC_W1_1_12_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_1_12_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_12_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_12_LK2_SHIFT)) & XRDC_PDAC_W1_1_12_LK2_MASK)

#define XRDC_PDAC_W1_1_12_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_1_12_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_12_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_12_VLD_SHIFT)) & XRDC_PDAC_W1_1_12_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_13 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_13_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_1_13_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_13_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_13_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_13_D0ACP_MASK)

#define XRDC_PDAC_W0_1_13_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_1_13_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_13_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_13_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_13_D1ACP_MASK)

#define XRDC_PDAC_W0_1_13_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_1_13_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_13_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_13_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_13_D2ACP_MASK)

#define XRDC_PDAC_W0_1_13_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_1_13_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_13_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_13_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_13_D3ACP_MASK)

#define XRDC_PDAC_W0_1_13_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_1_13_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_13_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_13_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_13_D4ACP_MASK)

#define XRDC_PDAC_W0_1_13_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_1_13_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_13_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_13_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_13_D5ACP_MASK)

#define XRDC_PDAC_W0_1_13_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_1_13_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_13_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_13_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_13_D6ACP_MASK)

#define XRDC_PDAC_W0_1_13_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_1_13_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_13_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_13_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_13_D7ACP_MASK)

#define XRDC_PDAC_W0_1_13_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_1_13_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_13_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_13_EALO_SHIFT)) & XRDC_PDAC_W0_1_13_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_13 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_13_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_1_13_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_13_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_13_EAL_SHIFT)) & XRDC_PDAC_W1_1_13_EAL_MASK)

#define XRDC_PDAC_W1_1_13_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_1_13_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_13_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_13_LK2_SHIFT)) & XRDC_PDAC_W1_1_13_LK2_MASK)

#define XRDC_PDAC_W1_1_13_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_1_13_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_13_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_13_VLD_SHIFT)) & XRDC_PDAC_W1_1_13_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_14 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_14_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_1_14_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_14_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_14_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_14_D0ACP_MASK)

#define XRDC_PDAC_W0_1_14_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_1_14_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_14_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_14_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_14_D1ACP_MASK)

#define XRDC_PDAC_W0_1_14_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_1_14_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_14_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_14_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_14_D2ACP_MASK)

#define XRDC_PDAC_W0_1_14_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_1_14_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_14_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_14_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_14_D3ACP_MASK)

#define XRDC_PDAC_W0_1_14_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_1_14_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_14_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_14_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_14_D4ACP_MASK)

#define XRDC_PDAC_W0_1_14_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_1_14_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_14_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_14_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_14_D5ACP_MASK)

#define XRDC_PDAC_W0_1_14_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_1_14_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_14_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_14_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_14_D6ACP_MASK)

#define XRDC_PDAC_W0_1_14_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_1_14_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_14_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_14_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_14_D7ACP_MASK)

#define XRDC_PDAC_W0_1_14_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_1_14_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_14_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_14_EALO_SHIFT)) & XRDC_PDAC_W0_1_14_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_14 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_14_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_1_14_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_14_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_14_EAL_SHIFT)) & XRDC_PDAC_W1_1_14_EAL_MASK)

#define XRDC_PDAC_W1_1_14_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_1_14_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_14_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_14_LK2_SHIFT)) & XRDC_PDAC_W1_1_14_LK2_MASK)

#define XRDC_PDAC_W1_1_14_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_1_14_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_14_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_14_VLD_SHIFT)) & XRDC_PDAC_W1_1_14_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_15 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_15_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_1_15_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_15_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_15_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_15_D0ACP_MASK)

#define XRDC_PDAC_W0_1_15_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_1_15_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_15_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_15_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_15_D1ACP_MASK)

#define XRDC_PDAC_W0_1_15_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_1_15_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_15_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_15_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_15_D2ACP_MASK)

#define XRDC_PDAC_W0_1_15_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_1_15_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_15_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_15_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_15_D3ACP_MASK)

#define XRDC_PDAC_W0_1_15_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_1_15_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_15_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_15_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_15_D4ACP_MASK)

#define XRDC_PDAC_W0_1_15_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_1_15_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_15_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_15_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_15_D5ACP_MASK)

#define XRDC_PDAC_W0_1_15_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_1_15_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_15_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_15_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_15_D6ACP_MASK)

#define XRDC_PDAC_W0_1_15_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_1_15_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_15_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_15_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_15_D7ACP_MASK)

#define XRDC_PDAC_W0_1_15_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_1_15_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_15_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_15_EALO_SHIFT)) & XRDC_PDAC_W0_1_15_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_15 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_15_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_1_15_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_15_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_15_EAL_SHIFT)) & XRDC_PDAC_W1_1_15_EAL_MASK)

#define XRDC_PDAC_W1_1_15_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_1_15_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_15_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_15_LK2_SHIFT)) & XRDC_PDAC_W1_1_15_LK2_MASK)

#define XRDC_PDAC_W1_1_15_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_1_15_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_15_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_15_VLD_SHIFT)) & XRDC_PDAC_W1_1_15_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_16 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_16_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_1_16_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_16_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_16_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_16_D0ACP_MASK)

#define XRDC_PDAC_W0_1_16_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_1_16_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_16_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_16_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_16_D1ACP_MASK)

#define XRDC_PDAC_W0_1_16_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_1_16_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_16_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_16_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_16_D2ACP_MASK)

#define XRDC_PDAC_W0_1_16_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_1_16_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_16_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_16_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_16_D3ACP_MASK)

#define XRDC_PDAC_W0_1_16_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_1_16_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_16_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_16_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_16_D4ACP_MASK)

#define XRDC_PDAC_W0_1_16_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_1_16_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_16_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_16_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_16_D5ACP_MASK)

#define XRDC_PDAC_W0_1_16_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_1_16_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_16_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_16_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_16_D6ACP_MASK)

#define XRDC_PDAC_W0_1_16_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_1_16_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_16_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_16_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_16_D7ACP_MASK)

#define XRDC_PDAC_W0_1_16_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_1_16_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_16_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_16_EALO_SHIFT)) & XRDC_PDAC_W0_1_16_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_16 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_16_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_1_16_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_16_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_16_EAL_SHIFT)) & XRDC_PDAC_W1_1_16_EAL_MASK)

#define XRDC_PDAC_W1_1_16_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_1_16_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_16_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_16_LK2_SHIFT)) & XRDC_PDAC_W1_1_16_LK2_MASK)

#define XRDC_PDAC_W1_1_16_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_1_16_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_16_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_16_VLD_SHIFT)) & XRDC_PDAC_W1_1_16_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_17 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_17_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_1_17_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_17_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_17_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_17_D0ACP_MASK)

#define XRDC_PDAC_W0_1_17_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_1_17_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_17_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_17_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_17_D1ACP_MASK)

#define XRDC_PDAC_W0_1_17_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_1_17_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_17_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_17_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_17_D2ACP_MASK)

#define XRDC_PDAC_W0_1_17_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_1_17_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_17_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_17_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_17_D3ACP_MASK)

#define XRDC_PDAC_W0_1_17_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_1_17_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_17_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_17_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_17_D4ACP_MASK)

#define XRDC_PDAC_W0_1_17_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_1_17_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_17_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_17_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_17_D5ACP_MASK)

#define XRDC_PDAC_W0_1_17_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_1_17_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_17_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_17_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_17_D6ACP_MASK)

#define XRDC_PDAC_W0_1_17_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_1_17_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_17_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_17_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_17_D7ACP_MASK)

#define XRDC_PDAC_W0_1_17_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_1_17_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_17_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_17_EALO_SHIFT)) & XRDC_PDAC_W0_1_17_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_17 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_17_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_1_17_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_17_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_17_EAL_SHIFT)) & XRDC_PDAC_W1_1_17_EAL_MASK)

#define XRDC_PDAC_W1_1_17_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_1_17_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_17_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_17_LK2_SHIFT)) & XRDC_PDAC_W1_1_17_LK2_MASK)

#define XRDC_PDAC_W1_1_17_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_1_17_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_17_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_17_VLD_SHIFT)) & XRDC_PDAC_W1_1_17_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_18 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_18_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_1_18_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_18_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_18_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_18_D0ACP_MASK)

#define XRDC_PDAC_W0_1_18_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_1_18_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_18_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_18_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_18_D1ACP_MASK)

#define XRDC_PDAC_W0_1_18_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_1_18_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_18_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_18_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_18_D2ACP_MASK)

#define XRDC_PDAC_W0_1_18_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_1_18_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_18_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_18_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_18_D3ACP_MASK)

#define XRDC_PDAC_W0_1_18_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_1_18_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_18_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_18_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_18_D4ACP_MASK)

#define XRDC_PDAC_W0_1_18_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_1_18_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_18_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_18_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_18_D5ACP_MASK)

#define XRDC_PDAC_W0_1_18_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_1_18_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_18_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_18_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_18_D6ACP_MASK)

#define XRDC_PDAC_W0_1_18_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_1_18_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_18_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_18_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_18_D7ACP_MASK)

#define XRDC_PDAC_W0_1_18_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_1_18_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_18_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_18_EALO_SHIFT)) & XRDC_PDAC_W0_1_18_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_18 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_18_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_1_18_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_18_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_18_EAL_SHIFT)) & XRDC_PDAC_W1_1_18_EAL_MASK)

#define XRDC_PDAC_W1_1_18_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_1_18_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_18_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_18_LK2_SHIFT)) & XRDC_PDAC_W1_1_18_LK2_MASK)

#define XRDC_PDAC_W1_1_18_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_1_18_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_18_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_18_VLD_SHIFT)) & XRDC_PDAC_W1_1_18_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_19 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_19_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_1_19_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_19_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_19_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_19_D0ACP_MASK)

#define XRDC_PDAC_W0_1_19_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_1_19_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_19_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_19_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_19_D1ACP_MASK)

#define XRDC_PDAC_W0_1_19_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_1_19_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_19_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_19_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_19_D2ACP_MASK)

#define XRDC_PDAC_W0_1_19_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_1_19_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_19_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_19_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_19_D3ACP_MASK)

#define XRDC_PDAC_W0_1_19_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_1_19_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_19_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_19_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_19_D4ACP_MASK)

#define XRDC_PDAC_W0_1_19_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_1_19_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_19_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_19_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_19_D5ACP_MASK)

#define XRDC_PDAC_W0_1_19_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_1_19_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_19_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_19_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_19_D6ACP_MASK)

#define XRDC_PDAC_W0_1_19_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_1_19_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_19_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_19_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_19_D7ACP_MASK)

#define XRDC_PDAC_W0_1_19_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_1_19_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_19_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_19_EALO_SHIFT)) & XRDC_PDAC_W0_1_19_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_19 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_19_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_1_19_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_19_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_19_EAL_SHIFT)) & XRDC_PDAC_W1_1_19_EAL_MASK)

#define XRDC_PDAC_W1_1_19_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_1_19_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_19_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_19_LK2_SHIFT)) & XRDC_PDAC_W1_1_19_LK2_MASK)

#define XRDC_PDAC_W1_1_19_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_1_19_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_19_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_19_VLD_SHIFT)) & XRDC_PDAC_W1_1_19_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_20 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_20_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_1_20_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_20_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_20_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_20_D0ACP_MASK)

#define XRDC_PDAC_W0_1_20_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_1_20_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_20_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_20_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_20_D1ACP_MASK)

#define XRDC_PDAC_W0_1_20_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_1_20_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_20_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_20_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_20_D2ACP_MASK)

#define XRDC_PDAC_W0_1_20_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_1_20_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_20_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_20_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_20_D3ACP_MASK)

#define XRDC_PDAC_W0_1_20_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_1_20_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_20_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_20_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_20_D4ACP_MASK)

#define XRDC_PDAC_W0_1_20_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_1_20_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_20_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_20_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_20_D5ACP_MASK)

#define XRDC_PDAC_W0_1_20_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_1_20_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_20_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_20_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_20_D6ACP_MASK)

#define XRDC_PDAC_W0_1_20_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_1_20_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_20_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_20_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_20_D7ACP_MASK)

#define XRDC_PDAC_W0_1_20_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_1_20_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_20_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_20_EALO_SHIFT)) & XRDC_PDAC_W0_1_20_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_20 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_20_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_1_20_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_20_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_20_EAL_SHIFT)) & XRDC_PDAC_W1_1_20_EAL_MASK)

#define XRDC_PDAC_W1_1_20_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_1_20_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_20_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_20_LK2_SHIFT)) & XRDC_PDAC_W1_1_20_LK2_MASK)

#define XRDC_PDAC_W1_1_20_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_1_20_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_20_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_20_VLD_SHIFT)) & XRDC_PDAC_W1_1_20_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_21 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_21_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_1_21_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_21_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_21_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_21_D0ACP_MASK)

#define XRDC_PDAC_W0_1_21_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_1_21_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_21_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_21_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_21_D1ACP_MASK)

#define XRDC_PDAC_W0_1_21_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_1_21_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_21_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_21_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_21_D2ACP_MASK)

#define XRDC_PDAC_W0_1_21_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_1_21_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_21_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_21_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_21_D3ACP_MASK)

#define XRDC_PDAC_W0_1_21_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_1_21_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_21_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_21_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_21_D4ACP_MASK)

#define XRDC_PDAC_W0_1_21_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_1_21_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_21_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_21_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_21_D5ACP_MASK)

#define XRDC_PDAC_W0_1_21_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_1_21_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_21_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_21_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_21_D6ACP_MASK)

#define XRDC_PDAC_W0_1_21_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_1_21_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_21_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_21_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_21_D7ACP_MASK)

#define XRDC_PDAC_W0_1_21_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_1_21_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_21_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_21_EALO_SHIFT)) & XRDC_PDAC_W0_1_21_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_21 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_21_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_1_21_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_21_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_21_EAL_SHIFT)) & XRDC_PDAC_W1_1_21_EAL_MASK)

#define XRDC_PDAC_W1_1_21_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_1_21_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_21_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_21_LK2_SHIFT)) & XRDC_PDAC_W1_1_21_LK2_MASK)

#define XRDC_PDAC_W1_1_21_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_1_21_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_21_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_21_VLD_SHIFT)) & XRDC_PDAC_W1_1_21_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_1_22 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_1_22_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_1_22_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_1_22_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_22_D0ACP_SHIFT)) & XRDC_PDAC_W0_1_22_D0ACP_MASK)

#define XRDC_PDAC_W0_1_22_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_1_22_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_1_22_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_22_D1ACP_SHIFT)) & XRDC_PDAC_W0_1_22_D1ACP_MASK)

#define XRDC_PDAC_W0_1_22_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_1_22_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_1_22_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_22_D2ACP_SHIFT)) & XRDC_PDAC_W0_1_22_D2ACP_MASK)

#define XRDC_PDAC_W0_1_22_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_1_22_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_1_22_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_22_D3ACP_SHIFT)) & XRDC_PDAC_W0_1_22_D3ACP_MASK)

#define XRDC_PDAC_W0_1_22_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_1_22_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_1_22_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_22_D4ACP_SHIFT)) & XRDC_PDAC_W0_1_22_D4ACP_MASK)

#define XRDC_PDAC_W0_1_22_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_1_22_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_1_22_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_22_D5ACP_SHIFT)) & XRDC_PDAC_W0_1_22_D5ACP_MASK)

#define XRDC_PDAC_W0_1_22_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_1_22_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_1_22_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_22_D6ACP_SHIFT)) & XRDC_PDAC_W0_1_22_D6ACP_MASK)

#define XRDC_PDAC_W0_1_22_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_1_22_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_1_22_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_22_D7ACP_SHIFT)) & XRDC_PDAC_W0_1_22_D7ACP_MASK)

#define XRDC_PDAC_W0_1_22_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_1_22_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_1_22_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_1_22_EALO_SHIFT)) & XRDC_PDAC_W0_1_22_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_1_22 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_1_22_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_1_22_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_1_22_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_22_EAL_SHIFT)) & XRDC_PDAC_W1_1_22_EAL_MASK)

#define XRDC_PDAC_W1_1_22_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_1_22_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_1_22_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_22_LK2_SHIFT)) & XRDC_PDAC_W1_1_22_LK2_MASK)

#define XRDC_PDAC_W1_1_22_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_1_22_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_1_22_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_1_22_VLD_SHIFT)) & XRDC_PDAC_W1_1_22_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_0 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_0_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_2_0_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_0_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_0_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_0_D0ACP_MASK)

#define XRDC_PDAC_W0_2_0_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_2_0_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_0_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_0_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_0_D1ACP_MASK)

#define XRDC_PDAC_W0_2_0_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_2_0_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_0_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_0_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_0_D2ACP_MASK)

#define XRDC_PDAC_W0_2_0_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_2_0_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_0_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_0_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_0_D3ACP_MASK)

#define XRDC_PDAC_W0_2_0_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_2_0_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_0_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_0_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_0_D4ACP_MASK)

#define XRDC_PDAC_W0_2_0_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_2_0_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_0_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_0_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_0_D5ACP_MASK)

#define XRDC_PDAC_W0_2_0_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_2_0_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_0_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_0_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_0_D6ACP_MASK)

#define XRDC_PDAC_W0_2_0_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_2_0_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_0_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_0_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_0_D7ACP_MASK)

#define XRDC_PDAC_W0_2_0_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_2_0_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_0_EALO_SHIFT)) & XRDC_PDAC_W0_2_0_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_0 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_0_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_2_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_0_EAL_SHIFT)) & XRDC_PDAC_W1_2_0_EAL_MASK)

#define XRDC_PDAC_W1_2_0_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_2_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_0_LK2_SHIFT)) & XRDC_PDAC_W1_2_0_LK2_MASK)

#define XRDC_PDAC_W1_2_0_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_2_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_0_VLD_SHIFT)) & XRDC_PDAC_W1_2_0_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_1 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_1_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_2_1_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_1_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_1_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_1_D0ACP_MASK)

#define XRDC_PDAC_W0_2_1_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_2_1_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_1_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_1_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_1_D1ACP_MASK)

#define XRDC_PDAC_W0_2_1_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_2_1_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_1_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_1_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_1_D2ACP_MASK)

#define XRDC_PDAC_W0_2_1_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_2_1_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_1_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_1_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_1_D3ACP_MASK)

#define XRDC_PDAC_W0_2_1_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_2_1_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_1_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_1_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_1_D4ACP_MASK)

#define XRDC_PDAC_W0_2_1_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_2_1_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_1_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_1_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_1_D5ACP_MASK)

#define XRDC_PDAC_W0_2_1_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_2_1_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_1_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_1_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_1_D6ACP_MASK)

#define XRDC_PDAC_W0_2_1_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_2_1_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_1_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_1_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_1_D7ACP_MASK)

#define XRDC_PDAC_W0_2_1_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_2_1_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_1_EALO_SHIFT)) & XRDC_PDAC_W0_2_1_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_1 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_1_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_2_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_1_EAL_SHIFT)) & XRDC_PDAC_W1_2_1_EAL_MASK)

#define XRDC_PDAC_W1_2_1_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_2_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_1_LK2_SHIFT)) & XRDC_PDAC_W1_2_1_LK2_MASK)

#define XRDC_PDAC_W1_2_1_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_2_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_1_VLD_SHIFT)) & XRDC_PDAC_W1_2_1_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_2 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_2_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_2_2_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_2_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_2_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_2_D0ACP_MASK)

#define XRDC_PDAC_W0_2_2_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_2_2_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_2_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_2_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_2_D1ACP_MASK)

#define XRDC_PDAC_W0_2_2_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_2_2_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_2_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_2_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_2_D2ACP_MASK)

#define XRDC_PDAC_W0_2_2_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_2_2_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_2_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_2_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_2_D3ACP_MASK)

#define XRDC_PDAC_W0_2_2_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_2_2_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_2_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_2_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_2_D4ACP_MASK)

#define XRDC_PDAC_W0_2_2_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_2_2_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_2_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_2_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_2_D5ACP_MASK)

#define XRDC_PDAC_W0_2_2_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_2_2_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_2_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_2_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_2_D6ACP_MASK)

#define XRDC_PDAC_W0_2_2_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_2_2_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_2_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_2_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_2_D7ACP_MASK)

#define XRDC_PDAC_W0_2_2_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_2_2_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_2_EALO_SHIFT)) & XRDC_PDAC_W0_2_2_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_2 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_2_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_2_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_2_EAL_SHIFT)) & XRDC_PDAC_W1_2_2_EAL_MASK)

#define XRDC_PDAC_W1_2_2_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_2_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_2_LK2_SHIFT)) & XRDC_PDAC_W1_2_2_LK2_MASK)

#define XRDC_PDAC_W1_2_2_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_2_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_2_VLD_SHIFT)) & XRDC_PDAC_W1_2_2_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_3 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_3_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_2_3_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_3_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_3_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_3_D0ACP_MASK)

#define XRDC_PDAC_W0_2_3_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_2_3_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_3_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_3_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_3_D1ACP_MASK)

#define XRDC_PDAC_W0_2_3_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_2_3_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_3_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_3_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_3_D2ACP_MASK)

#define XRDC_PDAC_W0_2_3_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_2_3_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_3_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_3_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_3_D3ACP_MASK)

#define XRDC_PDAC_W0_2_3_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_2_3_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_3_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_3_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_3_D4ACP_MASK)

#define XRDC_PDAC_W0_2_3_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_2_3_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_3_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_3_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_3_D5ACP_MASK)

#define XRDC_PDAC_W0_2_3_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_2_3_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_3_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_3_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_3_D6ACP_MASK)

#define XRDC_PDAC_W0_2_3_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_2_3_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_3_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_3_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_3_D7ACP_MASK)

#define XRDC_PDAC_W0_2_3_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_2_3_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_3_EALO_SHIFT)) & XRDC_PDAC_W0_2_3_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_3 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_3_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_2_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_3_EAL_SHIFT)) & XRDC_PDAC_W1_2_3_EAL_MASK)

#define XRDC_PDAC_W1_2_3_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_2_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_3_LK2_SHIFT)) & XRDC_PDAC_W1_2_3_LK2_MASK)

#define XRDC_PDAC_W1_2_3_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_2_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_3_VLD_SHIFT)) & XRDC_PDAC_W1_2_3_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_4 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_4_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_2_4_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_4_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_4_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_4_D0ACP_MASK)

#define XRDC_PDAC_W0_2_4_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_2_4_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_4_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_4_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_4_D1ACP_MASK)

#define XRDC_PDAC_W0_2_4_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_2_4_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_4_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_4_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_4_D2ACP_MASK)

#define XRDC_PDAC_W0_2_4_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_2_4_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_4_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_4_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_4_D3ACP_MASK)

#define XRDC_PDAC_W0_2_4_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_2_4_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_4_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_4_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_4_D4ACP_MASK)

#define XRDC_PDAC_W0_2_4_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_2_4_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_4_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_4_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_4_D5ACP_MASK)

#define XRDC_PDAC_W0_2_4_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_2_4_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_4_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_4_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_4_D6ACP_MASK)

#define XRDC_PDAC_W0_2_4_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_2_4_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_4_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_4_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_4_D7ACP_MASK)

#define XRDC_PDAC_W0_2_4_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_2_4_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_4_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_4_EALO_SHIFT)) & XRDC_PDAC_W0_2_4_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_4 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_4_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_2_4_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_4_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_4_EAL_SHIFT)) & XRDC_PDAC_W1_2_4_EAL_MASK)

#define XRDC_PDAC_W1_2_4_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_2_4_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_4_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_4_LK2_SHIFT)) & XRDC_PDAC_W1_2_4_LK2_MASK)

#define XRDC_PDAC_W1_2_4_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_2_4_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_4_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_4_VLD_SHIFT)) & XRDC_PDAC_W1_2_4_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_5 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_5_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_2_5_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_5_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_5_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_5_D0ACP_MASK)

#define XRDC_PDAC_W0_2_5_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_2_5_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_5_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_5_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_5_D1ACP_MASK)

#define XRDC_PDAC_W0_2_5_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_2_5_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_5_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_5_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_5_D2ACP_MASK)

#define XRDC_PDAC_W0_2_5_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_2_5_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_5_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_5_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_5_D3ACP_MASK)

#define XRDC_PDAC_W0_2_5_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_2_5_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_5_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_5_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_5_D4ACP_MASK)

#define XRDC_PDAC_W0_2_5_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_2_5_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_5_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_5_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_5_D5ACP_MASK)

#define XRDC_PDAC_W0_2_5_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_2_5_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_5_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_5_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_5_D6ACP_MASK)

#define XRDC_PDAC_W0_2_5_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_2_5_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_5_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_5_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_5_D7ACP_MASK)

#define XRDC_PDAC_W0_2_5_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_2_5_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_5_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_5_EALO_SHIFT)) & XRDC_PDAC_W0_2_5_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_5 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_5_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_2_5_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_5_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_5_EAL_SHIFT)) & XRDC_PDAC_W1_2_5_EAL_MASK)

#define XRDC_PDAC_W1_2_5_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_2_5_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_5_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_5_LK2_SHIFT)) & XRDC_PDAC_W1_2_5_LK2_MASK)

#define XRDC_PDAC_W1_2_5_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_2_5_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_5_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_5_VLD_SHIFT)) & XRDC_PDAC_W1_2_5_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_6 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_6_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_2_6_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_6_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_6_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_6_D0ACP_MASK)

#define XRDC_PDAC_W0_2_6_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_2_6_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_6_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_6_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_6_D1ACP_MASK)

#define XRDC_PDAC_W0_2_6_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_2_6_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_6_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_6_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_6_D2ACP_MASK)

#define XRDC_PDAC_W0_2_6_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_2_6_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_6_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_6_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_6_D3ACP_MASK)

#define XRDC_PDAC_W0_2_6_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_2_6_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_6_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_6_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_6_D4ACP_MASK)

#define XRDC_PDAC_W0_2_6_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_2_6_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_6_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_6_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_6_D5ACP_MASK)

#define XRDC_PDAC_W0_2_6_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_2_6_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_6_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_6_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_6_D6ACP_MASK)

#define XRDC_PDAC_W0_2_6_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_2_6_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_6_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_6_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_6_D7ACP_MASK)

#define XRDC_PDAC_W0_2_6_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_2_6_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_6_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_6_EALO_SHIFT)) & XRDC_PDAC_W0_2_6_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_6 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_6_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_2_6_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_6_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_6_EAL_SHIFT)) & XRDC_PDAC_W1_2_6_EAL_MASK)

#define XRDC_PDAC_W1_2_6_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_2_6_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_6_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_6_LK2_SHIFT)) & XRDC_PDAC_W1_2_6_LK2_MASK)

#define XRDC_PDAC_W1_2_6_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_2_6_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_6_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_6_VLD_SHIFT)) & XRDC_PDAC_W1_2_6_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_7 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_7_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_2_7_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_7_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_7_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_7_D0ACP_MASK)

#define XRDC_PDAC_W0_2_7_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_2_7_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_7_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_7_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_7_D1ACP_MASK)

#define XRDC_PDAC_W0_2_7_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_2_7_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_7_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_7_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_7_D2ACP_MASK)

#define XRDC_PDAC_W0_2_7_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_2_7_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_7_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_7_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_7_D3ACP_MASK)

#define XRDC_PDAC_W0_2_7_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_2_7_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_7_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_7_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_7_D4ACP_MASK)

#define XRDC_PDAC_W0_2_7_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_2_7_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_7_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_7_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_7_D5ACP_MASK)

#define XRDC_PDAC_W0_2_7_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_2_7_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_7_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_7_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_7_D6ACP_MASK)

#define XRDC_PDAC_W0_2_7_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_2_7_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_7_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_7_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_7_D7ACP_MASK)

#define XRDC_PDAC_W0_2_7_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_2_7_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_7_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_7_EALO_SHIFT)) & XRDC_PDAC_W0_2_7_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_7 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_7_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_2_7_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_7_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_7_EAL_SHIFT)) & XRDC_PDAC_W1_2_7_EAL_MASK)

#define XRDC_PDAC_W1_2_7_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_2_7_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_7_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_7_LK2_SHIFT)) & XRDC_PDAC_W1_2_7_LK2_MASK)

#define XRDC_PDAC_W1_2_7_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_2_7_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_7_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_7_VLD_SHIFT)) & XRDC_PDAC_W1_2_7_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_8 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_8_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_2_8_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_8_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_8_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_8_D0ACP_MASK)

#define XRDC_PDAC_W0_2_8_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_2_8_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_8_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_8_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_8_D1ACP_MASK)

#define XRDC_PDAC_W0_2_8_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_2_8_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_8_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_8_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_8_D2ACP_MASK)

#define XRDC_PDAC_W0_2_8_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_2_8_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_8_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_8_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_8_D3ACP_MASK)

#define XRDC_PDAC_W0_2_8_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_2_8_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_8_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_8_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_8_D4ACP_MASK)

#define XRDC_PDAC_W0_2_8_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_2_8_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_8_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_8_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_8_D5ACP_MASK)

#define XRDC_PDAC_W0_2_8_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_2_8_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_8_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_8_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_8_D6ACP_MASK)

#define XRDC_PDAC_W0_2_8_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_2_8_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_8_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_8_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_8_D7ACP_MASK)

#define XRDC_PDAC_W0_2_8_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_2_8_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_8_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_8_EALO_SHIFT)) & XRDC_PDAC_W0_2_8_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_8 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_8_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_2_8_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_8_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_8_EAL_SHIFT)) & XRDC_PDAC_W1_2_8_EAL_MASK)

#define XRDC_PDAC_W1_2_8_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_2_8_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_8_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_8_LK2_SHIFT)) & XRDC_PDAC_W1_2_8_LK2_MASK)

#define XRDC_PDAC_W1_2_8_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_2_8_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_8_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_8_VLD_SHIFT)) & XRDC_PDAC_W1_2_8_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_9 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_9_D0ACP_MASK              (0x7U)
#define XRDC_PDAC_W0_2_9_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_9_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_9_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_9_D0ACP_MASK)

#define XRDC_PDAC_W0_2_9_D1ACP_MASK              (0x38U)
#define XRDC_PDAC_W0_2_9_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_9_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_9_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_9_D1ACP_MASK)

#define XRDC_PDAC_W0_2_9_D2ACP_MASK              (0x1C0U)
#define XRDC_PDAC_W0_2_9_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_9_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_9_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_9_D2ACP_MASK)

#define XRDC_PDAC_W0_2_9_D3ACP_MASK              (0xE00U)
#define XRDC_PDAC_W0_2_9_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_9_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_9_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_9_D3ACP_MASK)

#define XRDC_PDAC_W0_2_9_D4ACP_MASK              (0x7000U)
#define XRDC_PDAC_W0_2_9_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_9_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_9_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_9_D4ACP_MASK)

#define XRDC_PDAC_W0_2_9_D5ACP_MASK              (0x38000U)
#define XRDC_PDAC_W0_2_9_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_9_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_9_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_9_D5ACP_MASK)

#define XRDC_PDAC_W0_2_9_D6ACP_MASK              (0x1C0000U)
#define XRDC_PDAC_W0_2_9_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_9_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_9_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_9_D6ACP_MASK)

#define XRDC_PDAC_W0_2_9_D7ACP_MASK              (0xE00000U)
#define XRDC_PDAC_W0_2_9_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_9_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_9_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_9_D7ACP_MASK)

#define XRDC_PDAC_W0_2_9_EALO_MASK               (0xF000000U)
#define XRDC_PDAC_W0_2_9_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_9_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_9_EALO_SHIFT)) & XRDC_PDAC_W0_2_9_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_9 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_9_EAL_MASK                (0x3000000U)
#define XRDC_PDAC_W1_2_9_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_9_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_9_EAL_SHIFT)) & XRDC_PDAC_W1_2_9_EAL_MASK)

#define XRDC_PDAC_W1_2_9_LK2_MASK                (0x60000000U)
#define XRDC_PDAC_W1_2_9_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_9_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_9_LK2_SHIFT)) & XRDC_PDAC_W1_2_9_LK2_MASK)

#define XRDC_PDAC_W1_2_9_VLD_MASK                (0x80000000U)
#define XRDC_PDAC_W1_2_9_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_9_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_9_VLD_SHIFT)) & XRDC_PDAC_W1_2_9_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_10 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_10_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_10_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_10_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_10_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_10_D0ACP_MASK)

#define XRDC_PDAC_W0_2_10_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_10_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_10_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_10_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_10_D1ACP_MASK)

#define XRDC_PDAC_W0_2_10_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_10_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_10_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_10_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_10_D2ACP_MASK)

#define XRDC_PDAC_W0_2_10_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_10_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_10_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_10_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_10_D3ACP_MASK)

#define XRDC_PDAC_W0_2_10_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_10_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_10_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_10_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_10_D4ACP_MASK)

#define XRDC_PDAC_W0_2_10_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_10_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_10_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_10_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_10_D5ACP_MASK)

#define XRDC_PDAC_W0_2_10_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_10_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_10_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_10_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_10_D6ACP_MASK)

#define XRDC_PDAC_W0_2_10_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_10_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_10_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_10_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_10_D7ACP_MASK)

#define XRDC_PDAC_W0_2_10_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_10_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_10_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_10_EALO_SHIFT)) & XRDC_PDAC_W0_2_10_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_10 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_10_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_10_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_10_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_10_EAL_SHIFT)) & XRDC_PDAC_W1_2_10_EAL_MASK)

#define XRDC_PDAC_W1_2_10_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_10_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_10_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_10_LK2_SHIFT)) & XRDC_PDAC_W1_2_10_LK2_MASK)

#define XRDC_PDAC_W1_2_10_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_10_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_10_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_10_VLD_SHIFT)) & XRDC_PDAC_W1_2_10_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_11 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_11_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_11_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_11_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_11_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_11_D0ACP_MASK)

#define XRDC_PDAC_W0_2_11_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_11_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_11_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_11_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_11_D1ACP_MASK)

#define XRDC_PDAC_W0_2_11_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_11_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_11_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_11_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_11_D2ACP_MASK)

#define XRDC_PDAC_W0_2_11_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_11_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_11_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_11_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_11_D3ACP_MASK)

#define XRDC_PDAC_W0_2_11_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_11_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_11_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_11_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_11_D4ACP_MASK)

#define XRDC_PDAC_W0_2_11_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_11_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_11_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_11_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_11_D5ACP_MASK)

#define XRDC_PDAC_W0_2_11_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_11_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_11_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_11_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_11_D6ACP_MASK)

#define XRDC_PDAC_W0_2_11_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_11_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_11_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_11_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_11_D7ACP_MASK)

#define XRDC_PDAC_W0_2_11_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_11_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_11_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_11_EALO_SHIFT)) & XRDC_PDAC_W0_2_11_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_11 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_11_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_11_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_11_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_11_EAL_SHIFT)) & XRDC_PDAC_W1_2_11_EAL_MASK)

#define XRDC_PDAC_W1_2_11_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_11_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_11_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_11_LK2_SHIFT)) & XRDC_PDAC_W1_2_11_LK2_MASK)

#define XRDC_PDAC_W1_2_11_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_11_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_11_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_11_VLD_SHIFT)) & XRDC_PDAC_W1_2_11_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_12 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_12_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_12_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_12_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_12_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_12_D0ACP_MASK)

#define XRDC_PDAC_W0_2_12_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_12_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_12_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_12_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_12_D1ACP_MASK)

#define XRDC_PDAC_W0_2_12_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_12_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_12_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_12_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_12_D2ACP_MASK)

#define XRDC_PDAC_W0_2_12_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_12_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_12_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_12_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_12_D3ACP_MASK)

#define XRDC_PDAC_W0_2_12_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_12_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_12_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_12_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_12_D4ACP_MASK)

#define XRDC_PDAC_W0_2_12_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_12_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_12_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_12_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_12_D5ACP_MASK)

#define XRDC_PDAC_W0_2_12_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_12_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_12_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_12_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_12_D6ACP_MASK)

#define XRDC_PDAC_W0_2_12_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_12_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_12_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_12_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_12_D7ACP_MASK)

#define XRDC_PDAC_W0_2_12_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_12_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_12_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_12_EALO_SHIFT)) & XRDC_PDAC_W0_2_12_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_12 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_12_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_12_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_12_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_12_EAL_SHIFT)) & XRDC_PDAC_W1_2_12_EAL_MASK)

#define XRDC_PDAC_W1_2_12_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_12_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_12_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_12_LK2_SHIFT)) & XRDC_PDAC_W1_2_12_LK2_MASK)

#define XRDC_PDAC_W1_2_12_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_12_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_12_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_12_VLD_SHIFT)) & XRDC_PDAC_W1_2_12_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_13 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_13_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_13_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_13_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_13_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_13_D0ACP_MASK)

#define XRDC_PDAC_W0_2_13_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_13_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_13_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_13_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_13_D1ACP_MASK)

#define XRDC_PDAC_W0_2_13_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_13_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_13_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_13_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_13_D2ACP_MASK)

#define XRDC_PDAC_W0_2_13_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_13_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_13_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_13_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_13_D3ACP_MASK)

#define XRDC_PDAC_W0_2_13_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_13_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_13_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_13_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_13_D4ACP_MASK)

#define XRDC_PDAC_W0_2_13_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_13_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_13_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_13_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_13_D5ACP_MASK)

#define XRDC_PDAC_W0_2_13_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_13_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_13_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_13_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_13_D6ACP_MASK)

#define XRDC_PDAC_W0_2_13_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_13_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_13_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_13_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_13_D7ACP_MASK)

#define XRDC_PDAC_W0_2_13_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_13_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_13_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_13_EALO_SHIFT)) & XRDC_PDAC_W0_2_13_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_13 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_13_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_13_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_13_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_13_EAL_SHIFT)) & XRDC_PDAC_W1_2_13_EAL_MASK)

#define XRDC_PDAC_W1_2_13_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_13_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_13_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_13_LK2_SHIFT)) & XRDC_PDAC_W1_2_13_LK2_MASK)

#define XRDC_PDAC_W1_2_13_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_13_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_13_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_13_VLD_SHIFT)) & XRDC_PDAC_W1_2_13_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_14 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_14_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_14_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_14_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_14_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_14_D0ACP_MASK)

#define XRDC_PDAC_W0_2_14_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_14_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_14_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_14_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_14_D1ACP_MASK)

#define XRDC_PDAC_W0_2_14_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_14_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_14_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_14_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_14_D2ACP_MASK)

#define XRDC_PDAC_W0_2_14_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_14_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_14_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_14_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_14_D3ACP_MASK)

#define XRDC_PDAC_W0_2_14_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_14_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_14_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_14_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_14_D4ACP_MASK)

#define XRDC_PDAC_W0_2_14_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_14_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_14_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_14_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_14_D5ACP_MASK)

#define XRDC_PDAC_W0_2_14_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_14_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_14_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_14_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_14_D6ACP_MASK)

#define XRDC_PDAC_W0_2_14_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_14_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_14_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_14_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_14_D7ACP_MASK)

#define XRDC_PDAC_W0_2_14_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_14_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_14_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_14_EALO_SHIFT)) & XRDC_PDAC_W0_2_14_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_14 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_14_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_14_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_14_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_14_EAL_SHIFT)) & XRDC_PDAC_W1_2_14_EAL_MASK)

#define XRDC_PDAC_W1_2_14_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_14_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_14_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_14_LK2_SHIFT)) & XRDC_PDAC_W1_2_14_LK2_MASK)

#define XRDC_PDAC_W1_2_14_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_14_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_14_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_14_VLD_SHIFT)) & XRDC_PDAC_W1_2_14_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_15 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_15_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_15_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_15_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_15_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_15_D0ACP_MASK)

#define XRDC_PDAC_W0_2_15_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_15_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_15_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_15_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_15_D1ACP_MASK)

#define XRDC_PDAC_W0_2_15_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_15_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_15_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_15_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_15_D2ACP_MASK)

#define XRDC_PDAC_W0_2_15_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_15_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_15_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_15_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_15_D3ACP_MASK)

#define XRDC_PDAC_W0_2_15_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_15_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_15_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_15_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_15_D4ACP_MASK)

#define XRDC_PDAC_W0_2_15_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_15_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_15_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_15_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_15_D5ACP_MASK)

#define XRDC_PDAC_W0_2_15_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_15_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_15_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_15_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_15_D6ACP_MASK)

#define XRDC_PDAC_W0_2_15_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_15_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_15_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_15_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_15_D7ACP_MASK)

#define XRDC_PDAC_W0_2_15_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_15_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_15_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_15_EALO_SHIFT)) & XRDC_PDAC_W0_2_15_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_15 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_15_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_15_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_15_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_15_EAL_SHIFT)) & XRDC_PDAC_W1_2_15_EAL_MASK)

#define XRDC_PDAC_W1_2_15_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_15_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_15_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_15_LK2_SHIFT)) & XRDC_PDAC_W1_2_15_LK2_MASK)

#define XRDC_PDAC_W1_2_15_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_15_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_15_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_15_VLD_SHIFT)) & XRDC_PDAC_W1_2_15_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_16 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_16_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_16_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_16_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_16_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_16_D0ACP_MASK)

#define XRDC_PDAC_W0_2_16_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_16_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_16_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_16_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_16_D1ACP_MASK)

#define XRDC_PDAC_W0_2_16_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_16_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_16_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_16_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_16_D2ACP_MASK)

#define XRDC_PDAC_W0_2_16_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_16_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_16_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_16_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_16_D3ACP_MASK)

#define XRDC_PDAC_W0_2_16_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_16_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_16_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_16_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_16_D4ACP_MASK)

#define XRDC_PDAC_W0_2_16_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_16_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_16_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_16_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_16_D5ACP_MASK)

#define XRDC_PDAC_W0_2_16_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_16_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_16_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_16_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_16_D6ACP_MASK)

#define XRDC_PDAC_W0_2_16_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_16_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_16_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_16_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_16_D7ACP_MASK)

#define XRDC_PDAC_W0_2_16_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_16_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_16_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_16_EALO_SHIFT)) & XRDC_PDAC_W0_2_16_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_16 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_16_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_16_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_16_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_16_EAL_SHIFT)) & XRDC_PDAC_W1_2_16_EAL_MASK)

#define XRDC_PDAC_W1_2_16_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_16_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_16_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_16_LK2_SHIFT)) & XRDC_PDAC_W1_2_16_LK2_MASK)

#define XRDC_PDAC_W1_2_16_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_16_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_16_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_16_VLD_SHIFT)) & XRDC_PDAC_W1_2_16_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_17 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_17_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_17_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_17_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_17_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_17_D0ACP_MASK)

#define XRDC_PDAC_W0_2_17_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_17_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_17_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_17_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_17_D1ACP_MASK)

#define XRDC_PDAC_W0_2_17_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_17_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_17_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_17_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_17_D2ACP_MASK)

#define XRDC_PDAC_W0_2_17_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_17_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_17_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_17_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_17_D3ACP_MASK)

#define XRDC_PDAC_W0_2_17_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_17_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_17_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_17_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_17_D4ACP_MASK)

#define XRDC_PDAC_W0_2_17_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_17_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_17_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_17_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_17_D5ACP_MASK)

#define XRDC_PDAC_W0_2_17_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_17_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_17_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_17_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_17_D6ACP_MASK)

#define XRDC_PDAC_W0_2_17_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_17_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_17_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_17_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_17_D7ACP_MASK)

#define XRDC_PDAC_W0_2_17_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_17_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_17_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_17_EALO_SHIFT)) & XRDC_PDAC_W0_2_17_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_17 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_17_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_17_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_17_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_17_EAL_SHIFT)) & XRDC_PDAC_W1_2_17_EAL_MASK)

#define XRDC_PDAC_W1_2_17_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_17_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_17_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_17_LK2_SHIFT)) & XRDC_PDAC_W1_2_17_LK2_MASK)

#define XRDC_PDAC_W1_2_17_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_17_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_17_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_17_VLD_SHIFT)) & XRDC_PDAC_W1_2_17_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_18 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_18_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_18_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_18_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_18_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_18_D0ACP_MASK)

#define XRDC_PDAC_W0_2_18_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_18_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_18_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_18_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_18_D1ACP_MASK)

#define XRDC_PDAC_W0_2_18_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_18_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_18_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_18_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_18_D2ACP_MASK)

#define XRDC_PDAC_W0_2_18_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_18_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_18_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_18_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_18_D3ACP_MASK)

#define XRDC_PDAC_W0_2_18_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_18_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_18_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_18_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_18_D4ACP_MASK)

#define XRDC_PDAC_W0_2_18_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_18_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_18_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_18_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_18_D5ACP_MASK)

#define XRDC_PDAC_W0_2_18_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_18_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_18_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_18_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_18_D6ACP_MASK)

#define XRDC_PDAC_W0_2_18_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_18_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_18_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_18_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_18_D7ACP_MASK)

#define XRDC_PDAC_W0_2_18_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_18_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_18_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_18_EALO_SHIFT)) & XRDC_PDAC_W0_2_18_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_18 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_18_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_18_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_18_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_18_EAL_SHIFT)) & XRDC_PDAC_W1_2_18_EAL_MASK)

#define XRDC_PDAC_W1_2_18_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_18_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_18_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_18_LK2_SHIFT)) & XRDC_PDAC_W1_2_18_LK2_MASK)

#define XRDC_PDAC_W1_2_18_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_18_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_18_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_18_VLD_SHIFT)) & XRDC_PDAC_W1_2_18_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_19 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_19_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_19_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_19_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_19_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_19_D0ACP_MASK)

#define XRDC_PDAC_W0_2_19_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_19_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_19_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_19_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_19_D1ACP_MASK)

#define XRDC_PDAC_W0_2_19_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_19_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_19_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_19_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_19_D2ACP_MASK)

#define XRDC_PDAC_W0_2_19_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_19_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_19_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_19_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_19_D3ACP_MASK)

#define XRDC_PDAC_W0_2_19_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_19_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_19_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_19_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_19_D4ACP_MASK)

#define XRDC_PDAC_W0_2_19_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_19_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_19_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_19_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_19_D5ACP_MASK)

#define XRDC_PDAC_W0_2_19_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_19_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_19_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_19_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_19_D6ACP_MASK)

#define XRDC_PDAC_W0_2_19_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_19_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_19_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_19_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_19_D7ACP_MASK)

#define XRDC_PDAC_W0_2_19_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_19_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_19_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_19_EALO_SHIFT)) & XRDC_PDAC_W0_2_19_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_19 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_19_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_19_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_19_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_19_EAL_SHIFT)) & XRDC_PDAC_W1_2_19_EAL_MASK)

#define XRDC_PDAC_W1_2_19_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_19_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_19_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_19_LK2_SHIFT)) & XRDC_PDAC_W1_2_19_LK2_MASK)

#define XRDC_PDAC_W1_2_19_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_19_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_19_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_19_VLD_SHIFT)) & XRDC_PDAC_W1_2_19_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_20 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_20_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_20_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_20_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_20_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_20_D0ACP_MASK)

#define XRDC_PDAC_W0_2_20_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_20_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_20_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_20_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_20_D1ACP_MASK)

#define XRDC_PDAC_W0_2_20_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_20_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_20_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_20_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_20_D2ACP_MASK)

#define XRDC_PDAC_W0_2_20_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_20_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_20_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_20_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_20_D3ACP_MASK)

#define XRDC_PDAC_W0_2_20_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_20_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_20_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_20_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_20_D4ACP_MASK)

#define XRDC_PDAC_W0_2_20_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_20_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_20_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_20_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_20_D5ACP_MASK)

#define XRDC_PDAC_W0_2_20_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_20_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_20_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_20_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_20_D6ACP_MASK)

#define XRDC_PDAC_W0_2_20_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_20_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_20_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_20_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_20_D7ACP_MASK)

#define XRDC_PDAC_W0_2_20_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_20_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_20_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_20_EALO_SHIFT)) & XRDC_PDAC_W0_2_20_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_20 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_20_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_20_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_20_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_20_EAL_SHIFT)) & XRDC_PDAC_W1_2_20_EAL_MASK)

#define XRDC_PDAC_W1_2_20_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_20_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_20_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_20_LK2_SHIFT)) & XRDC_PDAC_W1_2_20_LK2_MASK)

#define XRDC_PDAC_W1_2_20_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_20_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_20_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_20_VLD_SHIFT)) & XRDC_PDAC_W1_2_20_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_21 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_21_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_21_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_21_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_21_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_21_D0ACP_MASK)

#define XRDC_PDAC_W0_2_21_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_21_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_21_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_21_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_21_D1ACP_MASK)

#define XRDC_PDAC_W0_2_21_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_21_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_21_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_21_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_21_D2ACP_MASK)

#define XRDC_PDAC_W0_2_21_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_21_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_21_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_21_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_21_D3ACP_MASK)

#define XRDC_PDAC_W0_2_21_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_21_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_21_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_21_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_21_D4ACP_MASK)

#define XRDC_PDAC_W0_2_21_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_21_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_21_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_21_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_21_D5ACP_MASK)

#define XRDC_PDAC_W0_2_21_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_21_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_21_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_21_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_21_D6ACP_MASK)

#define XRDC_PDAC_W0_2_21_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_21_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_21_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_21_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_21_D7ACP_MASK)

#define XRDC_PDAC_W0_2_21_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_21_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_21_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_21_EALO_SHIFT)) & XRDC_PDAC_W0_2_21_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_21 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_21_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_21_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_21_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_21_EAL_SHIFT)) & XRDC_PDAC_W1_2_21_EAL_MASK)

#define XRDC_PDAC_W1_2_21_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_21_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_21_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_21_LK2_SHIFT)) & XRDC_PDAC_W1_2_21_LK2_MASK)

#define XRDC_PDAC_W1_2_21_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_21_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_21_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_21_VLD_SHIFT)) & XRDC_PDAC_W1_2_21_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_22 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_22_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_22_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_22_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_22_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_22_D0ACP_MASK)

#define XRDC_PDAC_W0_2_22_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_22_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_22_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_22_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_22_D1ACP_MASK)

#define XRDC_PDAC_W0_2_22_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_22_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_22_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_22_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_22_D2ACP_MASK)

#define XRDC_PDAC_W0_2_22_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_22_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_22_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_22_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_22_D3ACP_MASK)

#define XRDC_PDAC_W0_2_22_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_22_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_22_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_22_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_22_D4ACP_MASK)

#define XRDC_PDAC_W0_2_22_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_22_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_22_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_22_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_22_D5ACP_MASK)

#define XRDC_PDAC_W0_2_22_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_22_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_22_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_22_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_22_D6ACP_MASK)

#define XRDC_PDAC_W0_2_22_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_22_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_22_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_22_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_22_D7ACP_MASK)

#define XRDC_PDAC_W0_2_22_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_22_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_22_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_22_EALO_SHIFT)) & XRDC_PDAC_W0_2_22_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_22 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_22_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_22_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_22_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_22_EAL_SHIFT)) & XRDC_PDAC_W1_2_22_EAL_MASK)

#define XRDC_PDAC_W1_2_22_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_22_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_22_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_22_LK2_SHIFT)) & XRDC_PDAC_W1_2_22_LK2_MASK)

#define XRDC_PDAC_W1_2_22_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_22_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_22_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_22_VLD_SHIFT)) & XRDC_PDAC_W1_2_22_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_23 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_23_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_23_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_23_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_23_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_23_D0ACP_MASK)

#define XRDC_PDAC_W0_2_23_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_23_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_23_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_23_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_23_D1ACP_MASK)

#define XRDC_PDAC_W0_2_23_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_23_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_23_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_23_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_23_D2ACP_MASK)

#define XRDC_PDAC_W0_2_23_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_23_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_23_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_23_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_23_D3ACP_MASK)

#define XRDC_PDAC_W0_2_23_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_23_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_23_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_23_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_23_D4ACP_MASK)

#define XRDC_PDAC_W0_2_23_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_23_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_23_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_23_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_23_D5ACP_MASK)

#define XRDC_PDAC_W0_2_23_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_23_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_23_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_23_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_23_D6ACP_MASK)

#define XRDC_PDAC_W0_2_23_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_23_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_23_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_23_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_23_D7ACP_MASK)

#define XRDC_PDAC_W0_2_23_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_23_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_23_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_23_EALO_SHIFT)) & XRDC_PDAC_W0_2_23_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_23 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_23_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_23_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_23_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_23_EAL_SHIFT)) & XRDC_PDAC_W1_2_23_EAL_MASK)

#define XRDC_PDAC_W1_2_23_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_23_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_23_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_23_LK2_SHIFT)) & XRDC_PDAC_W1_2_23_LK2_MASK)

#define XRDC_PDAC_W1_2_23_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_23_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_23_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_23_VLD_SHIFT)) & XRDC_PDAC_W1_2_23_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_24 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_24_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_24_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_24_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_24_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_24_D0ACP_MASK)

#define XRDC_PDAC_W0_2_24_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_24_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_24_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_24_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_24_D1ACP_MASK)

#define XRDC_PDAC_W0_2_24_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_24_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_24_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_24_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_24_D2ACP_MASK)

#define XRDC_PDAC_W0_2_24_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_24_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_24_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_24_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_24_D3ACP_MASK)

#define XRDC_PDAC_W0_2_24_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_24_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_24_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_24_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_24_D4ACP_MASK)

#define XRDC_PDAC_W0_2_24_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_24_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_24_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_24_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_24_D5ACP_MASK)

#define XRDC_PDAC_W0_2_24_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_24_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_24_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_24_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_24_D6ACP_MASK)

#define XRDC_PDAC_W0_2_24_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_24_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_24_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_24_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_24_D7ACP_MASK)

#define XRDC_PDAC_W0_2_24_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_24_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_24_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_24_EALO_SHIFT)) & XRDC_PDAC_W0_2_24_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_24 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_24_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_24_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_24_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_24_EAL_SHIFT)) & XRDC_PDAC_W1_2_24_EAL_MASK)

#define XRDC_PDAC_W1_2_24_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_24_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_24_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_24_LK2_SHIFT)) & XRDC_PDAC_W1_2_24_LK2_MASK)

#define XRDC_PDAC_W1_2_24_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_24_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_24_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_24_VLD_SHIFT)) & XRDC_PDAC_W1_2_24_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_25 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_25_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_25_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_25_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_25_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_25_D0ACP_MASK)

#define XRDC_PDAC_W0_2_25_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_25_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_25_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_25_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_25_D1ACP_MASK)

#define XRDC_PDAC_W0_2_25_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_25_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_25_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_25_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_25_D2ACP_MASK)

#define XRDC_PDAC_W0_2_25_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_25_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_25_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_25_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_25_D3ACP_MASK)

#define XRDC_PDAC_W0_2_25_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_25_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_25_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_25_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_25_D4ACP_MASK)

#define XRDC_PDAC_W0_2_25_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_25_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_25_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_25_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_25_D5ACP_MASK)

#define XRDC_PDAC_W0_2_25_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_25_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_25_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_25_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_25_D6ACP_MASK)

#define XRDC_PDAC_W0_2_25_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_25_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_25_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_25_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_25_D7ACP_MASK)

#define XRDC_PDAC_W0_2_25_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_25_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_25_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_25_EALO_SHIFT)) & XRDC_PDAC_W0_2_25_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_25 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_25_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_25_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_25_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_25_EAL_SHIFT)) & XRDC_PDAC_W1_2_25_EAL_MASK)

#define XRDC_PDAC_W1_2_25_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_25_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_25_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_25_LK2_SHIFT)) & XRDC_PDAC_W1_2_25_LK2_MASK)

#define XRDC_PDAC_W1_2_25_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_25_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_25_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_25_VLD_SHIFT)) & XRDC_PDAC_W1_2_25_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_26 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_26_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_26_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_26_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_26_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_26_D0ACP_MASK)

#define XRDC_PDAC_W0_2_26_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_26_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_26_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_26_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_26_D1ACP_MASK)

#define XRDC_PDAC_W0_2_26_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_26_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_26_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_26_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_26_D2ACP_MASK)

#define XRDC_PDAC_W0_2_26_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_26_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_26_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_26_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_26_D3ACP_MASK)

#define XRDC_PDAC_W0_2_26_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_26_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_26_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_26_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_26_D4ACP_MASK)

#define XRDC_PDAC_W0_2_26_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_26_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_26_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_26_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_26_D5ACP_MASK)

#define XRDC_PDAC_W0_2_26_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_26_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_26_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_26_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_26_D6ACP_MASK)

#define XRDC_PDAC_W0_2_26_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_26_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_26_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_26_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_26_D7ACP_MASK)

#define XRDC_PDAC_W0_2_26_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_26_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_26_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_26_EALO_SHIFT)) & XRDC_PDAC_W0_2_26_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_26 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_26_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_26_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_26_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_26_EAL_SHIFT)) & XRDC_PDAC_W1_2_26_EAL_MASK)

#define XRDC_PDAC_W1_2_26_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_26_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_26_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_26_LK2_SHIFT)) & XRDC_PDAC_W1_2_26_LK2_MASK)

#define XRDC_PDAC_W1_2_26_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_26_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_26_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_26_VLD_SHIFT)) & XRDC_PDAC_W1_2_26_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_27 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_27_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_27_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_27_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_27_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_27_D0ACP_MASK)

#define XRDC_PDAC_W0_2_27_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_27_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_27_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_27_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_27_D1ACP_MASK)

#define XRDC_PDAC_W0_2_27_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_27_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_27_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_27_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_27_D2ACP_MASK)

#define XRDC_PDAC_W0_2_27_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_27_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_27_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_27_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_27_D3ACP_MASK)

#define XRDC_PDAC_W0_2_27_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_27_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_27_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_27_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_27_D4ACP_MASK)

#define XRDC_PDAC_W0_2_27_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_27_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_27_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_27_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_27_D5ACP_MASK)

#define XRDC_PDAC_W0_2_27_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_27_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_27_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_27_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_27_D6ACP_MASK)

#define XRDC_PDAC_W0_2_27_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_27_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_27_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_27_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_27_D7ACP_MASK)

#define XRDC_PDAC_W0_2_27_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_27_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_27_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_27_EALO_SHIFT)) & XRDC_PDAC_W0_2_27_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_27 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_27_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_27_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_27_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_27_EAL_SHIFT)) & XRDC_PDAC_W1_2_27_EAL_MASK)

#define XRDC_PDAC_W1_2_27_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_27_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_27_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_27_LK2_SHIFT)) & XRDC_PDAC_W1_2_27_LK2_MASK)

#define XRDC_PDAC_W1_2_27_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_27_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_27_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_27_VLD_SHIFT)) & XRDC_PDAC_W1_2_27_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_28 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_28_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_28_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_28_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_28_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_28_D0ACP_MASK)

#define XRDC_PDAC_W0_2_28_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_28_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_28_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_28_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_28_D1ACP_MASK)

#define XRDC_PDAC_W0_2_28_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_28_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_28_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_28_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_28_D2ACP_MASK)

#define XRDC_PDAC_W0_2_28_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_28_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_28_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_28_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_28_D3ACP_MASK)

#define XRDC_PDAC_W0_2_28_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_28_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_28_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_28_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_28_D4ACP_MASK)

#define XRDC_PDAC_W0_2_28_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_28_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_28_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_28_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_28_D5ACP_MASK)

#define XRDC_PDAC_W0_2_28_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_28_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_28_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_28_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_28_D6ACP_MASK)

#define XRDC_PDAC_W0_2_28_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_28_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_28_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_28_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_28_D7ACP_MASK)

#define XRDC_PDAC_W0_2_28_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_28_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_28_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_28_EALO_SHIFT)) & XRDC_PDAC_W0_2_28_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_28 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_28_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_28_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_28_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_28_EAL_SHIFT)) & XRDC_PDAC_W1_2_28_EAL_MASK)

#define XRDC_PDAC_W1_2_28_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_28_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_28_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_28_LK2_SHIFT)) & XRDC_PDAC_W1_2_28_LK2_MASK)

#define XRDC_PDAC_W1_2_28_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_28_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_28_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_28_VLD_SHIFT)) & XRDC_PDAC_W1_2_28_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_29 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_29_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_29_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_29_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_29_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_29_D0ACP_MASK)

#define XRDC_PDAC_W0_2_29_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_29_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_29_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_29_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_29_D1ACP_MASK)

#define XRDC_PDAC_W0_2_29_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_29_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_29_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_29_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_29_D2ACP_MASK)

#define XRDC_PDAC_W0_2_29_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_29_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_29_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_29_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_29_D3ACP_MASK)

#define XRDC_PDAC_W0_2_29_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_29_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_29_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_29_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_29_D4ACP_MASK)

#define XRDC_PDAC_W0_2_29_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_29_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_29_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_29_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_29_D5ACP_MASK)

#define XRDC_PDAC_W0_2_29_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_29_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_29_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_29_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_29_D6ACP_MASK)

#define XRDC_PDAC_W0_2_29_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_29_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_29_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_29_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_29_D7ACP_MASK)

#define XRDC_PDAC_W0_2_29_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_29_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_29_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_29_EALO_SHIFT)) & XRDC_PDAC_W0_2_29_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_29 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_29_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_29_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_29_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_29_EAL_SHIFT)) & XRDC_PDAC_W1_2_29_EAL_MASK)

#define XRDC_PDAC_W1_2_29_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_29_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_29_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_29_LK2_SHIFT)) & XRDC_PDAC_W1_2_29_LK2_MASK)

#define XRDC_PDAC_W1_2_29_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_29_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_29_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_29_VLD_SHIFT)) & XRDC_PDAC_W1_2_29_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_30 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_30_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_30_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_30_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_30_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_30_D0ACP_MASK)

#define XRDC_PDAC_W0_2_30_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_30_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_30_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_30_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_30_D1ACP_MASK)

#define XRDC_PDAC_W0_2_30_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_30_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_30_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_30_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_30_D2ACP_MASK)

#define XRDC_PDAC_W0_2_30_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_30_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_30_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_30_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_30_D3ACP_MASK)

#define XRDC_PDAC_W0_2_30_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_30_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_30_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_30_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_30_D4ACP_MASK)

#define XRDC_PDAC_W0_2_30_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_30_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_30_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_30_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_30_D5ACP_MASK)

#define XRDC_PDAC_W0_2_30_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_30_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_30_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_30_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_30_D6ACP_MASK)

#define XRDC_PDAC_W0_2_30_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_30_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_30_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_30_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_30_D7ACP_MASK)

#define XRDC_PDAC_W0_2_30_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_30_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_30_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_30_EALO_SHIFT)) & XRDC_PDAC_W0_2_30_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_30 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_30_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_30_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_30_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_30_EAL_SHIFT)) & XRDC_PDAC_W1_2_30_EAL_MASK)

#define XRDC_PDAC_W1_2_30_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_30_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_30_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_30_LK2_SHIFT)) & XRDC_PDAC_W1_2_30_LK2_MASK)

#define XRDC_PDAC_W1_2_30_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_30_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_30_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_30_VLD_SHIFT)) & XRDC_PDAC_W1_2_30_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_31 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_31_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_31_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_31_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_31_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_31_D0ACP_MASK)

#define XRDC_PDAC_W0_2_31_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_31_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_31_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_31_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_31_D1ACP_MASK)

#define XRDC_PDAC_W0_2_31_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_31_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_31_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_31_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_31_D2ACP_MASK)

#define XRDC_PDAC_W0_2_31_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_31_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_31_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_31_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_31_D3ACP_MASK)

#define XRDC_PDAC_W0_2_31_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_31_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_31_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_31_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_31_D4ACP_MASK)

#define XRDC_PDAC_W0_2_31_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_31_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_31_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_31_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_31_D5ACP_MASK)

#define XRDC_PDAC_W0_2_31_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_31_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_31_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_31_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_31_D6ACP_MASK)

#define XRDC_PDAC_W0_2_31_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_31_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_31_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_31_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_31_D7ACP_MASK)

#define XRDC_PDAC_W0_2_31_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_31_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_31_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_31_EALO_SHIFT)) & XRDC_PDAC_W0_2_31_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_31 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_31_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_31_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_31_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_31_EAL_SHIFT)) & XRDC_PDAC_W1_2_31_EAL_MASK)

#define XRDC_PDAC_W1_2_31_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_31_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_31_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_31_LK2_SHIFT)) & XRDC_PDAC_W1_2_31_LK2_MASK)

#define XRDC_PDAC_W1_2_31_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_31_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_31_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_31_VLD_SHIFT)) & XRDC_PDAC_W1_2_31_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_32 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_32_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_32_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_32_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_32_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_32_D0ACP_MASK)

#define XRDC_PDAC_W0_2_32_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_32_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_32_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_32_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_32_D1ACP_MASK)

#define XRDC_PDAC_W0_2_32_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_32_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_32_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_32_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_32_D2ACP_MASK)

#define XRDC_PDAC_W0_2_32_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_32_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_32_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_32_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_32_D3ACP_MASK)

#define XRDC_PDAC_W0_2_32_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_32_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_32_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_32_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_32_D4ACP_MASK)

#define XRDC_PDAC_W0_2_32_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_32_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_32_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_32_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_32_D5ACP_MASK)

#define XRDC_PDAC_W0_2_32_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_32_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_32_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_32_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_32_D6ACP_MASK)

#define XRDC_PDAC_W0_2_32_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_32_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_32_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_32_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_32_D7ACP_MASK)

#define XRDC_PDAC_W0_2_32_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_32_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_32_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_32_EALO_SHIFT)) & XRDC_PDAC_W0_2_32_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_32 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_32_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_32_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_32_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_32_EAL_SHIFT)) & XRDC_PDAC_W1_2_32_EAL_MASK)

#define XRDC_PDAC_W1_2_32_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_32_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_32_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_32_LK2_SHIFT)) & XRDC_PDAC_W1_2_32_LK2_MASK)

#define XRDC_PDAC_W1_2_32_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_32_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_32_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_32_VLD_SHIFT)) & XRDC_PDAC_W1_2_32_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_33 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_33_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_33_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_33_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_33_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_33_D0ACP_MASK)

#define XRDC_PDAC_W0_2_33_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_33_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_33_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_33_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_33_D1ACP_MASK)

#define XRDC_PDAC_W0_2_33_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_33_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_33_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_33_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_33_D2ACP_MASK)

#define XRDC_PDAC_W0_2_33_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_33_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_33_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_33_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_33_D3ACP_MASK)

#define XRDC_PDAC_W0_2_33_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_33_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_33_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_33_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_33_D4ACP_MASK)

#define XRDC_PDAC_W0_2_33_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_33_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_33_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_33_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_33_D5ACP_MASK)

#define XRDC_PDAC_W0_2_33_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_33_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_33_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_33_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_33_D6ACP_MASK)

#define XRDC_PDAC_W0_2_33_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_33_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_33_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_33_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_33_D7ACP_MASK)

#define XRDC_PDAC_W0_2_33_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_33_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_33_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_33_EALO_SHIFT)) & XRDC_PDAC_W0_2_33_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_33 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_33_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_33_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_33_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_33_EAL_SHIFT)) & XRDC_PDAC_W1_2_33_EAL_MASK)

#define XRDC_PDAC_W1_2_33_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_33_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_33_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_33_LK2_SHIFT)) & XRDC_PDAC_W1_2_33_LK2_MASK)

#define XRDC_PDAC_W1_2_33_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_33_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_33_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_33_VLD_SHIFT)) & XRDC_PDAC_W1_2_33_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_34 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_34_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_34_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_34_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_34_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_34_D0ACP_MASK)

#define XRDC_PDAC_W0_2_34_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_34_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_34_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_34_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_34_D1ACP_MASK)

#define XRDC_PDAC_W0_2_34_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_34_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_34_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_34_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_34_D2ACP_MASK)

#define XRDC_PDAC_W0_2_34_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_34_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_34_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_34_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_34_D3ACP_MASK)

#define XRDC_PDAC_W0_2_34_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_34_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_34_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_34_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_34_D4ACP_MASK)

#define XRDC_PDAC_W0_2_34_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_34_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_34_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_34_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_34_D5ACP_MASK)

#define XRDC_PDAC_W0_2_34_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_34_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_34_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_34_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_34_D6ACP_MASK)

#define XRDC_PDAC_W0_2_34_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_34_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_34_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_34_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_34_D7ACP_MASK)

#define XRDC_PDAC_W0_2_34_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_34_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_34_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_34_EALO_SHIFT)) & XRDC_PDAC_W0_2_34_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_34 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_34_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_34_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_34_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_34_EAL_SHIFT)) & XRDC_PDAC_W1_2_34_EAL_MASK)

#define XRDC_PDAC_W1_2_34_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_34_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_34_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_34_LK2_SHIFT)) & XRDC_PDAC_W1_2_34_LK2_MASK)

#define XRDC_PDAC_W1_2_34_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_34_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_34_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_34_VLD_SHIFT)) & XRDC_PDAC_W1_2_34_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_35 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_35_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_35_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_35_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_35_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_35_D0ACP_MASK)

#define XRDC_PDAC_W0_2_35_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_35_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_35_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_35_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_35_D1ACP_MASK)

#define XRDC_PDAC_W0_2_35_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_35_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_35_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_35_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_35_D2ACP_MASK)

#define XRDC_PDAC_W0_2_35_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_35_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_35_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_35_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_35_D3ACP_MASK)

#define XRDC_PDAC_W0_2_35_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_35_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_35_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_35_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_35_D4ACP_MASK)

#define XRDC_PDAC_W0_2_35_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_35_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_35_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_35_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_35_D5ACP_MASK)

#define XRDC_PDAC_W0_2_35_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_35_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_35_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_35_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_35_D6ACP_MASK)

#define XRDC_PDAC_W0_2_35_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_35_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_35_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_35_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_35_D7ACP_MASK)

#define XRDC_PDAC_W0_2_35_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_35_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_35_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_35_EALO_SHIFT)) & XRDC_PDAC_W0_2_35_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_35 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_35_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_35_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_35_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_35_EAL_SHIFT)) & XRDC_PDAC_W1_2_35_EAL_MASK)

#define XRDC_PDAC_W1_2_35_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_35_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_35_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_35_LK2_SHIFT)) & XRDC_PDAC_W1_2_35_LK2_MASK)

#define XRDC_PDAC_W1_2_35_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_35_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_35_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_35_VLD_SHIFT)) & XRDC_PDAC_W1_2_35_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_36 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_36_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_36_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_36_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_36_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_36_D0ACP_MASK)

#define XRDC_PDAC_W0_2_36_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_36_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_36_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_36_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_36_D1ACP_MASK)

#define XRDC_PDAC_W0_2_36_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_36_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_36_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_36_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_36_D2ACP_MASK)

#define XRDC_PDAC_W0_2_36_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_36_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_36_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_36_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_36_D3ACP_MASK)

#define XRDC_PDAC_W0_2_36_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_36_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_36_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_36_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_36_D4ACP_MASK)

#define XRDC_PDAC_W0_2_36_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_36_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_36_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_36_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_36_D5ACP_MASK)

#define XRDC_PDAC_W0_2_36_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_36_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_36_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_36_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_36_D6ACP_MASK)

#define XRDC_PDAC_W0_2_36_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_36_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_36_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_36_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_36_D7ACP_MASK)

#define XRDC_PDAC_W0_2_36_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_36_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_36_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_36_EALO_SHIFT)) & XRDC_PDAC_W0_2_36_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_36 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_36_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_36_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_36_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_36_EAL_SHIFT)) & XRDC_PDAC_W1_2_36_EAL_MASK)

#define XRDC_PDAC_W1_2_36_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_36_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_36_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_36_LK2_SHIFT)) & XRDC_PDAC_W1_2_36_LK2_MASK)

#define XRDC_PDAC_W1_2_36_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_36_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_36_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_36_VLD_SHIFT)) & XRDC_PDAC_W1_2_36_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_37 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_37_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_37_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_37_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_37_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_37_D0ACP_MASK)

#define XRDC_PDAC_W0_2_37_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_37_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_37_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_37_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_37_D1ACP_MASK)

#define XRDC_PDAC_W0_2_37_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_37_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_37_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_37_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_37_D2ACP_MASK)

#define XRDC_PDAC_W0_2_37_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_37_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_37_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_37_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_37_D3ACP_MASK)

#define XRDC_PDAC_W0_2_37_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_37_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_37_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_37_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_37_D4ACP_MASK)

#define XRDC_PDAC_W0_2_37_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_37_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_37_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_37_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_37_D5ACP_MASK)

#define XRDC_PDAC_W0_2_37_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_37_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_37_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_37_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_37_D6ACP_MASK)

#define XRDC_PDAC_W0_2_37_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_37_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_37_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_37_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_37_D7ACP_MASK)

#define XRDC_PDAC_W0_2_37_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_37_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_37_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_37_EALO_SHIFT)) & XRDC_PDAC_W0_2_37_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_37 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_37_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_37_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_37_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_37_EAL_SHIFT)) & XRDC_PDAC_W1_2_37_EAL_MASK)

#define XRDC_PDAC_W1_2_37_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_37_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_37_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_37_LK2_SHIFT)) & XRDC_PDAC_W1_2_37_LK2_MASK)

#define XRDC_PDAC_W1_2_37_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_37_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_37_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_37_VLD_SHIFT)) & XRDC_PDAC_W1_2_37_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_38 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_38_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_38_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_38_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_38_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_38_D0ACP_MASK)

#define XRDC_PDAC_W0_2_38_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_38_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_38_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_38_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_38_D1ACP_MASK)

#define XRDC_PDAC_W0_2_38_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_38_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_38_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_38_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_38_D2ACP_MASK)

#define XRDC_PDAC_W0_2_38_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_38_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_38_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_38_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_38_D3ACP_MASK)

#define XRDC_PDAC_W0_2_38_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_38_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_38_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_38_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_38_D4ACP_MASK)

#define XRDC_PDAC_W0_2_38_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_38_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_38_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_38_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_38_D5ACP_MASK)

#define XRDC_PDAC_W0_2_38_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_38_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_38_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_38_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_38_D6ACP_MASK)

#define XRDC_PDAC_W0_2_38_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_38_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_38_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_38_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_38_D7ACP_MASK)

#define XRDC_PDAC_W0_2_38_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_38_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_38_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_38_EALO_SHIFT)) & XRDC_PDAC_W0_2_38_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_38 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_38_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_38_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_38_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_38_EAL_SHIFT)) & XRDC_PDAC_W1_2_38_EAL_MASK)

#define XRDC_PDAC_W1_2_38_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_38_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_38_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_38_LK2_SHIFT)) & XRDC_PDAC_W1_2_38_LK2_MASK)

#define XRDC_PDAC_W1_2_38_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_38_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_38_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_38_VLD_SHIFT)) & XRDC_PDAC_W1_2_38_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_39 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_39_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_39_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_39_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_39_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_39_D0ACP_MASK)

#define XRDC_PDAC_W0_2_39_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_39_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_39_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_39_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_39_D1ACP_MASK)

#define XRDC_PDAC_W0_2_39_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_39_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_39_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_39_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_39_D2ACP_MASK)

#define XRDC_PDAC_W0_2_39_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_39_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_39_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_39_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_39_D3ACP_MASK)

#define XRDC_PDAC_W0_2_39_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_39_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_39_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_39_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_39_D4ACP_MASK)

#define XRDC_PDAC_W0_2_39_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_39_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_39_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_39_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_39_D5ACP_MASK)

#define XRDC_PDAC_W0_2_39_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_39_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_39_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_39_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_39_D6ACP_MASK)

#define XRDC_PDAC_W0_2_39_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_39_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_39_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_39_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_39_D7ACP_MASK)

#define XRDC_PDAC_W0_2_39_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_39_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_39_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_39_EALO_SHIFT)) & XRDC_PDAC_W0_2_39_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_39 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_39_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_39_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_39_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_39_EAL_SHIFT)) & XRDC_PDAC_W1_2_39_EAL_MASK)

#define XRDC_PDAC_W1_2_39_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_39_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_39_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_39_LK2_SHIFT)) & XRDC_PDAC_W1_2_39_LK2_MASK)

#define XRDC_PDAC_W1_2_39_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_39_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_39_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_39_VLD_SHIFT)) & XRDC_PDAC_W1_2_39_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_40 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_40_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_40_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_40_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_40_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_40_D0ACP_MASK)

#define XRDC_PDAC_W0_2_40_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_40_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_40_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_40_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_40_D1ACP_MASK)

#define XRDC_PDAC_W0_2_40_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_40_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_40_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_40_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_40_D2ACP_MASK)

#define XRDC_PDAC_W0_2_40_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_40_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_40_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_40_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_40_D3ACP_MASK)

#define XRDC_PDAC_W0_2_40_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_40_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_40_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_40_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_40_D4ACP_MASK)

#define XRDC_PDAC_W0_2_40_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_40_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_40_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_40_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_40_D5ACP_MASK)

#define XRDC_PDAC_W0_2_40_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_40_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_40_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_40_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_40_D6ACP_MASK)

#define XRDC_PDAC_W0_2_40_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_40_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_40_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_40_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_40_D7ACP_MASK)

#define XRDC_PDAC_W0_2_40_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_40_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_40_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_40_EALO_SHIFT)) & XRDC_PDAC_W0_2_40_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_40 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_40_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_40_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_40_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_40_EAL_SHIFT)) & XRDC_PDAC_W1_2_40_EAL_MASK)

#define XRDC_PDAC_W1_2_40_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_40_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_40_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_40_LK2_SHIFT)) & XRDC_PDAC_W1_2_40_LK2_MASK)

#define XRDC_PDAC_W1_2_40_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_40_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_40_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_40_VLD_SHIFT)) & XRDC_PDAC_W1_2_40_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_41 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_41_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_41_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_41_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_41_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_41_D0ACP_MASK)

#define XRDC_PDAC_W0_2_41_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_41_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_41_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_41_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_41_D1ACP_MASK)

#define XRDC_PDAC_W0_2_41_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_41_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_41_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_41_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_41_D2ACP_MASK)

#define XRDC_PDAC_W0_2_41_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_41_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_41_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_41_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_41_D3ACP_MASK)

#define XRDC_PDAC_W0_2_41_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_41_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_41_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_41_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_41_D4ACP_MASK)

#define XRDC_PDAC_W0_2_41_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_41_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_41_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_41_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_41_D5ACP_MASK)

#define XRDC_PDAC_W0_2_41_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_41_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_41_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_41_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_41_D6ACP_MASK)

#define XRDC_PDAC_W0_2_41_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_41_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_41_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_41_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_41_D7ACP_MASK)

#define XRDC_PDAC_W0_2_41_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_41_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_41_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_41_EALO_SHIFT)) & XRDC_PDAC_W0_2_41_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_41 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_41_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_41_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_41_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_41_EAL_SHIFT)) & XRDC_PDAC_W1_2_41_EAL_MASK)

#define XRDC_PDAC_W1_2_41_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_41_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_41_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_41_LK2_SHIFT)) & XRDC_PDAC_W1_2_41_LK2_MASK)

#define XRDC_PDAC_W1_2_41_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_41_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_41_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_41_VLD_SHIFT)) & XRDC_PDAC_W1_2_41_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_42 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_42_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_42_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_42_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_42_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_42_D0ACP_MASK)

#define XRDC_PDAC_W0_2_42_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_42_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_42_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_42_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_42_D1ACP_MASK)

#define XRDC_PDAC_W0_2_42_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_42_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_42_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_42_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_42_D2ACP_MASK)

#define XRDC_PDAC_W0_2_42_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_42_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_42_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_42_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_42_D3ACP_MASK)

#define XRDC_PDAC_W0_2_42_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_42_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_42_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_42_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_42_D4ACP_MASK)

#define XRDC_PDAC_W0_2_42_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_42_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_42_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_42_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_42_D5ACP_MASK)

#define XRDC_PDAC_W0_2_42_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_42_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_42_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_42_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_42_D6ACP_MASK)

#define XRDC_PDAC_W0_2_42_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_42_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_42_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_42_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_42_D7ACP_MASK)

#define XRDC_PDAC_W0_2_42_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_42_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_42_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_42_EALO_SHIFT)) & XRDC_PDAC_W0_2_42_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_42 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_42_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_42_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_42_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_42_EAL_SHIFT)) & XRDC_PDAC_W1_2_42_EAL_MASK)

#define XRDC_PDAC_W1_2_42_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_42_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_42_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_42_LK2_SHIFT)) & XRDC_PDAC_W1_2_42_LK2_MASK)

#define XRDC_PDAC_W1_2_42_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_42_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_42_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_42_VLD_SHIFT)) & XRDC_PDAC_W1_2_42_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_43 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_43_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_43_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_43_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_43_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_43_D0ACP_MASK)

#define XRDC_PDAC_W0_2_43_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_43_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_43_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_43_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_43_D1ACP_MASK)

#define XRDC_PDAC_W0_2_43_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_43_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_43_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_43_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_43_D2ACP_MASK)

#define XRDC_PDAC_W0_2_43_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_43_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_43_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_43_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_43_D3ACP_MASK)

#define XRDC_PDAC_W0_2_43_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_43_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_43_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_43_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_43_D4ACP_MASK)

#define XRDC_PDAC_W0_2_43_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_43_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_43_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_43_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_43_D5ACP_MASK)

#define XRDC_PDAC_W0_2_43_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_43_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_43_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_43_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_43_D6ACP_MASK)

#define XRDC_PDAC_W0_2_43_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_43_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_43_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_43_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_43_D7ACP_MASK)

#define XRDC_PDAC_W0_2_43_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_43_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_43_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_43_EALO_SHIFT)) & XRDC_PDAC_W0_2_43_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_43 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_43_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_43_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_43_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_43_EAL_SHIFT)) & XRDC_PDAC_W1_2_43_EAL_MASK)

#define XRDC_PDAC_W1_2_43_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_43_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_43_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_43_LK2_SHIFT)) & XRDC_PDAC_W1_2_43_LK2_MASK)

#define XRDC_PDAC_W1_2_43_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_43_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_43_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_43_VLD_SHIFT)) & XRDC_PDAC_W1_2_43_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_44 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_44_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_44_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_44_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_44_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_44_D0ACP_MASK)

#define XRDC_PDAC_W0_2_44_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_44_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_44_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_44_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_44_D1ACP_MASK)

#define XRDC_PDAC_W0_2_44_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_44_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_44_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_44_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_44_D2ACP_MASK)

#define XRDC_PDAC_W0_2_44_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_44_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_44_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_44_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_44_D3ACP_MASK)

#define XRDC_PDAC_W0_2_44_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_44_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_44_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_44_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_44_D4ACP_MASK)

#define XRDC_PDAC_W0_2_44_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_44_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_44_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_44_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_44_D5ACP_MASK)

#define XRDC_PDAC_W0_2_44_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_44_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_44_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_44_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_44_D6ACP_MASK)

#define XRDC_PDAC_W0_2_44_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_44_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_44_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_44_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_44_D7ACP_MASK)

#define XRDC_PDAC_W0_2_44_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_44_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_44_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_44_EALO_SHIFT)) & XRDC_PDAC_W0_2_44_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_44 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_44_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_44_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_44_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_44_EAL_SHIFT)) & XRDC_PDAC_W1_2_44_EAL_MASK)

#define XRDC_PDAC_W1_2_44_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_44_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_44_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_44_LK2_SHIFT)) & XRDC_PDAC_W1_2_44_LK2_MASK)

#define XRDC_PDAC_W1_2_44_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_44_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_44_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_44_VLD_SHIFT)) & XRDC_PDAC_W1_2_44_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_45 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_45_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_45_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_45_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_45_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_45_D0ACP_MASK)

#define XRDC_PDAC_W0_2_45_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_45_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_45_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_45_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_45_D1ACP_MASK)

#define XRDC_PDAC_W0_2_45_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_45_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_45_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_45_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_45_D2ACP_MASK)

#define XRDC_PDAC_W0_2_45_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_45_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_45_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_45_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_45_D3ACP_MASK)

#define XRDC_PDAC_W0_2_45_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_45_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_45_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_45_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_45_D4ACP_MASK)

#define XRDC_PDAC_W0_2_45_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_45_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_45_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_45_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_45_D5ACP_MASK)

#define XRDC_PDAC_W0_2_45_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_45_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_45_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_45_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_45_D6ACP_MASK)

#define XRDC_PDAC_W0_2_45_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_45_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_45_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_45_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_45_D7ACP_MASK)

#define XRDC_PDAC_W0_2_45_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_45_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_45_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_45_EALO_SHIFT)) & XRDC_PDAC_W0_2_45_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_45 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_45_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_45_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_45_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_45_EAL_SHIFT)) & XRDC_PDAC_W1_2_45_EAL_MASK)

#define XRDC_PDAC_W1_2_45_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_45_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_45_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_45_LK2_SHIFT)) & XRDC_PDAC_W1_2_45_LK2_MASK)

#define XRDC_PDAC_W1_2_45_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_45_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_45_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_45_VLD_SHIFT)) & XRDC_PDAC_W1_2_45_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_46 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_46_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_46_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_46_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_46_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_46_D0ACP_MASK)

#define XRDC_PDAC_W0_2_46_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_46_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_46_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_46_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_46_D1ACP_MASK)

#define XRDC_PDAC_W0_2_46_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_46_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_46_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_46_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_46_D2ACP_MASK)

#define XRDC_PDAC_W0_2_46_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_46_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_46_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_46_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_46_D3ACP_MASK)

#define XRDC_PDAC_W0_2_46_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_46_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_46_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_46_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_46_D4ACP_MASK)

#define XRDC_PDAC_W0_2_46_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_46_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_46_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_46_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_46_D5ACP_MASK)

#define XRDC_PDAC_W0_2_46_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_46_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_46_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_46_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_46_D6ACP_MASK)

#define XRDC_PDAC_W0_2_46_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_46_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_46_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_46_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_46_D7ACP_MASK)

#define XRDC_PDAC_W0_2_46_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_46_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_46_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_46_EALO_SHIFT)) & XRDC_PDAC_W0_2_46_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_46 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_46_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_46_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_46_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_46_EAL_SHIFT)) & XRDC_PDAC_W1_2_46_EAL_MASK)

#define XRDC_PDAC_W1_2_46_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_46_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_46_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_46_LK2_SHIFT)) & XRDC_PDAC_W1_2_46_LK2_MASK)

#define XRDC_PDAC_W1_2_46_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_46_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_46_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_46_VLD_SHIFT)) & XRDC_PDAC_W1_2_46_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_47 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_47_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_47_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_47_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_47_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_47_D0ACP_MASK)

#define XRDC_PDAC_W0_2_47_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_47_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_47_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_47_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_47_D1ACP_MASK)

#define XRDC_PDAC_W0_2_47_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_47_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_47_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_47_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_47_D2ACP_MASK)

#define XRDC_PDAC_W0_2_47_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_47_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_47_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_47_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_47_D3ACP_MASK)

#define XRDC_PDAC_W0_2_47_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_47_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_47_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_47_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_47_D4ACP_MASK)

#define XRDC_PDAC_W0_2_47_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_47_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_47_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_47_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_47_D5ACP_MASK)

#define XRDC_PDAC_W0_2_47_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_47_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_47_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_47_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_47_D6ACP_MASK)

#define XRDC_PDAC_W0_2_47_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_47_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_47_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_47_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_47_D7ACP_MASK)

#define XRDC_PDAC_W0_2_47_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_47_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_47_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_47_EALO_SHIFT)) & XRDC_PDAC_W0_2_47_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_47 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_47_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_47_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_47_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_47_EAL_SHIFT)) & XRDC_PDAC_W1_2_47_EAL_MASK)

#define XRDC_PDAC_W1_2_47_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_47_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_47_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_47_LK2_SHIFT)) & XRDC_PDAC_W1_2_47_LK2_MASK)

#define XRDC_PDAC_W1_2_47_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_47_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_47_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_47_VLD_SHIFT)) & XRDC_PDAC_W1_2_47_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_48 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_48_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_48_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_48_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_48_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_48_D0ACP_MASK)

#define XRDC_PDAC_W0_2_48_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_48_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_48_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_48_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_48_D1ACP_MASK)

#define XRDC_PDAC_W0_2_48_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_48_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_48_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_48_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_48_D2ACP_MASK)

#define XRDC_PDAC_W0_2_48_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_48_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_48_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_48_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_48_D3ACP_MASK)

#define XRDC_PDAC_W0_2_48_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_48_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_48_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_48_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_48_D4ACP_MASK)

#define XRDC_PDAC_W0_2_48_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_48_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_48_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_48_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_48_D5ACP_MASK)

#define XRDC_PDAC_W0_2_48_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_48_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_48_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_48_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_48_D6ACP_MASK)

#define XRDC_PDAC_W0_2_48_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_48_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_48_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_48_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_48_D7ACP_MASK)

#define XRDC_PDAC_W0_2_48_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_48_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_48_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_48_EALO_SHIFT)) & XRDC_PDAC_W0_2_48_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_48 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_48_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_48_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_48_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_48_EAL_SHIFT)) & XRDC_PDAC_W1_2_48_EAL_MASK)

#define XRDC_PDAC_W1_2_48_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_48_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_48_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_48_LK2_SHIFT)) & XRDC_PDAC_W1_2_48_LK2_MASK)

#define XRDC_PDAC_W1_2_48_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_48_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_48_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_48_VLD_SHIFT)) & XRDC_PDAC_W1_2_48_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_50 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_50_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_50_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_50_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_50_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_50_D0ACP_MASK)

#define XRDC_PDAC_W0_2_50_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_50_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_50_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_50_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_50_D1ACP_MASK)

#define XRDC_PDAC_W0_2_50_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_50_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_50_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_50_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_50_D2ACP_MASK)

#define XRDC_PDAC_W0_2_50_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_50_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_50_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_50_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_50_D3ACP_MASK)

#define XRDC_PDAC_W0_2_50_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_50_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_50_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_50_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_50_D4ACP_MASK)

#define XRDC_PDAC_W0_2_50_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_50_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_50_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_50_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_50_D5ACP_MASK)

#define XRDC_PDAC_W0_2_50_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_50_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_50_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_50_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_50_D6ACP_MASK)

#define XRDC_PDAC_W0_2_50_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_50_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_50_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_50_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_50_D7ACP_MASK)

#define XRDC_PDAC_W0_2_50_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_50_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_50_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_50_EALO_SHIFT)) & XRDC_PDAC_W0_2_50_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_50 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_50_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_50_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_50_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_50_EAL_SHIFT)) & XRDC_PDAC_W1_2_50_EAL_MASK)

#define XRDC_PDAC_W1_2_50_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_50_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_50_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_50_LK2_SHIFT)) & XRDC_PDAC_W1_2_50_LK2_MASK)

#define XRDC_PDAC_W1_2_50_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_50_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_50_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_50_VLD_SHIFT)) & XRDC_PDAC_W1_2_50_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_51 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_51_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_51_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_51_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_51_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_51_D0ACP_MASK)

#define XRDC_PDAC_W0_2_51_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_51_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_51_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_51_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_51_D1ACP_MASK)

#define XRDC_PDAC_W0_2_51_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_51_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_51_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_51_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_51_D2ACP_MASK)

#define XRDC_PDAC_W0_2_51_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_51_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_51_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_51_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_51_D3ACP_MASK)

#define XRDC_PDAC_W0_2_51_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_51_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_51_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_51_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_51_D4ACP_MASK)

#define XRDC_PDAC_W0_2_51_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_51_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_51_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_51_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_51_D5ACP_MASK)

#define XRDC_PDAC_W0_2_51_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_51_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_51_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_51_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_51_D6ACP_MASK)

#define XRDC_PDAC_W0_2_51_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_51_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_51_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_51_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_51_D7ACP_MASK)

#define XRDC_PDAC_W0_2_51_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_51_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_51_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_51_EALO_SHIFT)) & XRDC_PDAC_W0_2_51_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_51 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_51_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_51_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_51_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_51_EAL_SHIFT)) & XRDC_PDAC_W1_2_51_EAL_MASK)

#define XRDC_PDAC_W1_2_51_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_51_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_51_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_51_LK2_SHIFT)) & XRDC_PDAC_W1_2_51_LK2_MASK)

#define XRDC_PDAC_W1_2_51_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_51_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_51_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_51_VLD_SHIFT)) & XRDC_PDAC_W1_2_51_VLD_MASK)
/*! @} */

/*! @name PDAC_W0_2_52 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W0_2_52_D0ACP_MASK             (0x7U)
#define XRDC_PDAC_W0_2_52_D0ACP_SHIFT            (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_PDAC_W0_2_52_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_52_D0ACP_SHIFT)) & XRDC_PDAC_W0_2_52_D0ACP_MASK)

#define XRDC_PDAC_W0_2_52_D1ACP_MASK             (0x38U)
#define XRDC_PDAC_W0_2_52_D1ACP_SHIFT            (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_PDAC_W0_2_52_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_52_D1ACP_SHIFT)) & XRDC_PDAC_W0_2_52_D1ACP_MASK)

#define XRDC_PDAC_W0_2_52_D2ACP_MASK             (0x1C0U)
#define XRDC_PDAC_W0_2_52_D2ACP_SHIFT            (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_PDAC_W0_2_52_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_52_D2ACP_SHIFT)) & XRDC_PDAC_W0_2_52_D2ACP_MASK)

#define XRDC_PDAC_W0_2_52_D3ACP_MASK             (0xE00U)
#define XRDC_PDAC_W0_2_52_D3ACP_SHIFT            (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_PDAC_W0_2_52_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_52_D3ACP_SHIFT)) & XRDC_PDAC_W0_2_52_D3ACP_MASK)

#define XRDC_PDAC_W0_2_52_D4ACP_MASK             (0x7000U)
#define XRDC_PDAC_W0_2_52_D4ACP_SHIFT            (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_PDAC_W0_2_52_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_52_D4ACP_SHIFT)) & XRDC_PDAC_W0_2_52_D4ACP_MASK)

#define XRDC_PDAC_W0_2_52_D5ACP_MASK             (0x38000U)
#define XRDC_PDAC_W0_2_52_D5ACP_SHIFT            (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_PDAC_W0_2_52_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_52_D5ACP_SHIFT)) & XRDC_PDAC_W0_2_52_D5ACP_MASK)

#define XRDC_PDAC_W0_2_52_D6ACP_MASK             (0x1C0000U)
#define XRDC_PDAC_W0_2_52_D6ACP_SHIFT            (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_PDAC_W0_2_52_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_52_D6ACP_SHIFT)) & XRDC_PDAC_W0_2_52_D6ACP_MASK)

#define XRDC_PDAC_W0_2_52_D7ACP_MASK             (0xE00000U)
#define XRDC_PDAC_W0_2_52_D7ACP_SHIFT            (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_PDAC_W0_2_52_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_52_D7ACP_SHIFT)) & XRDC_PDAC_W0_2_52_D7ACP_MASK)

#define XRDC_PDAC_W0_2_52_EALO_MASK              (0xF000000U)
#define XRDC_PDAC_W0_2_52_EALO_SHIFT             (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_PDAC_W0_2_52_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_2_52_EALO_SHIFT)) & XRDC_PDAC_W0_2_52_EALO_MASK)
/*! @} */

/*! @name PDAC_W1_2_52 - Peripheral Domain Access Control */
/*! @{ */

#define XRDC_PDAC_W1_2_52_EAL_MASK               (0x3000000U)
#define XRDC_PDAC_W1_2_52_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_PDAC_W1_2_52_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_52_EAL_SHIFT)) & XRDC_PDAC_W1_2_52_EAL_MASK)

#define XRDC_PDAC_W1_2_52_LK2_MASK               (0x60000000U)
#define XRDC_PDAC_W1_2_52_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire PDACs can be written.
 *  0b01..Entire PDACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
 *  0b11..PDACs is locked (read-only) until the next reset.
 */
#define XRDC_PDAC_W1_2_52_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_52_LK2_SHIFT)) & XRDC_PDAC_W1_2_52_LK2_MASK)

#define XRDC_PDAC_W1_2_52_VLD_MASK               (0x80000000U)
#define XRDC_PDAC_W1_2_52_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The PDACs assignment is invalid.
 *  0b1..The PDACs assignment is valid.
 */
#define XRDC_PDAC_W1_2_52_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_2_52_VLD_SHIFT)) & XRDC_PDAC_W1_2_52_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_0_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_0_0_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_0_0_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_0_0_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_0_0_SRTADDR_SHIFT)) & XRDC_MRGD_W0_0_0_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_0_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_0_0_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_0_0_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_0_0_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_0_0_ENDADDR_SHIFT)) & XRDC_MRGD_W1_0_0_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_0_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_0_0_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_0_0_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_0_0_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_0_D0SEL_SHIFT)) & XRDC_MRGD_W2_0_0_D0SEL_MASK)

#define XRDC_MRGD_W2_0_0_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_0_0_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_0_0_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_0_D1SEL_SHIFT)) & XRDC_MRGD_W2_0_0_D1SEL_MASK)

#define XRDC_MRGD_W2_0_0_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_0_0_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_0_0_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_0_D2SEL_SHIFT)) & XRDC_MRGD_W2_0_0_D2SEL_MASK)

#define XRDC_MRGD_W2_0_0_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_0_0_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_0_0_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_0_D3SEL_SHIFT)) & XRDC_MRGD_W2_0_0_D3SEL_MASK)

#define XRDC_MRGD_W2_0_0_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_0_0_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_0_0_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_0_D4SEL_SHIFT)) & XRDC_MRGD_W2_0_0_D4SEL_MASK)

#define XRDC_MRGD_W2_0_0_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_0_0_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_0_0_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_0_D5SEL_SHIFT)) & XRDC_MRGD_W2_0_0_D5SEL_MASK)

#define XRDC_MRGD_W2_0_0_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_0_0_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_0_0_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_0_D6SEL_SHIFT)) & XRDC_MRGD_W2_0_0_D6SEL_MASK)

#define XRDC_MRGD_W2_0_0_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_0_0_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_0_0_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_0_D7SEL_SHIFT)) & XRDC_MRGD_W2_0_0_D7SEL_MASK)

#define XRDC_MRGD_W2_0_0_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_0_0_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_0_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_0_EALO_SHIFT)) & XRDC_MRGD_W2_0_0_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_0_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_0_0_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_0_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_0_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_0_0_EAL_SHIFT)) & XRDC_MRGD_W3_0_0_EAL_MASK)

#define XRDC_MRGD_W3_0_0_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_0_0_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_0_0_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_0_0_CR_SHIFT)) & XRDC_MRGD_W3_0_0_CR_MASK)
/*! @} */

/*! @name MRGD_W4_0_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_0_0_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_0_0_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_0_0_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_0_ACCSET1_SHIFT)) & XRDC_MRGD_W4_0_0_ACCSET1_MASK)

#define XRDC_MRGD_W4_0_0_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_0_0_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_0_0_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_0_LKAS1_SHIFT)) & XRDC_MRGD_W4_0_0_LKAS1_MASK)

#define XRDC_MRGD_W4_0_0_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_0_0_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_0_0_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_0_ACCSET2_SHIFT)) & XRDC_MRGD_W4_0_0_ACCSET2_MASK)

#define XRDC_MRGD_W4_0_0_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_0_0_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_0_0_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_0_LKAS2_SHIFT)) & XRDC_MRGD_W4_0_0_LKAS2_MASK)

#define XRDC_MRGD_W4_0_0_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_0_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_0_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_0_LK2_SHIFT)) & XRDC_MRGD_W4_0_0_LK2_MASK)

#define XRDC_MRGD_W4_0_0_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_0_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_0_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_0_VLD_SHIFT)) & XRDC_MRGD_W4_0_0_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_0_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_0_1_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_0_1_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_0_1_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_0_1_SRTADDR_SHIFT)) & XRDC_MRGD_W0_0_1_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_0_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_0_1_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_0_1_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_0_1_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_0_1_ENDADDR_SHIFT)) & XRDC_MRGD_W1_0_1_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_0_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_0_1_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_0_1_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_0_1_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_1_D0SEL_SHIFT)) & XRDC_MRGD_W2_0_1_D0SEL_MASK)

#define XRDC_MRGD_W2_0_1_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_0_1_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_0_1_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_1_D1SEL_SHIFT)) & XRDC_MRGD_W2_0_1_D1SEL_MASK)

#define XRDC_MRGD_W2_0_1_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_0_1_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_0_1_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_1_D2SEL_SHIFT)) & XRDC_MRGD_W2_0_1_D2SEL_MASK)

#define XRDC_MRGD_W2_0_1_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_0_1_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_0_1_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_1_D3SEL_SHIFT)) & XRDC_MRGD_W2_0_1_D3SEL_MASK)

#define XRDC_MRGD_W2_0_1_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_0_1_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_0_1_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_1_D4SEL_SHIFT)) & XRDC_MRGD_W2_0_1_D4SEL_MASK)

#define XRDC_MRGD_W2_0_1_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_0_1_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_0_1_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_1_D5SEL_SHIFT)) & XRDC_MRGD_W2_0_1_D5SEL_MASK)

#define XRDC_MRGD_W2_0_1_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_0_1_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_0_1_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_1_D6SEL_SHIFT)) & XRDC_MRGD_W2_0_1_D6SEL_MASK)

#define XRDC_MRGD_W2_0_1_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_0_1_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_0_1_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_1_D7SEL_SHIFT)) & XRDC_MRGD_W2_0_1_D7SEL_MASK)

#define XRDC_MRGD_W2_0_1_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_0_1_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_0_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_1_EALO_SHIFT)) & XRDC_MRGD_W2_0_1_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_0_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_0_1_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_0_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_0_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_0_1_EAL_SHIFT)) & XRDC_MRGD_W3_0_1_EAL_MASK)

#define XRDC_MRGD_W3_0_1_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_0_1_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_0_1_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_0_1_CR_SHIFT)) & XRDC_MRGD_W3_0_1_CR_MASK)
/*! @} */

/*! @name MRGD_W4_0_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_0_1_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_0_1_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_0_1_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_1_ACCSET1_SHIFT)) & XRDC_MRGD_W4_0_1_ACCSET1_MASK)

#define XRDC_MRGD_W4_0_1_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_0_1_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_0_1_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_1_LKAS1_SHIFT)) & XRDC_MRGD_W4_0_1_LKAS1_MASK)

#define XRDC_MRGD_W4_0_1_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_0_1_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_0_1_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_1_ACCSET2_SHIFT)) & XRDC_MRGD_W4_0_1_ACCSET2_MASK)

#define XRDC_MRGD_W4_0_1_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_0_1_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_0_1_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_1_LKAS2_SHIFT)) & XRDC_MRGD_W4_0_1_LKAS2_MASK)

#define XRDC_MRGD_W4_0_1_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_0_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_0_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_1_LK2_SHIFT)) & XRDC_MRGD_W4_0_1_LK2_MASK)

#define XRDC_MRGD_W4_0_1_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_0_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_0_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_1_VLD_SHIFT)) & XRDC_MRGD_W4_0_1_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_0_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_0_2_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_0_2_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_0_2_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_0_2_SRTADDR_SHIFT)) & XRDC_MRGD_W0_0_2_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_0_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_0_2_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_0_2_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_0_2_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_0_2_ENDADDR_SHIFT)) & XRDC_MRGD_W1_0_2_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_0_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_0_2_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_0_2_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_0_2_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_2_D0SEL_SHIFT)) & XRDC_MRGD_W2_0_2_D0SEL_MASK)

#define XRDC_MRGD_W2_0_2_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_0_2_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_0_2_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_2_D1SEL_SHIFT)) & XRDC_MRGD_W2_0_2_D1SEL_MASK)

#define XRDC_MRGD_W2_0_2_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_0_2_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_0_2_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_2_D2SEL_SHIFT)) & XRDC_MRGD_W2_0_2_D2SEL_MASK)

#define XRDC_MRGD_W2_0_2_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_0_2_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_0_2_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_2_D3SEL_SHIFT)) & XRDC_MRGD_W2_0_2_D3SEL_MASK)

#define XRDC_MRGD_W2_0_2_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_0_2_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_0_2_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_2_D4SEL_SHIFT)) & XRDC_MRGD_W2_0_2_D4SEL_MASK)

#define XRDC_MRGD_W2_0_2_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_0_2_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_0_2_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_2_D5SEL_SHIFT)) & XRDC_MRGD_W2_0_2_D5SEL_MASK)

#define XRDC_MRGD_W2_0_2_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_0_2_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_0_2_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_2_D6SEL_SHIFT)) & XRDC_MRGD_W2_0_2_D6SEL_MASK)

#define XRDC_MRGD_W2_0_2_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_0_2_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_0_2_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_2_D7SEL_SHIFT)) & XRDC_MRGD_W2_0_2_D7SEL_MASK)

#define XRDC_MRGD_W2_0_2_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_0_2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_0_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_2_EALO_SHIFT)) & XRDC_MRGD_W2_0_2_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_0_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_0_2_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_0_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_0_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_0_2_EAL_SHIFT)) & XRDC_MRGD_W3_0_2_EAL_MASK)

#define XRDC_MRGD_W3_0_2_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_0_2_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_0_2_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_0_2_CR_SHIFT)) & XRDC_MRGD_W3_0_2_CR_MASK)
/*! @} */

/*! @name MRGD_W4_0_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_0_2_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_0_2_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_0_2_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_2_ACCSET1_SHIFT)) & XRDC_MRGD_W4_0_2_ACCSET1_MASK)

#define XRDC_MRGD_W4_0_2_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_0_2_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_0_2_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_2_LKAS1_SHIFT)) & XRDC_MRGD_W4_0_2_LKAS1_MASK)

#define XRDC_MRGD_W4_0_2_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_0_2_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_0_2_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_2_ACCSET2_SHIFT)) & XRDC_MRGD_W4_0_2_ACCSET2_MASK)

#define XRDC_MRGD_W4_0_2_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_0_2_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_0_2_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_2_LKAS2_SHIFT)) & XRDC_MRGD_W4_0_2_LKAS2_MASK)

#define XRDC_MRGD_W4_0_2_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_0_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_0_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_2_LK2_SHIFT)) & XRDC_MRGD_W4_0_2_LK2_MASK)

#define XRDC_MRGD_W4_0_2_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_0_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_0_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_2_VLD_SHIFT)) & XRDC_MRGD_W4_0_2_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_0_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_0_3_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_0_3_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_0_3_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_0_3_SRTADDR_SHIFT)) & XRDC_MRGD_W0_0_3_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_0_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_0_3_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_0_3_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_0_3_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_0_3_ENDADDR_SHIFT)) & XRDC_MRGD_W1_0_3_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_0_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_0_3_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_0_3_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_0_3_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_3_D0SEL_SHIFT)) & XRDC_MRGD_W2_0_3_D0SEL_MASK)

#define XRDC_MRGD_W2_0_3_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_0_3_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_0_3_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_3_D1SEL_SHIFT)) & XRDC_MRGD_W2_0_3_D1SEL_MASK)

#define XRDC_MRGD_W2_0_3_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_0_3_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_0_3_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_3_D2SEL_SHIFT)) & XRDC_MRGD_W2_0_3_D2SEL_MASK)

#define XRDC_MRGD_W2_0_3_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_0_3_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_0_3_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_3_D3SEL_SHIFT)) & XRDC_MRGD_W2_0_3_D3SEL_MASK)

#define XRDC_MRGD_W2_0_3_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_0_3_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_0_3_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_3_D4SEL_SHIFT)) & XRDC_MRGD_W2_0_3_D4SEL_MASK)

#define XRDC_MRGD_W2_0_3_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_0_3_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_0_3_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_3_D5SEL_SHIFT)) & XRDC_MRGD_W2_0_3_D5SEL_MASK)

#define XRDC_MRGD_W2_0_3_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_0_3_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_0_3_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_3_D6SEL_SHIFT)) & XRDC_MRGD_W2_0_3_D6SEL_MASK)

#define XRDC_MRGD_W2_0_3_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_0_3_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_0_3_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_3_D7SEL_SHIFT)) & XRDC_MRGD_W2_0_3_D7SEL_MASK)

#define XRDC_MRGD_W2_0_3_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_0_3_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_0_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_0_3_EALO_SHIFT)) & XRDC_MRGD_W2_0_3_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_0_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_0_3_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_0_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_0_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_0_3_EAL_SHIFT)) & XRDC_MRGD_W3_0_3_EAL_MASK)

#define XRDC_MRGD_W3_0_3_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_0_3_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_0_3_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_0_3_CR_SHIFT)) & XRDC_MRGD_W3_0_3_CR_MASK)
/*! @} */

/*! @name MRGD_W4_0_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_0_3_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_0_3_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_0_3_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_3_ACCSET1_SHIFT)) & XRDC_MRGD_W4_0_3_ACCSET1_MASK)

#define XRDC_MRGD_W4_0_3_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_0_3_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_0_3_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_3_LKAS1_SHIFT)) & XRDC_MRGD_W4_0_3_LKAS1_MASK)

#define XRDC_MRGD_W4_0_3_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_0_3_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_0_3_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_3_ACCSET2_SHIFT)) & XRDC_MRGD_W4_0_3_ACCSET2_MASK)

#define XRDC_MRGD_W4_0_3_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_0_3_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_0_3_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_3_LKAS2_SHIFT)) & XRDC_MRGD_W4_0_3_LKAS2_MASK)

#define XRDC_MRGD_W4_0_3_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_0_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_0_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_3_LK2_SHIFT)) & XRDC_MRGD_W4_0_3_LK2_MASK)

#define XRDC_MRGD_W4_0_3_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_0_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_0_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_0_3_VLD_SHIFT)) & XRDC_MRGD_W4_0_3_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_1_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_1_0_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_1_0_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_1_0_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_1_0_SRTADDR_SHIFT)) & XRDC_MRGD_W0_1_0_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_1_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_1_0_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_1_0_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_1_0_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_1_0_ENDADDR_SHIFT)) & XRDC_MRGD_W1_1_0_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_1_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_1_0_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_1_0_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_1_0_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_0_D0SEL_SHIFT)) & XRDC_MRGD_W2_1_0_D0SEL_MASK)

#define XRDC_MRGD_W2_1_0_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_1_0_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_1_0_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_0_D1SEL_SHIFT)) & XRDC_MRGD_W2_1_0_D1SEL_MASK)

#define XRDC_MRGD_W2_1_0_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_1_0_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_1_0_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_0_D2SEL_SHIFT)) & XRDC_MRGD_W2_1_0_D2SEL_MASK)

#define XRDC_MRGD_W2_1_0_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_1_0_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_1_0_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_0_D3SEL_SHIFT)) & XRDC_MRGD_W2_1_0_D3SEL_MASK)

#define XRDC_MRGD_W2_1_0_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_1_0_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_1_0_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_0_D4SEL_SHIFT)) & XRDC_MRGD_W2_1_0_D4SEL_MASK)

#define XRDC_MRGD_W2_1_0_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_1_0_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_1_0_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_0_D5SEL_SHIFT)) & XRDC_MRGD_W2_1_0_D5SEL_MASK)

#define XRDC_MRGD_W2_1_0_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_1_0_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_1_0_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_0_D6SEL_SHIFT)) & XRDC_MRGD_W2_1_0_D6SEL_MASK)

#define XRDC_MRGD_W2_1_0_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_1_0_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_1_0_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_0_D7SEL_SHIFT)) & XRDC_MRGD_W2_1_0_D7SEL_MASK)

#define XRDC_MRGD_W2_1_0_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_1_0_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_1_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_0_EALO_SHIFT)) & XRDC_MRGD_W2_1_0_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_1_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_1_0_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_1_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_1_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_0_EAL_SHIFT)) & XRDC_MRGD_W3_1_0_EAL_MASK)

#define XRDC_MRGD_W3_1_0_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_1_0_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_1_0_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_0_CR_SHIFT)) & XRDC_MRGD_W3_1_0_CR_MASK)
/*! @} */

/*! @name MRGD_W4_1_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_1_0_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_1_0_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_1_0_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_0_ACCSET1_SHIFT)) & XRDC_MRGD_W4_1_0_ACCSET1_MASK)

#define XRDC_MRGD_W4_1_0_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_1_0_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_1_0_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_0_LKAS1_SHIFT)) & XRDC_MRGD_W4_1_0_LKAS1_MASK)

#define XRDC_MRGD_W4_1_0_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_1_0_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_1_0_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_0_ACCSET2_SHIFT)) & XRDC_MRGD_W4_1_0_ACCSET2_MASK)

#define XRDC_MRGD_W4_1_0_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_1_0_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_1_0_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_0_LKAS2_SHIFT)) & XRDC_MRGD_W4_1_0_LKAS2_MASK)

#define XRDC_MRGD_W4_1_0_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_1_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_1_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_0_LK2_SHIFT)) & XRDC_MRGD_W4_1_0_LK2_MASK)

#define XRDC_MRGD_W4_1_0_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_1_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_1_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_0_VLD_SHIFT)) & XRDC_MRGD_W4_1_0_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_1_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_1_1_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_1_1_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_1_1_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_1_1_SRTADDR_SHIFT)) & XRDC_MRGD_W0_1_1_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_1_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_1_1_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_1_1_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_1_1_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_1_1_ENDADDR_SHIFT)) & XRDC_MRGD_W1_1_1_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_1_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_1_1_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_1_1_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_1_1_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_1_D0SEL_SHIFT)) & XRDC_MRGD_W2_1_1_D0SEL_MASK)

#define XRDC_MRGD_W2_1_1_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_1_1_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_1_1_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_1_D1SEL_SHIFT)) & XRDC_MRGD_W2_1_1_D1SEL_MASK)

#define XRDC_MRGD_W2_1_1_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_1_1_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_1_1_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_1_D2SEL_SHIFT)) & XRDC_MRGD_W2_1_1_D2SEL_MASK)

#define XRDC_MRGD_W2_1_1_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_1_1_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_1_1_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_1_D3SEL_SHIFT)) & XRDC_MRGD_W2_1_1_D3SEL_MASK)

#define XRDC_MRGD_W2_1_1_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_1_1_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_1_1_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_1_D4SEL_SHIFT)) & XRDC_MRGD_W2_1_1_D4SEL_MASK)

#define XRDC_MRGD_W2_1_1_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_1_1_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_1_1_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_1_D5SEL_SHIFT)) & XRDC_MRGD_W2_1_1_D5SEL_MASK)

#define XRDC_MRGD_W2_1_1_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_1_1_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_1_1_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_1_D6SEL_SHIFT)) & XRDC_MRGD_W2_1_1_D6SEL_MASK)

#define XRDC_MRGD_W2_1_1_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_1_1_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_1_1_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_1_D7SEL_SHIFT)) & XRDC_MRGD_W2_1_1_D7SEL_MASK)

#define XRDC_MRGD_W2_1_1_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_1_1_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_1_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_1_EALO_SHIFT)) & XRDC_MRGD_W2_1_1_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_1_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_1_1_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_1_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_1_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_1_EAL_SHIFT)) & XRDC_MRGD_W3_1_1_EAL_MASK)

#define XRDC_MRGD_W3_1_1_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_1_1_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_1_1_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_1_CR_SHIFT)) & XRDC_MRGD_W3_1_1_CR_MASK)
/*! @} */

/*! @name MRGD_W4_1_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_1_1_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_1_1_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_1_1_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_1_ACCSET1_SHIFT)) & XRDC_MRGD_W4_1_1_ACCSET1_MASK)

#define XRDC_MRGD_W4_1_1_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_1_1_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_1_1_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_1_LKAS1_SHIFT)) & XRDC_MRGD_W4_1_1_LKAS1_MASK)

#define XRDC_MRGD_W4_1_1_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_1_1_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_1_1_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_1_ACCSET2_SHIFT)) & XRDC_MRGD_W4_1_1_ACCSET2_MASK)

#define XRDC_MRGD_W4_1_1_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_1_1_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_1_1_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_1_LKAS2_SHIFT)) & XRDC_MRGD_W4_1_1_LKAS2_MASK)

#define XRDC_MRGD_W4_1_1_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_1_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_1_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_1_LK2_SHIFT)) & XRDC_MRGD_W4_1_1_LK2_MASK)

#define XRDC_MRGD_W4_1_1_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_1_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_1_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_1_VLD_SHIFT)) & XRDC_MRGD_W4_1_1_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_1_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_1_2_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_1_2_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_1_2_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_1_2_SRTADDR_SHIFT)) & XRDC_MRGD_W0_1_2_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_1_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_1_2_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_1_2_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_1_2_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_1_2_ENDADDR_SHIFT)) & XRDC_MRGD_W1_1_2_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_1_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_1_2_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_1_2_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_1_2_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_2_D0SEL_SHIFT)) & XRDC_MRGD_W2_1_2_D0SEL_MASK)

#define XRDC_MRGD_W2_1_2_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_1_2_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_1_2_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_2_D1SEL_SHIFT)) & XRDC_MRGD_W2_1_2_D1SEL_MASK)

#define XRDC_MRGD_W2_1_2_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_1_2_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_1_2_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_2_D2SEL_SHIFT)) & XRDC_MRGD_W2_1_2_D2SEL_MASK)

#define XRDC_MRGD_W2_1_2_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_1_2_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_1_2_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_2_D3SEL_SHIFT)) & XRDC_MRGD_W2_1_2_D3SEL_MASK)

#define XRDC_MRGD_W2_1_2_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_1_2_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_1_2_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_2_D4SEL_SHIFT)) & XRDC_MRGD_W2_1_2_D4SEL_MASK)

#define XRDC_MRGD_W2_1_2_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_1_2_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_1_2_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_2_D5SEL_SHIFT)) & XRDC_MRGD_W2_1_2_D5SEL_MASK)

#define XRDC_MRGD_W2_1_2_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_1_2_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_1_2_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_2_D6SEL_SHIFT)) & XRDC_MRGD_W2_1_2_D6SEL_MASK)

#define XRDC_MRGD_W2_1_2_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_1_2_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_1_2_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_2_D7SEL_SHIFT)) & XRDC_MRGD_W2_1_2_D7SEL_MASK)

#define XRDC_MRGD_W2_1_2_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_1_2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_1_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_2_EALO_SHIFT)) & XRDC_MRGD_W2_1_2_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_1_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_1_2_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_1_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_1_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_2_EAL_SHIFT)) & XRDC_MRGD_W3_1_2_EAL_MASK)

#define XRDC_MRGD_W3_1_2_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_1_2_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_1_2_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_2_CR_SHIFT)) & XRDC_MRGD_W3_1_2_CR_MASK)
/*! @} */

/*! @name MRGD_W4_1_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_1_2_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_1_2_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_1_2_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_2_ACCSET1_SHIFT)) & XRDC_MRGD_W4_1_2_ACCSET1_MASK)

#define XRDC_MRGD_W4_1_2_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_1_2_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_1_2_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_2_LKAS1_SHIFT)) & XRDC_MRGD_W4_1_2_LKAS1_MASK)

#define XRDC_MRGD_W4_1_2_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_1_2_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_1_2_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_2_ACCSET2_SHIFT)) & XRDC_MRGD_W4_1_2_ACCSET2_MASK)

#define XRDC_MRGD_W4_1_2_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_1_2_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_1_2_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_2_LKAS2_SHIFT)) & XRDC_MRGD_W4_1_2_LKAS2_MASK)

#define XRDC_MRGD_W4_1_2_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_1_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_1_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_2_LK2_SHIFT)) & XRDC_MRGD_W4_1_2_LK2_MASK)

#define XRDC_MRGD_W4_1_2_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_1_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_1_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_2_VLD_SHIFT)) & XRDC_MRGD_W4_1_2_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_1_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_1_3_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_1_3_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_1_3_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_1_3_SRTADDR_SHIFT)) & XRDC_MRGD_W0_1_3_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_1_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_1_3_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_1_3_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_1_3_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_1_3_ENDADDR_SHIFT)) & XRDC_MRGD_W1_1_3_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_1_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_1_3_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_1_3_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_1_3_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_3_D0SEL_SHIFT)) & XRDC_MRGD_W2_1_3_D0SEL_MASK)

#define XRDC_MRGD_W2_1_3_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_1_3_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_1_3_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_3_D1SEL_SHIFT)) & XRDC_MRGD_W2_1_3_D1SEL_MASK)

#define XRDC_MRGD_W2_1_3_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_1_3_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_1_3_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_3_D2SEL_SHIFT)) & XRDC_MRGD_W2_1_3_D2SEL_MASK)

#define XRDC_MRGD_W2_1_3_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_1_3_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_1_3_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_3_D3SEL_SHIFT)) & XRDC_MRGD_W2_1_3_D3SEL_MASK)

#define XRDC_MRGD_W2_1_3_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_1_3_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_1_3_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_3_D4SEL_SHIFT)) & XRDC_MRGD_W2_1_3_D4SEL_MASK)

#define XRDC_MRGD_W2_1_3_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_1_3_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_1_3_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_3_D5SEL_SHIFT)) & XRDC_MRGD_W2_1_3_D5SEL_MASK)

#define XRDC_MRGD_W2_1_3_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_1_3_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_1_3_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_3_D6SEL_SHIFT)) & XRDC_MRGD_W2_1_3_D6SEL_MASK)

#define XRDC_MRGD_W2_1_3_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_1_3_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_1_3_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_3_D7SEL_SHIFT)) & XRDC_MRGD_W2_1_3_D7SEL_MASK)

#define XRDC_MRGD_W2_1_3_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_1_3_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_1_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_3_EALO_SHIFT)) & XRDC_MRGD_W2_1_3_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_1_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_1_3_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_1_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_1_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_3_EAL_SHIFT)) & XRDC_MRGD_W3_1_3_EAL_MASK)

#define XRDC_MRGD_W3_1_3_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_1_3_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_1_3_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_3_CR_SHIFT)) & XRDC_MRGD_W3_1_3_CR_MASK)
/*! @} */

/*! @name MRGD_W4_1_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_1_3_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_1_3_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_1_3_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_3_ACCSET1_SHIFT)) & XRDC_MRGD_W4_1_3_ACCSET1_MASK)

#define XRDC_MRGD_W4_1_3_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_1_3_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_1_3_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_3_LKAS1_SHIFT)) & XRDC_MRGD_W4_1_3_LKAS1_MASK)

#define XRDC_MRGD_W4_1_3_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_1_3_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_1_3_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_3_ACCSET2_SHIFT)) & XRDC_MRGD_W4_1_3_ACCSET2_MASK)

#define XRDC_MRGD_W4_1_3_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_1_3_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_1_3_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_3_LKAS2_SHIFT)) & XRDC_MRGD_W4_1_3_LKAS2_MASK)

#define XRDC_MRGD_W4_1_3_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_1_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_1_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_3_LK2_SHIFT)) & XRDC_MRGD_W4_1_3_LK2_MASK)

#define XRDC_MRGD_W4_1_3_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_1_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_1_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_3_VLD_SHIFT)) & XRDC_MRGD_W4_1_3_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_1_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_1_4_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_1_4_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_1_4_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_1_4_SRTADDR_SHIFT)) & XRDC_MRGD_W0_1_4_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_1_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_1_4_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_1_4_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_1_4_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_1_4_ENDADDR_SHIFT)) & XRDC_MRGD_W1_1_4_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_1_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_1_4_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_1_4_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_1_4_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_4_D0SEL_SHIFT)) & XRDC_MRGD_W2_1_4_D0SEL_MASK)

#define XRDC_MRGD_W2_1_4_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_1_4_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_1_4_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_4_D1SEL_SHIFT)) & XRDC_MRGD_W2_1_4_D1SEL_MASK)

#define XRDC_MRGD_W2_1_4_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_1_4_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_1_4_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_4_D2SEL_SHIFT)) & XRDC_MRGD_W2_1_4_D2SEL_MASK)

#define XRDC_MRGD_W2_1_4_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_1_4_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_1_4_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_4_D3SEL_SHIFT)) & XRDC_MRGD_W2_1_4_D3SEL_MASK)

#define XRDC_MRGD_W2_1_4_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_1_4_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_1_4_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_4_D4SEL_SHIFT)) & XRDC_MRGD_W2_1_4_D4SEL_MASK)

#define XRDC_MRGD_W2_1_4_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_1_4_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_1_4_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_4_D5SEL_SHIFT)) & XRDC_MRGD_W2_1_4_D5SEL_MASK)

#define XRDC_MRGD_W2_1_4_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_1_4_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_1_4_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_4_D6SEL_SHIFT)) & XRDC_MRGD_W2_1_4_D6SEL_MASK)

#define XRDC_MRGD_W2_1_4_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_1_4_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_1_4_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_4_D7SEL_SHIFT)) & XRDC_MRGD_W2_1_4_D7SEL_MASK)

#define XRDC_MRGD_W2_1_4_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_1_4_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_1_4_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_4_EALO_SHIFT)) & XRDC_MRGD_W2_1_4_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_1_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_1_4_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_1_4_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_1_4_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_4_EAL_SHIFT)) & XRDC_MRGD_W3_1_4_EAL_MASK)

#define XRDC_MRGD_W3_1_4_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_1_4_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_1_4_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_4_CR_SHIFT)) & XRDC_MRGD_W3_1_4_CR_MASK)
/*! @} */

/*! @name MRGD_W4_1_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_1_4_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_1_4_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_1_4_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_4_ACCSET1_SHIFT)) & XRDC_MRGD_W4_1_4_ACCSET1_MASK)

#define XRDC_MRGD_W4_1_4_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_1_4_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_1_4_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_4_LKAS1_SHIFT)) & XRDC_MRGD_W4_1_4_LKAS1_MASK)

#define XRDC_MRGD_W4_1_4_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_1_4_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_1_4_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_4_ACCSET2_SHIFT)) & XRDC_MRGD_W4_1_4_ACCSET2_MASK)

#define XRDC_MRGD_W4_1_4_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_1_4_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_1_4_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_4_LKAS2_SHIFT)) & XRDC_MRGD_W4_1_4_LKAS2_MASK)

#define XRDC_MRGD_W4_1_4_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_1_4_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_1_4_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_4_LK2_SHIFT)) & XRDC_MRGD_W4_1_4_LK2_MASK)

#define XRDC_MRGD_W4_1_4_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_1_4_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_1_4_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_4_VLD_SHIFT)) & XRDC_MRGD_W4_1_4_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_1_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_1_5_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_1_5_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_1_5_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_1_5_SRTADDR_SHIFT)) & XRDC_MRGD_W0_1_5_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_1_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_1_5_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_1_5_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_1_5_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_1_5_ENDADDR_SHIFT)) & XRDC_MRGD_W1_1_5_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_1_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_1_5_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_1_5_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_1_5_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_5_D0SEL_SHIFT)) & XRDC_MRGD_W2_1_5_D0SEL_MASK)

#define XRDC_MRGD_W2_1_5_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_1_5_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_1_5_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_5_D1SEL_SHIFT)) & XRDC_MRGD_W2_1_5_D1SEL_MASK)

#define XRDC_MRGD_W2_1_5_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_1_5_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_1_5_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_5_D2SEL_SHIFT)) & XRDC_MRGD_W2_1_5_D2SEL_MASK)

#define XRDC_MRGD_W2_1_5_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_1_5_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_1_5_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_5_D3SEL_SHIFT)) & XRDC_MRGD_W2_1_5_D3SEL_MASK)

#define XRDC_MRGD_W2_1_5_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_1_5_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_1_5_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_5_D4SEL_SHIFT)) & XRDC_MRGD_W2_1_5_D4SEL_MASK)

#define XRDC_MRGD_W2_1_5_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_1_5_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_1_5_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_5_D5SEL_SHIFT)) & XRDC_MRGD_W2_1_5_D5SEL_MASK)

#define XRDC_MRGD_W2_1_5_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_1_5_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_1_5_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_5_D6SEL_SHIFT)) & XRDC_MRGD_W2_1_5_D6SEL_MASK)

#define XRDC_MRGD_W2_1_5_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_1_5_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_1_5_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_5_D7SEL_SHIFT)) & XRDC_MRGD_W2_1_5_D7SEL_MASK)

#define XRDC_MRGD_W2_1_5_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_1_5_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_1_5_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_5_EALO_SHIFT)) & XRDC_MRGD_W2_1_5_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_1_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_1_5_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_1_5_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_1_5_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_5_EAL_SHIFT)) & XRDC_MRGD_W3_1_5_EAL_MASK)

#define XRDC_MRGD_W3_1_5_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_1_5_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_1_5_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_5_CR_SHIFT)) & XRDC_MRGD_W3_1_5_CR_MASK)
/*! @} */

/*! @name MRGD_W4_1_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_1_5_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_1_5_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_1_5_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_5_ACCSET1_SHIFT)) & XRDC_MRGD_W4_1_5_ACCSET1_MASK)

#define XRDC_MRGD_W4_1_5_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_1_5_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_1_5_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_5_LKAS1_SHIFT)) & XRDC_MRGD_W4_1_5_LKAS1_MASK)

#define XRDC_MRGD_W4_1_5_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_1_5_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_1_5_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_5_ACCSET2_SHIFT)) & XRDC_MRGD_W4_1_5_ACCSET2_MASK)

#define XRDC_MRGD_W4_1_5_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_1_5_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_1_5_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_5_LKAS2_SHIFT)) & XRDC_MRGD_W4_1_5_LKAS2_MASK)

#define XRDC_MRGD_W4_1_5_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_1_5_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_1_5_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_5_LK2_SHIFT)) & XRDC_MRGD_W4_1_5_LK2_MASK)

#define XRDC_MRGD_W4_1_5_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_1_5_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_1_5_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_5_VLD_SHIFT)) & XRDC_MRGD_W4_1_5_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_1_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_1_6_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_1_6_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_1_6_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_1_6_SRTADDR_SHIFT)) & XRDC_MRGD_W0_1_6_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_1_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_1_6_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_1_6_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_1_6_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_1_6_ENDADDR_SHIFT)) & XRDC_MRGD_W1_1_6_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_1_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_1_6_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_1_6_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_1_6_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_6_D0SEL_SHIFT)) & XRDC_MRGD_W2_1_6_D0SEL_MASK)

#define XRDC_MRGD_W2_1_6_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_1_6_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_1_6_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_6_D1SEL_SHIFT)) & XRDC_MRGD_W2_1_6_D1SEL_MASK)

#define XRDC_MRGD_W2_1_6_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_1_6_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_1_6_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_6_D2SEL_SHIFT)) & XRDC_MRGD_W2_1_6_D2SEL_MASK)

#define XRDC_MRGD_W2_1_6_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_1_6_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_1_6_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_6_D3SEL_SHIFT)) & XRDC_MRGD_W2_1_6_D3SEL_MASK)

#define XRDC_MRGD_W2_1_6_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_1_6_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_1_6_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_6_D4SEL_SHIFT)) & XRDC_MRGD_W2_1_6_D4SEL_MASK)

#define XRDC_MRGD_W2_1_6_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_1_6_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_1_6_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_6_D5SEL_SHIFT)) & XRDC_MRGD_W2_1_6_D5SEL_MASK)

#define XRDC_MRGD_W2_1_6_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_1_6_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_1_6_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_6_D6SEL_SHIFT)) & XRDC_MRGD_W2_1_6_D6SEL_MASK)

#define XRDC_MRGD_W2_1_6_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_1_6_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_1_6_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_6_D7SEL_SHIFT)) & XRDC_MRGD_W2_1_6_D7SEL_MASK)

#define XRDC_MRGD_W2_1_6_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_1_6_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_1_6_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_6_EALO_SHIFT)) & XRDC_MRGD_W2_1_6_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_1_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_1_6_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_1_6_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_1_6_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_6_EAL_SHIFT)) & XRDC_MRGD_W3_1_6_EAL_MASK)

#define XRDC_MRGD_W3_1_6_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_1_6_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_1_6_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_6_CR_SHIFT)) & XRDC_MRGD_W3_1_6_CR_MASK)
/*! @} */

/*! @name MRGD_W4_1_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_1_6_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_1_6_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_1_6_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_6_ACCSET1_SHIFT)) & XRDC_MRGD_W4_1_6_ACCSET1_MASK)

#define XRDC_MRGD_W4_1_6_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_1_6_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_1_6_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_6_LKAS1_SHIFT)) & XRDC_MRGD_W4_1_6_LKAS1_MASK)

#define XRDC_MRGD_W4_1_6_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_1_6_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_1_6_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_6_ACCSET2_SHIFT)) & XRDC_MRGD_W4_1_6_ACCSET2_MASK)

#define XRDC_MRGD_W4_1_6_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_1_6_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_1_6_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_6_LKAS2_SHIFT)) & XRDC_MRGD_W4_1_6_LKAS2_MASK)

#define XRDC_MRGD_W4_1_6_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_1_6_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_1_6_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_6_LK2_SHIFT)) & XRDC_MRGD_W4_1_6_LK2_MASK)

#define XRDC_MRGD_W4_1_6_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_1_6_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_1_6_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_6_VLD_SHIFT)) & XRDC_MRGD_W4_1_6_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_1_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_1_7_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_1_7_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_1_7_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_1_7_SRTADDR_SHIFT)) & XRDC_MRGD_W0_1_7_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_1_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_1_7_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_1_7_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_1_7_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_1_7_ENDADDR_SHIFT)) & XRDC_MRGD_W1_1_7_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_1_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_1_7_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_1_7_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_1_7_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_7_D0SEL_SHIFT)) & XRDC_MRGD_W2_1_7_D0SEL_MASK)

#define XRDC_MRGD_W2_1_7_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_1_7_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_1_7_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_7_D1SEL_SHIFT)) & XRDC_MRGD_W2_1_7_D1SEL_MASK)

#define XRDC_MRGD_W2_1_7_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_1_7_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_1_7_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_7_D2SEL_SHIFT)) & XRDC_MRGD_W2_1_7_D2SEL_MASK)

#define XRDC_MRGD_W2_1_7_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_1_7_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_1_7_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_7_D3SEL_SHIFT)) & XRDC_MRGD_W2_1_7_D3SEL_MASK)

#define XRDC_MRGD_W2_1_7_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_1_7_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_1_7_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_7_D4SEL_SHIFT)) & XRDC_MRGD_W2_1_7_D4SEL_MASK)

#define XRDC_MRGD_W2_1_7_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_1_7_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_1_7_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_7_D5SEL_SHIFT)) & XRDC_MRGD_W2_1_7_D5SEL_MASK)

#define XRDC_MRGD_W2_1_7_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_1_7_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_1_7_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_7_D6SEL_SHIFT)) & XRDC_MRGD_W2_1_7_D6SEL_MASK)

#define XRDC_MRGD_W2_1_7_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_1_7_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_1_7_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_7_D7SEL_SHIFT)) & XRDC_MRGD_W2_1_7_D7SEL_MASK)

#define XRDC_MRGD_W2_1_7_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_1_7_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_1_7_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_1_7_EALO_SHIFT)) & XRDC_MRGD_W2_1_7_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_1_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_1_7_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_1_7_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_1_7_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_7_EAL_SHIFT)) & XRDC_MRGD_W3_1_7_EAL_MASK)

#define XRDC_MRGD_W3_1_7_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_1_7_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_1_7_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_1_7_CR_SHIFT)) & XRDC_MRGD_W3_1_7_CR_MASK)
/*! @} */

/*! @name MRGD_W4_1_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_1_7_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_1_7_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_1_7_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_7_ACCSET1_SHIFT)) & XRDC_MRGD_W4_1_7_ACCSET1_MASK)

#define XRDC_MRGD_W4_1_7_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_1_7_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_1_7_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_7_LKAS1_SHIFT)) & XRDC_MRGD_W4_1_7_LKAS1_MASK)

#define XRDC_MRGD_W4_1_7_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_1_7_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_1_7_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_7_ACCSET2_SHIFT)) & XRDC_MRGD_W4_1_7_ACCSET2_MASK)

#define XRDC_MRGD_W4_1_7_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_1_7_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_1_7_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_7_LKAS2_SHIFT)) & XRDC_MRGD_W4_1_7_LKAS2_MASK)

#define XRDC_MRGD_W4_1_7_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_1_7_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_1_7_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_7_LK2_SHIFT)) & XRDC_MRGD_W4_1_7_LK2_MASK)

#define XRDC_MRGD_W4_1_7_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_1_7_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_1_7_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_1_7_VLD_SHIFT)) & XRDC_MRGD_W4_1_7_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_2_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_2_0_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_2_0_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_2_0_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_2_0_SRTADDR_SHIFT)) & XRDC_MRGD_W0_2_0_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_2_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_2_0_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_2_0_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_2_0_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_2_0_ENDADDR_SHIFT)) & XRDC_MRGD_W1_2_0_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_2_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_2_0_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_2_0_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_2_0_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_0_D0SEL_SHIFT)) & XRDC_MRGD_W2_2_0_D0SEL_MASK)

#define XRDC_MRGD_W2_2_0_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_2_0_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_2_0_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_0_D1SEL_SHIFT)) & XRDC_MRGD_W2_2_0_D1SEL_MASK)

#define XRDC_MRGD_W2_2_0_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_2_0_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_2_0_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_0_D2SEL_SHIFT)) & XRDC_MRGD_W2_2_0_D2SEL_MASK)

#define XRDC_MRGD_W2_2_0_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_2_0_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_2_0_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_0_D3SEL_SHIFT)) & XRDC_MRGD_W2_2_0_D3SEL_MASK)

#define XRDC_MRGD_W2_2_0_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_2_0_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_2_0_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_0_D4SEL_SHIFT)) & XRDC_MRGD_W2_2_0_D4SEL_MASK)

#define XRDC_MRGD_W2_2_0_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_2_0_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_2_0_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_0_D5SEL_SHIFT)) & XRDC_MRGD_W2_2_0_D5SEL_MASK)

#define XRDC_MRGD_W2_2_0_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_2_0_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_2_0_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_0_D6SEL_SHIFT)) & XRDC_MRGD_W2_2_0_D6SEL_MASK)

#define XRDC_MRGD_W2_2_0_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_2_0_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_2_0_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_0_D7SEL_SHIFT)) & XRDC_MRGD_W2_2_0_D7SEL_MASK)

#define XRDC_MRGD_W2_2_0_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_2_0_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_2_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_0_EALO_SHIFT)) & XRDC_MRGD_W2_2_0_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_2_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_2_0_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_2_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_2_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_2_0_EAL_SHIFT)) & XRDC_MRGD_W3_2_0_EAL_MASK)

#define XRDC_MRGD_W3_2_0_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_2_0_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_2_0_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_2_0_CR_SHIFT)) & XRDC_MRGD_W3_2_0_CR_MASK)
/*! @} */

/*! @name MRGD_W4_2_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_2_0_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_2_0_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_2_0_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_0_ACCSET1_SHIFT)) & XRDC_MRGD_W4_2_0_ACCSET1_MASK)

#define XRDC_MRGD_W4_2_0_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_2_0_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_2_0_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_0_LKAS1_SHIFT)) & XRDC_MRGD_W4_2_0_LKAS1_MASK)

#define XRDC_MRGD_W4_2_0_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_2_0_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_2_0_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_0_ACCSET2_SHIFT)) & XRDC_MRGD_W4_2_0_ACCSET2_MASK)

#define XRDC_MRGD_W4_2_0_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_2_0_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_2_0_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_0_LKAS2_SHIFT)) & XRDC_MRGD_W4_2_0_LKAS2_MASK)

#define XRDC_MRGD_W4_2_0_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_2_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_2_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_0_LK2_SHIFT)) & XRDC_MRGD_W4_2_0_LK2_MASK)

#define XRDC_MRGD_W4_2_0_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_2_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_2_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_0_VLD_SHIFT)) & XRDC_MRGD_W4_2_0_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_2_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_2_1_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_2_1_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_2_1_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_2_1_SRTADDR_SHIFT)) & XRDC_MRGD_W0_2_1_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_2_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_2_1_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_2_1_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_2_1_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_2_1_ENDADDR_SHIFT)) & XRDC_MRGD_W1_2_1_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_2_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_2_1_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_2_1_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_2_1_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_1_D0SEL_SHIFT)) & XRDC_MRGD_W2_2_1_D0SEL_MASK)

#define XRDC_MRGD_W2_2_1_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_2_1_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_2_1_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_1_D1SEL_SHIFT)) & XRDC_MRGD_W2_2_1_D1SEL_MASK)

#define XRDC_MRGD_W2_2_1_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_2_1_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_2_1_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_1_D2SEL_SHIFT)) & XRDC_MRGD_W2_2_1_D2SEL_MASK)

#define XRDC_MRGD_W2_2_1_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_2_1_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_2_1_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_1_D3SEL_SHIFT)) & XRDC_MRGD_W2_2_1_D3SEL_MASK)

#define XRDC_MRGD_W2_2_1_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_2_1_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_2_1_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_1_D4SEL_SHIFT)) & XRDC_MRGD_W2_2_1_D4SEL_MASK)

#define XRDC_MRGD_W2_2_1_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_2_1_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_2_1_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_1_D5SEL_SHIFT)) & XRDC_MRGD_W2_2_1_D5SEL_MASK)

#define XRDC_MRGD_W2_2_1_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_2_1_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_2_1_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_1_D6SEL_SHIFT)) & XRDC_MRGD_W2_2_1_D6SEL_MASK)

#define XRDC_MRGD_W2_2_1_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_2_1_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_2_1_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_1_D7SEL_SHIFT)) & XRDC_MRGD_W2_2_1_D7SEL_MASK)

#define XRDC_MRGD_W2_2_1_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_2_1_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_2_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_1_EALO_SHIFT)) & XRDC_MRGD_W2_2_1_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_2_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_2_1_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_2_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_2_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_2_1_EAL_SHIFT)) & XRDC_MRGD_W3_2_1_EAL_MASK)

#define XRDC_MRGD_W3_2_1_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_2_1_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_2_1_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_2_1_CR_SHIFT)) & XRDC_MRGD_W3_2_1_CR_MASK)
/*! @} */

/*! @name MRGD_W4_2_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_2_1_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_2_1_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_2_1_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_1_ACCSET1_SHIFT)) & XRDC_MRGD_W4_2_1_ACCSET1_MASK)

#define XRDC_MRGD_W4_2_1_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_2_1_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_2_1_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_1_LKAS1_SHIFT)) & XRDC_MRGD_W4_2_1_LKAS1_MASK)

#define XRDC_MRGD_W4_2_1_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_2_1_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_2_1_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_1_ACCSET2_SHIFT)) & XRDC_MRGD_W4_2_1_ACCSET2_MASK)

#define XRDC_MRGD_W4_2_1_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_2_1_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_2_1_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_1_LKAS2_SHIFT)) & XRDC_MRGD_W4_2_1_LKAS2_MASK)

#define XRDC_MRGD_W4_2_1_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_2_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_2_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_1_LK2_SHIFT)) & XRDC_MRGD_W4_2_1_LK2_MASK)

#define XRDC_MRGD_W4_2_1_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_2_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_2_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_1_VLD_SHIFT)) & XRDC_MRGD_W4_2_1_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_2_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_2_2_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_2_2_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_2_2_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_2_2_SRTADDR_SHIFT)) & XRDC_MRGD_W0_2_2_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_2_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_2_2_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_2_2_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_2_2_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_2_2_ENDADDR_SHIFT)) & XRDC_MRGD_W1_2_2_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_2_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_2_2_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_2_2_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_2_2_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_2_D0SEL_SHIFT)) & XRDC_MRGD_W2_2_2_D0SEL_MASK)

#define XRDC_MRGD_W2_2_2_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_2_2_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_2_2_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_2_D1SEL_SHIFT)) & XRDC_MRGD_W2_2_2_D1SEL_MASK)

#define XRDC_MRGD_W2_2_2_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_2_2_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_2_2_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_2_D2SEL_SHIFT)) & XRDC_MRGD_W2_2_2_D2SEL_MASK)

#define XRDC_MRGD_W2_2_2_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_2_2_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_2_2_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_2_D3SEL_SHIFT)) & XRDC_MRGD_W2_2_2_D3SEL_MASK)

#define XRDC_MRGD_W2_2_2_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_2_2_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_2_2_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_2_D4SEL_SHIFT)) & XRDC_MRGD_W2_2_2_D4SEL_MASK)

#define XRDC_MRGD_W2_2_2_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_2_2_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_2_2_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_2_D5SEL_SHIFT)) & XRDC_MRGD_W2_2_2_D5SEL_MASK)

#define XRDC_MRGD_W2_2_2_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_2_2_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_2_2_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_2_D6SEL_SHIFT)) & XRDC_MRGD_W2_2_2_D6SEL_MASK)

#define XRDC_MRGD_W2_2_2_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_2_2_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_2_2_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_2_D7SEL_SHIFT)) & XRDC_MRGD_W2_2_2_D7SEL_MASK)

#define XRDC_MRGD_W2_2_2_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_2_2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_2_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_2_EALO_SHIFT)) & XRDC_MRGD_W2_2_2_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_2_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_2_2_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_2_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_2_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_2_2_EAL_SHIFT)) & XRDC_MRGD_W3_2_2_EAL_MASK)

#define XRDC_MRGD_W3_2_2_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_2_2_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_2_2_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_2_2_CR_SHIFT)) & XRDC_MRGD_W3_2_2_CR_MASK)
/*! @} */

/*! @name MRGD_W4_2_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_2_2_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_2_2_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_2_2_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_2_ACCSET1_SHIFT)) & XRDC_MRGD_W4_2_2_ACCSET1_MASK)

#define XRDC_MRGD_W4_2_2_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_2_2_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_2_2_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_2_LKAS1_SHIFT)) & XRDC_MRGD_W4_2_2_LKAS1_MASK)

#define XRDC_MRGD_W4_2_2_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_2_2_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_2_2_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_2_ACCSET2_SHIFT)) & XRDC_MRGD_W4_2_2_ACCSET2_MASK)

#define XRDC_MRGD_W4_2_2_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_2_2_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_2_2_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_2_LKAS2_SHIFT)) & XRDC_MRGD_W4_2_2_LKAS2_MASK)

#define XRDC_MRGD_W4_2_2_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_2_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_2_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_2_LK2_SHIFT)) & XRDC_MRGD_W4_2_2_LK2_MASK)

#define XRDC_MRGD_W4_2_2_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_2_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_2_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_2_VLD_SHIFT)) & XRDC_MRGD_W4_2_2_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_2_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_2_3_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_2_3_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_2_3_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_2_3_SRTADDR_SHIFT)) & XRDC_MRGD_W0_2_3_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_2_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_2_3_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_2_3_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_2_3_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_2_3_ENDADDR_SHIFT)) & XRDC_MRGD_W1_2_3_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_2_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_2_3_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_2_3_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_2_3_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_3_D0SEL_SHIFT)) & XRDC_MRGD_W2_2_3_D0SEL_MASK)

#define XRDC_MRGD_W2_2_3_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_2_3_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_2_3_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_3_D1SEL_SHIFT)) & XRDC_MRGD_W2_2_3_D1SEL_MASK)

#define XRDC_MRGD_W2_2_3_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_2_3_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_2_3_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_3_D2SEL_SHIFT)) & XRDC_MRGD_W2_2_3_D2SEL_MASK)

#define XRDC_MRGD_W2_2_3_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_2_3_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_2_3_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_3_D3SEL_SHIFT)) & XRDC_MRGD_W2_2_3_D3SEL_MASK)

#define XRDC_MRGD_W2_2_3_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_2_3_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_2_3_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_3_D4SEL_SHIFT)) & XRDC_MRGD_W2_2_3_D4SEL_MASK)

#define XRDC_MRGD_W2_2_3_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_2_3_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_2_3_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_3_D5SEL_SHIFT)) & XRDC_MRGD_W2_2_3_D5SEL_MASK)

#define XRDC_MRGD_W2_2_3_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_2_3_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_2_3_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_3_D6SEL_SHIFT)) & XRDC_MRGD_W2_2_3_D6SEL_MASK)

#define XRDC_MRGD_W2_2_3_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_2_3_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_2_3_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_3_D7SEL_SHIFT)) & XRDC_MRGD_W2_2_3_D7SEL_MASK)

#define XRDC_MRGD_W2_2_3_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_2_3_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_2_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_2_3_EALO_SHIFT)) & XRDC_MRGD_W2_2_3_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_2_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_2_3_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_2_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_2_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_2_3_EAL_SHIFT)) & XRDC_MRGD_W3_2_3_EAL_MASK)

#define XRDC_MRGD_W3_2_3_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_2_3_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_2_3_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_2_3_CR_SHIFT)) & XRDC_MRGD_W3_2_3_CR_MASK)
/*! @} */

/*! @name MRGD_W4_2_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_2_3_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_2_3_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_2_3_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_3_ACCSET1_SHIFT)) & XRDC_MRGD_W4_2_3_ACCSET1_MASK)

#define XRDC_MRGD_W4_2_3_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_2_3_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_2_3_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_3_LKAS1_SHIFT)) & XRDC_MRGD_W4_2_3_LKAS1_MASK)

#define XRDC_MRGD_W4_2_3_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_2_3_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_2_3_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_3_ACCSET2_SHIFT)) & XRDC_MRGD_W4_2_3_ACCSET2_MASK)

#define XRDC_MRGD_W4_2_3_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_2_3_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_2_3_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_3_LKAS2_SHIFT)) & XRDC_MRGD_W4_2_3_LKAS2_MASK)

#define XRDC_MRGD_W4_2_3_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_2_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_2_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_3_LK2_SHIFT)) & XRDC_MRGD_W4_2_3_LK2_MASK)

#define XRDC_MRGD_W4_2_3_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_2_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_2_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_2_3_VLD_SHIFT)) & XRDC_MRGD_W4_2_3_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_3_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_3_0_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_3_0_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_3_0_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_3_0_SRTADDR_SHIFT)) & XRDC_MRGD_W0_3_0_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_3_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_3_0_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_3_0_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_3_0_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_3_0_ENDADDR_SHIFT)) & XRDC_MRGD_W1_3_0_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_3_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_3_0_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_3_0_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_3_0_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_0_D0SEL_SHIFT)) & XRDC_MRGD_W2_3_0_D0SEL_MASK)

#define XRDC_MRGD_W2_3_0_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_3_0_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_3_0_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_0_D1SEL_SHIFT)) & XRDC_MRGD_W2_3_0_D1SEL_MASK)

#define XRDC_MRGD_W2_3_0_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_3_0_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_3_0_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_0_D2SEL_SHIFT)) & XRDC_MRGD_W2_3_0_D2SEL_MASK)

#define XRDC_MRGD_W2_3_0_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_3_0_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_3_0_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_0_D3SEL_SHIFT)) & XRDC_MRGD_W2_3_0_D3SEL_MASK)

#define XRDC_MRGD_W2_3_0_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_3_0_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_3_0_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_0_D4SEL_SHIFT)) & XRDC_MRGD_W2_3_0_D4SEL_MASK)

#define XRDC_MRGD_W2_3_0_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_3_0_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_3_0_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_0_D5SEL_SHIFT)) & XRDC_MRGD_W2_3_0_D5SEL_MASK)

#define XRDC_MRGD_W2_3_0_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_3_0_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_3_0_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_0_D6SEL_SHIFT)) & XRDC_MRGD_W2_3_0_D6SEL_MASK)

#define XRDC_MRGD_W2_3_0_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_3_0_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_3_0_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_0_D7SEL_SHIFT)) & XRDC_MRGD_W2_3_0_D7SEL_MASK)

#define XRDC_MRGD_W2_3_0_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_3_0_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_3_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_0_EALO_SHIFT)) & XRDC_MRGD_W2_3_0_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_3_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_3_0_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_3_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_3_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_3_0_EAL_SHIFT)) & XRDC_MRGD_W3_3_0_EAL_MASK)

#define XRDC_MRGD_W3_3_0_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_3_0_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_3_0_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_3_0_CR_SHIFT)) & XRDC_MRGD_W3_3_0_CR_MASK)
/*! @} */

/*! @name MRGD_W4_3_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_3_0_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_3_0_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_3_0_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_0_ACCSET1_SHIFT)) & XRDC_MRGD_W4_3_0_ACCSET1_MASK)

#define XRDC_MRGD_W4_3_0_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_3_0_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_3_0_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_0_LKAS1_SHIFT)) & XRDC_MRGD_W4_3_0_LKAS1_MASK)

#define XRDC_MRGD_W4_3_0_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_3_0_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_3_0_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_0_ACCSET2_SHIFT)) & XRDC_MRGD_W4_3_0_ACCSET2_MASK)

#define XRDC_MRGD_W4_3_0_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_3_0_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_3_0_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_0_LKAS2_SHIFT)) & XRDC_MRGD_W4_3_0_LKAS2_MASK)

#define XRDC_MRGD_W4_3_0_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_3_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_3_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_0_LK2_SHIFT)) & XRDC_MRGD_W4_3_0_LK2_MASK)

#define XRDC_MRGD_W4_3_0_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_3_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_3_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_0_VLD_SHIFT)) & XRDC_MRGD_W4_3_0_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_3_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_3_1_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_3_1_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_3_1_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_3_1_SRTADDR_SHIFT)) & XRDC_MRGD_W0_3_1_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_3_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_3_1_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_3_1_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_3_1_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_3_1_ENDADDR_SHIFT)) & XRDC_MRGD_W1_3_1_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_3_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_3_1_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_3_1_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_3_1_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_1_D0SEL_SHIFT)) & XRDC_MRGD_W2_3_1_D0SEL_MASK)

#define XRDC_MRGD_W2_3_1_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_3_1_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_3_1_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_1_D1SEL_SHIFT)) & XRDC_MRGD_W2_3_1_D1SEL_MASK)

#define XRDC_MRGD_W2_3_1_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_3_1_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_3_1_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_1_D2SEL_SHIFT)) & XRDC_MRGD_W2_3_1_D2SEL_MASK)

#define XRDC_MRGD_W2_3_1_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_3_1_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_3_1_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_1_D3SEL_SHIFT)) & XRDC_MRGD_W2_3_1_D3SEL_MASK)

#define XRDC_MRGD_W2_3_1_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_3_1_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_3_1_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_1_D4SEL_SHIFT)) & XRDC_MRGD_W2_3_1_D4SEL_MASK)

#define XRDC_MRGD_W2_3_1_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_3_1_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_3_1_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_1_D5SEL_SHIFT)) & XRDC_MRGD_W2_3_1_D5SEL_MASK)

#define XRDC_MRGD_W2_3_1_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_3_1_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_3_1_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_1_D6SEL_SHIFT)) & XRDC_MRGD_W2_3_1_D6SEL_MASK)

#define XRDC_MRGD_W2_3_1_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_3_1_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_3_1_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_1_D7SEL_SHIFT)) & XRDC_MRGD_W2_3_1_D7SEL_MASK)

#define XRDC_MRGD_W2_3_1_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_3_1_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_3_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_1_EALO_SHIFT)) & XRDC_MRGD_W2_3_1_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_3_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_3_1_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_3_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_3_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_3_1_EAL_SHIFT)) & XRDC_MRGD_W3_3_1_EAL_MASK)

#define XRDC_MRGD_W3_3_1_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_3_1_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_3_1_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_3_1_CR_SHIFT)) & XRDC_MRGD_W3_3_1_CR_MASK)
/*! @} */

/*! @name MRGD_W4_3_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_3_1_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_3_1_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_3_1_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_1_ACCSET1_SHIFT)) & XRDC_MRGD_W4_3_1_ACCSET1_MASK)

#define XRDC_MRGD_W4_3_1_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_3_1_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_3_1_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_1_LKAS1_SHIFT)) & XRDC_MRGD_W4_3_1_LKAS1_MASK)

#define XRDC_MRGD_W4_3_1_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_3_1_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_3_1_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_1_ACCSET2_SHIFT)) & XRDC_MRGD_W4_3_1_ACCSET2_MASK)

#define XRDC_MRGD_W4_3_1_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_3_1_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_3_1_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_1_LKAS2_SHIFT)) & XRDC_MRGD_W4_3_1_LKAS2_MASK)

#define XRDC_MRGD_W4_3_1_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_3_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_3_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_1_LK2_SHIFT)) & XRDC_MRGD_W4_3_1_LK2_MASK)

#define XRDC_MRGD_W4_3_1_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_3_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_3_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_1_VLD_SHIFT)) & XRDC_MRGD_W4_3_1_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_3_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_3_2_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_3_2_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_3_2_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_3_2_SRTADDR_SHIFT)) & XRDC_MRGD_W0_3_2_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_3_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_3_2_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_3_2_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_3_2_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_3_2_ENDADDR_SHIFT)) & XRDC_MRGD_W1_3_2_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_3_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_3_2_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_3_2_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_3_2_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_2_D0SEL_SHIFT)) & XRDC_MRGD_W2_3_2_D0SEL_MASK)

#define XRDC_MRGD_W2_3_2_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_3_2_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_3_2_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_2_D1SEL_SHIFT)) & XRDC_MRGD_W2_3_2_D1SEL_MASK)

#define XRDC_MRGD_W2_3_2_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_3_2_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_3_2_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_2_D2SEL_SHIFT)) & XRDC_MRGD_W2_3_2_D2SEL_MASK)

#define XRDC_MRGD_W2_3_2_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_3_2_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_3_2_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_2_D3SEL_SHIFT)) & XRDC_MRGD_W2_3_2_D3SEL_MASK)

#define XRDC_MRGD_W2_3_2_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_3_2_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_3_2_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_2_D4SEL_SHIFT)) & XRDC_MRGD_W2_3_2_D4SEL_MASK)

#define XRDC_MRGD_W2_3_2_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_3_2_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_3_2_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_2_D5SEL_SHIFT)) & XRDC_MRGD_W2_3_2_D5SEL_MASK)

#define XRDC_MRGD_W2_3_2_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_3_2_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_3_2_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_2_D6SEL_SHIFT)) & XRDC_MRGD_W2_3_2_D6SEL_MASK)

#define XRDC_MRGD_W2_3_2_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_3_2_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_3_2_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_2_D7SEL_SHIFT)) & XRDC_MRGD_W2_3_2_D7SEL_MASK)

#define XRDC_MRGD_W2_3_2_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_3_2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_3_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_2_EALO_SHIFT)) & XRDC_MRGD_W2_3_2_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_3_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_3_2_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_3_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_3_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_3_2_EAL_SHIFT)) & XRDC_MRGD_W3_3_2_EAL_MASK)

#define XRDC_MRGD_W3_3_2_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_3_2_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_3_2_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_3_2_CR_SHIFT)) & XRDC_MRGD_W3_3_2_CR_MASK)
/*! @} */

/*! @name MRGD_W4_3_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_3_2_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_3_2_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_3_2_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_2_ACCSET1_SHIFT)) & XRDC_MRGD_W4_3_2_ACCSET1_MASK)

#define XRDC_MRGD_W4_3_2_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_3_2_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_3_2_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_2_LKAS1_SHIFT)) & XRDC_MRGD_W4_3_2_LKAS1_MASK)

#define XRDC_MRGD_W4_3_2_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_3_2_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_3_2_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_2_ACCSET2_SHIFT)) & XRDC_MRGD_W4_3_2_ACCSET2_MASK)

#define XRDC_MRGD_W4_3_2_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_3_2_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_3_2_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_2_LKAS2_SHIFT)) & XRDC_MRGD_W4_3_2_LKAS2_MASK)

#define XRDC_MRGD_W4_3_2_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_3_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_3_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_2_LK2_SHIFT)) & XRDC_MRGD_W4_3_2_LK2_MASK)

#define XRDC_MRGD_W4_3_2_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_3_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_3_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_2_VLD_SHIFT)) & XRDC_MRGD_W4_3_2_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_3_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_3_3_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_3_3_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_3_3_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_3_3_SRTADDR_SHIFT)) & XRDC_MRGD_W0_3_3_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_3_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_3_3_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_3_3_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_3_3_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_3_3_ENDADDR_SHIFT)) & XRDC_MRGD_W1_3_3_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_3_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_3_3_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_3_3_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_3_3_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_3_D0SEL_SHIFT)) & XRDC_MRGD_W2_3_3_D0SEL_MASK)

#define XRDC_MRGD_W2_3_3_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_3_3_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_3_3_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_3_D1SEL_SHIFT)) & XRDC_MRGD_W2_3_3_D1SEL_MASK)

#define XRDC_MRGD_W2_3_3_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_3_3_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_3_3_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_3_D2SEL_SHIFT)) & XRDC_MRGD_W2_3_3_D2SEL_MASK)

#define XRDC_MRGD_W2_3_3_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_3_3_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_3_3_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_3_D3SEL_SHIFT)) & XRDC_MRGD_W2_3_3_D3SEL_MASK)

#define XRDC_MRGD_W2_3_3_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_3_3_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_3_3_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_3_D4SEL_SHIFT)) & XRDC_MRGD_W2_3_3_D4SEL_MASK)

#define XRDC_MRGD_W2_3_3_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_3_3_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_3_3_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_3_D5SEL_SHIFT)) & XRDC_MRGD_W2_3_3_D5SEL_MASK)

#define XRDC_MRGD_W2_3_3_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_3_3_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_3_3_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_3_D6SEL_SHIFT)) & XRDC_MRGD_W2_3_3_D6SEL_MASK)

#define XRDC_MRGD_W2_3_3_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_3_3_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_3_3_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_3_D7SEL_SHIFT)) & XRDC_MRGD_W2_3_3_D7SEL_MASK)

#define XRDC_MRGD_W2_3_3_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_3_3_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_3_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_3_3_EALO_SHIFT)) & XRDC_MRGD_W2_3_3_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_3_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_3_3_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_3_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_3_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_3_3_EAL_SHIFT)) & XRDC_MRGD_W3_3_3_EAL_MASK)

#define XRDC_MRGD_W3_3_3_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_3_3_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_3_3_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_3_3_CR_SHIFT)) & XRDC_MRGD_W3_3_3_CR_MASK)
/*! @} */

/*! @name MRGD_W4_3_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_3_3_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_3_3_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_3_3_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_3_ACCSET1_SHIFT)) & XRDC_MRGD_W4_3_3_ACCSET1_MASK)

#define XRDC_MRGD_W4_3_3_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_3_3_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_3_3_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_3_LKAS1_SHIFT)) & XRDC_MRGD_W4_3_3_LKAS1_MASK)

#define XRDC_MRGD_W4_3_3_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_3_3_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_3_3_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_3_ACCSET2_SHIFT)) & XRDC_MRGD_W4_3_3_ACCSET2_MASK)

#define XRDC_MRGD_W4_3_3_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_3_3_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_3_3_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_3_LKAS2_SHIFT)) & XRDC_MRGD_W4_3_3_LKAS2_MASK)

#define XRDC_MRGD_W4_3_3_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_3_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_3_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_3_LK2_SHIFT)) & XRDC_MRGD_W4_3_3_LK2_MASK)

#define XRDC_MRGD_W4_3_3_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_3_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_3_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_3_3_VLD_SHIFT)) & XRDC_MRGD_W4_3_3_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_4_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_4_0_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_4_0_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_4_0_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_4_0_SRTADDR_SHIFT)) & XRDC_MRGD_W0_4_0_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_4_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_4_0_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_4_0_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_4_0_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_4_0_ENDADDR_SHIFT)) & XRDC_MRGD_W1_4_0_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_4_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_4_0_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_4_0_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_4_0_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_0_D0SEL_SHIFT)) & XRDC_MRGD_W2_4_0_D0SEL_MASK)

#define XRDC_MRGD_W2_4_0_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_4_0_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_4_0_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_0_D1SEL_SHIFT)) & XRDC_MRGD_W2_4_0_D1SEL_MASK)

#define XRDC_MRGD_W2_4_0_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_4_0_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_4_0_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_0_D2SEL_SHIFT)) & XRDC_MRGD_W2_4_0_D2SEL_MASK)

#define XRDC_MRGD_W2_4_0_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_4_0_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_4_0_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_0_D3SEL_SHIFT)) & XRDC_MRGD_W2_4_0_D3SEL_MASK)

#define XRDC_MRGD_W2_4_0_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_4_0_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_4_0_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_0_D4SEL_SHIFT)) & XRDC_MRGD_W2_4_0_D4SEL_MASK)

#define XRDC_MRGD_W2_4_0_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_4_0_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_4_0_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_0_D5SEL_SHIFT)) & XRDC_MRGD_W2_4_0_D5SEL_MASK)

#define XRDC_MRGD_W2_4_0_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_4_0_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_4_0_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_0_D6SEL_SHIFT)) & XRDC_MRGD_W2_4_0_D6SEL_MASK)

#define XRDC_MRGD_W2_4_0_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_4_0_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_4_0_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_0_D7SEL_SHIFT)) & XRDC_MRGD_W2_4_0_D7SEL_MASK)

#define XRDC_MRGD_W2_4_0_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_4_0_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_4_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_0_EALO_SHIFT)) & XRDC_MRGD_W2_4_0_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_4_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_4_0_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_4_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_4_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_0_EAL_SHIFT)) & XRDC_MRGD_W3_4_0_EAL_MASK)

#define XRDC_MRGD_W3_4_0_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_4_0_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_4_0_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_0_CR_SHIFT)) & XRDC_MRGD_W3_4_0_CR_MASK)
/*! @} */

/*! @name MRGD_W4_4_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_4_0_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_4_0_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_4_0_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_0_ACCSET1_SHIFT)) & XRDC_MRGD_W4_4_0_ACCSET1_MASK)

#define XRDC_MRGD_W4_4_0_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_4_0_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_4_0_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_0_LKAS1_SHIFT)) & XRDC_MRGD_W4_4_0_LKAS1_MASK)

#define XRDC_MRGD_W4_4_0_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_4_0_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_4_0_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_0_ACCSET2_SHIFT)) & XRDC_MRGD_W4_4_0_ACCSET2_MASK)

#define XRDC_MRGD_W4_4_0_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_4_0_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_4_0_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_0_LKAS2_SHIFT)) & XRDC_MRGD_W4_4_0_LKAS2_MASK)

#define XRDC_MRGD_W4_4_0_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_4_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_4_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_0_LK2_SHIFT)) & XRDC_MRGD_W4_4_0_LK2_MASK)

#define XRDC_MRGD_W4_4_0_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_4_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_4_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_0_VLD_SHIFT)) & XRDC_MRGD_W4_4_0_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_4_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_4_1_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_4_1_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_4_1_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_4_1_SRTADDR_SHIFT)) & XRDC_MRGD_W0_4_1_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_4_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_4_1_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_4_1_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_4_1_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_4_1_ENDADDR_SHIFT)) & XRDC_MRGD_W1_4_1_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_4_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_4_1_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_4_1_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_4_1_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_1_D0SEL_SHIFT)) & XRDC_MRGD_W2_4_1_D0SEL_MASK)

#define XRDC_MRGD_W2_4_1_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_4_1_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_4_1_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_1_D1SEL_SHIFT)) & XRDC_MRGD_W2_4_1_D1SEL_MASK)

#define XRDC_MRGD_W2_4_1_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_4_1_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_4_1_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_1_D2SEL_SHIFT)) & XRDC_MRGD_W2_4_1_D2SEL_MASK)

#define XRDC_MRGD_W2_4_1_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_4_1_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_4_1_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_1_D3SEL_SHIFT)) & XRDC_MRGD_W2_4_1_D3SEL_MASK)

#define XRDC_MRGD_W2_4_1_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_4_1_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_4_1_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_1_D4SEL_SHIFT)) & XRDC_MRGD_W2_4_1_D4SEL_MASK)

#define XRDC_MRGD_W2_4_1_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_4_1_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_4_1_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_1_D5SEL_SHIFT)) & XRDC_MRGD_W2_4_1_D5SEL_MASK)

#define XRDC_MRGD_W2_4_1_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_4_1_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_4_1_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_1_D6SEL_SHIFT)) & XRDC_MRGD_W2_4_1_D6SEL_MASK)

#define XRDC_MRGD_W2_4_1_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_4_1_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_4_1_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_1_D7SEL_SHIFT)) & XRDC_MRGD_W2_4_1_D7SEL_MASK)

#define XRDC_MRGD_W2_4_1_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_4_1_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_4_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_1_EALO_SHIFT)) & XRDC_MRGD_W2_4_1_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_4_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_4_1_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_4_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_4_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_1_EAL_SHIFT)) & XRDC_MRGD_W3_4_1_EAL_MASK)

#define XRDC_MRGD_W3_4_1_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_4_1_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_4_1_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_1_CR_SHIFT)) & XRDC_MRGD_W3_4_1_CR_MASK)
/*! @} */

/*! @name MRGD_W4_4_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_4_1_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_4_1_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_4_1_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_1_ACCSET1_SHIFT)) & XRDC_MRGD_W4_4_1_ACCSET1_MASK)

#define XRDC_MRGD_W4_4_1_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_4_1_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_4_1_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_1_LKAS1_SHIFT)) & XRDC_MRGD_W4_4_1_LKAS1_MASK)

#define XRDC_MRGD_W4_4_1_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_4_1_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_4_1_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_1_ACCSET2_SHIFT)) & XRDC_MRGD_W4_4_1_ACCSET2_MASK)

#define XRDC_MRGD_W4_4_1_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_4_1_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_4_1_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_1_LKAS2_SHIFT)) & XRDC_MRGD_W4_4_1_LKAS2_MASK)

#define XRDC_MRGD_W4_4_1_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_4_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_4_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_1_LK2_SHIFT)) & XRDC_MRGD_W4_4_1_LK2_MASK)

#define XRDC_MRGD_W4_4_1_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_4_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_4_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_1_VLD_SHIFT)) & XRDC_MRGD_W4_4_1_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_4_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_4_2_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_4_2_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_4_2_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_4_2_SRTADDR_SHIFT)) & XRDC_MRGD_W0_4_2_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_4_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_4_2_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_4_2_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_4_2_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_4_2_ENDADDR_SHIFT)) & XRDC_MRGD_W1_4_2_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_4_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_4_2_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_4_2_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_4_2_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_2_D0SEL_SHIFT)) & XRDC_MRGD_W2_4_2_D0SEL_MASK)

#define XRDC_MRGD_W2_4_2_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_4_2_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_4_2_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_2_D1SEL_SHIFT)) & XRDC_MRGD_W2_4_2_D1SEL_MASK)

#define XRDC_MRGD_W2_4_2_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_4_2_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_4_2_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_2_D2SEL_SHIFT)) & XRDC_MRGD_W2_4_2_D2SEL_MASK)

#define XRDC_MRGD_W2_4_2_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_4_2_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_4_2_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_2_D3SEL_SHIFT)) & XRDC_MRGD_W2_4_2_D3SEL_MASK)

#define XRDC_MRGD_W2_4_2_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_4_2_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_4_2_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_2_D4SEL_SHIFT)) & XRDC_MRGD_W2_4_2_D4SEL_MASK)

#define XRDC_MRGD_W2_4_2_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_4_2_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_4_2_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_2_D5SEL_SHIFT)) & XRDC_MRGD_W2_4_2_D5SEL_MASK)

#define XRDC_MRGD_W2_4_2_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_4_2_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_4_2_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_2_D6SEL_SHIFT)) & XRDC_MRGD_W2_4_2_D6SEL_MASK)

#define XRDC_MRGD_W2_4_2_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_4_2_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_4_2_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_2_D7SEL_SHIFT)) & XRDC_MRGD_W2_4_2_D7SEL_MASK)

#define XRDC_MRGD_W2_4_2_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_4_2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_4_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_2_EALO_SHIFT)) & XRDC_MRGD_W2_4_2_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_4_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_4_2_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_4_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_4_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_2_EAL_SHIFT)) & XRDC_MRGD_W3_4_2_EAL_MASK)

#define XRDC_MRGD_W3_4_2_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_4_2_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_4_2_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_2_CR_SHIFT)) & XRDC_MRGD_W3_4_2_CR_MASK)
/*! @} */

/*! @name MRGD_W4_4_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_4_2_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_4_2_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_4_2_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_2_ACCSET1_SHIFT)) & XRDC_MRGD_W4_4_2_ACCSET1_MASK)

#define XRDC_MRGD_W4_4_2_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_4_2_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_4_2_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_2_LKAS1_SHIFT)) & XRDC_MRGD_W4_4_2_LKAS1_MASK)

#define XRDC_MRGD_W4_4_2_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_4_2_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_4_2_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_2_ACCSET2_SHIFT)) & XRDC_MRGD_W4_4_2_ACCSET2_MASK)

#define XRDC_MRGD_W4_4_2_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_4_2_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_4_2_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_2_LKAS2_SHIFT)) & XRDC_MRGD_W4_4_2_LKAS2_MASK)

#define XRDC_MRGD_W4_4_2_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_4_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_4_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_2_LK2_SHIFT)) & XRDC_MRGD_W4_4_2_LK2_MASK)

#define XRDC_MRGD_W4_4_2_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_4_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_4_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_2_VLD_SHIFT)) & XRDC_MRGD_W4_4_2_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_4_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_4_3_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_4_3_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_4_3_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_4_3_SRTADDR_SHIFT)) & XRDC_MRGD_W0_4_3_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_4_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_4_3_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_4_3_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_4_3_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_4_3_ENDADDR_SHIFT)) & XRDC_MRGD_W1_4_3_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_4_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_4_3_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_4_3_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_4_3_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_3_D0SEL_SHIFT)) & XRDC_MRGD_W2_4_3_D0SEL_MASK)

#define XRDC_MRGD_W2_4_3_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_4_3_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_4_3_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_3_D1SEL_SHIFT)) & XRDC_MRGD_W2_4_3_D1SEL_MASK)

#define XRDC_MRGD_W2_4_3_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_4_3_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_4_3_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_3_D2SEL_SHIFT)) & XRDC_MRGD_W2_4_3_D2SEL_MASK)

#define XRDC_MRGD_W2_4_3_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_4_3_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_4_3_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_3_D3SEL_SHIFT)) & XRDC_MRGD_W2_4_3_D3SEL_MASK)

#define XRDC_MRGD_W2_4_3_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_4_3_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_4_3_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_3_D4SEL_SHIFT)) & XRDC_MRGD_W2_4_3_D4SEL_MASK)

#define XRDC_MRGD_W2_4_3_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_4_3_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_4_3_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_3_D5SEL_SHIFT)) & XRDC_MRGD_W2_4_3_D5SEL_MASK)

#define XRDC_MRGD_W2_4_3_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_4_3_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_4_3_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_3_D6SEL_SHIFT)) & XRDC_MRGD_W2_4_3_D6SEL_MASK)

#define XRDC_MRGD_W2_4_3_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_4_3_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_4_3_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_3_D7SEL_SHIFT)) & XRDC_MRGD_W2_4_3_D7SEL_MASK)

#define XRDC_MRGD_W2_4_3_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_4_3_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_4_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_3_EALO_SHIFT)) & XRDC_MRGD_W2_4_3_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_4_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_4_3_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_4_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_4_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_3_EAL_SHIFT)) & XRDC_MRGD_W3_4_3_EAL_MASK)

#define XRDC_MRGD_W3_4_3_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_4_3_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_4_3_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_3_CR_SHIFT)) & XRDC_MRGD_W3_4_3_CR_MASK)
/*! @} */

/*! @name MRGD_W4_4_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_4_3_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_4_3_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_4_3_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_3_ACCSET1_SHIFT)) & XRDC_MRGD_W4_4_3_ACCSET1_MASK)

#define XRDC_MRGD_W4_4_3_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_4_3_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_4_3_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_3_LKAS1_SHIFT)) & XRDC_MRGD_W4_4_3_LKAS1_MASK)

#define XRDC_MRGD_W4_4_3_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_4_3_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_4_3_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_3_ACCSET2_SHIFT)) & XRDC_MRGD_W4_4_3_ACCSET2_MASK)

#define XRDC_MRGD_W4_4_3_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_4_3_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_4_3_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_3_LKAS2_SHIFT)) & XRDC_MRGD_W4_4_3_LKAS2_MASK)

#define XRDC_MRGD_W4_4_3_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_4_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_4_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_3_LK2_SHIFT)) & XRDC_MRGD_W4_4_3_LK2_MASK)

#define XRDC_MRGD_W4_4_3_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_4_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_4_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_3_VLD_SHIFT)) & XRDC_MRGD_W4_4_3_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_4_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_4_4_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_4_4_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_4_4_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_4_4_SRTADDR_SHIFT)) & XRDC_MRGD_W0_4_4_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_4_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_4_4_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_4_4_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_4_4_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_4_4_ENDADDR_SHIFT)) & XRDC_MRGD_W1_4_4_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_4_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_4_4_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_4_4_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_4_4_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_4_D0SEL_SHIFT)) & XRDC_MRGD_W2_4_4_D0SEL_MASK)

#define XRDC_MRGD_W2_4_4_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_4_4_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_4_4_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_4_D1SEL_SHIFT)) & XRDC_MRGD_W2_4_4_D1SEL_MASK)

#define XRDC_MRGD_W2_4_4_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_4_4_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_4_4_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_4_D2SEL_SHIFT)) & XRDC_MRGD_W2_4_4_D2SEL_MASK)

#define XRDC_MRGD_W2_4_4_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_4_4_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_4_4_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_4_D3SEL_SHIFT)) & XRDC_MRGD_W2_4_4_D3SEL_MASK)

#define XRDC_MRGD_W2_4_4_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_4_4_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_4_4_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_4_D4SEL_SHIFT)) & XRDC_MRGD_W2_4_4_D4SEL_MASK)

#define XRDC_MRGD_W2_4_4_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_4_4_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_4_4_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_4_D5SEL_SHIFT)) & XRDC_MRGD_W2_4_4_D5SEL_MASK)

#define XRDC_MRGD_W2_4_4_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_4_4_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_4_4_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_4_D6SEL_SHIFT)) & XRDC_MRGD_W2_4_4_D6SEL_MASK)

#define XRDC_MRGD_W2_4_4_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_4_4_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_4_4_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_4_D7SEL_SHIFT)) & XRDC_MRGD_W2_4_4_D7SEL_MASK)

#define XRDC_MRGD_W2_4_4_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_4_4_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_4_4_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_4_EALO_SHIFT)) & XRDC_MRGD_W2_4_4_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_4_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_4_4_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_4_4_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_4_4_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_4_EAL_SHIFT)) & XRDC_MRGD_W3_4_4_EAL_MASK)

#define XRDC_MRGD_W3_4_4_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_4_4_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_4_4_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_4_CR_SHIFT)) & XRDC_MRGD_W3_4_4_CR_MASK)
/*! @} */

/*! @name MRGD_W4_4_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_4_4_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_4_4_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_4_4_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_4_ACCSET1_SHIFT)) & XRDC_MRGD_W4_4_4_ACCSET1_MASK)

#define XRDC_MRGD_W4_4_4_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_4_4_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_4_4_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_4_LKAS1_SHIFT)) & XRDC_MRGD_W4_4_4_LKAS1_MASK)

#define XRDC_MRGD_W4_4_4_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_4_4_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_4_4_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_4_ACCSET2_SHIFT)) & XRDC_MRGD_W4_4_4_ACCSET2_MASK)

#define XRDC_MRGD_W4_4_4_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_4_4_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_4_4_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_4_LKAS2_SHIFT)) & XRDC_MRGD_W4_4_4_LKAS2_MASK)

#define XRDC_MRGD_W4_4_4_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_4_4_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_4_4_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_4_LK2_SHIFT)) & XRDC_MRGD_W4_4_4_LK2_MASK)

#define XRDC_MRGD_W4_4_4_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_4_4_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_4_4_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_4_VLD_SHIFT)) & XRDC_MRGD_W4_4_4_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_4_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_4_5_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_4_5_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_4_5_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_4_5_SRTADDR_SHIFT)) & XRDC_MRGD_W0_4_5_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_4_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_4_5_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_4_5_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_4_5_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_4_5_ENDADDR_SHIFT)) & XRDC_MRGD_W1_4_5_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_4_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_4_5_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_4_5_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_4_5_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_5_D0SEL_SHIFT)) & XRDC_MRGD_W2_4_5_D0SEL_MASK)

#define XRDC_MRGD_W2_4_5_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_4_5_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_4_5_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_5_D1SEL_SHIFT)) & XRDC_MRGD_W2_4_5_D1SEL_MASK)

#define XRDC_MRGD_W2_4_5_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_4_5_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_4_5_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_5_D2SEL_SHIFT)) & XRDC_MRGD_W2_4_5_D2SEL_MASK)

#define XRDC_MRGD_W2_4_5_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_4_5_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_4_5_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_5_D3SEL_SHIFT)) & XRDC_MRGD_W2_4_5_D3SEL_MASK)

#define XRDC_MRGD_W2_4_5_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_4_5_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_4_5_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_5_D4SEL_SHIFT)) & XRDC_MRGD_W2_4_5_D4SEL_MASK)

#define XRDC_MRGD_W2_4_5_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_4_5_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_4_5_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_5_D5SEL_SHIFT)) & XRDC_MRGD_W2_4_5_D5SEL_MASK)

#define XRDC_MRGD_W2_4_5_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_4_5_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_4_5_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_5_D6SEL_SHIFT)) & XRDC_MRGD_W2_4_5_D6SEL_MASK)

#define XRDC_MRGD_W2_4_5_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_4_5_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_4_5_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_5_D7SEL_SHIFT)) & XRDC_MRGD_W2_4_5_D7SEL_MASK)

#define XRDC_MRGD_W2_4_5_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_4_5_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_4_5_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_5_EALO_SHIFT)) & XRDC_MRGD_W2_4_5_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_4_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_4_5_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_4_5_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_4_5_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_5_EAL_SHIFT)) & XRDC_MRGD_W3_4_5_EAL_MASK)

#define XRDC_MRGD_W3_4_5_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_4_5_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_4_5_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_5_CR_SHIFT)) & XRDC_MRGD_W3_4_5_CR_MASK)
/*! @} */

/*! @name MRGD_W4_4_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_4_5_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_4_5_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_4_5_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_5_ACCSET1_SHIFT)) & XRDC_MRGD_W4_4_5_ACCSET1_MASK)

#define XRDC_MRGD_W4_4_5_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_4_5_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_4_5_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_5_LKAS1_SHIFT)) & XRDC_MRGD_W4_4_5_LKAS1_MASK)

#define XRDC_MRGD_W4_4_5_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_4_5_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_4_5_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_5_ACCSET2_SHIFT)) & XRDC_MRGD_W4_4_5_ACCSET2_MASK)

#define XRDC_MRGD_W4_4_5_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_4_5_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_4_5_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_5_LKAS2_SHIFT)) & XRDC_MRGD_W4_4_5_LKAS2_MASK)

#define XRDC_MRGD_W4_4_5_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_4_5_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_4_5_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_5_LK2_SHIFT)) & XRDC_MRGD_W4_4_5_LK2_MASK)

#define XRDC_MRGD_W4_4_5_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_4_5_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_4_5_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_5_VLD_SHIFT)) & XRDC_MRGD_W4_4_5_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_4_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_4_6_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_4_6_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_4_6_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_4_6_SRTADDR_SHIFT)) & XRDC_MRGD_W0_4_6_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_4_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_4_6_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_4_6_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_4_6_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_4_6_ENDADDR_SHIFT)) & XRDC_MRGD_W1_4_6_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_4_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_4_6_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_4_6_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_4_6_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_6_D0SEL_SHIFT)) & XRDC_MRGD_W2_4_6_D0SEL_MASK)

#define XRDC_MRGD_W2_4_6_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_4_6_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_4_6_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_6_D1SEL_SHIFT)) & XRDC_MRGD_W2_4_6_D1SEL_MASK)

#define XRDC_MRGD_W2_4_6_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_4_6_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_4_6_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_6_D2SEL_SHIFT)) & XRDC_MRGD_W2_4_6_D2SEL_MASK)

#define XRDC_MRGD_W2_4_6_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_4_6_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_4_6_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_6_D3SEL_SHIFT)) & XRDC_MRGD_W2_4_6_D3SEL_MASK)

#define XRDC_MRGD_W2_4_6_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_4_6_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_4_6_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_6_D4SEL_SHIFT)) & XRDC_MRGD_W2_4_6_D4SEL_MASK)

#define XRDC_MRGD_W2_4_6_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_4_6_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_4_6_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_6_D5SEL_SHIFT)) & XRDC_MRGD_W2_4_6_D5SEL_MASK)

#define XRDC_MRGD_W2_4_6_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_4_6_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_4_6_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_6_D6SEL_SHIFT)) & XRDC_MRGD_W2_4_6_D6SEL_MASK)

#define XRDC_MRGD_W2_4_6_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_4_6_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_4_6_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_6_D7SEL_SHIFT)) & XRDC_MRGD_W2_4_6_D7SEL_MASK)

#define XRDC_MRGD_W2_4_6_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_4_6_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_4_6_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_6_EALO_SHIFT)) & XRDC_MRGD_W2_4_6_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_4_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_4_6_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_4_6_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_4_6_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_6_EAL_SHIFT)) & XRDC_MRGD_W3_4_6_EAL_MASK)

#define XRDC_MRGD_W3_4_6_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_4_6_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_4_6_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_6_CR_SHIFT)) & XRDC_MRGD_W3_4_6_CR_MASK)
/*! @} */

/*! @name MRGD_W4_4_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_4_6_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_4_6_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_4_6_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_6_ACCSET1_SHIFT)) & XRDC_MRGD_W4_4_6_ACCSET1_MASK)

#define XRDC_MRGD_W4_4_6_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_4_6_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_4_6_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_6_LKAS1_SHIFT)) & XRDC_MRGD_W4_4_6_LKAS1_MASK)

#define XRDC_MRGD_W4_4_6_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_4_6_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_4_6_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_6_ACCSET2_SHIFT)) & XRDC_MRGD_W4_4_6_ACCSET2_MASK)

#define XRDC_MRGD_W4_4_6_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_4_6_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_4_6_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_6_LKAS2_SHIFT)) & XRDC_MRGD_W4_4_6_LKAS2_MASK)

#define XRDC_MRGD_W4_4_6_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_4_6_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_4_6_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_6_LK2_SHIFT)) & XRDC_MRGD_W4_4_6_LK2_MASK)

#define XRDC_MRGD_W4_4_6_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_4_6_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_4_6_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_6_VLD_SHIFT)) & XRDC_MRGD_W4_4_6_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_4_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_4_7_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_4_7_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_4_7_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_4_7_SRTADDR_SHIFT)) & XRDC_MRGD_W0_4_7_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_4_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_4_7_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_4_7_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_4_7_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_4_7_ENDADDR_SHIFT)) & XRDC_MRGD_W1_4_7_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_4_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_4_7_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_4_7_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_4_7_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_7_D0SEL_SHIFT)) & XRDC_MRGD_W2_4_7_D0SEL_MASK)

#define XRDC_MRGD_W2_4_7_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_4_7_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_4_7_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_7_D1SEL_SHIFT)) & XRDC_MRGD_W2_4_7_D1SEL_MASK)

#define XRDC_MRGD_W2_4_7_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_4_7_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_4_7_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_7_D2SEL_SHIFT)) & XRDC_MRGD_W2_4_7_D2SEL_MASK)

#define XRDC_MRGD_W2_4_7_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_4_7_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_4_7_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_7_D3SEL_SHIFT)) & XRDC_MRGD_W2_4_7_D3SEL_MASK)

#define XRDC_MRGD_W2_4_7_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_4_7_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_4_7_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_7_D4SEL_SHIFT)) & XRDC_MRGD_W2_4_7_D4SEL_MASK)

#define XRDC_MRGD_W2_4_7_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_4_7_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_4_7_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_7_D5SEL_SHIFT)) & XRDC_MRGD_W2_4_7_D5SEL_MASK)

#define XRDC_MRGD_W2_4_7_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_4_7_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_4_7_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_7_D6SEL_SHIFT)) & XRDC_MRGD_W2_4_7_D6SEL_MASK)

#define XRDC_MRGD_W2_4_7_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_4_7_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_4_7_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_7_D7SEL_SHIFT)) & XRDC_MRGD_W2_4_7_D7SEL_MASK)

#define XRDC_MRGD_W2_4_7_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_4_7_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_4_7_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_4_7_EALO_SHIFT)) & XRDC_MRGD_W2_4_7_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_4_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_4_7_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_4_7_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_4_7_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_7_EAL_SHIFT)) & XRDC_MRGD_W3_4_7_EAL_MASK)

#define XRDC_MRGD_W3_4_7_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_4_7_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_4_7_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_4_7_CR_SHIFT)) & XRDC_MRGD_W3_4_7_CR_MASK)
/*! @} */

/*! @name MRGD_W4_4_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_4_7_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_4_7_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_4_7_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_7_ACCSET1_SHIFT)) & XRDC_MRGD_W4_4_7_ACCSET1_MASK)

#define XRDC_MRGD_W4_4_7_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_4_7_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_4_7_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_7_LKAS1_SHIFT)) & XRDC_MRGD_W4_4_7_LKAS1_MASK)

#define XRDC_MRGD_W4_4_7_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_4_7_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_4_7_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_7_ACCSET2_SHIFT)) & XRDC_MRGD_W4_4_7_ACCSET2_MASK)

#define XRDC_MRGD_W4_4_7_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_4_7_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_4_7_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_7_LKAS2_SHIFT)) & XRDC_MRGD_W4_4_7_LKAS2_MASK)

#define XRDC_MRGD_W4_4_7_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_4_7_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_4_7_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_7_LK2_SHIFT)) & XRDC_MRGD_W4_4_7_LK2_MASK)

#define XRDC_MRGD_W4_4_7_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_4_7_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_4_7_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_4_7_VLD_SHIFT)) & XRDC_MRGD_W4_4_7_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_5_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_5_0_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_5_0_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_5_0_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_5_0_SRTADDR_SHIFT)) & XRDC_MRGD_W0_5_0_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_5_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_5_0_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_5_0_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_5_0_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_5_0_ENDADDR_SHIFT)) & XRDC_MRGD_W1_5_0_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_5_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_5_0_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_5_0_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_5_0_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_0_D0SEL_SHIFT)) & XRDC_MRGD_W2_5_0_D0SEL_MASK)

#define XRDC_MRGD_W2_5_0_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_5_0_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_5_0_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_0_D1SEL_SHIFT)) & XRDC_MRGD_W2_5_0_D1SEL_MASK)

#define XRDC_MRGD_W2_5_0_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_5_0_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_5_0_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_0_D2SEL_SHIFT)) & XRDC_MRGD_W2_5_0_D2SEL_MASK)

#define XRDC_MRGD_W2_5_0_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_5_0_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_5_0_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_0_D3SEL_SHIFT)) & XRDC_MRGD_W2_5_0_D3SEL_MASK)

#define XRDC_MRGD_W2_5_0_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_5_0_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_5_0_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_0_D4SEL_SHIFT)) & XRDC_MRGD_W2_5_0_D4SEL_MASK)

#define XRDC_MRGD_W2_5_0_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_5_0_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_5_0_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_0_D5SEL_SHIFT)) & XRDC_MRGD_W2_5_0_D5SEL_MASK)

#define XRDC_MRGD_W2_5_0_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_5_0_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_5_0_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_0_D6SEL_SHIFT)) & XRDC_MRGD_W2_5_0_D6SEL_MASK)

#define XRDC_MRGD_W2_5_0_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_5_0_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_5_0_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_0_D7SEL_SHIFT)) & XRDC_MRGD_W2_5_0_D7SEL_MASK)

#define XRDC_MRGD_W2_5_0_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_5_0_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_5_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_0_EALO_SHIFT)) & XRDC_MRGD_W2_5_0_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_5_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_5_0_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_5_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_5_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_0_EAL_SHIFT)) & XRDC_MRGD_W3_5_0_EAL_MASK)

#define XRDC_MRGD_W3_5_0_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_5_0_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_5_0_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_0_CR_SHIFT)) & XRDC_MRGD_W3_5_0_CR_MASK)
/*! @} */

/*! @name MRGD_W4_5_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_5_0_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_5_0_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_5_0_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_0_ACCSET1_SHIFT)) & XRDC_MRGD_W4_5_0_ACCSET1_MASK)

#define XRDC_MRGD_W4_5_0_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_5_0_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_5_0_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_0_LKAS1_SHIFT)) & XRDC_MRGD_W4_5_0_LKAS1_MASK)

#define XRDC_MRGD_W4_5_0_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_5_0_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_5_0_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_0_ACCSET2_SHIFT)) & XRDC_MRGD_W4_5_0_ACCSET2_MASK)

#define XRDC_MRGD_W4_5_0_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_5_0_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_5_0_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_0_LKAS2_SHIFT)) & XRDC_MRGD_W4_5_0_LKAS2_MASK)

#define XRDC_MRGD_W4_5_0_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_5_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_5_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_0_LK2_SHIFT)) & XRDC_MRGD_W4_5_0_LK2_MASK)

#define XRDC_MRGD_W4_5_0_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_5_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_5_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_0_VLD_SHIFT)) & XRDC_MRGD_W4_5_0_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_5_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_5_1_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_5_1_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_5_1_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_5_1_SRTADDR_SHIFT)) & XRDC_MRGD_W0_5_1_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_5_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_5_1_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_5_1_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_5_1_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_5_1_ENDADDR_SHIFT)) & XRDC_MRGD_W1_5_1_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_5_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_5_1_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_5_1_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_5_1_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_1_D0SEL_SHIFT)) & XRDC_MRGD_W2_5_1_D0SEL_MASK)

#define XRDC_MRGD_W2_5_1_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_5_1_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_5_1_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_1_D1SEL_SHIFT)) & XRDC_MRGD_W2_5_1_D1SEL_MASK)

#define XRDC_MRGD_W2_5_1_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_5_1_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_5_1_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_1_D2SEL_SHIFT)) & XRDC_MRGD_W2_5_1_D2SEL_MASK)

#define XRDC_MRGD_W2_5_1_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_5_1_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_5_1_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_1_D3SEL_SHIFT)) & XRDC_MRGD_W2_5_1_D3SEL_MASK)

#define XRDC_MRGD_W2_5_1_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_5_1_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_5_1_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_1_D4SEL_SHIFT)) & XRDC_MRGD_W2_5_1_D4SEL_MASK)

#define XRDC_MRGD_W2_5_1_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_5_1_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_5_1_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_1_D5SEL_SHIFT)) & XRDC_MRGD_W2_5_1_D5SEL_MASK)

#define XRDC_MRGD_W2_5_1_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_5_1_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_5_1_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_1_D6SEL_SHIFT)) & XRDC_MRGD_W2_5_1_D6SEL_MASK)

#define XRDC_MRGD_W2_5_1_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_5_1_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_5_1_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_1_D7SEL_SHIFT)) & XRDC_MRGD_W2_5_1_D7SEL_MASK)

#define XRDC_MRGD_W2_5_1_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_5_1_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_5_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_1_EALO_SHIFT)) & XRDC_MRGD_W2_5_1_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_5_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_5_1_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_5_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_5_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_1_EAL_SHIFT)) & XRDC_MRGD_W3_5_1_EAL_MASK)

#define XRDC_MRGD_W3_5_1_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_5_1_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_5_1_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_1_CR_SHIFT)) & XRDC_MRGD_W3_5_1_CR_MASK)
/*! @} */

/*! @name MRGD_W4_5_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_5_1_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_5_1_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_5_1_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_1_ACCSET1_SHIFT)) & XRDC_MRGD_W4_5_1_ACCSET1_MASK)

#define XRDC_MRGD_W4_5_1_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_5_1_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_5_1_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_1_LKAS1_SHIFT)) & XRDC_MRGD_W4_5_1_LKAS1_MASK)

#define XRDC_MRGD_W4_5_1_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_5_1_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_5_1_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_1_ACCSET2_SHIFT)) & XRDC_MRGD_W4_5_1_ACCSET2_MASK)

#define XRDC_MRGD_W4_5_1_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_5_1_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_5_1_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_1_LKAS2_SHIFT)) & XRDC_MRGD_W4_5_1_LKAS2_MASK)

#define XRDC_MRGD_W4_5_1_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_5_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_5_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_1_LK2_SHIFT)) & XRDC_MRGD_W4_5_1_LK2_MASK)

#define XRDC_MRGD_W4_5_1_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_5_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_5_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_1_VLD_SHIFT)) & XRDC_MRGD_W4_5_1_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_5_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_5_2_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_5_2_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_5_2_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_5_2_SRTADDR_SHIFT)) & XRDC_MRGD_W0_5_2_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_5_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_5_2_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_5_2_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_5_2_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_5_2_ENDADDR_SHIFT)) & XRDC_MRGD_W1_5_2_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_5_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_5_2_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_5_2_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_5_2_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_2_D0SEL_SHIFT)) & XRDC_MRGD_W2_5_2_D0SEL_MASK)

#define XRDC_MRGD_W2_5_2_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_5_2_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_5_2_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_2_D1SEL_SHIFT)) & XRDC_MRGD_W2_5_2_D1SEL_MASK)

#define XRDC_MRGD_W2_5_2_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_5_2_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_5_2_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_2_D2SEL_SHIFT)) & XRDC_MRGD_W2_5_2_D2SEL_MASK)

#define XRDC_MRGD_W2_5_2_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_5_2_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_5_2_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_2_D3SEL_SHIFT)) & XRDC_MRGD_W2_5_2_D3SEL_MASK)

#define XRDC_MRGD_W2_5_2_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_5_2_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_5_2_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_2_D4SEL_SHIFT)) & XRDC_MRGD_W2_5_2_D4SEL_MASK)

#define XRDC_MRGD_W2_5_2_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_5_2_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_5_2_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_2_D5SEL_SHIFT)) & XRDC_MRGD_W2_5_2_D5SEL_MASK)

#define XRDC_MRGD_W2_5_2_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_5_2_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_5_2_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_2_D6SEL_SHIFT)) & XRDC_MRGD_W2_5_2_D6SEL_MASK)

#define XRDC_MRGD_W2_5_2_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_5_2_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_5_2_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_2_D7SEL_SHIFT)) & XRDC_MRGD_W2_5_2_D7SEL_MASK)

#define XRDC_MRGD_W2_5_2_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_5_2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_5_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_2_EALO_SHIFT)) & XRDC_MRGD_W2_5_2_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_5_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_5_2_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_5_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_5_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_2_EAL_SHIFT)) & XRDC_MRGD_W3_5_2_EAL_MASK)

#define XRDC_MRGD_W3_5_2_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_5_2_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_5_2_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_2_CR_SHIFT)) & XRDC_MRGD_W3_5_2_CR_MASK)
/*! @} */

/*! @name MRGD_W4_5_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_5_2_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_5_2_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_5_2_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_2_ACCSET1_SHIFT)) & XRDC_MRGD_W4_5_2_ACCSET1_MASK)

#define XRDC_MRGD_W4_5_2_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_5_2_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_5_2_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_2_LKAS1_SHIFT)) & XRDC_MRGD_W4_5_2_LKAS1_MASK)

#define XRDC_MRGD_W4_5_2_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_5_2_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_5_2_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_2_ACCSET2_SHIFT)) & XRDC_MRGD_W4_5_2_ACCSET2_MASK)

#define XRDC_MRGD_W4_5_2_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_5_2_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_5_2_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_2_LKAS2_SHIFT)) & XRDC_MRGD_W4_5_2_LKAS2_MASK)

#define XRDC_MRGD_W4_5_2_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_5_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_5_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_2_LK2_SHIFT)) & XRDC_MRGD_W4_5_2_LK2_MASK)

#define XRDC_MRGD_W4_5_2_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_5_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_5_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_2_VLD_SHIFT)) & XRDC_MRGD_W4_5_2_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_5_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_5_3_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_5_3_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_5_3_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_5_3_SRTADDR_SHIFT)) & XRDC_MRGD_W0_5_3_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_5_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_5_3_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_5_3_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_5_3_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_5_3_ENDADDR_SHIFT)) & XRDC_MRGD_W1_5_3_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_5_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_5_3_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_5_3_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_5_3_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_3_D0SEL_SHIFT)) & XRDC_MRGD_W2_5_3_D0SEL_MASK)

#define XRDC_MRGD_W2_5_3_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_5_3_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_5_3_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_3_D1SEL_SHIFT)) & XRDC_MRGD_W2_5_3_D1SEL_MASK)

#define XRDC_MRGD_W2_5_3_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_5_3_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_5_3_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_3_D2SEL_SHIFT)) & XRDC_MRGD_W2_5_3_D2SEL_MASK)

#define XRDC_MRGD_W2_5_3_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_5_3_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_5_3_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_3_D3SEL_SHIFT)) & XRDC_MRGD_W2_5_3_D3SEL_MASK)

#define XRDC_MRGD_W2_5_3_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_5_3_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_5_3_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_3_D4SEL_SHIFT)) & XRDC_MRGD_W2_5_3_D4SEL_MASK)

#define XRDC_MRGD_W2_5_3_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_5_3_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_5_3_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_3_D5SEL_SHIFT)) & XRDC_MRGD_W2_5_3_D5SEL_MASK)

#define XRDC_MRGD_W2_5_3_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_5_3_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_5_3_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_3_D6SEL_SHIFT)) & XRDC_MRGD_W2_5_3_D6SEL_MASK)

#define XRDC_MRGD_W2_5_3_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_5_3_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_5_3_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_3_D7SEL_SHIFT)) & XRDC_MRGD_W2_5_3_D7SEL_MASK)

#define XRDC_MRGD_W2_5_3_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_5_3_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_5_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_3_EALO_SHIFT)) & XRDC_MRGD_W2_5_3_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_5_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_5_3_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_5_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_5_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_3_EAL_SHIFT)) & XRDC_MRGD_W3_5_3_EAL_MASK)

#define XRDC_MRGD_W3_5_3_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_5_3_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_5_3_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_3_CR_SHIFT)) & XRDC_MRGD_W3_5_3_CR_MASK)
/*! @} */

/*! @name MRGD_W4_5_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_5_3_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_5_3_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_5_3_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_3_ACCSET1_SHIFT)) & XRDC_MRGD_W4_5_3_ACCSET1_MASK)

#define XRDC_MRGD_W4_5_3_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_5_3_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_5_3_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_3_LKAS1_SHIFT)) & XRDC_MRGD_W4_5_3_LKAS1_MASK)

#define XRDC_MRGD_W4_5_3_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_5_3_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_5_3_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_3_ACCSET2_SHIFT)) & XRDC_MRGD_W4_5_3_ACCSET2_MASK)

#define XRDC_MRGD_W4_5_3_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_5_3_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_5_3_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_3_LKAS2_SHIFT)) & XRDC_MRGD_W4_5_3_LKAS2_MASK)

#define XRDC_MRGD_W4_5_3_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_5_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_5_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_3_LK2_SHIFT)) & XRDC_MRGD_W4_5_3_LK2_MASK)

#define XRDC_MRGD_W4_5_3_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_5_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_5_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_3_VLD_SHIFT)) & XRDC_MRGD_W4_5_3_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_5_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_5_4_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_5_4_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_5_4_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_5_4_SRTADDR_SHIFT)) & XRDC_MRGD_W0_5_4_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_5_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_5_4_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_5_4_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_5_4_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_5_4_ENDADDR_SHIFT)) & XRDC_MRGD_W1_5_4_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_5_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_5_4_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_5_4_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_5_4_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_4_D0SEL_SHIFT)) & XRDC_MRGD_W2_5_4_D0SEL_MASK)

#define XRDC_MRGD_W2_5_4_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_5_4_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_5_4_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_4_D1SEL_SHIFT)) & XRDC_MRGD_W2_5_4_D1SEL_MASK)

#define XRDC_MRGD_W2_5_4_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_5_4_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_5_4_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_4_D2SEL_SHIFT)) & XRDC_MRGD_W2_5_4_D2SEL_MASK)

#define XRDC_MRGD_W2_5_4_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_5_4_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_5_4_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_4_D3SEL_SHIFT)) & XRDC_MRGD_W2_5_4_D3SEL_MASK)

#define XRDC_MRGD_W2_5_4_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_5_4_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_5_4_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_4_D4SEL_SHIFT)) & XRDC_MRGD_W2_5_4_D4SEL_MASK)

#define XRDC_MRGD_W2_5_4_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_5_4_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_5_4_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_4_D5SEL_SHIFT)) & XRDC_MRGD_W2_5_4_D5SEL_MASK)

#define XRDC_MRGD_W2_5_4_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_5_4_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_5_4_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_4_D6SEL_SHIFT)) & XRDC_MRGD_W2_5_4_D6SEL_MASK)

#define XRDC_MRGD_W2_5_4_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_5_4_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_5_4_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_4_D7SEL_SHIFT)) & XRDC_MRGD_W2_5_4_D7SEL_MASK)

#define XRDC_MRGD_W2_5_4_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_5_4_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_5_4_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_4_EALO_SHIFT)) & XRDC_MRGD_W2_5_4_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_5_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_5_4_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_5_4_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_5_4_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_4_EAL_SHIFT)) & XRDC_MRGD_W3_5_4_EAL_MASK)

#define XRDC_MRGD_W3_5_4_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_5_4_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_5_4_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_4_CR_SHIFT)) & XRDC_MRGD_W3_5_4_CR_MASK)
/*! @} */

/*! @name MRGD_W4_5_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_5_4_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_5_4_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_5_4_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_4_ACCSET1_SHIFT)) & XRDC_MRGD_W4_5_4_ACCSET1_MASK)

#define XRDC_MRGD_W4_5_4_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_5_4_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_5_4_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_4_LKAS1_SHIFT)) & XRDC_MRGD_W4_5_4_LKAS1_MASK)

#define XRDC_MRGD_W4_5_4_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_5_4_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_5_4_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_4_ACCSET2_SHIFT)) & XRDC_MRGD_W4_5_4_ACCSET2_MASK)

#define XRDC_MRGD_W4_5_4_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_5_4_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_5_4_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_4_LKAS2_SHIFT)) & XRDC_MRGD_W4_5_4_LKAS2_MASK)

#define XRDC_MRGD_W4_5_4_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_5_4_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_5_4_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_4_LK2_SHIFT)) & XRDC_MRGD_W4_5_4_LK2_MASK)

#define XRDC_MRGD_W4_5_4_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_5_4_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_5_4_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_4_VLD_SHIFT)) & XRDC_MRGD_W4_5_4_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_5_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_5_5_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_5_5_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_5_5_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_5_5_SRTADDR_SHIFT)) & XRDC_MRGD_W0_5_5_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_5_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_5_5_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_5_5_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_5_5_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_5_5_ENDADDR_SHIFT)) & XRDC_MRGD_W1_5_5_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_5_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_5_5_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_5_5_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_5_5_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_5_D0SEL_SHIFT)) & XRDC_MRGD_W2_5_5_D0SEL_MASK)

#define XRDC_MRGD_W2_5_5_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_5_5_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_5_5_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_5_D1SEL_SHIFT)) & XRDC_MRGD_W2_5_5_D1SEL_MASK)

#define XRDC_MRGD_W2_5_5_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_5_5_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_5_5_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_5_D2SEL_SHIFT)) & XRDC_MRGD_W2_5_5_D2SEL_MASK)

#define XRDC_MRGD_W2_5_5_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_5_5_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_5_5_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_5_D3SEL_SHIFT)) & XRDC_MRGD_W2_5_5_D3SEL_MASK)

#define XRDC_MRGD_W2_5_5_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_5_5_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_5_5_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_5_D4SEL_SHIFT)) & XRDC_MRGD_W2_5_5_D4SEL_MASK)

#define XRDC_MRGD_W2_5_5_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_5_5_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_5_5_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_5_D5SEL_SHIFT)) & XRDC_MRGD_W2_5_5_D5SEL_MASK)

#define XRDC_MRGD_W2_5_5_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_5_5_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_5_5_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_5_D6SEL_SHIFT)) & XRDC_MRGD_W2_5_5_D6SEL_MASK)

#define XRDC_MRGD_W2_5_5_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_5_5_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_5_5_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_5_D7SEL_SHIFT)) & XRDC_MRGD_W2_5_5_D7SEL_MASK)

#define XRDC_MRGD_W2_5_5_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_5_5_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_5_5_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_5_EALO_SHIFT)) & XRDC_MRGD_W2_5_5_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_5_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_5_5_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_5_5_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_5_5_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_5_EAL_SHIFT)) & XRDC_MRGD_W3_5_5_EAL_MASK)

#define XRDC_MRGD_W3_5_5_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_5_5_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_5_5_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_5_CR_SHIFT)) & XRDC_MRGD_W3_5_5_CR_MASK)
/*! @} */

/*! @name MRGD_W4_5_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_5_5_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_5_5_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_5_5_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_5_ACCSET1_SHIFT)) & XRDC_MRGD_W4_5_5_ACCSET1_MASK)

#define XRDC_MRGD_W4_5_5_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_5_5_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_5_5_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_5_LKAS1_SHIFT)) & XRDC_MRGD_W4_5_5_LKAS1_MASK)

#define XRDC_MRGD_W4_5_5_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_5_5_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_5_5_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_5_ACCSET2_SHIFT)) & XRDC_MRGD_W4_5_5_ACCSET2_MASK)

#define XRDC_MRGD_W4_5_5_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_5_5_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_5_5_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_5_LKAS2_SHIFT)) & XRDC_MRGD_W4_5_5_LKAS2_MASK)

#define XRDC_MRGD_W4_5_5_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_5_5_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_5_5_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_5_LK2_SHIFT)) & XRDC_MRGD_W4_5_5_LK2_MASK)

#define XRDC_MRGD_W4_5_5_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_5_5_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_5_5_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_5_VLD_SHIFT)) & XRDC_MRGD_W4_5_5_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_5_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_5_6_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_5_6_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_5_6_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_5_6_SRTADDR_SHIFT)) & XRDC_MRGD_W0_5_6_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_5_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_5_6_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_5_6_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_5_6_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_5_6_ENDADDR_SHIFT)) & XRDC_MRGD_W1_5_6_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_5_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_5_6_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_5_6_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_5_6_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_6_D0SEL_SHIFT)) & XRDC_MRGD_W2_5_6_D0SEL_MASK)

#define XRDC_MRGD_W2_5_6_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_5_6_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_5_6_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_6_D1SEL_SHIFT)) & XRDC_MRGD_W2_5_6_D1SEL_MASK)

#define XRDC_MRGD_W2_5_6_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_5_6_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_5_6_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_6_D2SEL_SHIFT)) & XRDC_MRGD_W2_5_6_D2SEL_MASK)

#define XRDC_MRGD_W2_5_6_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_5_6_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_5_6_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_6_D3SEL_SHIFT)) & XRDC_MRGD_W2_5_6_D3SEL_MASK)

#define XRDC_MRGD_W2_5_6_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_5_6_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_5_6_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_6_D4SEL_SHIFT)) & XRDC_MRGD_W2_5_6_D4SEL_MASK)

#define XRDC_MRGD_W2_5_6_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_5_6_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_5_6_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_6_D5SEL_SHIFT)) & XRDC_MRGD_W2_5_6_D5SEL_MASK)

#define XRDC_MRGD_W2_5_6_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_5_6_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_5_6_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_6_D6SEL_SHIFT)) & XRDC_MRGD_W2_5_6_D6SEL_MASK)

#define XRDC_MRGD_W2_5_6_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_5_6_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_5_6_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_6_D7SEL_SHIFT)) & XRDC_MRGD_W2_5_6_D7SEL_MASK)

#define XRDC_MRGD_W2_5_6_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_5_6_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_5_6_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_6_EALO_SHIFT)) & XRDC_MRGD_W2_5_6_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_5_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_5_6_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_5_6_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_5_6_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_6_EAL_SHIFT)) & XRDC_MRGD_W3_5_6_EAL_MASK)

#define XRDC_MRGD_W3_5_6_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_5_6_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_5_6_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_6_CR_SHIFT)) & XRDC_MRGD_W3_5_6_CR_MASK)
/*! @} */

/*! @name MRGD_W4_5_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_5_6_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_5_6_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_5_6_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_6_ACCSET1_SHIFT)) & XRDC_MRGD_W4_5_6_ACCSET1_MASK)

#define XRDC_MRGD_W4_5_6_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_5_6_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_5_6_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_6_LKAS1_SHIFT)) & XRDC_MRGD_W4_5_6_LKAS1_MASK)

#define XRDC_MRGD_W4_5_6_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_5_6_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_5_6_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_6_ACCSET2_SHIFT)) & XRDC_MRGD_W4_5_6_ACCSET2_MASK)

#define XRDC_MRGD_W4_5_6_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_5_6_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_5_6_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_6_LKAS2_SHIFT)) & XRDC_MRGD_W4_5_6_LKAS2_MASK)

#define XRDC_MRGD_W4_5_6_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_5_6_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_5_6_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_6_LK2_SHIFT)) & XRDC_MRGD_W4_5_6_LK2_MASK)

#define XRDC_MRGD_W4_5_6_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_5_6_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_5_6_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_6_VLD_SHIFT)) & XRDC_MRGD_W4_5_6_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_5_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_5_7_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_5_7_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_5_7_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_5_7_SRTADDR_SHIFT)) & XRDC_MRGD_W0_5_7_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_5_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_5_7_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_5_7_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_5_7_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_5_7_ENDADDR_SHIFT)) & XRDC_MRGD_W1_5_7_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_5_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_5_7_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_5_7_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_5_7_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_7_D0SEL_SHIFT)) & XRDC_MRGD_W2_5_7_D0SEL_MASK)

#define XRDC_MRGD_W2_5_7_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_5_7_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_5_7_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_7_D1SEL_SHIFT)) & XRDC_MRGD_W2_5_7_D1SEL_MASK)

#define XRDC_MRGD_W2_5_7_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_5_7_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_5_7_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_7_D2SEL_SHIFT)) & XRDC_MRGD_W2_5_7_D2SEL_MASK)

#define XRDC_MRGD_W2_5_7_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_5_7_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_5_7_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_7_D3SEL_SHIFT)) & XRDC_MRGD_W2_5_7_D3SEL_MASK)

#define XRDC_MRGD_W2_5_7_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_5_7_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_5_7_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_7_D4SEL_SHIFT)) & XRDC_MRGD_W2_5_7_D4SEL_MASK)

#define XRDC_MRGD_W2_5_7_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_5_7_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_5_7_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_7_D5SEL_SHIFT)) & XRDC_MRGD_W2_5_7_D5SEL_MASK)

#define XRDC_MRGD_W2_5_7_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_5_7_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_5_7_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_7_D6SEL_SHIFT)) & XRDC_MRGD_W2_5_7_D6SEL_MASK)

#define XRDC_MRGD_W2_5_7_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_5_7_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_5_7_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_7_D7SEL_SHIFT)) & XRDC_MRGD_W2_5_7_D7SEL_MASK)

#define XRDC_MRGD_W2_5_7_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_5_7_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_5_7_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_5_7_EALO_SHIFT)) & XRDC_MRGD_W2_5_7_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_5_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_5_7_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_5_7_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_5_7_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_7_EAL_SHIFT)) & XRDC_MRGD_W3_5_7_EAL_MASK)

#define XRDC_MRGD_W3_5_7_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_5_7_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_5_7_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_5_7_CR_SHIFT)) & XRDC_MRGD_W3_5_7_CR_MASK)
/*! @} */

/*! @name MRGD_W4_5_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_5_7_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_5_7_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_5_7_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_7_ACCSET1_SHIFT)) & XRDC_MRGD_W4_5_7_ACCSET1_MASK)

#define XRDC_MRGD_W4_5_7_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_5_7_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_5_7_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_7_LKAS1_SHIFT)) & XRDC_MRGD_W4_5_7_LKAS1_MASK)

#define XRDC_MRGD_W4_5_7_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_5_7_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_5_7_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_7_ACCSET2_SHIFT)) & XRDC_MRGD_W4_5_7_ACCSET2_MASK)

#define XRDC_MRGD_W4_5_7_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_5_7_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_5_7_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_7_LKAS2_SHIFT)) & XRDC_MRGD_W4_5_7_LKAS2_MASK)

#define XRDC_MRGD_W4_5_7_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_5_7_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_5_7_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_7_LK2_SHIFT)) & XRDC_MRGD_W4_5_7_LK2_MASK)

#define XRDC_MRGD_W4_5_7_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_5_7_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_5_7_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_5_7_VLD_SHIFT)) & XRDC_MRGD_W4_5_7_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_6_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_6_0_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_6_0_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_6_0_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_6_0_SRTADDR_SHIFT)) & XRDC_MRGD_W0_6_0_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_6_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_6_0_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_6_0_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_6_0_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_6_0_ENDADDR_SHIFT)) & XRDC_MRGD_W1_6_0_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_6_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_6_0_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_6_0_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_6_0_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_0_D0SEL_SHIFT)) & XRDC_MRGD_W2_6_0_D0SEL_MASK)

#define XRDC_MRGD_W2_6_0_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_6_0_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_6_0_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_0_D1SEL_SHIFT)) & XRDC_MRGD_W2_6_0_D1SEL_MASK)

#define XRDC_MRGD_W2_6_0_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_6_0_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_6_0_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_0_D2SEL_SHIFT)) & XRDC_MRGD_W2_6_0_D2SEL_MASK)

#define XRDC_MRGD_W2_6_0_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_6_0_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_6_0_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_0_D3SEL_SHIFT)) & XRDC_MRGD_W2_6_0_D3SEL_MASK)

#define XRDC_MRGD_W2_6_0_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_6_0_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_6_0_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_0_D4SEL_SHIFT)) & XRDC_MRGD_W2_6_0_D4SEL_MASK)

#define XRDC_MRGD_W2_6_0_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_6_0_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_6_0_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_0_D5SEL_SHIFT)) & XRDC_MRGD_W2_6_0_D5SEL_MASK)

#define XRDC_MRGD_W2_6_0_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_6_0_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_6_0_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_0_D6SEL_SHIFT)) & XRDC_MRGD_W2_6_0_D6SEL_MASK)

#define XRDC_MRGD_W2_6_0_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_6_0_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_6_0_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_0_D7SEL_SHIFT)) & XRDC_MRGD_W2_6_0_D7SEL_MASK)

#define XRDC_MRGD_W2_6_0_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_6_0_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_6_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_0_EALO_SHIFT)) & XRDC_MRGD_W2_6_0_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_6_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_6_0_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_6_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_6_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_0_EAL_SHIFT)) & XRDC_MRGD_W3_6_0_EAL_MASK)

#define XRDC_MRGD_W3_6_0_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_6_0_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_6_0_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_0_CR_SHIFT)) & XRDC_MRGD_W3_6_0_CR_MASK)
/*! @} */

/*! @name MRGD_W4_6_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_6_0_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_6_0_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_6_0_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_0_ACCSET1_SHIFT)) & XRDC_MRGD_W4_6_0_ACCSET1_MASK)

#define XRDC_MRGD_W4_6_0_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_6_0_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_6_0_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_0_LKAS1_SHIFT)) & XRDC_MRGD_W4_6_0_LKAS1_MASK)

#define XRDC_MRGD_W4_6_0_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_6_0_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_6_0_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_0_ACCSET2_SHIFT)) & XRDC_MRGD_W4_6_0_ACCSET2_MASK)

#define XRDC_MRGD_W4_6_0_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_6_0_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_6_0_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_0_LKAS2_SHIFT)) & XRDC_MRGD_W4_6_0_LKAS2_MASK)

#define XRDC_MRGD_W4_6_0_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_6_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_6_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_0_LK2_SHIFT)) & XRDC_MRGD_W4_6_0_LK2_MASK)

#define XRDC_MRGD_W4_6_0_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_6_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_6_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_0_VLD_SHIFT)) & XRDC_MRGD_W4_6_0_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_6_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_6_1_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_6_1_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_6_1_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_6_1_SRTADDR_SHIFT)) & XRDC_MRGD_W0_6_1_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_6_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_6_1_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_6_1_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_6_1_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_6_1_ENDADDR_SHIFT)) & XRDC_MRGD_W1_6_1_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_6_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_6_1_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_6_1_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_6_1_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_1_D0SEL_SHIFT)) & XRDC_MRGD_W2_6_1_D0SEL_MASK)

#define XRDC_MRGD_W2_6_1_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_6_1_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_6_1_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_1_D1SEL_SHIFT)) & XRDC_MRGD_W2_6_1_D1SEL_MASK)

#define XRDC_MRGD_W2_6_1_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_6_1_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_6_1_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_1_D2SEL_SHIFT)) & XRDC_MRGD_W2_6_1_D2SEL_MASK)

#define XRDC_MRGD_W2_6_1_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_6_1_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_6_1_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_1_D3SEL_SHIFT)) & XRDC_MRGD_W2_6_1_D3SEL_MASK)

#define XRDC_MRGD_W2_6_1_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_6_1_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_6_1_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_1_D4SEL_SHIFT)) & XRDC_MRGD_W2_6_1_D4SEL_MASK)

#define XRDC_MRGD_W2_6_1_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_6_1_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_6_1_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_1_D5SEL_SHIFT)) & XRDC_MRGD_W2_6_1_D5SEL_MASK)

#define XRDC_MRGD_W2_6_1_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_6_1_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_6_1_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_1_D6SEL_SHIFT)) & XRDC_MRGD_W2_6_1_D6SEL_MASK)

#define XRDC_MRGD_W2_6_1_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_6_1_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_6_1_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_1_D7SEL_SHIFT)) & XRDC_MRGD_W2_6_1_D7SEL_MASK)

#define XRDC_MRGD_W2_6_1_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_6_1_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_6_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_1_EALO_SHIFT)) & XRDC_MRGD_W2_6_1_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_6_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_6_1_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_6_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_6_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_1_EAL_SHIFT)) & XRDC_MRGD_W3_6_1_EAL_MASK)

#define XRDC_MRGD_W3_6_1_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_6_1_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_6_1_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_1_CR_SHIFT)) & XRDC_MRGD_W3_6_1_CR_MASK)
/*! @} */

/*! @name MRGD_W4_6_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_6_1_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_6_1_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_6_1_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_1_ACCSET1_SHIFT)) & XRDC_MRGD_W4_6_1_ACCSET1_MASK)

#define XRDC_MRGD_W4_6_1_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_6_1_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_6_1_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_1_LKAS1_SHIFT)) & XRDC_MRGD_W4_6_1_LKAS1_MASK)

#define XRDC_MRGD_W4_6_1_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_6_1_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_6_1_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_1_ACCSET2_SHIFT)) & XRDC_MRGD_W4_6_1_ACCSET2_MASK)

#define XRDC_MRGD_W4_6_1_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_6_1_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_6_1_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_1_LKAS2_SHIFT)) & XRDC_MRGD_W4_6_1_LKAS2_MASK)

#define XRDC_MRGD_W4_6_1_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_6_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_6_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_1_LK2_SHIFT)) & XRDC_MRGD_W4_6_1_LK2_MASK)

#define XRDC_MRGD_W4_6_1_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_6_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_6_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_1_VLD_SHIFT)) & XRDC_MRGD_W4_6_1_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_6_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_6_2_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_6_2_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_6_2_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_6_2_SRTADDR_SHIFT)) & XRDC_MRGD_W0_6_2_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_6_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_6_2_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_6_2_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_6_2_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_6_2_ENDADDR_SHIFT)) & XRDC_MRGD_W1_6_2_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_6_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_6_2_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_6_2_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_6_2_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_2_D0SEL_SHIFT)) & XRDC_MRGD_W2_6_2_D0SEL_MASK)

#define XRDC_MRGD_W2_6_2_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_6_2_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_6_2_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_2_D1SEL_SHIFT)) & XRDC_MRGD_W2_6_2_D1SEL_MASK)

#define XRDC_MRGD_W2_6_2_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_6_2_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_6_2_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_2_D2SEL_SHIFT)) & XRDC_MRGD_W2_6_2_D2SEL_MASK)

#define XRDC_MRGD_W2_6_2_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_6_2_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_6_2_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_2_D3SEL_SHIFT)) & XRDC_MRGD_W2_6_2_D3SEL_MASK)

#define XRDC_MRGD_W2_6_2_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_6_2_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_6_2_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_2_D4SEL_SHIFT)) & XRDC_MRGD_W2_6_2_D4SEL_MASK)

#define XRDC_MRGD_W2_6_2_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_6_2_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_6_2_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_2_D5SEL_SHIFT)) & XRDC_MRGD_W2_6_2_D5SEL_MASK)

#define XRDC_MRGD_W2_6_2_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_6_2_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_6_2_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_2_D6SEL_SHIFT)) & XRDC_MRGD_W2_6_2_D6SEL_MASK)

#define XRDC_MRGD_W2_6_2_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_6_2_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_6_2_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_2_D7SEL_SHIFT)) & XRDC_MRGD_W2_6_2_D7SEL_MASK)

#define XRDC_MRGD_W2_6_2_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_6_2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_6_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_2_EALO_SHIFT)) & XRDC_MRGD_W2_6_2_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_6_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_6_2_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_6_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_6_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_2_EAL_SHIFT)) & XRDC_MRGD_W3_6_2_EAL_MASK)

#define XRDC_MRGD_W3_6_2_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_6_2_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_6_2_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_2_CR_SHIFT)) & XRDC_MRGD_W3_6_2_CR_MASK)
/*! @} */

/*! @name MRGD_W4_6_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_6_2_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_6_2_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_6_2_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_2_ACCSET1_SHIFT)) & XRDC_MRGD_W4_6_2_ACCSET1_MASK)

#define XRDC_MRGD_W4_6_2_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_6_2_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_6_2_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_2_LKAS1_SHIFT)) & XRDC_MRGD_W4_6_2_LKAS1_MASK)

#define XRDC_MRGD_W4_6_2_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_6_2_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_6_2_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_2_ACCSET2_SHIFT)) & XRDC_MRGD_W4_6_2_ACCSET2_MASK)

#define XRDC_MRGD_W4_6_2_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_6_2_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_6_2_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_2_LKAS2_SHIFT)) & XRDC_MRGD_W4_6_2_LKAS2_MASK)

#define XRDC_MRGD_W4_6_2_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_6_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_6_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_2_LK2_SHIFT)) & XRDC_MRGD_W4_6_2_LK2_MASK)

#define XRDC_MRGD_W4_6_2_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_6_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_6_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_2_VLD_SHIFT)) & XRDC_MRGD_W4_6_2_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_6_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_6_3_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_6_3_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_6_3_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_6_3_SRTADDR_SHIFT)) & XRDC_MRGD_W0_6_3_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_6_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_6_3_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_6_3_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_6_3_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_6_3_ENDADDR_SHIFT)) & XRDC_MRGD_W1_6_3_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_6_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_6_3_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_6_3_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_6_3_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_3_D0SEL_SHIFT)) & XRDC_MRGD_W2_6_3_D0SEL_MASK)

#define XRDC_MRGD_W2_6_3_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_6_3_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_6_3_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_3_D1SEL_SHIFT)) & XRDC_MRGD_W2_6_3_D1SEL_MASK)

#define XRDC_MRGD_W2_6_3_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_6_3_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_6_3_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_3_D2SEL_SHIFT)) & XRDC_MRGD_W2_6_3_D2SEL_MASK)

#define XRDC_MRGD_W2_6_3_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_6_3_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_6_3_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_3_D3SEL_SHIFT)) & XRDC_MRGD_W2_6_3_D3SEL_MASK)

#define XRDC_MRGD_W2_6_3_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_6_3_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_6_3_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_3_D4SEL_SHIFT)) & XRDC_MRGD_W2_6_3_D4SEL_MASK)

#define XRDC_MRGD_W2_6_3_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_6_3_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_6_3_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_3_D5SEL_SHIFT)) & XRDC_MRGD_W2_6_3_D5SEL_MASK)

#define XRDC_MRGD_W2_6_3_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_6_3_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_6_3_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_3_D6SEL_SHIFT)) & XRDC_MRGD_W2_6_3_D6SEL_MASK)

#define XRDC_MRGD_W2_6_3_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_6_3_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_6_3_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_3_D7SEL_SHIFT)) & XRDC_MRGD_W2_6_3_D7SEL_MASK)

#define XRDC_MRGD_W2_6_3_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_6_3_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_6_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_3_EALO_SHIFT)) & XRDC_MRGD_W2_6_3_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_6_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_6_3_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_6_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_6_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_3_EAL_SHIFT)) & XRDC_MRGD_W3_6_3_EAL_MASK)

#define XRDC_MRGD_W3_6_3_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_6_3_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_6_3_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_3_CR_SHIFT)) & XRDC_MRGD_W3_6_3_CR_MASK)
/*! @} */

/*! @name MRGD_W4_6_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_6_3_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_6_3_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_6_3_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_3_ACCSET1_SHIFT)) & XRDC_MRGD_W4_6_3_ACCSET1_MASK)

#define XRDC_MRGD_W4_6_3_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_6_3_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_6_3_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_3_LKAS1_SHIFT)) & XRDC_MRGD_W4_6_3_LKAS1_MASK)

#define XRDC_MRGD_W4_6_3_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_6_3_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_6_3_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_3_ACCSET2_SHIFT)) & XRDC_MRGD_W4_6_3_ACCSET2_MASK)

#define XRDC_MRGD_W4_6_3_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_6_3_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_6_3_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_3_LKAS2_SHIFT)) & XRDC_MRGD_W4_6_3_LKAS2_MASK)

#define XRDC_MRGD_W4_6_3_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_6_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_6_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_3_LK2_SHIFT)) & XRDC_MRGD_W4_6_3_LK2_MASK)

#define XRDC_MRGD_W4_6_3_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_6_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_6_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_3_VLD_SHIFT)) & XRDC_MRGD_W4_6_3_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_6_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_6_4_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_6_4_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_6_4_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_6_4_SRTADDR_SHIFT)) & XRDC_MRGD_W0_6_4_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_6_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_6_4_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_6_4_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_6_4_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_6_4_ENDADDR_SHIFT)) & XRDC_MRGD_W1_6_4_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_6_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_6_4_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_6_4_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_6_4_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_4_D0SEL_SHIFT)) & XRDC_MRGD_W2_6_4_D0SEL_MASK)

#define XRDC_MRGD_W2_6_4_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_6_4_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_6_4_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_4_D1SEL_SHIFT)) & XRDC_MRGD_W2_6_4_D1SEL_MASK)

#define XRDC_MRGD_W2_6_4_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_6_4_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_6_4_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_4_D2SEL_SHIFT)) & XRDC_MRGD_W2_6_4_D2SEL_MASK)

#define XRDC_MRGD_W2_6_4_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_6_4_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_6_4_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_4_D3SEL_SHIFT)) & XRDC_MRGD_W2_6_4_D3SEL_MASK)

#define XRDC_MRGD_W2_6_4_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_6_4_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_6_4_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_4_D4SEL_SHIFT)) & XRDC_MRGD_W2_6_4_D4SEL_MASK)

#define XRDC_MRGD_W2_6_4_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_6_4_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_6_4_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_4_D5SEL_SHIFT)) & XRDC_MRGD_W2_6_4_D5SEL_MASK)

#define XRDC_MRGD_W2_6_4_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_6_4_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_6_4_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_4_D6SEL_SHIFT)) & XRDC_MRGD_W2_6_4_D6SEL_MASK)

#define XRDC_MRGD_W2_6_4_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_6_4_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_6_4_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_4_D7SEL_SHIFT)) & XRDC_MRGD_W2_6_4_D7SEL_MASK)

#define XRDC_MRGD_W2_6_4_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_6_4_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_6_4_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_4_EALO_SHIFT)) & XRDC_MRGD_W2_6_4_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_6_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_6_4_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_6_4_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_6_4_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_4_EAL_SHIFT)) & XRDC_MRGD_W3_6_4_EAL_MASK)

#define XRDC_MRGD_W3_6_4_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_6_4_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_6_4_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_4_CR_SHIFT)) & XRDC_MRGD_W3_6_4_CR_MASK)
/*! @} */

/*! @name MRGD_W4_6_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_6_4_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_6_4_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_6_4_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_4_ACCSET1_SHIFT)) & XRDC_MRGD_W4_6_4_ACCSET1_MASK)

#define XRDC_MRGD_W4_6_4_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_6_4_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_6_4_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_4_LKAS1_SHIFT)) & XRDC_MRGD_W4_6_4_LKAS1_MASK)

#define XRDC_MRGD_W4_6_4_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_6_4_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_6_4_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_4_ACCSET2_SHIFT)) & XRDC_MRGD_W4_6_4_ACCSET2_MASK)

#define XRDC_MRGD_W4_6_4_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_6_4_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_6_4_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_4_LKAS2_SHIFT)) & XRDC_MRGD_W4_6_4_LKAS2_MASK)

#define XRDC_MRGD_W4_6_4_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_6_4_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_6_4_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_4_LK2_SHIFT)) & XRDC_MRGD_W4_6_4_LK2_MASK)

#define XRDC_MRGD_W4_6_4_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_6_4_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_6_4_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_4_VLD_SHIFT)) & XRDC_MRGD_W4_6_4_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_6_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_6_5_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_6_5_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_6_5_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_6_5_SRTADDR_SHIFT)) & XRDC_MRGD_W0_6_5_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_6_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_6_5_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_6_5_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_6_5_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_6_5_ENDADDR_SHIFT)) & XRDC_MRGD_W1_6_5_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_6_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_6_5_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_6_5_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_6_5_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_5_D0SEL_SHIFT)) & XRDC_MRGD_W2_6_5_D0SEL_MASK)

#define XRDC_MRGD_W2_6_5_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_6_5_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_6_5_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_5_D1SEL_SHIFT)) & XRDC_MRGD_W2_6_5_D1SEL_MASK)

#define XRDC_MRGD_W2_6_5_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_6_5_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_6_5_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_5_D2SEL_SHIFT)) & XRDC_MRGD_W2_6_5_D2SEL_MASK)

#define XRDC_MRGD_W2_6_5_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_6_5_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_6_5_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_5_D3SEL_SHIFT)) & XRDC_MRGD_W2_6_5_D3SEL_MASK)

#define XRDC_MRGD_W2_6_5_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_6_5_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_6_5_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_5_D4SEL_SHIFT)) & XRDC_MRGD_W2_6_5_D4SEL_MASK)

#define XRDC_MRGD_W2_6_5_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_6_5_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_6_5_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_5_D5SEL_SHIFT)) & XRDC_MRGD_W2_6_5_D5SEL_MASK)

#define XRDC_MRGD_W2_6_5_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_6_5_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_6_5_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_5_D6SEL_SHIFT)) & XRDC_MRGD_W2_6_5_D6SEL_MASK)

#define XRDC_MRGD_W2_6_5_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_6_5_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_6_5_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_5_D7SEL_SHIFT)) & XRDC_MRGD_W2_6_5_D7SEL_MASK)

#define XRDC_MRGD_W2_6_5_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_6_5_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_6_5_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_5_EALO_SHIFT)) & XRDC_MRGD_W2_6_5_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_6_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_6_5_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_6_5_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_6_5_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_5_EAL_SHIFT)) & XRDC_MRGD_W3_6_5_EAL_MASK)

#define XRDC_MRGD_W3_6_5_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_6_5_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_6_5_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_5_CR_SHIFT)) & XRDC_MRGD_W3_6_5_CR_MASK)
/*! @} */

/*! @name MRGD_W4_6_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_6_5_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_6_5_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_6_5_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_5_ACCSET1_SHIFT)) & XRDC_MRGD_W4_6_5_ACCSET1_MASK)

#define XRDC_MRGD_W4_6_5_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_6_5_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_6_5_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_5_LKAS1_SHIFT)) & XRDC_MRGD_W4_6_5_LKAS1_MASK)

#define XRDC_MRGD_W4_6_5_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_6_5_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_6_5_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_5_ACCSET2_SHIFT)) & XRDC_MRGD_W4_6_5_ACCSET2_MASK)

#define XRDC_MRGD_W4_6_5_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_6_5_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_6_5_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_5_LKAS2_SHIFT)) & XRDC_MRGD_W4_6_5_LKAS2_MASK)

#define XRDC_MRGD_W4_6_5_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_6_5_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_6_5_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_5_LK2_SHIFT)) & XRDC_MRGD_W4_6_5_LK2_MASK)

#define XRDC_MRGD_W4_6_5_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_6_5_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_6_5_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_5_VLD_SHIFT)) & XRDC_MRGD_W4_6_5_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_6_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_6_6_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_6_6_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_6_6_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_6_6_SRTADDR_SHIFT)) & XRDC_MRGD_W0_6_6_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_6_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_6_6_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_6_6_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_6_6_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_6_6_ENDADDR_SHIFT)) & XRDC_MRGD_W1_6_6_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_6_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_6_6_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_6_6_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_6_6_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_6_D0SEL_SHIFT)) & XRDC_MRGD_W2_6_6_D0SEL_MASK)

#define XRDC_MRGD_W2_6_6_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_6_6_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_6_6_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_6_D1SEL_SHIFT)) & XRDC_MRGD_W2_6_6_D1SEL_MASK)

#define XRDC_MRGD_W2_6_6_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_6_6_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_6_6_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_6_D2SEL_SHIFT)) & XRDC_MRGD_W2_6_6_D2SEL_MASK)

#define XRDC_MRGD_W2_6_6_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_6_6_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_6_6_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_6_D3SEL_SHIFT)) & XRDC_MRGD_W2_6_6_D3SEL_MASK)

#define XRDC_MRGD_W2_6_6_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_6_6_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_6_6_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_6_D4SEL_SHIFT)) & XRDC_MRGD_W2_6_6_D4SEL_MASK)

#define XRDC_MRGD_W2_6_6_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_6_6_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_6_6_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_6_D5SEL_SHIFT)) & XRDC_MRGD_W2_6_6_D5SEL_MASK)

#define XRDC_MRGD_W2_6_6_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_6_6_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_6_6_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_6_D6SEL_SHIFT)) & XRDC_MRGD_W2_6_6_D6SEL_MASK)

#define XRDC_MRGD_W2_6_6_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_6_6_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_6_6_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_6_D7SEL_SHIFT)) & XRDC_MRGD_W2_6_6_D7SEL_MASK)

#define XRDC_MRGD_W2_6_6_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_6_6_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_6_6_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_6_EALO_SHIFT)) & XRDC_MRGD_W2_6_6_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_6_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_6_6_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_6_6_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_6_6_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_6_EAL_SHIFT)) & XRDC_MRGD_W3_6_6_EAL_MASK)

#define XRDC_MRGD_W3_6_6_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_6_6_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_6_6_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_6_CR_SHIFT)) & XRDC_MRGD_W3_6_6_CR_MASK)
/*! @} */

/*! @name MRGD_W4_6_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_6_6_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_6_6_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_6_6_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_6_ACCSET1_SHIFT)) & XRDC_MRGD_W4_6_6_ACCSET1_MASK)

#define XRDC_MRGD_W4_6_6_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_6_6_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_6_6_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_6_LKAS1_SHIFT)) & XRDC_MRGD_W4_6_6_LKAS1_MASK)

#define XRDC_MRGD_W4_6_6_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_6_6_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_6_6_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_6_ACCSET2_SHIFT)) & XRDC_MRGD_W4_6_6_ACCSET2_MASK)

#define XRDC_MRGD_W4_6_6_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_6_6_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_6_6_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_6_LKAS2_SHIFT)) & XRDC_MRGD_W4_6_6_LKAS2_MASK)

#define XRDC_MRGD_W4_6_6_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_6_6_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_6_6_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_6_LK2_SHIFT)) & XRDC_MRGD_W4_6_6_LK2_MASK)

#define XRDC_MRGD_W4_6_6_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_6_6_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_6_6_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_6_VLD_SHIFT)) & XRDC_MRGD_W4_6_6_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_6_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_6_7_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_6_7_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_6_7_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_6_7_SRTADDR_SHIFT)) & XRDC_MRGD_W0_6_7_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_6_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_6_7_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_6_7_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_6_7_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_6_7_ENDADDR_SHIFT)) & XRDC_MRGD_W1_6_7_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_6_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_6_7_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_6_7_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_6_7_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_7_D0SEL_SHIFT)) & XRDC_MRGD_W2_6_7_D0SEL_MASK)

#define XRDC_MRGD_W2_6_7_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_6_7_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_6_7_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_7_D1SEL_SHIFT)) & XRDC_MRGD_W2_6_7_D1SEL_MASK)

#define XRDC_MRGD_W2_6_7_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_6_7_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_6_7_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_7_D2SEL_SHIFT)) & XRDC_MRGD_W2_6_7_D2SEL_MASK)

#define XRDC_MRGD_W2_6_7_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_6_7_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_6_7_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_7_D3SEL_SHIFT)) & XRDC_MRGD_W2_6_7_D3SEL_MASK)

#define XRDC_MRGD_W2_6_7_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_6_7_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_6_7_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_7_D4SEL_SHIFT)) & XRDC_MRGD_W2_6_7_D4SEL_MASK)

#define XRDC_MRGD_W2_6_7_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_6_7_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_6_7_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_7_D5SEL_SHIFT)) & XRDC_MRGD_W2_6_7_D5SEL_MASK)

#define XRDC_MRGD_W2_6_7_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_6_7_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_6_7_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_7_D6SEL_SHIFT)) & XRDC_MRGD_W2_6_7_D6SEL_MASK)

#define XRDC_MRGD_W2_6_7_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_6_7_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_6_7_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_7_D7SEL_SHIFT)) & XRDC_MRGD_W2_6_7_D7SEL_MASK)

#define XRDC_MRGD_W2_6_7_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_6_7_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_6_7_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_6_7_EALO_SHIFT)) & XRDC_MRGD_W2_6_7_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_6_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_6_7_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_6_7_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_6_7_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_7_EAL_SHIFT)) & XRDC_MRGD_W3_6_7_EAL_MASK)

#define XRDC_MRGD_W3_6_7_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_6_7_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_6_7_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_6_7_CR_SHIFT)) & XRDC_MRGD_W3_6_7_CR_MASK)
/*! @} */

/*! @name MRGD_W4_6_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_6_7_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_6_7_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_6_7_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_7_ACCSET1_SHIFT)) & XRDC_MRGD_W4_6_7_ACCSET1_MASK)

#define XRDC_MRGD_W4_6_7_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_6_7_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_6_7_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_7_LKAS1_SHIFT)) & XRDC_MRGD_W4_6_7_LKAS1_MASK)

#define XRDC_MRGD_W4_6_7_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_6_7_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_6_7_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_7_ACCSET2_SHIFT)) & XRDC_MRGD_W4_6_7_ACCSET2_MASK)

#define XRDC_MRGD_W4_6_7_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_6_7_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_6_7_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_7_LKAS2_SHIFT)) & XRDC_MRGD_W4_6_7_LKAS2_MASK)

#define XRDC_MRGD_W4_6_7_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_6_7_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_6_7_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_7_LK2_SHIFT)) & XRDC_MRGD_W4_6_7_LK2_MASK)

#define XRDC_MRGD_W4_6_7_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_6_7_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_6_7_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_6_7_VLD_SHIFT)) & XRDC_MRGD_W4_6_7_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_7_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_7_0_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_7_0_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_7_0_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_7_0_SRTADDR_SHIFT)) & XRDC_MRGD_W0_7_0_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_7_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_7_0_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_7_0_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_7_0_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_7_0_ENDADDR_SHIFT)) & XRDC_MRGD_W1_7_0_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_7_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_7_0_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_7_0_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_7_0_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_0_D0SEL_SHIFT)) & XRDC_MRGD_W2_7_0_D0SEL_MASK)

#define XRDC_MRGD_W2_7_0_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_7_0_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_7_0_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_0_D1SEL_SHIFT)) & XRDC_MRGD_W2_7_0_D1SEL_MASK)

#define XRDC_MRGD_W2_7_0_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_7_0_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_7_0_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_0_D2SEL_SHIFT)) & XRDC_MRGD_W2_7_0_D2SEL_MASK)

#define XRDC_MRGD_W2_7_0_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_7_0_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_7_0_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_0_D3SEL_SHIFT)) & XRDC_MRGD_W2_7_0_D3SEL_MASK)

#define XRDC_MRGD_W2_7_0_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_7_0_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_7_0_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_0_D4SEL_SHIFT)) & XRDC_MRGD_W2_7_0_D4SEL_MASK)

#define XRDC_MRGD_W2_7_0_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_7_0_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_7_0_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_0_D5SEL_SHIFT)) & XRDC_MRGD_W2_7_0_D5SEL_MASK)

#define XRDC_MRGD_W2_7_0_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_7_0_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_7_0_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_0_D6SEL_SHIFT)) & XRDC_MRGD_W2_7_0_D6SEL_MASK)

#define XRDC_MRGD_W2_7_0_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_7_0_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_7_0_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_0_D7SEL_SHIFT)) & XRDC_MRGD_W2_7_0_D7SEL_MASK)

#define XRDC_MRGD_W2_7_0_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_7_0_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_7_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_0_EALO_SHIFT)) & XRDC_MRGD_W2_7_0_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_7_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_7_0_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_7_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_7_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_0_EAL_SHIFT)) & XRDC_MRGD_W3_7_0_EAL_MASK)

#define XRDC_MRGD_W3_7_0_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_7_0_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_7_0_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_0_CR_SHIFT)) & XRDC_MRGD_W3_7_0_CR_MASK)
/*! @} */

/*! @name MRGD_W4_7_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_7_0_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_7_0_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_7_0_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_0_ACCSET1_SHIFT)) & XRDC_MRGD_W4_7_0_ACCSET1_MASK)

#define XRDC_MRGD_W4_7_0_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_7_0_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_7_0_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_0_LKAS1_SHIFT)) & XRDC_MRGD_W4_7_0_LKAS1_MASK)

#define XRDC_MRGD_W4_7_0_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_7_0_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_7_0_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_0_ACCSET2_SHIFT)) & XRDC_MRGD_W4_7_0_ACCSET2_MASK)

#define XRDC_MRGD_W4_7_0_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_7_0_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_7_0_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_0_LKAS2_SHIFT)) & XRDC_MRGD_W4_7_0_LKAS2_MASK)

#define XRDC_MRGD_W4_7_0_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_7_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_7_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_0_LK2_SHIFT)) & XRDC_MRGD_W4_7_0_LK2_MASK)

#define XRDC_MRGD_W4_7_0_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_7_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_7_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_0_VLD_SHIFT)) & XRDC_MRGD_W4_7_0_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_7_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_7_1_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_7_1_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_7_1_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_7_1_SRTADDR_SHIFT)) & XRDC_MRGD_W0_7_1_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_7_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_7_1_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_7_1_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_7_1_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_7_1_ENDADDR_SHIFT)) & XRDC_MRGD_W1_7_1_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_7_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_7_1_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_7_1_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_7_1_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_1_D0SEL_SHIFT)) & XRDC_MRGD_W2_7_1_D0SEL_MASK)

#define XRDC_MRGD_W2_7_1_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_7_1_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_7_1_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_1_D1SEL_SHIFT)) & XRDC_MRGD_W2_7_1_D1SEL_MASK)

#define XRDC_MRGD_W2_7_1_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_7_1_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_7_1_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_1_D2SEL_SHIFT)) & XRDC_MRGD_W2_7_1_D2SEL_MASK)

#define XRDC_MRGD_W2_7_1_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_7_1_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_7_1_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_1_D3SEL_SHIFT)) & XRDC_MRGD_W2_7_1_D3SEL_MASK)

#define XRDC_MRGD_W2_7_1_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_7_1_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_7_1_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_1_D4SEL_SHIFT)) & XRDC_MRGD_W2_7_1_D4SEL_MASK)

#define XRDC_MRGD_W2_7_1_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_7_1_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_7_1_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_1_D5SEL_SHIFT)) & XRDC_MRGD_W2_7_1_D5SEL_MASK)

#define XRDC_MRGD_W2_7_1_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_7_1_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_7_1_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_1_D6SEL_SHIFT)) & XRDC_MRGD_W2_7_1_D6SEL_MASK)

#define XRDC_MRGD_W2_7_1_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_7_1_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_7_1_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_1_D7SEL_SHIFT)) & XRDC_MRGD_W2_7_1_D7SEL_MASK)

#define XRDC_MRGD_W2_7_1_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_7_1_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_7_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_1_EALO_SHIFT)) & XRDC_MRGD_W2_7_1_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_7_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_7_1_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_7_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_7_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_1_EAL_SHIFT)) & XRDC_MRGD_W3_7_1_EAL_MASK)

#define XRDC_MRGD_W3_7_1_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_7_1_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_7_1_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_1_CR_SHIFT)) & XRDC_MRGD_W3_7_1_CR_MASK)
/*! @} */

/*! @name MRGD_W4_7_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_7_1_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_7_1_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_7_1_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_1_ACCSET1_SHIFT)) & XRDC_MRGD_W4_7_1_ACCSET1_MASK)

#define XRDC_MRGD_W4_7_1_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_7_1_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_7_1_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_1_LKAS1_SHIFT)) & XRDC_MRGD_W4_7_1_LKAS1_MASK)

#define XRDC_MRGD_W4_7_1_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_7_1_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_7_1_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_1_ACCSET2_SHIFT)) & XRDC_MRGD_W4_7_1_ACCSET2_MASK)

#define XRDC_MRGD_W4_7_1_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_7_1_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_7_1_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_1_LKAS2_SHIFT)) & XRDC_MRGD_W4_7_1_LKAS2_MASK)

#define XRDC_MRGD_W4_7_1_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_7_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_7_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_1_LK2_SHIFT)) & XRDC_MRGD_W4_7_1_LK2_MASK)

#define XRDC_MRGD_W4_7_1_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_7_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_7_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_1_VLD_SHIFT)) & XRDC_MRGD_W4_7_1_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_7_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_7_2_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_7_2_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_7_2_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_7_2_SRTADDR_SHIFT)) & XRDC_MRGD_W0_7_2_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_7_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_7_2_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_7_2_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_7_2_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_7_2_ENDADDR_SHIFT)) & XRDC_MRGD_W1_7_2_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_7_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_7_2_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_7_2_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_7_2_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_2_D0SEL_SHIFT)) & XRDC_MRGD_W2_7_2_D0SEL_MASK)

#define XRDC_MRGD_W2_7_2_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_7_2_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_7_2_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_2_D1SEL_SHIFT)) & XRDC_MRGD_W2_7_2_D1SEL_MASK)

#define XRDC_MRGD_W2_7_2_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_7_2_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_7_2_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_2_D2SEL_SHIFT)) & XRDC_MRGD_W2_7_2_D2SEL_MASK)

#define XRDC_MRGD_W2_7_2_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_7_2_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_7_2_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_2_D3SEL_SHIFT)) & XRDC_MRGD_W2_7_2_D3SEL_MASK)

#define XRDC_MRGD_W2_7_2_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_7_2_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_7_2_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_2_D4SEL_SHIFT)) & XRDC_MRGD_W2_7_2_D4SEL_MASK)

#define XRDC_MRGD_W2_7_2_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_7_2_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_7_2_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_2_D5SEL_SHIFT)) & XRDC_MRGD_W2_7_2_D5SEL_MASK)

#define XRDC_MRGD_W2_7_2_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_7_2_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_7_2_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_2_D6SEL_SHIFT)) & XRDC_MRGD_W2_7_2_D6SEL_MASK)

#define XRDC_MRGD_W2_7_2_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_7_2_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_7_2_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_2_D7SEL_SHIFT)) & XRDC_MRGD_W2_7_2_D7SEL_MASK)

#define XRDC_MRGD_W2_7_2_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_7_2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_7_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_2_EALO_SHIFT)) & XRDC_MRGD_W2_7_2_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_7_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_7_2_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_7_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_7_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_2_EAL_SHIFT)) & XRDC_MRGD_W3_7_2_EAL_MASK)

#define XRDC_MRGD_W3_7_2_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_7_2_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_7_2_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_2_CR_SHIFT)) & XRDC_MRGD_W3_7_2_CR_MASK)
/*! @} */

/*! @name MRGD_W4_7_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_7_2_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_7_2_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_7_2_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_2_ACCSET1_SHIFT)) & XRDC_MRGD_W4_7_2_ACCSET1_MASK)

#define XRDC_MRGD_W4_7_2_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_7_2_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_7_2_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_2_LKAS1_SHIFT)) & XRDC_MRGD_W4_7_2_LKAS1_MASK)

#define XRDC_MRGD_W4_7_2_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_7_2_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_7_2_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_2_ACCSET2_SHIFT)) & XRDC_MRGD_W4_7_2_ACCSET2_MASK)

#define XRDC_MRGD_W4_7_2_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_7_2_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_7_2_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_2_LKAS2_SHIFT)) & XRDC_MRGD_W4_7_2_LKAS2_MASK)

#define XRDC_MRGD_W4_7_2_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_7_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_7_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_2_LK2_SHIFT)) & XRDC_MRGD_W4_7_2_LK2_MASK)

#define XRDC_MRGD_W4_7_2_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_7_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_7_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_2_VLD_SHIFT)) & XRDC_MRGD_W4_7_2_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_7_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_7_3_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_7_3_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_7_3_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_7_3_SRTADDR_SHIFT)) & XRDC_MRGD_W0_7_3_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_7_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_7_3_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_7_3_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_7_3_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_7_3_ENDADDR_SHIFT)) & XRDC_MRGD_W1_7_3_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_7_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_7_3_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_7_3_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_7_3_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_3_D0SEL_SHIFT)) & XRDC_MRGD_W2_7_3_D0SEL_MASK)

#define XRDC_MRGD_W2_7_3_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_7_3_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_7_3_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_3_D1SEL_SHIFT)) & XRDC_MRGD_W2_7_3_D1SEL_MASK)

#define XRDC_MRGD_W2_7_3_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_7_3_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_7_3_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_3_D2SEL_SHIFT)) & XRDC_MRGD_W2_7_3_D2SEL_MASK)

#define XRDC_MRGD_W2_7_3_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_7_3_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_7_3_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_3_D3SEL_SHIFT)) & XRDC_MRGD_W2_7_3_D3SEL_MASK)

#define XRDC_MRGD_W2_7_3_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_7_3_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_7_3_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_3_D4SEL_SHIFT)) & XRDC_MRGD_W2_7_3_D4SEL_MASK)

#define XRDC_MRGD_W2_7_3_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_7_3_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_7_3_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_3_D5SEL_SHIFT)) & XRDC_MRGD_W2_7_3_D5SEL_MASK)

#define XRDC_MRGD_W2_7_3_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_7_3_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_7_3_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_3_D6SEL_SHIFT)) & XRDC_MRGD_W2_7_3_D6SEL_MASK)

#define XRDC_MRGD_W2_7_3_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_7_3_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_7_3_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_3_D7SEL_SHIFT)) & XRDC_MRGD_W2_7_3_D7SEL_MASK)

#define XRDC_MRGD_W2_7_3_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_7_3_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_7_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_3_EALO_SHIFT)) & XRDC_MRGD_W2_7_3_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_7_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_7_3_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_7_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_7_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_3_EAL_SHIFT)) & XRDC_MRGD_W3_7_3_EAL_MASK)

#define XRDC_MRGD_W3_7_3_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_7_3_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_7_3_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_3_CR_SHIFT)) & XRDC_MRGD_W3_7_3_CR_MASK)
/*! @} */

/*! @name MRGD_W4_7_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_7_3_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_7_3_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_7_3_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_3_ACCSET1_SHIFT)) & XRDC_MRGD_W4_7_3_ACCSET1_MASK)

#define XRDC_MRGD_W4_7_3_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_7_3_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_7_3_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_3_LKAS1_SHIFT)) & XRDC_MRGD_W4_7_3_LKAS1_MASK)

#define XRDC_MRGD_W4_7_3_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_7_3_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_7_3_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_3_ACCSET2_SHIFT)) & XRDC_MRGD_W4_7_3_ACCSET2_MASK)

#define XRDC_MRGD_W4_7_3_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_7_3_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_7_3_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_3_LKAS2_SHIFT)) & XRDC_MRGD_W4_7_3_LKAS2_MASK)

#define XRDC_MRGD_W4_7_3_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_7_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_7_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_3_LK2_SHIFT)) & XRDC_MRGD_W4_7_3_LK2_MASK)

#define XRDC_MRGD_W4_7_3_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_7_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_7_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_3_VLD_SHIFT)) & XRDC_MRGD_W4_7_3_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_7_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_7_4_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_7_4_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_7_4_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_7_4_SRTADDR_SHIFT)) & XRDC_MRGD_W0_7_4_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_7_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_7_4_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_7_4_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_7_4_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_7_4_ENDADDR_SHIFT)) & XRDC_MRGD_W1_7_4_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_7_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_7_4_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_7_4_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_7_4_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_4_D0SEL_SHIFT)) & XRDC_MRGD_W2_7_4_D0SEL_MASK)

#define XRDC_MRGD_W2_7_4_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_7_4_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_7_4_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_4_D1SEL_SHIFT)) & XRDC_MRGD_W2_7_4_D1SEL_MASK)

#define XRDC_MRGD_W2_7_4_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_7_4_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_7_4_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_4_D2SEL_SHIFT)) & XRDC_MRGD_W2_7_4_D2SEL_MASK)

#define XRDC_MRGD_W2_7_4_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_7_4_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_7_4_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_4_D3SEL_SHIFT)) & XRDC_MRGD_W2_7_4_D3SEL_MASK)

#define XRDC_MRGD_W2_7_4_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_7_4_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_7_4_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_4_D4SEL_SHIFT)) & XRDC_MRGD_W2_7_4_D4SEL_MASK)

#define XRDC_MRGD_W2_7_4_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_7_4_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_7_4_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_4_D5SEL_SHIFT)) & XRDC_MRGD_W2_7_4_D5SEL_MASK)

#define XRDC_MRGD_W2_7_4_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_7_4_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_7_4_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_4_D6SEL_SHIFT)) & XRDC_MRGD_W2_7_4_D6SEL_MASK)

#define XRDC_MRGD_W2_7_4_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_7_4_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_7_4_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_4_D7SEL_SHIFT)) & XRDC_MRGD_W2_7_4_D7SEL_MASK)

#define XRDC_MRGD_W2_7_4_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_7_4_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_7_4_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_4_EALO_SHIFT)) & XRDC_MRGD_W2_7_4_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_7_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_7_4_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_7_4_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_7_4_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_4_EAL_SHIFT)) & XRDC_MRGD_W3_7_4_EAL_MASK)

#define XRDC_MRGD_W3_7_4_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_7_4_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_7_4_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_4_CR_SHIFT)) & XRDC_MRGD_W3_7_4_CR_MASK)
/*! @} */

/*! @name MRGD_W4_7_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_7_4_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_7_4_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_7_4_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_4_ACCSET1_SHIFT)) & XRDC_MRGD_W4_7_4_ACCSET1_MASK)

#define XRDC_MRGD_W4_7_4_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_7_4_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_7_4_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_4_LKAS1_SHIFT)) & XRDC_MRGD_W4_7_4_LKAS1_MASK)

#define XRDC_MRGD_W4_7_4_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_7_4_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_7_4_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_4_ACCSET2_SHIFT)) & XRDC_MRGD_W4_7_4_ACCSET2_MASK)

#define XRDC_MRGD_W4_7_4_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_7_4_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_7_4_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_4_LKAS2_SHIFT)) & XRDC_MRGD_W4_7_4_LKAS2_MASK)

#define XRDC_MRGD_W4_7_4_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_7_4_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_7_4_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_4_LK2_SHIFT)) & XRDC_MRGD_W4_7_4_LK2_MASK)

#define XRDC_MRGD_W4_7_4_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_7_4_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_7_4_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_4_VLD_SHIFT)) & XRDC_MRGD_W4_7_4_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_7_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_7_5_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_7_5_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_7_5_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_7_5_SRTADDR_SHIFT)) & XRDC_MRGD_W0_7_5_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_7_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_7_5_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_7_5_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_7_5_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_7_5_ENDADDR_SHIFT)) & XRDC_MRGD_W1_7_5_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_7_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_7_5_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_7_5_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_7_5_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_5_D0SEL_SHIFT)) & XRDC_MRGD_W2_7_5_D0SEL_MASK)

#define XRDC_MRGD_W2_7_5_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_7_5_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_7_5_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_5_D1SEL_SHIFT)) & XRDC_MRGD_W2_7_5_D1SEL_MASK)

#define XRDC_MRGD_W2_7_5_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_7_5_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_7_5_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_5_D2SEL_SHIFT)) & XRDC_MRGD_W2_7_5_D2SEL_MASK)

#define XRDC_MRGD_W2_7_5_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_7_5_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_7_5_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_5_D3SEL_SHIFT)) & XRDC_MRGD_W2_7_5_D3SEL_MASK)

#define XRDC_MRGD_W2_7_5_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_7_5_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_7_5_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_5_D4SEL_SHIFT)) & XRDC_MRGD_W2_7_5_D4SEL_MASK)

#define XRDC_MRGD_W2_7_5_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_7_5_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_7_5_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_5_D5SEL_SHIFT)) & XRDC_MRGD_W2_7_5_D5SEL_MASK)

#define XRDC_MRGD_W2_7_5_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_7_5_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_7_5_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_5_D6SEL_SHIFT)) & XRDC_MRGD_W2_7_5_D6SEL_MASK)

#define XRDC_MRGD_W2_7_5_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_7_5_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_7_5_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_5_D7SEL_SHIFT)) & XRDC_MRGD_W2_7_5_D7SEL_MASK)

#define XRDC_MRGD_W2_7_5_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_7_5_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_7_5_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_5_EALO_SHIFT)) & XRDC_MRGD_W2_7_5_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_7_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_7_5_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_7_5_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_7_5_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_5_EAL_SHIFT)) & XRDC_MRGD_W3_7_5_EAL_MASK)

#define XRDC_MRGD_W3_7_5_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_7_5_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_7_5_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_5_CR_SHIFT)) & XRDC_MRGD_W3_7_5_CR_MASK)
/*! @} */

/*! @name MRGD_W4_7_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_7_5_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_7_5_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_7_5_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_5_ACCSET1_SHIFT)) & XRDC_MRGD_W4_7_5_ACCSET1_MASK)

#define XRDC_MRGD_W4_7_5_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_7_5_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_7_5_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_5_LKAS1_SHIFT)) & XRDC_MRGD_W4_7_5_LKAS1_MASK)

#define XRDC_MRGD_W4_7_5_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_7_5_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_7_5_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_5_ACCSET2_SHIFT)) & XRDC_MRGD_W4_7_5_ACCSET2_MASK)

#define XRDC_MRGD_W4_7_5_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_7_5_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_7_5_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_5_LKAS2_SHIFT)) & XRDC_MRGD_W4_7_5_LKAS2_MASK)

#define XRDC_MRGD_W4_7_5_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_7_5_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_7_5_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_5_LK2_SHIFT)) & XRDC_MRGD_W4_7_5_LK2_MASK)

#define XRDC_MRGD_W4_7_5_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_7_5_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_7_5_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_5_VLD_SHIFT)) & XRDC_MRGD_W4_7_5_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_7_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_7_6_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_7_6_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_7_6_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_7_6_SRTADDR_SHIFT)) & XRDC_MRGD_W0_7_6_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_7_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_7_6_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_7_6_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_7_6_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_7_6_ENDADDR_SHIFT)) & XRDC_MRGD_W1_7_6_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_7_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_7_6_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_7_6_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_7_6_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_6_D0SEL_SHIFT)) & XRDC_MRGD_W2_7_6_D0SEL_MASK)

#define XRDC_MRGD_W2_7_6_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_7_6_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_7_6_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_6_D1SEL_SHIFT)) & XRDC_MRGD_W2_7_6_D1SEL_MASK)

#define XRDC_MRGD_W2_7_6_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_7_6_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_7_6_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_6_D2SEL_SHIFT)) & XRDC_MRGD_W2_7_6_D2SEL_MASK)

#define XRDC_MRGD_W2_7_6_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_7_6_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_7_6_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_6_D3SEL_SHIFT)) & XRDC_MRGD_W2_7_6_D3SEL_MASK)

#define XRDC_MRGD_W2_7_6_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_7_6_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_7_6_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_6_D4SEL_SHIFT)) & XRDC_MRGD_W2_7_6_D4SEL_MASK)

#define XRDC_MRGD_W2_7_6_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_7_6_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_7_6_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_6_D5SEL_SHIFT)) & XRDC_MRGD_W2_7_6_D5SEL_MASK)

#define XRDC_MRGD_W2_7_6_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_7_6_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_7_6_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_6_D6SEL_SHIFT)) & XRDC_MRGD_W2_7_6_D6SEL_MASK)

#define XRDC_MRGD_W2_7_6_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_7_6_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_7_6_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_6_D7SEL_SHIFT)) & XRDC_MRGD_W2_7_6_D7SEL_MASK)

#define XRDC_MRGD_W2_7_6_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_7_6_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_7_6_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_6_EALO_SHIFT)) & XRDC_MRGD_W2_7_6_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_7_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_7_6_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_7_6_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_7_6_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_6_EAL_SHIFT)) & XRDC_MRGD_W3_7_6_EAL_MASK)

#define XRDC_MRGD_W3_7_6_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_7_6_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_7_6_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_6_CR_SHIFT)) & XRDC_MRGD_W3_7_6_CR_MASK)
/*! @} */

/*! @name MRGD_W4_7_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_7_6_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_7_6_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_7_6_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_6_ACCSET1_SHIFT)) & XRDC_MRGD_W4_7_6_ACCSET1_MASK)

#define XRDC_MRGD_W4_7_6_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_7_6_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_7_6_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_6_LKAS1_SHIFT)) & XRDC_MRGD_W4_7_6_LKAS1_MASK)

#define XRDC_MRGD_W4_7_6_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_7_6_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_7_6_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_6_ACCSET2_SHIFT)) & XRDC_MRGD_W4_7_6_ACCSET2_MASK)

#define XRDC_MRGD_W4_7_6_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_7_6_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_7_6_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_6_LKAS2_SHIFT)) & XRDC_MRGD_W4_7_6_LKAS2_MASK)

#define XRDC_MRGD_W4_7_6_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_7_6_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_7_6_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_6_LK2_SHIFT)) & XRDC_MRGD_W4_7_6_LK2_MASK)

#define XRDC_MRGD_W4_7_6_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_7_6_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_7_6_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_6_VLD_SHIFT)) & XRDC_MRGD_W4_7_6_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_7_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_7_7_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_7_7_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_7_7_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_7_7_SRTADDR_SHIFT)) & XRDC_MRGD_W0_7_7_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_7_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_7_7_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_7_7_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_7_7_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_7_7_ENDADDR_SHIFT)) & XRDC_MRGD_W1_7_7_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_7_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_7_7_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_7_7_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_7_7_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_7_D0SEL_SHIFT)) & XRDC_MRGD_W2_7_7_D0SEL_MASK)

#define XRDC_MRGD_W2_7_7_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_7_7_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_7_7_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_7_D1SEL_SHIFT)) & XRDC_MRGD_W2_7_7_D1SEL_MASK)

#define XRDC_MRGD_W2_7_7_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_7_7_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_7_7_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_7_D2SEL_SHIFT)) & XRDC_MRGD_W2_7_7_D2SEL_MASK)

#define XRDC_MRGD_W2_7_7_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_7_7_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_7_7_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_7_D3SEL_SHIFT)) & XRDC_MRGD_W2_7_7_D3SEL_MASK)

#define XRDC_MRGD_W2_7_7_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_7_7_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_7_7_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_7_D4SEL_SHIFT)) & XRDC_MRGD_W2_7_7_D4SEL_MASK)

#define XRDC_MRGD_W2_7_7_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_7_7_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_7_7_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_7_D5SEL_SHIFT)) & XRDC_MRGD_W2_7_7_D5SEL_MASK)

#define XRDC_MRGD_W2_7_7_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_7_7_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_7_7_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_7_D6SEL_SHIFT)) & XRDC_MRGD_W2_7_7_D6SEL_MASK)

#define XRDC_MRGD_W2_7_7_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_7_7_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_7_7_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_7_D7SEL_SHIFT)) & XRDC_MRGD_W2_7_7_D7SEL_MASK)

#define XRDC_MRGD_W2_7_7_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_7_7_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_7_7_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_7_7_EALO_SHIFT)) & XRDC_MRGD_W2_7_7_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_7_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_7_7_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_7_7_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_7_7_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_7_EAL_SHIFT)) & XRDC_MRGD_W3_7_7_EAL_MASK)

#define XRDC_MRGD_W3_7_7_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_7_7_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_7_7_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_7_7_CR_SHIFT)) & XRDC_MRGD_W3_7_7_CR_MASK)
/*! @} */

/*! @name MRGD_W4_7_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_7_7_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_7_7_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_7_7_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_7_ACCSET1_SHIFT)) & XRDC_MRGD_W4_7_7_ACCSET1_MASK)

#define XRDC_MRGD_W4_7_7_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_7_7_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_7_7_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_7_LKAS1_SHIFT)) & XRDC_MRGD_W4_7_7_LKAS1_MASK)

#define XRDC_MRGD_W4_7_7_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_7_7_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_7_7_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_7_ACCSET2_SHIFT)) & XRDC_MRGD_W4_7_7_ACCSET2_MASK)

#define XRDC_MRGD_W4_7_7_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_7_7_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_7_7_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_7_LKAS2_SHIFT)) & XRDC_MRGD_W4_7_7_LKAS2_MASK)

#define XRDC_MRGD_W4_7_7_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_7_7_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_7_7_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_7_LK2_SHIFT)) & XRDC_MRGD_W4_7_7_LK2_MASK)

#define XRDC_MRGD_W4_7_7_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_7_7_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_7_7_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_7_7_VLD_SHIFT)) & XRDC_MRGD_W4_7_7_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_8_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_8_0_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_8_0_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_8_0_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_8_0_SRTADDR_SHIFT)) & XRDC_MRGD_W0_8_0_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_8_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_8_0_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_8_0_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_8_0_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_8_0_ENDADDR_SHIFT)) & XRDC_MRGD_W1_8_0_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_8_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_8_0_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_8_0_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_8_0_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_0_D0SEL_SHIFT)) & XRDC_MRGD_W2_8_0_D0SEL_MASK)

#define XRDC_MRGD_W2_8_0_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_8_0_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_8_0_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_0_D1SEL_SHIFT)) & XRDC_MRGD_W2_8_0_D1SEL_MASK)

#define XRDC_MRGD_W2_8_0_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_8_0_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_8_0_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_0_D2SEL_SHIFT)) & XRDC_MRGD_W2_8_0_D2SEL_MASK)

#define XRDC_MRGD_W2_8_0_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_8_0_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_8_0_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_0_D3SEL_SHIFT)) & XRDC_MRGD_W2_8_0_D3SEL_MASK)

#define XRDC_MRGD_W2_8_0_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_8_0_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_8_0_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_0_D4SEL_SHIFT)) & XRDC_MRGD_W2_8_0_D4SEL_MASK)

#define XRDC_MRGD_W2_8_0_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_8_0_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_8_0_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_0_D5SEL_SHIFT)) & XRDC_MRGD_W2_8_0_D5SEL_MASK)

#define XRDC_MRGD_W2_8_0_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_8_0_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_8_0_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_0_D6SEL_SHIFT)) & XRDC_MRGD_W2_8_0_D6SEL_MASK)

#define XRDC_MRGD_W2_8_0_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_8_0_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_8_0_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_0_D7SEL_SHIFT)) & XRDC_MRGD_W2_8_0_D7SEL_MASK)

#define XRDC_MRGD_W2_8_0_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_8_0_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_8_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_0_EALO_SHIFT)) & XRDC_MRGD_W2_8_0_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_8_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_8_0_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_8_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_8_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_8_0_EAL_SHIFT)) & XRDC_MRGD_W3_8_0_EAL_MASK)

#define XRDC_MRGD_W3_8_0_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_8_0_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_8_0_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_8_0_CR_SHIFT)) & XRDC_MRGD_W3_8_0_CR_MASK)
/*! @} */

/*! @name MRGD_W4_8_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_8_0_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_8_0_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_8_0_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_0_ACCSET1_SHIFT)) & XRDC_MRGD_W4_8_0_ACCSET1_MASK)

#define XRDC_MRGD_W4_8_0_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_8_0_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_8_0_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_0_LKAS1_SHIFT)) & XRDC_MRGD_W4_8_0_LKAS1_MASK)

#define XRDC_MRGD_W4_8_0_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_8_0_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_8_0_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_0_ACCSET2_SHIFT)) & XRDC_MRGD_W4_8_0_ACCSET2_MASK)

#define XRDC_MRGD_W4_8_0_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_8_0_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_8_0_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_0_LKAS2_SHIFT)) & XRDC_MRGD_W4_8_0_LKAS2_MASK)

#define XRDC_MRGD_W4_8_0_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_8_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_8_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_0_LK2_SHIFT)) & XRDC_MRGD_W4_8_0_LK2_MASK)

#define XRDC_MRGD_W4_8_0_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_8_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_8_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_0_VLD_SHIFT)) & XRDC_MRGD_W4_8_0_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_8_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_8_1_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_8_1_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_8_1_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_8_1_SRTADDR_SHIFT)) & XRDC_MRGD_W0_8_1_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_8_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_8_1_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_8_1_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_8_1_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_8_1_ENDADDR_SHIFT)) & XRDC_MRGD_W1_8_1_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_8_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_8_1_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_8_1_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_8_1_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_1_D0SEL_SHIFT)) & XRDC_MRGD_W2_8_1_D0SEL_MASK)

#define XRDC_MRGD_W2_8_1_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_8_1_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_8_1_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_1_D1SEL_SHIFT)) & XRDC_MRGD_W2_8_1_D1SEL_MASK)

#define XRDC_MRGD_W2_8_1_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_8_1_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_8_1_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_1_D2SEL_SHIFT)) & XRDC_MRGD_W2_8_1_D2SEL_MASK)

#define XRDC_MRGD_W2_8_1_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_8_1_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_8_1_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_1_D3SEL_SHIFT)) & XRDC_MRGD_W2_8_1_D3SEL_MASK)

#define XRDC_MRGD_W2_8_1_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_8_1_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_8_1_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_1_D4SEL_SHIFT)) & XRDC_MRGD_W2_8_1_D4SEL_MASK)

#define XRDC_MRGD_W2_8_1_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_8_1_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_8_1_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_1_D5SEL_SHIFT)) & XRDC_MRGD_W2_8_1_D5SEL_MASK)

#define XRDC_MRGD_W2_8_1_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_8_1_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_8_1_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_1_D6SEL_SHIFT)) & XRDC_MRGD_W2_8_1_D6SEL_MASK)

#define XRDC_MRGD_W2_8_1_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_8_1_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_8_1_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_1_D7SEL_SHIFT)) & XRDC_MRGD_W2_8_1_D7SEL_MASK)

#define XRDC_MRGD_W2_8_1_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_8_1_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_8_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_1_EALO_SHIFT)) & XRDC_MRGD_W2_8_1_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_8_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_8_1_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_8_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_8_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_8_1_EAL_SHIFT)) & XRDC_MRGD_W3_8_1_EAL_MASK)

#define XRDC_MRGD_W3_8_1_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_8_1_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_8_1_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_8_1_CR_SHIFT)) & XRDC_MRGD_W3_8_1_CR_MASK)
/*! @} */

/*! @name MRGD_W4_8_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_8_1_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_8_1_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_8_1_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_1_ACCSET1_SHIFT)) & XRDC_MRGD_W4_8_1_ACCSET1_MASK)

#define XRDC_MRGD_W4_8_1_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_8_1_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_8_1_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_1_LKAS1_SHIFT)) & XRDC_MRGD_W4_8_1_LKAS1_MASK)

#define XRDC_MRGD_W4_8_1_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_8_1_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_8_1_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_1_ACCSET2_SHIFT)) & XRDC_MRGD_W4_8_1_ACCSET2_MASK)

#define XRDC_MRGD_W4_8_1_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_8_1_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_8_1_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_1_LKAS2_SHIFT)) & XRDC_MRGD_W4_8_1_LKAS2_MASK)

#define XRDC_MRGD_W4_8_1_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_8_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_8_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_1_LK2_SHIFT)) & XRDC_MRGD_W4_8_1_LK2_MASK)

#define XRDC_MRGD_W4_8_1_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_8_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_8_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_1_VLD_SHIFT)) & XRDC_MRGD_W4_8_1_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_8_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_8_2_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_8_2_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_8_2_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_8_2_SRTADDR_SHIFT)) & XRDC_MRGD_W0_8_2_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_8_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_8_2_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_8_2_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_8_2_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_8_2_ENDADDR_SHIFT)) & XRDC_MRGD_W1_8_2_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_8_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_8_2_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_8_2_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_8_2_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_2_D0SEL_SHIFT)) & XRDC_MRGD_W2_8_2_D0SEL_MASK)

#define XRDC_MRGD_W2_8_2_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_8_2_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_8_2_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_2_D1SEL_SHIFT)) & XRDC_MRGD_W2_8_2_D1SEL_MASK)

#define XRDC_MRGD_W2_8_2_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_8_2_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_8_2_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_2_D2SEL_SHIFT)) & XRDC_MRGD_W2_8_2_D2SEL_MASK)

#define XRDC_MRGD_W2_8_2_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_8_2_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_8_2_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_2_D3SEL_SHIFT)) & XRDC_MRGD_W2_8_2_D3SEL_MASK)

#define XRDC_MRGD_W2_8_2_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_8_2_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_8_2_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_2_D4SEL_SHIFT)) & XRDC_MRGD_W2_8_2_D4SEL_MASK)

#define XRDC_MRGD_W2_8_2_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_8_2_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_8_2_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_2_D5SEL_SHIFT)) & XRDC_MRGD_W2_8_2_D5SEL_MASK)

#define XRDC_MRGD_W2_8_2_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_8_2_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_8_2_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_2_D6SEL_SHIFT)) & XRDC_MRGD_W2_8_2_D6SEL_MASK)

#define XRDC_MRGD_W2_8_2_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_8_2_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_8_2_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_2_D7SEL_SHIFT)) & XRDC_MRGD_W2_8_2_D7SEL_MASK)

#define XRDC_MRGD_W2_8_2_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_8_2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_8_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_2_EALO_SHIFT)) & XRDC_MRGD_W2_8_2_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_8_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_8_2_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_8_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_8_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_8_2_EAL_SHIFT)) & XRDC_MRGD_W3_8_2_EAL_MASK)

#define XRDC_MRGD_W3_8_2_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_8_2_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_8_2_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_8_2_CR_SHIFT)) & XRDC_MRGD_W3_8_2_CR_MASK)
/*! @} */

/*! @name MRGD_W4_8_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_8_2_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_8_2_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_8_2_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_2_ACCSET1_SHIFT)) & XRDC_MRGD_W4_8_2_ACCSET1_MASK)

#define XRDC_MRGD_W4_8_2_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_8_2_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_8_2_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_2_LKAS1_SHIFT)) & XRDC_MRGD_W4_8_2_LKAS1_MASK)

#define XRDC_MRGD_W4_8_2_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_8_2_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_8_2_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_2_ACCSET2_SHIFT)) & XRDC_MRGD_W4_8_2_ACCSET2_MASK)

#define XRDC_MRGD_W4_8_2_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_8_2_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_8_2_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_2_LKAS2_SHIFT)) & XRDC_MRGD_W4_8_2_LKAS2_MASK)

#define XRDC_MRGD_W4_8_2_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_8_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_8_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_2_LK2_SHIFT)) & XRDC_MRGD_W4_8_2_LK2_MASK)

#define XRDC_MRGD_W4_8_2_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_8_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_8_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_2_VLD_SHIFT)) & XRDC_MRGD_W4_8_2_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_8_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_8_3_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_8_3_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_8_3_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_8_3_SRTADDR_SHIFT)) & XRDC_MRGD_W0_8_3_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_8_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_8_3_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_8_3_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_8_3_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_8_3_ENDADDR_SHIFT)) & XRDC_MRGD_W1_8_3_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_8_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_8_3_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_8_3_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_8_3_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_3_D0SEL_SHIFT)) & XRDC_MRGD_W2_8_3_D0SEL_MASK)

#define XRDC_MRGD_W2_8_3_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_8_3_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_8_3_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_3_D1SEL_SHIFT)) & XRDC_MRGD_W2_8_3_D1SEL_MASK)

#define XRDC_MRGD_W2_8_3_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_8_3_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_8_3_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_3_D2SEL_SHIFT)) & XRDC_MRGD_W2_8_3_D2SEL_MASK)

#define XRDC_MRGD_W2_8_3_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_8_3_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_8_3_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_3_D3SEL_SHIFT)) & XRDC_MRGD_W2_8_3_D3SEL_MASK)

#define XRDC_MRGD_W2_8_3_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_8_3_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_8_3_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_3_D4SEL_SHIFT)) & XRDC_MRGD_W2_8_3_D4SEL_MASK)

#define XRDC_MRGD_W2_8_3_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_8_3_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_8_3_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_3_D5SEL_SHIFT)) & XRDC_MRGD_W2_8_3_D5SEL_MASK)

#define XRDC_MRGD_W2_8_3_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_8_3_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_8_3_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_3_D6SEL_SHIFT)) & XRDC_MRGD_W2_8_3_D6SEL_MASK)

#define XRDC_MRGD_W2_8_3_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_8_3_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_8_3_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_3_D7SEL_SHIFT)) & XRDC_MRGD_W2_8_3_D7SEL_MASK)

#define XRDC_MRGD_W2_8_3_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_8_3_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_8_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_8_3_EALO_SHIFT)) & XRDC_MRGD_W2_8_3_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_8_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_8_3_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_8_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_8_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_8_3_EAL_SHIFT)) & XRDC_MRGD_W3_8_3_EAL_MASK)

#define XRDC_MRGD_W3_8_3_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_8_3_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_8_3_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_8_3_CR_SHIFT)) & XRDC_MRGD_W3_8_3_CR_MASK)
/*! @} */

/*! @name MRGD_W4_8_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_8_3_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_8_3_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_8_3_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_3_ACCSET1_SHIFT)) & XRDC_MRGD_W4_8_3_ACCSET1_MASK)

#define XRDC_MRGD_W4_8_3_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_8_3_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_8_3_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_3_LKAS1_SHIFT)) & XRDC_MRGD_W4_8_3_LKAS1_MASK)

#define XRDC_MRGD_W4_8_3_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_8_3_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_8_3_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_3_ACCSET2_SHIFT)) & XRDC_MRGD_W4_8_3_ACCSET2_MASK)

#define XRDC_MRGD_W4_8_3_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_8_3_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_8_3_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_3_LKAS2_SHIFT)) & XRDC_MRGD_W4_8_3_LKAS2_MASK)

#define XRDC_MRGD_W4_8_3_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_8_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_8_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_3_LK2_SHIFT)) & XRDC_MRGD_W4_8_3_LK2_MASK)

#define XRDC_MRGD_W4_8_3_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_8_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_8_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_8_3_VLD_SHIFT)) & XRDC_MRGD_W4_8_3_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_9_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_9_0_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_9_0_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_9_0_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_9_0_SRTADDR_SHIFT)) & XRDC_MRGD_W0_9_0_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_9_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_9_0_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_9_0_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_9_0_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_9_0_ENDADDR_SHIFT)) & XRDC_MRGD_W1_9_0_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_9_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_9_0_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_9_0_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_9_0_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_0_D0SEL_SHIFT)) & XRDC_MRGD_W2_9_0_D0SEL_MASK)

#define XRDC_MRGD_W2_9_0_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_9_0_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_9_0_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_0_D1SEL_SHIFT)) & XRDC_MRGD_W2_9_0_D1SEL_MASK)

#define XRDC_MRGD_W2_9_0_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_9_0_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_9_0_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_0_D2SEL_SHIFT)) & XRDC_MRGD_W2_9_0_D2SEL_MASK)

#define XRDC_MRGD_W2_9_0_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_9_0_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_9_0_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_0_D3SEL_SHIFT)) & XRDC_MRGD_W2_9_0_D3SEL_MASK)

#define XRDC_MRGD_W2_9_0_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_9_0_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_9_0_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_0_D4SEL_SHIFT)) & XRDC_MRGD_W2_9_0_D4SEL_MASK)

#define XRDC_MRGD_W2_9_0_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_9_0_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_9_0_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_0_D5SEL_SHIFT)) & XRDC_MRGD_W2_9_0_D5SEL_MASK)

#define XRDC_MRGD_W2_9_0_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_9_0_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_9_0_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_0_D6SEL_SHIFT)) & XRDC_MRGD_W2_9_0_D6SEL_MASK)

#define XRDC_MRGD_W2_9_0_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_9_0_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_9_0_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_0_D7SEL_SHIFT)) & XRDC_MRGD_W2_9_0_D7SEL_MASK)

#define XRDC_MRGD_W2_9_0_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_9_0_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_9_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_0_EALO_SHIFT)) & XRDC_MRGD_W2_9_0_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_9_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_9_0_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_9_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_9_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_0_EAL_SHIFT)) & XRDC_MRGD_W3_9_0_EAL_MASK)

#define XRDC_MRGD_W3_9_0_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_9_0_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_9_0_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_0_CR_SHIFT)) & XRDC_MRGD_W3_9_0_CR_MASK)
/*! @} */

/*! @name MRGD_W4_9_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_9_0_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_9_0_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_9_0_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_0_ACCSET1_SHIFT)) & XRDC_MRGD_W4_9_0_ACCSET1_MASK)

#define XRDC_MRGD_W4_9_0_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_9_0_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_9_0_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_0_LKAS1_SHIFT)) & XRDC_MRGD_W4_9_0_LKAS1_MASK)

#define XRDC_MRGD_W4_9_0_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_9_0_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_9_0_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_0_ACCSET2_SHIFT)) & XRDC_MRGD_W4_9_0_ACCSET2_MASK)

#define XRDC_MRGD_W4_9_0_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_9_0_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_9_0_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_0_LKAS2_SHIFT)) & XRDC_MRGD_W4_9_0_LKAS2_MASK)

#define XRDC_MRGD_W4_9_0_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_9_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_9_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_0_LK2_SHIFT)) & XRDC_MRGD_W4_9_0_LK2_MASK)

#define XRDC_MRGD_W4_9_0_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_9_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_9_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_0_VLD_SHIFT)) & XRDC_MRGD_W4_9_0_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_9_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_9_1_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_9_1_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_9_1_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_9_1_SRTADDR_SHIFT)) & XRDC_MRGD_W0_9_1_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_9_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_9_1_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_9_1_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_9_1_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_9_1_ENDADDR_SHIFT)) & XRDC_MRGD_W1_9_1_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_9_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_9_1_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_9_1_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_9_1_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_1_D0SEL_SHIFT)) & XRDC_MRGD_W2_9_1_D0SEL_MASK)

#define XRDC_MRGD_W2_9_1_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_9_1_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_9_1_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_1_D1SEL_SHIFT)) & XRDC_MRGD_W2_9_1_D1SEL_MASK)

#define XRDC_MRGD_W2_9_1_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_9_1_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_9_1_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_1_D2SEL_SHIFT)) & XRDC_MRGD_W2_9_1_D2SEL_MASK)

#define XRDC_MRGD_W2_9_1_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_9_1_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_9_1_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_1_D3SEL_SHIFT)) & XRDC_MRGD_W2_9_1_D3SEL_MASK)

#define XRDC_MRGD_W2_9_1_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_9_1_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_9_1_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_1_D4SEL_SHIFT)) & XRDC_MRGD_W2_9_1_D4SEL_MASK)

#define XRDC_MRGD_W2_9_1_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_9_1_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_9_1_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_1_D5SEL_SHIFT)) & XRDC_MRGD_W2_9_1_D5SEL_MASK)

#define XRDC_MRGD_W2_9_1_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_9_1_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_9_1_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_1_D6SEL_SHIFT)) & XRDC_MRGD_W2_9_1_D6SEL_MASK)

#define XRDC_MRGD_W2_9_1_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_9_1_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_9_1_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_1_D7SEL_SHIFT)) & XRDC_MRGD_W2_9_1_D7SEL_MASK)

#define XRDC_MRGD_W2_9_1_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_9_1_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_9_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_1_EALO_SHIFT)) & XRDC_MRGD_W2_9_1_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_9_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_9_1_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_9_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_9_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_1_EAL_SHIFT)) & XRDC_MRGD_W3_9_1_EAL_MASK)

#define XRDC_MRGD_W3_9_1_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_9_1_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_9_1_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_1_CR_SHIFT)) & XRDC_MRGD_W3_9_1_CR_MASK)
/*! @} */

/*! @name MRGD_W4_9_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_9_1_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_9_1_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_9_1_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_1_ACCSET1_SHIFT)) & XRDC_MRGD_W4_9_1_ACCSET1_MASK)

#define XRDC_MRGD_W4_9_1_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_9_1_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_9_1_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_1_LKAS1_SHIFT)) & XRDC_MRGD_W4_9_1_LKAS1_MASK)

#define XRDC_MRGD_W4_9_1_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_9_1_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_9_1_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_1_ACCSET2_SHIFT)) & XRDC_MRGD_W4_9_1_ACCSET2_MASK)

#define XRDC_MRGD_W4_9_1_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_9_1_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_9_1_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_1_LKAS2_SHIFT)) & XRDC_MRGD_W4_9_1_LKAS2_MASK)

#define XRDC_MRGD_W4_9_1_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_9_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_9_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_1_LK2_SHIFT)) & XRDC_MRGD_W4_9_1_LK2_MASK)

#define XRDC_MRGD_W4_9_1_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_9_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_9_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_1_VLD_SHIFT)) & XRDC_MRGD_W4_9_1_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_9_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_9_2_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_9_2_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_9_2_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_9_2_SRTADDR_SHIFT)) & XRDC_MRGD_W0_9_2_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_9_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_9_2_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_9_2_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_9_2_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_9_2_ENDADDR_SHIFT)) & XRDC_MRGD_W1_9_2_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_9_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_9_2_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_9_2_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_9_2_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_2_D0SEL_SHIFT)) & XRDC_MRGD_W2_9_2_D0SEL_MASK)

#define XRDC_MRGD_W2_9_2_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_9_2_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_9_2_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_2_D1SEL_SHIFT)) & XRDC_MRGD_W2_9_2_D1SEL_MASK)

#define XRDC_MRGD_W2_9_2_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_9_2_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_9_2_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_2_D2SEL_SHIFT)) & XRDC_MRGD_W2_9_2_D2SEL_MASK)

#define XRDC_MRGD_W2_9_2_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_9_2_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_9_2_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_2_D3SEL_SHIFT)) & XRDC_MRGD_W2_9_2_D3SEL_MASK)

#define XRDC_MRGD_W2_9_2_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_9_2_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_9_2_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_2_D4SEL_SHIFT)) & XRDC_MRGD_W2_9_2_D4SEL_MASK)

#define XRDC_MRGD_W2_9_2_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_9_2_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_9_2_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_2_D5SEL_SHIFT)) & XRDC_MRGD_W2_9_2_D5SEL_MASK)

#define XRDC_MRGD_W2_9_2_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_9_2_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_9_2_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_2_D6SEL_SHIFT)) & XRDC_MRGD_W2_9_2_D6SEL_MASK)

#define XRDC_MRGD_W2_9_2_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_9_2_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_9_2_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_2_D7SEL_SHIFT)) & XRDC_MRGD_W2_9_2_D7SEL_MASK)

#define XRDC_MRGD_W2_9_2_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_9_2_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_9_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_2_EALO_SHIFT)) & XRDC_MRGD_W2_9_2_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_9_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_9_2_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_9_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_9_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_2_EAL_SHIFT)) & XRDC_MRGD_W3_9_2_EAL_MASK)

#define XRDC_MRGD_W3_9_2_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_9_2_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_9_2_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_2_CR_SHIFT)) & XRDC_MRGD_W3_9_2_CR_MASK)
/*! @} */

/*! @name MRGD_W4_9_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_9_2_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_9_2_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_9_2_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_2_ACCSET1_SHIFT)) & XRDC_MRGD_W4_9_2_ACCSET1_MASK)

#define XRDC_MRGD_W4_9_2_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_9_2_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_9_2_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_2_LKAS1_SHIFT)) & XRDC_MRGD_W4_9_2_LKAS1_MASK)

#define XRDC_MRGD_W4_9_2_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_9_2_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_9_2_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_2_ACCSET2_SHIFT)) & XRDC_MRGD_W4_9_2_ACCSET2_MASK)

#define XRDC_MRGD_W4_9_2_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_9_2_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_9_2_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_2_LKAS2_SHIFT)) & XRDC_MRGD_W4_9_2_LKAS2_MASK)

#define XRDC_MRGD_W4_9_2_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_9_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_9_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_2_LK2_SHIFT)) & XRDC_MRGD_W4_9_2_LK2_MASK)

#define XRDC_MRGD_W4_9_2_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_9_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_9_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_2_VLD_SHIFT)) & XRDC_MRGD_W4_9_2_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_9_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_9_3_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_9_3_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_9_3_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_9_3_SRTADDR_SHIFT)) & XRDC_MRGD_W0_9_3_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_9_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_9_3_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_9_3_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_9_3_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_9_3_ENDADDR_SHIFT)) & XRDC_MRGD_W1_9_3_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_9_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_9_3_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_9_3_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_9_3_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_3_D0SEL_SHIFT)) & XRDC_MRGD_W2_9_3_D0SEL_MASK)

#define XRDC_MRGD_W2_9_3_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_9_3_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_9_3_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_3_D1SEL_SHIFT)) & XRDC_MRGD_W2_9_3_D1SEL_MASK)

#define XRDC_MRGD_W2_9_3_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_9_3_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_9_3_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_3_D2SEL_SHIFT)) & XRDC_MRGD_W2_9_3_D2SEL_MASK)

#define XRDC_MRGD_W2_9_3_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_9_3_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_9_3_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_3_D3SEL_SHIFT)) & XRDC_MRGD_W2_9_3_D3SEL_MASK)

#define XRDC_MRGD_W2_9_3_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_9_3_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_9_3_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_3_D4SEL_SHIFT)) & XRDC_MRGD_W2_9_3_D4SEL_MASK)

#define XRDC_MRGD_W2_9_3_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_9_3_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_9_3_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_3_D5SEL_SHIFT)) & XRDC_MRGD_W2_9_3_D5SEL_MASK)

#define XRDC_MRGD_W2_9_3_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_9_3_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_9_3_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_3_D6SEL_SHIFT)) & XRDC_MRGD_W2_9_3_D6SEL_MASK)

#define XRDC_MRGD_W2_9_3_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_9_3_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_9_3_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_3_D7SEL_SHIFT)) & XRDC_MRGD_W2_9_3_D7SEL_MASK)

#define XRDC_MRGD_W2_9_3_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_9_3_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_9_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_3_EALO_SHIFT)) & XRDC_MRGD_W2_9_3_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_9_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_9_3_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_9_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_9_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_3_EAL_SHIFT)) & XRDC_MRGD_W3_9_3_EAL_MASK)

#define XRDC_MRGD_W3_9_3_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_9_3_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_9_3_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_3_CR_SHIFT)) & XRDC_MRGD_W3_9_3_CR_MASK)
/*! @} */

/*! @name MRGD_W4_9_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_9_3_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_9_3_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_9_3_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_3_ACCSET1_SHIFT)) & XRDC_MRGD_W4_9_3_ACCSET1_MASK)

#define XRDC_MRGD_W4_9_3_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_9_3_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_9_3_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_3_LKAS1_SHIFT)) & XRDC_MRGD_W4_9_3_LKAS1_MASK)

#define XRDC_MRGD_W4_9_3_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_9_3_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_9_3_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_3_ACCSET2_SHIFT)) & XRDC_MRGD_W4_9_3_ACCSET2_MASK)

#define XRDC_MRGD_W4_9_3_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_9_3_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_9_3_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_3_LKAS2_SHIFT)) & XRDC_MRGD_W4_9_3_LKAS2_MASK)

#define XRDC_MRGD_W4_9_3_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_9_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_9_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_3_LK2_SHIFT)) & XRDC_MRGD_W4_9_3_LK2_MASK)

#define XRDC_MRGD_W4_9_3_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_9_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_9_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_3_VLD_SHIFT)) & XRDC_MRGD_W4_9_3_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_9_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_9_4_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_9_4_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_9_4_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_9_4_SRTADDR_SHIFT)) & XRDC_MRGD_W0_9_4_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_9_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_9_4_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_9_4_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_9_4_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_9_4_ENDADDR_SHIFT)) & XRDC_MRGD_W1_9_4_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_9_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_9_4_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_9_4_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_9_4_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_4_D0SEL_SHIFT)) & XRDC_MRGD_W2_9_4_D0SEL_MASK)

#define XRDC_MRGD_W2_9_4_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_9_4_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_9_4_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_4_D1SEL_SHIFT)) & XRDC_MRGD_W2_9_4_D1SEL_MASK)

#define XRDC_MRGD_W2_9_4_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_9_4_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_9_4_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_4_D2SEL_SHIFT)) & XRDC_MRGD_W2_9_4_D2SEL_MASK)

#define XRDC_MRGD_W2_9_4_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_9_4_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_9_4_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_4_D3SEL_SHIFT)) & XRDC_MRGD_W2_9_4_D3SEL_MASK)

#define XRDC_MRGD_W2_9_4_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_9_4_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_9_4_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_4_D4SEL_SHIFT)) & XRDC_MRGD_W2_9_4_D4SEL_MASK)

#define XRDC_MRGD_W2_9_4_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_9_4_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_9_4_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_4_D5SEL_SHIFT)) & XRDC_MRGD_W2_9_4_D5SEL_MASK)

#define XRDC_MRGD_W2_9_4_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_9_4_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_9_4_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_4_D6SEL_SHIFT)) & XRDC_MRGD_W2_9_4_D6SEL_MASK)

#define XRDC_MRGD_W2_9_4_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_9_4_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_9_4_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_4_D7SEL_SHIFT)) & XRDC_MRGD_W2_9_4_D7SEL_MASK)

#define XRDC_MRGD_W2_9_4_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_9_4_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_9_4_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_4_EALO_SHIFT)) & XRDC_MRGD_W2_9_4_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_9_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_9_4_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_9_4_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_9_4_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_4_EAL_SHIFT)) & XRDC_MRGD_W3_9_4_EAL_MASK)

#define XRDC_MRGD_W3_9_4_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_9_4_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_9_4_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_4_CR_SHIFT)) & XRDC_MRGD_W3_9_4_CR_MASK)
/*! @} */

/*! @name MRGD_W4_9_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_9_4_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_9_4_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_9_4_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_4_ACCSET1_SHIFT)) & XRDC_MRGD_W4_9_4_ACCSET1_MASK)

#define XRDC_MRGD_W4_9_4_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_9_4_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_9_4_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_4_LKAS1_SHIFT)) & XRDC_MRGD_W4_9_4_LKAS1_MASK)

#define XRDC_MRGD_W4_9_4_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_9_4_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_9_4_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_4_ACCSET2_SHIFT)) & XRDC_MRGD_W4_9_4_ACCSET2_MASK)

#define XRDC_MRGD_W4_9_4_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_9_4_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_9_4_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_4_LKAS2_SHIFT)) & XRDC_MRGD_W4_9_4_LKAS2_MASK)

#define XRDC_MRGD_W4_9_4_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_9_4_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_9_4_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_4_LK2_SHIFT)) & XRDC_MRGD_W4_9_4_LK2_MASK)

#define XRDC_MRGD_W4_9_4_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_9_4_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_9_4_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_4_VLD_SHIFT)) & XRDC_MRGD_W4_9_4_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_9_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_9_5_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_9_5_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_9_5_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_9_5_SRTADDR_SHIFT)) & XRDC_MRGD_W0_9_5_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_9_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_9_5_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_9_5_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_9_5_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_9_5_ENDADDR_SHIFT)) & XRDC_MRGD_W1_9_5_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_9_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_9_5_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_9_5_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_9_5_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_5_D0SEL_SHIFT)) & XRDC_MRGD_W2_9_5_D0SEL_MASK)

#define XRDC_MRGD_W2_9_5_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_9_5_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_9_5_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_5_D1SEL_SHIFT)) & XRDC_MRGD_W2_9_5_D1SEL_MASK)

#define XRDC_MRGD_W2_9_5_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_9_5_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_9_5_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_5_D2SEL_SHIFT)) & XRDC_MRGD_W2_9_5_D2SEL_MASK)

#define XRDC_MRGD_W2_9_5_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_9_5_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_9_5_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_5_D3SEL_SHIFT)) & XRDC_MRGD_W2_9_5_D3SEL_MASK)

#define XRDC_MRGD_W2_9_5_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_9_5_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_9_5_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_5_D4SEL_SHIFT)) & XRDC_MRGD_W2_9_5_D4SEL_MASK)

#define XRDC_MRGD_W2_9_5_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_9_5_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_9_5_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_5_D5SEL_SHIFT)) & XRDC_MRGD_W2_9_5_D5SEL_MASK)

#define XRDC_MRGD_W2_9_5_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_9_5_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_9_5_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_5_D6SEL_SHIFT)) & XRDC_MRGD_W2_9_5_D6SEL_MASK)

#define XRDC_MRGD_W2_9_5_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_9_5_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_9_5_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_5_D7SEL_SHIFT)) & XRDC_MRGD_W2_9_5_D7SEL_MASK)

#define XRDC_MRGD_W2_9_5_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_9_5_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_9_5_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_5_EALO_SHIFT)) & XRDC_MRGD_W2_9_5_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_9_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_9_5_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_9_5_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_9_5_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_5_EAL_SHIFT)) & XRDC_MRGD_W3_9_5_EAL_MASK)

#define XRDC_MRGD_W3_9_5_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_9_5_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_9_5_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_5_CR_SHIFT)) & XRDC_MRGD_W3_9_5_CR_MASK)
/*! @} */

/*! @name MRGD_W4_9_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_9_5_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_9_5_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_9_5_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_5_ACCSET1_SHIFT)) & XRDC_MRGD_W4_9_5_ACCSET1_MASK)

#define XRDC_MRGD_W4_9_5_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_9_5_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_9_5_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_5_LKAS1_SHIFT)) & XRDC_MRGD_W4_9_5_LKAS1_MASK)

#define XRDC_MRGD_W4_9_5_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_9_5_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_9_5_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_5_ACCSET2_SHIFT)) & XRDC_MRGD_W4_9_5_ACCSET2_MASK)

#define XRDC_MRGD_W4_9_5_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_9_5_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_9_5_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_5_LKAS2_SHIFT)) & XRDC_MRGD_W4_9_5_LKAS2_MASK)

#define XRDC_MRGD_W4_9_5_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_9_5_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_9_5_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_5_LK2_SHIFT)) & XRDC_MRGD_W4_9_5_LK2_MASK)

#define XRDC_MRGD_W4_9_5_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_9_5_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_9_5_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_5_VLD_SHIFT)) & XRDC_MRGD_W4_9_5_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_9_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_9_6_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_9_6_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_9_6_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_9_6_SRTADDR_SHIFT)) & XRDC_MRGD_W0_9_6_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_9_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_9_6_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_9_6_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_9_6_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_9_6_ENDADDR_SHIFT)) & XRDC_MRGD_W1_9_6_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_9_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_9_6_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_9_6_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_9_6_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_6_D0SEL_SHIFT)) & XRDC_MRGD_W2_9_6_D0SEL_MASK)

#define XRDC_MRGD_W2_9_6_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_9_6_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_9_6_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_6_D1SEL_SHIFT)) & XRDC_MRGD_W2_9_6_D1SEL_MASK)

#define XRDC_MRGD_W2_9_6_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_9_6_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_9_6_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_6_D2SEL_SHIFT)) & XRDC_MRGD_W2_9_6_D2SEL_MASK)

#define XRDC_MRGD_W2_9_6_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_9_6_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_9_6_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_6_D3SEL_SHIFT)) & XRDC_MRGD_W2_9_6_D3SEL_MASK)

#define XRDC_MRGD_W2_9_6_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_9_6_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_9_6_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_6_D4SEL_SHIFT)) & XRDC_MRGD_W2_9_6_D4SEL_MASK)

#define XRDC_MRGD_W2_9_6_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_9_6_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_9_6_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_6_D5SEL_SHIFT)) & XRDC_MRGD_W2_9_6_D5SEL_MASK)

#define XRDC_MRGD_W2_9_6_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_9_6_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_9_6_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_6_D6SEL_SHIFT)) & XRDC_MRGD_W2_9_6_D6SEL_MASK)

#define XRDC_MRGD_W2_9_6_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_9_6_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_9_6_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_6_D7SEL_SHIFT)) & XRDC_MRGD_W2_9_6_D7SEL_MASK)

#define XRDC_MRGD_W2_9_6_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_9_6_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_9_6_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_6_EALO_SHIFT)) & XRDC_MRGD_W2_9_6_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_9_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_9_6_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_9_6_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_9_6_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_6_EAL_SHIFT)) & XRDC_MRGD_W3_9_6_EAL_MASK)

#define XRDC_MRGD_W3_9_6_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_9_6_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_9_6_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_6_CR_SHIFT)) & XRDC_MRGD_W3_9_6_CR_MASK)
/*! @} */

/*! @name MRGD_W4_9_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_9_6_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_9_6_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_9_6_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_6_ACCSET1_SHIFT)) & XRDC_MRGD_W4_9_6_ACCSET1_MASK)

#define XRDC_MRGD_W4_9_6_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_9_6_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_9_6_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_6_LKAS1_SHIFT)) & XRDC_MRGD_W4_9_6_LKAS1_MASK)

#define XRDC_MRGD_W4_9_6_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_9_6_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_9_6_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_6_ACCSET2_SHIFT)) & XRDC_MRGD_W4_9_6_ACCSET2_MASK)

#define XRDC_MRGD_W4_9_6_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_9_6_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_9_6_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_6_LKAS2_SHIFT)) & XRDC_MRGD_W4_9_6_LKAS2_MASK)

#define XRDC_MRGD_W4_9_6_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_9_6_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_9_6_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_6_LK2_SHIFT)) & XRDC_MRGD_W4_9_6_LK2_MASK)

#define XRDC_MRGD_W4_9_6_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_9_6_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_9_6_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_6_VLD_SHIFT)) & XRDC_MRGD_W4_9_6_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_9_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_9_7_SRTADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W0_9_7_SRTADDR_SHIFT           (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_9_7_SRTADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_9_7_SRTADDR_SHIFT)) & XRDC_MRGD_W0_9_7_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_9_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_9_7_ENDADDR_MASK            (0xFFFFFFE0U)
#define XRDC_MRGD_W1_9_7_ENDADDR_SHIFT           (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_9_7_ENDADDR(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_9_7_ENDADDR_SHIFT)) & XRDC_MRGD_W1_9_7_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_9_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_9_7_D0SEL_MASK              (0x7U)
#define XRDC_MRGD_W2_9_7_D0SEL_SHIFT             (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_9_7_D0SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_7_D0SEL_SHIFT)) & XRDC_MRGD_W2_9_7_D0SEL_MASK)

#define XRDC_MRGD_W2_9_7_D1SEL_MASK              (0x38U)
#define XRDC_MRGD_W2_9_7_D1SEL_SHIFT             (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_9_7_D1SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_7_D1SEL_SHIFT)) & XRDC_MRGD_W2_9_7_D1SEL_MASK)

#define XRDC_MRGD_W2_9_7_D2SEL_MASK              (0x1C0U)
#define XRDC_MRGD_W2_9_7_D2SEL_SHIFT             (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_9_7_D2SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_7_D2SEL_SHIFT)) & XRDC_MRGD_W2_9_7_D2SEL_MASK)

#define XRDC_MRGD_W2_9_7_D3SEL_MASK              (0xE00U)
#define XRDC_MRGD_W2_9_7_D3SEL_SHIFT             (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_9_7_D3SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_7_D3SEL_SHIFT)) & XRDC_MRGD_W2_9_7_D3SEL_MASK)

#define XRDC_MRGD_W2_9_7_D4SEL_MASK              (0x7000U)
#define XRDC_MRGD_W2_9_7_D4SEL_SHIFT             (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_9_7_D4SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_7_D4SEL_SHIFT)) & XRDC_MRGD_W2_9_7_D4SEL_MASK)

#define XRDC_MRGD_W2_9_7_D5SEL_MASK              (0x38000U)
#define XRDC_MRGD_W2_9_7_D5SEL_SHIFT             (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_9_7_D5SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_7_D5SEL_SHIFT)) & XRDC_MRGD_W2_9_7_D5SEL_MASK)

#define XRDC_MRGD_W2_9_7_D6SEL_MASK              (0x1C0000U)
#define XRDC_MRGD_W2_9_7_D6SEL_SHIFT             (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_9_7_D6SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_7_D6SEL_SHIFT)) & XRDC_MRGD_W2_9_7_D6SEL_MASK)

#define XRDC_MRGD_W2_9_7_D7SEL_MASK              (0xE00000U)
#define XRDC_MRGD_W2_9_7_D7SEL_SHIFT             (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_9_7_D7SEL(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_7_D7SEL_SHIFT)) & XRDC_MRGD_W2_9_7_D7SEL_MASK)

#define XRDC_MRGD_W2_9_7_EALO_MASK               (0xF000000U)
#define XRDC_MRGD_W2_9_7_EALO_SHIFT              (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_9_7_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_9_7_EALO_SHIFT)) & XRDC_MRGD_W2_9_7_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_9_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_9_7_EAL_MASK                (0x3000000U)
#define XRDC_MRGD_W3_9_7_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_9_7_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_7_EAL_SHIFT)) & XRDC_MRGD_W3_9_7_EAL_MASK)

#define XRDC_MRGD_W3_9_7_CR_MASK                 (0x80000000U)
#define XRDC_MRGD_W3_9_7_CR_SHIFT                (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_9_7_CR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_9_7_CR_SHIFT)) & XRDC_MRGD_W3_9_7_CR_MASK)
/*! @} */

/*! @name MRGD_W4_9_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_9_7_ACCSET1_MASK            (0xFFFU)
#define XRDC_MRGD_W4_9_7_ACCSET1_SHIFT           (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_9_7_ACCSET1(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_7_ACCSET1_SHIFT)) & XRDC_MRGD_W4_9_7_ACCSET1_MASK)

#define XRDC_MRGD_W4_9_7_LKAS1_MASK              (0x1000U)
#define XRDC_MRGD_W4_9_7_LKAS1_SHIFT             (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_9_7_LKAS1(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_7_LKAS1_SHIFT)) & XRDC_MRGD_W4_9_7_LKAS1_MASK)

#define XRDC_MRGD_W4_9_7_ACCSET2_MASK            (0xFFF0000U)
#define XRDC_MRGD_W4_9_7_ACCSET2_SHIFT           (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_9_7_ACCSET2(x)              (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_7_ACCSET2_SHIFT)) & XRDC_MRGD_W4_9_7_ACCSET2_MASK)

#define XRDC_MRGD_W4_9_7_LKAS2_MASK              (0x10000000U)
#define XRDC_MRGD_W4_9_7_LKAS2_SHIFT             (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_9_7_LKAS2(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_7_LKAS2_SHIFT)) & XRDC_MRGD_W4_9_7_LKAS2_MASK)

#define XRDC_MRGD_W4_9_7_LK2_MASK                (0x60000000U)
#define XRDC_MRGD_W4_9_7_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_9_7_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_7_LK2_SHIFT)) & XRDC_MRGD_W4_9_7_LK2_MASK)

#define XRDC_MRGD_W4_9_7_VLD_MASK                (0x80000000U)
#define XRDC_MRGD_W4_9_7_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_9_7_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_9_7_VLD_SHIFT)) & XRDC_MRGD_W4_9_7_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_10_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_10_0_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_10_0_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_10_0_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_10_0_SRTADDR_SHIFT)) & XRDC_MRGD_W0_10_0_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_10_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_10_0_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_10_0_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_10_0_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_10_0_ENDADDR_SHIFT)) & XRDC_MRGD_W1_10_0_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_10_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_10_0_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_10_0_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_10_0_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_0_D0SEL_SHIFT)) & XRDC_MRGD_W2_10_0_D0SEL_MASK)

#define XRDC_MRGD_W2_10_0_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_10_0_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_10_0_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_0_D1SEL_SHIFT)) & XRDC_MRGD_W2_10_0_D1SEL_MASK)

#define XRDC_MRGD_W2_10_0_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_10_0_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_10_0_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_0_D2SEL_SHIFT)) & XRDC_MRGD_W2_10_0_D2SEL_MASK)

#define XRDC_MRGD_W2_10_0_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_10_0_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_10_0_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_0_D3SEL_SHIFT)) & XRDC_MRGD_W2_10_0_D3SEL_MASK)

#define XRDC_MRGD_W2_10_0_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_10_0_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_10_0_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_0_D4SEL_SHIFT)) & XRDC_MRGD_W2_10_0_D4SEL_MASK)

#define XRDC_MRGD_W2_10_0_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_10_0_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_10_0_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_0_D5SEL_SHIFT)) & XRDC_MRGD_W2_10_0_D5SEL_MASK)

#define XRDC_MRGD_W2_10_0_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_10_0_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_10_0_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_0_D6SEL_SHIFT)) & XRDC_MRGD_W2_10_0_D6SEL_MASK)

#define XRDC_MRGD_W2_10_0_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_10_0_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_10_0_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_0_D7SEL_SHIFT)) & XRDC_MRGD_W2_10_0_D7SEL_MASK)

#define XRDC_MRGD_W2_10_0_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_10_0_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_10_0_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_0_EALO_SHIFT)) & XRDC_MRGD_W2_10_0_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_10_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_10_0_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_10_0_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_10_0_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_0_EAL_SHIFT)) & XRDC_MRGD_W3_10_0_EAL_MASK)

#define XRDC_MRGD_W3_10_0_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_10_0_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_10_0_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_0_CR_SHIFT)) & XRDC_MRGD_W3_10_0_CR_MASK)
/*! @} */

/*! @name MRGD_W4_10_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_10_0_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_10_0_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_10_0_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_0_ACCSET1_SHIFT)) & XRDC_MRGD_W4_10_0_ACCSET1_MASK)

#define XRDC_MRGD_W4_10_0_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_10_0_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_10_0_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_0_LKAS1_SHIFT)) & XRDC_MRGD_W4_10_0_LKAS1_MASK)

#define XRDC_MRGD_W4_10_0_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_10_0_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_10_0_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_0_ACCSET2_SHIFT)) & XRDC_MRGD_W4_10_0_ACCSET2_MASK)

#define XRDC_MRGD_W4_10_0_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_10_0_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_10_0_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_0_LKAS2_SHIFT)) & XRDC_MRGD_W4_10_0_LKAS2_MASK)

#define XRDC_MRGD_W4_10_0_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_10_0_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_10_0_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_0_LK2_SHIFT)) & XRDC_MRGD_W4_10_0_LK2_MASK)

#define XRDC_MRGD_W4_10_0_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_10_0_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_10_0_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_0_VLD_SHIFT)) & XRDC_MRGD_W4_10_0_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_10_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_10_1_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_10_1_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_10_1_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_10_1_SRTADDR_SHIFT)) & XRDC_MRGD_W0_10_1_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_10_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_10_1_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_10_1_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_10_1_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_10_1_ENDADDR_SHIFT)) & XRDC_MRGD_W1_10_1_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_10_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_10_1_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_10_1_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_10_1_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_1_D0SEL_SHIFT)) & XRDC_MRGD_W2_10_1_D0SEL_MASK)

#define XRDC_MRGD_W2_10_1_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_10_1_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_10_1_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_1_D1SEL_SHIFT)) & XRDC_MRGD_W2_10_1_D1SEL_MASK)

#define XRDC_MRGD_W2_10_1_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_10_1_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_10_1_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_1_D2SEL_SHIFT)) & XRDC_MRGD_W2_10_1_D2SEL_MASK)

#define XRDC_MRGD_W2_10_1_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_10_1_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_10_1_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_1_D3SEL_SHIFT)) & XRDC_MRGD_W2_10_1_D3SEL_MASK)

#define XRDC_MRGD_W2_10_1_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_10_1_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_10_1_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_1_D4SEL_SHIFT)) & XRDC_MRGD_W2_10_1_D4SEL_MASK)

#define XRDC_MRGD_W2_10_1_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_10_1_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_10_1_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_1_D5SEL_SHIFT)) & XRDC_MRGD_W2_10_1_D5SEL_MASK)

#define XRDC_MRGD_W2_10_1_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_10_1_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_10_1_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_1_D6SEL_SHIFT)) & XRDC_MRGD_W2_10_1_D6SEL_MASK)

#define XRDC_MRGD_W2_10_1_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_10_1_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_10_1_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_1_D7SEL_SHIFT)) & XRDC_MRGD_W2_10_1_D7SEL_MASK)

#define XRDC_MRGD_W2_10_1_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_10_1_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_10_1_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_1_EALO_SHIFT)) & XRDC_MRGD_W2_10_1_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_10_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_10_1_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_10_1_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_10_1_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_1_EAL_SHIFT)) & XRDC_MRGD_W3_10_1_EAL_MASK)

#define XRDC_MRGD_W3_10_1_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_10_1_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_10_1_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_1_CR_SHIFT)) & XRDC_MRGD_W3_10_1_CR_MASK)
/*! @} */

/*! @name MRGD_W4_10_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_10_1_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_10_1_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_10_1_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_1_ACCSET1_SHIFT)) & XRDC_MRGD_W4_10_1_ACCSET1_MASK)

#define XRDC_MRGD_W4_10_1_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_10_1_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_10_1_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_1_LKAS1_SHIFT)) & XRDC_MRGD_W4_10_1_LKAS1_MASK)

#define XRDC_MRGD_W4_10_1_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_10_1_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_10_1_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_1_ACCSET2_SHIFT)) & XRDC_MRGD_W4_10_1_ACCSET2_MASK)

#define XRDC_MRGD_W4_10_1_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_10_1_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_10_1_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_1_LKAS2_SHIFT)) & XRDC_MRGD_W4_10_1_LKAS2_MASK)

#define XRDC_MRGD_W4_10_1_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_10_1_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_10_1_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_1_LK2_SHIFT)) & XRDC_MRGD_W4_10_1_LK2_MASK)

#define XRDC_MRGD_W4_10_1_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_10_1_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_10_1_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_1_VLD_SHIFT)) & XRDC_MRGD_W4_10_1_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_10_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_10_2_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_10_2_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_10_2_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_10_2_SRTADDR_SHIFT)) & XRDC_MRGD_W0_10_2_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_10_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_10_2_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_10_2_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_10_2_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_10_2_ENDADDR_SHIFT)) & XRDC_MRGD_W1_10_2_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_10_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_10_2_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_10_2_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_10_2_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_2_D0SEL_SHIFT)) & XRDC_MRGD_W2_10_2_D0SEL_MASK)

#define XRDC_MRGD_W2_10_2_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_10_2_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_10_2_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_2_D1SEL_SHIFT)) & XRDC_MRGD_W2_10_2_D1SEL_MASK)

#define XRDC_MRGD_W2_10_2_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_10_2_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_10_2_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_2_D2SEL_SHIFT)) & XRDC_MRGD_W2_10_2_D2SEL_MASK)

#define XRDC_MRGD_W2_10_2_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_10_2_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_10_2_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_2_D3SEL_SHIFT)) & XRDC_MRGD_W2_10_2_D3SEL_MASK)

#define XRDC_MRGD_W2_10_2_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_10_2_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_10_2_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_2_D4SEL_SHIFT)) & XRDC_MRGD_W2_10_2_D4SEL_MASK)

#define XRDC_MRGD_W2_10_2_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_10_2_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_10_2_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_2_D5SEL_SHIFT)) & XRDC_MRGD_W2_10_2_D5SEL_MASK)

#define XRDC_MRGD_W2_10_2_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_10_2_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_10_2_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_2_D6SEL_SHIFT)) & XRDC_MRGD_W2_10_2_D6SEL_MASK)

#define XRDC_MRGD_W2_10_2_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_10_2_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_10_2_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_2_D7SEL_SHIFT)) & XRDC_MRGD_W2_10_2_D7SEL_MASK)

#define XRDC_MRGD_W2_10_2_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_10_2_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_10_2_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_2_EALO_SHIFT)) & XRDC_MRGD_W2_10_2_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_10_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_10_2_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_10_2_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_10_2_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_2_EAL_SHIFT)) & XRDC_MRGD_W3_10_2_EAL_MASK)

#define XRDC_MRGD_W3_10_2_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_10_2_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_10_2_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_2_CR_SHIFT)) & XRDC_MRGD_W3_10_2_CR_MASK)
/*! @} */

/*! @name MRGD_W4_10_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_10_2_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_10_2_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_10_2_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_2_ACCSET1_SHIFT)) & XRDC_MRGD_W4_10_2_ACCSET1_MASK)

#define XRDC_MRGD_W4_10_2_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_10_2_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_10_2_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_2_LKAS1_SHIFT)) & XRDC_MRGD_W4_10_2_LKAS1_MASK)

#define XRDC_MRGD_W4_10_2_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_10_2_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_10_2_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_2_ACCSET2_SHIFT)) & XRDC_MRGD_W4_10_2_ACCSET2_MASK)

#define XRDC_MRGD_W4_10_2_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_10_2_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_10_2_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_2_LKAS2_SHIFT)) & XRDC_MRGD_W4_10_2_LKAS2_MASK)

#define XRDC_MRGD_W4_10_2_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_10_2_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_10_2_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_2_LK2_SHIFT)) & XRDC_MRGD_W4_10_2_LK2_MASK)

#define XRDC_MRGD_W4_10_2_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_10_2_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_10_2_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_2_VLD_SHIFT)) & XRDC_MRGD_W4_10_2_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_10_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_10_3_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_10_3_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_10_3_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_10_3_SRTADDR_SHIFT)) & XRDC_MRGD_W0_10_3_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_10_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_10_3_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_10_3_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_10_3_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_10_3_ENDADDR_SHIFT)) & XRDC_MRGD_W1_10_3_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_10_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_10_3_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_10_3_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_10_3_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_3_D0SEL_SHIFT)) & XRDC_MRGD_W2_10_3_D0SEL_MASK)

#define XRDC_MRGD_W2_10_3_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_10_3_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_10_3_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_3_D1SEL_SHIFT)) & XRDC_MRGD_W2_10_3_D1SEL_MASK)

#define XRDC_MRGD_W2_10_3_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_10_3_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_10_3_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_3_D2SEL_SHIFT)) & XRDC_MRGD_W2_10_3_D2SEL_MASK)

#define XRDC_MRGD_W2_10_3_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_10_3_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_10_3_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_3_D3SEL_SHIFT)) & XRDC_MRGD_W2_10_3_D3SEL_MASK)

#define XRDC_MRGD_W2_10_3_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_10_3_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_10_3_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_3_D4SEL_SHIFT)) & XRDC_MRGD_W2_10_3_D4SEL_MASK)

#define XRDC_MRGD_W2_10_3_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_10_3_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_10_3_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_3_D5SEL_SHIFT)) & XRDC_MRGD_W2_10_3_D5SEL_MASK)

#define XRDC_MRGD_W2_10_3_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_10_3_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_10_3_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_3_D6SEL_SHIFT)) & XRDC_MRGD_W2_10_3_D6SEL_MASK)

#define XRDC_MRGD_W2_10_3_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_10_3_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_10_3_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_3_D7SEL_SHIFT)) & XRDC_MRGD_W2_10_3_D7SEL_MASK)

#define XRDC_MRGD_W2_10_3_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_10_3_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_10_3_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_3_EALO_SHIFT)) & XRDC_MRGD_W2_10_3_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_10_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_10_3_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_10_3_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_10_3_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_3_EAL_SHIFT)) & XRDC_MRGD_W3_10_3_EAL_MASK)

#define XRDC_MRGD_W3_10_3_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_10_3_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_10_3_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_3_CR_SHIFT)) & XRDC_MRGD_W3_10_3_CR_MASK)
/*! @} */

/*! @name MRGD_W4_10_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_10_3_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_10_3_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_10_3_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_3_ACCSET1_SHIFT)) & XRDC_MRGD_W4_10_3_ACCSET1_MASK)

#define XRDC_MRGD_W4_10_3_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_10_3_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_10_3_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_3_LKAS1_SHIFT)) & XRDC_MRGD_W4_10_3_LKAS1_MASK)

#define XRDC_MRGD_W4_10_3_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_10_3_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_10_3_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_3_ACCSET2_SHIFT)) & XRDC_MRGD_W4_10_3_ACCSET2_MASK)

#define XRDC_MRGD_W4_10_3_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_10_3_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_10_3_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_3_LKAS2_SHIFT)) & XRDC_MRGD_W4_10_3_LKAS2_MASK)

#define XRDC_MRGD_W4_10_3_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_10_3_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_10_3_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_3_LK2_SHIFT)) & XRDC_MRGD_W4_10_3_LK2_MASK)

#define XRDC_MRGD_W4_10_3_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_10_3_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_10_3_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_3_VLD_SHIFT)) & XRDC_MRGD_W4_10_3_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_10_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_10_4_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_10_4_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_10_4_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_10_4_SRTADDR_SHIFT)) & XRDC_MRGD_W0_10_4_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_10_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_10_4_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_10_4_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_10_4_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_10_4_ENDADDR_SHIFT)) & XRDC_MRGD_W1_10_4_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_10_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_10_4_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_10_4_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_10_4_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_4_D0SEL_SHIFT)) & XRDC_MRGD_W2_10_4_D0SEL_MASK)

#define XRDC_MRGD_W2_10_4_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_10_4_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_10_4_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_4_D1SEL_SHIFT)) & XRDC_MRGD_W2_10_4_D1SEL_MASK)

#define XRDC_MRGD_W2_10_4_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_10_4_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_10_4_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_4_D2SEL_SHIFT)) & XRDC_MRGD_W2_10_4_D2SEL_MASK)

#define XRDC_MRGD_W2_10_4_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_10_4_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_10_4_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_4_D3SEL_SHIFT)) & XRDC_MRGD_W2_10_4_D3SEL_MASK)

#define XRDC_MRGD_W2_10_4_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_10_4_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_10_4_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_4_D4SEL_SHIFT)) & XRDC_MRGD_W2_10_4_D4SEL_MASK)

#define XRDC_MRGD_W2_10_4_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_10_4_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_10_4_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_4_D5SEL_SHIFT)) & XRDC_MRGD_W2_10_4_D5SEL_MASK)

#define XRDC_MRGD_W2_10_4_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_10_4_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_10_4_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_4_D6SEL_SHIFT)) & XRDC_MRGD_W2_10_4_D6SEL_MASK)

#define XRDC_MRGD_W2_10_4_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_10_4_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_10_4_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_4_D7SEL_SHIFT)) & XRDC_MRGD_W2_10_4_D7SEL_MASK)

#define XRDC_MRGD_W2_10_4_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_10_4_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_10_4_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_4_EALO_SHIFT)) & XRDC_MRGD_W2_10_4_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_10_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_10_4_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_10_4_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_10_4_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_4_EAL_SHIFT)) & XRDC_MRGD_W3_10_4_EAL_MASK)

#define XRDC_MRGD_W3_10_4_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_10_4_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_10_4_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_4_CR_SHIFT)) & XRDC_MRGD_W3_10_4_CR_MASK)
/*! @} */

/*! @name MRGD_W4_10_4 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_10_4_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_10_4_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_10_4_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_4_ACCSET1_SHIFT)) & XRDC_MRGD_W4_10_4_ACCSET1_MASK)

#define XRDC_MRGD_W4_10_4_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_10_4_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_10_4_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_4_LKAS1_SHIFT)) & XRDC_MRGD_W4_10_4_LKAS1_MASK)

#define XRDC_MRGD_W4_10_4_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_10_4_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_10_4_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_4_ACCSET2_SHIFT)) & XRDC_MRGD_W4_10_4_ACCSET2_MASK)

#define XRDC_MRGD_W4_10_4_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_10_4_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_10_4_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_4_LKAS2_SHIFT)) & XRDC_MRGD_W4_10_4_LKAS2_MASK)

#define XRDC_MRGD_W4_10_4_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_10_4_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_10_4_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_4_LK2_SHIFT)) & XRDC_MRGD_W4_10_4_LK2_MASK)

#define XRDC_MRGD_W4_10_4_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_10_4_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_10_4_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_4_VLD_SHIFT)) & XRDC_MRGD_W4_10_4_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_10_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_10_5_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_10_5_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_10_5_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_10_5_SRTADDR_SHIFT)) & XRDC_MRGD_W0_10_5_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_10_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_10_5_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_10_5_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_10_5_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_10_5_ENDADDR_SHIFT)) & XRDC_MRGD_W1_10_5_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_10_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_10_5_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_10_5_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_10_5_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_5_D0SEL_SHIFT)) & XRDC_MRGD_W2_10_5_D0SEL_MASK)

#define XRDC_MRGD_W2_10_5_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_10_5_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_10_5_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_5_D1SEL_SHIFT)) & XRDC_MRGD_W2_10_5_D1SEL_MASK)

#define XRDC_MRGD_W2_10_5_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_10_5_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_10_5_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_5_D2SEL_SHIFT)) & XRDC_MRGD_W2_10_5_D2SEL_MASK)

#define XRDC_MRGD_W2_10_5_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_10_5_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_10_5_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_5_D3SEL_SHIFT)) & XRDC_MRGD_W2_10_5_D3SEL_MASK)

#define XRDC_MRGD_W2_10_5_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_10_5_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_10_5_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_5_D4SEL_SHIFT)) & XRDC_MRGD_W2_10_5_D4SEL_MASK)

#define XRDC_MRGD_W2_10_5_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_10_5_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_10_5_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_5_D5SEL_SHIFT)) & XRDC_MRGD_W2_10_5_D5SEL_MASK)

#define XRDC_MRGD_W2_10_5_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_10_5_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_10_5_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_5_D6SEL_SHIFT)) & XRDC_MRGD_W2_10_5_D6SEL_MASK)

#define XRDC_MRGD_W2_10_5_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_10_5_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_10_5_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_5_D7SEL_SHIFT)) & XRDC_MRGD_W2_10_5_D7SEL_MASK)

#define XRDC_MRGD_W2_10_5_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_10_5_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_10_5_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_5_EALO_SHIFT)) & XRDC_MRGD_W2_10_5_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_10_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_10_5_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_10_5_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_10_5_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_5_EAL_SHIFT)) & XRDC_MRGD_W3_10_5_EAL_MASK)

#define XRDC_MRGD_W3_10_5_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_10_5_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_10_5_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_5_CR_SHIFT)) & XRDC_MRGD_W3_10_5_CR_MASK)
/*! @} */

/*! @name MRGD_W4_10_5 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_10_5_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_10_5_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_10_5_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_5_ACCSET1_SHIFT)) & XRDC_MRGD_W4_10_5_ACCSET1_MASK)

#define XRDC_MRGD_W4_10_5_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_10_5_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_10_5_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_5_LKAS1_SHIFT)) & XRDC_MRGD_W4_10_5_LKAS1_MASK)

#define XRDC_MRGD_W4_10_5_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_10_5_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_10_5_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_5_ACCSET2_SHIFT)) & XRDC_MRGD_W4_10_5_ACCSET2_MASK)

#define XRDC_MRGD_W4_10_5_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_10_5_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_10_5_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_5_LKAS2_SHIFT)) & XRDC_MRGD_W4_10_5_LKAS2_MASK)

#define XRDC_MRGD_W4_10_5_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_10_5_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_10_5_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_5_LK2_SHIFT)) & XRDC_MRGD_W4_10_5_LK2_MASK)

#define XRDC_MRGD_W4_10_5_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_10_5_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_10_5_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_5_VLD_SHIFT)) & XRDC_MRGD_W4_10_5_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_10_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_10_6_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_10_6_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_10_6_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_10_6_SRTADDR_SHIFT)) & XRDC_MRGD_W0_10_6_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_10_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_10_6_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_10_6_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_10_6_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_10_6_ENDADDR_SHIFT)) & XRDC_MRGD_W1_10_6_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_10_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_10_6_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_10_6_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_10_6_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_6_D0SEL_SHIFT)) & XRDC_MRGD_W2_10_6_D0SEL_MASK)

#define XRDC_MRGD_W2_10_6_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_10_6_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_10_6_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_6_D1SEL_SHIFT)) & XRDC_MRGD_W2_10_6_D1SEL_MASK)

#define XRDC_MRGD_W2_10_6_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_10_6_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_10_6_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_6_D2SEL_SHIFT)) & XRDC_MRGD_W2_10_6_D2SEL_MASK)

#define XRDC_MRGD_W2_10_6_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_10_6_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_10_6_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_6_D3SEL_SHIFT)) & XRDC_MRGD_W2_10_6_D3SEL_MASK)

#define XRDC_MRGD_W2_10_6_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_10_6_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_10_6_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_6_D4SEL_SHIFT)) & XRDC_MRGD_W2_10_6_D4SEL_MASK)

#define XRDC_MRGD_W2_10_6_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_10_6_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_10_6_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_6_D5SEL_SHIFT)) & XRDC_MRGD_W2_10_6_D5SEL_MASK)

#define XRDC_MRGD_W2_10_6_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_10_6_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_10_6_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_6_D6SEL_SHIFT)) & XRDC_MRGD_W2_10_6_D6SEL_MASK)

#define XRDC_MRGD_W2_10_6_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_10_6_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_10_6_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_6_D7SEL_SHIFT)) & XRDC_MRGD_W2_10_6_D7SEL_MASK)

#define XRDC_MRGD_W2_10_6_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_10_6_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_10_6_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_6_EALO_SHIFT)) & XRDC_MRGD_W2_10_6_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_10_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_10_6_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_10_6_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_10_6_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_6_EAL_SHIFT)) & XRDC_MRGD_W3_10_6_EAL_MASK)

#define XRDC_MRGD_W3_10_6_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_10_6_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_10_6_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_6_CR_SHIFT)) & XRDC_MRGD_W3_10_6_CR_MASK)
/*! @} */

/*! @name MRGD_W4_10_6 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_10_6_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_10_6_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_10_6_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_6_ACCSET1_SHIFT)) & XRDC_MRGD_W4_10_6_ACCSET1_MASK)

#define XRDC_MRGD_W4_10_6_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_10_6_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_10_6_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_6_LKAS1_SHIFT)) & XRDC_MRGD_W4_10_6_LKAS1_MASK)

#define XRDC_MRGD_W4_10_6_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_10_6_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_10_6_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_6_ACCSET2_SHIFT)) & XRDC_MRGD_W4_10_6_ACCSET2_MASK)

#define XRDC_MRGD_W4_10_6_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_10_6_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_10_6_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_6_LKAS2_SHIFT)) & XRDC_MRGD_W4_10_6_LKAS2_MASK)

#define XRDC_MRGD_W4_10_6_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_10_6_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_10_6_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_6_LK2_SHIFT)) & XRDC_MRGD_W4_10_6_LK2_MASK)

#define XRDC_MRGD_W4_10_6_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_10_6_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_10_6_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_6_VLD_SHIFT)) & XRDC_MRGD_W4_10_6_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_10_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_10_7_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_10_7_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_10_7_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_10_7_SRTADDR_SHIFT)) & XRDC_MRGD_W0_10_7_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_10_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_10_7_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_10_7_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_10_7_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_10_7_ENDADDR_SHIFT)) & XRDC_MRGD_W1_10_7_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_10_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_10_7_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_10_7_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_10_7_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_7_D0SEL_SHIFT)) & XRDC_MRGD_W2_10_7_D0SEL_MASK)

#define XRDC_MRGD_W2_10_7_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_10_7_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_10_7_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_7_D1SEL_SHIFT)) & XRDC_MRGD_W2_10_7_D1SEL_MASK)

#define XRDC_MRGD_W2_10_7_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_10_7_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_10_7_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_7_D2SEL_SHIFT)) & XRDC_MRGD_W2_10_7_D2SEL_MASK)

#define XRDC_MRGD_W2_10_7_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_10_7_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_10_7_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_7_D3SEL_SHIFT)) & XRDC_MRGD_W2_10_7_D3SEL_MASK)

#define XRDC_MRGD_W2_10_7_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_10_7_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_10_7_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_7_D4SEL_SHIFT)) & XRDC_MRGD_W2_10_7_D4SEL_MASK)

#define XRDC_MRGD_W2_10_7_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_10_7_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_10_7_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_7_D5SEL_SHIFT)) & XRDC_MRGD_W2_10_7_D5SEL_MASK)

#define XRDC_MRGD_W2_10_7_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_10_7_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_10_7_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_7_D6SEL_SHIFT)) & XRDC_MRGD_W2_10_7_D6SEL_MASK)

#define XRDC_MRGD_W2_10_7_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_10_7_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_10_7_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_7_D7SEL_SHIFT)) & XRDC_MRGD_W2_10_7_D7SEL_MASK)

#define XRDC_MRGD_W2_10_7_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_10_7_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_10_7_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_10_7_EALO_SHIFT)) & XRDC_MRGD_W2_10_7_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_10_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_10_7_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_10_7_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_10_7_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_7_EAL_SHIFT)) & XRDC_MRGD_W3_10_7_EAL_MASK)

#define XRDC_MRGD_W3_10_7_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_10_7_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_10_7_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_10_7_CR_SHIFT)) & XRDC_MRGD_W3_10_7_CR_MASK)
/*! @} */

/*! @name MRGD_W4_10_7 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_10_7_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_10_7_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_10_7_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_7_ACCSET1_SHIFT)) & XRDC_MRGD_W4_10_7_ACCSET1_MASK)

#define XRDC_MRGD_W4_10_7_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_10_7_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_10_7_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_7_LKAS1_SHIFT)) & XRDC_MRGD_W4_10_7_LKAS1_MASK)

#define XRDC_MRGD_W4_10_7_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_10_7_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_10_7_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_7_ACCSET2_SHIFT)) & XRDC_MRGD_W4_10_7_ACCSET2_MASK)

#define XRDC_MRGD_W4_10_7_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_10_7_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_10_7_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_7_LKAS2_SHIFT)) & XRDC_MRGD_W4_10_7_LKAS2_MASK)

#define XRDC_MRGD_W4_10_7_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_10_7_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_10_7_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_7_LK2_SHIFT)) & XRDC_MRGD_W4_10_7_LK2_MASK)

#define XRDC_MRGD_W4_10_7_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_10_7_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_10_7_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_10_7_VLD_SHIFT)) & XRDC_MRGD_W4_10_7_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_11_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_11_0_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_11_0_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_11_0_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_11_0_SRTADDR_SHIFT)) & XRDC_MRGD_W0_11_0_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_11_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_11_0_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_11_0_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_11_0_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_11_0_ENDADDR_SHIFT)) & XRDC_MRGD_W1_11_0_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_11_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_11_0_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_11_0_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_11_0_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_0_D0SEL_SHIFT)) & XRDC_MRGD_W2_11_0_D0SEL_MASK)

#define XRDC_MRGD_W2_11_0_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_11_0_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_11_0_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_0_D1SEL_SHIFT)) & XRDC_MRGD_W2_11_0_D1SEL_MASK)

#define XRDC_MRGD_W2_11_0_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_11_0_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_11_0_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_0_D2SEL_SHIFT)) & XRDC_MRGD_W2_11_0_D2SEL_MASK)

#define XRDC_MRGD_W2_11_0_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_11_0_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_11_0_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_0_D3SEL_SHIFT)) & XRDC_MRGD_W2_11_0_D3SEL_MASK)

#define XRDC_MRGD_W2_11_0_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_11_0_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_11_0_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_0_D4SEL_SHIFT)) & XRDC_MRGD_W2_11_0_D4SEL_MASK)

#define XRDC_MRGD_W2_11_0_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_11_0_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_11_0_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_0_D5SEL_SHIFT)) & XRDC_MRGD_W2_11_0_D5SEL_MASK)

#define XRDC_MRGD_W2_11_0_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_11_0_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_11_0_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_0_D6SEL_SHIFT)) & XRDC_MRGD_W2_11_0_D6SEL_MASK)

#define XRDC_MRGD_W2_11_0_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_11_0_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_11_0_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_0_D7SEL_SHIFT)) & XRDC_MRGD_W2_11_0_D7SEL_MASK)

#define XRDC_MRGD_W2_11_0_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_11_0_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_11_0_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_0_EALO_SHIFT)) & XRDC_MRGD_W2_11_0_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_11_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_11_0_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_11_0_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_11_0_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_11_0_EAL_SHIFT)) & XRDC_MRGD_W3_11_0_EAL_MASK)

#define XRDC_MRGD_W3_11_0_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_11_0_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_11_0_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_11_0_CR_SHIFT)) & XRDC_MRGD_W3_11_0_CR_MASK)
/*! @} */

/*! @name MRGD_W4_11_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_11_0_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_11_0_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_11_0_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_0_ACCSET1_SHIFT)) & XRDC_MRGD_W4_11_0_ACCSET1_MASK)

#define XRDC_MRGD_W4_11_0_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_11_0_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_11_0_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_0_LKAS1_SHIFT)) & XRDC_MRGD_W4_11_0_LKAS1_MASK)

#define XRDC_MRGD_W4_11_0_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_11_0_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_11_0_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_0_ACCSET2_SHIFT)) & XRDC_MRGD_W4_11_0_ACCSET2_MASK)

#define XRDC_MRGD_W4_11_0_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_11_0_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_11_0_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_0_LKAS2_SHIFT)) & XRDC_MRGD_W4_11_0_LKAS2_MASK)

#define XRDC_MRGD_W4_11_0_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_11_0_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_11_0_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_0_LK2_SHIFT)) & XRDC_MRGD_W4_11_0_LK2_MASK)

#define XRDC_MRGD_W4_11_0_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_11_0_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_11_0_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_0_VLD_SHIFT)) & XRDC_MRGD_W4_11_0_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_11_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_11_1_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_11_1_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_11_1_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_11_1_SRTADDR_SHIFT)) & XRDC_MRGD_W0_11_1_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_11_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_11_1_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_11_1_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_11_1_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_11_1_ENDADDR_SHIFT)) & XRDC_MRGD_W1_11_1_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_11_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_11_1_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_11_1_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_11_1_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_1_D0SEL_SHIFT)) & XRDC_MRGD_W2_11_1_D0SEL_MASK)

#define XRDC_MRGD_W2_11_1_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_11_1_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_11_1_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_1_D1SEL_SHIFT)) & XRDC_MRGD_W2_11_1_D1SEL_MASK)

#define XRDC_MRGD_W2_11_1_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_11_1_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_11_1_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_1_D2SEL_SHIFT)) & XRDC_MRGD_W2_11_1_D2SEL_MASK)

#define XRDC_MRGD_W2_11_1_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_11_1_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_11_1_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_1_D3SEL_SHIFT)) & XRDC_MRGD_W2_11_1_D3SEL_MASK)

#define XRDC_MRGD_W2_11_1_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_11_1_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_11_1_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_1_D4SEL_SHIFT)) & XRDC_MRGD_W2_11_1_D4SEL_MASK)

#define XRDC_MRGD_W2_11_1_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_11_1_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_11_1_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_1_D5SEL_SHIFT)) & XRDC_MRGD_W2_11_1_D5SEL_MASK)

#define XRDC_MRGD_W2_11_1_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_11_1_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_11_1_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_1_D6SEL_SHIFT)) & XRDC_MRGD_W2_11_1_D6SEL_MASK)

#define XRDC_MRGD_W2_11_1_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_11_1_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_11_1_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_1_D7SEL_SHIFT)) & XRDC_MRGD_W2_11_1_D7SEL_MASK)

#define XRDC_MRGD_W2_11_1_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_11_1_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_11_1_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_1_EALO_SHIFT)) & XRDC_MRGD_W2_11_1_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_11_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_11_1_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_11_1_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_11_1_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_11_1_EAL_SHIFT)) & XRDC_MRGD_W3_11_1_EAL_MASK)

#define XRDC_MRGD_W3_11_1_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_11_1_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_11_1_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_11_1_CR_SHIFT)) & XRDC_MRGD_W3_11_1_CR_MASK)
/*! @} */

/*! @name MRGD_W4_11_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_11_1_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_11_1_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_11_1_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_1_ACCSET1_SHIFT)) & XRDC_MRGD_W4_11_1_ACCSET1_MASK)

#define XRDC_MRGD_W4_11_1_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_11_1_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_11_1_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_1_LKAS1_SHIFT)) & XRDC_MRGD_W4_11_1_LKAS1_MASK)

#define XRDC_MRGD_W4_11_1_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_11_1_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_11_1_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_1_ACCSET2_SHIFT)) & XRDC_MRGD_W4_11_1_ACCSET2_MASK)

#define XRDC_MRGD_W4_11_1_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_11_1_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_11_1_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_1_LKAS2_SHIFT)) & XRDC_MRGD_W4_11_1_LKAS2_MASK)

#define XRDC_MRGD_W4_11_1_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_11_1_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_11_1_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_1_LK2_SHIFT)) & XRDC_MRGD_W4_11_1_LK2_MASK)

#define XRDC_MRGD_W4_11_1_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_11_1_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_11_1_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_1_VLD_SHIFT)) & XRDC_MRGD_W4_11_1_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_11_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_11_2_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_11_2_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_11_2_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_11_2_SRTADDR_SHIFT)) & XRDC_MRGD_W0_11_2_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_11_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_11_2_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_11_2_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_11_2_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_11_2_ENDADDR_SHIFT)) & XRDC_MRGD_W1_11_2_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_11_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_11_2_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_11_2_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_11_2_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_2_D0SEL_SHIFT)) & XRDC_MRGD_W2_11_2_D0SEL_MASK)

#define XRDC_MRGD_W2_11_2_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_11_2_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_11_2_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_2_D1SEL_SHIFT)) & XRDC_MRGD_W2_11_2_D1SEL_MASK)

#define XRDC_MRGD_W2_11_2_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_11_2_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_11_2_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_2_D2SEL_SHIFT)) & XRDC_MRGD_W2_11_2_D2SEL_MASK)

#define XRDC_MRGD_W2_11_2_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_11_2_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_11_2_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_2_D3SEL_SHIFT)) & XRDC_MRGD_W2_11_2_D3SEL_MASK)

#define XRDC_MRGD_W2_11_2_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_11_2_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_11_2_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_2_D4SEL_SHIFT)) & XRDC_MRGD_W2_11_2_D4SEL_MASK)

#define XRDC_MRGD_W2_11_2_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_11_2_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_11_2_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_2_D5SEL_SHIFT)) & XRDC_MRGD_W2_11_2_D5SEL_MASK)

#define XRDC_MRGD_W2_11_2_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_11_2_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_11_2_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_2_D6SEL_SHIFT)) & XRDC_MRGD_W2_11_2_D6SEL_MASK)

#define XRDC_MRGD_W2_11_2_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_11_2_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_11_2_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_2_D7SEL_SHIFT)) & XRDC_MRGD_W2_11_2_D7SEL_MASK)

#define XRDC_MRGD_W2_11_2_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_11_2_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_11_2_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_2_EALO_SHIFT)) & XRDC_MRGD_W2_11_2_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_11_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_11_2_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_11_2_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_11_2_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_11_2_EAL_SHIFT)) & XRDC_MRGD_W3_11_2_EAL_MASK)

#define XRDC_MRGD_W3_11_2_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_11_2_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_11_2_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_11_2_CR_SHIFT)) & XRDC_MRGD_W3_11_2_CR_MASK)
/*! @} */

/*! @name MRGD_W4_11_2 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_11_2_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_11_2_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_11_2_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_2_ACCSET1_SHIFT)) & XRDC_MRGD_W4_11_2_ACCSET1_MASK)

#define XRDC_MRGD_W4_11_2_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_11_2_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_11_2_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_2_LKAS1_SHIFT)) & XRDC_MRGD_W4_11_2_LKAS1_MASK)

#define XRDC_MRGD_W4_11_2_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_11_2_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_11_2_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_2_ACCSET2_SHIFT)) & XRDC_MRGD_W4_11_2_ACCSET2_MASK)

#define XRDC_MRGD_W4_11_2_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_11_2_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_11_2_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_2_LKAS2_SHIFT)) & XRDC_MRGD_W4_11_2_LKAS2_MASK)

#define XRDC_MRGD_W4_11_2_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_11_2_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_11_2_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_2_LK2_SHIFT)) & XRDC_MRGD_W4_11_2_LK2_MASK)

#define XRDC_MRGD_W4_11_2_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_11_2_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_11_2_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_2_VLD_SHIFT)) & XRDC_MRGD_W4_11_2_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_11_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_11_3_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_11_3_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_11_3_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_11_3_SRTADDR_SHIFT)) & XRDC_MRGD_W0_11_3_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_11_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_11_3_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_11_3_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_11_3_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_11_3_ENDADDR_SHIFT)) & XRDC_MRGD_W1_11_3_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_11_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_11_3_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_11_3_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_11_3_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_3_D0SEL_SHIFT)) & XRDC_MRGD_W2_11_3_D0SEL_MASK)

#define XRDC_MRGD_W2_11_3_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_11_3_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_11_3_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_3_D1SEL_SHIFT)) & XRDC_MRGD_W2_11_3_D1SEL_MASK)

#define XRDC_MRGD_W2_11_3_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_11_3_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_11_3_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_3_D2SEL_SHIFT)) & XRDC_MRGD_W2_11_3_D2SEL_MASK)

#define XRDC_MRGD_W2_11_3_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_11_3_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_11_3_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_3_D3SEL_SHIFT)) & XRDC_MRGD_W2_11_3_D3SEL_MASK)

#define XRDC_MRGD_W2_11_3_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_11_3_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_11_3_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_3_D4SEL_SHIFT)) & XRDC_MRGD_W2_11_3_D4SEL_MASK)

#define XRDC_MRGD_W2_11_3_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_11_3_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_11_3_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_3_D5SEL_SHIFT)) & XRDC_MRGD_W2_11_3_D5SEL_MASK)

#define XRDC_MRGD_W2_11_3_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_11_3_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_11_3_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_3_D6SEL_SHIFT)) & XRDC_MRGD_W2_11_3_D6SEL_MASK)

#define XRDC_MRGD_W2_11_3_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_11_3_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_11_3_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_3_D7SEL_SHIFT)) & XRDC_MRGD_W2_11_3_D7SEL_MASK)

#define XRDC_MRGD_W2_11_3_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_11_3_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_11_3_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_11_3_EALO_SHIFT)) & XRDC_MRGD_W2_11_3_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_11_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_11_3_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_11_3_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_11_3_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_11_3_EAL_SHIFT)) & XRDC_MRGD_W3_11_3_EAL_MASK)

#define XRDC_MRGD_W3_11_3_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_11_3_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_11_3_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_11_3_CR_SHIFT)) & XRDC_MRGD_W3_11_3_CR_MASK)
/*! @} */

/*! @name MRGD_W4_11_3 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_11_3_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_11_3_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_11_3_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_3_ACCSET1_SHIFT)) & XRDC_MRGD_W4_11_3_ACCSET1_MASK)

#define XRDC_MRGD_W4_11_3_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_11_3_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_11_3_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_3_LKAS1_SHIFT)) & XRDC_MRGD_W4_11_3_LKAS1_MASK)

#define XRDC_MRGD_W4_11_3_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_11_3_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_11_3_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_3_ACCSET2_SHIFT)) & XRDC_MRGD_W4_11_3_ACCSET2_MASK)

#define XRDC_MRGD_W4_11_3_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_11_3_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_11_3_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_3_LKAS2_SHIFT)) & XRDC_MRGD_W4_11_3_LKAS2_MASK)

#define XRDC_MRGD_W4_11_3_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_11_3_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_11_3_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_3_LK2_SHIFT)) & XRDC_MRGD_W4_11_3_LK2_MASK)

#define XRDC_MRGD_W4_11_3_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_11_3_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_11_3_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_11_3_VLD_SHIFT)) & XRDC_MRGD_W4_11_3_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_12_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_12_0_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_12_0_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_12_0_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_12_0_SRTADDR_SHIFT)) & XRDC_MRGD_W0_12_0_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_12_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_12_0_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_12_0_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_12_0_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_12_0_ENDADDR_SHIFT)) & XRDC_MRGD_W1_12_0_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_12_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_12_0_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_12_0_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_12_0_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_0_D0SEL_SHIFT)) & XRDC_MRGD_W2_12_0_D0SEL_MASK)

#define XRDC_MRGD_W2_12_0_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_12_0_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_12_0_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_0_D1SEL_SHIFT)) & XRDC_MRGD_W2_12_0_D1SEL_MASK)

#define XRDC_MRGD_W2_12_0_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_12_0_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_12_0_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_0_D2SEL_SHIFT)) & XRDC_MRGD_W2_12_0_D2SEL_MASK)

#define XRDC_MRGD_W2_12_0_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_12_0_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_12_0_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_0_D3SEL_SHIFT)) & XRDC_MRGD_W2_12_0_D3SEL_MASK)

#define XRDC_MRGD_W2_12_0_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_12_0_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_12_0_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_0_D4SEL_SHIFT)) & XRDC_MRGD_W2_12_0_D4SEL_MASK)

#define XRDC_MRGD_W2_12_0_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_12_0_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_12_0_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_0_D5SEL_SHIFT)) & XRDC_MRGD_W2_12_0_D5SEL_MASK)

#define XRDC_MRGD_W2_12_0_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_12_0_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_12_0_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_0_D6SEL_SHIFT)) & XRDC_MRGD_W2_12_0_D6SEL_MASK)

#define XRDC_MRGD_W2_12_0_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_12_0_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_12_0_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_0_D7SEL_SHIFT)) & XRDC_MRGD_W2_12_0_D7SEL_MASK)

#define XRDC_MRGD_W2_12_0_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_12_0_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_12_0_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_0_EALO_SHIFT)) & XRDC_MRGD_W2_12_0_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_12_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_12_0_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_12_0_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_12_0_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_12_0_EAL_SHIFT)) & XRDC_MRGD_W3_12_0_EAL_MASK)

#define XRDC_MRGD_W3_12_0_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_12_0_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_12_0_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_12_0_CR_SHIFT)) & XRDC_MRGD_W3_12_0_CR_MASK)
/*! @} */

/*! @name MRGD_W4_12_0 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_12_0_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_12_0_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_12_0_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_12_0_ACCSET1_SHIFT)) & XRDC_MRGD_W4_12_0_ACCSET1_MASK)

#define XRDC_MRGD_W4_12_0_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_12_0_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_12_0_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_12_0_LKAS1_SHIFT)) & XRDC_MRGD_W4_12_0_LKAS1_MASK)

#define XRDC_MRGD_W4_12_0_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_12_0_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_12_0_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_12_0_ACCSET2_SHIFT)) & XRDC_MRGD_W4_12_0_ACCSET2_MASK)

#define XRDC_MRGD_W4_12_0_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_12_0_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_12_0_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_12_0_LKAS2_SHIFT)) & XRDC_MRGD_W4_12_0_LKAS2_MASK)

#define XRDC_MRGD_W4_12_0_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_12_0_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_12_0_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_12_0_LK2_SHIFT)) & XRDC_MRGD_W4_12_0_LK2_MASK)

#define XRDC_MRGD_W4_12_0_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_12_0_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_12_0_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_12_0_VLD_SHIFT)) & XRDC_MRGD_W4_12_0_VLD_MASK)
/*! @} */

/*! @name MRGD_W0_12_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W0_12_1_SRTADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W0_12_1_SRTADDR_SHIFT          (5U)
/*! SRTADDR - Start Address */
#define XRDC_MRGD_W0_12_1_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W0_12_1_SRTADDR_SHIFT)) & XRDC_MRGD_W0_12_1_SRTADDR_MASK)
/*! @} */

/*! @name MRGD_W1_12_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W1_12_1_ENDADDR_MASK           (0xFFFFFFE0U)
#define XRDC_MRGD_W1_12_1_ENDADDR_SHIFT          (5U)
/*! ENDADDR - End Address */
#define XRDC_MRGD_W1_12_1_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W1_12_1_ENDADDR_SHIFT)) & XRDC_MRGD_W1_12_1_ENDADDR_MASK)
/*! @} */

/*! @name MRGD_W2_12_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W2_12_1_D0SEL_MASK             (0x7U)
#define XRDC_MRGD_W2_12_1_D0SEL_SHIFT            (0U)
/*! D0SEL - Domain 0 select */
#define XRDC_MRGD_W2_12_1_D0SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_1_D0SEL_SHIFT)) & XRDC_MRGD_W2_12_1_D0SEL_MASK)

#define XRDC_MRGD_W2_12_1_D1SEL_MASK             (0x38U)
#define XRDC_MRGD_W2_12_1_D1SEL_SHIFT            (3U)
/*! D1SEL - Domain 1 select */
#define XRDC_MRGD_W2_12_1_D1SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_1_D1SEL_SHIFT)) & XRDC_MRGD_W2_12_1_D1SEL_MASK)

#define XRDC_MRGD_W2_12_1_D2SEL_MASK             (0x1C0U)
#define XRDC_MRGD_W2_12_1_D2SEL_SHIFT            (6U)
/*! D2SEL - Domain 2 select */
#define XRDC_MRGD_W2_12_1_D2SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_1_D2SEL_SHIFT)) & XRDC_MRGD_W2_12_1_D2SEL_MASK)

#define XRDC_MRGD_W2_12_1_D3SEL_MASK             (0xE00U)
#define XRDC_MRGD_W2_12_1_D3SEL_SHIFT            (9U)
/*! D3SEL - Domain 3 select */
#define XRDC_MRGD_W2_12_1_D3SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_1_D3SEL_SHIFT)) & XRDC_MRGD_W2_12_1_D3SEL_MASK)

#define XRDC_MRGD_W2_12_1_D4SEL_MASK             (0x7000U)
#define XRDC_MRGD_W2_12_1_D4SEL_SHIFT            (12U)
/*! D4SEL - Domain 4 select */
#define XRDC_MRGD_W2_12_1_D4SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_1_D4SEL_SHIFT)) & XRDC_MRGD_W2_12_1_D4SEL_MASK)

#define XRDC_MRGD_W2_12_1_D5SEL_MASK             (0x38000U)
#define XRDC_MRGD_W2_12_1_D5SEL_SHIFT            (15U)
/*! D5SEL - Domain 5 select */
#define XRDC_MRGD_W2_12_1_D5SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_1_D5SEL_SHIFT)) & XRDC_MRGD_W2_12_1_D5SEL_MASK)

#define XRDC_MRGD_W2_12_1_D6SEL_MASK             (0x1C0000U)
#define XRDC_MRGD_W2_12_1_D6SEL_SHIFT            (18U)
/*! D6SEL - Domain 6 select */
#define XRDC_MRGD_W2_12_1_D6SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_1_D6SEL_SHIFT)) & XRDC_MRGD_W2_12_1_D6SEL_MASK)

#define XRDC_MRGD_W2_12_1_D7SEL_MASK             (0xE00000U)
#define XRDC_MRGD_W2_12_1_D7SEL_SHIFT            (21U)
/*! D7SEL - Domain 7 select */
#define XRDC_MRGD_W2_12_1_D7SEL(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_1_D7SEL_SHIFT)) & XRDC_MRGD_W2_12_1_D7SEL_MASK)

#define XRDC_MRGD_W2_12_1_EALO_MASK              (0xF000000U)
#define XRDC_MRGD_W2_12_1_EALO_SHIFT             (24U)
/*! EALO - Exclusive Access Lock Owner */
#define XRDC_MRGD_W2_12_1_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W2_12_1_EALO_SHIFT)) & XRDC_MRGD_W2_12_1_EALO_MASK)
/*! @} */

/*! @name MRGD_W3_12_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W3_12_1_EAL_MASK               (0x3000000U)
#define XRDC_MRGD_W3_12_1_EAL_SHIFT              (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MRGD_W3_12_1_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_12_1_EAL_SHIFT)) & XRDC_MRGD_W3_12_1_EAL_MASK)

#define XRDC_MRGD_W3_12_1_CR_MASK                (0x80000000U)
#define XRDC_MRGD_W3_12_1_CR_SHIFT               (31U)
/*! CR - Code Region Indicator */
#define XRDC_MRGD_W3_12_1_CR(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W3_12_1_CR_SHIFT)) & XRDC_MRGD_W3_12_1_CR_MASK)
/*! @} */

/*! @name MRGD_W4_12_1 - Memory Region Descriptor */
/*! @{ */

#define XRDC_MRGD_W4_12_1_ACCSET1_MASK           (0xFFFU)
#define XRDC_MRGD_W4_12_1_ACCSET1_SHIFT          (0U)
/*! ACCSET1 - SET 1 of Programmable access flags. */
#define XRDC_MRGD_W4_12_1_ACCSET1(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_12_1_ACCSET1_SHIFT)) & XRDC_MRGD_W4_12_1_ACCSET1_MASK)

#define XRDC_MRGD_W4_12_1_LKAS1_MASK             (0x1000U)
#define XRDC_MRGD_W4_12_1_LKAS1_SHIFT            (12U)
/*! LKAS1 - Lock ACCSET1
 *  0b0..Writes to ACCSET1 affect lesser modes
 *  0b1..ACCSET1 cannot be modified
 */
#define XRDC_MRGD_W4_12_1_LKAS1(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_12_1_LKAS1_SHIFT)) & XRDC_MRGD_W4_12_1_LKAS1_MASK)

#define XRDC_MRGD_W4_12_1_ACCSET2_MASK           (0xFFF0000U)
#define XRDC_MRGD_W4_12_1_ACCSET2_SHIFT          (16U)
/*! ACCSET2 - SET 2 of Programmable access flags. */
#define XRDC_MRGD_W4_12_1_ACCSET2(x)             (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_12_1_ACCSET2_SHIFT)) & XRDC_MRGD_W4_12_1_ACCSET2_MASK)

#define XRDC_MRGD_W4_12_1_LKAS2_MASK             (0x10000000U)
#define XRDC_MRGD_W4_12_1_LKAS2_SHIFT            (28U)
/*! LKAS2 - Lock ACCSET2
 *  0b0..Writes to ACCSET2 affect lesser modes
 *  0b1..ACCSET2 cannot be modified
 */
#define XRDC_MRGD_W4_12_1_LKAS2(x)               (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_12_1_LKAS2_SHIFT)) & XRDC_MRGD_W4_12_1_LKAS2_MASK)

#define XRDC_MRGD_W4_12_1_LK2_MASK               (0x60000000U)
#define XRDC_MRGD_W4_12_1_LK2_SHIFT              (29U)
/*! LK2 - Lock
 *  0b00..Entire MRGDn can be written.
 *  0b01..Entire MRGDn can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
 *  0b11..MRGDn is locked (read-only) until the next reset.
 */
#define XRDC_MRGD_W4_12_1_LK2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_12_1_LK2_SHIFT)) & XRDC_MRGD_W4_12_1_LK2_MASK)

#define XRDC_MRGD_W4_12_1_VLD_MASK               (0x80000000U)
#define XRDC_MRGD_W4_12_1_VLD_SHIFT              (31U)
/*! VLD - Valid
 *  0b0..The MRGDn assignment is invalid.
 *  0b1..The MRGDn assignment is valid.
 */
#define XRDC_MRGD_W4_12_1_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W4_12_1_VLD_SHIFT)) & XRDC_MRGD_W4_12_1_VLD_MASK)
/*! @} */

/*! @name MSAC_W0_0_0 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W0_0_0_D0ACP_MASK              (0x7U)
#define XRDC_MSAC_W0_0_0_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_MSAC_W0_0_0_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_0_D0ACP_SHIFT)) & XRDC_MSAC_W0_0_0_D0ACP_MASK)

#define XRDC_MSAC_W0_0_0_D1ACP_MASK              (0x38U)
#define XRDC_MSAC_W0_0_0_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_MSAC_W0_0_0_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_0_D1ACP_SHIFT)) & XRDC_MSAC_W0_0_0_D1ACP_MASK)

#define XRDC_MSAC_W0_0_0_D2ACP_MASK              (0x1C0U)
#define XRDC_MSAC_W0_0_0_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_MSAC_W0_0_0_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_0_D2ACP_SHIFT)) & XRDC_MSAC_W0_0_0_D2ACP_MASK)

#define XRDC_MSAC_W0_0_0_D3ACP_MASK              (0xE00U)
#define XRDC_MSAC_W0_0_0_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_MSAC_W0_0_0_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_0_D3ACP_SHIFT)) & XRDC_MSAC_W0_0_0_D3ACP_MASK)

#define XRDC_MSAC_W0_0_0_D4ACP_MASK              (0x7000U)
#define XRDC_MSAC_W0_0_0_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_MSAC_W0_0_0_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_0_D4ACP_SHIFT)) & XRDC_MSAC_W0_0_0_D4ACP_MASK)

#define XRDC_MSAC_W0_0_0_D5ACP_MASK              (0x38000U)
#define XRDC_MSAC_W0_0_0_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_MSAC_W0_0_0_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_0_D5ACP_SHIFT)) & XRDC_MSAC_W0_0_0_D5ACP_MASK)

#define XRDC_MSAC_W0_0_0_D6ACP_MASK              (0x1C0000U)
#define XRDC_MSAC_W0_0_0_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_MSAC_W0_0_0_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_0_D6ACP_SHIFT)) & XRDC_MSAC_W0_0_0_D6ACP_MASK)

#define XRDC_MSAC_W0_0_0_D7ACP_MASK              (0xE00000U)
#define XRDC_MSAC_W0_0_0_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_MSAC_W0_0_0_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_0_D7ACP_SHIFT)) & XRDC_MSAC_W0_0_0_D7ACP_MASK)

#define XRDC_MSAC_W0_0_0_EALO_MASK               (0xF000000U)
#define XRDC_MSAC_W0_0_0_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_MSAC_W0_0_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_0_EALO_SHIFT)) & XRDC_MSAC_W0_0_0_EALO_MASK)
/*! @} */

/*! @name MSAC_W1_0_0 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W1_0_0_EAL_MASK                (0x3000000U)
#define XRDC_MSAC_W1_0_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MSAC_W1_0_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_0_0_EAL_SHIFT)) & XRDC_MSAC_W1_0_0_EAL_MASK)

#define XRDC_MSAC_W1_0_0_LK2_MASK                (0x60000000U)
#define XRDC_MSAC_W1_0_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MSACs can be written.
 *  0b01..Entire MSACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MSACs fields can be written.
 *  0b11..MSACs is locked (read-only) until the next reset.
 */
#define XRDC_MSAC_W1_0_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_0_0_LK2_SHIFT)) & XRDC_MSAC_W1_0_0_LK2_MASK)

#define XRDC_MSAC_W1_0_0_VLD_MASK                (0x80000000U)
#define XRDC_MSAC_W1_0_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MSACs assignment is invalid.
 *  0b1..The MSACs assignment is valid.
 */
#define XRDC_MSAC_W1_0_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_0_0_VLD_SHIFT)) & XRDC_MSAC_W1_0_0_VLD_MASK)
/*! @} */

/*! @name MSAC_W0_0_1 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W0_0_1_D0ACP_MASK              (0x7U)
#define XRDC_MSAC_W0_0_1_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_MSAC_W0_0_1_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_1_D0ACP_SHIFT)) & XRDC_MSAC_W0_0_1_D0ACP_MASK)

#define XRDC_MSAC_W0_0_1_D1ACP_MASK              (0x38U)
#define XRDC_MSAC_W0_0_1_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_MSAC_W0_0_1_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_1_D1ACP_SHIFT)) & XRDC_MSAC_W0_0_1_D1ACP_MASK)

#define XRDC_MSAC_W0_0_1_D2ACP_MASK              (0x1C0U)
#define XRDC_MSAC_W0_0_1_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_MSAC_W0_0_1_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_1_D2ACP_SHIFT)) & XRDC_MSAC_W0_0_1_D2ACP_MASK)

#define XRDC_MSAC_W0_0_1_D3ACP_MASK              (0xE00U)
#define XRDC_MSAC_W0_0_1_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_MSAC_W0_0_1_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_1_D3ACP_SHIFT)) & XRDC_MSAC_W0_0_1_D3ACP_MASK)

#define XRDC_MSAC_W0_0_1_D4ACP_MASK              (0x7000U)
#define XRDC_MSAC_W0_0_1_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_MSAC_W0_0_1_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_1_D4ACP_SHIFT)) & XRDC_MSAC_W0_0_1_D4ACP_MASK)

#define XRDC_MSAC_W0_0_1_D5ACP_MASK              (0x38000U)
#define XRDC_MSAC_W0_0_1_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_MSAC_W0_0_1_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_1_D5ACP_SHIFT)) & XRDC_MSAC_W0_0_1_D5ACP_MASK)

#define XRDC_MSAC_W0_0_1_D6ACP_MASK              (0x1C0000U)
#define XRDC_MSAC_W0_0_1_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_MSAC_W0_0_1_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_1_D6ACP_SHIFT)) & XRDC_MSAC_W0_0_1_D6ACP_MASK)

#define XRDC_MSAC_W0_0_1_D7ACP_MASK              (0xE00000U)
#define XRDC_MSAC_W0_0_1_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_MSAC_W0_0_1_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_1_D7ACP_SHIFT)) & XRDC_MSAC_W0_0_1_D7ACP_MASK)

#define XRDC_MSAC_W0_0_1_EALO_MASK               (0xF000000U)
#define XRDC_MSAC_W0_0_1_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_MSAC_W0_0_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_0_1_EALO_SHIFT)) & XRDC_MSAC_W0_0_1_EALO_MASK)
/*! @} */

/*! @name MSAC_W1_0_1 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W1_0_1_EAL_MASK                (0x3000000U)
#define XRDC_MSAC_W1_0_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MSAC_W1_0_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_0_1_EAL_SHIFT)) & XRDC_MSAC_W1_0_1_EAL_MASK)

#define XRDC_MSAC_W1_0_1_LK2_MASK                (0x60000000U)
#define XRDC_MSAC_W1_0_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MSACs can be written.
 *  0b01..Entire MSACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MSACs fields can be written.
 *  0b11..MSACs is locked (read-only) until the next reset.
 */
#define XRDC_MSAC_W1_0_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_0_1_LK2_SHIFT)) & XRDC_MSAC_W1_0_1_LK2_MASK)

#define XRDC_MSAC_W1_0_1_VLD_MASK                (0x80000000U)
#define XRDC_MSAC_W1_0_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MSACs assignment is invalid.
 *  0b1..The MSACs assignment is valid.
 */
#define XRDC_MSAC_W1_0_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_0_1_VLD_SHIFT)) & XRDC_MSAC_W1_0_1_VLD_MASK)
/*! @} */

/*! @name MSAC_W0_1_0 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W0_1_0_D0ACP_MASK              (0x7U)
#define XRDC_MSAC_W0_1_0_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_MSAC_W0_1_0_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_1_0_D0ACP_SHIFT)) & XRDC_MSAC_W0_1_0_D0ACP_MASK)

#define XRDC_MSAC_W0_1_0_D1ACP_MASK              (0x38U)
#define XRDC_MSAC_W0_1_0_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_MSAC_W0_1_0_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_1_0_D1ACP_SHIFT)) & XRDC_MSAC_W0_1_0_D1ACP_MASK)

#define XRDC_MSAC_W0_1_0_D2ACP_MASK              (0x1C0U)
#define XRDC_MSAC_W0_1_0_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_MSAC_W0_1_0_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_1_0_D2ACP_SHIFT)) & XRDC_MSAC_W0_1_0_D2ACP_MASK)

#define XRDC_MSAC_W0_1_0_D3ACP_MASK              (0xE00U)
#define XRDC_MSAC_W0_1_0_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_MSAC_W0_1_0_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_1_0_D3ACP_SHIFT)) & XRDC_MSAC_W0_1_0_D3ACP_MASK)

#define XRDC_MSAC_W0_1_0_D4ACP_MASK              (0x7000U)
#define XRDC_MSAC_W0_1_0_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_MSAC_W0_1_0_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_1_0_D4ACP_SHIFT)) & XRDC_MSAC_W0_1_0_D4ACP_MASK)

#define XRDC_MSAC_W0_1_0_D5ACP_MASK              (0x38000U)
#define XRDC_MSAC_W0_1_0_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_MSAC_W0_1_0_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_1_0_D5ACP_SHIFT)) & XRDC_MSAC_W0_1_0_D5ACP_MASK)

#define XRDC_MSAC_W0_1_0_D6ACP_MASK              (0x1C0000U)
#define XRDC_MSAC_W0_1_0_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_MSAC_W0_1_0_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_1_0_D6ACP_SHIFT)) & XRDC_MSAC_W0_1_0_D6ACP_MASK)

#define XRDC_MSAC_W0_1_0_D7ACP_MASK              (0xE00000U)
#define XRDC_MSAC_W0_1_0_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_MSAC_W0_1_0_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_1_0_D7ACP_SHIFT)) & XRDC_MSAC_W0_1_0_D7ACP_MASK)

#define XRDC_MSAC_W0_1_0_EALO_MASK               (0xF000000U)
#define XRDC_MSAC_W0_1_0_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_MSAC_W0_1_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_1_0_EALO_SHIFT)) & XRDC_MSAC_W0_1_0_EALO_MASK)
/*! @} */

/*! @name MSAC_W1_1_0 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W1_1_0_EAL_MASK                (0x3000000U)
#define XRDC_MSAC_W1_1_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MSAC_W1_1_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_1_0_EAL_SHIFT)) & XRDC_MSAC_W1_1_0_EAL_MASK)

#define XRDC_MSAC_W1_1_0_LK2_MASK                (0x60000000U)
#define XRDC_MSAC_W1_1_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MSACs can be written.
 *  0b01..Entire MSACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MSACs fields can be written.
 *  0b11..MSACs is locked (read-only) until the next reset.
 */
#define XRDC_MSAC_W1_1_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_1_0_LK2_SHIFT)) & XRDC_MSAC_W1_1_0_LK2_MASK)

#define XRDC_MSAC_W1_1_0_VLD_MASK                (0x80000000U)
#define XRDC_MSAC_W1_1_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MSACs assignment is invalid.
 *  0b1..The MSACs assignment is valid.
 */
#define XRDC_MSAC_W1_1_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_1_0_VLD_SHIFT)) & XRDC_MSAC_W1_1_0_VLD_MASK)
/*! @} */

/*! @name MSAC_W0_2_0 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W0_2_0_D0ACP_MASK              (0x7U)
#define XRDC_MSAC_W0_2_0_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_MSAC_W0_2_0_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_0_D0ACP_SHIFT)) & XRDC_MSAC_W0_2_0_D0ACP_MASK)

#define XRDC_MSAC_W0_2_0_D1ACP_MASK              (0x38U)
#define XRDC_MSAC_W0_2_0_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_MSAC_W0_2_0_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_0_D1ACP_SHIFT)) & XRDC_MSAC_W0_2_0_D1ACP_MASK)

#define XRDC_MSAC_W0_2_0_D2ACP_MASK              (0x1C0U)
#define XRDC_MSAC_W0_2_0_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_MSAC_W0_2_0_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_0_D2ACP_SHIFT)) & XRDC_MSAC_W0_2_0_D2ACP_MASK)

#define XRDC_MSAC_W0_2_0_D3ACP_MASK              (0xE00U)
#define XRDC_MSAC_W0_2_0_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_MSAC_W0_2_0_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_0_D3ACP_SHIFT)) & XRDC_MSAC_W0_2_0_D3ACP_MASK)

#define XRDC_MSAC_W0_2_0_D4ACP_MASK              (0x7000U)
#define XRDC_MSAC_W0_2_0_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_MSAC_W0_2_0_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_0_D4ACP_SHIFT)) & XRDC_MSAC_W0_2_0_D4ACP_MASK)

#define XRDC_MSAC_W0_2_0_D5ACP_MASK              (0x38000U)
#define XRDC_MSAC_W0_2_0_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_MSAC_W0_2_0_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_0_D5ACP_SHIFT)) & XRDC_MSAC_W0_2_0_D5ACP_MASK)

#define XRDC_MSAC_W0_2_0_D6ACP_MASK              (0x1C0000U)
#define XRDC_MSAC_W0_2_0_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_MSAC_W0_2_0_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_0_D6ACP_SHIFT)) & XRDC_MSAC_W0_2_0_D6ACP_MASK)

#define XRDC_MSAC_W0_2_0_D7ACP_MASK              (0xE00000U)
#define XRDC_MSAC_W0_2_0_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_MSAC_W0_2_0_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_0_D7ACP_SHIFT)) & XRDC_MSAC_W0_2_0_D7ACP_MASK)

#define XRDC_MSAC_W0_2_0_EALO_MASK               (0xF000000U)
#define XRDC_MSAC_W0_2_0_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_MSAC_W0_2_0_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_0_EALO_SHIFT)) & XRDC_MSAC_W0_2_0_EALO_MASK)
/*! @} */

/*! @name MSAC_W1_2_0 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W1_2_0_EAL_MASK                (0x3000000U)
#define XRDC_MSAC_W1_2_0_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MSAC_W1_2_0_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_0_EAL_SHIFT)) & XRDC_MSAC_W1_2_0_EAL_MASK)

#define XRDC_MSAC_W1_2_0_LK2_MASK                (0x60000000U)
#define XRDC_MSAC_W1_2_0_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MSACs can be written.
 *  0b01..Entire MSACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MSACs fields can be written.
 *  0b11..MSACs is locked (read-only) until the next reset.
 */
#define XRDC_MSAC_W1_2_0_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_0_LK2_SHIFT)) & XRDC_MSAC_W1_2_0_LK2_MASK)

#define XRDC_MSAC_W1_2_0_VLD_MASK                (0x80000000U)
#define XRDC_MSAC_W1_2_0_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MSACs assignment is invalid.
 *  0b1..The MSACs assignment is valid.
 */
#define XRDC_MSAC_W1_2_0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_0_VLD_SHIFT)) & XRDC_MSAC_W1_2_0_VLD_MASK)
/*! @} */

/*! @name MSAC_W0_2_1 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W0_2_1_D0ACP_MASK              (0x7U)
#define XRDC_MSAC_W0_2_1_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_MSAC_W0_2_1_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_1_D0ACP_SHIFT)) & XRDC_MSAC_W0_2_1_D0ACP_MASK)

#define XRDC_MSAC_W0_2_1_D1ACP_MASK              (0x38U)
#define XRDC_MSAC_W0_2_1_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_MSAC_W0_2_1_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_1_D1ACP_SHIFT)) & XRDC_MSAC_W0_2_1_D1ACP_MASK)

#define XRDC_MSAC_W0_2_1_D2ACP_MASK              (0x1C0U)
#define XRDC_MSAC_W0_2_1_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_MSAC_W0_2_1_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_1_D2ACP_SHIFT)) & XRDC_MSAC_W0_2_1_D2ACP_MASK)

#define XRDC_MSAC_W0_2_1_D3ACP_MASK              (0xE00U)
#define XRDC_MSAC_W0_2_1_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_MSAC_W0_2_1_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_1_D3ACP_SHIFT)) & XRDC_MSAC_W0_2_1_D3ACP_MASK)

#define XRDC_MSAC_W0_2_1_D4ACP_MASK              (0x7000U)
#define XRDC_MSAC_W0_2_1_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_MSAC_W0_2_1_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_1_D4ACP_SHIFT)) & XRDC_MSAC_W0_2_1_D4ACP_MASK)

#define XRDC_MSAC_W0_2_1_D5ACP_MASK              (0x38000U)
#define XRDC_MSAC_W0_2_1_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_MSAC_W0_2_1_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_1_D5ACP_SHIFT)) & XRDC_MSAC_W0_2_1_D5ACP_MASK)

#define XRDC_MSAC_W0_2_1_D6ACP_MASK              (0x1C0000U)
#define XRDC_MSAC_W0_2_1_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_MSAC_W0_2_1_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_1_D6ACP_SHIFT)) & XRDC_MSAC_W0_2_1_D6ACP_MASK)

#define XRDC_MSAC_W0_2_1_D7ACP_MASK              (0xE00000U)
#define XRDC_MSAC_W0_2_1_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_MSAC_W0_2_1_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_1_D7ACP_SHIFT)) & XRDC_MSAC_W0_2_1_D7ACP_MASK)

#define XRDC_MSAC_W0_2_1_EALO_MASK               (0xF000000U)
#define XRDC_MSAC_W0_2_1_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_MSAC_W0_2_1_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_1_EALO_SHIFT)) & XRDC_MSAC_W0_2_1_EALO_MASK)
/*! @} */

/*! @name MSAC_W1_2_1 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W1_2_1_EAL_MASK                (0x3000000U)
#define XRDC_MSAC_W1_2_1_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MSAC_W1_2_1_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_1_EAL_SHIFT)) & XRDC_MSAC_W1_2_1_EAL_MASK)

#define XRDC_MSAC_W1_2_1_LK2_MASK                (0x60000000U)
#define XRDC_MSAC_W1_2_1_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MSACs can be written.
 *  0b01..Entire MSACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MSACs fields can be written.
 *  0b11..MSACs is locked (read-only) until the next reset.
 */
#define XRDC_MSAC_W1_2_1_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_1_LK2_SHIFT)) & XRDC_MSAC_W1_2_1_LK2_MASK)

#define XRDC_MSAC_W1_2_1_VLD_MASK                (0x80000000U)
#define XRDC_MSAC_W1_2_1_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MSACs assignment is invalid.
 *  0b1..The MSACs assignment is valid.
 */
#define XRDC_MSAC_W1_2_1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_1_VLD_SHIFT)) & XRDC_MSAC_W1_2_1_VLD_MASK)
/*! @} */

/*! @name MSAC_W0_2_2 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W0_2_2_D0ACP_MASK              (0x7U)
#define XRDC_MSAC_W0_2_2_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_MSAC_W0_2_2_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_2_D0ACP_SHIFT)) & XRDC_MSAC_W0_2_2_D0ACP_MASK)

#define XRDC_MSAC_W0_2_2_D1ACP_MASK              (0x38U)
#define XRDC_MSAC_W0_2_2_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_MSAC_W0_2_2_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_2_D1ACP_SHIFT)) & XRDC_MSAC_W0_2_2_D1ACP_MASK)

#define XRDC_MSAC_W0_2_2_D2ACP_MASK              (0x1C0U)
#define XRDC_MSAC_W0_2_2_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_MSAC_W0_2_2_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_2_D2ACP_SHIFT)) & XRDC_MSAC_W0_2_2_D2ACP_MASK)

#define XRDC_MSAC_W0_2_2_D3ACP_MASK              (0xE00U)
#define XRDC_MSAC_W0_2_2_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_MSAC_W0_2_2_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_2_D3ACP_SHIFT)) & XRDC_MSAC_W0_2_2_D3ACP_MASK)

#define XRDC_MSAC_W0_2_2_D4ACP_MASK              (0x7000U)
#define XRDC_MSAC_W0_2_2_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_MSAC_W0_2_2_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_2_D4ACP_SHIFT)) & XRDC_MSAC_W0_2_2_D4ACP_MASK)

#define XRDC_MSAC_W0_2_2_D5ACP_MASK              (0x38000U)
#define XRDC_MSAC_W0_2_2_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_MSAC_W0_2_2_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_2_D5ACP_SHIFT)) & XRDC_MSAC_W0_2_2_D5ACP_MASK)

#define XRDC_MSAC_W0_2_2_D6ACP_MASK              (0x1C0000U)
#define XRDC_MSAC_W0_2_2_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_MSAC_W0_2_2_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_2_D6ACP_SHIFT)) & XRDC_MSAC_W0_2_2_D6ACP_MASK)

#define XRDC_MSAC_W0_2_2_D7ACP_MASK              (0xE00000U)
#define XRDC_MSAC_W0_2_2_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_MSAC_W0_2_2_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_2_D7ACP_SHIFT)) & XRDC_MSAC_W0_2_2_D7ACP_MASK)

#define XRDC_MSAC_W0_2_2_EALO_MASK               (0xF000000U)
#define XRDC_MSAC_W0_2_2_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_MSAC_W0_2_2_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_2_EALO_SHIFT)) & XRDC_MSAC_W0_2_2_EALO_MASK)
/*! @} */

/*! @name MSAC_W1_2_2 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W1_2_2_EAL_MASK                (0x3000000U)
#define XRDC_MSAC_W1_2_2_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MSAC_W1_2_2_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_2_EAL_SHIFT)) & XRDC_MSAC_W1_2_2_EAL_MASK)

#define XRDC_MSAC_W1_2_2_LK2_MASK                (0x60000000U)
#define XRDC_MSAC_W1_2_2_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MSACs can be written.
 *  0b01..Entire MSACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MSACs fields can be written.
 *  0b11..MSACs is locked (read-only) until the next reset.
 */
#define XRDC_MSAC_W1_2_2_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_2_LK2_SHIFT)) & XRDC_MSAC_W1_2_2_LK2_MASK)

#define XRDC_MSAC_W1_2_2_VLD_MASK                (0x80000000U)
#define XRDC_MSAC_W1_2_2_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MSACs assignment is invalid.
 *  0b1..The MSACs assignment is valid.
 */
#define XRDC_MSAC_W1_2_2_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_2_VLD_SHIFT)) & XRDC_MSAC_W1_2_2_VLD_MASK)
/*! @} */

/*! @name MSAC_W0_2_3 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W0_2_3_D0ACP_MASK              (0x7U)
#define XRDC_MSAC_W0_2_3_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_MSAC_W0_2_3_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_3_D0ACP_SHIFT)) & XRDC_MSAC_W0_2_3_D0ACP_MASK)

#define XRDC_MSAC_W0_2_3_D1ACP_MASK              (0x38U)
#define XRDC_MSAC_W0_2_3_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_MSAC_W0_2_3_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_3_D1ACP_SHIFT)) & XRDC_MSAC_W0_2_3_D1ACP_MASK)

#define XRDC_MSAC_W0_2_3_D2ACP_MASK              (0x1C0U)
#define XRDC_MSAC_W0_2_3_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_MSAC_W0_2_3_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_3_D2ACP_SHIFT)) & XRDC_MSAC_W0_2_3_D2ACP_MASK)

#define XRDC_MSAC_W0_2_3_D3ACP_MASK              (0xE00U)
#define XRDC_MSAC_W0_2_3_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_MSAC_W0_2_3_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_3_D3ACP_SHIFT)) & XRDC_MSAC_W0_2_3_D3ACP_MASK)

#define XRDC_MSAC_W0_2_3_D4ACP_MASK              (0x7000U)
#define XRDC_MSAC_W0_2_3_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_MSAC_W0_2_3_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_3_D4ACP_SHIFT)) & XRDC_MSAC_W0_2_3_D4ACP_MASK)

#define XRDC_MSAC_W0_2_3_D5ACP_MASK              (0x38000U)
#define XRDC_MSAC_W0_2_3_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_MSAC_W0_2_3_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_3_D5ACP_SHIFT)) & XRDC_MSAC_W0_2_3_D5ACP_MASK)

#define XRDC_MSAC_W0_2_3_D6ACP_MASK              (0x1C0000U)
#define XRDC_MSAC_W0_2_3_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_MSAC_W0_2_3_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_3_D6ACP_SHIFT)) & XRDC_MSAC_W0_2_3_D6ACP_MASK)

#define XRDC_MSAC_W0_2_3_D7ACP_MASK              (0xE00000U)
#define XRDC_MSAC_W0_2_3_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_MSAC_W0_2_3_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_3_D7ACP_SHIFT)) & XRDC_MSAC_W0_2_3_D7ACP_MASK)

#define XRDC_MSAC_W0_2_3_EALO_MASK               (0xF000000U)
#define XRDC_MSAC_W0_2_3_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_MSAC_W0_2_3_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_3_EALO_SHIFT)) & XRDC_MSAC_W0_2_3_EALO_MASK)
/*! @} */

/*! @name MSAC_W1_2_3 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W1_2_3_EAL_MASK                (0x3000000U)
#define XRDC_MSAC_W1_2_3_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MSAC_W1_2_3_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_3_EAL_SHIFT)) & XRDC_MSAC_W1_2_3_EAL_MASK)

#define XRDC_MSAC_W1_2_3_LK2_MASK                (0x60000000U)
#define XRDC_MSAC_W1_2_3_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MSACs can be written.
 *  0b01..Entire MSACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MSACs fields can be written.
 *  0b11..MSACs is locked (read-only) until the next reset.
 */
#define XRDC_MSAC_W1_2_3_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_3_LK2_SHIFT)) & XRDC_MSAC_W1_2_3_LK2_MASK)

#define XRDC_MSAC_W1_2_3_VLD_MASK                (0x80000000U)
#define XRDC_MSAC_W1_2_3_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MSACs assignment is invalid.
 *  0b1..The MSACs assignment is valid.
 */
#define XRDC_MSAC_W1_2_3_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_3_VLD_SHIFT)) & XRDC_MSAC_W1_2_3_VLD_MASK)
/*! @} */

/*! @name MSAC_W0_2_4 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W0_2_4_D0ACP_MASK              (0x7U)
#define XRDC_MSAC_W0_2_4_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_MSAC_W0_2_4_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_4_D0ACP_SHIFT)) & XRDC_MSAC_W0_2_4_D0ACP_MASK)

#define XRDC_MSAC_W0_2_4_D1ACP_MASK              (0x38U)
#define XRDC_MSAC_W0_2_4_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_MSAC_W0_2_4_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_4_D1ACP_SHIFT)) & XRDC_MSAC_W0_2_4_D1ACP_MASK)

#define XRDC_MSAC_W0_2_4_D2ACP_MASK              (0x1C0U)
#define XRDC_MSAC_W0_2_4_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_MSAC_W0_2_4_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_4_D2ACP_SHIFT)) & XRDC_MSAC_W0_2_4_D2ACP_MASK)

#define XRDC_MSAC_W0_2_4_D3ACP_MASK              (0xE00U)
#define XRDC_MSAC_W0_2_4_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_MSAC_W0_2_4_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_4_D3ACP_SHIFT)) & XRDC_MSAC_W0_2_4_D3ACP_MASK)

#define XRDC_MSAC_W0_2_4_D4ACP_MASK              (0x7000U)
#define XRDC_MSAC_W0_2_4_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_MSAC_W0_2_4_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_4_D4ACP_SHIFT)) & XRDC_MSAC_W0_2_4_D4ACP_MASK)

#define XRDC_MSAC_W0_2_4_D5ACP_MASK              (0x38000U)
#define XRDC_MSAC_W0_2_4_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_MSAC_W0_2_4_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_4_D5ACP_SHIFT)) & XRDC_MSAC_W0_2_4_D5ACP_MASK)

#define XRDC_MSAC_W0_2_4_D6ACP_MASK              (0x1C0000U)
#define XRDC_MSAC_W0_2_4_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_MSAC_W0_2_4_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_4_D6ACP_SHIFT)) & XRDC_MSAC_W0_2_4_D6ACP_MASK)

#define XRDC_MSAC_W0_2_4_D7ACP_MASK              (0xE00000U)
#define XRDC_MSAC_W0_2_4_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_MSAC_W0_2_4_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_4_D7ACP_SHIFT)) & XRDC_MSAC_W0_2_4_D7ACP_MASK)

#define XRDC_MSAC_W0_2_4_EALO_MASK               (0xF000000U)
#define XRDC_MSAC_W0_2_4_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_MSAC_W0_2_4_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_4_EALO_SHIFT)) & XRDC_MSAC_W0_2_4_EALO_MASK)
/*! @} */

/*! @name MSAC_W1_2_4 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W1_2_4_EAL_MASK                (0x3000000U)
#define XRDC_MSAC_W1_2_4_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MSAC_W1_2_4_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_4_EAL_SHIFT)) & XRDC_MSAC_W1_2_4_EAL_MASK)

#define XRDC_MSAC_W1_2_4_LK2_MASK                (0x60000000U)
#define XRDC_MSAC_W1_2_4_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MSACs can be written.
 *  0b01..Entire MSACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MSACs fields can be written.
 *  0b11..MSACs is locked (read-only) until the next reset.
 */
#define XRDC_MSAC_W1_2_4_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_4_LK2_SHIFT)) & XRDC_MSAC_W1_2_4_LK2_MASK)

#define XRDC_MSAC_W1_2_4_VLD_MASK                (0x80000000U)
#define XRDC_MSAC_W1_2_4_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MSACs assignment is invalid.
 *  0b1..The MSACs assignment is valid.
 */
#define XRDC_MSAC_W1_2_4_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_4_VLD_SHIFT)) & XRDC_MSAC_W1_2_4_VLD_MASK)
/*! @} */

/*! @name MSAC_W0_2_5 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W0_2_5_D0ACP_MASK              (0x7U)
#define XRDC_MSAC_W0_2_5_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_MSAC_W0_2_5_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_5_D0ACP_SHIFT)) & XRDC_MSAC_W0_2_5_D0ACP_MASK)

#define XRDC_MSAC_W0_2_5_D1ACP_MASK              (0x38U)
#define XRDC_MSAC_W0_2_5_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_MSAC_W0_2_5_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_5_D1ACP_SHIFT)) & XRDC_MSAC_W0_2_5_D1ACP_MASK)

#define XRDC_MSAC_W0_2_5_D2ACP_MASK              (0x1C0U)
#define XRDC_MSAC_W0_2_5_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_MSAC_W0_2_5_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_5_D2ACP_SHIFT)) & XRDC_MSAC_W0_2_5_D2ACP_MASK)

#define XRDC_MSAC_W0_2_5_D3ACP_MASK              (0xE00U)
#define XRDC_MSAC_W0_2_5_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_MSAC_W0_2_5_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_5_D3ACP_SHIFT)) & XRDC_MSAC_W0_2_5_D3ACP_MASK)

#define XRDC_MSAC_W0_2_5_D4ACP_MASK              (0x7000U)
#define XRDC_MSAC_W0_2_5_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_MSAC_W0_2_5_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_5_D4ACP_SHIFT)) & XRDC_MSAC_W0_2_5_D4ACP_MASK)

#define XRDC_MSAC_W0_2_5_D5ACP_MASK              (0x38000U)
#define XRDC_MSAC_W0_2_5_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_MSAC_W0_2_5_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_5_D5ACP_SHIFT)) & XRDC_MSAC_W0_2_5_D5ACP_MASK)

#define XRDC_MSAC_W0_2_5_D6ACP_MASK              (0x1C0000U)
#define XRDC_MSAC_W0_2_5_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_MSAC_W0_2_5_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_5_D6ACP_SHIFT)) & XRDC_MSAC_W0_2_5_D6ACP_MASK)

#define XRDC_MSAC_W0_2_5_D7ACP_MASK              (0xE00000U)
#define XRDC_MSAC_W0_2_5_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_MSAC_W0_2_5_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_5_D7ACP_SHIFT)) & XRDC_MSAC_W0_2_5_D7ACP_MASK)

#define XRDC_MSAC_W0_2_5_EALO_MASK               (0xF000000U)
#define XRDC_MSAC_W0_2_5_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_MSAC_W0_2_5_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_5_EALO_SHIFT)) & XRDC_MSAC_W0_2_5_EALO_MASK)
/*! @} */

/*! @name MSAC_W1_2_5 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W1_2_5_EAL_MASK                (0x3000000U)
#define XRDC_MSAC_W1_2_5_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MSAC_W1_2_5_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_5_EAL_SHIFT)) & XRDC_MSAC_W1_2_5_EAL_MASK)

#define XRDC_MSAC_W1_2_5_LK2_MASK                (0x60000000U)
#define XRDC_MSAC_W1_2_5_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MSACs can be written.
 *  0b01..Entire MSACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MSACs fields can be written.
 *  0b11..MSACs is locked (read-only) until the next reset.
 */
#define XRDC_MSAC_W1_2_5_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_5_LK2_SHIFT)) & XRDC_MSAC_W1_2_5_LK2_MASK)

#define XRDC_MSAC_W1_2_5_VLD_MASK                (0x80000000U)
#define XRDC_MSAC_W1_2_5_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MSACs assignment is invalid.
 *  0b1..The MSACs assignment is valid.
 */
#define XRDC_MSAC_W1_2_5_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_5_VLD_SHIFT)) & XRDC_MSAC_W1_2_5_VLD_MASK)
/*! @} */

/*! @name MSAC_W0_2_6 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W0_2_6_D0ACP_MASK              (0x7U)
#define XRDC_MSAC_W0_2_6_D0ACP_SHIFT             (0U)
/*! D0ACP - Domain 0 access control policy */
#define XRDC_MSAC_W0_2_6_D0ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_6_D0ACP_SHIFT)) & XRDC_MSAC_W0_2_6_D0ACP_MASK)

#define XRDC_MSAC_W0_2_6_D1ACP_MASK              (0x38U)
#define XRDC_MSAC_W0_2_6_D1ACP_SHIFT             (3U)
/*! D1ACP - Domain 1 access control policy */
#define XRDC_MSAC_W0_2_6_D1ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_6_D1ACP_SHIFT)) & XRDC_MSAC_W0_2_6_D1ACP_MASK)

#define XRDC_MSAC_W0_2_6_D2ACP_MASK              (0x1C0U)
#define XRDC_MSAC_W0_2_6_D2ACP_SHIFT             (6U)
/*! D2ACP - Domain 2 access control policy */
#define XRDC_MSAC_W0_2_6_D2ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_6_D2ACP_SHIFT)) & XRDC_MSAC_W0_2_6_D2ACP_MASK)

#define XRDC_MSAC_W0_2_6_D3ACP_MASK              (0xE00U)
#define XRDC_MSAC_W0_2_6_D3ACP_SHIFT             (9U)
/*! D3ACP - Domain 3 access control policy */
#define XRDC_MSAC_W0_2_6_D3ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_6_D3ACP_SHIFT)) & XRDC_MSAC_W0_2_6_D3ACP_MASK)

#define XRDC_MSAC_W0_2_6_D4ACP_MASK              (0x7000U)
#define XRDC_MSAC_W0_2_6_D4ACP_SHIFT             (12U)
/*! D4ACP - Domain 4 access control policy */
#define XRDC_MSAC_W0_2_6_D4ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_6_D4ACP_SHIFT)) & XRDC_MSAC_W0_2_6_D4ACP_MASK)

#define XRDC_MSAC_W0_2_6_D5ACP_MASK              (0x38000U)
#define XRDC_MSAC_W0_2_6_D5ACP_SHIFT             (15U)
/*! D5ACP - Domain 5 access control policy */
#define XRDC_MSAC_W0_2_6_D5ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_6_D5ACP_SHIFT)) & XRDC_MSAC_W0_2_6_D5ACP_MASK)

#define XRDC_MSAC_W0_2_6_D6ACP_MASK              (0x1C0000U)
#define XRDC_MSAC_W0_2_6_D6ACP_SHIFT             (18U)
/*! D6ACP - Domain 6 access control policy */
#define XRDC_MSAC_W0_2_6_D6ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_6_D6ACP_SHIFT)) & XRDC_MSAC_W0_2_6_D6ACP_MASK)

#define XRDC_MSAC_W0_2_6_D7ACP_MASK              (0xE00000U)
#define XRDC_MSAC_W0_2_6_D7ACP_SHIFT             (21U)
/*! D7ACP - Domain 7 access control policy */
#define XRDC_MSAC_W0_2_6_D7ACP(x)                (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_6_D7ACP_SHIFT)) & XRDC_MSAC_W0_2_6_D7ACP_MASK)

#define XRDC_MSAC_W0_2_6_EALO_MASK               (0xF000000U)
#define XRDC_MSAC_W0_2_6_EALO_SHIFT              (24U)
/*! EALO - Excessive Access Lock Owner */
#define XRDC_MSAC_W0_2_6_EALO(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W0_2_6_EALO_SHIFT)) & XRDC_MSAC_W0_2_6_EALO_MASK)
/*! @} */

/*! @name MSAC_W1_2_6 - Memory Slot Access Control */
/*! @{ */

#define XRDC_MSAC_W1_2_6_EAL_MASK                (0x3000000U)
#define XRDC_MSAC_W1_2_6_EAL_SHIFT               (24U)
/*! EAL - Exclusive Access Lock
 *  0b00..Lock disabled
 *  0b01..Lock disabled until next reset
 *  0b10..Lock enabled, lock state = available
 *  0b11..Lock enabled, lock state = not available
 */
#define XRDC_MSAC_W1_2_6_EAL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_6_EAL_SHIFT)) & XRDC_MSAC_W1_2_6_EAL_MASK)

#define XRDC_MSAC_W1_2_6_LK2_MASK                (0x60000000U)
#define XRDC_MSAC_W1_2_6_LK2_SHIFT               (29U)
/*! LK2 - Lock
 *  0b00..Entire MSACs can be written.
 *  0b01..Entire MSACs can be written.
 *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MSACs fields can be written.
 *  0b11..MSACs is locked (read-only) until the next reset.
 */
#define XRDC_MSAC_W1_2_6_LK2(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_6_LK2_SHIFT)) & XRDC_MSAC_W1_2_6_LK2_MASK)

#define XRDC_MSAC_W1_2_6_VLD_MASK                (0x80000000U)
#define XRDC_MSAC_W1_2_6_VLD_SHIFT               (31U)
/*! VLD - Valid
 *  0b0..The MSACs assignment is invalid.
 *  0b1..The MSACs assignment is valid.
 */
#define XRDC_MSAC_W1_2_6_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_MSAC_W1_2_6_VLD_SHIFT)) & XRDC_MSAC_W1_2_6_VLD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group XRDC_Register_Masks */


/* XRDC - Peripheral instance base addresses */
/** Peripheral XRDC base address */
#define XRDC_BASE                                (0x292F0000u)
/** Peripheral XRDC base pointer */
#define XRDC                                     ((XRDC_Type *)XRDC_BASE)
/** Array initializer of XRDC peripheral base addresses */
#define XRDC_BASE_ADDRS                          { XRDC_BASE }
/** Array initializer of XRDC peripheral base pointers */
#define XRDC_BASE_PTRS                           { XRDC }

/*!
 * @}
 */ /* end of group XRDC_Peripheral_Access_Layer */


/*
** End of section using anonymous unions
*/

#if defined(__XTENSA__)
  /* leave anonymous unions enabled */
#else
  #error Not supported compiler type
#endif

/*!
 * @}
 */ /* end of group Peripheral_access_layer */


/* ----------------------------------------------------------------------------
   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
 * @{
 */

/**
 * @brief Mask and left-shift a bit field value for use in a register bit range.
 * @param field Name of the register bit field.
 * @param value Value of the bit field.
 * @return Masked and shifted value.
 */
#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
/**
 * @brief Mask and right-shift a register value to extract a bit field value.
 * @param field Name of the register bit field.
 * @param value Value of the register.
 * @return Masked and shifted bit field value.
 */
#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))

/*!
 * @}
 */ /* end of group Bit_Field_Generic_Macros */


/* ----------------------------------------------------------------------------
   -- SDK Compatibility
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
 * @{
 */

/* No SDK compatibility issues. */

/*!
 * @}
 */ /* end of group SDK_Compatibility_Symbols */


#endif  /* MIMX8UD7_DSP1_H_ */